1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_drv.h" 26 #include "i915_vgpu.h" 27 28 #include <linux/pm_runtime.h> 29 30 #define FORCEWAKE_ACK_TIMEOUT_MS 2 31 32 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) 33 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) 34 35 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) 36 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) 37 38 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) 39 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) 40 41 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) 42 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) 43 44 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) 45 46 static const char * const forcewake_domain_names[] = { 47 "render", 48 "blitter", 49 "media", 50 }; 51 52 const char * 53 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 54 { 55 BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) != 56 FW_DOMAIN_ID_COUNT); 57 58 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 59 return forcewake_domain_names[id]; 60 61 WARN_ON(id); 62 63 return "unknown"; 64 } 65 66 static void 67 assert_device_not_suspended(struct drm_i915_private *dev_priv) 68 { 69 WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, 70 "Device suspended\n"); 71 } 72 73 static inline void 74 fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 75 { 76 WARN_ON(d->reg_set == 0); 77 __raw_i915_write32(d->i915, d->reg_set, d->val_reset); 78 } 79 80 static inline void 81 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 82 { 83 mod_timer_pinned(&d->timer, jiffies + 1); 84 } 85 86 static inline void 87 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 88 { 89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & 90 FORCEWAKE_KERNEL) == 0, 91 FORCEWAKE_ACK_TIMEOUT_MS)) 92 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 93 intel_uncore_forcewake_domain_to_str(d->id)); 94 } 95 96 static inline void 97 fw_domain_get(const struct intel_uncore_forcewake_domain *d) 98 { 99 __raw_i915_write32(d->i915, d->reg_set, d->val_set); 100 } 101 102 static inline void 103 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) 104 { 105 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & 106 FORCEWAKE_KERNEL), 107 FORCEWAKE_ACK_TIMEOUT_MS)) 108 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 109 intel_uncore_forcewake_domain_to_str(d->id)); 110 } 111 112 static inline void 113 fw_domain_put(const struct intel_uncore_forcewake_domain *d) 114 { 115 __raw_i915_write32(d->i915, d->reg_set, d->val_clear); 116 } 117 118 static inline void 119 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) 120 { 121 /* something from same cacheline, but not from the set register */ 122 if (d->reg_post) 123 __raw_posting_read(d->i915, d->reg_post); 124 } 125 126 static void 127 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) 128 { 129 struct intel_uncore_forcewake_domain *d; 130 enum forcewake_domain_id id; 131 132 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { 133 fw_domain_wait_ack_clear(d); 134 fw_domain_get(d); 135 fw_domain_wait_ack(d); 136 } 137 } 138 139 static void 140 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) 141 { 142 struct intel_uncore_forcewake_domain *d; 143 enum forcewake_domain_id id; 144 145 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { 146 fw_domain_put(d); 147 fw_domain_posting_read(d); 148 } 149 } 150 151 static void 152 fw_domains_posting_read(struct drm_i915_private *dev_priv) 153 { 154 struct intel_uncore_forcewake_domain *d; 155 enum forcewake_domain_id id; 156 157 /* No need to do for all, just do for first found */ 158 for_each_fw_domain(d, dev_priv, id) { 159 fw_domain_posting_read(d); 160 break; 161 } 162 } 163 164 static void 165 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) 166 { 167 struct intel_uncore_forcewake_domain *d; 168 enum forcewake_domain_id id; 169 170 if (dev_priv->uncore.fw_domains == 0) 171 return; 172 173 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) 174 fw_domain_reset(d); 175 176 fw_domains_posting_read(dev_priv); 177 } 178 179 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 180 { 181 /* w/a for a sporadic read returning 0 by waiting for the GT 182 * thread to wake up. 183 */ 184 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & 185 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) 186 DRM_ERROR("GT thread status wait timed out\n"); 187 } 188 189 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, 190 enum forcewake_domains fw_domains) 191 { 192 fw_domains_get(dev_priv, fw_domains); 193 194 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 195 __gen6_gt_wait_for_thread_c0(dev_priv); 196 } 197 198 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 199 { 200 u32 gtfifodbg; 201 202 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); 203 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) 204 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); 205 } 206 207 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, 208 enum forcewake_domains fw_domains) 209 { 210 fw_domains_put(dev_priv, fw_domains); 211 gen6_gt_check_fifodbg(dev_priv); 212 } 213 214 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) 215 { 216 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); 217 218 return count & GT_FIFO_FREE_ENTRIES_MASK; 219 } 220 221 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 222 { 223 int ret = 0; 224 225 /* On VLV, FIFO will be shared by both SW and HW. 226 * So, we need to read the FREE_ENTRIES everytime */ 227 if (IS_VALLEYVIEW(dev_priv->dev)) 228 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); 229 230 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 231 int loop = 500; 232 u32 fifo = fifo_free_entries(dev_priv); 233 234 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 235 udelay(10); 236 fifo = fifo_free_entries(dev_priv); 237 } 238 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 239 ++ret; 240 dev_priv->uncore.fifo_count = fifo; 241 } 242 dev_priv->uncore.fifo_count--; 243 244 return ret; 245 } 246 247 static void intel_uncore_fw_release_timer(unsigned long arg) 248 { 249 struct intel_uncore_forcewake_domain *domain = (void *)arg; 250 unsigned long irqflags; 251 252 assert_device_not_suspended(domain->i915); 253 254 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); 255 if (WARN_ON(domain->wake_count == 0)) 256 domain->wake_count++; 257 258 if (--domain->wake_count == 0) 259 domain->i915->uncore.funcs.force_wake_put(domain->i915, 260 1 << domain->id); 261 262 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); 263 } 264 265 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) 266 { 267 struct drm_i915_private *dev_priv = dev->dev_private; 268 unsigned long irqflags; 269 struct intel_uncore_forcewake_domain *domain; 270 int retry_count = 100; 271 enum forcewake_domain_id id; 272 enum forcewake_domains fw = 0, active_domains; 273 274 /* Hold uncore.lock across reset to prevent any register access 275 * with forcewake not set correctly. Wait until all pending 276 * timers are run before holding. 277 */ 278 while (1) { 279 active_domains = 0; 280 281 for_each_fw_domain(domain, dev_priv, id) { 282 if (del_timer_sync(&domain->timer) == 0) 283 continue; 284 285 intel_uncore_fw_release_timer((unsigned long)domain); 286 } 287 288 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 289 290 for_each_fw_domain(domain, dev_priv, id) { 291 if (timer_pending(&domain->timer)) 292 active_domains |= (1 << id); 293 } 294 295 if (active_domains == 0) 296 break; 297 298 if (--retry_count == 0) { 299 DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); 300 break; 301 } 302 303 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 304 cond_resched(); 305 } 306 307 WARN_ON(active_domains); 308 309 for_each_fw_domain(domain, dev_priv, id) 310 if (domain->wake_count) 311 fw |= 1 << id; 312 313 if (fw) 314 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); 315 316 fw_domains_reset(dev_priv, FORCEWAKE_ALL); 317 318 if (restore) { /* If reset with a user forcewake, try to restore */ 319 if (fw) 320 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); 321 322 if (IS_GEN6(dev) || IS_GEN7(dev)) 323 dev_priv->uncore.fifo_count = 324 fifo_free_entries(dev_priv); 325 } 326 327 if (!restore) 328 assert_forcewakes_inactive(dev_priv); 329 330 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 331 } 332 333 static void intel_uncore_ellc_detect(struct drm_device *dev) 334 { 335 struct drm_i915_private *dev_priv = dev->dev_private; 336 337 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || 338 INTEL_INFO(dev)->gen >= 9) && 339 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { 340 /* The docs do not explain exactly how the calculation can be 341 * made. It is somewhat guessable, but for now, it's always 342 * 128MB. 343 * NB: We can't write IDICR yet because we do not have gt funcs 344 * set up */ 345 dev_priv->ellc_size = 128; 346 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); 347 } 348 } 349 350 static void __intel_uncore_early_sanitize(struct drm_device *dev, 351 bool restore_forcewake) 352 { 353 struct drm_i915_private *dev_priv = dev->dev_private; 354 355 if (HAS_FPGA_DBG_UNCLAIMED(dev)) 356 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 357 358 /* clear out old GT FIFO errors */ 359 if (IS_GEN6(dev) || IS_GEN7(dev)) 360 __raw_i915_write32(dev_priv, GTFIFODBG, 361 __raw_i915_read32(dev_priv, GTFIFODBG)); 362 363 /* WaDisableShadowRegForCpd:chv */ 364 if (IS_CHERRYVIEW(dev)) { 365 __raw_i915_write32(dev_priv, GTFIFOCTL, 366 __raw_i915_read32(dev_priv, GTFIFOCTL) | 367 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 368 GT_FIFO_CTL_RC6_POLICY_STALL); 369 } 370 371 intel_uncore_forcewake_reset(dev, restore_forcewake); 372 } 373 374 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) 375 { 376 __intel_uncore_early_sanitize(dev, restore_forcewake); 377 i915_check_and_clear_faults(dev); 378 } 379 380 void intel_uncore_sanitize(struct drm_device *dev) 381 { 382 /* BIOS often leaves RC6 enabled, but disable it for hw init */ 383 intel_disable_gt_powersave(dev); 384 } 385 386 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 387 enum forcewake_domains fw_domains) 388 { 389 struct intel_uncore_forcewake_domain *domain; 390 enum forcewake_domain_id id; 391 392 if (!dev_priv->uncore.funcs.force_wake_get) 393 return; 394 395 fw_domains &= dev_priv->uncore.fw_domains; 396 397 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { 398 if (domain->wake_count++) 399 fw_domains &= ~(1 << id); 400 } 401 402 if (fw_domains) 403 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); 404 } 405 406 /** 407 * intel_uncore_forcewake_get - grab forcewake domain references 408 * @dev_priv: i915 device instance 409 * @fw_domains: forcewake domains to get reference on 410 * 411 * This function can be used get GT's forcewake domain references. 412 * Normal register access will handle the forcewake domains automatically. 413 * However if some sequence requires the GT to not power down a particular 414 * forcewake domains this function should be called at the beginning of the 415 * sequence. And subsequently the reference should be dropped by symmetric 416 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 417 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 418 */ 419 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 420 enum forcewake_domains fw_domains) 421 { 422 unsigned long irqflags; 423 424 if (!dev_priv->uncore.funcs.force_wake_get) 425 return; 426 427 WARN_ON(dev_priv->pm.suspended); 428 429 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 430 __intel_uncore_forcewake_get(dev_priv, fw_domains); 431 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 432 } 433 434 /** 435 * intel_uncore_forcewake_get__locked - grab forcewake domain references 436 * @dev_priv: i915 device instance 437 * @fw_domains: forcewake domains to get reference on 438 * 439 * See intel_uncore_forcewake_get(). This variant places the onus 440 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 441 */ 442 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, 443 enum forcewake_domains fw_domains) 444 { 445 assert_spin_locked(&dev_priv->uncore.lock); 446 447 if (!dev_priv->uncore.funcs.force_wake_get) 448 return; 449 450 __intel_uncore_forcewake_get(dev_priv, fw_domains); 451 } 452 453 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 454 enum forcewake_domains fw_domains) 455 { 456 struct intel_uncore_forcewake_domain *domain; 457 enum forcewake_domain_id id; 458 459 if (!dev_priv->uncore.funcs.force_wake_put) 460 return; 461 462 fw_domains &= dev_priv->uncore.fw_domains; 463 464 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { 465 if (WARN_ON(domain->wake_count == 0)) 466 continue; 467 468 if (--domain->wake_count) 469 continue; 470 471 domain->wake_count++; 472 fw_domain_arm_timer(domain); 473 } 474 } 475 476 /** 477 * intel_uncore_forcewake_put - release a forcewake domain reference 478 * @dev_priv: i915 device instance 479 * @fw_domains: forcewake domains to put references 480 * 481 * This function drops the device-level forcewakes for specified 482 * domains obtained by intel_uncore_forcewake_get(). 483 */ 484 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 485 enum forcewake_domains fw_domains) 486 { 487 unsigned long irqflags; 488 489 if (!dev_priv->uncore.funcs.force_wake_put) 490 return; 491 492 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 493 __intel_uncore_forcewake_put(dev_priv, fw_domains); 494 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 495 } 496 497 /** 498 * intel_uncore_forcewake_put__locked - grab forcewake domain references 499 * @dev_priv: i915 device instance 500 * @fw_domains: forcewake domains to get reference on 501 * 502 * See intel_uncore_forcewake_put(). This variant places the onus 503 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 504 */ 505 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, 506 enum forcewake_domains fw_domains) 507 { 508 assert_spin_locked(&dev_priv->uncore.lock); 509 510 if (!dev_priv->uncore.funcs.force_wake_put) 511 return; 512 513 __intel_uncore_forcewake_put(dev_priv, fw_domains); 514 } 515 516 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) 517 { 518 struct intel_uncore_forcewake_domain *domain; 519 enum forcewake_domain_id id; 520 521 if (!dev_priv->uncore.funcs.force_wake_get) 522 return; 523 524 for_each_fw_domain(domain, dev_priv, id) 525 WARN_ON(domain->wake_count); 526 } 527 528 /* We give fast paths for the really cool registers */ 529 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 530 ((reg) < 0x40000 && (reg) != FORCEWAKE) 531 532 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) 533 534 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ 535 (REG_RANGE((reg), 0x2000, 0x4000) || \ 536 REG_RANGE((reg), 0x5000, 0x8000) || \ 537 REG_RANGE((reg), 0xB000, 0x12000) || \ 538 REG_RANGE((reg), 0x2E000, 0x30000)) 539 540 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ 541 (REG_RANGE((reg), 0x12000, 0x14000) || \ 542 REG_RANGE((reg), 0x22000, 0x24000) || \ 543 REG_RANGE((reg), 0x30000, 0x40000)) 544 545 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ 546 (REG_RANGE((reg), 0x2000, 0x4000) || \ 547 REG_RANGE((reg), 0x5200, 0x8000) || \ 548 REG_RANGE((reg), 0x8300, 0x8500) || \ 549 REG_RANGE((reg), 0xB000, 0xB480) || \ 550 REG_RANGE((reg), 0xE000, 0xE800)) 551 552 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ 553 (REG_RANGE((reg), 0x8800, 0x8900) || \ 554 REG_RANGE((reg), 0xD000, 0xD800) || \ 555 REG_RANGE((reg), 0x12000, 0x14000) || \ 556 REG_RANGE((reg), 0x1A000, 0x1C000) || \ 557 REG_RANGE((reg), 0x1E800, 0x1EA00) || \ 558 REG_RANGE((reg), 0x30000, 0x38000)) 559 560 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ 561 (REG_RANGE((reg), 0x4000, 0x5000) || \ 562 REG_RANGE((reg), 0x8000, 0x8300) || \ 563 REG_RANGE((reg), 0x8500, 0x8600) || \ 564 REG_RANGE((reg), 0x9000, 0xB000) || \ 565 REG_RANGE((reg), 0xF000, 0x10000)) 566 567 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ 568 REG_RANGE((reg), 0xB00, 0x2000) 569 570 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ 571 (REG_RANGE((reg), 0x2000, 0x2700) || \ 572 REG_RANGE((reg), 0x3000, 0x4000) || \ 573 REG_RANGE((reg), 0x5200, 0x8000) || \ 574 REG_RANGE((reg), 0x8140, 0x8160) || \ 575 REG_RANGE((reg), 0x8300, 0x8500) || \ 576 REG_RANGE((reg), 0x8C00, 0x8D00) || \ 577 REG_RANGE((reg), 0xB000, 0xB480) || \ 578 REG_RANGE((reg), 0xE000, 0xE900) || \ 579 REG_RANGE((reg), 0x24400, 0x24800)) 580 581 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ 582 (REG_RANGE((reg), 0x8130, 0x8140) || \ 583 REG_RANGE((reg), 0x8800, 0x8A00) || \ 584 REG_RANGE((reg), 0xD000, 0xD800) || \ 585 REG_RANGE((reg), 0x12000, 0x14000) || \ 586 REG_RANGE((reg), 0x1A000, 0x1EA00) || \ 587 REG_RANGE((reg), 0x30000, 0x40000)) 588 589 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ 590 REG_RANGE((reg), 0x9400, 0x9800) 591 592 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ 593 ((reg) < 0x40000 &&\ 594 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ 595 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ 596 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ 597 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) 598 599 static void 600 ilk_dummy_write(struct drm_i915_private *dev_priv) 601 { 602 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 603 * the chip from rc6 before touching it for real. MI_MODE is masked, 604 * hence harmless to write 0 into. */ 605 __raw_i915_write32(dev_priv, MI_MODE, 0); 606 } 607 608 static void 609 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, 610 bool before) 611 { 612 const char *op = read ? "reading" : "writing to"; 613 const char *when = before ? "before" : "after"; 614 615 if (!i915.mmio_debug) 616 return; 617 618 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { 619 WARN(1, "Unclaimed register detected %s %s register 0x%x\n", 620 when, op, reg); 621 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 622 i915.mmio_debug--; /* Only report the first N failures */ 623 } 624 } 625 626 static void 627 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) 628 { 629 static bool mmio_debug_once = true; 630 631 if (i915.mmio_debug || !mmio_debug_once) 632 return; 633 634 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { 635 DRM_DEBUG("Unclaimed register detected, " 636 "enabling oneshot unclaimed register reporting. " 637 "Please use i915.mmio_debug=N for more information.\n"); 638 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 639 i915.mmio_debug = mmio_debug_once--; 640 } 641 } 642 643 #define GEN2_READ_HEADER(x) \ 644 u##x val = 0; \ 645 assert_device_not_suspended(dev_priv); 646 647 #define GEN2_READ_FOOTER \ 648 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 649 return val 650 651 #define __gen2_read(x) \ 652 static u##x \ 653 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 654 GEN2_READ_HEADER(x); \ 655 val = __raw_i915_read##x(dev_priv, reg); \ 656 GEN2_READ_FOOTER; \ 657 } 658 659 #define __gen5_read(x) \ 660 static u##x \ 661 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 662 GEN2_READ_HEADER(x); \ 663 ilk_dummy_write(dev_priv); \ 664 val = __raw_i915_read##x(dev_priv, reg); \ 665 GEN2_READ_FOOTER; \ 666 } 667 668 __gen5_read(8) 669 __gen5_read(16) 670 __gen5_read(32) 671 __gen5_read(64) 672 __gen2_read(8) 673 __gen2_read(16) 674 __gen2_read(32) 675 __gen2_read(64) 676 677 #undef __gen5_read 678 #undef __gen2_read 679 680 #undef GEN2_READ_FOOTER 681 #undef GEN2_READ_HEADER 682 683 #define GEN6_READ_HEADER(x) \ 684 unsigned long irqflags; \ 685 u##x val = 0; \ 686 assert_device_not_suspended(dev_priv); \ 687 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) 688 689 #define GEN6_READ_FOOTER \ 690 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ 691 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 692 return val 693 694 static inline void __force_wake_get(struct drm_i915_private *dev_priv, 695 enum forcewake_domains fw_domains) 696 { 697 struct intel_uncore_forcewake_domain *domain; 698 enum forcewake_domain_id id; 699 700 if (WARN_ON(!fw_domains)) 701 return; 702 703 /* Ideally GCC would be constant-fold and eliminate this loop */ 704 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { 705 if (domain->wake_count) { 706 fw_domains &= ~(1 << id); 707 continue; 708 } 709 710 domain->wake_count++; 711 fw_domain_arm_timer(domain); 712 } 713 714 if (fw_domains) 715 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); 716 } 717 718 #define __vgpu_read(x) \ 719 static u##x \ 720 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 721 GEN6_READ_HEADER(x); \ 722 val = __raw_i915_read##x(dev_priv, reg); \ 723 GEN6_READ_FOOTER; \ 724 } 725 726 #define __gen6_read(x) \ 727 static u##x \ 728 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 729 GEN6_READ_HEADER(x); \ 730 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ 731 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \ 732 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ 733 val = __raw_i915_read##x(dev_priv, reg); \ 734 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ 735 GEN6_READ_FOOTER; \ 736 } 737 738 #define __vlv_read(x) \ 739 static u##x \ 740 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 741 GEN6_READ_HEADER(x); \ 742 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \ 743 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ 744 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \ 745 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \ 746 val = __raw_i915_read##x(dev_priv, reg); \ 747 GEN6_READ_FOOTER; \ 748 } 749 750 #define __chv_read(x) \ 751 static u##x \ 752 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 753 GEN6_READ_HEADER(x); \ 754 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \ 755 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ 756 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \ 757 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \ 758 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \ 759 __force_wake_get(dev_priv, \ 760 FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \ 761 val = __raw_i915_read##x(dev_priv, reg); \ 762 GEN6_READ_FOOTER; \ 763 } 764 765 #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \ 766 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) 767 768 #define __gen9_read(x) \ 769 static u##x \ 770 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 771 enum forcewake_domains fw_engine; \ 772 GEN6_READ_HEADER(x); \ 773 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) \ 774 fw_engine = 0; \ 775 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \ 776 fw_engine = FORCEWAKE_RENDER; \ 777 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \ 778 fw_engine = FORCEWAKE_MEDIA; \ 779 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \ 780 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ 781 else \ 782 fw_engine = FORCEWAKE_BLITTER; \ 783 if (fw_engine) \ 784 __force_wake_get(dev_priv, fw_engine); \ 785 val = __raw_i915_read##x(dev_priv, reg); \ 786 GEN6_READ_FOOTER; \ 787 } 788 789 __vgpu_read(8) 790 __vgpu_read(16) 791 __vgpu_read(32) 792 __vgpu_read(64) 793 __gen9_read(8) 794 __gen9_read(16) 795 __gen9_read(32) 796 __gen9_read(64) 797 __chv_read(8) 798 __chv_read(16) 799 __chv_read(32) 800 __chv_read(64) 801 __vlv_read(8) 802 __vlv_read(16) 803 __vlv_read(32) 804 __vlv_read(64) 805 __gen6_read(8) 806 __gen6_read(16) 807 __gen6_read(32) 808 __gen6_read(64) 809 810 #undef __gen9_read 811 #undef __chv_read 812 #undef __vlv_read 813 #undef __gen6_read 814 #undef __vgpu_read 815 #undef GEN6_READ_FOOTER 816 #undef GEN6_READ_HEADER 817 818 #define GEN2_WRITE_HEADER \ 819 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 820 assert_device_not_suspended(dev_priv); \ 821 822 #define GEN2_WRITE_FOOTER 823 824 #define __gen2_write(x) \ 825 static void \ 826 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 827 GEN2_WRITE_HEADER; \ 828 __raw_i915_write##x(dev_priv, reg, val); \ 829 GEN2_WRITE_FOOTER; \ 830 } 831 832 #define __gen5_write(x) \ 833 static void \ 834 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 835 GEN2_WRITE_HEADER; \ 836 ilk_dummy_write(dev_priv); \ 837 __raw_i915_write##x(dev_priv, reg, val); \ 838 GEN2_WRITE_FOOTER; \ 839 } 840 841 __gen5_write(8) 842 __gen5_write(16) 843 __gen5_write(32) 844 __gen5_write(64) 845 __gen2_write(8) 846 __gen2_write(16) 847 __gen2_write(32) 848 __gen2_write(64) 849 850 #undef __gen5_write 851 #undef __gen2_write 852 853 #undef GEN2_WRITE_FOOTER 854 #undef GEN2_WRITE_HEADER 855 856 #define GEN6_WRITE_HEADER \ 857 unsigned long irqflags; \ 858 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 859 assert_device_not_suspended(dev_priv); \ 860 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) 861 862 #define GEN6_WRITE_FOOTER \ 863 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) 864 865 #define __gen6_write(x) \ 866 static void \ 867 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 868 u32 __fifo_ret = 0; \ 869 GEN6_WRITE_HEADER; \ 870 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 871 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 872 } \ 873 __raw_i915_write##x(dev_priv, reg, val); \ 874 if (unlikely(__fifo_ret)) { \ 875 gen6_gt_check_fifodbg(dev_priv); \ 876 } \ 877 GEN6_WRITE_FOOTER; \ 878 } 879 880 #define __hsw_write(x) \ 881 static void \ 882 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 883 u32 __fifo_ret = 0; \ 884 GEN6_WRITE_HEADER; \ 885 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 886 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 887 } \ 888 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ 889 __raw_i915_write##x(dev_priv, reg, val); \ 890 if (unlikely(__fifo_ret)) { \ 891 gen6_gt_check_fifodbg(dev_priv); \ 892 } \ 893 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ 894 hsw_unclaimed_reg_detect(dev_priv); \ 895 GEN6_WRITE_FOOTER; \ 896 } 897 898 #define __vgpu_write(x) \ 899 static void vgpu_write##x(struct drm_i915_private *dev_priv, \ 900 off_t reg, u##x val, bool trace) { \ 901 GEN6_WRITE_HEADER; \ 902 __raw_i915_write##x(dev_priv, reg, val); \ 903 GEN6_WRITE_FOOTER; \ 904 } 905 906 static const u32 gen8_shadowed_regs[] = { 907 FORCEWAKE_MT, 908 GEN6_RPNSWREQ, 909 GEN6_RC_VIDEO_FREQ, 910 RING_TAIL(RENDER_RING_BASE), 911 RING_TAIL(GEN6_BSD_RING_BASE), 912 RING_TAIL(VEBOX_RING_BASE), 913 RING_TAIL(BLT_RING_BASE), 914 /* TODO: Other registers are not yet used */ 915 }; 916 917 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) 918 { 919 int i; 920 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) 921 if (reg == gen8_shadowed_regs[i]) 922 return true; 923 924 return false; 925 } 926 927 #define __gen8_write(x) \ 928 static void \ 929 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 930 GEN6_WRITE_HEADER; \ 931 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ 932 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \ 933 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ 934 __raw_i915_write##x(dev_priv, reg, val); \ 935 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ 936 hsw_unclaimed_reg_detect(dev_priv); \ 937 GEN6_WRITE_FOOTER; \ 938 } 939 940 #define __chv_write(x) \ 941 static void \ 942 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 943 bool shadowed = is_gen8_shadowed(dev_priv, reg); \ 944 GEN6_WRITE_HEADER; \ 945 if (!shadowed) { \ 946 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \ 947 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ 948 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \ 949 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \ 950 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \ 951 __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \ 952 } \ 953 __raw_i915_write##x(dev_priv, reg, val); \ 954 GEN6_WRITE_FOOTER; \ 955 } 956 957 static const u32 gen9_shadowed_regs[] = { 958 RING_TAIL(RENDER_RING_BASE), 959 RING_TAIL(GEN6_BSD_RING_BASE), 960 RING_TAIL(VEBOX_RING_BASE), 961 RING_TAIL(BLT_RING_BASE), 962 FORCEWAKE_BLITTER_GEN9, 963 FORCEWAKE_RENDER_GEN9, 964 FORCEWAKE_MEDIA_GEN9, 965 GEN6_RPNSWREQ, 966 GEN6_RC_VIDEO_FREQ, 967 /* TODO: Other registers are not yet used */ 968 }; 969 970 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) 971 { 972 int i; 973 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) 974 if (reg == gen9_shadowed_regs[i]) 975 return true; 976 977 return false; 978 } 979 980 #define __gen9_write(x) \ 981 static void \ 982 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ 983 bool trace) { \ 984 enum forcewake_domains fw_engine; \ 985 GEN6_WRITE_HEADER; \ 986 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ 987 is_gen9_shadowed(dev_priv, reg)) \ 988 fw_engine = 0; \ 989 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \ 990 fw_engine = FORCEWAKE_RENDER; \ 991 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \ 992 fw_engine = FORCEWAKE_MEDIA; \ 993 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \ 994 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ 995 else \ 996 fw_engine = FORCEWAKE_BLITTER; \ 997 if (fw_engine) \ 998 __force_wake_get(dev_priv, fw_engine); \ 999 __raw_i915_write##x(dev_priv, reg, val); \ 1000 GEN6_WRITE_FOOTER; \ 1001 } 1002 1003 __gen9_write(8) 1004 __gen9_write(16) 1005 __gen9_write(32) 1006 __gen9_write(64) 1007 __chv_write(8) 1008 __chv_write(16) 1009 __chv_write(32) 1010 __chv_write(64) 1011 __gen8_write(8) 1012 __gen8_write(16) 1013 __gen8_write(32) 1014 __gen8_write(64) 1015 __hsw_write(8) 1016 __hsw_write(16) 1017 __hsw_write(32) 1018 __hsw_write(64) 1019 __gen6_write(8) 1020 __gen6_write(16) 1021 __gen6_write(32) 1022 __gen6_write(64) 1023 __vgpu_write(8) 1024 __vgpu_write(16) 1025 __vgpu_write(32) 1026 __vgpu_write(64) 1027 1028 #undef __gen9_write 1029 #undef __chv_write 1030 #undef __gen8_write 1031 #undef __hsw_write 1032 #undef __gen6_write 1033 #undef __vgpu_write 1034 #undef GEN6_WRITE_FOOTER 1035 #undef GEN6_WRITE_HEADER 1036 1037 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ 1038 do { \ 1039 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ 1040 dev_priv->uncore.funcs.mmio_writew = x##_write16; \ 1041 dev_priv->uncore.funcs.mmio_writel = x##_write32; \ 1042 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ 1043 } while (0) 1044 1045 #define ASSIGN_READ_MMIO_VFUNCS(x) \ 1046 do { \ 1047 dev_priv->uncore.funcs.mmio_readb = x##_read8; \ 1048 dev_priv->uncore.funcs.mmio_readw = x##_read16; \ 1049 dev_priv->uncore.funcs.mmio_readl = x##_read32; \ 1050 dev_priv->uncore.funcs.mmio_readq = x##_read64; \ 1051 } while (0) 1052 1053 1054 static void fw_domain_init(struct drm_i915_private *dev_priv, 1055 enum forcewake_domain_id domain_id, 1056 u32 reg_set, u32 reg_ack) 1057 { 1058 struct intel_uncore_forcewake_domain *d; 1059 1060 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) 1061 return; 1062 1063 d = &dev_priv->uncore.fw_domain[domain_id]; 1064 1065 WARN_ON(d->wake_count); 1066 1067 d->wake_count = 0; 1068 d->reg_set = reg_set; 1069 d->reg_ack = reg_ack; 1070 1071 if (IS_GEN6(dev_priv)) { 1072 d->val_reset = 0; 1073 d->val_set = FORCEWAKE_KERNEL; 1074 d->val_clear = 0; 1075 } else { 1076 /* WaRsClearFWBitsAtReset:bdw,skl */ 1077 d->val_reset = _MASKED_BIT_DISABLE(0xffff); 1078 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); 1079 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); 1080 } 1081 1082 if (IS_VALLEYVIEW(dev_priv)) 1083 d->reg_post = FORCEWAKE_ACK_VLV; 1084 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) 1085 d->reg_post = ECOBUS; 1086 else 1087 d->reg_post = 0; 1088 1089 d->i915 = dev_priv; 1090 d->id = domain_id; 1091 1092 setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d); 1093 1094 dev_priv->uncore.fw_domains |= (1 << domain_id); 1095 1096 fw_domain_reset(d); 1097 } 1098 1099 static void intel_uncore_fw_domains_init(struct drm_device *dev) 1100 { 1101 struct drm_i915_private *dev_priv = dev->dev_private; 1102 1103 if (INTEL_INFO(dev_priv->dev)->gen <= 5) 1104 return; 1105 1106 if (IS_GEN9(dev)) { 1107 dev_priv->uncore.funcs.force_wake_get = fw_domains_get; 1108 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1109 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1110 FORCEWAKE_RENDER_GEN9, 1111 FORCEWAKE_ACK_RENDER_GEN9); 1112 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, 1113 FORCEWAKE_BLITTER_GEN9, 1114 FORCEWAKE_ACK_BLITTER_GEN9); 1115 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, 1116 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 1117 } else if (IS_VALLEYVIEW(dev)) { 1118 dev_priv->uncore.funcs.force_wake_get = fw_domains_get; 1119 if (!IS_CHERRYVIEW(dev)) 1120 dev_priv->uncore.funcs.force_wake_put = 1121 fw_domains_put_with_fifo; 1122 else 1123 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1124 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1125 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 1126 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, 1127 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 1128 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 1129 dev_priv->uncore.funcs.force_wake_get = 1130 fw_domains_get_with_thread_status; 1131 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1132 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1133 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 1134 } else if (IS_IVYBRIDGE(dev)) { 1135 u32 ecobus; 1136 1137 /* IVB configs may use multi-threaded forcewake */ 1138 1139 /* A small trick here - if the bios hasn't configured 1140 * MT forcewake, and if the device is in RC6, then 1141 * force_wake_mt_get will not wake the device and the 1142 * ECOBUS read will return zero. Which will be 1143 * (correctly) interpreted by the test below as MT 1144 * forcewake being disabled. 1145 */ 1146 dev_priv->uncore.funcs.force_wake_get = 1147 fw_domains_get_with_thread_status; 1148 dev_priv->uncore.funcs.force_wake_put = 1149 fw_domains_put_with_fifo; 1150 1151 /* We need to init first for ECOBUS access and then 1152 * determine later if we want to reinit, in case of MT access is 1153 * not working. In this stage we don't know which flavour this 1154 * ivb is, so it is better to reset also the gen6 fw registers 1155 * before the ecobus check. 1156 */ 1157 1158 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 1159 __raw_posting_read(dev_priv, ECOBUS); 1160 1161 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1162 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 1163 1164 mutex_lock(&dev->struct_mutex); 1165 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); 1166 ecobus = __raw_i915_read32(dev_priv, ECOBUS); 1167 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); 1168 mutex_unlock(&dev->struct_mutex); 1169 1170 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 1171 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); 1172 DRM_INFO("when using vblank-synced partial screen updates.\n"); 1173 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1174 FORCEWAKE, FORCEWAKE_ACK); 1175 } 1176 } else if (IS_GEN6(dev)) { 1177 dev_priv->uncore.funcs.force_wake_get = 1178 fw_domains_get_with_thread_status; 1179 dev_priv->uncore.funcs.force_wake_put = 1180 fw_domains_put_with_fifo; 1181 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1182 FORCEWAKE, FORCEWAKE_ACK); 1183 } 1184 1185 /* All future platforms are expected to require complex power gating */ 1186 WARN_ON(dev_priv->uncore.fw_domains == 0); 1187 } 1188 1189 void intel_uncore_init(struct drm_device *dev) 1190 { 1191 struct drm_i915_private *dev_priv = dev->dev_private; 1192 1193 i915_check_vgpu(dev); 1194 1195 intel_uncore_ellc_detect(dev); 1196 intel_uncore_fw_domains_init(dev); 1197 __intel_uncore_early_sanitize(dev, false); 1198 1199 switch (INTEL_INFO(dev)->gen) { 1200 default: 1201 MISSING_CASE(INTEL_INFO(dev)->gen); 1202 return; 1203 case 9: 1204 ASSIGN_WRITE_MMIO_VFUNCS(gen9); 1205 ASSIGN_READ_MMIO_VFUNCS(gen9); 1206 break; 1207 case 8: 1208 if (IS_CHERRYVIEW(dev)) { 1209 ASSIGN_WRITE_MMIO_VFUNCS(chv); 1210 ASSIGN_READ_MMIO_VFUNCS(chv); 1211 1212 } else { 1213 ASSIGN_WRITE_MMIO_VFUNCS(gen8); 1214 ASSIGN_READ_MMIO_VFUNCS(gen6); 1215 } 1216 break; 1217 case 7: 1218 case 6: 1219 if (IS_HASWELL(dev)) { 1220 ASSIGN_WRITE_MMIO_VFUNCS(hsw); 1221 } else { 1222 ASSIGN_WRITE_MMIO_VFUNCS(gen6); 1223 } 1224 1225 if (IS_VALLEYVIEW(dev)) { 1226 ASSIGN_READ_MMIO_VFUNCS(vlv); 1227 } else { 1228 ASSIGN_READ_MMIO_VFUNCS(gen6); 1229 } 1230 break; 1231 case 5: 1232 ASSIGN_WRITE_MMIO_VFUNCS(gen5); 1233 ASSIGN_READ_MMIO_VFUNCS(gen5); 1234 break; 1235 case 4: 1236 case 3: 1237 case 2: 1238 ASSIGN_WRITE_MMIO_VFUNCS(gen2); 1239 ASSIGN_READ_MMIO_VFUNCS(gen2); 1240 break; 1241 } 1242 1243 if (intel_vgpu_active(dev)) { 1244 ASSIGN_WRITE_MMIO_VFUNCS(vgpu); 1245 ASSIGN_READ_MMIO_VFUNCS(vgpu); 1246 } 1247 1248 i915_check_and_clear_faults(dev); 1249 } 1250 #undef ASSIGN_WRITE_MMIO_VFUNCS 1251 #undef ASSIGN_READ_MMIO_VFUNCS 1252 1253 void intel_uncore_fini(struct drm_device *dev) 1254 { 1255 /* Paranoia: make sure we have disabled everything before we exit. */ 1256 intel_uncore_sanitize(dev); 1257 intel_uncore_forcewake_reset(dev, false); 1258 } 1259 1260 #define GEN_RANGE(l, h) GENMASK(h, l) 1261 1262 static const struct register_whitelist { 1263 uint64_t offset; 1264 uint32_t size; 1265 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ 1266 uint32_t gen_bitmask; 1267 } whitelist[] = { 1268 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) }, 1269 }; 1270 1271 int i915_reg_read_ioctl(struct drm_device *dev, 1272 void *data, struct drm_file *file) 1273 { 1274 struct drm_i915_private *dev_priv = dev->dev_private; 1275 struct drm_i915_reg_read *reg = data; 1276 struct register_whitelist const *entry = whitelist; 1277 unsigned size; 1278 u64 offset; 1279 int i, ret = 0; 1280 1281 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { 1282 if (entry->offset == (reg->offset & -entry->size) && 1283 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) 1284 break; 1285 } 1286 1287 if (i == ARRAY_SIZE(whitelist)) 1288 return -EINVAL; 1289 1290 /* We use the low bits to encode extra flags as the register should 1291 * be naturally aligned (and those that are not so aligned merely 1292 * limit the available flags for that register). 1293 */ 1294 offset = entry->offset; 1295 size = entry->size; 1296 size |= reg->offset ^ offset; 1297 1298 intel_runtime_pm_get(dev_priv); 1299 1300 switch (size) { 1301 case 8 | 1: 1302 reg->val = I915_READ64_2x32(offset, offset+4); 1303 break; 1304 case 8: 1305 reg->val = I915_READ64(offset); 1306 break; 1307 case 4: 1308 reg->val = I915_READ(offset); 1309 break; 1310 case 2: 1311 reg->val = I915_READ16(offset); 1312 break; 1313 case 1: 1314 reg->val = I915_READ8(offset); 1315 break; 1316 default: 1317 ret = -EINVAL; 1318 goto out; 1319 } 1320 1321 out: 1322 intel_runtime_pm_put(dev_priv); 1323 return ret; 1324 } 1325 1326 int i915_get_reset_stats_ioctl(struct drm_device *dev, 1327 void *data, struct drm_file *file) 1328 { 1329 struct drm_i915_private *dev_priv = dev->dev_private; 1330 struct drm_i915_reset_stats *args = data; 1331 struct i915_ctx_hang_stats *hs; 1332 struct intel_context *ctx; 1333 int ret; 1334 1335 if (args->flags || args->pad) 1336 return -EINVAL; 1337 1338 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) 1339 return -EPERM; 1340 1341 ret = mutex_lock_interruptible(&dev->struct_mutex); 1342 if (ret) 1343 return ret; 1344 1345 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); 1346 if (IS_ERR(ctx)) { 1347 mutex_unlock(&dev->struct_mutex); 1348 return PTR_ERR(ctx); 1349 } 1350 hs = &ctx->hang_stats; 1351 1352 if (capable(CAP_SYS_ADMIN)) 1353 args->reset_count = i915_reset_count(&dev_priv->gpu_error); 1354 else 1355 args->reset_count = 0; 1356 1357 args->batch_active = hs->batch_active; 1358 args->batch_pending = hs->batch_pending; 1359 1360 mutex_unlock(&dev->struct_mutex); 1361 1362 return 0; 1363 } 1364 1365 static int i915_reset_complete(struct drm_device *dev) 1366 { 1367 u8 gdrst; 1368 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); 1369 return (gdrst & GRDOM_RESET_STATUS) == 0; 1370 } 1371 1372 static int i915_do_reset(struct drm_device *dev) 1373 { 1374 /* assert reset for at least 20 usec */ 1375 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); 1376 udelay(20); 1377 pci_write_config_byte(dev->pdev, I915_GDRST, 0); 1378 1379 return wait_for(i915_reset_complete(dev), 500); 1380 } 1381 1382 static int g4x_reset_complete(struct drm_device *dev) 1383 { 1384 u8 gdrst; 1385 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); 1386 return (gdrst & GRDOM_RESET_ENABLE) == 0; 1387 } 1388 1389 static int g33_do_reset(struct drm_device *dev) 1390 { 1391 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); 1392 return wait_for(g4x_reset_complete(dev), 500); 1393 } 1394 1395 static int g4x_do_reset(struct drm_device *dev) 1396 { 1397 struct drm_i915_private *dev_priv = dev->dev_private; 1398 int ret; 1399 1400 pci_write_config_byte(dev->pdev, I915_GDRST, 1401 GRDOM_RENDER | GRDOM_RESET_ENABLE); 1402 ret = wait_for(g4x_reset_complete(dev), 500); 1403 if (ret) 1404 return ret; 1405 1406 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1407 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); 1408 POSTING_READ(VDECCLK_GATE_D); 1409 1410 pci_write_config_byte(dev->pdev, I915_GDRST, 1411 GRDOM_MEDIA | GRDOM_RESET_ENABLE); 1412 ret = wait_for(g4x_reset_complete(dev), 500); 1413 if (ret) 1414 return ret; 1415 1416 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1417 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); 1418 POSTING_READ(VDECCLK_GATE_D); 1419 1420 pci_write_config_byte(dev->pdev, I915_GDRST, 0); 1421 1422 return 0; 1423 } 1424 1425 static int ironlake_do_reset(struct drm_device *dev) 1426 { 1427 struct drm_i915_private *dev_priv = dev->dev_private; 1428 int ret; 1429 1430 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 1431 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); 1432 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 1433 ILK_GRDOM_RESET_ENABLE) == 0, 500); 1434 if (ret) 1435 return ret; 1436 1437 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 1438 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); 1439 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 1440 ILK_GRDOM_RESET_ENABLE) == 0, 500); 1441 if (ret) 1442 return ret; 1443 1444 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); 1445 1446 return 0; 1447 } 1448 1449 static int gen6_do_reset(struct drm_device *dev) 1450 { 1451 struct drm_i915_private *dev_priv = dev->dev_private; 1452 int ret; 1453 1454 /* Reset the chip */ 1455 1456 /* GEN6_GDRST is not in the gt power well, no need to check 1457 * for fifo space for the write or forcewake the chip for 1458 * the read 1459 */ 1460 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); 1461 1462 /* Spin waiting for the device to ack the reset request */ 1463 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); 1464 1465 intel_uncore_forcewake_reset(dev, true); 1466 1467 return ret; 1468 } 1469 1470 static int wait_for_register(struct drm_i915_private *dev_priv, 1471 const u32 reg, 1472 const u32 mask, 1473 const u32 value, 1474 const unsigned long timeout_ms) 1475 { 1476 return wait_for((I915_READ(reg) & mask) == value, timeout_ms); 1477 } 1478 1479 static int gen8_do_reset(struct drm_device *dev) 1480 { 1481 struct drm_i915_private *dev_priv = dev->dev_private; 1482 struct intel_engine_cs *engine; 1483 int i; 1484 1485 for_each_ring(engine, dev_priv, i) { 1486 I915_WRITE(RING_RESET_CTL(engine->mmio_base), 1487 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); 1488 1489 if (wait_for_register(dev_priv, 1490 RING_RESET_CTL(engine->mmio_base), 1491 RESET_CTL_READY_TO_RESET, 1492 RESET_CTL_READY_TO_RESET, 1493 700)) { 1494 DRM_ERROR("%s: reset request timeout\n", engine->name); 1495 goto not_ready; 1496 } 1497 } 1498 1499 return gen6_do_reset(dev); 1500 1501 not_ready: 1502 for_each_ring(engine, dev_priv, i) 1503 I915_WRITE(RING_RESET_CTL(engine->mmio_base), 1504 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); 1505 1506 return -EIO; 1507 } 1508 1509 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *) 1510 { 1511 if (!i915.reset) 1512 return NULL; 1513 1514 if (INTEL_INFO(dev)->gen >= 8) 1515 return gen8_do_reset; 1516 else if (INTEL_INFO(dev)->gen >= 6) 1517 return gen6_do_reset; 1518 else if (IS_GEN5(dev)) 1519 return ironlake_do_reset; 1520 else if (IS_G4X(dev)) 1521 return g4x_do_reset; 1522 else if (IS_G33(dev)) 1523 return g33_do_reset; 1524 else if (INTEL_INFO(dev)->gen >= 3) 1525 return i915_do_reset; 1526 else 1527 return NULL; 1528 } 1529 1530 int intel_gpu_reset(struct drm_device *dev) 1531 { 1532 int (*reset)(struct drm_device *); 1533 1534 reset = intel_get_gpu_reset(dev); 1535 if (reset == NULL) 1536 return -ENODEV; 1537 1538 return reset(dev); 1539 } 1540 1541 bool intel_has_gpu_reset(struct drm_device *dev) 1542 { 1543 return intel_get_gpu_reset(dev) != NULL; 1544 } 1545 1546 void intel_uncore_check_errors(struct drm_device *dev) 1547 { 1548 struct drm_i915_private *dev_priv = dev->dev_private; 1549 1550 if (HAS_FPGA_DBG_UNCLAIMED(dev) && 1551 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { 1552 DRM_ERROR("Unclaimed register before interrupt\n"); 1553 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 1554 } 1555 } 1556