1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_drv.h" 26 #include "i915_vgpu.h" 27 28 #include <asm/iosf_mbi.h> 29 #include <linux/pm_runtime.h> 30 31 #define FORCEWAKE_ACK_TIMEOUT_MS 50 32 #define GT_FIFO_TIMEOUT_MS 10 33 34 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) 35 36 static const char * const forcewake_domain_names[] = { 37 "render", 38 "blitter", 39 "media", 40 }; 41 42 const char * 43 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 44 { 45 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 46 47 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 48 return forcewake_domain_names[id]; 49 50 WARN_ON(id); 51 52 return "unknown"; 53 } 54 55 static inline void 56 fw_domain_reset(struct drm_i915_private *i915, 57 const struct intel_uncore_forcewake_domain *d) 58 { 59 __raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset); 60 } 61 62 static inline void 63 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 64 { 65 d->wake_count++; 66 hrtimer_start_range_ns(&d->timer, 67 NSEC_PER_MSEC, 68 NSEC_PER_MSEC, 69 HRTIMER_MODE_REL); 70 } 71 72 static inline void 73 fw_domain_wait_ack_clear(const struct drm_i915_private *i915, 74 const struct intel_uncore_forcewake_domain *d) 75 { 76 if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) & 77 FORCEWAKE_KERNEL) == 0, 78 FORCEWAKE_ACK_TIMEOUT_MS)) 79 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 80 intel_uncore_forcewake_domain_to_str(d->id)); 81 } 82 83 static inline void 84 fw_domain_get(struct drm_i915_private *i915, 85 const struct intel_uncore_forcewake_domain *d) 86 { 87 __raw_i915_write32(i915, d->reg_set, i915->uncore.fw_set); 88 } 89 90 static inline void 91 fw_domain_wait_ack(const struct drm_i915_private *i915, 92 const struct intel_uncore_forcewake_domain *d) 93 { 94 if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) & 95 FORCEWAKE_KERNEL), 96 FORCEWAKE_ACK_TIMEOUT_MS)) 97 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 98 intel_uncore_forcewake_domain_to_str(d->id)); 99 } 100 101 static inline void 102 fw_domain_put(const struct drm_i915_private *i915, 103 const struct intel_uncore_forcewake_domain *d) 104 { 105 __raw_i915_write32(i915, d->reg_set, i915->uncore.fw_clear); 106 } 107 108 static void 109 fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains) 110 { 111 struct intel_uncore_forcewake_domain *d; 112 unsigned int tmp; 113 114 GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains); 115 116 for_each_fw_domain_masked(d, fw_domains, i915, tmp) { 117 fw_domain_wait_ack_clear(i915, d); 118 fw_domain_get(i915, d); 119 } 120 121 for_each_fw_domain_masked(d, fw_domains, i915, tmp) 122 fw_domain_wait_ack(i915, d); 123 124 i915->uncore.fw_domains_active |= fw_domains; 125 } 126 127 static void 128 fw_domains_put(struct drm_i915_private *i915, enum forcewake_domains fw_domains) 129 { 130 struct intel_uncore_forcewake_domain *d; 131 unsigned int tmp; 132 133 GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains); 134 135 for_each_fw_domain_masked(d, fw_domains, i915, tmp) 136 fw_domain_put(i915, d); 137 138 i915->uncore.fw_domains_active &= ~fw_domains; 139 } 140 141 static void 142 fw_domains_reset(struct drm_i915_private *i915, 143 enum forcewake_domains fw_domains) 144 { 145 struct intel_uncore_forcewake_domain *d; 146 unsigned int tmp; 147 148 if (!fw_domains) 149 return; 150 151 GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains); 152 153 for_each_fw_domain_masked(d, fw_domains, i915, tmp) 154 fw_domain_reset(i915, d); 155 } 156 157 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 158 { 159 /* w/a for a sporadic read returning 0 by waiting for the GT 160 * thread to wake up. 161 */ 162 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & 163 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) 164 DRM_ERROR("GT thread status wait timed out\n"); 165 } 166 167 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, 168 enum forcewake_domains fw_domains) 169 { 170 fw_domains_get(dev_priv, fw_domains); 171 172 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 173 __gen6_gt_wait_for_thread_c0(dev_priv); 174 } 175 176 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) 177 { 178 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); 179 180 return count & GT_FIFO_FREE_ENTRIES_MASK; 181 } 182 183 static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 184 { 185 u32 n; 186 187 /* On VLV, FIFO will be shared by both SW and HW. 188 * So, we need to read the FREE_ENTRIES everytime */ 189 if (IS_VALLEYVIEW(dev_priv)) 190 n = fifo_free_entries(dev_priv); 191 else 192 n = dev_priv->uncore.fifo_count; 193 194 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { 195 if (wait_for_atomic((n = fifo_free_entries(dev_priv)) > 196 GT_FIFO_NUM_RESERVED_ENTRIES, 197 GT_FIFO_TIMEOUT_MS)) { 198 DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n); 199 return; 200 } 201 } 202 203 dev_priv->uncore.fifo_count = n - 1; 204 } 205 206 static enum hrtimer_restart 207 intel_uncore_fw_release_timer(struct hrtimer *timer) 208 { 209 struct intel_uncore_forcewake_domain *domain = 210 container_of(timer, struct intel_uncore_forcewake_domain, timer); 211 struct drm_i915_private *dev_priv = 212 container_of(domain, struct drm_i915_private, uncore.fw_domain[domain->id]); 213 unsigned long irqflags; 214 215 assert_rpm_device_not_suspended(dev_priv); 216 217 if (xchg(&domain->active, false)) 218 return HRTIMER_RESTART; 219 220 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 221 if (WARN_ON(domain->wake_count == 0)) 222 domain->wake_count++; 223 224 if (--domain->wake_count == 0) 225 dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask); 226 227 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 228 229 return HRTIMER_NORESTART; 230 } 231 232 static void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, 233 bool restore) 234 { 235 unsigned long irqflags; 236 struct intel_uncore_forcewake_domain *domain; 237 int retry_count = 100; 238 enum forcewake_domains fw, active_domains; 239 240 /* Hold uncore.lock across reset to prevent any register access 241 * with forcewake not set correctly. Wait until all pending 242 * timers are run before holding. 243 */ 244 while (1) { 245 unsigned int tmp; 246 247 active_domains = 0; 248 249 for_each_fw_domain(domain, dev_priv, tmp) { 250 smp_store_mb(domain->active, false); 251 if (hrtimer_cancel(&domain->timer) == 0) 252 continue; 253 254 intel_uncore_fw_release_timer(&domain->timer); 255 } 256 257 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 258 259 for_each_fw_domain(domain, dev_priv, tmp) { 260 if (hrtimer_active(&domain->timer)) 261 active_domains |= domain->mask; 262 } 263 264 if (active_domains == 0) 265 break; 266 267 if (--retry_count == 0) { 268 DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); 269 break; 270 } 271 272 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 273 cond_resched(); 274 } 275 276 WARN_ON(active_domains); 277 278 fw = dev_priv->uncore.fw_domains_active; 279 if (fw) 280 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); 281 282 fw_domains_reset(dev_priv, dev_priv->uncore.fw_domains); 283 284 if (restore) { /* If reset with a user forcewake, try to restore */ 285 if (fw) 286 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); 287 288 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) 289 dev_priv->uncore.fifo_count = 290 fifo_free_entries(dev_priv); 291 } 292 293 if (!restore) 294 assert_forcewakes_inactive(dev_priv); 295 296 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 297 } 298 299 static u64 gen9_edram_size(struct drm_i915_private *dev_priv) 300 { 301 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; 302 const unsigned int sets[4] = { 1, 1, 2, 2 }; 303 const u32 cap = dev_priv->edram_cap; 304 305 return EDRAM_NUM_BANKS(cap) * 306 ways[EDRAM_WAYS_IDX(cap)] * 307 sets[EDRAM_SETS_IDX(cap)] * 308 1024 * 1024; 309 } 310 311 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) 312 { 313 if (!HAS_EDRAM(dev_priv)) 314 return 0; 315 316 /* The needed capability bits for size calculation 317 * are not there with pre gen9 so return 128MB always. 318 */ 319 if (INTEL_GEN(dev_priv) < 9) 320 return 128 * 1024 * 1024; 321 322 return gen9_edram_size(dev_priv); 323 } 324 325 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) 326 { 327 if (IS_HASWELL(dev_priv) || 328 IS_BROADWELL(dev_priv) || 329 INTEL_GEN(dev_priv) >= 9) { 330 dev_priv->edram_cap = __raw_i915_read32(dev_priv, 331 HSW_EDRAM_CAP); 332 333 /* NB: We can't write IDICR yet because we do not have gt funcs 334 * set up */ 335 } else { 336 dev_priv->edram_cap = 0; 337 } 338 339 if (HAS_EDRAM(dev_priv)) 340 DRM_INFO("Found %lluMB of eDRAM\n", 341 intel_uncore_edram_size(dev_priv) / (1024 * 1024)); 342 } 343 344 static bool 345 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 346 { 347 u32 dbg; 348 349 dbg = __raw_i915_read32(dev_priv, FPGA_DBG); 350 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 351 return false; 352 353 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 354 355 return true; 356 } 357 358 static bool 359 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 360 { 361 u32 cer; 362 363 cer = __raw_i915_read32(dev_priv, CLAIM_ER); 364 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 365 return false; 366 367 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); 368 369 return true; 370 } 371 372 static bool 373 gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv) 374 { 375 u32 fifodbg; 376 377 fifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); 378 379 if (unlikely(fifodbg)) { 380 DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg); 381 __raw_i915_write32(dev_priv, GTFIFODBG, fifodbg); 382 } 383 384 return fifodbg; 385 } 386 387 static bool 388 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 389 { 390 bool ret = false; 391 392 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) 393 ret |= fpga_check_for_unclaimed_mmio(dev_priv); 394 395 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 396 ret |= vlv_check_for_unclaimed_mmio(dev_priv); 397 398 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) 399 ret |= gen6_check_for_fifo_debug(dev_priv); 400 401 return ret; 402 } 403 404 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, 405 bool restore_forcewake) 406 { 407 /* clear out unclaimed reg detection bit */ 408 if (check_for_unclaimed_mmio(dev_priv)) 409 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); 410 411 /* WaDisableShadowRegForCpd:chv */ 412 if (IS_CHERRYVIEW(dev_priv)) { 413 __raw_i915_write32(dev_priv, GTFIFOCTL, 414 __raw_i915_read32(dev_priv, GTFIFOCTL) | 415 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 416 GT_FIFO_CTL_RC6_POLICY_STALL); 417 } 418 419 intel_uncore_forcewake_reset(dev_priv, restore_forcewake); 420 } 421 422 void intel_uncore_suspend(struct drm_i915_private *dev_priv) 423 { 424 iosf_mbi_unregister_pmic_bus_access_notifier( 425 &dev_priv->uncore.pmic_bus_access_nb); 426 intel_uncore_forcewake_reset(dev_priv, false); 427 } 428 429 void intel_uncore_resume_early(struct drm_i915_private *dev_priv) 430 { 431 __intel_uncore_early_sanitize(dev_priv, true); 432 iosf_mbi_register_pmic_bus_access_notifier( 433 &dev_priv->uncore.pmic_bus_access_nb); 434 i915_check_and_clear_faults(dev_priv); 435 } 436 437 void intel_uncore_sanitize(struct drm_i915_private *dev_priv) 438 { 439 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6); 440 441 /* BIOS often leaves RC6 enabled, but disable it for hw init */ 442 intel_sanitize_gt_powersave(dev_priv); 443 } 444 445 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 446 enum forcewake_domains fw_domains) 447 { 448 struct intel_uncore_forcewake_domain *domain; 449 unsigned int tmp; 450 451 fw_domains &= dev_priv->uncore.fw_domains; 452 453 for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) { 454 if (domain->wake_count++) { 455 fw_domains &= ~domain->mask; 456 domain->active = true; 457 } 458 } 459 460 if (fw_domains) 461 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); 462 } 463 464 /** 465 * intel_uncore_forcewake_get - grab forcewake domain references 466 * @dev_priv: i915 device instance 467 * @fw_domains: forcewake domains to get reference on 468 * 469 * This function can be used get GT's forcewake domain references. 470 * Normal register access will handle the forcewake domains automatically. 471 * However if some sequence requires the GT to not power down a particular 472 * forcewake domains this function should be called at the beginning of the 473 * sequence. And subsequently the reference should be dropped by symmetric 474 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 475 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 476 */ 477 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 478 enum forcewake_domains fw_domains) 479 { 480 unsigned long irqflags; 481 482 if (!dev_priv->uncore.funcs.force_wake_get) 483 return; 484 485 assert_rpm_wakelock_held(dev_priv); 486 487 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 488 __intel_uncore_forcewake_get(dev_priv, fw_domains); 489 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 490 } 491 492 /** 493 * intel_uncore_forcewake_get__locked - grab forcewake domain references 494 * @dev_priv: i915 device instance 495 * @fw_domains: forcewake domains to get reference on 496 * 497 * See intel_uncore_forcewake_get(). This variant places the onus 498 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 499 */ 500 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, 501 enum forcewake_domains fw_domains) 502 { 503 lockdep_assert_held(&dev_priv->uncore.lock); 504 505 if (!dev_priv->uncore.funcs.force_wake_get) 506 return; 507 508 __intel_uncore_forcewake_get(dev_priv, fw_domains); 509 } 510 511 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 512 enum forcewake_domains fw_domains) 513 { 514 struct intel_uncore_forcewake_domain *domain; 515 unsigned int tmp; 516 517 fw_domains &= dev_priv->uncore.fw_domains; 518 519 for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) { 520 if (WARN_ON(domain->wake_count == 0)) 521 continue; 522 523 if (--domain->wake_count) { 524 domain->active = true; 525 continue; 526 } 527 528 fw_domain_arm_timer(domain); 529 } 530 } 531 532 /** 533 * intel_uncore_forcewake_put - release a forcewake domain reference 534 * @dev_priv: i915 device instance 535 * @fw_domains: forcewake domains to put references 536 * 537 * This function drops the device-level forcewakes for specified 538 * domains obtained by intel_uncore_forcewake_get(). 539 */ 540 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 541 enum forcewake_domains fw_domains) 542 { 543 unsigned long irqflags; 544 545 if (!dev_priv->uncore.funcs.force_wake_put) 546 return; 547 548 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 549 __intel_uncore_forcewake_put(dev_priv, fw_domains); 550 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 551 } 552 553 /** 554 * intel_uncore_forcewake_put__locked - grab forcewake domain references 555 * @dev_priv: i915 device instance 556 * @fw_domains: forcewake domains to get reference on 557 * 558 * See intel_uncore_forcewake_put(). This variant places the onus 559 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 560 */ 561 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, 562 enum forcewake_domains fw_domains) 563 { 564 lockdep_assert_held(&dev_priv->uncore.lock); 565 566 if (!dev_priv->uncore.funcs.force_wake_put) 567 return; 568 569 __intel_uncore_forcewake_put(dev_priv, fw_domains); 570 } 571 572 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) 573 { 574 if (!dev_priv->uncore.funcs.force_wake_get) 575 return; 576 577 WARN_ON(dev_priv->uncore.fw_domains_active); 578 } 579 580 /* We give fast paths for the really cool registers */ 581 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) 582 583 #define __gen6_reg_read_fw_domains(offset) \ 584 ({ \ 585 enum forcewake_domains __fwd; \ 586 if (NEEDS_FORCE_WAKE(offset)) \ 587 __fwd = FORCEWAKE_RENDER; \ 588 else \ 589 __fwd = 0; \ 590 __fwd; \ 591 }) 592 593 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) 594 { 595 if (offset < entry->start) 596 return -1; 597 else if (offset > entry->end) 598 return 1; 599 else 600 return 0; 601 } 602 603 /* Copied and "macroized" from lib/bsearch.c */ 604 #define BSEARCH(key, base, num, cmp) ({ \ 605 unsigned int start__ = 0, end__ = (num); \ 606 typeof(base) result__ = NULL; \ 607 while (start__ < end__) { \ 608 unsigned int mid__ = start__ + (end__ - start__) / 2; \ 609 int ret__ = (cmp)((key), (base) + mid__); \ 610 if (ret__ < 0) { \ 611 end__ = mid__; \ 612 } else if (ret__ > 0) { \ 613 start__ = mid__ + 1; \ 614 } else { \ 615 result__ = (base) + mid__; \ 616 break; \ 617 } \ 618 } \ 619 result__; \ 620 }) 621 622 static enum forcewake_domains 623 find_fw_domain(struct drm_i915_private *dev_priv, u32 offset) 624 { 625 const struct intel_forcewake_range *entry; 626 627 entry = BSEARCH(offset, 628 dev_priv->uncore.fw_domains_table, 629 dev_priv->uncore.fw_domains_table_entries, 630 fw_range_cmp); 631 632 if (!entry) 633 return 0; 634 635 WARN(entry->domains & ~dev_priv->uncore.fw_domains, 636 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", 637 entry->domains & ~dev_priv->uncore.fw_domains, offset); 638 639 return entry->domains; 640 } 641 642 #define GEN_FW_RANGE(s, e, d) \ 643 { .start = (s), .end = (e), .domains = (d) } 644 645 #define HAS_FWTABLE(dev_priv) \ 646 (INTEL_GEN(dev_priv) >= 9 || \ 647 IS_CHERRYVIEW(dev_priv) || \ 648 IS_VALLEYVIEW(dev_priv)) 649 650 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 651 static const struct intel_forcewake_range __vlv_fw_ranges[] = { 652 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 653 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), 654 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), 655 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 656 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), 657 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), 658 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 659 }; 660 661 #define __fwtable_reg_read_fw_domains(offset) \ 662 ({ \ 663 enum forcewake_domains __fwd = 0; \ 664 if (NEEDS_FORCE_WAKE((offset))) \ 665 __fwd = find_fw_domain(dev_priv, offset); \ 666 __fwd; \ 667 }) 668 669 /* *Must* be sorted by offset! See intel_shadow_table_check(). */ 670 static const i915_reg_t gen8_shadowed_regs[] = { 671 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 672 GEN6_RPNSWREQ, /* 0xA008 */ 673 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 674 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ 675 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ 676 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 677 /* TODO: Other registers are not yet used */ 678 }; 679 680 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) 681 { 682 u32 offset = i915_mmio_reg_offset(*reg); 683 684 if (key < offset) 685 return -1; 686 else if (key > offset) 687 return 1; 688 else 689 return 0; 690 } 691 692 static bool is_gen8_shadowed(u32 offset) 693 { 694 const i915_reg_t *regs = gen8_shadowed_regs; 695 696 return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs), 697 mmio_reg_cmp); 698 } 699 700 #define __gen8_reg_write_fw_domains(offset) \ 701 ({ \ 702 enum forcewake_domains __fwd; \ 703 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ 704 __fwd = FORCEWAKE_RENDER; \ 705 else \ 706 __fwd = 0; \ 707 __fwd; \ 708 }) 709 710 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 711 static const struct intel_forcewake_range __chv_fw_ranges[] = { 712 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 713 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 714 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 715 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 716 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 717 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 718 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), 719 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 720 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 721 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 722 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), 723 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 724 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 725 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), 726 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), 727 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), 728 }; 729 730 #define __fwtable_reg_write_fw_domains(offset) \ 731 ({ \ 732 enum forcewake_domains __fwd = 0; \ 733 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ 734 __fwd = find_fw_domain(dev_priv, offset); \ 735 __fwd; \ 736 }) 737 738 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 739 static const struct intel_forcewake_range __gen9_fw_ranges[] = { 740 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER), 741 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ 742 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 743 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER), 744 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 745 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER), 746 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 747 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER), 748 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), 749 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 750 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER), 751 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 752 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER), 753 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), 754 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER), 755 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 756 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER), 757 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 758 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER), 759 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 760 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER), 761 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 762 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER), 763 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), 764 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER), 765 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 766 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER), 767 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), 768 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER), 769 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), 770 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER), 771 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 772 }; 773 774 static void 775 ilk_dummy_write(struct drm_i915_private *dev_priv) 776 { 777 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 778 * the chip from rc6 before touching it for real. MI_MODE is masked, 779 * hence harmless to write 0 into. */ 780 __raw_i915_write32(dev_priv, MI_MODE, 0); 781 } 782 783 static void 784 __unclaimed_reg_debug(struct drm_i915_private *dev_priv, 785 const i915_reg_t reg, 786 const bool read, 787 const bool before) 788 { 789 if (WARN(check_for_unclaimed_mmio(dev_priv) && !before, 790 "Unclaimed %s register 0x%x\n", 791 read ? "read from" : "write to", 792 i915_mmio_reg_offset(reg))) 793 i915.mmio_debug--; /* Only report the first N failures */ 794 } 795 796 static inline void 797 unclaimed_reg_debug(struct drm_i915_private *dev_priv, 798 const i915_reg_t reg, 799 const bool read, 800 const bool before) 801 { 802 if (likely(!i915.mmio_debug)) 803 return; 804 805 __unclaimed_reg_debug(dev_priv, reg, read, before); 806 } 807 808 #define GEN2_READ_HEADER(x) \ 809 u##x val = 0; \ 810 assert_rpm_wakelock_held(dev_priv); 811 812 #define GEN2_READ_FOOTER \ 813 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 814 return val 815 816 #define __gen2_read(x) \ 817 static u##x \ 818 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 819 GEN2_READ_HEADER(x); \ 820 val = __raw_i915_read##x(dev_priv, reg); \ 821 GEN2_READ_FOOTER; \ 822 } 823 824 #define __gen5_read(x) \ 825 static u##x \ 826 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 827 GEN2_READ_HEADER(x); \ 828 ilk_dummy_write(dev_priv); \ 829 val = __raw_i915_read##x(dev_priv, reg); \ 830 GEN2_READ_FOOTER; \ 831 } 832 833 __gen5_read(8) 834 __gen5_read(16) 835 __gen5_read(32) 836 __gen5_read(64) 837 __gen2_read(8) 838 __gen2_read(16) 839 __gen2_read(32) 840 __gen2_read(64) 841 842 #undef __gen5_read 843 #undef __gen2_read 844 845 #undef GEN2_READ_FOOTER 846 #undef GEN2_READ_HEADER 847 848 #define GEN6_READ_HEADER(x) \ 849 u32 offset = i915_mmio_reg_offset(reg); \ 850 unsigned long irqflags; \ 851 u##x val = 0; \ 852 assert_rpm_wakelock_held(dev_priv); \ 853 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ 854 unclaimed_reg_debug(dev_priv, reg, true, true) 855 856 #define GEN6_READ_FOOTER \ 857 unclaimed_reg_debug(dev_priv, reg, true, false); \ 858 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ 859 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 860 return val 861 862 static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv, 863 enum forcewake_domains fw_domains) 864 { 865 struct intel_uncore_forcewake_domain *domain; 866 unsigned int tmp; 867 868 GEM_BUG_ON(fw_domains & ~dev_priv->uncore.fw_domains); 869 870 for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) 871 fw_domain_arm_timer(domain); 872 873 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); 874 } 875 876 static inline void __force_wake_auto(struct drm_i915_private *dev_priv, 877 enum forcewake_domains fw_domains) 878 { 879 if (WARN_ON(!fw_domains)) 880 return; 881 882 /* Turn on all requested but inactive supported forcewake domains. */ 883 fw_domains &= dev_priv->uncore.fw_domains; 884 fw_domains &= ~dev_priv->uncore.fw_domains_active; 885 886 if (fw_domains) 887 ___force_wake_auto(dev_priv, fw_domains); 888 } 889 890 #define __gen_read(func, x) \ 891 static u##x \ 892 func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 893 enum forcewake_domains fw_engine; \ 894 GEN6_READ_HEADER(x); \ 895 fw_engine = __##func##_reg_read_fw_domains(offset); \ 896 if (fw_engine) \ 897 __force_wake_auto(dev_priv, fw_engine); \ 898 val = __raw_i915_read##x(dev_priv, reg); \ 899 GEN6_READ_FOOTER; \ 900 } 901 #define __gen6_read(x) __gen_read(gen6, x) 902 #define __fwtable_read(x) __gen_read(fwtable, x) 903 904 __fwtable_read(8) 905 __fwtable_read(16) 906 __fwtable_read(32) 907 __fwtable_read(64) 908 __gen6_read(8) 909 __gen6_read(16) 910 __gen6_read(32) 911 __gen6_read(64) 912 913 #undef __fwtable_read 914 #undef __gen6_read 915 #undef GEN6_READ_FOOTER 916 #undef GEN6_READ_HEADER 917 918 #define GEN2_WRITE_HEADER \ 919 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 920 assert_rpm_wakelock_held(dev_priv); \ 921 922 #define GEN2_WRITE_FOOTER 923 924 #define __gen2_write(x) \ 925 static void \ 926 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 927 GEN2_WRITE_HEADER; \ 928 __raw_i915_write##x(dev_priv, reg, val); \ 929 GEN2_WRITE_FOOTER; \ 930 } 931 932 #define __gen5_write(x) \ 933 static void \ 934 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 935 GEN2_WRITE_HEADER; \ 936 ilk_dummy_write(dev_priv); \ 937 __raw_i915_write##x(dev_priv, reg, val); \ 938 GEN2_WRITE_FOOTER; \ 939 } 940 941 __gen5_write(8) 942 __gen5_write(16) 943 __gen5_write(32) 944 __gen2_write(8) 945 __gen2_write(16) 946 __gen2_write(32) 947 948 #undef __gen5_write 949 #undef __gen2_write 950 951 #undef GEN2_WRITE_FOOTER 952 #undef GEN2_WRITE_HEADER 953 954 #define GEN6_WRITE_HEADER \ 955 u32 offset = i915_mmio_reg_offset(reg); \ 956 unsigned long irqflags; \ 957 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 958 assert_rpm_wakelock_held(dev_priv); \ 959 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ 960 unclaimed_reg_debug(dev_priv, reg, false, true) 961 962 #define GEN6_WRITE_FOOTER \ 963 unclaimed_reg_debug(dev_priv, reg, false, false); \ 964 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) 965 966 #define __gen6_write(x) \ 967 static void \ 968 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 969 GEN6_WRITE_HEADER; \ 970 if (NEEDS_FORCE_WAKE(offset)) \ 971 __gen6_gt_wait_for_fifo(dev_priv); \ 972 __raw_i915_write##x(dev_priv, reg, val); \ 973 GEN6_WRITE_FOOTER; \ 974 } 975 976 #define __gen_write(func, x) \ 977 static void \ 978 func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 979 enum forcewake_domains fw_engine; \ 980 GEN6_WRITE_HEADER; \ 981 fw_engine = __##func##_reg_write_fw_domains(offset); \ 982 if (fw_engine) \ 983 __force_wake_auto(dev_priv, fw_engine); \ 984 __raw_i915_write##x(dev_priv, reg, val); \ 985 GEN6_WRITE_FOOTER; \ 986 } 987 #define __gen8_write(x) __gen_write(gen8, x) 988 #define __fwtable_write(x) __gen_write(fwtable, x) 989 990 __fwtable_write(8) 991 __fwtable_write(16) 992 __fwtable_write(32) 993 __gen8_write(8) 994 __gen8_write(16) 995 __gen8_write(32) 996 __gen6_write(8) 997 __gen6_write(16) 998 __gen6_write(32) 999 1000 #undef __fwtable_write 1001 #undef __gen8_write 1002 #undef __gen6_write 1003 #undef GEN6_WRITE_FOOTER 1004 #undef GEN6_WRITE_HEADER 1005 1006 #define ASSIGN_WRITE_MMIO_VFUNCS(i915, x) \ 1007 do { \ 1008 (i915)->uncore.funcs.mmio_writeb = x##_write8; \ 1009 (i915)->uncore.funcs.mmio_writew = x##_write16; \ 1010 (i915)->uncore.funcs.mmio_writel = x##_write32; \ 1011 } while (0) 1012 1013 #define ASSIGN_READ_MMIO_VFUNCS(i915, x) \ 1014 do { \ 1015 (i915)->uncore.funcs.mmio_readb = x##_read8; \ 1016 (i915)->uncore.funcs.mmio_readw = x##_read16; \ 1017 (i915)->uncore.funcs.mmio_readl = x##_read32; \ 1018 (i915)->uncore.funcs.mmio_readq = x##_read64; \ 1019 } while (0) 1020 1021 1022 static void fw_domain_init(struct drm_i915_private *dev_priv, 1023 enum forcewake_domain_id domain_id, 1024 i915_reg_t reg_set, 1025 i915_reg_t reg_ack) 1026 { 1027 struct intel_uncore_forcewake_domain *d; 1028 1029 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) 1030 return; 1031 1032 d = &dev_priv->uncore.fw_domain[domain_id]; 1033 1034 WARN_ON(d->wake_count); 1035 1036 WARN_ON(!i915_mmio_reg_valid(reg_set)); 1037 WARN_ON(!i915_mmio_reg_valid(reg_ack)); 1038 1039 d->wake_count = 0; 1040 d->reg_set = reg_set; 1041 d->reg_ack = reg_ack; 1042 1043 d->id = domain_id; 1044 1045 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 1046 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); 1047 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 1048 1049 d->mask = BIT(domain_id); 1050 1051 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1052 d->timer.function = intel_uncore_fw_release_timer; 1053 1054 dev_priv->uncore.fw_domains |= BIT(domain_id); 1055 1056 fw_domain_reset(dev_priv, d); 1057 } 1058 1059 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) 1060 { 1061 if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) 1062 return; 1063 1064 if (IS_GEN6(dev_priv)) { 1065 dev_priv->uncore.fw_reset = 0; 1066 dev_priv->uncore.fw_set = FORCEWAKE_KERNEL; 1067 dev_priv->uncore.fw_clear = 0; 1068 } else { 1069 /* WaRsClearFWBitsAtReset:bdw,skl */ 1070 dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff); 1071 dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); 1072 dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); 1073 } 1074 1075 if (INTEL_GEN(dev_priv) >= 9) { 1076 dev_priv->uncore.funcs.force_wake_get = fw_domains_get; 1077 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1078 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1079 FORCEWAKE_RENDER_GEN9, 1080 FORCEWAKE_ACK_RENDER_GEN9); 1081 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, 1082 FORCEWAKE_BLITTER_GEN9, 1083 FORCEWAKE_ACK_BLITTER_GEN9); 1084 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, 1085 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 1086 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1087 dev_priv->uncore.funcs.force_wake_get = fw_domains_get; 1088 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1089 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1090 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 1091 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, 1092 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 1093 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1094 dev_priv->uncore.funcs.force_wake_get = 1095 fw_domains_get_with_thread_status; 1096 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1097 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1098 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 1099 } else if (IS_IVYBRIDGE(dev_priv)) { 1100 u32 ecobus; 1101 1102 /* IVB configs may use multi-threaded forcewake */ 1103 1104 /* A small trick here - if the bios hasn't configured 1105 * MT forcewake, and if the device is in RC6, then 1106 * force_wake_mt_get will not wake the device and the 1107 * ECOBUS read will return zero. Which will be 1108 * (correctly) interpreted by the test below as MT 1109 * forcewake being disabled. 1110 */ 1111 dev_priv->uncore.funcs.force_wake_get = 1112 fw_domains_get_with_thread_status; 1113 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1114 1115 /* We need to init first for ECOBUS access and then 1116 * determine later if we want to reinit, in case of MT access is 1117 * not working. In this stage we don't know which flavour this 1118 * ivb is, so it is better to reset also the gen6 fw registers 1119 * before the ecobus check. 1120 */ 1121 1122 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 1123 __raw_posting_read(dev_priv, ECOBUS); 1124 1125 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1126 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 1127 1128 spin_lock_irq(&dev_priv->uncore.lock); 1129 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_RENDER); 1130 ecobus = __raw_i915_read32(dev_priv, ECOBUS); 1131 fw_domains_put(dev_priv, FORCEWAKE_RENDER); 1132 spin_unlock_irq(&dev_priv->uncore.lock); 1133 1134 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 1135 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); 1136 DRM_INFO("when using vblank-synced partial screen updates.\n"); 1137 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1138 FORCEWAKE, FORCEWAKE_ACK); 1139 } 1140 } else if (IS_GEN6(dev_priv)) { 1141 dev_priv->uncore.funcs.force_wake_get = 1142 fw_domains_get_with_thread_status; 1143 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1144 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1145 FORCEWAKE, FORCEWAKE_ACK); 1146 } 1147 1148 /* All future platforms are expected to require complex power gating */ 1149 WARN_ON(dev_priv->uncore.fw_domains == 0); 1150 } 1151 1152 #define ASSIGN_FW_DOMAINS_TABLE(d) \ 1153 { \ 1154 dev_priv->uncore.fw_domains_table = \ 1155 (struct intel_forcewake_range *)(d); \ 1156 dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \ 1157 } 1158 1159 static int i915_pmic_bus_access_notifier(struct notifier_block *nb, 1160 unsigned long action, void *data) 1161 { 1162 struct drm_i915_private *dev_priv = container_of(nb, 1163 struct drm_i915_private, uncore.pmic_bus_access_nb); 1164 1165 switch (action) { 1166 case MBI_PMIC_BUS_ACCESS_BEGIN: 1167 /* 1168 * forcewake all now to make sure that we don't need to do a 1169 * forcewake later which on systems where this notifier gets 1170 * called requires the punit to access to the shared pmic i2c 1171 * bus, which will be busy after this notification, leading to: 1172 * "render: timed out waiting for forcewake ack request." 1173 * errors. 1174 */ 1175 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1176 break; 1177 case MBI_PMIC_BUS_ACCESS_END: 1178 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1179 break; 1180 } 1181 1182 return NOTIFY_OK; 1183 } 1184 1185 void intel_uncore_init(struct drm_i915_private *dev_priv) 1186 { 1187 i915_check_vgpu(dev_priv); 1188 1189 intel_uncore_edram_detect(dev_priv); 1190 intel_uncore_fw_domains_init(dev_priv); 1191 __intel_uncore_early_sanitize(dev_priv, false); 1192 1193 dev_priv->uncore.unclaimed_mmio_check = 1; 1194 dev_priv->uncore.pmic_bus_access_nb.notifier_call = 1195 i915_pmic_bus_access_notifier; 1196 1197 if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { 1198 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); 1199 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); 1200 } else if (IS_GEN5(dev_priv)) { 1201 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); 1202 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); 1203 } else if (IS_GEN(dev_priv, 6, 7)) { 1204 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); 1205 1206 if (IS_VALLEYVIEW(dev_priv)) { 1207 ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges); 1208 ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); 1209 } else { 1210 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); 1211 } 1212 } else if (IS_GEN8(dev_priv)) { 1213 if (IS_CHERRYVIEW(dev_priv)) { 1214 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); 1215 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); 1216 ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); 1217 1218 } else { 1219 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); 1220 ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); 1221 } 1222 } else { 1223 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); 1224 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); 1225 ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); 1226 } 1227 1228 iosf_mbi_register_pmic_bus_access_notifier( 1229 &dev_priv->uncore.pmic_bus_access_nb); 1230 1231 i915_check_and_clear_faults(dev_priv); 1232 } 1233 1234 void intel_uncore_fini(struct drm_i915_private *dev_priv) 1235 { 1236 iosf_mbi_unregister_pmic_bus_access_notifier( 1237 &dev_priv->uncore.pmic_bus_access_nb); 1238 1239 /* Paranoia: make sure we have disabled everything before we exit. */ 1240 intel_uncore_sanitize(dev_priv); 1241 intel_uncore_forcewake_reset(dev_priv, false); 1242 } 1243 1244 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1) 1245 1246 static const struct register_whitelist { 1247 i915_reg_t offset_ldw, offset_udw; 1248 uint32_t size; 1249 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ 1250 uint32_t gen_bitmask; 1251 } whitelist[] = { 1252 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), 1253 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), 1254 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, 1255 }; 1256 1257 int i915_reg_read_ioctl(struct drm_device *dev, 1258 void *data, struct drm_file *file) 1259 { 1260 struct drm_i915_private *dev_priv = to_i915(dev); 1261 struct drm_i915_reg_read *reg = data; 1262 struct register_whitelist const *entry = whitelist; 1263 unsigned size; 1264 i915_reg_t offset_ldw, offset_udw; 1265 int i, ret = 0; 1266 1267 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { 1268 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && 1269 (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask)) 1270 break; 1271 } 1272 1273 if (i == ARRAY_SIZE(whitelist)) 1274 return -EINVAL; 1275 1276 /* We use the low bits to encode extra flags as the register should 1277 * be naturally aligned (and those that are not so aligned merely 1278 * limit the available flags for that register). 1279 */ 1280 offset_ldw = entry->offset_ldw; 1281 offset_udw = entry->offset_udw; 1282 size = entry->size; 1283 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); 1284 1285 intel_runtime_pm_get(dev_priv); 1286 1287 switch (size) { 1288 case 8 | 1: 1289 reg->val = I915_READ64_2x32(offset_ldw, offset_udw); 1290 break; 1291 case 8: 1292 reg->val = I915_READ64(offset_ldw); 1293 break; 1294 case 4: 1295 reg->val = I915_READ(offset_ldw); 1296 break; 1297 case 2: 1298 reg->val = I915_READ16(offset_ldw); 1299 break; 1300 case 1: 1301 reg->val = I915_READ8(offset_ldw); 1302 break; 1303 default: 1304 ret = -EINVAL; 1305 goto out; 1306 } 1307 1308 out: 1309 intel_runtime_pm_put(dev_priv); 1310 return ret; 1311 } 1312 1313 static void gen3_stop_rings(struct drm_i915_private *dev_priv) 1314 { 1315 struct intel_engine_cs *engine; 1316 enum intel_engine_id id; 1317 1318 for_each_engine(engine, dev_priv, id) { 1319 const u32 base = engine->mmio_base; 1320 const i915_reg_t mode = RING_MI_MODE(base); 1321 1322 I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING)); 1323 if (intel_wait_for_register_fw(dev_priv, 1324 mode, 1325 MODE_IDLE, 1326 MODE_IDLE, 1327 500)) 1328 DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n", 1329 engine->name); 1330 1331 I915_WRITE_FW(RING_CTL(base), 0); 1332 I915_WRITE_FW(RING_HEAD(base), 0); 1333 I915_WRITE_FW(RING_TAIL(base), 0); 1334 1335 /* Check acts as a post */ 1336 if (I915_READ_FW(RING_HEAD(base)) != 0) 1337 DRM_DEBUG_DRIVER("%s: ring head not parked\n", 1338 engine->name); 1339 } 1340 } 1341 1342 static bool i915_reset_complete(struct pci_dev *pdev) 1343 { 1344 u8 gdrst; 1345 1346 pci_read_config_byte(pdev, I915_GDRST, &gdrst); 1347 return (gdrst & GRDOM_RESET_STATUS) == 0; 1348 } 1349 1350 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1351 { 1352 struct pci_dev *pdev = dev_priv->drm.pdev; 1353 1354 /* assert reset for at least 20 usec */ 1355 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); 1356 usleep_range(50, 200); 1357 pci_write_config_byte(pdev, I915_GDRST, 0); 1358 1359 return wait_for(i915_reset_complete(pdev), 500); 1360 } 1361 1362 static bool g4x_reset_complete(struct pci_dev *pdev) 1363 { 1364 u8 gdrst; 1365 1366 pci_read_config_byte(pdev, I915_GDRST, &gdrst); 1367 return (gdrst & GRDOM_RESET_ENABLE) == 0; 1368 } 1369 1370 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1371 { 1372 struct pci_dev *pdev = dev_priv->drm.pdev; 1373 1374 /* Stop engines before we reset; see g4x_do_reset() below for why. */ 1375 gen3_stop_rings(dev_priv); 1376 1377 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); 1378 return wait_for(g4x_reset_complete(pdev), 500); 1379 } 1380 1381 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1382 { 1383 struct pci_dev *pdev = dev_priv->drm.pdev; 1384 int ret; 1385 1386 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1387 I915_WRITE(VDECCLK_GATE_D, 1388 I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); 1389 POSTING_READ(VDECCLK_GATE_D); 1390 1391 /* We stop engines, otherwise we might get failed reset and a 1392 * dead gpu (on elk). 1393 * WaMediaResetMainRingCleanup:ctg,elk (presumably) 1394 */ 1395 gen3_stop_rings(dev_priv); 1396 1397 pci_write_config_byte(pdev, I915_GDRST, 1398 GRDOM_MEDIA | GRDOM_RESET_ENABLE); 1399 ret = wait_for(g4x_reset_complete(pdev), 500); 1400 if (ret) { 1401 DRM_DEBUG_DRIVER("Wait for media reset failed\n"); 1402 goto out; 1403 } 1404 1405 pci_write_config_byte(pdev, I915_GDRST, 1406 GRDOM_RENDER | GRDOM_RESET_ENABLE); 1407 ret = wait_for(g4x_reset_complete(pdev), 500); 1408 if (ret) { 1409 DRM_DEBUG_DRIVER("Wait for render reset failed\n"); 1410 goto out; 1411 } 1412 1413 out: 1414 pci_write_config_byte(pdev, I915_GDRST, 0); 1415 1416 I915_WRITE(VDECCLK_GATE_D, 1417 I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); 1418 POSTING_READ(VDECCLK_GATE_D); 1419 1420 return ret; 1421 } 1422 1423 static int ironlake_do_reset(struct drm_i915_private *dev_priv, 1424 unsigned engine_mask) 1425 { 1426 int ret; 1427 1428 I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); 1429 ret = intel_wait_for_register(dev_priv, 1430 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, 1431 500); 1432 if (ret) { 1433 DRM_DEBUG_DRIVER("Wait for render reset failed\n"); 1434 goto out; 1435 } 1436 1437 I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); 1438 ret = intel_wait_for_register(dev_priv, 1439 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, 1440 500); 1441 if (ret) { 1442 DRM_DEBUG_DRIVER("Wait for media reset failed\n"); 1443 goto out; 1444 } 1445 1446 out: 1447 I915_WRITE(ILK_GDSR, 0); 1448 POSTING_READ(ILK_GDSR); 1449 return ret; 1450 } 1451 1452 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */ 1453 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, 1454 u32 hw_domain_mask) 1455 { 1456 int err; 1457 1458 /* GEN6_GDRST is not in the gt power well, no need to check 1459 * for fifo space for the write or forcewake the chip for 1460 * the read 1461 */ 1462 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); 1463 1464 /* Wait for the device to ack the reset requests */ 1465 err = intel_wait_for_register_fw(dev_priv, 1466 GEN6_GDRST, hw_domain_mask, 0, 1467 500); 1468 if (err) 1469 DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n", 1470 hw_domain_mask); 1471 1472 return err; 1473 } 1474 1475 /** 1476 * gen6_reset_engines - reset individual engines 1477 * @dev_priv: i915 device 1478 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset 1479 * 1480 * This function will reset the individual engines that are set in engine_mask. 1481 * If you provide ALL_ENGINES as mask, full global domain reset will be issued. 1482 * 1483 * Note: It is responsibility of the caller to handle the difference between 1484 * asking full domain reset versus reset for all available individual engines. 1485 * 1486 * Returns 0 on success, nonzero on error. 1487 */ 1488 static int gen6_reset_engines(struct drm_i915_private *dev_priv, 1489 unsigned engine_mask) 1490 { 1491 struct intel_engine_cs *engine; 1492 const u32 hw_engine_mask[I915_NUM_ENGINES] = { 1493 [RCS] = GEN6_GRDOM_RENDER, 1494 [BCS] = GEN6_GRDOM_BLT, 1495 [VCS] = GEN6_GRDOM_MEDIA, 1496 [VCS2] = GEN8_GRDOM_MEDIA2, 1497 [VECS] = GEN6_GRDOM_VECS, 1498 }; 1499 u32 hw_mask; 1500 1501 if (engine_mask == ALL_ENGINES) { 1502 hw_mask = GEN6_GRDOM_FULL; 1503 } else { 1504 unsigned int tmp; 1505 1506 hw_mask = 0; 1507 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) 1508 hw_mask |= hw_engine_mask[engine->id]; 1509 } 1510 1511 return gen6_hw_domain_reset(dev_priv, hw_mask); 1512 } 1513 1514 /** 1515 * __intel_wait_for_register_fw - wait until register matches expected state 1516 * @dev_priv: the i915 device 1517 * @reg: the register to read 1518 * @mask: mask to apply to register value 1519 * @value: expected value 1520 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 1521 * @slow_timeout_ms: slow timeout in millisecond 1522 * @out_value: optional placeholder to hold registry value 1523 * 1524 * This routine waits until the target register @reg contains the expected 1525 * @value after applying the @mask, i.e. it waits until :: 1526 * 1527 * (I915_READ_FW(reg) & mask) == value 1528 * 1529 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 1530 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 1531 * must be not larger than 20,0000 microseconds. 1532 * 1533 * Note that this routine assumes the caller holds forcewake asserted, it is 1534 * not suitable for very long waits. See intel_wait_for_register() if you 1535 * wish to wait without holding forcewake for the duration (i.e. you expect 1536 * the wait to be slow). 1537 * 1538 * Returns 0 if the register matches the desired condition, or -ETIMEOUT. 1539 */ 1540 int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv, 1541 i915_reg_t reg, 1542 u32 mask, 1543 u32 value, 1544 unsigned int fast_timeout_us, 1545 unsigned int slow_timeout_ms, 1546 u32 *out_value) 1547 { 1548 u32 uninitialized_var(reg_value); 1549 #define done (((reg_value = I915_READ_FW(reg)) & mask) == value) 1550 int ret; 1551 1552 /* Catch any overuse of this function */ 1553 might_sleep_if(slow_timeout_ms); 1554 GEM_BUG_ON(fast_timeout_us > 20000); 1555 1556 ret = -ETIMEDOUT; 1557 if (fast_timeout_us && fast_timeout_us <= 20000) 1558 ret = _wait_for_atomic(done, fast_timeout_us, 0); 1559 if (ret && slow_timeout_ms) 1560 ret = wait_for(done, slow_timeout_ms); 1561 1562 if (out_value) 1563 *out_value = reg_value; 1564 1565 return ret; 1566 #undef done 1567 } 1568 1569 /** 1570 * intel_wait_for_register - wait until register matches expected state 1571 * @dev_priv: the i915 device 1572 * @reg: the register to read 1573 * @mask: mask to apply to register value 1574 * @value: expected value 1575 * @timeout_ms: timeout in millisecond 1576 * 1577 * This routine waits until the target register @reg contains the expected 1578 * @value after applying the @mask, i.e. it waits until :: 1579 * 1580 * (I915_READ(reg) & mask) == value 1581 * 1582 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 1583 * 1584 * Returns 0 if the register matches the desired condition, or -ETIMEOUT. 1585 */ 1586 int intel_wait_for_register(struct drm_i915_private *dev_priv, 1587 i915_reg_t reg, 1588 u32 mask, 1589 u32 value, 1590 unsigned int timeout_ms) 1591 { 1592 unsigned fw = 1593 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ); 1594 int ret; 1595 1596 might_sleep(); 1597 1598 spin_lock_irq(&dev_priv->uncore.lock); 1599 intel_uncore_forcewake_get__locked(dev_priv, fw); 1600 1601 ret = __intel_wait_for_register_fw(dev_priv, 1602 reg, mask, value, 1603 2, 0, NULL); 1604 1605 intel_uncore_forcewake_put__locked(dev_priv, fw); 1606 spin_unlock_irq(&dev_priv->uncore.lock); 1607 1608 if (ret) 1609 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value, 1610 timeout_ms); 1611 1612 return ret; 1613 } 1614 1615 static int gen8_reset_engine_start(struct intel_engine_cs *engine) 1616 { 1617 struct drm_i915_private *dev_priv = engine->i915; 1618 int ret; 1619 1620 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), 1621 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); 1622 1623 ret = intel_wait_for_register_fw(dev_priv, 1624 RING_RESET_CTL(engine->mmio_base), 1625 RESET_CTL_READY_TO_RESET, 1626 RESET_CTL_READY_TO_RESET, 1627 700); 1628 if (ret) 1629 DRM_ERROR("%s: reset request timeout\n", engine->name); 1630 1631 return ret; 1632 } 1633 1634 static void gen8_reset_engine_cancel(struct intel_engine_cs *engine) 1635 { 1636 struct drm_i915_private *dev_priv = engine->i915; 1637 1638 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), 1639 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); 1640 } 1641 1642 static int gen8_reset_engines(struct drm_i915_private *dev_priv, 1643 unsigned engine_mask) 1644 { 1645 struct intel_engine_cs *engine; 1646 unsigned int tmp; 1647 1648 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) 1649 if (gen8_reset_engine_start(engine)) 1650 goto not_ready; 1651 1652 return gen6_reset_engines(dev_priv, engine_mask); 1653 1654 not_ready: 1655 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) 1656 gen8_reset_engine_cancel(engine); 1657 1658 return -EIO; 1659 } 1660 1661 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask); 1662 1663 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) 1664 { 1665 if (!i915.reset) 1666 return NULL; 1667 1668 if (INTEL_INFO(dev_priv)->gen >= 8) 1669 return gen8_reset_engines; 1670 else if (INTEL_INFO(dev_priv)->gen >= 6) 1671 return gen6_reset_engines; 1672 else if (IS_GEN5(dev_priv)) 1673 return ironlake_do_reset; 1674 else if (IS_G4X(dev_priv)) 1675 return g4x_do_reset; 1676 else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) 1677 return g33_do_reset; 1678 else if (INTEL_INFO(dev_priv)->gen >= 3) 1679 return i915_do_reset; 1680 else 1681 return NULL; 1682 } 1683 1684 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1685 { 1686 reset_func reset; 1687 int retry; 1688 int ret; 1689 1690 might_sleep(); 1691 1692 reset = intel_get_gpu_reset(dev_priv); 1693 if (reset == NULL) 1694 return -ENODEV; 1695 1696 /* If the power well sleeps during the reset, the reset 1697 * request may be dropped and never completes (causing -EIO). 1698 */ 1699 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1700 for (retry = 0; retry < 3; retry++) { 1701 ret = reset(dev_priv, engine_mask); 1702 if (ret != -ETIMEDOUT) 1703 break; 1704 1705 cond_resched(); 1706 } 1707 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1708 1709 return ret; 1710 } 1711 1712 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) 1713 { 1714 return intel_get_gpu_reset(dev_priv) != NULL; 1715 } 1716 1717 /* 1718 * When GuC submission is enabled, GuC manages ELSP and can initiate the 1719 * engine reset too. For now, fall back to full GPU reset if it is enabled. 1720 */ 1721 bool intel_has_reset_engine(struct drm_i915_private *dev_priv) 1722 { 1723 return (dev_priv->info.has_reset_engine && 1724 !dev_priv->guc.execbuf_client && 1725 i915.reset >= 2); 1726 } 1727 1728 int intel_guc_reset(struct drm_i915_private *dev_priv) 1729 { 1730 int ret; 1731 1732 if (!HAS_GUC(dev_priv)) 1733 return -EINVAL; 1734 1735 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1736 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC); 1737 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1738 1739 return ret; 1740 } 1741 1742 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) 1743 { 1744 return check_for_unclaimed_mmio(dev_priv); 1745 } 1746 1747 bool 1748 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) 1749 { 1750 if (unlikely(i915.mmio_debug || 1751 dev_priv->uncore.unclaimed_mmio_check <= 0)) 1752 return false; 1753 1754 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { 1755 DRM_DEBUG("Unclaimed register detected, " 1756 "enabling oneshot unclaimed register reporting. " 1757 "Please use i915.mmio_debug=N for more information.\n"); 1758 i915.mmio_debug++; 1759 dev_priv->uncore.unclaimed_mmio_check--; 1760 return true; 1761 } 1762 1763 return false; 1764 } 1765 1766 static enum forcewake_domains 1767 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, 1768 i915_reg_t reg) 1769 { 1770 u32 offset = i915_mmio_reg_offset(reg); 1771 enum forcewake_domains fw_domains; 1772 1773 if (HAS_FWTABLE(dev_priv)) { 1774 fw_domains = __fwtable_reg_read_fw_domains(offset); 1775 } else if (INTEL_GEN(dev_priv) >= 6) { 1776 fw_domains = __gen6_reg_read_fw_domains(offset); 1777 } else { 1778 WARN_ON(!IS_GEN(dev_priv, 2, 5)); 1779 fw_domains = 0; 1780 } 1781 1782 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); 1783 1784 return fw_domains; 1785 } 1786 1787 static enum forcewake_domains 1788 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, 1789 i915_reg_t reg) 1790 { 1791 u32 offset = i915_mmio_reg_offset(reg); 1792 enum forcewake_domains fw_domains; 1793 1794 if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { 1795 fw_domains = __fwtable_reg_write_fw_domains(offset); 1796 } else if (IS_GEN8(dev_priv)) { 1797 fw_domains = __gen8_reg_write_fw_domains(offset); 1798 } else if (IS_GEN(dev_priv, 6, 7)) { 1799 fw_domains = FORCEWAKE_RENDER; 1800 } else { 1801 WARN_ON(!IS_GEN(dev_priv, 2, 5)); 1802 fw_domains = 0; 1803 } 1804 1805 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); 1806 1807 return fw_domains; 1808 } 1809 1810 /** 1811 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 1812 * a register 1813 * @dev_priv: pointer to struct drm_i915_private 1814 * @reg: register in question 1815 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 1816 * 1817 * Returns a set of forcewake domains required to be taken with for example 1818 * intel_uncore_forcewake_get for the specified register to be accessible in the 1819 * specified mode (read, write or read/write) with raw mmio accessors. 1820 * 1821 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 1822 * callers to do FIFO management on their own or risk losing writes. 1823 */ 1824 enum forcewake_domains 1825 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, 1826 i915_reg_t reg, unsigned int op) 1827 { 1828 enum forcewake_domains fw_domains = 0; 1829 1830 WARN_ON(!op); 1831 1832 if (intel_vgpu_active(dev_priv)) 1833 return 0; 1834 1835 if (op & FW_REG_READ) 1836 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg); 1837 1838 if (op & FW_REG_WRITE) 1839 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg); 1840 1841 return fw_domains; 1842 } 1843 1844 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1845 #include "selftests/mock_uncore.c" 1846 #include "selftests/intel_uncore.c" 1847 #endif 1848