1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <linux/pm_runtime.h> 25 26 #include "gt/intel_engine_regs.h" 27 #include "gt/intel_gt_regs.h" 28 29 #include "i915_drv.h" 30 #include "i915_iosf_mbi.h" 31 #include "i915_reg.h" 32 #include "i915_trace.h" 33 #include "i915_vgpu.h" 34 #include "intel_pm.h" 35 36 #define FORCEWAKE_ACK_TIMEOUT_MS 50 37 #define GT_FIFO_TIMEOUT_MS 10 38 39 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) 40 41 static void 42 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 43 { 44 uncore->fw_get_funcs->force_wake_get(uncore, fw_domains); 45 } 46 47 void 48 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) 49 { 50 spin_lock_init(&mmio_debug->lock); 51 mmio_debug->unclaimed_mmio_check = 1; 52 } 53 54 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug) 55 { 56 lockdep_assert_held(&mmio_debug->lock); 57 58 /* Save and disable mmio debugging for the user bypass */ 59 if (!mmio_debug->suspend_count++) { 60 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check; 61 mmio_debug->unclaimed_mmio_check = 0; 62 } 63 } 64 65 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug) 66 { 67 lockdep_assert_held(&mmio_debug->lock); 68 69 if (!--mmio_debug->suspend_count) 70 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check; 71 } 72 73 static const char * const forcewake_domain_names[] = { 74 "render", 75 "gt", 76 "media", 77 "vdbox0", 78 "vdbox1", 79 "vdbox2", 80 "vdbox3", 81 "vdbox4", 82 "vdbox5", 83 "vdbox6", 84 "vdbox7", 85 "vebox0", 86 "vebox1", 87 "vebox2", 88 "vebox3", 89 }; 90 91 const char * 92 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 93 { 94 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 95 96 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 97 return forcewake_domain_names[id]; 98 99 WARN_ON(id); 100 101 return "unknown"; 102 } 103 104 #define fw_ack(d) readl((d)->reg_ack) 105 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) 106 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) 107 108 static inline void 109 fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 110 { 111 /* 112 * We don't really know if the powerwell for the forcewake domain we are 113 * trying to reset here does exist at this point (engines could be fused 114 * off in ICL+), so no waiting for acks 115 */ 116 /* WaRsClearFWBitsAtReset:bdw,skl */ 117 fw_clear(d, 0xffff); 118 } 119 120 static inline void 121 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 122 { 123 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); 124 d->uncore->fw_domains_timer |= d->mask; 125 d->wake_count++; 126 hrtimer_start_range_ns(&d->timer, 127 NSEC_PER_MSEC, 128 NSEC_PER_MSEC, 129 HRTIMER_MODE_REL); 130 } 131 132 static inline int 133 __wait_for_ack(const struct intel_uncore_forcewake_domain *d, 134 const u32 ack, 135 const u32 value) 136 { 137 return wait_for_atomic((fw_ack(d) & ack) == value, 138 FORCEWAKE_ACK_TIMEOUT_MS); 139 } 140 141 static inline int 142 wait_ack_clear(const struct intel_uncore_forcewake_domain *d, 143 const u32 ack) 144 { 145 return __wait_for_ack(d, ack, 0); 146 } 147 148 static inline int 149 wait_ack_set(const struct intel_uncore_forcewake_domain *d, 150 const u32 ack) 151 { 152 return __wait_for_ack(d, ack, ack); 153 } 154 155 static inline void 156 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 157 { 158 if (wait_ack_clear(d, FORCEWAKE_KERNEL)) { 159 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 160 intel_uncore_forcewake_domain_to_str(d->id)); 161 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 162 } 163 } 164 165 enum ack_type { 166 ACK_CLEAR = 0, 167 ACK_SET 168 }; 169 170 static int 171 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, 172 const enum ack_type type) 173 { 174 const u32 ack_bit = FORCEWAKE_KERNEL; 175 const u32 value = type == ACK_SET ? ack_bit : 0; 176 unsigned int pass; 177 bool ack_detected; 178 179 /* 180 * There is a possibility of driver's wake request colliding 181 * with hardware's own wake requests and that can cause 182 * hardware to not deliver the driver's ack message. 183 * 184 * Use a fallback bit toggle to kick the gpu state machine 185 * in the hope that the original ack will be delivered along with 186 * the fallback ack. 187 * 188 * This workaround is described in HSDES #1604254524 and it's known as: 189 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl 190 * although the name is a bit misleading. 191 */ 192 193 pass = 1; 194 do { 195 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); 196 197 fw_set(d, FORCEWAKE_KERNEL_FALLBACK); 198 /* Give gt some time to relax before the polling frenzy */ 199 udelay(10 * pass); 200 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); 201 202 ack_detected = (fw_ack(d) & ack_bit) == value; 203 204 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); 205 } while (!ack_detected && pass++ < 10); 206 207 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", 208 intel_uncore_forcewake_domain_to_str(d->id), 209 type == ACK_SET ? "set" : "clear", 210 fw_ack(d), 211 pass); 212 213 return ack_detected ? 0 : -ETIMEDOUT; 214 } 215 216 static inline void 217 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) 218 { 219 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) 220 return; 221 222 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) 223 fw_domain_wait_ack_clear(d); 224 } 225 226 static inline void 227 fw_domain_get(const struct intel_uncore_forcewake_domain *d) 228 { 229 fw_set(d, FORCEWAKE_KERNEL); 230 } 231 232 static inline void 233 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) 234 { 235 if (wait_ack_set(d, FORCEWAKE_KERNEL)) { 236 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 237 intel_uncore_forcewake_domain_to_str(d->id)); 238 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 239 } 240 } 241 242 static inline void 243 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) 244 { 245 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) 246 return; 247 248 if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) 249 fw_domain_wait_ack_set(d); 250 } 251 252 static inline void 253 fw_domain_put(const struct intel_uncore_forcewake_domain *d) 254 { 255 fw_clear(d, FORCEWAKE_KERNEL); 256 } 257 258 static void 259 fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 260 { 261 struct intel_uncore_forcewake_domain *d; 262 unsigned int tmp; 263 264 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 265 266 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 267 fw_domain_wait_ack_clear(d); 268 fw_domain_get(d); 269 } 270 271 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 272 fw_domain_wait_ack_set(d); 273 274 uncore->fw_domains_active |= fw_domains; 275 } 276 277 static void 278 fw_domains_get_with_fallback(struct intel_uncore *uncore, 279 enum forcewake_domains fw_domains) 280 { 281 struct intel_uncore_forcewake_domain *d; 282 unsigned int tmp; 283 284 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 285 286 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 287 fw_domain_wait_ack_clear_fallback(d); 288 fw_domain_get(d); 289 } 290 291 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 292 fw_domain_wait_ack_set_fallback(d); 293 294 uncore->fw_domains_active |= fw_domains; 295 } 296 297 static void 298 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 299 { 300 struct intel_uncore_forcewake_domain *d; 301 unsigned int tmp; 302 303 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 304 305 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 306 fw_domain_put(d); 307 308 uncore->fw_domains_active &= ~fw_domains; 309 } 310 311 static void 312 fw_domains_reset(struct intel_uncore *uncore, 313 enum forcewake_domains fw_domains) 314 { 315 struct intel_uncore_forcewake_domain *d; 316 unsigned int tmp; 317 318 if (!fw_domains) 319 return; 320 321 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 322 323 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 324 fw_domain_reset(d); 325 } 326 327 static inline u32 gt_thread_status(struct intel_uncore *uncore) 328 { 329 u32 val; 330 331 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); 332 val &= GEN6_GT_THREAD_STATUS_CORE_MASK; 333 334 return val; 335 } 336 337 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) 338 { 339 /* 340 * w/a for a sporadic read returning 0 by waiting for the GT 341 * thread to wake up. 342 */ 343 drm_WARN_ONCE(&uncore->i915->drm, 344 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), 345 "GT thread status wait timed out\n"); 346 } 347 348 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, 349 enum forcewake_domains fw_domains) 350 { 351 fw_domains_get_normal(uncore, fw_domains); 352 353 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 354 __gen6_gt_wait_for_thread_c0(uncore); 355 } 356 357 static inline u32 fifo_free_entries(struct intel_uncore *uncore) 358 { 359 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); 360 361 return count & GT_FIFO_FREE_ENTRIES_MASK; 362 } 363 364 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) 365 { 366 u32 n; 367 368 /* On VLV, FIFO will be shared by both SW and HW. 369 * So, we need to read the FREE_ENTRIES everytime */ 370 if (IS_VALLEYVIEW(uncore->i915)) 371 n = fifo_free_entries(uncore); 372 else 373 n = uncore->fifo_count; 374 375 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { 376 if (wait_for_atomic((n = fifo_free_entries(uncore)) > 377 GT_FIFO_NUM_RESERVED_ENTRIES, 378 GT_FIFO_TIMEOUT_MS)) { 379 drm_dbg(&uncore->i915->drm, 380 "GT_FIFO timeout, entries: %u\n", n); 381 return; 382 } 383 } 384 385 uncore->fifo_count = n - 1; 386 } 387 388 static enum hrtimer_restart 389 intel_uncore_fw_release_timer(struct hrtimer *timer) 390 { 391 struct intel_uncore_forcewake_domain *domain = 392 container_of(timer, struct intel_uncore_forcewake_domain, timer); 393 struct intel_uncore *uncore = domain->uncore; 394 unsigned long irqflags; 395 396 assert_rpm_device_not_suspended(uncore->rpm); 397 398 if (xchg(&domain->active, false)) 399 return HRTIMER_RESTART; 400 401 spin_lock_irqsave(&uncore->lock, irqflags); 402 403 uncore->fw_domains_timer &= ~domain->mask; 404 405 GEM_BUG_ON(!domain->wake_count); 406 if (--domain->wake_count == 0) 407 fw_domains_put(uncore, domain->mask); 408 409 spin_unlock_irqrestore(&uncore->lock, irqflags); 410 411 return HRTIMER_NORESTART; 412 } 413 414 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ 415 static unsigned int 416 intel_uncore_forcewake_reset(struct intel_uncore *uncore) 417 { 418 unsigned long irqflags; 419 struct intel_uncore_forcewake_domain *domain; 420 int retry_count = 100; 421 enum forcewake_domains fw, active_domains; 422 423 iosf_mbi_assert_punit_acquired(); 424 425 /* Hold uncore.lock across reset to prevent any register access 426 * with forcewake not set correctly. Wait until all pending 427 * timers are run before holding. 428 */ 429 while (1) { 430 unsigned int tmp; 431 432 active_domains = 0; 433 434 for_each_fw_domain(domain, uncore, tmp) { 435 smp_store_mb(domain->active, false); 436 if (hrtimer_cancel(&domain->timer) == 0) 437 continue; 438 439 intel_uncore_fw_release_timer(&domain->timer); 440 } 441 442 spin_lock_irqsave(&uncore->lock, irqflags); 443 444 for_each_fw_domain(domain, uncore, tmp) { 445 if (hrtimer_active(&domain->timer)) 446 active_domains |= domain->mask; 447 } 448 449 if (active_domains == 0) 450 break; 451 452 if (--retry_count == 0) { 453 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n"); 454 break; 455 } 456 457 spin_unlock_irqrestore(&uncore->lock, irqflags); 458 cond_resched(); 459 } 460 461 drm_WARN_ON(&uncore->i915->drm, active_domains); 462 463 fw = uncore->fw_domains_active; 464 if (fw) 465 fw_domains_put(uncore, fw); 466 467 fw_domains_reset(uncore, uncore->fw_domains); 468 assert_forcewakes_inactive(uncore); 469 470 spin_unlock_irqrestore(&uncore->lock, irqflags); 471 472 return fw; /* track the lost user forcewake domains */ 473 } 474 475 static bool 476 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) 477 { 478 u32 dbg; 479 480 dbg = __raw_uncore_read32(uncore, FPGA_DBG); 481 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 482 return false; 483 484 /* 485 * Bugs in PCI programming (or failing hardware) can occasionally cause 486 * us to lose access to the MMIO BAR. When this happens, register 487 * reads will come back with 0xFFFFFFFF for every register and things 488 * go bad very quickly. Let's try to detect that special case and at 489 * least try to print a more informative message about what has 490 * happened. 491 * 492 * During normal operation the FPGA_DBG register has several unused 493 * bits that will always read back as 0's so we can use them as canaries 494 * to recognize when MMIO accesses are just busted. 495 */ 496 if (unlikely(dbg == ~0)) 497 drm_err(&uncore->i915->drm, 498 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n"); 499 500 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 501 502 return true; 503 } 504 505 static bool 506 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) 507 { 508 u32 cer; 509 510 cer = __raw_uncore_read32(uncore, CLAIM_ER); 511 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 512 return false; 513 514 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); 515 516 return true; 517 } 518 519 static bool 520 gen6_check_for_fifo_debug(struct intel_uncore *uncore) 521 { 522 u32 fifodbg; 523 524 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); 525 526 if (unlikely(fifodbg)) { 527 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); 528 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); 529 } 530 531 return fifodbg; 532 } 533 534 static bool 535 check_for_unclaimed_mmio(struct intel_uncore *uncore) 536 { 537 bool ret = false; 538 539 lockdep_assert_held(&uncore->debug->lock); 540 541 if (uncore->debug->suspend_count) 542 return false; 543 544 if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) 545 ret |= fpga_check_for_unclaimed_mmio(uncore); 546 547 if (intel_uncore_has_dbg_unclaimed(uncore)) 548 ret |= vlv_check_for_unclaimed_mmio(uncore); 549 550 if (intel_uncore_has_fifo(uncore)) 551 ret |= gen6_check_for_fifo_debug(uncore); 552 553 return ret; 554 } 555 556 static void forcewake_early_sanitize(struct intel_uncore *uncore, 557 unsigned int restore_forcewake) 558 { 559 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 560 561 /* WaDisableShadowRegForCpd:chv */ 562 if (IS_CHERRYVIEW(uncore->i915)) { 563 __raw_uncore_write32(uncore, GTFIFOCTL, 564 __raw_uncore_read32(uncore, GTFIFOCTL) | 565 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 566 GT_FIFO_CTL_RC6_POLICY_STALL); 567 } 568 569 iosf_mbi_punit_acquire(); 570 intel_uncore_forcewake_reset(uncore); 571 if (restore_forcewake) { 572 spin_lock_irq(&uncore->lock); 573 fw_domains_get(uncore, restore_forcewake); 574 575 if (intel_uncore_has_fifo(uncore)) 576 uncore->fifo_count = fifo_free_entries(uncore); 577 spin_unlock_irq(&uncore->lock); 578 } 579 iosf_mbi_punit_release(); 580 } 581 582 void intel_uncore_suspend(struct intel_uncore *uncore) 583 { 584 if (!intel_uncore_has_forcewake(uncore)) 585 return; 586 587 iosf_mbi_punit_acquire(); 588 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 589 &uncore->pmic_bus_access_nb); 590 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); 591 iosf_mbi_punit_release(); 592 } 593 594 void intel_uncore_resume_early(struct intel_uncore *uncore) 595 { 596 unsigned int restore_forcewake; 597 598 if (intel_uncore_unclaimed_mmio(uncore)) 599 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n"); 600 601 if (!intel_uncore_has_forcewake(uncore)) 602 return; 603 604 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); 605 forcewake_early_sanitize(uncore, restore_forcewake); 606 607 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 608 } 609 610 void intel_uncore_runtime_resume(struct intel_uncore *uncore) 611 { 612 if (!intel_uncore_has_forcewake(uncore)) 613 return; 614 615 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 616 } 617 618 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, 619 enum forcewake_domains fw_domains) 620 { 621 struct intel_uncore_forcewake_domain *domain; 622 unsigned int tmp; 623 624 fw_domains &= uncore->fw_domains; 625 626 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 627 if (domain->wake_count++) { 628 fw_domains &= ~domain->mask; 629 domain->active = true; 630 } 631 } 632 633 if (fw_domains) 634 fw_domains_get(uncore, fw_domains); 635 } 636 637 /** 638 * intel_uncore_forcewake_get - grab forcewake domain references 639 * @uncore: the intel_uncore structure 640 * @fw_domains: forcewake domains to get reference on 641 * 642 * This function can be used get GT's forcewake domain references. 643 * Normal register access will handle the forcewake domains automatically. 644 * However if some sequence requires the GT to not power down a particular 645 * forcewake domains this function should be called at the beginning of the 646 * sequence. And subsequently the reference should be dropped by symmetric 647 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 648 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 649 */ 650 void intel_uncore_forcewake_get(struct intel_uncore *uncore, 651 enum forcewake_domains fw_domains) 652 { 653 unsigned long irqflags; 654 655 if (!uncore->fw_get_funcs) 656 return; 657 658 assert_rpm_wakelock_held(uncore->rpm); 659 660 spin_lock_irqsave(&uncore->lock, irqflags); 661 __intel_uncore_forcewake_get(uncore, fw_domains); 662 spin_unlock_irqrestore(&uncore->lock, irqflags); 663 } 664 665 /** 666 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace 667 * @uncore: the intel_uncore structure 668 * 669 * This function is a wrapper around intel_uncore_forcewake_get() to acquire 670 * the GT powerwell and in the process disable our debugging for the 671 * duration of userspace's bypass. 672 */ 673 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) 674 { 675 spin_lock_irq(&uncore->lock); 676 if (!uncore->user_forcewake_count++) { 677 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); 678 spin_lock(&uncore->debug->lock); 679 mmio_debug_suspend(uncore->debug); 680 spin_unlock(&uncore->debug->lock); 681 } 682 spin_unlock_irq(&uncore->lock); 683 } 684 685 /** 686 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace 687 * @uncore: the intel_uncore structure 688 * 689 * This function complements intel_uncore_forcewake_user_get() and releases 690 * the GT powerwell taken on behalf of the userspace bypass. 691 */ 692 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) 693 { 694 spin_lock_irq(&uncore->lock); 695 if (!--uncore->user_forcewake_count) { 696 spin_lock(&uncore->debug->lock); 697 mmio_debug_resume(uncore->debug); 698 699 if (check_for_unclaimed_mmio(uncore)) 700 drm_info(&uncore->i915->drm, 701 "Invalid mmio detected during user access\n"); 702 spin_unlock(&uncore->debug->lock); 703 704 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); 705 } 706 spin_unlock_irq(&uncore->lock); 707 } 708 709 /** 710 * intel_uncore_forcewake_get__locked - grab forcewake domain references 711 * @uncore: the intel_uncore structure 712 * @fw_domains: forcewake domains to get reference on 713 * 714 * See intel_uncore_forcewake_get(). This variant places the onus 715 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 716 */ 717 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 718 enum forcewake_domains fw_domains) 719 { 720 lockdep_assert_held(&uncore->lock); 721 722 if (!uncore->fw_get_funcs) 723 return; 724 725 __intel_uncore_forcewake_get(uncore, fw_domains); 726 } 727 728 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, 729 enum forcewake_domains fw_domains, 730 bool delayed) 731 { 732 struct intel_uncore_forcewake_domain *domain; 733 unsigned int tmp; 734 735 fw_domains &= uncore->fw_domains; 736 737 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 738 GEM_BUG_ON(!domain->wake_count); 739 740 if (--domain->wake_count) { 741 domain->active = true; 742 continue; 743 } 744 745 if (delayed && 746 !(domain->uncore->fw_domains_timer & domain->mask)) 747 fw_domain_arm_timer(domain); 748 else 749 fw_domains_put(uncore, domain->mask); 750 } 751 } 752 753 /** 754 * intel_uncore_forcewake_put - release a forcewake domain reference 755 * @uncore: the intel_uncore structure 756 * @fw_domains: forcewake domains to put references 757 * 758 * This function drops the device-level forcewakes for specified 759 * domains obtained by intel_uncore_forcewake_get(). 760 */ 761 void intel_uncore_forcewake_put(struct intel_uncore *uncore, 762 enum forcewake_domains fw_domains) 763 { 764 unsigned long irqflags; 765 766 if (!uncore->fw_get_funcs) 767 return; 768 769 spin_lock_irqsave(&uncore->lock, irqflags); 770 __intel_uncore_forcewake_put(uncore, fw_domains, false); 771 spin_unlock_irqrestore(&uncore->lock, irqflags); 772 } 773 774 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, 775 enum forcewake_domains fw_domains) 776 { 777 unsigned long irqflags; 778 779 if (!uncore->fw_get_funcs) 780 return; 781 782 spin_lock_irqsave(&uncore->lock, irqflags); 783 __intel_uncore_forcewake_put(uncore, fw_domains, true); 784 spin_unlock_irqrestore(&uncore->lock, irqflags); 785 } 786 787 /** 788 * intel_uncore_forcewake_flush - flush the delayed release 789 * @uncore: the intel_uncore structure 790 * @fw_domains: forcewake domains to flush 791 */ 792 void intel_uncore_forcewake_flush(struct intel_uncore *uncore, 793 enum forcewake_domains fw_domains) 794 { 795 struct intel_uncore_forcewake_domain *domain; 796 unsigned int tmp; 797 798 if (!uncore->fw_get_funcs) 799 return; 800 801 fw_domains &= uncore->fw_domains; 802 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 803 WRITE_ONCE(domain->active, false); 804 if (hrtimer_cancel(&domain->timer)) 805 intel_uncore_fw_release_timer(&domain->timer); 806 } 807 } 808 809 /** 810 * intel_uncore_forcewake_put__locked - grab forcewake domain references 811 * @uncore: the intel_uncore structure 812 * @fw_domains: forcewake domains to get reference on 813 * 814 * See intel_uncore_forcewake_put(). This variant places the onus 815 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 816 */ 817 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 818 enum forcewake_domains fw_domains) 819 { 820 lockdep_assert_held(&uncore->lock); 821 822 if (!uncore->fw_get_funcs) 823 return; 824 825 __intel_uncore_forcewake_put(uncore, fw_domains, false); 826 } 827 828 void assert_forcewakes_inactive(struct intel_uncore *uncore) 829 { 830 if (!uncore->fw_get_funcs) 831 return; 832 833 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active, 834 "Expected all fw_domains to be inactive, but %08x are still on\n", 835 uncore->fw_domains_active); 836 } 837 838 void assert_forcewakes_active(struct intel_uncore *uncore, 839 enum forcewake_domains fw_domains) 840 { 841 struct intel_uncore_forcewake_domain *domain; 842 unsigned int tmp; 843 844 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 845 return; 846 847 if (!uncore->fw_get_funcs) 848 return; 849 850 spin_lock_irq(&uncore->lock); 851 852 assert_rpm_wakelock_held(uncore->rpm); 853 854 fw_domains &= uncore->fw_domains; 855 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active, 856 "Expected %08x fw_domains to be active, but %08x are off\n", 857 fw_domains, fw_domains & ~uncore->fw_domains_active); 858 859 /* 860 * Check that the caller has an explicit wakeref and we don't mistake 861 * it for the auto wakeref. 862 */ 863 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 864 unsigned int actual = READ_ONCE(domain->wake_count); 865 unsigned int expect = 1; 866 867 if (uncore->fw_domains_timer & domain->mask) 868 expect++; /* pending automatic release */ 869 870 if (drm_WARN(&uncore->i915->drm, actual < expect, 871 "Expected domain %d to be held awake by caller, count=%d\n", 872 domain->id, actual)) 873 break; 874 } 875 876 spin_unlock_irq(&uncore->lock); 877 } 878 879 /* We give fast paths for the really cool registers */ 880 #define NEEDS_FORCE_WAKE(reg) ({ \ 881 u32 __reg = (reg); \ 882 __reg < 0x40000 || __reg >= GEN11_BSD_RING_BASE; \ 883 }) 884 885 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) 886 { 887 if (offset < entry->start) 888 return -1; 889 else if (offset > entry->end) 890 return 1; 891 else 892 return 0; 893 } 894 895 /* Copied and "macroized" from lib/bsearch.c */ 896 #define BSEARCH(key, base, num, cmp) ({ \ 897 unsigned int start__ = 0, end__ = (num); \ 898 typeof(base) result__ = NULL; \ 899 while (start__ < end__) { \ 900 unsigned int mid__ = start__ + (end__ - start__) / 2; \ 901 int ret__ = (cmp)((key), (base) + mid__); \ 902 if (ret__ < 0) { \ 903 end__ = mid__; \ 904 } else if (ret__ > 0) { \ 905 start__ = mid__ + 1; \ 906 } else { \ 907 result__ = (base) + mid__; \ 908 break; \ 909 } \ 910 } \ 911 result__; \ 912 }) 913 914 static enum forcewake_domains 915 find_fw_domain(struct intel_uncore *uncore, u32 offset) 916 { 917 const struct intel_forcewake_range *entry; 918 919 entry = BSEARCH(offset, 920 uncore->fw_domains_table, 921 uncore->fw_domains_table_entries, 922 fw_range_cmp); 923 924 if (!entry) 925 return 0; 926 927 /* 928 * The list of FW domains depends on the SKU in gen11+ so we 929 * can't determine it statically. We use FORCEWAKE_ALL and 930 * translate it here to the list of available domains. 931 */ 932 if (entry->domains == FORCEWAKE_ALL) 933 return uncore->fw_domains; 934 935 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains, 936 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", 937 entry->domains & ~uncore->fw_domains, offset); 938 939 return entry->domains; 940 } 941 942 /* 943 * Shadowed register tables describe special register ranges that i915 is 944 * allowed to write to without acquiring forcewake. If these registers' power 945 * wells are down, the hardware will save values written by i915 to a shadow 946 * copy and automatically transfer them into the real register the next time 947 * the power well is woken up. Shadowing only applies to writes; forcewake 948 * must still be acquired when reading from registers in these ranges. 949 * 950 * The documentation for shadowed registers is somewhat spotty on older 951 * platforms. However missing registers from these lists is non-fatal; it just 952 * means we'll wake up the hardware for some register accesses where we didn't 953 * really need to. 954 * 955 * The ranges listed in these tables must be sorted by offset. 956 * 957 * When adding new tables here, please also add them to 958 * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be 959 * scanned for obvious mistakes or typos by the selftests. 960 */ 961 962 static const struct i915_range gen8_shadowed_regs[] = { 963 { .start = 0x2030, .end = 0x2030 }, 964 { .start = 0xA008, .end = 0xA00C }, 965 { .start = 0x12030, .end = 0x12030 }, 966 { .start = 0x1a030, .end = 0x1a030 }, 967 { .start = 0x22030, .end = 0x22030 }, 968 }; 969 970 static const struct i915_range gen11_shadowed_regs[] = { 971 { .start = 0x2030, .end = 0x2030 }, 972 { .start = 0x2550, .end = 0x2550 }, 973 { .start = 0xA008, .end = 0xA00C }, 974 { .start = 0x22030, .end = 0x22030 }, 975 { .start = 0x22230, .end = 0x22230 }, 976 { .start = 0x22510, .end = 0x22550 }, 977 { .start = 0x1C0030, .end = 0x1C0030 }, 978 { .start = 0x1C0230, .end = 0x1C0230 }, 979 { .start = 0x1C0510, .end = 0x1C0550 }, 980 { .start = 0x1C4030, .end = 0x1C4030 }, 981 { .start = 0x1C4230, .end = 0x1C4230 }, 982 { .start = 0x1C4510, .end = 0x1C4550 }, 983 { .start = 0x1C8030, .end = 0x1C8030 }, 984 { .start = 0x1C8230, .end = 0x1C8230 }, 985 { .start = 0x1C8510, .end = 0x1C8550 }, 986 { .start = 0x1D0030, .end = 0x1D0030 }, 987 { .start = 0x1D0230, .end = 0x1D0230 }, 988 { .start = 0x1D0510, .end = 0x1D0550 }, 989 { .start = 0x1D4030, .end = 0x1D4030 }, 990 { .start = 0x1D4230, .end = 0x1D4230 }, 991 { .start = 0x1D4510, .end = 0x1D4550 }, 992 { .start = 0x1D8030, .end = 0x1D8030 }, 993 { .start = 0x1D8230, .end = 0x1D8230 }, 994 { .start = 0x1D8510, .end = 0x1D8550 }, 995 }; 996 997 static const struct i915_range gen12_shadowed_regs[] = { 998 { .start = 0x2030, .end = 0x2030 }, 999 { .start = 0x2510, .end = 0x2550 }, 1000 { .start = 0xA008, .end = 0xA00C }, 1001 { .start = 0xA188, .end = 0xA188 }, 1002 { .start = 0xA278, .end = 0xA278 }, 1003 { .start = 0xA540, .end = 0xA56C }, 1004 { .start = 0xC4C8, .end = 0xC4C8 }, 1005 { .start = 0xC4D4, .end = 0xC4D4 }, 1006 { .start = 0xC600, .end = 0xC600 }, 1007 { .start = 0x22030, .end = 0x22030 }, 1008 { .start = 0x22510, .end = 0x22550 }, 1009 { .start = 0x1C0030, .end = 0x1C0030 }, 1010 { .start = 0x1C0510, .end = 0x1C0550 }, 1011 { .start = 0x1C4030, .end = 0x1C4030 }, 1012 { .start = 0x1C4510, .end = 0x1C4550 }, 1013 { .start = 0x1C8030, .end = 0x1C8030 }, 1014 { .start = 0x1C8510, .end = 0x1C8550 }, 1015 { .start = 0x1D0030, .end = 0x1D0030 }, 1016 { .start = 0x1D0510, .end = 0x1D0550 }, 1017 { .start = 0x1D4030, .end = 0x1D4030 }, 1018 { .start = 0x1D4510, .end = 0x1D4550 }, 1019 { .start = 0x1D8030, .end = 0x1D8030 }, 1020 { .start = 0x1D8510, .end = 0x1D8550 }, 1021 1022 /* 1023 * The rest of these ranges are specific to Xe_HP and beyond, but 1024 * are reserved/unused ranges on earlier gen12 platforms, so they can 1025 * be safely added to the gen12 table. 1026 */ 1027 { .start = 0x1E0030, .end = 0x1E0030 }, 1028 { .start = 0x1E0510, .end = 0x1E0550 }, 1029 { .start = 0x1E4030, .end = 0x1E4030 }, 1030 { .start = 0x1E4510, .end = 0x1E4550 }, 1031 { .start = 0x1E8030, .end = 0x1E8030 }, 1032 { .start = 0x1E8510, .end = 0x1E8550 }, 1033 { .start = 0x1F0030, .end = 0x1F0030 }, 1034 { .start = 0x1F0510, .end = 0x1F0550 }, 1035 { .start = 0x1F4030, .end = 0x1F4030 }, 1036 { .start = 0x1F4510, .end = 0x1F4550 }, 1037 { .start = 0x1F8030, .end = 0x1F8030 }, 1038 { .start = 0x1F8510, .end = 0x1F8550 }, 1039 }; 1040 1041 static const struct i915_range dg2_shadowed_regs[] = { 1042 { .start = 0x2030, .end = 0x2030 }, 1043 { .start = 0x2510, .end = 0x2550 }, 1044 { .start = 0xA008, .end = 0xA00C }, 1045 { .start = 0xA188, .end = 0xA188 }, 1046 { .start = 0xA278, .end = 0xA278 }, 1047 { .start = 0xA540, .end = 0xA56C }, 1048 { .start = 0xC4C8, .end = 0xC4C8 }, 1049 { .start = 0xC4E0, .end = 0xC4E0 }, 1050 { .start = 0xC600, .end = 0xC600 }, 1051 { .start = 0xC658, .end = 0xC658 }, 1052 { .start = 0x22030, .end = 0x22030 }, 1053 { .start = 0x22510, .end = 0x22550 }, 1054 { .start = 0x1C0030, .end = 0x1C0030 }, 1055 { .start = 0x1C0510, .end = 0x1C0550 }, 1056 { .start = 0x1C4030, .end = 0x1C4030 }, 1057 { .start = 0x1C4510, .end = 0x1C4550 }, 1058 { .start = 0x1C8030, .end = 0x1C8030 }, 1059 { .start = 0x1C8510, .end = 0x1C8550 }, 1060 { .start = 0x1D0030, .end = 0x1D0030 }, 1061 { .start = 0x1D0510, .end = 0x1D0550 }, 1062 { .start = 0x1D4030, .end = 0x1D4030 }, 1063 { .start = 0x1D4510, .end = 0x1D4550 }, 1064 { .start = 0x1D8030, .end = 0x1D8030 }, 1065 { .start = 0x1D8510, .end = 0x1D8550 }, 1066 { .start = 0x1E0030, .end = 0x1E0030 }, 1067 { .start = 0x1E0510, .end = 0x1E0550 }, 1068 { .start = 0x1E4030, .end = 0x1E4030 }, 1069 { .start = 0x1E4510, .end = 0x1E4550 }, 1070 { .start = 0x1E8030, .end = 0x1E8030 }, 1071 { .start = 0x1E8510, .end = 0x1E8550 }, 1072 { .start = 0x1F0030, .end = 0x1F0030 }, 1073 { .start = 0x1F0510, .end = 0x1F0550 }, 1074 { .start = 0x1F4030, .end = 0x1F4030 }, 1075 { .start = 0x1F4510, .end = 0x1F4550 }, 1076 { .start = 0x1F8030, .end = 0x1F8030 }, 1077 { .start = 0x1F8510, .end = 0x1F8550 }, 1078 }; 1079 1080 static const struct i915_range pvc_shadowed_regs[] = { 1081 { .start = 0x2030, .end = 0x2030 }, 1082 { .start = 0x2510, .end = 0x2550 }, 1083 { .start = 0xA008, .end = 0xA00C }, 1084 { .start = 0xA188, .end = 0xA188 }, 1085 { .start = 0xA278, .end = 0xA278 }, 1086 { .start = 0xA540, .end = 0xA56C }, 1087 { .start = 0xC4C8, .end = 0xC4C8 }, 1088 { .start = 0xC4E0, .end = 0xC4E0 }, 1089 { .start = 0xC600, .end = 0xC600 }, 1090 { .start = 0xC658, .end = 0xC658 }, 1091 { .start = 0x22030, .end = 0x22030 }, 1092 { .start = 0x22510, .end = 0x22550 }, 1093 { .start = 0x1C0030, .end = 0x1C0030 }, 1094 { .start = 0x1C0510, .end = 0x1C0550 }, 1095 { .start = 0x1C4030, .end = 0x1C4030 }, 1096 { .start = 0x1C4510, .end = 0x1C4550 }, 1097 { .start = 0x1C8030, .end = 0x1C8030 }, 1098 { .start = 0x1C8510, .end = 0x1C8550 }, 1099 { .start = 0x1D0030, .end = 0x1D0030 }, 1100 { .start = 0x1D0510, .end = 0x1D0550 }, 1101 { .start = 0x1D4030, .end = 0x1D4030 }, 1102 { .start = 0x1D4510, .end = 0x1D4550 }, 1103 { .start = 0x1D8030, .end = 0x1D8030 }, 1104 { .start = 0x1D8510, .end = 0x1D8550 }, 1105 { .start = 0x1E0030, .end = 0x1E0030 }, 1106 { .start = 0x1E0510, .end = 0x1E0550 }, 1107 { .start = 0x1E4030, .end = 0x1E4030 }, 1108 { .start = 0x1E4510, .end = 0x1E4550 }, 1109 { .start = 0x1E8030, .end = 0x1E8030 }, 1110 { .start = 0x1E8510, .end = 0x1E8550 }, 1111 { .start = 0x1F0030, .end = 0x1F0030 }, 1112 { .start = 0x1F0510, .end = 0x1F0550 }, 1113 { .start = 0x1F4030, .end = 0x1F4030 }, 1114 { .start = 0x1F4510, .end = 0x1F4550 }, 1115 { .start = 0x1F8030, .end = 0x1F8030 }, 1116 { .start = 0x1F8510, .end = 0x1F8550 }, 1117 }; 1118 1119 static int mmio_range_cmp(u32 key, const struct i915_range *range) 1120 { 1121 if (key < range->start) 1122 return -1; 1123 else if (key > range->end) 1124 return 1; 1125 else 1126 return 0; 1127 } 1128 1129 static bool is_shadowed(struct intel_uncore *uncore, u32 offset) 1130 { 1131 if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table)) 1132 return false; 1133 1134 return BSEARCH(offset, 1135 uncore->shadowed_reg_table, 1136 uncore->shadowed_reg_table_entries, 1137 mmio_range_cmp); 1138 } 1139 1140 static enum forcewake_domains 1141 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 1142 { 1143 return FORCEWAKE_RENDER; 1144 } 1145 1146 #define __fwtable_reg_read_fw_domains(uncore, offset) \ 1147 ({ \ 1148 enum forcewake_domains __fwd = 0; \ 1149 if (NEEDS_FORCE_WAKE((offset))) \ 1150 __fwd = find_fw_domain(uncore, offset); \ 1151 __fwd; \ 1152 }) 1153 1154 #define __fwtable_reg_write_fw_domains(uncore, offset) \ 1155 ({ \ 1156 enum forcewake_domains __fwd = 0; \ 1157 const u32 __offset = (offset); \ 1158 if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \ 1159 __fwd = find_fw_domain(uncore, __offset); \ 1160 __fwd; \ 1161 }) 1162 1163 #define GEN_FW_RANGE(s, e, d) \ 1164 { .start = (s), .end = (e), .domains = (d) } 1165 1166 /* 1167 * All platforms' forcewake tables below must be sorted by offset ranges. 1168 * Furthermore, new forcewake tables added should be "watertight" and have 1169 * no gaps between ranges. 1170 * 1171 * When there are multiple consecutive ranges listed in the bspec with 1172 * the same forcewake domain, it is customary to combine them into a single 1173 * row in the tables below to keep the tables small and lookups fast. 1174 * Likewise, reserved/unused ranges may be combined with the preceding and/or 1175 * following ranges since the driver will never be making MMIO accesses in 1176 * those ranges. 1177 * 1178 * For example, if the bspec were to list: 1179 * 1180 * ... 1181 * 0x1000 - 0x1fff: GT 1182 * 0x2000 - 0x2cff: GT 1183 * 0x2d00 - 0x2fff: unused/reserved 1184 * 0x3000 - 0xffff: GT 1185 * ... 1186 * 1187 * these could all be represented by a single line in the code: 1188 * 1189 * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT) 1190 * 1191 * When adding new forcewake tables here, please also add them to 1192 * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be 1193 * scanned for obvious mistakes or typos by the selftests. 1194 */ 1195 1196 static const struct intel_forcewake_range __gen6_fw_ranges[] = { 1197 GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER), 1198 }; 1199 1200 static const struct intel_forcewake_range __vlv_fw_ranges[] = { 1201 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1202 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), 1203 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), 1204 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1205 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), 1206 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), 1207 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1208 }; 1209 1210 static const struct intel_forcewake_range __chv_fw_ranges[] = { 1211 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1212 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1213 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1214 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1215 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1216 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1217 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), 1218 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1219 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1220 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1221 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), 1222 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1223 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1224 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), 1225 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), 1226 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), 1227 }; 1228 1229 static const struct intel_forcewake_range __gen9_fw_ranges[] = { 1230 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), 1231 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ 1232 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1233 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1234 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1235 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1236 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1237 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), 1238 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), 1239 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1240 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1241 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1242 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1243 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), 1244 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), 1245 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1246 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), 1247 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1248 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1249 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1250 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), 1251 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1252 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), 1253 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), 1254 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), 1255 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1256 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), 1257 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), 1258 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), 1259 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), 1260 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), 1261 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1262 }; 1263 1264 static const struct intel_forcewake_range __gen11_fw_ranges[] = { 1265 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ 1266 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1267 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1268 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1269 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1270 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1271 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1272 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1273 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1274 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1275 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1276 GEN_FW_RANGE(0x8800, 0x8bff, 0), 1277 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1278 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), 1279 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1280 GEN_FW_RANGE(0x9560, 0x95ff, 0), 1281 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), 1282 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1283 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), 1284 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), 1285 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), 1286 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), 1287 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), 1288 GEN_FW_RANGE(0x24000, 0x2407f, 0), 1289 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), 1290 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), 1291 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), 1292 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), 1293 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), 1294 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1295 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), 1296 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1297 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0), 1298 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), 1299 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) 1300 }; 1301 1302 static const struct intel_forcewake_range __gen12_fw_ranges[] = { 1303 GEN_FW_RANGE(0x0, 0x1fff, 0), /* 1304 0x0 - 0xaff: reserved 1305 0xb00 - 0x1fff: always on */ 1306 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1307 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), 1308 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), 1309 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), 1310 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1311 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1312 0x4000 - 0x48ff: gt 1313 0x4900 - 0x51ff: reserved */ 1314 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1315 0x5200 - 0x53ff: render 1316 0x5400 - 0x54ff: reserved 1317 0x5500 - 0x7fff: render */ 1318 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1319 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1320 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 1321 0x8160 - 0x817f: reserved 1322 0x8180 - 0x81ff: always on */ 1323 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 1324 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1325 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* 1326 0x8500 - 0x87ff: gt 1327 0x8800 - 0x8fff: reserved 1328 0x9000 - 0x947f: gt 1329 0x9480 - 0x94cf: reserved */ 1330 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1331 GEN_FW_RANGE(0x9560, 0x97ff, 0), /* 1332 0x9560 - 0x95ff: always on 1333 0x9600 - 0x97ff: reserved */ 1334 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1335 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), 1336 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* 1337 0xb400 - 0xbf7f: gt 1338 0xb480 - 0xbfff: reserved 1339 0xc000 - 0xcfff: gt */ 1340 GEN_FW_RANGE(0xd000, 0xd7ff, 0), 1341 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), 1342 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), 1343 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* 1344 0xdc00 - 0xddff: render 1345 0xde00 - 0xde7f: reserved 1346 0xde80 - 0xe8ff: render 1347 0xe900 - 0xefff: reserved */ 1348 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* 1349 0xf000 - 0xffff: gt 1350 0x10000 - 0x147ff: reserved */ 1351 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* 1352 0x14800 - 0x14fff: render 1353 0x15000 - 0x16dff: reserved 1354 0x16e00 - 0x1bfff: render 1355 0x1c000 - 0x1ffff: reserved */ 1356 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), 1357 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), 1358 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1359 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1360 0x24000 - 0x2407f: always on 1361 0x24080 - 0x2417f: reserved */ 1362 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* 1363 0x24180 - 0x241ff: gt 1364 0x24200 - 0x249ff: reserved */ 1365 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* 1366 0x24a00 - 0x24a7f: render 1367 0x24a80 - 0x251ff: reserved */ 1368 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* 1369 0x25200 - 0x252ff: gt 1370 0x25300 - 0x255ff: reserved */ 1371 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), 1372 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* 1373 0x25680 - 0x256ff: VD2 1374 0x25700 - 0x259ff: reserved */ 1375 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), 1376 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1377 0x25a80 - 0x25aff: VD2 1378 0x25b00 - 0x2ffff: reserved */ 1379 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1380 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1381 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1382 0x1c0000 - 0x1c2bff: VD0 1383 0x1c2c00 - 0x1c2cff: reserved 1384 0x1c2d00 - 0x1c2dff: VD0 1385 0x1c2e00 - 0x1c3eff: reserved 1386 0x1c3f00 - 0x1c3fff: VD0 */ 1387 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1388 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1389 0x1c8000 - 0x1ca0ff: VE0 1390 0x1ca100 - 0x1cbeff: reserved 1391 0x1cbf00 - 0x1cbfff: VE0 */ 1392 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1393 0x1cc000 - 0x1ccfff: VD0 1394 0x1cd000 - 0x1cffff: reserved */ 1395 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* 1396 0x1d0000 - 0x1d2bff: VD2 1397 0x1d2c00 - 0x1d2cff: reserved 1398 0x1d2d00 - 0x1d2dff: VD2 1399 0x1d2e00 - 0x1d3eff: reserved 1400 0x1d3f00 - 0x1d3fff: VD2 */ 1401 }; 1402 1403 /* 1404 * Graphics IP version 12.55 brings a slight change to the 0xd800 range, 1405 * switching it from the GT domain to the render domain. 1406 */ 1407 #define XEHP_FWRANGES(FW_RANGE_D800) \ 1408 GEN_FW_RANGE(0x0, 0x1fff, 0), /* \ 1409 0x0 - 0xaff: reserved \ 1410 0xb00 - 0x1fff: always on */ \ 1411 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \ 1412 GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \ 1413 GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \ 1414 0x4b00 - 0x4fff: reserved \ 1415 0x5000 - 0x51ff: always on */ \ 1416 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \ 1417 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \ 1418 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \ 1419 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \ 1420 0x8160 - 0x817f: reserved \ 1421 0x8180 - 0x81ff: always on */ \ 1422 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \ 1423 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \ 1424 GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \ 1425 0x8500 - 0x87ff: gt \ 1426 0x8800 - 0x8c7f: reserved \ 1427 0x8c80 - 0x8cff: gt (DG2 only) */ \ 1428 GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \ 1429 0x8d00 - 0x8dff: render (DG2 only) \ 1430 0x8e00 - 0x8fff: reserved */ \ 1431 GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \ 1432 0x9000 - 0x947f: gt \ 1433 0x9480 - 0x94cf: reserved */ \ 1434 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \ 1435 GEN_FW_RANGE(0x9560, 0x967f, 0), /* \ 1436 0x9560 - 0x95ff: always on \ 1437 0x9600 - 0x967f: reserved */ \ 1438 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \ 1439 0x9680 - 0x96ff: render (DG2 only) \ 1440 0x9700 - 0x97ff: reserved */ \ 1441 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \ 1442 0x9800 - 0xb4ff: gt \ 1443 0xb500 - 0xbfff: reserved \ 1444 0xc000 - 0xcfff: gt */ \ 1445 GEN_FW_RANGE(0xd000, 0xd7ff, 0), \ 1446 GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \ 1447 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \ 1448 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \ 1449 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \ 1450 0xdd00 - 0xddff: gt \ 1451 0xde00 - 0xde7f: reserved */ \ 1452 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \ 1453 0xde80 - 0xdfff: render \ 1454 0xe000 - 0xe0ff: reserved \ 1455 0xe100 - 0xe8ff: render */ \ 1456 GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \ 1457 0xe900 - 0xe9ff: gt \ 1458 0xea00 - 0xefff: reserved \ 1459 0xf000 - 0xffff: gt */ \ 1460 GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \ 1461 0x10000 - 0x11fff: reserved \ 1462 0x12000 - 0x127ff: always on \ 1463 0x12800 - 0x12fff: reserved */ \ 1464 GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \ 1465 GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \ 1466 0x13200 - 0x133ff: VD2 (DG2 only) \ 1467 0x13400 - 0x13fff: reserved */ \ 1468 GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \ 1469 GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \ 1470 GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \ 1471 GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \ 1472 GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \ 1473 GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \ 1474 0x15000 - 0x15fff: gt (DG2 only) \ 1475 0x16000 - 0x16dff: reserved */ \ 1476 GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \ 1477 GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \ 1478 0x20000 - 0x20fff: VD0 (XEHPSDV only) \ 1479 0x21000 - 0x21fff: reserved */ \ 1480 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \ 1481 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \ 1482 0x24000 - 0x2407f: always on \ 1483 0x24080 - 0x2417f: reserved */ \ 1484 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \ 1485 0x24180 - 0x241ff: gt \ 1486 0x24200 - 0x249ff: reserved */ \ 1487 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \ 1488 0x24a00 - 0x24a7f: render \ 1489 0x24a80 - 0x251ff: reserved */ \ 1490 GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \ 1491 0x25200 - 0x252ff: gt \ 1492 0x25300 - 0x25fff: reserved */ \ 1493 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \ 1494 0x26000 - 0x27fff: render \ 1495 0x28000 - 0x29fff: reserved \ 1496 0x2a000 - 0x2ffff: undocumented */ \ 1497 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \ 1498 GEN_FW_RANGE(0x40000, 0x1bffff, 0), \ 1499 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \ 1500 0x1c0000 - 0x1c2bff: VD0 \ 1501 0x1c2c00 - 0x1c2cff: reserved \ 1502 0x1c2d00 - 0x1c2dff: VD0 \ 1503 0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \ 1504 0x1c3f00 - 0x1c3fff: VD0 */ \ 1505 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \ 1506 0x1c4000 - 0x1c6bff: VD1 \ 1507 0x1c6c00 - 0x1c6cff: reserved \ 1508 0x1c6d00 - 0x1c6dff: VD1 \ 1509 0x1c6e00 - 0x1c7fff: reserved */ \ 1510 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \ 1511 0x1c8000 - 0x1ca0ff: VE0 \ 1512 0x1ca100 - 0x1cbfff: reserved */ \ 1513 GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \ 1514 GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \ 1515 GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \ 1516 GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \ 1517 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \ 1518 0x1d0000 - 0x1d2bff: VD2 \ 1519 0x1d2c00 - 0x1d2cff: reserved \ 1520 0x1d2d00 - 0x1d2dff: VD2 \ 1521 0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \ 1522 0x1d3e00 - 0x1d3eff: reserved \ 1523 0x1d3f00 - 0x1d3fff: VD2 */ \ 1524 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \ 1525 0x1d4000 - 0x1d6bff: VD3 \ 1526 0x1d6c00 - 0x1d6cff: reserved \ 1527 0x1d6d00 - 0x1d6dff: VD3 \ 1528 0x1d6e00 - 0x1d7fff: reserved */ \ 1529 GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \ 1530 0x1d8000 - 0x1da0ff: VE1 \ 1531 0x1da100 - 0x1dffff: reserved */ \ 1532 GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \ 1533 0x1e0000 - 0x1e2bff: VD4 \ 1534 0x1e2c00 - 0x1e2cff: reserved \ 1535 0x1e2d00 - 0x1e2dff: VD4 \ 1536 0x1e2e00 - 0x1e3eff: reserved \ 1537 0x1e3f00 - 0x1e3fff: VD4 */ \ 1538 GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \ 1539 0x1e4000 - 0x1e6bff: VD5 \ 1540 0x1e6c00 - 0x1e6cff: reserved \ 1541 0x1e6d00 - 0x1e6dff: VD5 \ 1542 0x1e6e00 - 0x1e7fff: reserved */ \ 1543 GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \ 1544 0x1e8000 - 0x1ea0ff: VE2 \ 1545 0x1ea100 - 0x1effff: reserved */ \ 1546 GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \ 1547 0x1f0000 - 0x1f2bff: VD6 \ 1548 0x1f2c00 - 0x1f2cff: reserved \ 1549 0x1f2d00 - 0x1f2dff: VD6 \ 1550 0x1f2e00 - 0x1f3eff: reserved \ 1551 0x1f3f00 - 0x1f3fff: VD6 */ \ 1552 GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \ 1553 0x1f4000 - 0x1f6bff: VD7 \ 1554 0x1f6c00 - 0x1f6cff: reserved \ 1555 0x1f6d00 - 0x1f6dff: VD7 \ 1556 0x1f6e00 - 0x1f7fff: reserved */ \ 1557 GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3), 1558 1559 static const struct intel_forcewake_range __xehp_fw_ranges[] = { 1560 XEHP_FWRANGES(FORCEWAKE_GT) 1561 }; 1562 1563 static const struct intel_forcewake_range __dg2_fw_ranges[] = { 1564 XEHP_FWRANGES(FORCEWAKE_RENDER) 1565 }; 1566 1567 static const struct intel_forcewake_range __pvc_fw_ranges[] = { 1568 GEN_FW_RANGE(0x0, 0xaff, 0), 1569 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT), 1570 GEN_FW_RANGE(0xc00, 0xfff, 0), 1571 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT), 1572 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1573 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1574 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1575 GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /* 1576 0x4000 - 0x4aff: gt 1577 0x4b00 - 0x4fff: reserved 1578 0x5000 - 0x51ff: gt 1579 0x5200 - 0x52ff: reserved 1580 0x5300 - 0x53ff: gt 1581 0x5400 - 0x7fff: reserved 1582 0x8000 - 0x813f: gt */ 1583 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), 1584 GEN_FW_RANGE(0x8180, 0x81ff, 0), 1585 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /* 1586 0x8200 - 0x82ff: gt 1587 0x8300 - 0x84ff: reserved 1588 0x8500 - 0x887f: gt 1589 0x8880 - 0x8a7f: reserved 1590 0x8a80 - 0x8aff: gt 1591 0x8b00 - 0x8fff: reserved 1592 0x9000 - 0x947f: gt 1593 0x9480 - 0x94cf: reserved */ 1594 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1595 GEN_FW_RANGE(0x9560, 0x967f, 0), /* 1596 0x9560 - 0x95ff: always on 1597 0x9600 - 0x967f: reserved */ 1598 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* 1599 0x9680 - 0x96ff: render 1600 0x9700 - 0x97ff: reserved */ 1601 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* 1602 0x9800 - 0xb4ff: gt 1603 0xb500 - 0xbfff: reserved 1604 0xc000 - 0xcfff: gt */ 1605 GEN_FW_RANGE(0xd000, 0xd3ff, 0), 1606 GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT), 1607 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), 1608 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* 1609 0xdd00 - 0xddff: gt 1610 0xde00 - 0xde7f: reserved */ 1611 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* 1612 0xde80 - 0xdeff: render 1613 0xdf00 - 0xe1ff: reserved 1614 0xe200 - 0xe7ff: render 1615 0xe800 - 0xe8ff: reserved */ 1616 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /* 1617 0xe900 - 0xe9ff: gt 1618 0xea00 - 0xebff: reserved 1619 0xec00 - 0xffff: gt 1620 0x10000 - 0x11fff: reserved */ 1621 GEN_FW_RANGE(0x12000, 0x12fff, 0), /* 1622 0x12000 - 0x127ff: always on 1623 0x12800 - 0x12fff: reserved */ 1624 GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /* 1625 0x13000 - 0x135ff: gt 1626 0x13600 - 0x147ff: reserved 1627 0x14800 - 0x153ff: gt 1628 0x15400 - 0x19fff: reserved 1629 0x1a000 - 0x1ffff: gt 1630 0x20000 - 0x21fff: reserved 1631 0x22000 - 0x23fff: gt */ 1632 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1633 24000 - 0x2407f: always on 1634 24080 - 0x2417f: reserved */ 1635 GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /* 1636 0x24180 - 0x241ff: gt 1637 0x24200 - 0x251ff: reserved 1638 0x25200 - 0x252ff: gt 1639 0x25300 - 0x25fff: reserved 1640 0x26000 - 0x27fff: gt 1641 0x28000 - 0x2ffff: reserved 1642 0x30000 - 0x3ffff: gt */ 1643 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1644 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1645 0x1c0000 - 0x1c2bff: VD0 1646 0x1c2c00 - 0x1c2cff: reserved 1647 0x1c2d00 - 0x1c2dff: VD0 1648 0x1c2e00 - 0x1c3eff: reserved 1649 0x1c3f00 - 0x1c3fff: VD0 */ 1650 GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /* 1651 0x1c4000 - 0x1c6aff: VD1 1652 0x1c6b00 - 0x1c7eff: reserved 1653 0x1c7f00 - 0x1c7fff: VD1 1654 0x1c8000 - 0x1cffff: reserved */ 1655 GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1656 0x1d0000 - 0x1d2aff: VD2 1657 0x1d2b00 - 0x1d3eff: reserved 1658 0x1d3f00 - 0x1d3fff: VD2 1659 0x1d4000 - 0x23ffff: reserved */ 1660 GEN_FW_RANGE(0x240000, 0x3dffff, 0), 1661 GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT), 1662 }; 1663 1664 static void 1665 ilk_dummy_write(struct intel_uncore *uncore) 1666 { 1667 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 1668 * the chip from rc6 before touching it for real. MI_MODE is masked, 1669 * hence harmless to write 0 into. */ 1670 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); 1671 } 1672 1673 static void 1674 __unclaimed_reg_debug(struct intel_uncore *uncore, 1675 const i915_reg_t reg, 1676 const bool read) 1677 { 1678 if (drm_WARN(&uncore->i915->drm, 1679 check_for_unclaimed_mmio(uncore), 1680 "Unclaimed %s register 0x%x\n", 1681 read ? "read from" : "write to", 1682 i915_mmio_reg_offset(reg))) 1683 /* Only report the first N failures */ 1684 uncore->i915->params.mmio_debug--; 1685 } 1686 1687 static void 1688 __unclaimed_previous_reg_debug(struct intel_uncore *uncore, 1689 const i915_reg_t reg, 1690 const bool read) 1691 { 1692 if (check_for_unclaimed_mmio(uncore)) 1693 drm_dbg(&uncore->i915->drm, 1694 "Unclaimed access detected before %s register 0x%x\n", 1695 read ? "read from" : "write to", 1696 i915_mmio_reg_offset(reg)); 1697 } 1698 1699 static inline void 1700 unclaimed_reg_debug(struct intel_uncore *uncore, 1701 const i915_reg_t reg, 1702 const bool read, 1703 const bool before) 1704 { 1705 if (likely(!uncore->i915->params.mmio_debug)) 1706 return; 1707 1708 /* interrupts are disabled and re-enabled around uncore->lock usage */ 1709 lockdep_assert_held(&uncore->lock); 1710 1711 if (before) { 1712 spin_lock(&uncore->debug->lock); 1713 __unclaimed_previous_reg_debug(uncore, reg, read); 1714 } else { 1715 __unclaimed_reg_debug(uncore, reg, read); 1716 spin_unlock(&uncore->debug->lock); 1717 } 1718 } 1719 1720 #define __vgpu_read(x) \ 1721 static u##x \ 1722 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1723 u##x val = __raw_uncore_read##x(uncore, reg); \ 1724 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1725 return val; \ 1726 } 1727 __vgpu_read(8) 1728 __vgpu_read(16) 1729 __vgpu_read(32) 1730 __vgpu_read(64) 1731 1732 #define GEN2_READ_HEADER(x) \ 1733 u##x val = 0; \ 1734 assert_rpm_wakelock_held(uncore->rpm); 1735 1736 #define GEN2_READ_FOOTER \ 1737 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1738 return val 1739 1740 #define __gen2_read(x) \ 1741 static u##x \ 1742 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1743 GEN2_READ_HEADER(x); \ 1744 val = __raw_uncore_read##x(uncore, reg); \ 1745 GEN2_READ_FOOTER; \ 1746 } 1747 1748 #define __gen5_read(x) \ 1749 static u##x \ 1750 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1751 GEN2_READ_HEADER(x); \ 1752 ilk_dummy_write(uncore); \ 1753 val = __raw_uncore_read##x(uncore, reg); \ 1754 GEN2_READ_FOOTER; \ 1755 } 1756 1757 __gen5_read(8) 1758 __gen5_read(16) 1759 __gen5_read(32) 1760 __gen5_read(64) 1761 __gen2_read(8) 1762 __gen2_read(16) 1763 __gen2_read(32) 1764 __gen2_read(64) 1765 1766 #undef __gen5_read 1767 #undef __gen2_read 1768 1769 #undef GEN2_READ_FOOTER 1770 #undef GEN2_READ_HEADER 1771 1772 #define GEN6_READ_HEADER(x) \ 1773 u32 offset = i915_mmio_reg_offset(reg); \ 1774 unsigned long irqflags; \ 1775 u##x val = 0; \ 1776 assert_rpm_wakelock_held(uncore->rpm); \ 1777 spin_lock_irqsave(&uncore->lock, irqflags); \ 1778 unclaimed_reg_debug(uncore, reg, true, true) 1779 1780 #define GEN6_READ_FOOTER \ 1781 unclaimed_reg_debug(uncore, reg, true, false); \ 1782 spin_unlock_irqrestore(&uncore->lock, irqflags); \ 1783 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1784 return val 1785 1786 static noinline void ___force_wake_auto(struct intel_uncore *uncore, 1787 enum forcewake_domains fw_domains) 1788 { 1789 struct intel_uncore_forcewake_domain *domain; 1790 unsigned int tmp; 1791 1792 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 1793 1794 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) 1795 fw_domain_arm_timer(domain); 1796 1797 fw_domains_get(uncore, fw_domains); 1798 } 1799 1800 static inline void __force_wake_auto(struct intel_uncore *uncore, 1801 enum forcewake_domains fw_domains) 1802 { 1803 GEM_BUG_ON(!fw_domains); 1804 1805 /* Turn on all requested but inactive supported forcewake domains. */ 1806 fw_domains &= uncore->fw_domains; 1807 fw_domains &= ~uncore->fw_domains_active; 1808 1809 if (fw_domains) 1810 ___force_wake_auto(uncore, fw_domains); 1811 } 1812 1813 #define __gen_fwtable_read(x) \ 1814 static u##x \ 1815 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \ 1816 { \ 1817 enum forcewake_domains fw_engine; \ 1818 GEN6_READ_HEADER(x); \ 1819 fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \ 1820 if (fw_engine) \ 1821 __force_wake_auto(uncore, fw_engine); \ 1822 val = __raw_uncore_read##x(uncore, reg); \ 1823 GEN6_READ_FOOTER; \ 1824 } 1825 1826 static enum forcewake_domains 1827 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { 1828 return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); 1829 } 1830 1831 __gen_fwtable_read(8) 1832 __gen_fwtable_read(16) 1833 __gen_fwtable_read(32) 1834 __gen_fwtable_read(64) 1835 1836 #undef __gen_fwtable_read 1837 #undef GEN6_READ_FOOTER 1838 #undef GEN6_READ_HEADER 1839 1840 #define GEN2_WRITE_HEADER \ 1841 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1842 assert_rpm_wakelock_held(uncore->rpm); \ 1843 1844 #define GEN2_WRITE_FOOTER 1845 1846 #define __gen2_write(x) \ 1847 static void \ 1848 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1849 GEN2_WRITE_HEADER; \ 1850 __raw_uncore_write##x(uncore, reg, val); \ 1851 GEN2_WRITE_FOOTER; \ 1852 } 1853 1854 #define __gen5_write(x) \ 1855 static void \ 1856 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1857 GEN2_WRITE_HEADER; \ 1858 ilk_dummy_write(uncore); \ 1859 __raw_uncore_write##x(uncore, reg, val); \ 1860 GEN2_WRITE_FOOTER; \ 1861 } 1862 1863 __gen5_write(8) 1864 __gen5_write(16) 1865 __gen5_write(32) 1866 __gen2_write(8) 1867 __gen2_write(16) 1868 __gen2_write(32) 1869 1870 #undef __gen5_write 1871 #undef __gen2_write 1872 1873 #undef GEN2_WRITE_FOOTER 1874 #undef GEN2_WRITE_HEADER 1875 1876 #define GEN6_WRITE_HEADER \ 1877 u32 offset = i915_mmio_reg_offset(reg); \ 1878 unsigned long irqflags; \ 1879 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1880 assert_rpm_wakelock_held(uncore->rpm); \ 1881 spin_lock_irqsave(&uncore->lock, irqflags); \ 1882 unclaimed_reg_debug(uncore, reg, false, true) 1883 1884 #define GEN6_WRITE_FOOTER \ 1885 unclaimed_reg_debug(uncore, reg, false, false); \ 1886 spin_unlock_irqrestore(&uncore->lock, irqflags) 1887 1888 #define __gen6_write(x) \ 1889 static void \ 1890 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1891 GEN6_WRITE_HEADER; \ 1892 if (NEEDS_FORCE_WAKE(offset)) \ 1893 __gen6_gt_wait_for_fifo(uncore); \ 1894 __raw_uncore_write##x(uncore, reg, val); \ 1895 GEN6_WRITE_FOOTER; \ 1896 } 1897 __gen6_write(8) 1898 __gen6_write(16) 1899 __gen6_write(32) 1900 1901 #define __gen_fwtable_write(x) \ 1902 static void \ 1903 fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1904 enum forcewake_domains fw_engine; \ 1905 GEN6_WRITE_HEADER; \ 1906 fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \ 1907 if (fw_engine) \ 1908 __force_wake_auto(uncore, fw_engine); \ 1909 __raw_uncore_write##x(uncore, reg, val); \ 1910 GEN6_WRITE_FOOTER; \ 1911 } 1912 1913 static enum forcewake_domains 1914 fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 1915 { 1916 return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); 1917 } 1918 1919 __gen_fwtable_write(8) 1920 __gen_fwtable_write(16) 1921 __gen_fwtable_write(32) 1922 1923 #undef __gen_fwtable_write 1924 #undef GEN6_WRITE_FOOTER 1925 #undef GEN6_WRITE_HEADER 1926 1927 #define __vgpu_write(x) \ 1928 static void \ 1929 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1930 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1931 __raw_uncore_write##x(uncore, reg, val); \ 1932 } 1933 __vgpu_write(8) 1934 __vgpu_write(16) 1935 __vgpu_write(32) 1936 1937 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ 1938 do { \ 1939 (uncore)->funcs.mmio_writeb = x##_write8; \ 1940 (uncore)->funcs.mmio_writew = x##_write16; \ 1941 (uncore)->funcs.mmio_writel = x##_write32; \ 1942 } while (0) 1943 1944 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ 1945 do { \ 1946 (uncore)->funcs.mmio_readb = x##_read8; \ 1947 (uncore)->funcs.mmio_readw = x##_read16; \ 1948 (uncore)->funcs.mmio_readl = x##_read32; \ 1949 (uncore)->funcs.mmio_readq = x##_read64; \ 1950 } while (0) 1951 1952 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ 1953 do { \ 1954 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ 1955 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ 1956 } while (0) 1957 1958 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ 1959 do { \ 1960 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ 1961 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ 1962 } while (0) 1963 1964 static int __fw_domain_init(struct intel_uncore *uncore, 1965 enum forcewake_domain_id domain_id, 1966 i915_reg_t reg_set, 1967 i915_reg_t reg_ack) 1968 { 1969 struct intel_uncore_forcewake_domain *d; 1970 1971 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 1972 GEM_BUG_ON(uncore->fw_domain[domain_id]); 1973 1974 if (i915_inject_probe_failure(uncore->i915)) 1975 return -ENOMEM; 1976 1977 d = kzalloc(sizeof(*d), GFP_KERNEL); 1978 if (!d) 1979 return -ENOMEM; 1980 1981 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); 1982 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack)); 1983 1984 d->uncore = uncore; 1985 d->wake_count = 0; 1986 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); 1987 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); 1988 1989 d->id = domain_id; 1990 1991 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 1992 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); 1993 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 1994 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); 1995 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); 1996 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); 1997 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); 1998 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4)); 1999 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5)); 2000 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6)); 2001 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7)); 2002 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); 2003 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); 2004 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2)); 2005 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3)); 2006 2007 d->mask = BIT(domain_id); 2008 2009 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2010 d->timer.function = intel_uncore_fw_release_timer; 2011 2012 uncore->fw_domains |= BIT(domain_id); 2013 2014 fw_domain_reset(d); 2015 2016 uncore->fw_domain[domain_id] = d; 2017 2018 return 0; 2019 } 2020 2021 static void fw_domain_fini(struct intel_uncore *uncore, 2022 enum forcewake_domain_id domain_id) 2023 { 2024 struct intel_uncore_forcewake_domain *d; 2025 2026 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 2027 2028 d = fetch_and_zero(&uncore->fw_domain[domain_id]); 2029 if (!d) 2030 return; 2031 2032 uncore->fw_domains &= ~BIT(domain_id); 2033 drm_WARN_ON(&uncore->i915->drm, d->wake_count); 2034 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer)); 2035 kfree(d); 2036 } 2037 2038 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) 2039 { 2040 struct intel_uncore_forcewake_domain *d; 2041 int tmp; 2042 2043 for_each_fw_domain(d, uncore, tmp) 2044 fw_domain_fini(uncore, d->id); 2045 } 2046 2047 static const struct intel_uncore_fw_get uncore_get_fallback = { 2048 .force_wake_get = fw_domains_get_with_fallback 2049 }; 2050 2051 static const struct intel_uncore_fw_get uncore_get_normal = { 2052 .force_wake_get = fw_domains_get_normal, 2053 }; 2054 2055 static const struct intel_uncore_fw_get uncore_get_thread_status = { 2056 .force_wake_get = fw_domains_get_with_thread_status 2057 }; 2058 2059 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) 2060 { 2061 struct drm_i915_private *i915 = uncore->i915; 2062 int ret = 0; 2063 2064 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2065 2066 #define fw_domain_init(uncore__, id__, set__, ack__) \ 2067 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) 2068 2069 if (GRAPHICS_VER(i915) >= 11) { 2070 /* we'll prune the domains of missing engines later */ 2071 intel_engine_mask_t emask = RUNTIME_INFO(i915)->platform_engine_mask; 2072 int i; 2073 2074 uncore->fw_get_funcs = &uncore_get_fallback; 2075 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2076 FORCEWAKE_RENDER_GEN9, 2077 FORCEWAKE_ACK_RENDER_GEN9); 2078 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2079 FORCEWAKE_GT_GEN9, 2080 FORCEWAKE_ACK_GT_GEN9); 2081 2082 for (i = 0; i < I915_MAX_VCS; i++) { 2083 if (!__HAS_ENGINE(emask, _VCS(i))) 2084 continue; 2085 2086 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, 2087 FORCEWAKE_MEDIA_VDBOX_GEN11(i), 2088 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); 2089 } 2090 for (i = 0; i < I915_MAX_VECS; i++) { 2091 if (!__HAS_ENGINE(emask, _VECS(i))) 2092 continue; 2093 2094 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, 2095 FORCEWAKE_MEDIA_VEBOX_GEN11(i), 2096 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); 2097 } 2098 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2099 uncore->fw_get_funcs = &uncore_get_fallback; 2100 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2101 FORCEWAKE_RENDER_GEN9, 2102 FORCEWAKE_ACK_RENDER_GEN9); 2103 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2104 FORCEWAKE_GT_GEN9, 2105 FORCEWAKE_ACK_GT_GEN9); 2106 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 2107 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 2108 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 2109 uncore->fw_get_funcs = &uncore_get_normal; 2110 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2111 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 2112 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 2113 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 2114 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2115 uncore->fw_get_funcs = &uncore_get_thread_status; 2116 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2117 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 2118 } else if (IS_IVYBRIDGE(i915)) { 2119 u32 ecobus; 2120 2121 /* IVB configs may use multi-threaded forcewake */ 2122 2123 /* A small trick here - if the bios hasn't configured 2124 * MT forcewake, and if the device is in RC6, then 2125 * force_wake_mt_get will not wake the device and the 2126 * ECOBUS read will return zero. Which will be 2127 * (correctly) interpreted by the test below as MT 2128 * forcewake being disabled. 2129 */ 2130 uncore->fw_get_funcs = &uncore_get_thread_status; 2131 2132 /* We need to init first for ECOBUS access and then 2133 * determine later if we want to reinit, in case of MT access is 2134 * not working. In this stage we don't know which flavour this 2135 * ivb is, so it is better to reset also the gen6 fw registers 2136 * before the ecobus check. 2137 */ 2138 2139 __raw_uncore_write32(uncore, FORCEWAKE, 0); 2140 __raw_posting_read(uncore, ECOBUS); 2141 2142 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2143 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 2144 if (ret) 2145 goto out; 2146 2147 spin_lock_irq(&uncore->lock); 2148 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); 2149 ecobus = __raw_uncore_read32(uncore, ECOBUS); 2150 fw_domains_put(uncore, FORCEWAKE_RENDER); 2151 spin_unlock_irq(&uncore->lock); 2152 2153 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 2154 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n"); 2155 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n"); 2156 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); 2157 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2158 FORCEWAKE, FORCEWAKE_ACK); 2159 } 2160 } else if (GRAPHICS_VER(i915) == 6) { 2161 uncore->fw_get_funcs = &uncore_get_thread_status; 2162 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2163 FORCEWAKE, FORCEWAKE_ACK); 2164 } 2165 2166 #undef fw_domain_init 2167 2168 /* All future platforms are expected to require complex power gating */ 2169 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); 2170 2171 out: 2172 if (ret) 2173 intel_uncore_fw_domains_fini(uncore); 2174 2175 return ret; 2176 } 2177 2178 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ 2179 { \ 2180 (uncore)->fw_domains_table = \ 2181 (struct intel_forcewake_range *)(d); \ 2182 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ 2183 } 2184 2185 #define ASSIGN_SHADOW_TABLE(uncore, d) \ 2186 { \ 2187 (uncore)->shadowed_reg_table = d; \ 2188 (uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \ 2189 } 2190 2191 static int i915_pmic_bus_access_notifier(struct notifier_block *nb, 2192 unsigned long action, void *data) 2193 { 2194 struct intel_uncore *uncore = container_of(nb, 2195 struct intel_uncore, pmic_bus_access_nb); 2196 2197 switch (action) { 2198 case MBI_PMIC_BUS_ACCESS_BEGIN: 2199 /* 2200 * forcewake all now to make sure that we don't need to do a 2201 * forcewake later which on systems where this notifier gets 2202 * called requires the punit to access to the shared pmic i2c 2203 * bus, which will be busy after this notification, leading to: 2204 * "render: timed out waiting for forcewake ack request." 2205 * errors. 2206 * 2207 * The notifier is unregistered during intel_runtime_suspend(), 2208 * so it's ok to access the HW here without holding a RPM 2209 * wake reference -> disable wakeref asserts for the time of 2210 * the access. 2211 */ 2212 disable_rpm_wakeref_asserts(uncore->rpm); 2213 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 2214 enable_rpm_wakeref_asserts(uncore->rpm); 2215 break; 2216 case MBI_PMIC_BUS_ACCESS_END: 2217 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 2218 break; 2219 } 2220 2221 return NOTIFY_OK; 2222 } 2223 2224 int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) 2225 { 2226 struct drm_i915_private *i915 = uncore->i915; 2227 int mmio_size; 2228 2229 /* 2230 * Before gen4, the registers and the GTT are behind different BARs. 2231 * However, from gen4 onwards, the registers and the GTT are shared 2232 * in the same BAR, so we want to restrict this ioremap from 2233 * clobbering the GTT which we want ioremap_wc instead. Fortunately, 2234 * the register BAR remains the same size for all the earlier 2235 * generations up to Ironlake. 2236 * For dgfx chips register range is expanded to 4MB. 2237 */ 2238 if (GRAPHICS_VER(i915) < 5) 2239 mmio_size = 512 * 1024; 2240 else if (IS_DGFX(i915)) 2241 mmio_size = 4 * 1024 * 1024; 2242 else 2243 mmio_size = 2 * 1024 * 1024; 2244 2245 uncore->regs = ioremap(phys_addr, mmio_size); 2246 if (uncore->regs == NULL) { 2247 drm_err(&i915->drm, "failed to map registers\n"); 2248 return -EIO; 2249 } 2250 2251 return 0; 2252 } 2253 2254 void intel_uncore_cleanup_mmio(struct intel_uncore *uncore) 2255 { 2256 iounmap(uncore->regs); 2257 } 2258 2259 void intel_uncore_init_early(struct intel_uncore *uncore, 2260 struct intel_gt *gt) 2261 { 2262 spin_lock_init(&uncore->lock); 2263 uncore->i915 = gt->i915; 2264 uncore->gt = gt; 2265 uncore->rpm = >->i915->runtime_pm; 2266 uncore->debug = >->i915->mmio_debug; 2267 } 2268 2269 static void uncore_raw_init(struct intel_uncore *uncore) 2270 { 2271 GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); 2272 2273 if (intel_vgpu_active(uncore->i915)) { 2274 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu); 2275 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu); 2276 } else if (GRAPHICS_VER(uncore->i915) == 5) { 2277 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); 2278 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); 2279 } else { 2280 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); 2281 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); 2282 } 2283 } 2284 2285 static int uncore_forcewake_init(struct intel_uncore *uncore) 2286 { 2287 struct drm_i915_private *i915 = uncore->i915; 2288 int ret; 2289 2290 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2291 2292 ret = intel_uncore_fw_domains_init(uncore); 2293 if (ret) 2294 return ret; 2295 forcewake_early_sanitize(uncore, 0); 2296 2297 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 2298 2299 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) { 2300 ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges); 2301 ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs); 2302 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2303 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 2304 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges); 2305 ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs); 2306 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2307 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 2308 ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges); 2309 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); 2310 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2311 } else if (GRAPHICS_VER(i915) >= 12) { 2312 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); 2313 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); 2314 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2315 } else if (GRAPHICS_VER(i915) == 11) { 2316 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); 2317 ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs); 2318 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2319 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2320 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); 2321 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2322 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2323 } else if (IS_CHERRYVIEW(i915)) { 2324 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); 2325 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2326 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2327 } else if (GRAPHICS_VER(i915) == 8) { 2328 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); 2329 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2330 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2331 } else if (IS_VALLEYVIEW(i915)) { 2332 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); 2333 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2334 } else if (IS_GRAPHICS_VER(i915, 6, 7)) { 2335 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); 2336 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2337 } 2338 2339 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; 2340 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 2341 2342 return 0; 2343 } 2344 2345 int intel_uncore_init_mmio(struct intel_uncore *uncore) 2346 { 2347 struct drm_i915_private *i915 = uncore->i915; 2348 int ret; 2349 2350 /* 2351 * The boot firmware initializes local memory and assesses its health. 2352 * If memory training fails, the punit will have been instructed to 2353 * keep the GT powered down; we won't be able to communicate with it 2354 * and we should not continue with driver initialization. 2355 */ 2356 if (IS_DGFX(i915) && 2357 !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) { 2358 drm_err(&i915->drm, "LMEM not initialized by firmware\n"); 2359 return -ENODEV; 2360 } 2361 2362 if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915)) 2363 uncore->flags |= UNCORE_HAS_FORCEWAKE; 2364 2365 if (!intel_uncore_has_forcewake(uncore)) { 2366 uncore_raw_init(uncore); 2367 } else { 2368 ret = uncore_forcewake_init(uncore); 2369 if (ret) 2370 return ret; 2371 } 2372 2373 /* make sure fw funcs are set if and only if we have fw*/ 2374 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs); 2375 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); 2376 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); 2377 2378 if (HAS_FPGA_DBG_UNCLAIMED(i915)) 2379 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; 2380 2381 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 2382 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; 2383 2384 if (IS_GRAPHICS_VER(i915, 6, 7)) 2385 uncore->flags |= UNCORE_HAS_FIFO; 2386 2387 /* clear out unclaimed reg detection bit */ 2388 if (intel_uncore_unclaimed_mmio(uncore)) 2389 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n"); 2390 2391 return 0; 2392 } 2393 2394 /* 2395 * We might have detected that some engines are fused off after we initialized 2396 * the forcewake domains. Prune them, to make sure they only reference existing 2397 * engines. 2398 */ 2399 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, 2400 struct intel_gt *gt) 2401 { 2402 enum forcewake_domains fw_domains = uncore->fw_domains; 2403 enum forcewake_domain_id domain_id; 2404 int i; 2405 2406 if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11) 2407 return; 2408 2409 for (i = 0; i < I915_MAX_VCS; i++) { 2410 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; 2411 2412 if (HAS_ENGINE(gt, _VCS(i))) 2413 continue; 2414 2415 /* 2416 * Starting with XeHP, the power well for an even-numbered 2417 * VDBOX is also used for shared units within the 2418 * media slice such as SFC. So even if the engine 2419 * itself is fused off, we still need to initialize 2420 * the forcewake domain if any of the other engines 2421 * in the same media slice are present. 2422 */ 2423 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) { 2424 if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1))) 2425 continue; 2426 2427 if (HAS_ENGINE(gt, _VECS(i / 2))) 2428 continue; 2429 } 2430 2431 if (fw_domains & BIT(domain_id)) 2432 fw_domain_fini(uncore, domain_id); 2433 } 2434 2435 for (i = 0; i < I915_MAX_VECS; i++) { 2436 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; 2437 2438 if (HAS_ENGINE(gt, _VECS(i))) 2439 continue; 2440 2441 if (fw_domains & BIT(domain_id)) 2442 fw_domain_fini(uncore, domain_id); 2443 } 2444 } 2445 2446 void intel_uncore_fini_mmio(struct intel_uncore *uncore) 2447 { 2448 if (intel_uncore_has_forcewake(uncore)) { 2449 iosf_mbi_punit_acquire(); 2450 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 2451 &uncore->pmic_bus_access_nb); 2452 intel_uncore_forcewake_reset(uncore); 2453 intel_uncore_fw_domains_fini(uncore); 2454 iosf_mbi_punit_release(); 2455 } 2456 } 2457 2458 /** 2459 * __intel_wait_for_register_fw - wait until register matches expected state 2460 * @uncore: the struct intel_uncore 2461 * @reg: the register to read 2462 * @mask: mask to apply to register value 2463 * @value: expected value 2464 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2465 * @slow_timeout_ms: slow timeout in millisecond 2466 * @out_value: optional placeholder to hold registry value 2467 * 2468 * This routine waits until the target register @reg contains the expected 2469 * @value after applying the @mask, i.e. it waits until :: 2470 * 2471 * (intel_uncore_read_fw(uncore, reg) & mask) == value 2472 * 2473 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 2474 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 2475 * must be not larger than 20,0000 microseconds. 2476 * 2477 * Note that this routine assumes the caller holds forcewake asserted, it is 2478 * not suitable for very long waits. See intel_wait_for_register() if you 2479 * wish to wait without holding forcewake for the duration (i.e. you expect 2480 * the wait to be slow). 2481 * 2482 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2483 */ 2484 int __intel_wait_for_register_fw(struct intel_uncore *uncore, 2485 i915_reg_t reg, 2486 u32 mask, 2487 u32 value, 2488 unsigned int fast_timeout_us, 2489 unsigned int slow_timeout_ms, 2490 u32 *out_value) 2491 { 2492 u32 reg_value = 0; 2493 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) 2494 int ret; 2495 2496 /* Catch any overuse of this function */ 2497 might_sleep_if(slow_timeout_ms); 2498 GEM_BUG_ON(fast_timeout_us > 20000); 2499 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms); 2500 2501 ret = -ETIMEDOUT; 2502 if (fast_timeout_us && fast_timeout_us <= 20000) 2503 ret = _wait_for_atomic(done, fast_timeout_us, 0); 2504 if (ret && slow_timeout_ms) 2505 ret = wait_for(done, slow_timeout_ms); 2506 2507 if (out_value) 2508 *out_value = reg_value; 2509 2510 return ret; 2511 #undef done 2512 } 2513 2514 /** 2515 * __intel_wait_for_register - wait until register matches expected state 2516 * @uncore: the struct intel_uncore 2517 * @reg: the register to read 2518 * @mask: mask to apply to register value 2519 * @value: expected value 2520 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2521 * @slow_timeout_ms: slow timeout in millisecond 2522 * @out_value: optional placeholder to hold registry value 2523 * 2524 * This routine waits until the target register @reg contains the expected 2525 * @value after applying the @mask, i.e. it waits until :: 2526 * 2527 * (intel_uncore_read(uncore, reg) & mask) == value 2528 * 2529 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 2530 * 2531 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2532 */ 2533 int __intel_wait_for_register(struct intel_uncore *uncore, 2534 i915_reg_t reg, 2535 u32 mask, 2536 u32 value, 2537 unsigned int fast_timeout_us, 2538 unsigned int slow_timeout_ms, 2539 u32 *out_value) 2540 { 2541 unsigned fw = 2542 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 2543 u32 reg_value; 2544 int ret; 2545 2546 might_sleep_if(slow_timeout_ms); 2547 2548 spin_lock_irq(&uncore->lock); 2549 intel_uncore_forcewake_get__locked(uncore, fw); 2550 2551 ret = __intel_wait_for_register_fw(uncore, 2552 reg, mask, value, 2553 fast_timeout_us, 0, ®_value); 2554 2555 intel_uncore_forcewake_put__locked(uncore, fw); 2556 spin_unlock_irq(&uncore->lock); 2557 2558 if (ret && slow_timeout_ms) 2559 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, 2560 reg), 2561 (reg_value & mask) == value, 2562 slow_timeout_ms * 1000, 10, 1000); 2563 2564 /* just trace the final value */ 2565 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 2566 2567 if (out_value) 2568 *out_value = reg_value; 2569 2570 return ret; 2571 } 2572 2573 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) 2574 { 2575 bool ret; 2576 2577 spin_lock_irq(&uncore->debug->lock); 2578 ret = check_for_unclaimed_mmio(uncore); 2579 spin_unlock_irq(&uncore->debug->lock); 2580 2581 return ret; 2582 } 2583 2584 bool 2585 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) 2586 { 2587 bool ret = false; 2588 2589 spin_lock_irq(&uncore->debug->lock); 2590 2591 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) 2592 goto out; 2593 2594 if (unlikely(check_for_unclaimed_mmio(uncore))) { 2595 if (!uncore->i915->params.mmio_debug) { 2596 drm_dbg(&uncore->i915->drm, 2597 "Unclaimed register detected, " 2598 "enabling oneshot unclaimed register reporting. " 2599 "Please use i915.mmio_debug=N for more information.\n"); 2600 uncore->i915->params.mmio_debug++; 2601 } 2602 uncore->debug->unclaimed_mmio_check--; 2603 ret = true; 2604 } 2605 2606 out: 2607 spin_unlock_irq(&uncore->debug->lock); 2608 2609 return ret; 2610 } 2611 2612 /** 2613 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 2614 * a register 2615 * @uncore: pointer to struct intel_uncore 2616 * @reg: register in question 2617 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 2618 * 2619 * Returns a set of forcewake domains required to be taken with for example 2620 * intel_uncore_forcewake_get for the specified register to be accessible in the 2621 * specified mode (read, write or read/write) with raw mmio accessors. 2622 * 2623 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 2624 * callers to do FIFO management on their own or risk losing writes. 2625 */ 2626 enum forcewake_domains 2627 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 2628 i915_reg_t reg, unsigned int op) 2629 { 2630 enum forcewake_domains fw_domains = 0; 2631 2632 drm_WARN_ON(&uncore->i915->drm, !op); 2633 2634 if (!intel_uncore_has_forcewake(uncore)) 2635 return 0; 2636 2637 if (op & FW_REG_READ) 2638 fw_domains = uncore->funcs.read_fw_domains(uncore, reg); 2639 2640 if (op & FW_REG_WRITE) 2641 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); 2642 2643 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains); 2644 2645 return fw_domains; 2646 } 2647 2648 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2649 #include "selftests/mock_uncore.c" 2650 #include "selftests/intel_uncore.c" 2651 #endif 2652