1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_managed.h> 25 #include <linux/pm_runtime.h> 26 27 #include "gt/intel_engine_regs.h" 28 #include "gt/intel_gt_regs.h" 29 30 #include "i915_drv.h" 31 #include "i915_iosf_mbi.h" 32 #include "i915_trace.h" 33 #include "i915_vgpu.h" 34 #include "intel_pm.h" 35 36 #define FORCEWAKE_ACK_TIMEOUT_MS 50 37 #define GT_FIFO_TIMEOUT_MS 10 38 39 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) 40 41 static void 42 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 43 { 44 uncore->fw_get_funcs->force_wake_get(uncore, fw_domains); 45 } 46 47 void 48 intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915) 49 { 50 spin_lock_init(&i915->mmio_debug.lock); 51 i915->mmio_debug.unclaimed_mmio_check = 1; 52 53 i915->uncore.debug = &i915->mmio_debug; 54 } 55 56 static void mmio_debug_suspend(struct intel_uncore *uncore) 57 { 58 if (!uncore->debug) 59 return; 60 61 spin_lock(&uncore->debug->lock); 62 63 /* Save and disable mmio debugging for the user bypass */ 64 if (!uncore->debug->suspend_count++) { 65 uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check; 66 uncore->debug->unclaimed_mmio_check = 0; 67 } 68 69 spin_unlock(&uncore->debug->lock); 70 } 71 72 static bool check_for_unclaimed_mmio(struct intel_uncore *uncore); 73 74 static void mmio_debug_resume(struct intel_uncore *uncore) 75 { 76 if (!uncore->debug) 77 return; 78 79 spin_lock(&uncore->debug->lock); 80 81 if (!--uncore->debug->suspend_count) 82 uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check; 83 84 if (check_for_unclaimed_mmio(uncore)) 85 drm_info(&uncore->i915->drm, 86 "Invalid mmio detected during user access\n"); 87 88 spin_unlock(&uncore->debug->lock); 89 } 90 91 static const char * const forcewake_domain_names[] = { 92 "render", 93 "gt", 94 "media", 95 "vdbox0", 96 "vdbox1", 97 "vdbox2", 98 "vdbox3", 99 "vdbox4", 100 "vdbox5", 101 "vdbox6", 102 "vdbox7", 103 "vebox0", 104 "vebox1", 105 "vebox2", 106 "vebox3", 107 "gsc", 108 }; 109 110 const char * 111 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 112 { 113 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 114 115 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 116 return forcewake_domain_names[id]; 117 118 WARN_ON(id); 119 120 return "unknown"; 121 } 122 123 #define fw_ack(d) readl((d)->reg_ack) 124 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) 125 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) 126 127 static inline void 128 fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 129 { 130 /* 131 * We don't really know if the powerwell for the forcewake domain we are 132 * trying to reset here does exist at this point (engines could be fused 133 * off in ICL+), so no waiting for acks 134 */ 135 /* WaRsClearFWBitsAtReset */ 136 if (GRAPHICS_VER(d->uncore->i915) >= 12) 137 fw_clear(d, 0xefff); 138 else 139 fw_clear(d, 0xffff); 140 } 141 142 static inline void 143 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 144 { 145 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); 146 d->uncore->fw_domains_timer |= d->mask; 147 d->wake_count++; 148 hrtimer_start_range_ns(&d->timer, 149 NSEC_PER_MSEC, 150 NSEC_PER_MSEC, 151 HRTIMER_MODE_REL); 152 } 153 154 static inline int 155 __wait_for_ack(const struct intel_uncore_forcewake_domain *d, 156 const u32 ack, 157 const u32 value) 158 { 159 return wait_for_atomic((fw_ack(d) & ack) == value, 160 FORCEWAKE_ACK_TIMEOUT_MS); 161 } 162 163 static inline int 164 wait_ack_clear(const struct intel_uncore_forcewake_domain *d, 165 const u32 ack) 166 { 167 return __wait_for_ack(d, ack, 0); 168 } 169 170 static inline int 171 wait_ack_set(const struct intel_uncore_forcewake_domain *d, 172 const u32 ack) 173 { 174 return __wait_for_ack(d, ack, ack); 175 } 176 177 static inline void 178 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 179 { 180 if (wait_ack_clear(d, FORCEWAKE_KERNEL)) { 181 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 182 intel_uncore_forcewake_domain_to_str(d->id)); 183 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 184 } 185 } 186 187 enum ack_type { 188 ACK_CLEAR = 0, 189 ACK_SET 190 }; 191 192 static int 193 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, 194 const enum ack_type type) 195 { 196 const u32 ack_bit = FORCEWAKE_KERNEL; 197 const u32 value = type == ACK_SET ? ack_bit : 0; 198 unsigned int pass; 199 bool ack_detected; 200 201 /* 202 * There is a possibility of driver's wake request colliding 203 * with hardware's own wake requests and that can cause 204 * hardware to not deliver the driver's ack message. 205 * 206 * Use a fallback bit toggle to kick the gpu state machine 207 * in the hope that the original ack will be delivered along with 208 * the fallback ack. 209 * 210 * This workaround is described in HSDES #1604254524 and it's known as: 211 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl 212 * although the name is a bit misleading. 213 */ 214 215 pass = 1; 216 do { 217 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); 218 219 fw_set(d, FORCEWAKE_KERNEL_FALLBACK); 220 /* Give gt some time to relax before the polling frenzy */ 221 udelay(10 * pass); 222 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); 223 224 ack_detected = (fw_ack(d) & ack_bit) == value; 225 226 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); 227 } while (!ack_detected && pass++ < 10); 228 229 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", 230 intel_uncore_forcewake_domain_to_str(d->id), 231 type == ACK_SET ? "set" : "clear", 232 fw_ack(d), 233 pass); 234 235 return ack_detected ? 0 : -ETIMEDOUT; 236 } 237 238 static inline void 239 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) 240 { 241 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) 242 return; 243 244 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) 245 fw_domain_wait_ack_clear(d); 246 } 247 248 static inline void 249 fw_domain_get(const struct intel_uncore_forcewake_domain *d) 250 { 251 fw_set(d, FORCEWAKE_KERNEL); 252 } 253 254 static inline void 255 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) 256 { 257 if (wait_ack_set(d, FORCEWAKE_KERNEL)) { 258 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 259 intel_uncore_forcewake_domain_to_str(d->id)); 260 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 261 } 262 } 263 264 static inline void 265 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) 266 { 267 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) 268 return; 269 270 if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) 271 fw_domain_wait_ack_set(d); 272 } 273 274 static inline void 275 fw_domain_put(const struct intel_uncore_forcewake_domain *d) 276 { 277 fw_clear(d, FORCEWAKE_KERNEL); 278 } 279 280 static void 281 fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 282 { 283 struct intel_uncore_forcewake_domain *d; 284 unsigned int tmp; 285 286 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 287 288 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 289 fw_domain_wait_ack_clear(d); 290 fw_domain_get(d); 291 } 292 293 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 294 fw_domain_wait_ack_set(d); 295 296 uncore->fw_domains_active |= fw_domains; 297 } 298 299 static void 300 fw_domains_get_with_fallback(struct intel_uncore *uncore, 301 enum forcewake_domains fw_domains) 302 { 303 struct intel_uncore_forcewake_domain *d; 304 unsigned int tmp; 305 306 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 307 308 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 309 fw_domain_wait_ack_clear_fallback(d); 310 fw_domain_get(d); 311 } 312 313 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 314 fw_domain_wait_ack_set_fallback(d); 315 316 uncore->fw_domains_active |= fw_domains; 317 } 318 319 static void 320 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 321 { 322 struct intel_uncore_forcewake_domain *d; 323 unsigned int tmp; 324 325 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 326 327 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 328 fw_domain_put(d); 329 330 uncore->fw_domains_active &= ~fw_domains; 331 } 332 333 static void 334 fw_domains_reset(struct intel_uncore *uncore, 335 enum forcewake_domains fw_domains) 336 { 337 struct intel_uncore_forcewake_domain *d; 338 unsigned int tmp; 339 340 if (!fw_domains) 341 return; 342 343 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 344 345 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 346 fw_domain_reset(d); 347 } 348 349 static inline u32 gt_thread_status(struct intel_uncore *uncore) 350 { 351 u32 val; 352 353 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); 354 val &= GEN6_GT_THREAD_STATUS_CORE_MASK; 355 356 return val; 357 } 358 359 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) 360 { 361 /* 362 * w/a for a sporadic read returning 0 by waiting for the GT 363 * thread to wake up. 364 */ 365 drm_WARN_ONCE(&uncore->i915->drm, 366 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), 367 "GT thread status wait timed out\n"); 368 } 369 370 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, 371 enum forcewake_domains fw_domains) 372 { 373 fw_domains_get_normal(uncore, fw_domains); 374 375 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 376 __gen6_gt_wait_for_thread_c0(uncore); 377 } 378 379 static inline u32 fifo_free_entries(struct intel_uncore *uncore) 380 { 381 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); 382 383 return count & GT_FIFO_FREE_ENTRIES_MASK; 384 } 385 386 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) 387 { 388 u32 n; 389 390 /* On VLV, FIFO will be shared by both SW and HW. 391 * So, we need to read the FREE_ENTRIES everytime */ 392 if (IS_VALLEYVIEW(uncore->i915)) 393 n = fifo_free_entries(uncore); 394 else 395 n = uncore->fifo_count; 396 397 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { 398 if (wait_for_atomic((n = fifo_free_entries(uncore)) > 399 GT_FIFO_NUM_RESERVED_ENTRIES, 400 GT_FIFO_TIMEOUT_MS)) { 401 drm_dbg(&uncore->i915->drm, 402 "GT_FIFO timeout, entries: %u\n", n); 403 return; 404 } 405 } 406 407 uncore->fifo_count = n - 1; 408 } 409 410 static enum hrtimer_restart 411 intel_uncore_fw_release_timer(struct hrtimer *timer) 412 { 413 struct intel_uncore_forcewake_domain *domain = 414 container_of(timer, struct intel_uncore_forcewake_domain, timer); 415 struct intel_uncore *uncore = domain->uncore; 416 unsigned long irqflags; 417 418 assert_rpm_device_not_suspended(uncore->rpm); 419 420 if (xchg(&domain->active, false)) 421 return HRTIMER_RESTART; 422 423 spin_lock_irqsave(&uncore->lock, irqflags); 424 425 uncore->fw_domains_timer &= ~domain->mask; 426 427 GEM_BUG_ON(!domain->wake_count); 428 if (--domain->wake_count == 0) 429 fw_domains_put(uncore, domain->mask); 430 431 spin_unlock_irqrestore(&uncore->lock, irqflags); 432 433 return HRTIMER_NORESTART; 434 } 435 436 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ 437 static unsigned int 438 intel_uncore_forcewake_reset(struct intel_uncore *uncore) 439 { 440 unsigned long irqflags; 441 struct intel_uncore_forcewake_domain *domain; 442 int retry_count = 100; 443 enum forcewake_domains fw, active_domains; 444 445 iosf_mbi_assert_punit_acquired(); 446 447 /* Hold uncore.lock across reset to prevent any register access 448 * with forcewake not set correctly. Wait until all pending 449 * timers are run before holding. 450 */ 451 while (1) { 452 unsigned int tmp; 453 454 active_domains = 0; 455 456 for_each_fw_domain(domain, uncore, tmp) { 457 smp_store_mb(domain->active, false); 458 if (hrtimer_cancel(&domain->timer) == 0) 459 continue; 460 461 intel_uncore_fw_release_timer(&domain->timer); 462 } 463 464 spin_lock_irqsave(&uncore->lock, irqflags); 465 466 for_each_fw_domain(domain, uncore, tmp) { 467 if (hrtimer_active(&domain->timer)) 468 active_domains |= domain->mask; 469 } 470 471 if (active_domains == 0) 472 break; 473 474 if (--retry_count == 0) { 475 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n"); 476 break; 477 } 478 479 spin_unlock_irqrestore(&uncore->lock, irqflags); 480 cond_resched(); 481 } 482 483 drm_WARN_ON(&uncore->i915->drm, active_domains); 484 485 fw = uncore->fw_domains_active; 486 if (fw) 487 fw_domains_put(uncore, fw); 488 489 fw_domains_reset(uncore, uncore->fw_domains); 490 assert_forcewakes_inactive(uncore); 491 492 spin_unlock_irqrestore(&uncore->lock, irqflags); 493 494 return fw; /* track the lost user forcewake domains */ 495 } 496 497 static bool 498 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) 499 { 500 u32 dbg; 501 502 dbg = __raw_uncore_read32(uncore, FPGA_DBG); 503 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 504 return false; 505 506 /* 507 * Bugs in PCI programming (or failing hardware) can occasionally cause 508 * us to lose access to the MMIO BAR. When this happens, register 509 * reads will come back with 0xFFFFFFFF for every register and things 510 * go bad very quickly. Let's try to detect that special case and at 511 * least try to print a more informative message about what has 512 * happened. 513 * 514 * During normal operation the FPGA_DBG register has several unused 515 * bits that will always read back as 0's so we can use them as canaries 516 * to recognize when MMIO accesses are just busted. 517 */ 518 if (unlikely(dbg == ~0)) 519 drm_err(&uncore->i915->drm, 520 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n"); 521 522 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 523 524 return true; 525 } 526 527 static bool 528 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) 529 { 530 u32 cer; 531 532 cer = __raw_uncore_read32(uncore, CLAIM_ER); 533 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 534 return false; 535 536 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); 537 538 return true; 539 } 540 541 static bool 542 gen6_check_for_fifo_debug(struct intel_uncore *uncore) 543 { 544 u32 fifodbg; 545 546 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); 547 548 if (unlikely(fifodbg)) { 549 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); 550 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); 551 } 552 553 return fifodbg; 554 } 555 556 static bool 557 check_for_unclaimed_mmio(struct intel_uncore *uncore) 558 { 559 bool ret = false; 560 561 lockdep_assert_held(&uncore->debug->lock); 562 563 if (uncore->debug->suspend_count) 564 return false; 565 566 if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) 567 ret |= fpga_check_for_unclaimed_mmio(uncore); 568 569 if (intel_uncore_has_dbg_unclaimed(uncore)) 570 ret |= vlv_check_for_unclaimed_mmio(uncore); 571 572 if (intel_uncore_has_fifo(uncore)) 573 ret |= gen6_check_for_fifo_debug(uncore); 574 575 return ret; 576 } 577 578 static void forcewake_early_sanitize(struct intel_uncore *uncore, 579 unsigned int restore_forcewake) 580 { 581 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 582 583 /* WaDisableShadowRegForCpd:chv */ 584 if (IS_CHERRYVIEW(uncore->i915)) { 585 __raw_uncore_write32(uncore, GTFIFOCTL, 586 __raw_uncore_read32(uncore, GTFIFOCTL) | 587 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 588 GT_FIFO_CTL_RC6_POLICY_STALL); 589 } 590 591 iosf_mbi_punit_acquire(); 592 intel_uncore_forcewake_reset(uncore); 593 if (restore_forcewake) { 594 spin_lock_irq(&uncore->lock); 595 fw_domains_get(uncore, restore_forcewake); 596 597 if (intel_uncore_has_fifo(uncore)) 598 uncore->fifo_count = fifo_free_entries(uncore); 599 spin_unlock_irq(&uncore->lock); 600 } 601 iosf_mbi_punit_release(); 602 } 603 604 void intel_uncore_suspend(struct intel_uncore *uncore) 605 { 606 if (!intel_uncore_has_forcewake(uncore)) 607 return; 608 609 iosf_mbi_punit_acquire(); 610 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 611 &uncore->pmic_bus_access_nb); 612 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); 613 iosf_mbi_punit_release(); 614 } 615 616 void intel_uncore_resume_early(struct intel_uncore *uncore) 617 { 618 unsigned int restore_forcewake; 619 620 if (intel_uncore_unclaimed_mmio(uncore)) 621 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n"); 622 623 if (!intel_uncore_has_forcewake(uncore)) 624 return; 625 626 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); 627 forcewake_early_sanitize(uncore, restore_forcewake); 628 629 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 630 } 631 632 void intel_uncore_runtime_resume(struct intel_uncore *uncore) 633 { 634 if (!intel_uncore_has_forcewake(uncore)) 635 return; 636 637 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 638 } 639 640 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, 641 enum forcewake_domains fw_domains) 642 { 643 struct intel_uncore_forcewake_domain *domain; 644 unsigned int tmp; 645 646 fw_domains &= uncore->fw_domains; 647 648 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 649 if (domain->wake_count++) { 650 fw_domains &= ~domain->mask; 651 domain->active = true; 652 } 653 } 654 655 if (fw_domains) 656 fw_domains_get(uncore, fw_domains); 657 } 658 659 /** 660 * intel_uncore_forcewake_get - grab forcewake domain references 661 * @uncore: the intel_uncore structure 662 * @fw_domains: forcewake domains to get reference on 663 * 664 * This function can be used get GT's forcewake domain references. 665 * Normal register access will handle the forcewake domains automatically. 666 * However if some sequence requires the GT to not power down a particular 667 * forcewake domains this function should be called at the beginning of the 668 * sequence. And subsequently the reference should be dropped by symmetric 669 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 670 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 671 */ 672 void intel_uncore_forcewake_get(struct intel_uncore *uncore, 673 enum forcewake_domains fw_domains) 674 { 675 unsigned long irqflags; 676 677 if (!uncore->fw_get_funcs) 678 return; 679 680 assert_rpm_wakelock_held(uncore->rpm); 681 682 spin_lock_irqsave(&uncore->lock, irqflags); 683 __intel_uncore_forcewake_get(uncore, fw_domains); 684 spin_unlock_irqrestore(&uncore->lock, irqflags); 685 } 686 687 /** 688 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace 689 * @uncore: the intel_uncore structure 690 * 691 * This function is a wrapper around intel_uncore_forcewake_get() to acquire 692 * the GT powerwell and in the process disable our debugging for the 693 * duration of userspace's bypass. 694 */ 695 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) 696 { 697 spin_lock_irq(&uncore->lock); 698 if (!uncore->user_forcewake_count++) { 699 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); 700 mmio_debug_suspend(uncore); 701 } 702 spin_unlock_irq(&uncore->lock); 703 } 704 705 /** 706 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace 707 * @uncore: the intel_uncore structure 708 * 709 * This function complements intel_uncore_forcewake_user_get() and releases 710 * the GT powerwell taken on behalf of the userspace bypass. 711 */ 712 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) 713 { 714 spin_lock_irq(&uncore->lock); 715 if (!--uncore->user_forcewake_count) { 716 mmio_debug_resume(uncore); 717 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); 718 } 719 spin_unlock_irq(&uncore->lock); 720 } 721 722 /** 723 * intel_uncore_forcewake_get__locked - grab forcewake domain references 724 * @uncore: the intel_uncore structure 725 * @fw_domains: forcewake domains to get reference on 726 * 727 * See intel_uncore_forcewake_get(). This variant places the onus 728 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 729 */ 730 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 731 enum forcewake_domains fw_domains) 732 { 733 lockdep_assert_held(&uncore->lock); 734 735 if (!uncore->fw_get_funcs) 736 return; 737 738 __intel_uncore_forcewake_get(uncore, fw_domains); 739 } 740 741 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, 742 enum forcewake_domains fw_domains, 743 bool delayed) 744 { 745 struct intel_uncore_forcewake_domain *domain; 746 unsigned int tmp; 747 748 fw_domains &= uncore->fw_domains; 749 750 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 751 GEM_BUG_ON(!domain->wake_count); 752 753 if (--domain->wake_count) { 754 domain->active = true; 755 continue; 756 } 757 758 if (delayed && 759 !(domain->uncore->fw_domains_timer & domain->mask)) 760 fw_domain_arm_timer(domain); 761 else 762 fw_domains_put(uncore, domain->mask); 763 } 764 } 765 766 /** 767 * intel_uncore_forcewake_put - release a forcewake domain reference 768 * @uncore: the intel_uncore structure 769 * @fw_domains: forcewake domains to put references 770 * 771 * This function drops the device-level forcewakes for specified 772 * domains obtained by intel_uncore_forcewake_get(). 773 */ 774 void intel_uncore_forcewake_put(struct intel_uncore *uncore, 775 enum forcewake_domains fw_domains) 776 { 777 unsigned long irqflags; 778 779 if (!uncore->fw_get_funcs) 780 return; 781 782 spin_lock_irqsave(&uncore->lock, irqflags); 783 __intel_uncore_forcewake_put(uncore, fw_domains, false); 784 spin_unlock_irqrestore(&uncore->lock, irqflags); 785 } 786 787 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, 788 enum forcewake_domains fw_domains) 789 { 790 unsigned long irqflags; 791 792 if (!uncore->fw_get_funcs) 793 return; 794 795 spin_lock_irqsave(&uncore->lock, irqflags); 796 __intel_uncore_forcewake_put(uncore, fw_domains, true); 797 spin_unlock_irqrestore(&uncore->lock, irqflags); 798 } 799 800 /** 801 * intel_uncore_forcewake_flush - flush the delayed release 802 * @uncore: the intel_uncore structure 803 * @fw_domains: forcewake domains to flush 804 */ 805 void intel_uncore_forcewake_flush(struct intel_uncore *uncore, 806 enum forcewake_domains fw_domains) 807 { 808 struct intel_uncore_forcewake_domain *domain; 809 unsigned int tmp; 810 811 if (!uncore->fw_get_funcs) 812 return; 813 814 fw_domains &= uncore->fw_domains; 815 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 816 WRITE_ONCE(domain->active, false); 817 if (hrtimer_cancel(&domain->timer)) 818 intel_uncore_fw_release_timer(&domain->timer); 819 } 820 } 821 822 /** 823 * intel_uncore_forcewake_put__locked - grab forcewake domain references 824 * @uncore: the intel_uncore structure 825 * @fw_domains: forcewake domains to get reference on 826 * 827 * See intel_uncore_forcewake_put(). This variant places the onus 828 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 829 */ 830 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 831 enum forcewake_domains fw_domains) 832 { 833 lockdep_assert_held(&uncore->lock); 834 835 if (!uncore->fw_get_funcs) 836 return; 837 838 __intel_uncore_forcewake_put(uncore, fw_domains, false); 839 } 840 841 void assert_forcewakes_inactive(struct intel_uncore *uncore) 842 { 843 if (!uncore->fw_get_funcs) 844 return; 845 846 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active, 847 "Expected all fw_domains to be inactive, but %08x are still on\n", 848 uncore->fw_domains_active); 849 } 850 851 void assert_forcewakes_active(struct intel_uncore *uncore, 852 enum forcewake_domains fw_domains) 853 { 854 struct intel_uncore_forcewake_domain *domain; 855 unsigned int tmp; 856 857 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 858 return; 859 860 if (!uncore->fw_get_funcs) 861 return; 862 863 spin_lock_irq(&uncore->lock); 864 865 assert_rpm_wakelock_held(uncore->rpm); 866 867 fw_domains &= uncore->fw_domains; 868 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active, 869 "Expected %08x fw_domains to be active, but %08x are off\n", 870 fw_domains, fw_domains & ~uncore->fw_domains_active); 871 872 /* 873 * Check that the caller has an explicit wakeref and we don't mistake 874 * it for the auto wakeref. 875 */ 876 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 877 unsigned int actual = READ_ONCE(domain->wake_count); 878 unsigned int expect = 1; 879 880 if (uncore->fw_domains_timer & domain->mask) 881 expect++; /* pending automatic release */ 882 883 if (drm_WARN(&uncore->i915->drm, actual < expect, 884 "Expected domain %d to be held awake by caller, count=%d\n", 885 domain->id, actual)) 886 break; 887 } 888 889 spin_unlock_irq(&uncore->lock); 890 } 891 892 /* 893 * We give fast paths for the really cool registers. The second range includes 894 * media domains (and the GSC starting from Xe_LPM+) 895 */ 896 #define NEEDS_FORCE_WAKE(reg) ({ \ 897 u32 __reg = (reg); \ 898 __reg < 0x40000 || __reg >= 0x116000; \ 899 }) 900 901 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) 902 { 903 if (offset < entry->start) 904 return -1; 905 else if (offset > entry->end) 906 return 1; 907 else 908 return 0; 909 } 910 911 /* Copied and "macroized" from lib/bsearch.c */ 912 #define BSEARCH(key, base, num, cmp) ({ \ 913 unsigned int start__ = 0, end__ = (num); \ 914 typeof(base) result__ = NULL; \ 915 while (start__ < end__) { \ 916 unsigned int mid__ = start__ + (end__ - start__) / 2; \ 917 int ret__ = (cmp)((key), (base) + mid__); \ 918 if (ret__ < 0) { \ 919 end__ = mid__; \ 920 } else if (ret__ > 0) { \ 921 start__ = mid__ + 1; \ 922 } else { \ 923 result__ = (base) + mid__; \ 924 break; \ 925 } \ 926 } \ 927 result__; \ 928 }) 929 930 static enum forcewake_domains 931 find_fw_domain(struct intel_uncore *uncore, u32 offset) 932 { 933 const struct intel_forcewake_range *entry; 934 935 if (IS_GSI_REG(offset)) 936 offset += uncore->gsi_offset; 937 938 entry = BSEARCH(offset, 939 uncore->fw_domains_table, 940 uncore->fw_domains_table_entries, 941 fw_range_cmp); 942 943 if (!entry) 944 return 0; 945 946 /* 947 * The list of FW domains depends on the SKU in gen11+ so we 948 * can't determine it statically. We use FORCEWAKE_ALL and 949 * translate it here to the list of available domains. 950 */ 951 if (entry->domains == FORCEWAKE_ALL) 952 return uncore->fw_domains; 953 954 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains, 955 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", 956 entry->domains & ~uncore->fw_domains, offset); 957 958 return entry->domains; 959 } 960 961 /* 962 * Shadowed register tables describe special register ranges that i915 is 963 * allowed to write to without acquiring forcewake. If these registers' power 964 * wells are down, the hardware will save values written by i915 to a shadow 965 * copy and automatically transfer them into the real register the next time 966 * the power well is woken up. Shadowing only applies to writes; forcewake 967 * must still be acquired when reading from registers in these ranges. 968 * 969 * The documentation for shadowed registers is somewhat spotty on older 970 * platforms. However missing registers from these lists is non-fatal; it just 971 * means we'll wake up the hardware for some register accesses where we didn't 972 * really need to. 973 * 974 * The ranges listed in these tables must be sorted by offset. 975 * 976 * When adding new tables here, please also add them to 977 * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be 978 * scanned for obvious mistakes or typos by the selftests. 979 */ 980 981 static const struct i915_range gen8_shadowed_regs[] = { 982 { .start = 0x2030, .end = 0x2030 }, 983 { .start = 0xA008, .end = 0xA00C }, 984 { .start = 0x12030, .end = 0x12030 }, 985 { .start = 0x1a030, .end = 0x1a030 }, 986 { .start = 0x22030, .end = 0x22030 }, 987 }; 988 989 static const struct i915_range gen11_shadowed_regs[] = { 990 { .start = 0x2030, .end = 0x2030 }, 991 { .start = 0x2550, .end = 0x2550 }, 992 { .start = 0xA008, .end = 0xA00C }, 993 { .start = 0x22030, .end = 0x22030 }, 994 { .start = 0x22230, .end = 0x22230 }, 995 { .start = 0x22510, .end = 0x22550 }, 996 { .start = 0x1C0030, .end = 0x1C0030 }, 997 { .start = 0x1C0230, .end = 0x1C0230 }, 998 { .start = 0x1C0510, .end = 0x1C0550 }, 999 { .start = 0x1C4030, .end = 0x1C4030 }, 1000 { .start = 0x1C4230, .end = 0x1C4230 }, 1001 { .start = 0x1C4510, .end = 0x1C4550 }, 1002 { .start = 0x1C8030, .end = 0x1C8030 }, 1003 { .start = 0x1C8230, .end = 0x1C8230 }, 1004 { .start = 0x1C8510, .end = 0x1C8550 }, 1005 { .start = 0x1D0030, .end = 0x1D0030 }, 1006 { .start = 0x1D0230, .end = 0x1D0230 }, 1007 { .start = 0x1D0510, .end = 0x1D0550 }, 1008 { .start = 0x1D4030, .end = 0x1D4030 }, 1009 { .start = 0x1D4230, .end = 0x1D4230 }, 1010 { .start = 0x1D4510, .end = 0x1D4550 }, 1011 { .start = 0x1D8030, .end = 0x1D8030 }, 1012 { .start = 0x1D8230, .end = 0x1D8230 }, 1013 { .start = 0x1D8510, .end = 0x1D8550 }, 1014 }; 1015 1016 static const struct i915_range gen12_shadowed_regs[] = { 1017 { .start = 0x2030, .end = 0x2030 }, 1018 { .start = 0x2510, .end = 0x2550 }, 1019 { .start = 0xA008, .end = 0xA00C }, 1020 { .start = 0xA188, .end = 0xA188 }, 1021 { .start = 0xA278, .end = 0xA278 }, 1022 { .start = 0xA540, .end = 0xA56C }, 1023 { .start = 0xC4C8, .end = 0xC4C8 }, 1024 { .start = 0xC4D4, .end = 0xC4D4 }, 1025 { .start = 0xC600, .end = 0xC600 }, 1026 { .start = 0x22030, .end = 0x22030 }, 1027 { .start = 0x22510, .end = 0x22550 }, 1028 { .start = 0x1C0030, .end = 0x1C0030 }, 1029 { .start = 0x1C0510, .end = 0x1C0550 }, 1030 { .start = 0x1C4030, .end = 0x1C4030 }, 1031 { .start = 0x1C4510, .end = 0x1C4550 }, 1032 { .start = 0x1C8030, .end = 0x1C8030 }, 1033 { .start = 0x1C8510, .end = 0x1C8550 }, 1034 { .start = 0x1D0030, .end = 0x1D0030 }, 1035 { .start = 0x1D0510, .end = 0x1D0550 }, 1036 { .start = 0x1D4030, .end = 0x1D4030 }, 1037 { .start = 0x1D4510, .end = 0x1D4550 }, 1038 { .start = 0x1D8030, .end = 0x1D8030 }, 1039 { .start = 0x1D8510, .end = 0x1D8550 }, 1040 1041 /* 1042 * The rest of these ranges are specific to Xe_HP and beyond, but 1043 * are reserved/unused ranges on earlier gen12 platforms, so they can 1044 * be safely added to the gen12 table. 1045 */ 1046 { .start = 0x1E0030, .end = 0x1E0030 }, 1047 { .start = 0x1E0510, .end = 0x1E0550 }, 1048 { .start = 0x1E4030, .end = 0x1E4030 }, 1049 { .start = 0x1E4510, .end = 0x1E4550 }, 1050 { .start = 0x1E8030, .end = 0x1E8030 }, 1051 { .start = 0x1E8510, .end = 0x1E8550 }, 1052 { .start = 0x1F0030, .end = 0x1F0030 }, 1053 { .start = 0x1F0510, .end = 0x1F0550 }, 1054 { .start = 0x1F4030, .end = 0x1F4030 }, 1055 { .start = 0x1F4510, .end = 0x1F4550 }, 1056 { .start = 0x1F8030, .end = 0x1F8030 }, 1057 { .start = 0x1F8510, .end = 0x1F8550 }, 1058 }; 1059 1060 static const struct i915_range dg2_shadowed_regs[] = { 1061 { .start = 0x2030, .end = 0x2030 }, 1062 { .start = 0x2510, .end = 0x2550 }, 1063 { .start = 0xA008, .end = 0xA00C }, 1064 { .start = 0xA188, .end = 0xA188 }, 1065 { .start = 0xA278, .end = 0xA278 }, 1066 { .start = 0xA540, .end = 0xA56C }, 1067 { .start = 0xC4C8, .end = 0xC4C8 }, 1068 { .start = 0xC4E0, .end = 0xC4E0 }, 1069 { .start = 0xC600, .end = 0xC600 }, 1070 { .start = 0xC658, .end = 0xC658 }, 1071 { .start = 0x22030, .end = 0x22030 }, 1072 { .start = 0x22510, .end = 0x22550 }, 1073 { .start = 0x1C0030, .end = 0x1C0030 }, 1074 { .start = 0x1C0510, .end = 0x1C0550 }, 1075 { .start = 0x1C4030, .end = 0x1C4030 }, 1076 { .start = 0x1C4510, .end = 0x1C4550 }, 1077 { .start = 0x1C8030, .end = 0x1C8030 }, 1078 { .start = 0x1C8510, .end = 0x1C8550 }, 1079 { .start = 0x1D0030, .end = 0x1D0030 }, 1080 { .start = 0x1D0510, .end = 0x1D0550 }, 1081 { .start = 0x1D4030, .end = 0x1D4030 }, 1082 { .start = 0x1D4510, .end = 0x1D4550 }, 1083 { .start = 0x1D8030, .end = 0x1D8030 }, 1084 { .start = 0x1D8510, .end = 0x1D8550 }, 1085 { .start = 0x1E0030, .end = 0x1E0030 }, 1086 { .start = 0x1E0510, .end = 0x1E0550 }, 1087 { .start = 0x1E4030, .end = 0x1E4030 }, 1088 { .start = 0x1E4510, .end = 0x1E4550 }, 1089 { .start = 0x1E8030, .end = 0x1E8030 }, 1090 { .start = 0x1E8510, .end = 0x1E8550 }, 1091 { .start = 0x1F0030, .end = 0x1F0030 }, 1092 { .start = 0x1F0510, .end = 0x1F0550 }, 1093 { .start = 0x1F4030, .end = 0x1F4030 }, 1094 { .start = 0x1F4510, .end = 0x1F4550 }, 1095 { .start = 0x1F8030, .end = 0x1F8030 }, 1096 { .start = 0x1F8510, .end = 0x1F8550 }, 1097 }; 1098 1099 static const struct i915_range pvc_shadowed_regs[] = { 1100 { .start = 0x2030, .end = 0x2030 }, 1101 { .start = 0x2510, .end = 0x2550 }, 1102 { .start = 0xA008, .end = 0xA00C }, 1103 { .start = 0xA188, .end = 0xA188 }, 1104 { .start = 0xA278, .end = 0xA278 }, 1105 { .start = 0xA540, .end = 0xA56C }, 1106 { .start = 0xC4C8, .end = 0xC4C8 }, 1107 { .start = 0xC4E0, .end = 0xC4E0 }, 1108 { .start = 0xC600, .end = 0xC600 }, 1109 { .start = 0xC658, .end = 0xC658 }, 1110 { .start = 0x22030, .end = 0x22030 }, 1111 { .start = 0x22510, .end = 0x22550 }, 1112 { .start = 0x1C0030, .end = 0x1C0030 }, 1113 { .start = 0x1C0510, .end = 0x1C0550 }, 1114 { .start = 0x1C4030, .end = 0x1C4030 }, 1115 { .start = 0x1C4510, .end = 0x1C4550 }, 1116 { .start = 0x1C8030, .end = 0x1C8030 }, 1117 { .start = 0x1C8510, .end = 0x1C8550 }, 1118 { .start = 0x1D0030, .end = 0x1D0030 }, 1119 { .start = 0x1D0510, .end = 0x1D0550 }, 1120 { .start = 0x1D4030, .end = 0x1D4030 }, 1121 { .start = 0x1D4510, .end = 0x1D4550 }, 1122 { .start = 0x1D8030, .end = 0x1D8030 }, 1123 { .start = 0x1D8510, .end = 0x1D8550 }, 1124 { .start = 0x1E0030, .end = 0x1E0030 }, 1125 { .start = 0x1E0510, .end = 0x1E0550 }, 1126 { .start = 0x1E4030, .end = 0x1E4030 }, 1127 { .start = 0x1E4510, .end = 0x1E4550 }, 1128 { .start = 0x1E8030, .end = 0x1E8030 }, 1129 { .start = 0x1E8510, .end = 0x1E8550 }, 1130 { .start = 0x1F0030, .end = 0x1F0030 }, 1131 { .start = 0x1F0510, .end = 0x1F0550 }, 1132 { .start = 0x1F4030, .end = 0x1F4030 }, 1133 { .start = 0x1F4510, .end = 0x1F4550 }, 1134 { .start = 0x1F8030, .end = 0x1F8030 }, 1135 { .start = 0x1F8510, .end = 0x1F8550 }, 1136 }; 1137 1138 static const struct i915_range mtl_shadowed_regs[] = { 1139 { .start = 0x2030, .end = 0x2030 }, 1140 { .start = 0x2510, .end = 0x2550 }, 1141 { .start = 0xA008, .end = 0xA00C }, 1142 { .start = 0xA188, .end = 0xA188 }, 1143 { .start = 0xA278, .end = 0xA278 }, 1144 { .start = 0xA540, .end = 0xA56C }, 1145 { .start = 0xC050, .end = 0xC050 }, 1146 { .start = 0xC340, .end = 0xC340 }, 1147 { .start = 0xC4C8, .end = 0xC4C8 }, 1148 { .start = 0xC4E0, .end = 0xC4E0 }, 1149 { .start = 0xC600, .end = 0xC600 }, 1150 { .start = 0xC658, .end = 0xC658 }, 1151 { .start = 0xCFD4, .end = 0xCFDC }, 1152 { .start = 0x22030, .end = 0x22030 }, 1153 { .start = 0x22510, .end = 0x22550 }, 1154 }; 1155 1156 static const struct i915_range xelpmp_shadowed_regs[] = { 1157 { .start = 0x1C0030, .end = 0x1C0030 }, 1158 { .start = 0x1C0510, .end = 0x1C0550 }, 1159 { .start = 0x1C8030, .end = 0x1C8030 }, 1160 { .start = 0x1C8510, .end = 0x1C8550 }, 1161 { .start = 0x1D0030, .end = 0x1D0030 }, 1162 { .start = 0x1D0510, .end = 0x1D0550 }, 1163 { .start = 0x38A008, .end = 0x38A00C }, 1164 { .start = 0x38A188, .end = 0x38A188 }, 1165 { .start = 0x38A278, .end = 0x38A278 }, 1166 { .start = 0x38A540, .end = 0x38A56C }, 1167 { .start = 0x38A618, .end = 0x38A618 }, 1168 { .start = 0x38C050, .end = 0x38C050 }, 1169 { .start = 0x38C340, .end = 0x38C340 }, 1170 { .start = 0x38C4C8, .end = 0x38C4C8 }, 1171 { .start = 0x38C4E0, .end = 0x38C4E4 }, 1172 { .start = 0x38C600, .end = 0x38C600 }, 1173 { .start = 0x38C658, .end = 0x38C658 }, 1174 { .start = 0x38CFD4, .end = 0x38CFDC }, 1175 }; 1176 1177 static int mmio_range_cmp(u32 key, const struct i915_range *range) 1178 { 1179 if (key < range->start) 1180 return -1; 1181 else if (key > range->end) 1182 return 1; 1183 else 1184 return 0; 1185 } 1186 1187 static bool is_shadowed(struct intel_uncore *uncore, u32 offset) 1188 { 1189 if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table)) 1190 return false; 1191 1192 if (IS_GSI_REG(offset)) 1193 offset += uncore->gsi_offset; 1194 1195 return BSEARCH(offset, 1196 uncore->shadowed_reg_table, 1197 uncore->shadowed_reg_table_entries, 1198 mmio_range_cmp); 1199 } 1200 1201 static enum forcewake_domains 1202 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 1203 { 1204 return FORCEWAKE_RENDER; 1205 } 1206 1207 #define __fwtable_reg_read_fw_domains(uncore, offset) \ 1208 ({ \ 1209 enum forcewake_domains __fwd = 0; \ 1210 if (NEEDS_FORCE_WAKE((offset))) \ 1211 __fwd = find_fw_domain(uncore, offset); \ 1212 __fwd; \ 1213 }) 1214 1215 #define __fwtable_reg_write_fw_domains(uncore, offset) \ 1216 ({ \ 1217 enum forcewake_domains __fwd = 0; \ 1218 const u32 __offset = (offset); \ 1219 if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \ 1220 __fwd = find_fw_domain(uncore, __offset); \ 1221 __fwd; \ 1222 }) 1223 1224 #define GEN_FW_RANGE(s, e, d) \ 1225 { .start = (s), .end = (e), .domains = (d) } 1226 1227 /* 1228 * All platforms' forcewake tables below must be sorted by offset ranges. 1229 * Furthermore, new forcewake tables added should be "watertight" and have 1230 * no gaps between ranges. 1231 * 1232 * When there are multiple consecutive ranges listed in the bspec with 1233 * the same forcewake domain, it is customary to combine them into a single 1234 * row in the tables below to keep the tables small and lookups fast. 1235 * Likewise, reserved/unused ranges may be combined with the preceding and/or 1236 * following ranges since the driver will never be making MMIO accesses in 1237 * those ranges. 1238 * 1239 * For example, if the bspec were to list: 1240 * 1241 * ... 1242 * 0x1000 - 0x1fff: GT 1243 * 0x2000 - 0x2cff: GT 1244 * 0x2d00 - 0x2fff: unused/reserved 1245 * 0x3000 - 0xffff: GT 1246 * ... 1247 * 1248 * these could all be represented by a single line in the code: 1249 * 1250 * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT) 1251 * 1252 * When adding new forcewake tables here, please also add them to 1253 * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be 1254 * scanned for obvious mistakes or typos by the selftests. 1255 */ 1256 1257 static const struct intel_forcewake_range __gen6_fw_ranges[] = { 1258 GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER), 1259 }; 1260 1261 static const struct intel_forcewake_range __vlv_fw_ranges[] = { 1262 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1263 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), 1264 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), 1265 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1266 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), 1267 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), 1268 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1269 }; 1270 1271 static const struct intel_forcewake_range __chv_fw_ranges[] = { 1272 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1273 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1274 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1275 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1276 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1277 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1278 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), 1279 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1280 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1281 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1282 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), 1283 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1284 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1285 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), 1286 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), 1287 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), 1288 }; 1289 1290 static const struct intel_forcewake_range __gen9_fw_ranges[] = { 1291 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), 1292 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ 1293 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1294 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1295 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1296 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1297 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1298 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), 1299 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), 1300 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1301 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1302 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1303 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1304 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), 1305 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), 1306 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1307 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), 1308 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1309 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1310 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1311 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), 1312 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1313 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), 1314 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), 1315 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), 1316 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1317 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), 1318 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), 1319 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), 1320 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), 1321 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), 1322 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1323 }; 1324 1325 static const struct intel_forcewake_range __gen11_fw_ranges[] = { 1326 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ 1327 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1328 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1329 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1330 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1331 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1332 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1333 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1334 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1335 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1336 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1337 GEN_FW_RANGE(0x8800, 0x8bff, 0), 1338 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1339 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), 1340 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1341 GEN_FW_RANGE(0x9560, 0x95ff, 0), 1342 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), 1343 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1344 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), 1345 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), 1346 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), 1347 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), 1348 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), 1349 GEN_FW_RANGE(0x24000, 0x2407f, 0), 1350 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), 1351 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), 1352 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), 1353 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), 1354 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), 1355 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1356 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), 1357 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1358 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0), 1359 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), 1360 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) 1361 }; 1362 1363 static const struct intel_forcewake_range __gen12_fw_ranges[] = { 1364 GEN_FW_RANGE(0x0, 0x1fff, 0), /* 1365 0x0 - 0xaff: reserved 1366 0xb00 - 0x1fff: always on */ 1367 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1368 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), 1369 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), 1370 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), 1371 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1372 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1373 0x4000 - 0x48ff: gt 1374 0x4900 - 0x51ff: reserved */ 1375 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1376 0x5200 - 0x53ff: render 1377 0x5400 - 0x54ff: reserved 1378 0x5500 - 0x7fff: render */ 1379 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1380 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1381 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 1382 0x8160 - 0x817f: reserved 1383 0x8180 - 0x81ff: always on */ 1384 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 1385 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1386 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* 1387 0x8500 - 0x87ff: gt 1388 0x8800 - 0x8fff: reserved 1389 0x9000 - 0x947f: gt 1390 0x9480 - 0x94cf: reserved */ 1391 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1392 GEN_FW_RANGE(0x9560, 0x97ff, 0), /* 1393 0x9560 - 0x95ff: always on 1394 0x9600 - 0x97ff: reserved */ 1395 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1396 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), 1397 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* 1398 0xb400 - 0xbf7f: gt 1399 0xb480 - 0xbfff: reserved 1400 0xc000 - 0xcfff: gt */ 1401 GEN_FW_RANGE(0xd000, 0xd7ff, 0), 1402 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), 1403 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), 1404 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* 1405 0xdc00 - 0xddff: render 1406 0xde00 - 0xde7f: reserved 1407 0xde80 - 0xe8ff: render 1408 0xe900 - 0xefff: reserved */ 1409 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* 1410 0xf000 - 0xffff: gt 1411 0x10000 - 0x147ff: reserved */ 1412 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* 1413 0x14800 - 0x14fff: render 1414 0x15000 - 0x16dff: reserved 1415 0x16e00 - 0x1bfff: render 1416 0x1c000 - 0x1ffff: reserved */ 1417 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), 1418 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), 1419 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1420 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1421 0x24000 - 0x2407f: always on 1422 0x24080 - 0x2417f: reserved */ 1423 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* 1424 0x24180 - 0x241ff: gt 1425 0x24200 - 0x249ff: reserved */ 1426 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* 1427 0x24a00 - 0x24a7f: render 1428 0x24a80 - 0x251ff: reserved */ 1429 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* 1430 0x25200 - 0x252ff: gt 1431 0x25300 - 0x255ff: reserved */ 1432 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), 1433 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* 1434 0x25680 - 0x256ff: VD2 1435 0x25700 - 0x259ff: reserved */ 1436 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), 1437 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1438 0x25a80 - 0x25aff: VD2 1439 0x25b00 - 0x2ffff: reserved */ 1440 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1441 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1442 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1443 0x1c0000 - 0x1c2bff: VD0 1444 0x1c2c00 - 0x1c2cff: reserved 1445 0x1c2d00 - 0x1c2dff: VD0 1446 0x1c2e00 - 0x1c3eff: reserved 1447 0x1c3f00 - 0x1c3fff: VD0 */ 1448 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1449 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1450 0x1c8000 - 0x1ca0ff: VE0 1451 0x1ca100 - 0x1cbeff: reserved 1452 0x1cbf00 - 0x1cbfff: VE0 */ 1453 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1454 0x1cc000 - 0x1ccfff: VD0 1455 0x1cd000 - 0x1cffff: reserved */ 1456 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* 1457 0x1d0000 - 0x1d2bff: VD2 1458 0x1d2c00 - 0x1d2cff: reserved 1459 0x1d2d00 - 0x1d2dff: VD2 1460 0x1d2e00 - 0x1d3eff: reserved 1461 0x1d3f00 - 0x1d3fff: VD2 */ 1462 }; 1463 1464 /* 1465 * Graphics IP version 12.55 brings a slight change to the 0xd800 range, 1466 * switching it from the GT domain to the render domain. 1467 */ 1468 #define XEHP_FWRANGES(FW_RANGE_D800) \ 1469 GEN_FW_RANGE(0x0, 0x1fff, 0), /* \ 1470 0x0 - 0xaff: reserved \ 1471 0xb00 - 0x1fff: always on */ \ 1472 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \ 1473 GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \ 1474 GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \ 1475 0x4b00 - 0x4fff: reserved \ 1476 0x5000 - 0x51ff: always on */ \ 1477 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \ 1478 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \ 1479 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \ 1480 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \ 1481 0x8160 - 0x817f: reserved \ 1482 0x8180 - 0x81ff: always on */ \ 1483 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \ 1484 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \ 1485 GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \ 1486 0x8500 - 0x87ff: gt \ 1487 0x8800 - 0x8c7f: reserved \ 1488 0x8c80 - 0x8cff: gt (DG2 only) */ \ 1489 GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \ 1490 0x8d00 - 0x8dff: render (DG2 only) \ 1491 0x8e00 - 0x8fff: reserved */ \ 1492 GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \ 1493 0x9000 - 0x947f: gt \ 1494 0x9480 - 0x94cf: reserved */ \ 1495 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \ 1496 GEN_FW_RANGE(0x9560, 0x967f, 0), /* \ 1497 0x9560 - 0x95ff: always on \ 1498 0x9600 - 0x967f: reserved */ \ 1499 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \ 1500 0x9680 - 0x96ff: render (DG2 only) \ 1501 0x9700 - 0x97ff: reserved */ \ 1502 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \ 1503 0x9800 - 0xb4ff: gt \ 1504 0xb500 - 0xbfff: reserved \ 1505 0xc000 - 0xcfff: gt */ \ 1506 GEN_FW_RANGE(0xd000, 0xd7ff, 0), \ 1507 GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \ 1508 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \ 1509 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \ 1510 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \ 1511 0xdd00 - 0xddff: gt \ 1512 0xde00 - 0xde7f: reserved */ \ 1513 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \ 1514 0xde80 - 0xdfff: render \ 1515 0xe000 - 0xe0ff: reserved \ 1516 0xe100 - 0xe8ff: render */ \ 1517 GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \ 1518 0xe900 - 0xe9ff: gt \ 1519 0xea00 - 0xefff: reserved \ 1520 0xf000 - 0xffff: gt */ \ 1521 GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \ 1522 0x10000 - 0x11fff: reserved \ 1523 0x12000 - 0x127ff: always on \ 1524 0x12800 - 0x12fff: reserved */ \ 1525 GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \ 1526 GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \ 1527 0x13200 - 0x133ff: VD2 (DG2 only) \ 1528 0x13400 - 0x13fff: reserved */ \ 1529 GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \ 1530 GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \ 1531 GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \ 1532 GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \ 1533 GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \ 1534 GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \ 1535 0x15000 - 0x15fff: gt (DG2 only) \ 1536 0x16000 - 0x16dff: reserved */ \ 1537 GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \ 1538 GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \ 1539 0x20000 - 0x20fff: VD0 (XEHPSDV only) \ 1540 0x21000 - 0x21fff: reserved */ \ 1541 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \ 1542 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \ 1543 0x24000 - 0x2407f: always on \ 1544 0x24080 - 0x2417f: reserved */ \ 1545 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \ 1546 0x24180 - 0x241ff: gt \ 1547 0x24200 - 0x249ff: reserved */ \ 1548 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \ 1549 0x24a00 - 0x24a7f: render \ 1550 0x24a80 - 0x251ff: reserved */ \ 1551 GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \ 1552 0x25200 - 0x252ff: gt \ 1553 0x25300 - 0x25fff: reserved */ \ 1554 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \ 1555 0x26000 - 0x27fff: render \ 1556 0x28000 - 0x29fff: reserved \ 1557 0x2a000 - 0x2ffff: undocumented */ \ 1558 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \ 1559 GEN_FW_RANGE(0x40000, 0x1bffff, 0), \ 1560 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \ 1561 0x1c0000 - 0x1c2bff: VD0 \ 1562 0x1c2c00 - 0x1c2cff: reserved \ 1563 0x1c2d00 - 0x1c2dff: VD0 \ 1564 0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \ 1565 0x1c3f00 - 0x1c3fff: VD0 */ \ 1566 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \ 1567 0x1c4000 - 0x1c6bff: VD1 \ 1568 0x1c6c00 - 0x1c6cff: reserved \ 1569 0x1c6d00 - 0x1c6dff: VD1 \ 1570 0x1c6e00 - 0x1c7fff: reserved */ \ 1571 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \ 1572 0x1c8000 - 0x1ca0ff: VE0 \ 1573 0x1ca100 - 0x1cbfff: reserved */ \ 1574 GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \ 1575 GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \ 1576 GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \ 1577 GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \ 1578 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \ 1579 0x1d0000 - 0x1d2bff: VD2 \ 1580 0x1d2c00 - 0x1d2cff: reserved \ 1581 0x1d2d00 - 0x1d2dff: VD2 \ 1582 0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \ 1583 0x1d3e00 - 0x1d3eff: reserved \ 1584 0x1d3f00 - 0x1d3fff: VD2 */ \ 1585 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \ 1586 0x1d4000 - 0x1d6bff: VD3 \ 1587 0x1d6c00 - 0x1d6cff: reserved \ 1588 0x1d6d00 - 0x1d6dff: VD3 \ 1589 0x1d6e00 - 0x1d7fff: reserved */ \ 1590 GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \ 1591 0x1d8000 - 0x1da0ff: VE1 \ 1592 0x1da100 - 0x1dffff: reserved */ \ 1593 GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \ 1594 0x1e0000 - 0x1e2bff: VD4 \ 1595 0x1e2c00 - 0x1e2cff: reserved \ 1596 0x1e2d00 - 0x1e2dff: VD4 \ 1597 0x1e2e00 - 0x1e3eff: reserved \ 1598 0x1e3f00 - 0x1e3fff: VD4 */ \ 1599 GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \ 1600 0x1e4000 - 0x1e6bff: VD5 \ 1601 0x1e6c00 - 0x1e6cff: reserved \ 1602 0x1e6d00 - 0x1e6dff: VD5 \ 1603 0x1e6e00 - 0x1e7fff: reserved */ \ 1604 GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \ 1605 0x1e8000 - 0x1ea0ff: VE2 \ 1606 0x1ea100 - 0x1effff: reserved */ \ 1607 GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \ 1608 0x1f0000 - 0x1f2bff: VD6 \ 1609 0x1f2c00 - 0x1f2cff: reserved \ 1610 0x1f2d00 - 0x1f2dff: VD6 \ 1611 0x1f2e00 - 0x1f3eff: reserved \ 1612 0x1f3f00 - 0x1f3fff: VD6 */ \ 1613 GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \ 1614 0x1f4000 - 0x1f6bff: VD7 \ 1615 0x1f6c00 - 0x1f6cff: reserved \ 1616 0x1f6d00 - 0x1f6dff: VD7 \ 1617 0x1f6e00 - 0x1f7fff: reserved */ \ 1618 GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3), 1619 1620 static const struct intel_forcewake_range __xehp_fw_ranges[] = { 1621 XEHP_FWRANGES(FORCEWAKE_GT) 1622 }; 1623 1624 static const struct intel_forcewake_range __dg2_fw_ranges[] = { 1625 XEHP_FWRANGES(FORCEWAKE_RENDER) 1626 }; 1627 1628 static const struct intel_forcewake_range __pvc_fw_ranges[] = { 1629 GEN_FW_RANGE(0x0, 0xaff, 0), 1630 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT), 1631 GEN_FW_RANGE(0xc00, 0xfff, 0), 1632 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT), 1633 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1634 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1635 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1636 GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /* 1637 0x4000 - 0x4aff: gt 1638 0x4b00 - 0x4fff: reserved 1639 0x5000 - 0x51ff: gt 1640 0x5200 - 0x52ff: reserved 1641 0x5300 - 0x53ff: gt 1642 0x5400 - 0x7fff: reserved 1643 0x8000 - 0x813f: gt */ 1644 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), 1645 GEN_FW_RANGE(0x8180, 0x81ff, 0), 1646 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /* 1647 0x8200 - 0x82ff: gt 1648 0x8300 - 0x84ff: reserved 1649 0x8500 - 0x887f: gt 1650 0x8880 - 0x8a7f: reserved 1651 0x8a80 - 0x8aff: gt 1652 0x8b00 - 0x8fff: reserved 1653 0x9000 - 0x947f: gt 1654 0x9480 - 0x94cf: reserved */ 1655 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1656 GEN_FW_RANGE(0x9560, 0x967f, 0), /* 1657 0x9560 - 0x95ff: always on 1658 0x9600 - 0x967f: reserved */ 1659 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* 1660 0x9680 - 0x96ff: render 1661 0x9700 - 0x97ff: reserved */ 1662 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* 1663 0x9800 - 0xb4ff: gt 1664 0xb500 - 0xbfff: reserved 1665 0xc000 - 0xcfff: gt */ 1666 GEN_FW_RANGE(0xd000, 0xd3ff, 0), 1667 GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT), 1668 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), 1669 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* 1670 0xdd00 - 0xddff: gt 1671 0xde00 - 0xde7f: reserved */ 1672 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* 1673 0xde80 - 0xdeff: render 1674 0xdf00 - 0xe1ff: reserved 1675 0xe200 - 0xe7ff: render 1676 0xe800 - 0xe8ff: reserved */ 1677 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /* 1678 0xe900 - 0xe9ff: gt 1679 0xea00 - 0xebff: reserved 1680 0xec00 - 0xffff: gt 1681 0x10000 - 0x11fff: reserved */ 1682 GEN_FW_RANGE(0x12000, 0x12fff, 0), /* 1683 0x12000 - 0x127ff: always on 1684 0x12800 - 0x12fff: reserved */ 1685 GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /* 1686 0x13000 - 0x135ff: gt 1687 0x13600 - 0x147ff: reserved 1688 0x14800 - 0x153ff: gt 1689 0x15400 - 0x19fff: reserved */ 1690 GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /* 1691 0x1a000 - 0x1ffff: render 1692 0x20000 - 0x21fff: reserved */ 1693 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1694 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1695 24000 - 0x2407f: always on 1696 24080 - 0x2417f: reserved */ 1697 GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /* 1698 0x24180 - 0x241ff: gt 1699 0x24200 - 0x251ff: reserved 1700 0x25200 - 0x252ff: gt 1701 0x25300 - 0x25fff: reserved */ 1702 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* 1703 0x26000 - 0x27fff: render 1704 0x28000 - 0x2ffff: reserved */ 1705 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1706 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1707 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1708 0x1c0000 - 0x1c2bff: VD0 1709 0x1c2c00 - 0x1c2cff: reserved 1710 0x1c2d00 - 0x1c2dff: VD0 1711 0x1c2e00 - 0x1c3eff: reserved 1712 0x1c3f00 - 0x1c3fff: VD0 */ 1713 GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /* 1714 0x1c4000 - 0x1c6aff: VD1 1715 0x1c6b00 - 0x1c7eff: reserved 1716 0x1c7f00 - 0x1c7fff: VD1 1717 0x1c8000 - 0x1cffff: reserved */ 1718 GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1719 0x1d0000 - 0x1d2aff: VD2 1720 0x1d2b00 - 0x1d3eff: reserved 1721 0x1d3f00 - 0x1d3fff: VD2 1722 0x1d4000 - 0x23ffff: reserved */ 1723 GEN_FW_RANGE(0x240000, 0x3dffff, 0), 1724 GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT), 1725 }; 1726 1727 static const struct intel_forcewake_range __mtl_fw_ranges[] = { 1728 GEN_FW_RANGE(0x0, 0xaff, 0), 1729 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT), 1730 GEN_FW_RANGE(0xc00, 0xfff, 0), 1731 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT), 1732 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1733 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1734 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1735 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1736 0x4000 - 0x48ff: render 1737 0x4900 - 0x51ff: reserved */ 1738 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1739 0x5200 - 0x53ff: render 1740 0x5400 - 0x54ff: reserved 1741 0x5500 - 0x7fff: render */ 1742 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1743 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), /* 1744 0x8140 - 0x815f: render 1745 0x8160 - 0x817f: reserved */ 1746 GEN_FW_RANGE(0x8180, 0x81ff, 0), 1747 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /* 1748 0x8200 - 0x87ff: gt 1749 0x8800 - 0x8dff: reserved 1750 0x8e00 - 0x8f7f: gt 1751 0x8f80 - 0x8fff: reserved 1752 0x9000 - 0x947f: gt 1753 0x9480 - 0x94cf: reserved */ 1754 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1755 GEN_FW_RANGE(0x9560, 0x967f, 0), /* 1756 0x9560 - 0x95ff: always on 1757 0x9600 - 0x967f: reserved */ 1758 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* 1759 0x9680 - 0x96ff: render 1760 0x9700 - 0x97ff: reserved */ 1761 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* 1762 0x9800 - 0xb4ff: gt 1763 0xb500 - 0xbfff: reserved 1764 0xc000 - 0xcfff: gt */ 1765 GEN_FW_RANGE(0xd000, 0xd7ff, 0), /* 1766 0xd000 - 0xd3ff: always on 1767 0xd400 - 0xd7ff: reserved */ 1768 GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER), 1769 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), 1770 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), 1771 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* 1772 0xdd00 - 0xddff: gt 1773 0xde00 - 0xde7f: reserved */ 1774 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* 1775 0xde80 - 0xdfff: render 1776 0xe000 - 0xe0ff: reserved 1777 0xe100 - 0xe8ff: render */ 1778 GEN_FW_RANGE(0xe900, 0xe9ff, FORCEWAKE_GT), 1779 GEN_FW_RANGE(0xea00, 0x147ff, 0), /* 1780 0xea00 - 0x11fff: reserved 1781 0x12000 - 0x127ff: always on 1782 0x12800 - 0x147ff: reserved */ 1783 GEN_FW_RANGE(0x14800, 0x19fff, FORCEWAKE_GT), /* 1784 0x14800 - 0x153ff: gt 1785 0x15400 - 0x19fff: reserved */ 1786 GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /* 1787 0x1a000 - 0x1bfff: render 1788 0x1c000 - 0x21fff: reserved */ 1789 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1790 GEN_FW_RANGE(0x24000, 0x2ffff, 0), /* 1791 0x24000 - 0x2407f: always on 1792 0x24080 - 0x2ffff: reserved */ 1793 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT) 1794 }; 1795 1796 /* 1797 * Note that the register ranges here are the final offsets after 1798 * translation of the GSI block to the 0x380000 offset. 1799 * 1800 * NOTE: There are a couple MCR ranges near the bottom of this table 1801 * that need to power up either VD0 or VD2 depending on which replicated 1802 * instance of the register we're trying to access. Our forcewake logic 1803 * at the moment doesn't have a good way to take steering into consideration, 1804 * and the driver doesn't even access any registers in those ranges today, 1805 * so for now we just mark those ranges as FORCEWAKE_ALL. That will ensure 1806 * proper operation if we do start using the ranges in the future, and we 1807 * can determine at that time whether it's worth adding extra complexity to 1808 * the forcewake handling to take steering into consideration. 1809 */ 1810 static const struct intel_forcewake_range __xelpmp_fw_ranges[] = { 1811 GEN_FW_RANGE(0x0, 0x115fff, 0), /* render GT range */ 1812 GEN_FW_RANGE(0x116000, 0x11ffff, FORCEWAKE_GSC), /* 1813 0x116000 - 0x117fff: gsc 1814 0x118000 - 0x119fff: reserved 1815 0x11a000 - 0x11efff: gsc 1816 0x11f000 - 0x11ffff: reserved */ 1817 GEN_FW_RANGE(0x120000, 0x1bffff, 0), /* non-GT range */ 1818 GEN_FW_RANGE(0x1c0000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX0), /* 1819 0x1c0000 - 0x1c3dff: VD0 1820 0x1c3e00 - 0x1c3eff: reserved 1821 0x1c3f00 - 0x1c3fff: VD0 1822 0x1c4000 - 0x1c7fff: reserved */ 1823 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1824 0x1c8000 - 0x1ca0ff: VE0 1825 0x1ca100 - 0x1cbfff: reserved */ 1826 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1827 0x1cc000 - 0x1cdfff: VD0 1828 0x1ce000 - 0x1cffff: reserved */ 1829 GEN_FW_RANGE(0x1d0000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX2), /* 1830 0x1d0000 - 0x1d3dff: VD2 1831 0x1d3e00 - 0x1d3eff: reserved 1832 0x1d4000 - 0x1d7fff: VD2 */ 1833 GEN_FW_RANGE(0x1d8000, 0x1da0ff, FORCEWAKE_MEDIA_VEBOX1), 1834 GEN_FW_RANGE(0x1da100, 0x380aff, 0), /* 1835 0x1da100 - 0x23ffff: reserved 1836 0x240000 - 0x37ffff: non-GT range 1837 0x380000 - 0x380aff: reserved */ 1838 GEN_FW_RANGE(0x380b00, 0x380bff, FORCEWAKE_GT), 1839 GEN_FW_RANGE(0x380c00, 0x380fff, 0), 1840 GEN_FW_RANGE(0x381000, 0x38817f, FORCEWAKE_GT), /* 1841 0x381000 - 0x381fff: gt 1842 0x382000 - 0x383fff: reserved 1843 0x384000 - 0x384aff: gt 1844 0x384b00 - 0x3851ff: reserved 1845 0x385200 - 0x3871ff: gt 1846 0x387200 - 0x387fff: reserved 1847 0x388000 - 0x38813f: gt 1848 0x388140 - 0x38817f: reserved */ 1849 GEN_FW_RANGE(0x388180, 0x3882ff, 0), /* 1850 0x388180 - 0x3881ff: always on 1851 0x388200 - 0x3882ff: reserved */ 1852 GEN_FW_RANGE(0x388300, 0x38955f, FORCEWAKE_GT), /* 1853 0x388300 - 0x38887f: gt 1854 0x388880 - 0x388fff: reserved 1855 0x389000 - 0x38947f: gt 1856 0x389480 - 0x38955f: reserved */ 1857 GEN_FW_RANGE(0x389560, 0x389fff, 0), /* 1858 0x389560 - 0x3895ff: always on 1859 0x389600 - 0x389fff: reserved */ 1860 GEN_FW_RANGE(0x38a000, 0x38cfff, FORCEWAKE_GT), /* 1861 0x38a000 - 0x38afff: gt 1862 0x38b000 - 0x38bfff: reserved 1863 0x38c000 - 0x38cfff: gt */ 1864 GEN_FW_RANGE(0x38d000, 0x38d11f, 0), 1865 GEN_FW_RANGE(0x38d120, 0x391fff, FORCEWAKE_GT), /* 1866 0x38d120 - 0x38dfff: gt 1867 0x38e000 - 0x38efff: reserved 1868 0x38f000 - 0x38ffff: gt 1869 0x389000 - 0x391fff: reserved */ 1870 GEN_FW_RANGE(0x392000, 0x392fff, 0), /* 1871 0x392000 - 0x3927ff: always on 1872 0x392800 - 0x292fff: reserved */ 1873 GEN_FW_RANGE(0x393000, 0x3931ff, FORCEWAKE_GT), 1874 GEN_FW_RANGE(0x393200, 0x39323f, FORCEWAKE_ALL), /* instance-based, see note above */ 1875 GEN_FW_RANGE(0x393240, 0x3933ff, FORCEWAKE_GT), 1876 GEN_FW_RANGE(0x393400, 0x3934ff, FORCEWAKE_ALL), /* instance-based, see note above */ 1877 GEN_FW_RANGE(0x393500, 0x393c7f, 0), /* 1878 0x393500 - 0x393bff: reserved 1879 0x393c00 - 0x393c7f: always on */ 1880 GEN_FW_RANGE(0x393c80, 0x393dff, FORCEWAKE_GT), 1881 }; 1882 1883 static void 1884 ilk_dummy_write(struct intel_uncore *uncore) 1885 { 1886 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 1887 * the chip from rc6 before touching it for real. MI_MODE is masked, 1888 * hence harmless to write 0 into. */ 1889 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); 1890 } 1891 1892 static void 1893 __unclaimed_reg_debug(struct intel_uncore *uncore, 1894 const i915_reg_t reg, 1895 const bool read) 1896 { 1897 if (drm_WARN(&uncore->i915->drm, 1898 check_for_unclaimed_mmio(uncore), 1899 "Unclaimed %s register 0x%x\n", 1900 read ? "read from" : "write to", 1901 i915_mmio_reg_offset(reg))) 1902 /* Only report the first N failures */ 1903 uncore->i915->params.mmio_debug--; 1904 } 1905 1906 static void 1907 __unclaimed_previous_reg_debug(struct intel_uncore *uncore, 1908 const i915_reg_t reg, 1909 const bool read) 1910 { 1911 if (check_for_unclaimed_mmio(uncore)) 1912 drm_dbg(&uncore->i915->drm, 1913 "Unclaimed access detected before %s register 0x%x\n", 1914 read ? "read from" : "write to", 1915 i915_mmio_reg_offset(reg)); 1916 } 1917 1918 static inline void 1919 unclaimed_reg_debug(struct intel_uncore *uncore, 1920 const i915_reg_t reg, 1921 const bool read, 1922 const bool before) 1923 { 1924 if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug) 1925 return; 1926 1927 /* interrupts are disabled and re-enabled around uncore->lock usage */ 1928 lockdep_assert_held(&uncore->lock); 1929 1930 if (before) { 1931 spin_lock(&uncore->debug->lock); 1932 __unclaimed_previous_reg_debug(uncore, reg, read); 1933 } else { 1934 __unclaimed_reg_debug(uncore, reg, read); 1935 spin_unlock(&uncore->debug->lock); 1936 } 1937 } 1938 1939 #define __vgpu_read(x) \ 1940 static u##x \ 1941 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1942 u##x val = __raw_uncore_read##x(uncore, reg); \ 1943 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1944 return val; \ 1945 } 1946 __vgpu_read(8) 1947 __vgpu_read(16) 1948 __vgpu_read(32) 1949 __vgpu_read(64) 1950 1951 #define GEN2_READ_HEADER(x) \ 1952 u##x val = 0; \ 1953 assert_rpm_wakelock_held(uncore->rpm); 1954 1955 #define GEN2_READ_FOOTER \ 1956 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1957 return val 1958 1959 #define __gen2_read(x) \ 1960 static u##x \ 1961 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1962 GEN2_READ_HEADER(x); \ 1963 val = __raw_uncore_read##x(uncore, reg); \ 1964 GEN2_READ_FOOTER; \ 1965 } 1966 1967 #define __gen5_read(x) \ 1968 static u##x \ 1969 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1970 GEN2_READ_HEADER(x); \ 1971 ilk_dummy_write(uncore); \ 1972 val = __raw_uncore_read##x(uncore, reg); \ 1973 GEN2_READ_FOOTER; \ 1974 } 1975 1976 __gen5_read(8) 1977 __gen5_read(16) 1978 __gen5_read(32) 1979 __gen5_read(64) 1980 __gen2_read(8) 1981 __gen2_read(16) 1982 __gen2_read(32) 1983 __gen2_read(64) 1984 1985 #undef __gen5_read 1986 #undef __gen2_read 1987 1988 #undef GEN2_READ_FOOTER 1989 #undef GEN2_READ_HEADER 1990 1991 #define GEN6_READ_HEADER(x) \ 1992 u32 offset = i915_mmio_reg_offset(reg); \ 1993 unsigned long irqflags; \ 1994 u##x val = 0; \ 1995 assert_rpm_wakelock_held(uncore->rpm); \ 1996 spin_lock_irqsave(&uncore->lock, irqflags); \ 1997 unclaimed_reg_debug(uncore, reg, true, true) 1998 1999 #define GEN6_READ_FOOTER \ 2000 unclaimed_reg_debug(uncore, reg, true, false); \ 2001 spin_unlock_irqrestore(&uncore->lock, irqflags); \ 2002 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 2003 return val 2004 2005 static noinline void ___force_wake_auto(struct intel_uncore *uncore, 2006 enum forcewake_domains fw_domains) 2007 { 2008 struct intel_uncore_forcewake_domain *domain; 2009 unsigned int tmp; 2010 2011 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 2012 2013 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) 2014 fw_domain_arm_timer(domain); 2015 2016 fw_domains_get(uncore, fw_domains); 2017 } 2018 2019 static inline void __force_wake_auto(struct intel_uncore *uncore, 2020 enum forcewake_domains fw_domains) 2021 { 2022 GEM_BUG_ON(!fw_domains); 2023 2024 /* Turn on all requested but inactive supported forcewake domains. */ 2025 fw_domains &= uncore->fw_domains; 2026 fw_domains &= ~uncore->fw_domains_active; 2027 2028 if (fw_domains) 2029 ___force_wake_auto(uncore, fw_domains); 2030 } 2031 2032 #define __gen_fwtable_read(x) \ 2033 static u##x \ 2034 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \ 2035 { \ 2036 enum forcewake_domains fw_engine; \ 2037 GEN6_READ_HEADER(x); \ 2038 fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \ 2039 if (fw_engine) \ 2040 __force_wake_auto(uncore, fw_engine); \ 2041 val = __raw_uncore_read##x(uncore, reg); \ 2042 GEN6_READ_FOOTER; \ 2043 } 2044 2045 static enum forcewake_domains 2046 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { 2047 return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); 2048 } 2049 2050 __gen_fwtable_read(8) 2051 __gen_fwtable_read(16) 2052 __gen_fwtable_read(32) 2053 __gen_fwtable_read(64) 2054 2055 #undef __gen_fwtable_read 2056 #undef GEN6_READ_FOOTER 2057 #undef GEN6_READ_HEADER 2058 2059 #define GEN2_WRITE_HEADER \ 2060 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 2061 assert_rpm_wakelock_held(uncore->rpm); \ 2062 2063 #define GEN2_WRITE_FOOTER 2064 2065 #define __gen2_write(x) \ 2066 static void \ 2067 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 2068 GEN2_WRITE_HEADER; \ 2069 __raw_uncore_write##x(uncore, reg, val); \ 2070 GEN2_WRITE_FOOTER; \ 2071 } 2072 2073 #define __gen5_write(x) \ 2074 static void \ 2075 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 2076 GEN2_WRITE_HEADER; \ 2077 ilk_dummy_write(uncore); \ 2078 __raw_uncore_write##x(uncore, reg, val); \ 2079 GEN2_WRITE_FOOTER; \ 2080 } 2081 2082 __gen5_write(8) 2083 __gen5_write(16) 2084 __gen5_write(32) 2085 __gen2_write(8) 2086 __gen2_write(16) 2087 __gen2_write(32) 2088 2089 #undef __gen5_write 2090 #undef __gen2_write 2091 2092 #undef GEN2_WRITE_FOOTER 2093 #undef GEN2_WRITE_HEADER 2094 2095 #define GEN6_WRITE_HEADER \ 2096 u32 offset = i915_mmio_reg_offset(reg); \ 2097 unsigned long irqflags; \ 2098 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 2099 assert_rpm_wakelock_held(uncore->rpm); \ 2100 spin_lock_irqsave(&uncore->lock, irqflags); \ 2101 unclaimed_reg_debug(uncore, reg, false, true) 2102 2103 #define GEN6_WRITE_FOOTER \ 2104 unclaimed_reg_debug(uncore, reg, false, false); \ 2105 spin_unlock_irqrestore(&uncore->lock, irqflags) 2106 2107 #define __gen6_write(x) \ 2108 static void \ 2109 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 2110 GEN6_WRITE_HEADER; \ 2111 if (NEEDS_FORCE_WAKE(offset)) \ 2112 __gen6_gt_wait_for_fifo(uncore); \ 2113 __raw_uncore_write##x(uncore, reg, val); \ 2114 GEN6_WRITE_FOOTER; \ 2115 } 2116 __gen6_write(8) 2117 __gen6_write(16) 2118 __gen6_write(32) 2119 2120 #define __gen_fwtable_write(x) \ 2121 static void \ 2122 fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 2123 enum forcewake_domains fw_engine; \ 2124 GEN6_WRITE_HEADER; \ 2125 fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \ 2126 if (fw_engine) \ 2127 __force_wake_auto(uncore, fw_engine); \ 2128 __raw_uncore_write##x(uncore, reg, val); \ 2129 GEN6_WRITE_FOOTER; \ 2130 } 2131 2132 static enum forcewake_domains 2133 fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 2134 { 2135 return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); 2136 } 2137 2138 __gen_fwtable_write(8) 2139 __gen_fwtable_write(16) 2140 __gen_fwtable_write(32) 2141 2142 #undef __gen_fwtable_write 2143 #undef GEN6_WRITE_FOOTER 2144 #undef GEN6_WRITE_HEADER 2145 2146 #define __vgpu_write(x) \ 2147 static void \ 2148 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 2149 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 2150 __raw_uncore_write##x(uncore, reg, val); \ 2151 } 2152 __vgpu_write(8) 2153 __vgpu_write(16) 2154 __vgpu_write(32) 2155 2156 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ 2157 do { \ 2158 (uncore)->funcs.mmio_writeb = x##_write8; \ 2159 (uncore)->funcs.mmio_writew = x##_write16; \ 2160 (uncore)->funcs.mmio_writel = x##_write32; \ 2161 } while (0) 2162 2163 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ 2164 do { \ 2165 (uncore)->funcs.mmio_readb = x##_read8; \ 2166 (uncore)->funcs.mmio_readw = x##_read16; \ 2167 (uncore)->funcs.mmio_readl = x##_read32; \ 2168 (uncore)->funcs.mmio_readq = x##_read64; \ 2169 } while (0) 2170 2171 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ 2172 do { \ 2173 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ 2174 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ 2175 } while (0) 2176 2177 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ 2178 do { \ 2179 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ 2180 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ 2181 } while (0) 2182 2183 static int __fw_domain_init(struct intel_uncore *uncore, 2184 enum forcewake_domain_id domain_id, 2185 i915_reg_t reg_set, 2186 i915_reg_t reg_ack) 2187 { 2188 struct intel_uncore_forcewake_domain *d; 2189 2190 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 2191 GEM_BUG_ON(uncore->fw_domain[domain_id]); 2192 2193 if (i915_inject_probe_failure(uncore->i915)) 2194 return -ENOMEM; 2195 2196 d = kzalloc(sizeof(*d), GFP_KERNEL); 2197 if (!d) 2198 return -ENOMEM; 2199 2200 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); 2201 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack)); 2202 2203 d->uncore = uncore; 2204 d->wake_count = 0; 2205 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset; 2206 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset; 2207 2208 d->id = domain_id; 2209 2210 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 2211 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); 2212 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 2213 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); 2214 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); 2215 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); 2216 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); 2217 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4)); 2218 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5)); 2219 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6)); 2220 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7)); 2221 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); 2222 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); 2223 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2)); 2224 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3)); 2225 BUILD_BUG_ON(FORCEWAKE_GSC != (1 << FW_DOMAIN_ID_GSC)); 2226 2227 d->mask = BIT(domain_id); 2228 2229 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2230 d->timer.function = intel_uncore_fw_release_timer; 2231 2232 uncore->fw_domains |= BIT(domain_id); 2233 2234 fw_domain_reset(d); 2235 2236 uncore->fw_domain[domain_id] = d; 2237 2238 return 0; 2239 } 2240 2241 static void fw_domain_fini(struct intel_uncore *uncore, 2242 enum forcewake_domain_id domain_id) 2243 { 2244 struct intel_uncore_forcewake_domain *d; 2245 2246 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 2247 2248 d = fetch_and_zero(&uncore->fw_domain[domain_id]); 2249 if (!d) 2250 return; 2251 2252 uncore->fw_domains &= ~BIT(domain_id); 2253 drm_WARN_ON(&uncore->i915->drm, d->wake_count); 2254 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer)); 2255 kfree(d); 2256 } 2257 2258 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) 2259 { 2260 struct intel_uncore_forcewake_domain *d; 2261 int tmp; 2262 2263 for_each_fw_domain(d, uncore, tmp) 2264 fw_domain_fini(uncore, d->id); 2265 } 2266 2267 static const struct intel_uncore_fw_get uncore_get_fallback = { 2268 .force_wake_get = fw_domains_get_with_fallback 2269 }; 2270 2271 static const struct intel_uncore_fw_get uncore_get_normal = { 2272 .force_wake_get = fw_domains_get_normal, 2273 }; 2274 2275 static const struct intel_uncore_fw_get uncore_get_thread_status = { 2276 .force_wake_get = fw_domains_get_with_thread_status 2277 }; 2278 2279 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) 2280 { 2281 struct drm_i915_private *i915 = uncore->i915; 2282 int ret = 0; 2283 2284 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2285 2286 #define fw_domain_init(uncore__, id__, set__, ack__) \ 2287 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) 2288 2289 if (GRAPHICS_VER(i915) >= 11) { 2290 intel_engine_mask_t emask; 2291 int i; 2292 2293 /* we'll prune the domains of missing engines later */ 2294 emask = uncore->gt->info.engine_mask; 2295 2296 uncore->fw_get_funcs = &uncore_get_fallback; 2297 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 2298 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2299 FORCEWAKE_GT_GEN9, 2300 FORCEWAKE_ACK_GT_MTL); 2301 else 2302 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2303 FORCEWAKE_GT_GEN9, 2304 FORCEWAKE_ACK_GT_GEN9); 2305 2306 if (RCS_MASK(uncore->gt) || CCS_MASK(uncore->gt)) 2307 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2308 FORCEWAKE_RENDER_GEN9, 2309 FORCEWAKE_ACK_RENDER_GEN9); 2310 2311 for (i = 0; i < I915_MAX_VCS; i++) { 2312 if (!__HAS_ENGINE(emask, _VCS(i))) 2313 continue; 2314 2315 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, 2316 FORCEWAKE_MEDIA_VDBOX_GEN11(i), 2317 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); 2318 } 2319 for (i = 0; i < I915_MAX_VECS; i++) { 2320 if (!__HAS_ENGINE(emask, _VECS(i))) 2321 continue; 2322 2323 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, 2324 FORCEWAKE_MEDIA_VEBOX_GEN11(i), 2325 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); 2326 } 2327 2328 if (uncore->gt->type == GT_MEDIA) 2329 fw_domain_init(uncore, FW_DOMAIN_ID_GSC, 2330 FORCEWAKE_REQ_GSC, FORCEWAKE_ACK_GSC); 2331 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2332 uncore->fw_get_funcs = &uncore_get_fallback; 2333 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2334 FORCEWAKE_RENDER_GEN9, 2335 FORCEWAKE_ACK_RENDER_GEN9); 2336 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2337 FORCEWAKE_GT_GEN9, 2338 FORCEWAKE_ACK_GT_GEN9); 2339 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 2340 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 2341 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 2342 uncore->fw_get_funcs = &uncore_get_normal; 2343 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2344 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 2345 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 2346 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 2347 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2348 uncore->fw_get_funcs = &uncore_get_thread_status; 2349 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2350 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 2351 } else if (IS_IVYBRIDGE(i915)) { 2352 u32 ecobus; 2353 2354 /* IVB configs may use multi-threaded forcewake */ 2355 2356 /* A small trick here - if the bios hasn't configured 2357 * MT forcewake, and if the device is in RC6, then 2358 * force_wake_mt_get will not wake the device and the 2359 * ECOBUS read will return zero. Which will be 2360 * (correctly) interpreted by the test below as MT 2361 * forcewake being disabled. 2362 */ 2363 uncore->fw_get_funcs = &uncore_get_thread_status; 2364 2365 /* We need to init first for ECOBUS access and then 2366 * determine later if we want to reinit, in case of MT access is 2367 * not working. In this stage we don't know which flavour this 2368 * ivb is, so it is better to reset also the gen6 fw registers 2369 * before the ecobus check. 2370 */ 2371 2372 __raw_uncore_write32(uncore, FORCEWAKE, 0); 2373 __raw_posting_read(uncore, ECOBUS); 2374 2375 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2376 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 2377 if (ret) 2378 goto out; 2379 2380 spin_lock_irq(&uncore->lock); 2381 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); 2382 ecobus = __raw_uncore_read32(uncore, ECOBUS); 2383 fw_domains_put(uncore, FORCEWAKE_RENDER); 2384 spin_unlock_irq(&uncore->lock); 2385 2386 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 2387 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n"); 2388 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n"); 2389 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); 2390 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2391 FORCEWAKE, FORCEWAKE_ACK); 2392 } 2393 } else if (GRAPHICS_VER(i915) == 6) { 2394 uncore->fw_get_funcs = &uncore_get_thread_status; 2395 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2396 FORCEWAKE, FORCEWAKE_ACK); 2397 } 2398 2399 #undef fw_domain_init 2400 2401 /* All future platforms are expected to require complex power gating */ 2402 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); 2403 2404 out: 2405 if (ret) 2406 intel_uncore_fw_domains_fini(uncore); 2407 2408 return ret; 2409 } 2410 2411 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ 2412 { \ 2413 (uncore)->fw_domains_table = \ 2414 (struct intel_forcewake_range *)(d); \ 2415 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ 2416 } 2417 2418 #define ASSIGN_SHADOW_TABLE(uncore, d) \ 2419 { \ 2420 (uncore)->shadowed_reg_table = d; \ 2421 (uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \ 2422 } 2423 2424 static int i915_pmic_bus_access_notifier(struct notifier_block *nb, 2425 unsigned long action, void *data) 2426 { 2427 struct intel_uncore *uncore = container_of(nb, 2428 struct intel_uncore, pmic_bus_access_nb); 2429 2430 switch (action) { 2431 case MBI_PMIC_BUS_ACCESS_BEGIN: 2432 /* 2433 * forcewake all now to make sure that we don't need to do a 2434 * forcewake later which on systems where this notifier gets 2435 * called requires the punit to access to the shared pmic i2c 2436 * bus, which will be busy after this notification, leading to: 2437 * "render: timed out waiting for forcewake ack request." 2438 * errors. 2439 * 2440 * The notifier is unregistered during intel_runtime_suspend(), 2441 * so it's ok to access the HW here without holding a RPM 2442 * wake reference -> disable wakeref asserts for the time of 2443 * the access. 2444 */ 2445 disable_rpm_wakeref_asserts(uncore->rpm); 2446 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 2447 enable_rpm_wakeref_asserts(uncore->rpm); 2448 break; 2449 case MBI_PMIC_BUS_ACCESS_END: 2450 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 2451 break; 2452 } 2453 2454 return NOTIFY_OK; 2455 } 2456 2457 static void uncore_unmap_mmio(struct drm_device *drm, void *regs) 2458 { 2459 iounmap(regs); 2460 } 2461 2462 int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) 2463 { 2464 struct drm_i915_private *i915 = uncore->i915; 2465 int mmio_size; 2466 2467 /* 2468 * Before gen4, the registers and the GTT are behind different BARs. 2469 * However, from gen4 onwards, the registers and the GTT are shared 2470 * in the same BAR, so we want to restrict this ioremap from 2471 * clobbering the GTT which we want ioremap_wc instead. Fortunately, 2472 * the register BAR remains the same size for all the earlier 2473 * generations up to Ironlake. 2474 * For dgfx chips register range is expanded to 4MB, and this larger 2475 * range is also used for integrated gpus beginning with Meteor Lake. 2476 */ 2477 if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 2478 mmio_size = 4 * 1024 * 1024; 2479 else if (GRAPHICS_VER(i915) >= 5) 2480 mmio_size = 2 * 1024 * 1024; 2481 else 2482 mmio_size = 512 * 1024; 2483 2484 uncore->regs = ioremap(phys_addr, mmio_size); 2485 if (uncore->regs == NULL) { 2486 drm_err(&i915->drm, "failed to map registers\n"); 2487 return -EIO; 2488 } 2489 2490 return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio, uncore->regs); 2491 } 2492 2493 void intel_uncore_init_early(struct intel_uncore *uncore, 2494 struct intel_gt *gt) 2495 { 2496 spin_lock_init(&uncore->lock); 2497 uncore->i915 = gt->i915; 2498 uncore->gt = gt; 2499 uncore->rpm = >->i915->runtime_pm; 2500 } 2501 2502 static void uncore_raw_init(struct intel_uncore *uncore) 2503 { 2504 GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); 2505 2506 if (intel_vgpu_active(uncore->i915)) { 2507 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu); 2508 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu); 2509 } else if (GRAPHICS_VER(uncore->i915) == 5) { 2510 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); 2511 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); 2512 } else { 2513 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); 2514 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); 2515 } 2516 } 2517 2518 static int uncore_media_forcewake_init(struct intel_uncore *uncore) 2519 { 2520 struct drm_i915_private *i915 = uncore->i915; 2521 2522 if (MEDIA_VER(i915) >= 13) { 2523 ASSIGN_FW_DOMAINS_TABLE(uncore, __xelpmp_fw_ranges); 2524 ASSIGN_SHADOW_TABLE(uncore, xelpmp_shadowed_regs); 2525 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2526 } else { 2527 MISSING_CASE(MEDIA_VER(i915)); 2528 return -ENODEV; 2529 } 2530 2531 return 0; 2532 } 2533 2534 static int uncore_forcewake_init(struct intel_uncore *uncore) 2535 { 2536 struct drm_i915_private *i915 = uncore->i915; 2537 int ret; 2538 2539 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2540 2541 ret = intel_uncore_fw_domains_init(uncore); 2542 if (ret) 2543 return ret; 2544 forcewake_early_sanitize(uncore, 0); 2545 2546 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 2547 2548 if (uncore->gt->type == GT_MEDIA) 2549 return uncore_media_forcewake_init(uncore); 2550 2551 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { 2552 ASSIGN_FW_DOMAINS_TABLE(uncore, __mtl_fw_ranges); 2553 ASSIGN_SHADOW_TABLE(uncore, mtl_shadowed_regs); 2554 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2555 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) { 2556 ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges); 2557 ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs); 2558 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2559 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 2560 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges); 2561 ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs); 2562 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2563 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 2564 ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges); 2565 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); 2566 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2567 } else if (GRAPHICS_VER(i915) >= 12) { 2568 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); 2569 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); 2570 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2571 } else if (GRAPHICS_VER(i915) == 11) { 2572 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); 2573 ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs); 2574 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2575 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2576 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); 2577 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2578 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2579 } else if (IS_CHERRYVIEW(i915)) { 2580 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); 2581 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2582 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2583 } else if (GRAPHICS_VER(i915) == 8) { 2584 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); 2585 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2586 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2587 } else if (IS_VALLEYVIEW(i915)) { 2588 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); 2589 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2590 } else if (IS_GRAPHICS_VER(i915, 6, 7)) { 2591 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); 2592 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2593 } 2594 2595 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; 2596 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 2597 2598 return 0; 2599 } 2600 2601 int intel_uncore_init_mmio(struct intel_uncore *uncore) 2602 { 2603 struct drm_i915_private *i915 = uncore->i915; 2604 int ret; 2605 2606 /* 2607 * The boot firmware initializes local memory and assesses its health. 2608 * If memory training fails, the punit will have been instructed to 2609 * keep the GT powered down; we won't be able to communicate with it 2610 * and we should not continue with driver initialization. 2611 */ 2612 if (IS_DGFX(i915) && 2613 !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) { 2614 drm_err(&i915->drm, "LMEM not initialized by firmware\n"); 2615 return -ENODEV; 2616 } 2617 2618 if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915)) 2619 uncore->flags |= UNCORE_HAS_FORCEWAKE; 2620 2621 if (!intel_uncore_has_forcewake(uncore)) { 2622 uncore_raw_init(uncore); 2623 } else { 2624 ret = uncore_forcewake_init(uncore); 2625 if (ret) 2626 return ret; 2627 } 2628 2629 /* make sure fw funcs are set if and only if we have fw*/ 2630 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs); 2631 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); 2632 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); 2633 2634 if (HAS_FPGA_DBG_UNCLAIMED(i915)) 2635 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; 2636 2637 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 2638 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; 2639 2640 if (IS_GRAPHICS_VER(i915, 6, 7)) 2641 uncore->flags |= UNCORE_HAS_FIFO; 2642 2643 /* clear out unclaimed reg detection bit */ 2644 if (intel_uncore_unclaimed_mmio(uncore)) 2645 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n"); 2646 2647 return 0; 2648 } 2649 2650 /* 2651 * We might have detected that some engines are fused off after we initialized 2652 * the forcewake domains. Prune them, to make sure they only reference existing 2653 * engines. 2654 */ 2655 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, 2656 struct intel_gt *gt) 2657 { 2658 enum forcewake_domains fw_domains = uncore->fw_domains; 2659 enum forcewake_domain_id domain_id; 2660 int i; 2661 2662 if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11) 2663 return; 2664 2665 for (i = 0; i < I915_MAX_VCS; i++) { 2666 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; 2667 2668 if (HAS_ENGINE(gt, _VCS(i))) 2669 continue; 2670 2671 /* 2672 * Starting with XeHP, the power well for an even-numbered 2673 * VDBOX is also used for shared units within the 2674 * media slice such as SFC. So even if the engine 2675 * itself is fused off, we still need to initialize 2676 * the forcewake domain if any of the other engines 2677 * in the same media slice are present. 2678 */ 2679 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) { 2680 if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1))) 2681 continue; 2682 2683 if (HAS_ENGINE(gt, _VECS(i / 2))) 2684 continue; 2685 } 2686 2687 if (fw_domains & BIT(domain_id)) 2688 fw_domain_fini(uncore, domain_id); 2689 } 2690 2691 for (i = 0; i < I915_MAX_VECS; i++) { 2692 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; 2693 2694 if (HAS_ENGINE(gt, _VECS(i))) 2695 continue; 2696 2697 if (fw_domains & BIT(domain_id)) 2698 fw_domain_fini(uncore, domain_id); 2699 } 2700 } 2701 2702 /* Called via drm-managed action */ 2703 void intel_uncore_fini_mmio(struct drm_device *dev, void *data) 2704 { 2705 struct intel_uncore *uncore = data; 2706 2707 if (intel_uncore_has_forcewake(uncore)) { 2708 iosf_mbi_punit_acquire(); 2709 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 2710 &uncore->pmic_bus_access_nb); 2711 intel_uncore_forcewake_reset(uncore); 2712 intel_uncore_fw_domains_fini(uncore); 2713 iosf_mbi_punit_release(); 2714 } 2715 } 2716 2717 /** 2718 * __intel_wait_for_register_fw - wait until register matches expected state 2719 * @uncore: the struct intel_uncore 2720 * @reg: the register to read 2721 * @mask: mask to apply to register value 2722 * @value: expected value 2723 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2724 * @slow_timeout_ms: slow timeout in millisecond 2725 * @out_value: optional placeholder to hold registry value 2726 * 2727 * This routine waits until the target register @reg contains the expected 2728 * @value after applying the @mask, i.e. it waits until :: 2729 * 2730 * (intel_uncore_read_fw(uncore, reg) & mask) == value 2731 * 2732 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 2733 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 2734 * must be not larger than 20,0000 microseconds. 2735 * 2736 * Note that this routine assumes the caller holds forcewake asserted, it is 2737 * not suitable for very long waits. See intel_wait_for_register() if you 2738 * wish to wait without holding forcewake for the duration (i.e. you expect 2739 * the wait to be slow). 2740 * 2741 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2742 */ 2743 int __intel_wait_for_register_fw(struct intel_uncore *uncore, 2744 i915_reg_t reg, 2745 u32 mask, 2746 u32 value, 2747 unsigned int fast_timeout_us, 2748 unsigned int slow_timeout_ms, 2749 u32 *out_value) 2750 { 2751 u32 reg_value = 0; 2752 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) 2753 int ret; 2754 2755 /* Catch any overuse of this function */ 2756 might_sleep_if(slow_timeout_ms); 2757 GEM_BUG_ON(fast_timeout_us > 20000); 2758 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms); 2759 2760 ret = -ETIMEDOUT; 2761 if (fast_timeout_us && fast_timeout_us <= 20000) 2762 ret = _wait_for_atomic(done, fast_timeout_us, 0); 2763 if (ret && slow_timeout_ms) 2764 ret = wait_for(done, slow_timeout_ms); 2765 2766 if (out_value) 2767 *out_value = reg_value; 2768 2769 return ret; 2770 #undef done 2771 } 2772 2773 /** 2774 * __intel_wait_for_register - wait until register matches expected state 2775 * @uncore: the struct intel_uncore 2776 * @reg: the register to read 2777 * @mask: mask to apply to register value 2778 * @value: expected value 2779 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2780 * @slow_timeout_ms: slow timeout in millisecond 2781 * @out_value: optional placeholder to hold registry value 2782 * 2783 * This routine waits until the target register @reg contains the expected 2784 * @value after applying the @mask, i.e. it waits until :: 2785 * 2786 * (intel_uncore_read(uncore, reg) & mask) == value 2787 * 2788 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 2789 * 2790 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2791 */ 2792 int __intel_wait_for_register(struct intel_uncore *uncore, 2793 i915_reg_t reg, 2794 u32 mask, 2795 u32 value, 2796 unsigned int fast_timeout_us, 2797 unsigned int slow_timeout_ms, 2798 u32 *out_value) 2799 { 2800 unsigned fw = 2801 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 2802 u32 reg_value; 2803 int ret; 2804 2805 might_sleep_if(slow_timeout_ms); 2806 2807 spin_lock_irq(&uncore->lock); 2808 intel_uncore_forcewake_get__locked(uncore, fw); 2809 2810 ret = __intel_wait_for_register_fw(uncore, 2811 reg, mask, value, 2812 fast_timeout_us, 0, ®_value); 2813 2814 intel_uncore_forcewake_put__locked(uncore, fw); 2815 spin_unlock_irq(&uncore->lock); 2816 2817 if (ret && slow_timeout_ms) 2818 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, 2819 reg), 2820 (reg_value & mask) == value, 2821 slow_timeout_ms * 1000, 10, 1000); 2822 2823 /* just trace the final value */ 2824 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 2825 2826 if (out_value) 2827 *out_value = reg_value; 2828 2829 return ret; 2830 } 2831 2832 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) 2833 { 2834 bool ret; 2835 2836 if (!uncore->debug) 2837 return false; 2838 2839 spin_lock_irq(&uncore->debug->lock); 2840 ret = check_for_unclaimed_mmio(uncore); 2841 spin_unlock_irq(&uncore->debug->lock); 2842 2843 return ret; 2844 } 2845 2846 bool 2847 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) 2848 { 2849 bool ret = false; 2850 2851 if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug)) 2852 return false; 2853 2854 spin_lock_irq(&uncore->debug->lock); 2855 2856 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) 2857 goto out; 2858 2859 if (unlikely(check_for_unclaimed_mmio(uncore))) { 2860 if (!uncore->i915->params.mmio_debug) { 2861 drm_dbg(&uncore->i915->drm, 2862 "Unclaimed register detected, " 2863 "enabling oneshot unclaimed register reporting. " 2864 "Please use i915.mmio_debug=N for more information.\n"); 2865 uncore->i915->params.mmio_debug++; 2866 } 2867 uncore->debug->unclaimed_mmio_check--; 2868 ret = true; 2869 } 2870 2871 out: 2872 spin_unlock_irq(&uncore->debug->lock); 2873 2874 return ret; 2875 } 2876 2877 /** 2878 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 2879 * a register 2880 * @uncore: pointer to struct intel_uncore 2881 * @reg: register in question 2882 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 2883 * 2884 * Returns a set of forcewake domains required to be taken with for example 2885 * intel_uncore_forcewake_get for the specified register to be accessible in the 2886 * specified mode (read, write or read/write) with raw mmio accessors. 2887 * 2888 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 2889 * callers to do FIFO management on their own or risk losing writes. 2890 */ 2891 enum forcewake_domains 2892 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 2893 i915_reg_t reg, unsigned int op) 2894 { 2895 enum forcewake_domains fw_domains = 0; 2896 2897 drm_WARN_ON(&uncore->i915->drm, !op); 2898 2899 if (!intel_uncore_has_forcewake(uncore)) 2900 return 0; 2901 2902 if (op & FW_REG_READ) 2903 fw_domains = uncore->funcs.read_fw_domains(uncore, reg); 2904 2905 if (op & FW_REG_WRITE) 2906 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); 2907 2908 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains); 2909 2910 return fw_domains; 2911 } 2912 2913 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2914 #include "selftests/mock_uncore.c" 2915 #include "selftests/intel_uncore.c" 2916 #endif 2917