1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_drv.h" 26 #include "i915_vgpu.h" 27 28 #include <linux/pm_runtime.h> 29 30 #define FORCEWAKE_ACK_TIMEOUT_MS 50 31 32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) 33 34 static const char * const forcewake_domain_names[] = { 35 "render", 36 "blitter", 37 "media", 38 }; 39 40 const char * 41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 42 { 43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 44 45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 46 return forcewake_domain_names[id]; 47 48 WARN_ON(id); 49 50 return "unknown"; 51 } 52 53 static inline void 54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 55 { 56 WARN_ON(!i915_mmio_reg_valid(d->reg_set)); 57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset); 58 } 59 60 static inline void 61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 62 { 63 d->wake_count++; 64 hrtimer_start_range_ns(&d->timer, 65 ktime_set(0, NSEC_PER_MSEC), 66 NSEC_PER_MSEC, 67 HRTIMER_MODE_REL); 68 } 69 70 static inline void 71 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 72 { 73 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & 74 FORCEWAKE_KERNEL) == 0, 75 FORCEWAKE_ACK_TIMEOUT_MS)) 76 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 77 intel_uncore_forcewake_domain_to_str(d->id)); 78 } 79 80 static inline void 81 fw_domain_get(const struct intel_uncore_forcewake_domain *d) 82 { 83 __raw_i915_write32(d->i915, d->reg_set, d->val_set); 84 } 85 86 static inline void 87 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) 88 { 89 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & 90 FORCEWAKE_KERNEL), 91 FORCEWAKE_ACK_TIMEOUT_MS)) 92 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 93 intel_uncore_forcewake_domain_to_str(d->id)); 94 } 95 96 static inline void 97 fw_domain_put(const struct intel_uncore_forcewake_domain *d) 98 { 99 __raw_i915_write32(d->i915, d->reg_set, d->val_clear); 100 } 101 102 static inline void 103 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) 104 { 105 /* something from same cacheline, but not from the set register */ 106 if (i915_mmio_reg_valid(d->reg_post)) 107 __raw_posting_read(d->i915, d->reg_post); 108 } 109 110 static void 111 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) 112 { 113 struct intel_uncore_forcewake_domain *d; 114 115 for_each_fw_domain_masked(d, fw_domains, dev_priv) { 116 fw_domain_wait_ack_clear(d); 117 fw_domain_get(d); 118 } 119 120 for_each_fw_domain_masked(d, fw_domains, dev_priv) 121 fw_domain_wait_ack(d); 122 } 123 124 static void 125 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) 126 { 127 struct intel_uncore_forcewake_domain *d; 128 129 for_each_fw_domain_masked(d, fw_domains, dev_priv) { 130 fw_domain_put(d); 131 fw_domain_posting_read(d); 132 } 133 } 134 135 static void 136 fw_domains_posting_read(struct drm_i915_private *dev_priv) 137 { 138 struct intel_uncore_forcewake_domain *d; 139 140 /* No need to do for all, just do for first found */ 141 for_each_fw_domain(d, dev_priv) { 142 fw_domain_posting_read(d); 143 break; 144 } 145 } 146 147 static void 148 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) 149 { 150 struct intel_uncore_forcewake_domain *d; 151 152 if (dev_priv->uncore.fw_domains == 0) 153 return; 154 155 for_each_fw_domain_masked(d, fw_domains, dev_priv) 156 fw_domain_reset(d); 157 158 fw_domains_posting_read(dev_priv); 159 } 160 161 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 162 { 163 /* w/a for a sporadic read returning 0 by waiting for the GT 164 * thread to wake up. 165 */ 166 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & 167 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) 168 DRM_ERROR("GT thread status wait timed out\n"); 169 } 170 171 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, 172 enum forcewake_domains fw_domains) 173 { 174 fw_domains_get(dev_priv, fw_domains); 175 176 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 177 __gen6_gt_wait_for_thread_c0(dev_priv); 178 } 179 180 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 181 { 182 u32 gtfifodbg; 183 184 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); 185 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) 186 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); 187 } 188 189 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, 190 enum forcewake_domains fw_domains) 191 { 192 fw_domains_put(dev_priv, fw_domains); 193 gen6_gt_check_fifodbg(dev_priv); 194 } 195 196 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) 197 { 198 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); 199 200 return count & GT_FIFO_FREE_ENTRIES_MASK; 201 } 202 203 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 204 { 205 int ret = 0; 206 207 /* On VLV, FIFO will be shared by both SW and HW. 208 * So, we need to read the FREE_ENTRIES everytime */ 209 if (IS_VALLEYVIEW(dev_priv)) 210 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); 211 212 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 213 int loop = 500; 214 u32 fifo = fifo_free_entries(dev_priv); 215 216 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 217 udelay(10); 218 fifo = fifo_free_entries(dev_priv); 219 } 220 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 221 ++ret; 222 dev_priv->uncore.fifo_count = fifo; 223 } 224 dev_priv->uncore.fifo_count--; 225 226 return ret; 227 } 228 229 static enum hrtimer_restart 230 intel_uncore_fw_release_timer(struct hrtimer *timer) 231 { 232 struct intel_uncore_forcewake_domain *domain = 233 container_of(timer, struct intel_uncore_forcewake_domain, timer); 234 unsigned long irqflags; 235 236 assert_rpm_device_not_suspended(domain->i915); 237 238 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); 239 if (WARN_ON(domain->wake_count == 0)) 240 domain->wake_count++; 241 242 if (--domain->wake_count == 0) 243 domain->i915->uncore.funcs.force_wake_put(domain->i915, 244 1 << domain->id); 245 246 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); 247 248 return HRTIMER_NORESTART; 249 } 250 251 void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, 252 bool restore) 253 { 254 unsigned long irqflags; 255 struct intel_uncore_forcewake_domain *domain; 256 int retry_count = 100; 257 enum forcewake_domains fw = 0, active_domains; 258 259 /* Hold uncore.lock across reset to prevent any register access 260 * with forcewake not set correctly. Wait until all pending 261 * timers are run before holding. 262 */ 263 while (1) { 264 active_domains = 0; 265 266 for_each_fw_domain(domain, dev_priv) { 267 if (hrtimer_cancel(&domain->timer) == 0) 268 continue; 269 270 intel_uncore_fw_release_timer(&domain->timer); 271 } 272 273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 274 275 for_each_fw_domain(domain, dev_priv) { 276 if (hrtimer_active(&domain->timer)) 277 active_domains |= domain->mask; 278 } 279 280 if (active_domains == 0) 281 break; 282 283 if (--retry_count == 0) { 284 DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); 285 break; 286 } 287 288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 289 cond_resched(); 290 } 291 292 WARN_ON(active_domains); 293 294 for_each_fw_domain(domain, dev_priv) 295 if (domain->wake_count) 296 fw |= domain->mask; 297 298 if (fw) 299 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); 300 301 fw_domains_reset(dev_priv, FORCEWAKE_ALL); 302 303 if (restore) { /* If reset with a user forcewake, try to restore */ 304 if (fw) 305 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); 306 307 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) 308 dev_priv->uncore.fifo_count = 309 fifo_free_entries(dev_priv); 310 } 311 312 if (!restore) 313 assert_forcewakes_inactive(dev_priv); 314 315 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 316 } 317 318 static u64 gen9_edram_size(struct drm_i915_private *dev_priv) 319 { 320 const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; 321 const unsigned int sets[4] = { 1, 1, 2, 2 }; 322 const u32 cap = dev_priv->edram_cap; 323 324 return EDRAM_NUM_BANKS(cap) * 325 ways[EDRAM_WAYS_IDX(cap)] * 326 sets[EDRAM_SETS_IDX(cap)] * 327 1024 * 1024; 328 } 329 330 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) 331 { 332 if (!HAS_EDRAM(dev_priv)) 333 return 0; 334 335 /* The needed capability bits for size calculation 336 * are not there with pre gen9 so return 128MB always. 337 */ 338 if (INTEL_GEN(dev_priv) < 9) 339 return 128 * 1024 * 1024; 340 341 return gen9_edram_size(dev_priv); 342 } 343 344 static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) 345 { 346 if (IS_HASWELL(dev_priv) || 347 IS_BROADWELL(dev_priv) || 348 INTEL_GEN(dev_priv) >= 9) { 349 dev_priv->edram_cap = __raw_i915_read32(dev_priv, 350 HSW_EDRAM_CAP); 351 352 /* NB: We can't write IDICR yet because we do not have gt funcs 353 * set up */ 354 } else { 355 dev_priv->edram_cap = 0; 356 } 357 358 if (HAS_EDRAM(dev_priv)) 359 DRM_INFO("Found %lluMB of eDRAM\n", 360 intel_uncore_edram_size(dev_priv) / (1024 * 1024)); 361 } 362 363 static bool 364 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 365 { 366 u32 dbg; 367 368 dbg = __raw_i915_read32(dev_priv, FPGA_DBG); 369 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 370 return false; 371 372 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 373 374 return true; 375 } 376 377 static bool 378 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 379 { 380 u32 cer; 381 382 cer = __raw_i915_read32(dev_priv, CLAIM_ER); 383 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 384 return false; 385 386 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); 387 388 return true; 389 } 390 391 static bool 392 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) 393 { 394 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) 395 return fpga_check_for_unclaimed_mmio(dev_priv); 396 397 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 398 return vlv_check_for_unclaimed_mmio(dev_priv); 399 400 return false; 401 } 402 403 static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, 404 bool restore_forcewake) 405 { 406 /* clear out unclaimed reg detection bit */ 407 if (check_for_unclaimed_mmio(dev_priv)) 408 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); 409 410 /* clear out old GT FIFO errors */ 411 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) 412 __raw_i915_write32(dev_priv, GTFIFODBG, 413 __raw_i915_read32(dev_priv, GTFIFODBG)); 414 415 /* WaDisableShadowRegForCpd:chv */ 416 if (IS_CHERRYVIEW(dev_priv)) { 417 __raw_i915_write32(dev_priv, GTFIFOCTL, 418 __raw_i915_read32(dev_priv, GTFIFOCTL) | 419 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 420 GT_FIFO_CTL_RC6_POLICY_STALL); 421 } 422 423 intel_uncore_forcewake_reset(dev_priv, restore_forcewake); 424 } 425 426 void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, 427 bool restore_forcewake) 428 { 429 __intel_uncore_early_sanitize(dev_priv, restore_forcewake); 430 i915_check_and_clear_faults(dev_priv); 431 } 432 433 void intel_uncore_sanitize(struct drm_i915_private *dev_priv) 434 { 435 i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6); 436 437 /* BIOS often leaves RC6 enabled, but disable it for hw init */ 438 intel_disable_gt_powersave(dev_priv); 439 } 440 441 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 442 enum forcewake_domains fw_domains) 443 { 444 struct intel_uncore_forcewake_domain *domain; 445 446 if (!dev_priv->uncore.funcs.force_wake_get) 447 return; 448 449 fw_domains &= dev_priv->uncore.fw_domains; 450 451 for_each_fw_domain_masked(domain, fw_domains, dev_priv) { 452 if (domain->wake_count++) 453 fw_domains &= ~domain->mask; 454 } 455 456 if (fw_domains) 457 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); 458 } 459 460 /** 461 * intel_uncore_forcewake_get - grab forcewake domain references 462 * @dev_priv: i915 device instance 463 * @fw_domains: forcewake domains to get reference on 464 * 465 * This function can be used get GT's forcewake domain references. 466 * Normal register access will handle the forcewake domains automatically. 467 * However if some sequence requires the GT to not power down a particular 468 * forcewake domains this function should be called at the beginning of the 469 * sequence. And subsequently the reference should be dropped by symmetric 470 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 471 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 472 */ 473 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, 474 enum forcewake_domains fw_domains) 475 { 476 unsigned long irqflags; 477 478 if (!dev_priv->uncore.funcs.force_wake_get) 479 return; 480 481 assert_rpm_wakelock_held(dev_priv); 482 483 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 484 __intel_uncore_forcewake_get(dev_priv, fw_domains); 485 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 486 } 487 488 /** 489 * intel_uncore_forcewake_get__locked - grab forcewake domain references 490 * @dev_priv: i915 device instance 491 * @fw_domains: forcewake domains to get reference on 492 * 493 * See intel_uncore_forcewake_get(). This variant places the onus 494 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 495 */ 496 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, 497 enum forcewake_domains fw_domains) 498 { 499 assert_spin_locked(&dev_priv->uncore.lock); 500 501 if (!dev_priv->uncore.funcs.force_wake_get) 502 return; 503 504 __intel_uncore_forcewake_get(dev_priv, fw_domains); 505 } 506 507 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 508 enum forcewake_domains fw_domains) 509 { 510 struct intel_uncore_forcewake_domain *domain; 511 512 if (!dev_priv->uncore.funcs.force_wake_put) 513 return; 514 515 fw_domains &= dev_priv->uncore.fw_domains; 516 517 for_each_fw_domain_masked(domain, fw_domains, dev_priv) { 518 if (WARN_ON(domain->wake_count == 0)) 519 continue; 520 521 if (--domain->wake_count) 522 continue; 523 524 fw_domain_arm_timer(domain); 525 } 526 } 527 528 /** 529 * intel_uncore_forcewake_put - release a forcewake domain reference 530 * @dev_priv: i915 device instance 531 * @fw_domains: forcewake domains to put references 532 * 533 * This function drops the device-level forcewakes for specified 534 * domains obtained by intel_uncore_forcewake_get(). 535 */ 536 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, 537 enum forcewake_domains fw_domains) 538 { 539 unsigned long irqflags; 540 541 if (!dev_priv->uncore.funcs.force_wake_put) 542 return; 543 544 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 545 __intel_uncore_forcewake_put(dev_priv, fw_domains); 546 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 547 } 548 549 /** 550 * intel_uncore_forcewake_put__locked - grab forcewake domain references 551 * @dev_priv: i915 device instance 552 * @fw_domains: forcewake domains to get reference on 553 * 554 * See intel_uncore_forcewake_put(). This variant places the onus 555 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 556 */ 557 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, 558 enum forcewake_domains fw_domains) 559 { 560 assert_spin_locked(&dev_priv->uncore.lock); 561 562 if (!dev_priv->uncore.funcs.force_wake_put) 563 return; 564 565 __intel_uncore_forcewake_put(dev_priv, fw_domains); 566 } 567 568 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) 569 { 570 struct intel_uncore_forcewake_domain *domain; 571 572 if (!dev_priv->uncore.funcs.force_wake_get) 573 return; 574 575 for_each_fw_domain(domain, dev_priv) 576 WARN_ON(domain->wake_count); 577 } 578 579 /* We give fast paths for the really cool registers */ 580 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) 581 582 #define __gen6_reg_read_fw_domains(offset) \ 583 ({ \ 584 enum forcewake_domains __fwd; \ 585 if (NEEDS_FORCE_WAKE(offset)) \ 586 __fwd = FORCEWAKE_RENDER; \ 587 else \ 588 __fwd = 0; \ 589 __fwd; \ 590 }) 591 592 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) 593 594 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ 595 (REG_RANGE((reg), 0x2000, 0x4000) || \ 596 REG_RANGE((reg), 0x5000, 0x8000) || \ 597 REG_RANGE((reg), 0xB000, 0x12000) || \ 598 REG_RANGE((reg), 0x2E000, 0x30000)) 599 600 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ 601 (REG_RANGE((reg), 0x12000, 0x14000) || \ 602 REG_RANGE((reg), 0x22000, 0x24000) || \ 603 REG_RANGE((reg), 0x30000, 0x40000)) 604 605 #define __vlv_reg_read_fw_domains(offset) \ 606 ({ \ 607 enum forcewake_domains __fwd = 0; \ 608 if (!NEEDS_FORCE_WAKE(offset)) \ 609 __fwd = 0; \ 610 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \ 611 __fwd = FORCEWAKE_RENDER; \ 612 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \ 613 __fwd = FORCEWAKE_MEDIA; \ 614 __fwd; \ 615 }) 616 617 static const i915_reg_t gen8_shadowed_regs[] = { 618 GEN6_RPNSWREQ, 619 GEN6_RC_VIDEO_FREQ, 620 RING_TAIL(RENDER_RING_BASE), 621 RING_TAIL(GEN6_BSD_RING_BASE), 622 RING_TAIL(VEBOX_RING_BASE), 623 RING_TAIL(BLT_RING_BASE), 624 /* TODO: Other registers are not yet used */ 625 }; 626 627 static bool is_gen8_shadowed(u32 offset) 628 { 629 int i; 630 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) 631 if (offset == gen8_shadowed_regs[i].reg) 632 return true; 633 634 return false; 635 } 636 637 #define __gen8_reg_write_fw_domains(offset) \ 638 ({ \ 639 enum forcewake_domains __fwd; \ 640 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ 641 __fwd = FORCEWAKE_RENDER; \ 642 else \ 643 __fwd = 0; \ 644 __fwd; \ 645 }) 646 647 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ 648 (REG_RANGE((reg), 0x2000, 0x4000) || \ 649 REG_RANGE((reg), 0x5200, 0x8000) || \ 650 REG_RANGE((reg), 0x8300, 0x8500) || \ 651 REG_RANGE((reg), 0xB000, 0xB480) || \ 652 REG_RANGE((reg), 0xE000, 0xE800)) 653 654 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ 655 (REG_RANGE((reg), 0x8800, 0x8900) || \ 656 REG_RANGE((reg), 0xD000, 0xD800) || \ 657 REG_RANGE((reg), 0x12000, 0x14000) || \ 658 REG_RANGE((reg), 0x1A000, 0x1C000) || \ 659 REG_RANGE((reg), 0x1E800, 0x1EA00) || \ 660 REG_RANGE((reg), 0x30000, 0x38000)) 661 662 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ 663 (REG_RANGE((reg), 0x4000, 0x5000) || \ 664 REG_RANGE((reg), 0x8000, 0x8300) || \ 665 REG_RANGE((reg), 0x8500, 0x8600) || \ 666 REG_RANGE((reg), 0x9000, 0xB000) || \ 667 REG_RANGE((reg), 0xF000, 0x10000)) 668 669 #define __chv_reg_read_fw_domains(offset) \ 670 ({ \ 671 enum forcewake_domains __fwd = 0; \ 672 if (!NEEDS_FORCE_WAKE(offset)) \ 673 __fwd = 0; \ 674 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ 675 __fwd = FORCEWAKE_RENDER; \ 676 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ 677 __fwd = FORCEWAKE_MEDIA; \ 678 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ 679 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ 680 __fwd; \ 681 }) 682 683 #define __chv_reg_write_fw_domains(offset) \ 684 ({ \ 685 enum forcewake_domains __fwd = 0; \ 686 if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \ 687 __fwd = 0; \ 688 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ 689 __fwd = FORCEWAKE_RENDER; \ 690 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ 691 __fwd = FORCEWAKE_MEDIA; \ 692 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ 693 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ 694 __fwd; \ 695 }) 696 697 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ 698 REG_RANGE((reg), 0xB00, 0x2000) 699 700 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ 701 (REG_RANGE((reg), 0x2000, 0x2700) || \ 702 REG_RANGE((reg), 0x3000, 0x4000) || \ 703 REG_RANGE((reg), 0x5200, 0x8000) || \ 704 REG_RANGE((reg), 0x8140, 0x8160) || \ 705 REG_RANGE((reg), 0x8300, 0x8500) || \ 706 REG_RANGE((reg), 0x8C00, 0x8D00) || \ 707 REG_RANGE((reg), 0xB000, 0xB480) || \ 708 REG_RANGE((reg), 0xE000, 0xE900) || \ 709 REG_RANGE((reg), 0x24400, 0x24800)) 710 711 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ 712 (REG_RANGE((reg), 0x8130, 0x8140) || \ 713 REG_RANGE((reg), 0x8800, 0x8A00) || \ 714 REG_RANGE((reg), 0xD000, 0xD800) || \ 715 REG_RANGE((reg), 0x12000, 0x14000) || \ 716 REG_RANGE((reg), 0x1A000, 0x1EA00) || \ 717 REG_RANGE((reg), 0x30000, 0x40000)) 718 719 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ 720 REG_RANGE((reg), 0x9400, 0x9800) 721 722 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ 723 ((reg) < 0x40000 && \ 724 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ 725 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ 726 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ 727 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) 728 729 #define SKL_NEEDS_FORCE_WAKE(reg) \ 730 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) 731 732 #define __gen9_reg_read_fw_domains(offset) \ 733 ({ \ 734 enum forcewake_domains __fwd; \ 735 if (!SKL_NEEDS_FORCE_WAKE(offset)) \ 736 __fwd = 0; \ 737 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ 738 __fwd = FORCEWAKE_RENDER; \ 739 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ 740 __fwd = FORCEWAKE_MEDIA; \ 741 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ 742 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ 743 else \ 744 __fwd = FORCEWAKE_BLITTER; \ 745 __fwd; \ 746 }) 747 748 static const i915_reg_t gen9_shadowed_regs[] = { 749 RING_TAIL(RENDER_RING_BASE), 750 RING_TAIL(GEN6_BSD_RING_BASE), 751 RING_TAIL(VEBOX_RING_BASE), 752 RING_TAIL(BLT_RING_BASE), 753 GEN6_RPNSWREQ, 754 GEN6_RC_VIDEO_FREQ, 755 /* TODO: Other registers are not yet used */ 756 }; 757 758 static bool is_gen9_shadowed(u32 offset) 759 { 760 int i; 761 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) 762 if (offset == gen9_shadowed_regs[i].reg) 763 return true; 764 765 return false; 766 } 767 768 #define __gen9_reg_write_fw_domains(offset) \ 769 ({ \ 770 enum forcewake_domains __fwd; \ 771 if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \ 772 __fwd = 0; \ 773 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ 774 __fwd = FORCEWAKE_RENDER; \ 775 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ 776 __fwd = FORCEWAKE_MEDIA; \ 777 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ 778 __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ 779 else \ 780 __fwd = FORCEWAKE_BLITTER; \ 781 __fwd; \ 782 }) 783 784 static void 785 ilk_dummy_write(struct drm_i915_private *dev_priv) 786 { 787 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 788 * the chip from rc6 before touching it for real. MI_MODE is masked, 789 * hence harmless to write 0 into. */ 790 __raw_i915_write32(dev_priv, MI_MODE, 0); 791 } 792 793 static void 794 __unclaimed_reg_debug(struct drm_i915_private *dev_priv, 795 const i915_reg_t reg, 796 const bool read, 797 const bool before) 798 { 799 if (WARN(check_for_unclaimed_mmio(dev_priv), 800 "Unclaimed register detected %s %s register 0x%x\n", 801 before ? "before" : "after", 802 read ? "reading" : "writing to", 803 i915_mmio_reg_offset(reg))) 804 i915.mmio_debug--; /* Only report the first N failures */ 805 } 806 807 static inline void 808 unclaimed_reg_debug(struct drm_i915_private *dev_priv, 809 const i915_reg_t reg, 810 const bool read, 811 const bool before) 812 { 813 if (likely(!i915.mmio_debug)) 814 return; 815 816 __unclaimed_reg_debug(dev_priv, reg, read, before); 817 } 818 819 #define GEN2_READ_HEADER(x) \ 820 u##x val = 0; \ 821 assert_rpm_wakelock_held(dev_priv); 822 823 #define GEN2_READ_FOOTER \ 824 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 825 return val 826 827 #define __gen2_read(x) \ 828 static u##x \ 829 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 830 GEN2_READ_HEADER(x); \ 831 val = __raw_i915_read##x(dev_priv, reg); \ 832 GEN2_READ_FOOTER; \ 833 } 834 835 #define __gen5_read(x) \ 836 static u##x \ 837 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 838 GEN2_READ_HEADER(x); \ 839 ilk_dummy_write(dev_priv); \ 840 val = __raw_i915_read##x(dev_priv, reg); \ 841 GEN2_READ_FOOTER; \ 842 } 843 844 __gen5_read(8) 845 __gen5_read(16) 846 __gen5_read(32) 847 __gen5_read(64) 848 __gen2_read(8) 849 __gen2_read(16) 850 __gen2_read(32) 851 __gen2_read(64) 852 853 #undef __gen5_read 854 #undef __gen2_read 855 856 #undef GEN2_READ_FOOTER 857 #undef GEN2_READ_HEADER 858 859 #define GEN6_READ_HEADER(x) \ 860 u32 offset = i915_mmio_reg_offset(reg); \ 861 unsigned long irqflags; \ 862 u##x val = 0; \ 863 assert_rpm_wakelock_held(dev_priv); \ 864 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ 865 unclaimed_reg_debug(dev_priv, reg, true, true) 866 867 #define GEN6_READ_FOOTER \ 868 unclaimed_reg_debug(dev_priv, reg, true, false); \ 869 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ 870 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 871 return val 872 873 static inline void __force_wake_auto(struct drm_i915_private *dev_priv, 874 enum forcewake_domains fw_domains) 875 { 876 struct intel_uncore_forcewake_domain *domain; 877 878 if (WARN_ON(!fw_domains)) 879 return; 880 881 /* Ideally GCC would be constant-fold and eliminate this loop */ 882 for_each_fw_domain_masked(domain, fw_domains, dev_priv) { 883 if (domain->wake_count) { 884 fw_domains &= ~domain->mask; 885 continue; 886 } 887 888 fw_domain_arm_timer(domain); 889 } 890 891 if (fw_domains) 892 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); 893 } 894 895 #define __gen6_read(x) \ 896 static u##x \ 897 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 898 enum forcewake_domains fw_engine; \ 899 GEN6_READ_HEADER(x); \ 900 fw_engine = __gen6_reg_read_fw_domains(offset); \ 901 if (fw_engine) \ 902 __force_wake_auto(dev_priv, fw_engine); \ 903 val = __raw_i915_read##x(dev_priv, reg); \ 904 GEN6_READ_FOOTER; \ 905 } 906 907 #define __vlv_read(x) \ 908 static u##x \ 909 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 910 enum forcewake_domains fw_engine; \ 911 GEN6_READ_HEADER(x); \ 912 fw_engine = __vlv_reg_read_fw_domains(offset); \ 913 if (fw_engine) \ 914 __force_wake_auto(dev_priv, fw_engine); \ 915 val = __raw_i915_read##x(dev_priv, reg); \ 916 GEN6_READ_FOOTER; \ 917 } 918 919 #define __chv_read(x) \ 920 static u##x \ 921 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 922 enum forcewake_domains fw_engine; \ 923 GEN6_READ_HEADER(x); \ 924 fw_engine = __chv_reg_read_fw_domains(offset); \ 925 if (fw_engine) \ 926 __force_wake_auto(dev_priv, fw_engine); \ 927 val = __raw_i915_read##x(dev_priv, reg); \ 928 GEN6_READ_FOOTER; \ 929 } 930 931 #define __gen9_read(x) \ 932 static u##x \ 933 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 934 enum forcewake_domains fw_engine; \ 935 GEN6_READ_HEADER(x); \ 936 fw_engine = __gen9_reg_read_fw_domains(offset); \ 937 if (fw_engine) \ 938 __force_wake_auto(dev_priv, fw_engine); \ 939 val = __raw_i915_read##x(dev_priv, reg); \ 940 GEN6_READ_FOOTER; \ 941 } 942 943 __gen9_read(8) 944 __gen9_read(16) 945 __gen9_read(32) 946 __gen9_read(64) 947 __chv_read(8) 948 __chv_read(16) 949 __chv_read(32) 950 __chv_read(64) 951 __vlv_read(8) 952 __vlv_read(16) 953 __vlv_read(32) 954 __vlv_read(64) 955 __gen6_read(8) 956 __gen6_read(16) 957 __gen6_read(32) 958 __gen6_read(64) 959 960 #undef __gen9_read 961 #undef __chv_read 962 #undef __vlv_read 963 #undef __gen6_read 964 #undef GEN6_READ_FOOTER 965 #undef GEN6_READ_HEADER 966 967 #define VGPU_READ_HEADER(x) \ 968 unsigned long irqflags; \ 969 u##x val = 0; \ 970 assert_rpm_device_not_suspended(dev_priv); \ 971 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) 972 973 #define VGPU_READ_FOOTER \ 974 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ 975 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 976 return val 977 978 #define __vgpu_read(x) \ 979 static u##x \ 980 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ 981 VGPU_READ_HEADER(x); \ 982 val = __raw_i915_read##x(dev_priv, reg); \ 983 VGPU_READ_FOOTER; \ 984 } 985 986 __vgpu_read(8) 987 __vgpu_read(16) 988 __vgpu_read(32) 989 __vgpu_read(64) 990 991 #undef __vgpu_read 992 #undef VGPU_READ_FOOTER 993 #undef VGPU_READ_HEADER 994 995 #define GEN2_WRITE_HEADER \ 996 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 997 assert_rpm_wakelock_held(dev_priv); \ 998 999 #define GEN2_WRITE_FOOTER 1000 1001 #define __gen2_write(x) \ 1002 static void \ 1003 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 1004 GEN2_WRITE_HEADER; \ 1005 __raw_i915_write##x(dev_priv, reg, val); \ 1006 GEN2_WRITE_FOOTER; \ 1007 } 1008 1009 #define __gen5_write(x) \ 1010 static void \ 1011 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 1012 GEN2_WRITE_HEADER; \ 1013 ilk_dummy_write(dev_priv); \ 1014 __raw_i915_write##x(dev_priv, reg, val); \ 1015 GEN2_WRITE_FOOTER; \ 1016 } 1017 1018 __gen5_write(8) 1019 __gen5_write(16) 1020 __gen5_write(32) 1021 __gen5_write(64) 1022 __gen2_write(8) 1023 __gen2_write(16) 1024 __gen2_write(32) 1025 __gen2_write(64) 1026 1027 #undef __gen5_write 1028 #undef __gen2_write 1029 1030 #undef GEN2_WRITE_FOOTER 1031 #undef GEN2_WRITE_HEADER 1032 1033 #define GEN6_WRITE_HEADER \ 1034 u32 offset = i915_mmio_reg_offset(reg); \ 1035 unsigned long irqflags; \ 1036 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1037 assert_rpm_wakelock_held(dev_priv); \ 1038 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ 1039 unclaimed_reg_debug(dev_priv, reg, false, true) 1040 1041 #define GEN6_WRITE_FOOTER \ 1042 unclaimed_reg_debug(dev_priv, reg, false, false); \ 1043 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) 1044 1045 #define __gen6_write(x) \ 1046 static void \ 1047 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 1048 u32 __fifo_ret = 0; \ 1049 GEN6_WRITE_HEADER; \ 1050 if (NEEDS_FORCE_WAKE(offset)) { \ 1051 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 1052 } \ 1053 __raw_i915_write##x(dev_priv, reg, val); \ 1054 if (unlikely(__fifo_ret)) { \ 1055 gen6_gt_check_fifodbg(dev_priv); \ 1056 } \ 1057 GEN6_WRITE_FOOTER; \ 1058 } 1059 1060 #define __hsw_write(x) \ 1061 static void \ 1062 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 1063 u32 __fifo_ret = 0; \ 1064 GEN6_WRITE_HEADER; \ 1065 if (NEEDS_FORCE_WAKE(offset)) { \ 1066 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 1067 } \ 1068 __raw_i915_write##x(dev_priv, reg, val); \ 1069 if (unlikely(__fifo_ret)) { \ 1070 gen6_gt_check_fifodbg(dev_priv); \ 1071 } \ 1072 GEN6_WRITE_FOOTER; \ 1073 } 1074 1075 #define __gen8_write(x) \ 1076 static void \ 1077 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 1078 enum forcewake_domains fw_engine; \ 1079 GEN6_WRITE_HEADER; \ 1080 fw_engine = __gen8_reg_write_fw_domains(offset); \ 1081 if (fw_engine) \ 1082 __force_wake_auto(dev_priv, fw_engine); \ 1083 __raw_i915_write##x(dev_priv, reg, val); \ 1084 GEN6_WRITE_FOOTER; \ 1085 } 1086 1087 #define __chv_write(x) \ 1088 static void \ 1089 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ 1090 enum forcewake_domains fw_engine; \ 1091 GEN6_WRITE_HEADER; \ 1092 fw_engine = __chv_reg_write_fw_domains(offset); \ 1093 if (fw_engine) \ 1094 __force_wake_auto(dev_priv, fw_engine); \ 1095 __raw_i915_write##x(dev_priv, reg, val); \ 1096 GEN6_WRITE_FOOTER; \ 1097 } 1098 1099 #define __gen9_write(x) \ 1100 static void \ 1101 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ 1102 bool trace) { \ 1103 enum forcewake_domains fw_engine; \ 1104 GEN6_WRITE_HEADER; \ 1105 fw_engine = __gen9_reg_write_fw_domains(offset); \ 1106 if (fw_engine) \ 1107 __force_wake_auto(dev_priv, fw_engine); \ 1108 __raw_i915_write##x(dev_priv, reg, val); \ 1109 GEN6_WRITE_FOOTER; \ 1110 } 1111 1112 __gen9_write(8) 1113 __gen9_write(16) 1114 __gen9_write(32) 1115 __gen9_write(64) 1116 __chv_write(8) 1117 __chv_write(16) 1118 __chv_write(32) 1119 __chv_write(64) 1120 __gen8_write(8) 1121 __gen8_write(16) 1122 __gen8_write(32) 1123 __gen8_write(64) 1124 __hsw_write(8) 1125 __hsw_write(16) 1126 __hsw_write(32) 1127 __hsw_write(64) 1128 __gen6_write(8) 1129 __gen6_write(16) 1130 __gen6_write(32) 1131 __gen6_write(64) 1132 1133 #undef __gen9_write 1134 #undef __chv_write 1135 #undef __gen8_write 1136 #undef __hsw_write 1137 #undef __gen6_write 1138 #undef GEN6_WRITE_FOOTER 1139 #undef GEN6_WRITE_HEADER 1140 1141 #define VGPU_WRITE_HEADER \ 1142 unsigned long irqflags; \ 1143 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1144 assert_rpm_device_not_suspended(dev_priv); \ 1145 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) 1146 1147 #define VGPU_WRITE_FOOTER \ 1148 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) 1149 1150 #define __vgpu_write(x) \ 1151 static void vgpu_write##x(struct drm_i915_private *dev_priv, \ 1152 i915_reg_t reg, u##x val, bool trace) { \ 1153 VGPU_WRITE_HEADER; \ 1154 __raw_i915_write##x(dev_priv, reg, val); \ 1155 VGPU_WRITE_FOOTER; \ 1156 } 1157 1158 __vgpu_write(8) 1159 __vgpu_write(16) 1160 __vgpu_write(32) 1161 __vgpu_write(64) 1162 1163 #undef __vgpu_write 1164 #undef VGPU_WRITE_FOOTER 1165 #undef VGPU_WRITE_HEADER 1166 1167 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ 1168 do { \ 1169 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ 1170 dev_priv->uncore.funcs.mmio_writew = x##_write16; \ 1171 dev_priv->uncore.funcs.mmio_writel = x##_write32; \ 1172 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ 1173 } while (0) 1174 1175 #define ASSIGN_READ_MMIO_VFUNCS(x) \ 1176 do { \ 1177 dev_priv->uncore.funcs.mmio_readb = x##_read8; \ 1178 dev_priv->uncore.funcs.mmio_readw = x##_read16; \ 1179 dev_priv->uncore.funcs.mmio_readl = x##_read32; \ 1180 dev_priv->uncore.funcs.mmio_readq = x##_read64; \ 1181 } while (0) 1182 1183 1184 static void fw_domain_init(struct drm_i915_private *dev_priv, 1185 enum forcewake_domain_id domain_id, 1186 i915_reg_t reg_set, 1187 i915_reg_t reg_ack) 1188 { 1189 struct intel_uncore_forcewake_domain *d; 1190 1191 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) 1192 return; 1193 1194 d = &dev_priv->uncore.fw_domain[domain_id]; 1195 1196 WARN_ON(d->wake_count); 1197 1198 d->wake_count = 0; 1199 d->reg_set = reg_set; 1200 d->reg_ack = reg_ack; 1201 1202 if (IS_GEN6(dev_priv)) { 1203 d->val_reset = 0; 1204 d->val_set = FORCEWAKE_KERNEL; 1205 d->val_clear = 0; 1206 } else { 1207 /* WaRsClearFWBitsAtReset:bdw,skl */ 1208 d->val_reset = _MASKED_BIT_DISABLE(0xffff); 1209 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); 1210 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); 1211 } 1212 1213 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1214 d->reg_post = FORCEWAKE_ACK_VLV; 1215 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) 1216 d->reg_post = ECOBUS; 1217 1218 d->i915 = dev_priv; 1219 d->id = domain_id; 1220 1221 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 1222 BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); 1223 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 1224 1225 d->mask = 1 << domain_id; 1226 1227 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1228 d->timer.function = intel_uncore_fw_release_timer; 1229 1230 dev_priv->uncore.fw_domains |= (1 << domain_id); 1231 1232 fw_domain_reset(d); 1233 } 1234 1235 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) 1236 { 1237 if (INTEL_INFO(dev_priv)->gen <= 5) 1238 return; 1239 1240 if (IS_GEN9(dev_priv)) { 1241 dev_priv->uncore.funcs.force_wake_get = fw_domains_get; 1242 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1243 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1244 FORCEWAKE_RENDER_GEN9, 1245 FORCEWAKE_ACK_RENDER_GEN9); 1246 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, 1247 FORCEWAKE_BLITTER_GEN9, 1248 FORCEWAKE_ACK_BLITTER_GEN9); 1249 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, 1250 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 1251 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1252 dev_priv->uncore.funcs.force_wake_get = fw_domains_get; 1253 if (!IS_CHERRYVIEW(dev_priv)) 1254 dev_priv->uncore.funcs.force_wake_put = 1255 fw_domains_put_with_fifo; 1256 else 1257 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1258 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1259 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 1260 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, 1261 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 1262 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1263 dev_priv->uncore.funcs.force_wake_get = 1264 fw_domains_get_with_thread_status; 1265 if (IS_HASWELL(dev_priv)) 1266 dev_priv->uncore.funcs.force_wake_put = 1267 fw_domains_put_with_fifo; 1268 else 1269 dev_priv->uncore.funcs.force_wake_put = fw_domains_put; 1270 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1271 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 1272 } else if (IS_IVYBRIDGE(dev_priv)) { 1273 u32 ecobus; 1274 1275 /* IVB configs may use multi-threaded forcewake */ 1276 1277 /* A small trick here - if the bios hasn't configured 1278 * MT forcewake, and if the device is in RC6, then 1279 * force_wake_mt_get will not wake the device and the 1280 * ECOBUS read will return zero. Which will be 1281 * (correctly) interpreted by the test below as MT 1282 * forcewake being disabled. 1283 */ 1284 dev_priv->uncore.funcs.force_wake_get = 1285 fw_domains_get_with_thread_status; 1286 dev_priv->uncore.funcs.force_wake_put = 1287 fw_domains_put_with_fifo; 1288 1289 /* We need to init first for ECOBUS access and then 1290 * determine later if we want to reinit, in case of MT access is 1291 * not working. In this stage we don't know which flavour this 1292 * ivb is, so it is better to reset also the gen6 fw registers 1293 * before the ecobus check. 1294 */ 1295 1296 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 1297 __raw_posting_read(dev_priv, ECOBUS); 1298 1299 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1300 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 1301 1302 spin_lock_irq(&dev_priv->uncore.lock); 1303 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); 1304 ecobus = __raw_i915_read32(dev_priv, ECOBUS); 1305 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); 1306 spin_unlock_irq(&dev_priv->uncore.lock); 1307 1308 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 1309 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); 1310 DRM_INFO("when using vblank-synced partial screen updates.\n"); 1311 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1312 FORCEWAKE, FORCEWAKE_ACK); 1313 } 1314 } else if (IS_GEN6(dev_priv)) { 1315 dev_priv->uncore.funcs.force_wake_get = 1316 fw_domains_get_with_thread_status; 1317 dev_priv->uncore.funcs.force_wake_put = 1318 fw_domains_put_with_fifo; 1319 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, 1320 FORCEWAKE, FORCEWAKE_ACK); 1321 } 1322 1323 /* All future platforms are expected to require complex power gating */ 1324 WARN_ON(dev_priv->uncore.fw_domains == 0); 1325 } 1326 1327 void intel_uncore_init(struct drm_i915_private *dev_priv) 1328 { 1329 i915_check_vgpu(dev_priv); 1330 1331 intel_uncore_edram_detect(dev_priv); 1332 intel_uncore_fw_domains_init(dev_priv); 1333 __intel_uncore_early_sanitize(dev_priv, false); 1334 1335 dev_priv->uncore.unclaimed_mmio_check = 1; 1336 1337 switch (INTEL_INFO(dev_priv)->gen) { 1338 default: 1339 case 9: 1340 ASSIGN_WRITE_MMIO_VFUNCS(gen9); 1341 ASSIGN_READ_MMIO_VFUNCS(gen9); 1342 break; 1343 case 8: 1344 if (IS_CHERRYVIEW(dev_priv)) { 1345 ASSIGN_WRITE_MMIO_VFUNCS(chv); 1346 ASSIGN_READ_MMIO_VFUNCS(chv); 1347 1348 } else { 1349 ASSIGN_WRITE_MMIO_VFUNCS(gen8); 1350 ASSIGN_READ_MMIO_VFUNCS(gen6); 1351 } 1352 break; 1353 case 7: 1354 case 6: 1355 if (IS_HASWELL(dev_priv)) { 1356 ASSIGN_WRITE_MMIO_VFUNCS(hsw); 1357 } else { 1358 ASSIGN_WRITE_MMIO_VFUNCS(gen6); 1359 } 1360 1361 if (IS_VALLEYVIEW(dev_priv)) { 1362 ASSIGN_READ_MMIO_VFUNCS(vlv); 1363 } else { 1364 ASSIGN_READ_MMIO_VFUNCS(gen6); 1365 } 1366 break; 1367 case 5: 1368 ASSIGN_WRITE_MMIO_VFUNCS(gen5); 1369 ASSIGN_READ_MMIO_VFUNCS(gen5); 1370 break; 1371 case 4: 1372 case 3: 1373 case 2: 1374 ASSIGN_WRITE_MMIO_VFUNCS(gen2); 1375 ASSIGN_READ_MMIO_VFUNCS(gen2); 1376 break; 1377 } 1378 1379 if (intel_vgpu_active(dev_priv)) { 1380 ASSIGN_WRITE_MMIO_VFUNCS(vgpu); 1381 ASSIGN_READ_MMIO_VFUNCS(vgpu); 1382 } 1383 1384 i915_check_and_clear_faults(dev_priv); 1385 } 1386 #undef ASSIGN_WRITE_MMIO_VFUNCS 1387 #undef ASSIGN_READ_MMIO_VFUNCS 1388 1389 void intel_uncore_fini(struct drm_i915_private *dev_priv) 1390 { 1391 /* Paranoia: make sure we have disabled everything before we exit. */ 1392 intel_uncore_sanitize(dev_priv); 1393 intel_uncore_forcewake_reset(dev_priv, false); 1394 } 1395 1396 #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1) 1397 1398 static const struct register_whitelist { 1399 i915_reg_t offset_ldw, offset_udw; 1400 uint32_t size; 1401 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ 1402 uint32_t gen_bitmask; 1403 } whitelist[] = { 1404 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), 1405 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), 1406 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, 1407 }; 1408 1409 int i915_reg_read_ioctl(struct drm_device *dev, 1410 void *data, struct drm_file *file) 1411 { 1412 struct drm_i915_private *dev_priv = to_i915(dev); 1413 struct drm_i915_reg_read *reg = data; 1414 struct register_whitelist const *entry = whitelist; 1415 unsigned size; 1416 i915_reg_t offset_ldw, offset_udw; 1417 int i, ret = 0; 1418 1419 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { 1420 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && 1421 (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask)) 1422 break; 1423 } 1424 1425 if (i == ARRAY_SIZE(whitelist)) 1426 return -EINVAL; 1427 1428 /* We use the low bits to encode extra flags as the register should 1429 * be naturally aligned (and those that are not so aligned merely 1430 * limit the available flags for that register). 1431 */ 1432 offset_ldw = entry->offset_ldw; 1433 offset_udw = entry->offset_udw; 1434 size = entry->size; 1435 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); 1436 1437 intel_runtime_pm_get(dev_priv); 1438 1439 switch (size) { 1440 case 8 | 1: 1441 reg->val = I915_READ64_2x32(offset_ldw, offset_udw); 1442 break; 1443 case 8: 1444 reg->val = I915_READ64(offset_ldw); 1445 break; 1446 case 4: 1447 reg->val = I915_READ(offset_ldw); 1448 break; 1449 case 2: 1450 reg->val = I915_READ16(offset_ldw); 1451 break; 1452 case 1: 1453 reg->val = I915_READ8(offset_ldw); 1454 break; 1455 default: 1456 ret = -EINVAL; 1457 goto out; 1458 } 1459 1460 out: 1461 intel_runtime_pm_put(dev_priv); 1462 return ret; 1463 } 1464 1465 static int i915_reset_complete(struct pci_dev *pdev) 1466 { 1467 u8 gdrst; 1468 pci_read_config_byte(pdev, I915_GDRST, &gdrst); 1469 return (gdrst & GRDOM_RESET_STATUS) == 0; 1470 } 1471 1472 static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1473 { 1474 struct pci_dev *pdev = dev_priv->drm.pdev; 1475 1476 /* assert reset for at least 20 usec */ 1477 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); 1478 udelay(20); 1479 pci_write_config_byte(pdev, I915_GDRST, 0); 1480 1481 return wait_for(i915_reset_complete(pdev), 500); 1482 } 1483 1484 static int g4x_reset_complete(struct pci_dev *pdev) 1485 { 1486 u8 gdrst; 1487 pci_read_config_byte(pdev, I915_GDRST, &gdrst); 1488 return (gdrst & GRDOM_RESET_ENABLE) == 0; 1489 } 1490 1491 static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1492 { 1493 struct pci_dev *pdev = dev_priv->drm.pdev; 1494 pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); 1495 return wait_for(g4x_reset_complete(pdev), 500); 1496 } 1497 1498 static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1499 { 1500 struct pci_dev *pdev = dev_priv->drm.pdev; 1501 int ret; 1502 1503 pci_write_config_byte(pdev, I915_GDRST, 1504 GRDOM_RENDER | GRDOM_RESET_ENABLE); 1505 ret = wait_for(g4x_reset_complete(pdev), 500); 1506 if (ret) 1507 return ret; 1508 1509 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1510 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); 1511 POSTING_READ(VDECCLK_GATE_D); 1512 1513 pci_write_config_byte(pdev, I915_GDRST, 1514 GRDOM_MEDIA | GRDOM_RESET_ENABLE); 1515 ret = wait_for(g4x_reset_complete(pdev), 500); 1516 if (ret) 1517 return ret; 1518 1519 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1520 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); 1521 POSTING_READ(VDECCLK_GATE_D); 1522 1523 pci_write_config_byte(pdev, I915_GDRST, 0); 1524 1525 return 0; 1526 } 1527 1528 static int ironlake_do_reset(struct drm_i915_private *dev_priv, 1529 unsigned engine_mask) 1530 { 1531 int ret; 1532 1533 I915_WRITE(ILK_GDSR, 1534 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); 1535 ret = intel_wait_for_register(dev_priv, 1536 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, 1537 500); 1538 if (ret) 1539 return ret; 1540 1541 I915_WRITE(ILK_GDSR, 1542 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); 1543 ret = intel_wait_for_register(dev_priv, 1544 ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, 1545 500); 1546 if (ret) 1547 return ret; 1548 1549 I915_WRITE(ILK_GDSR, 0); 1550 1551 return 0; 1552 } 1553 1554 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */ 1555 static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, 1556 u32 hw_domain_mask) 1557 { 1558 /* GEN6_GDRST is not in the gt power well, no need to check 1559 * for fifo space for the write or forcewake the chip for 1560 * the read 1561 */ 1562 __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); 1563 1564 /* Spin waiting for the device to ack the reset requests */ 1565 return intel_wait_for_register_fw(dev_priv, 1566 GEN6_GDRST, hw_domain_mask, 0, 1567 500); 1568 } 1569 1570 /** 1571 * gen6_reset_engines - reset individual engines 1572 * @dev_priv: i915 device 1573 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset 1574 * 1575 * This function will reset the individual engines that are set in engine_mask. 1576 * If you provide ALL_ENGINES as mask, full global domain reset will be issued. 1577 * 1578 * Note: It is responsibility of the caller to handle the difference between 1579 * asking full domain reset versus reset for all available individual engines. 1580 * 1581 * Returns 0 on success, nonzero on error. 1582 */ 1583 static int gen6_reset_engines(struct drm_i915_private *dev_priv, 1584 unsigned engine_mask) 1585 { 1586 struct intel_engine_cs *engine; 1587 const u32 hw_engine_mask[I915_NUM_ENGINES] = { 1588 [RCS] = GEN6_GRDOM_RENDER, 1589 [BCS] = GEN6_GRDOM_BLT, 1590 [VCS] = GEN6_GRDOM_MEDIA, 1591 [VCS2] = GEN8_GRDOM_MEDIA2, 1592 [VECS] = GEN6_GRDOM_VECS, 1593 }; 1594 u32 hw_mask; 1595 int ret; 1596 1597 if (engine_mask == ALL_ENGINES) { 1598 hw_mask = GEN6_GRDOM_FULL; 1599 } else { 1600 hw_mask = 0; 1601 for_each_engine_masked(engine, dev_priv, engine_mask) 1602 hw_mask |= hw_engine_mask[engine->id]; 1603 } 1604 1605 ret = gen6_hw_domain_reset(dev_priv, hw_mask); 1606 1607 intel_uncore_forcewake_reset(dev_priv, true); 1608 1609 return ret; 1610 } 1611 1612 /** 1613 * intel_wait_for_register_fw - wait until register matches expected state 1614 * @dev_priv: the i915 device 1615 * @reg: the register to read 1616 * @mask: mask to apply to register value 1617 * @value: expected value 1618 * @timeout_ms: timeout in millisecond 1619 * 1620 * This routine waits until the target register @reg contains the expected 1621 * @value after applying the @mask, i.e. it waits until 1622 * (I915_READ_FW(@reg) & @mask) == @value 1623 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 1624 * 1625 * Note that this routine assumes the caller holds forcewake asserted, it is 1626 * not suitable for very long waits. See intel_wait_for_register() if you 1627 * wish to wait without holding forcewake for the duration (i.e. you expect 1628 * the wait to be slow). 1629 * 1630 * Returns 0 if the register matches the desired condition, or -ETIMEOUT. 1631 */ 1632 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, 1633 i915_reg_t reg, 1634 const u32 mask, 1635 const u32 value, 1636 const unsigned long timeout_ms) 1637 { 1638 #define done ((I915_READ_FW(reg) & mask) == value) 1639 int ret = wait_for_us(done, 2); 1640 if (ret) 1641 ret = wait_for(done, timeout_ms); 1642 return ret; 1643 #undef done 1644 } 1645 1646 /** 1647 * intel_wait_for_register - wait until register matches expected state 1648 * @dev_priv: the i915 device 1649 * @reg: the register to read 1650 * @mask: mask to apply to register value 1651 * @value: expected value 1652 * @timeout_ms: timeout in millisecond 1653 * 1654 * This routine waits until the target register @reg contains the expected 1655 * @value after applying the @mask, i.e. it waits until 1656 * (I915_READ(@reg) & @mask) == @value 1657 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 1658 * 1659 * Returns 0 if the register matches the desired condition, or -ETIMEOUT. 1660 */ 1661 int intel_wait_for_register(struct drm_i915_private *dev_priv, 1662 i915_reg_t reg, 1663 const u32 mask, 1664 const u32 value, 1665 const unsigned long timeout_ms) 1666 { 1667 1668 unsigned fw = 1669 intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ); 1670 int ret; 1671 1672 intel_uncore_forcewake_get(dev_priv, fw); 1673 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2); 1674 intel_uncore_forcewake_put(dev_priv, fw); 1675 if (ret) 1676 ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value, 1677 timeout_ms); 1678 1679 return ret; 1680 } 1681 1682 static int gen8_request_engine_reset(struct intel_engine_cs *engine) 1683 { 1684 struct drm_i915_private *dev_priv = engine->i915; 1685 int ret; 1686 1687 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), 1688 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); 1689 1690 ret = intel_wait_for_register_fw(dev_priv, 1691 RING_RESET_CTL(engine->mmio_base), 1692 RESET_CTL_READY_TO_RESET, 1693 RESET_CTL_READY_TO_RESET, 1694 700); 1695 if (ret) 1696 DRM_ERROR("%s: reset request timeout\n", engine->name); 1697 1698 return ret; 1699 } 1700 1701 static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine) 1702 { 1703 struct drm_i915_private *dev_priv = engine->i915; 1704 1705 I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), 1706 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); 1707 } 1708 1709 static int gen8_reset_engines(struct drm_i915_private *dev_priv, 1710 unsigned engine_mask) 1711 { 1712 struct intel_engine_cs *engine; 1713 1714 for_each_engine_masked(engine, dev_priv, engine_mask) 1715 if (gen8_request_engine_reset(engine)) 1716 goto not_ready; 1717 1718 return gen6_reset_engines(dev_priv, engine_mask); 1719 1720 not_ready: 1721 for_each_engine_masked(engine, dev_priv, engine_mask) 1722 gen8_unrequest_engine_reset(engine); 1723 1724 return -EIO; 1725 } 1726 1727 typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask); 1728 1729 static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) 1730 { 1731 if (!i915.reset) 1732 return NULL; 1733 1734 if (INTEL_INFO(dev_priv)->gen >= 8) 1735 return gen8_reset_engines; 1736 else if (INTEL_INFO(dev_priv)->gen >= 6) 1737 return gen6_reset_engines; 1738 else if (IS_GEN5(dev_priv)) 1739 return ironlake_do_reset; 1740 else if (IS_G4X(dev_priv)) 1741 return g4x_do_reset; 1742 else if (IS_G33(dev_priv)) 1743 return g33_do_reset; 1744 else if (INTEL_INFO(dev_priv)->gen >= 3) 1745 return i915_do_reset; 1746 else 1747 return NULL; 1748 } 1749 1750 int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) 1751 { 1752 reset_func reset; 1753 int ret; 1754 1755 reset = intel_get_gpu_reset(dev_priv); 1756 if (reset == NULL) 1757 return -ENODEV; 1758 1759 /* If the power well sleeps during the reset, the reset 1760 * request may be dropped and never completes (causing -EIO). 1761 */ 1762 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1763 ret = reset(dev_priv, engine_mask); 1764 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1765 1766 return ret; 1767 } 1768 1769 bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) 1770 { 1771 return intel_get_gpu_reset(dev_priv) != NULL; 1772 } 1773 1774 int intel_guc_reset(struct drm_i915_private *dev_priv) 1775 { 1776 int ret; 1777 unsigned long irqflags; 1778 1779 if (!HAS_GUC(dev_priv)) 1780 return -EINVAL; 1781 1782 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1783 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1784 1785 ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC); 1786 1787 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1788 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1789 1790 return ret; 1791 } 1792 1793 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) 1794 { 1795 return check_for_unclaimed_mmio(dev_priv); 1796 } 1797 1798 bool 1799 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) 1800 { 1801 if (unlikely(i915.mmio_debug || 1802 dev_priv->uncore.unclaimed_mmio_check <= 0)) 1803 return false; 1804 1805 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { 1806 DRM_DEBUG("Unclaimed register detected, " 1807 "enabling oneshot unclaimed register reporting. " 1808 "Please use i915.mmio_debug=N for more information.\n"); 1809 i915.mmio_debug++; 1810 dev_priv->uncore.unclaimed_mmio_check--; 1811 return true; 1812 } 1813 1814 return false; 1815 } 1816 1817 static enum forcewake_domains 1818 intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, 1819 i915_reg_t reg) 1820 { 1821 enum forcewake_domains fw_domains; 1822 1823 if (intel_vgpu_active(dev_priv)) 1824 return 0; 1825 1826 switch (INTEL_GEN(dev_priv)) { 1827 case 9: 1828 fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg)); 1829 break; 1830 case 8: 1831 if (IS_CHERRYVIEW(dev_priv)) 1832 fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg)); 1833 else 1834 fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg)); 1835 break; 1836 case 7: 1837 case 6: 1838 if (IS_VALLEYVIEW(dev_priv)) 1839 fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg)); 1840 else 1841 fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg)); 1842 break; 1843 default: 1844 MISSING_CASE(INTEL_INFO(dev_priv)->gen); 1845 case 5: /* forcewake was introduced with gen6 */ 1846 case 4: 1847 case 3: 1848 case 2: 1849 return 0; 1850 } 1851 1852 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); 1853 1854 return fw_domains; 1855 } 1856 1857 static enum forcewake_domains 1858 intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, 1859 i915_reg_t reg) 1860 { 1861 enum forcewake_domains fw_domains; 1862 1863 if (intel_vgpu_active(dev_priv)) 1864 return 0; 1865 1866 switch (INTEL_GEN(dev_priv)) { 1867 case 9: 1868 fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg)); 1869 break; 1870 case 8: 1871 if (IS_CHERRYVIEW(dev_priv)) 1872 fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg)); 1873 else 1874 fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg)); 1875 break; 1876 case 7: 1877 case 6: 1878 fw_domains = FORCEWAKE_RENDER; 1879 break; 1880 default: 1881 MISSING_CASE(INTEL_INFO(dev_priv)->gen); 1882 case 5: 1883 case 4: 1884 case 3: 1885 case 2: 1886 return 0; 1887 } 1888 1889 WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); 1890 1891 return fw_domains; 1892 } 1893 1894 /** 1895 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 1896 * a register 1897 * @dev_priv: pointer to struct drm_i915_private 1898 * @reg: register in question 1899 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 1900 * 1901 * Returns a set of forcewake domains required to be taken with for example 1902 * intel_uncore_forcewake_get for the specified register to be accessible in the 1903 * specified mode (read, write or read/write) with raw mmio accessors. 1904 * 1905 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 1906 * callers to do FIFO management on their own or risk losing writes. 1907 */ 1908 enum forcewake_domains 1909 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, 1910 i915_reg_t reg, unsigned int op) 1911 { 1912 enum forcewake_domains fw_domains = 0; 1913 1914 WARN_ON(!op); 1915 1916 if (op & FW_REG_READ) 1917 fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg); 1918 1919 if (op & FW_REG_WRITE) 1920 fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg); 1921 1922 return fw_domains; 1923 } 1924