1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 53 enum i915_power_well_id power_well_id); 54 55 const char * 56 intel_display_power_domain_str(enum intel_display_power_domain domain) 57 { 58 switch (domain) { 59 case POWER_DOMAIN_PIPE_A: 60 return "PIPE_A"; 61 case POWER_DOMAIN_PIPE_B: 62 return "PIPE_B"; 63 case POWER_DOMAIN_PIPE_C: 64 return "PIPE_C"; 65 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 66 return "PIPE_A_PANEL_FITTER"; 67 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 68 return "PIPE_B_PANEL_FITTER"; 69 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 70 return "PIPE_C_PANEL_FITTER"; 71 case POWER_DOMAIN_TRANSCODER_A: 72 return "TRANSCODER_A"; 73 case POWER_DOMAIN_TRANSCODER_B: 74 return "TRANSCODER_B"; 75 case POWER_DOMAIN_TRANSCODER_C: 76 return "TRANSCODER_C"; 77 case POWER_DOMAIN_TRANSCODER_EDP: 78 return "TRANSCODER_EDP"; 79 case POWER_DOMAIN_TRANSCODER_DSI_A: 80 return "TRANSCODER_DSI_A"; 81 case POWER_DOMAIN_TRANSCODER_DSI_C: 82 return "TRANSCODER_DSI_C"; 83 case POWER_DOMAIN_PORT_DDI_A_LANES: 84 return "PORT_DDI_A_LANES"; 85 case POWER_DOMAIN_PORT_DDI_B_LANES: 86 return "PORT_DDI_B_LANES"; 87 case POWER_DOMAIN_PORT_DDI_C_LANES: 88 return "PORT_DDI_C_LANES"; 89 case POWER_DOMAIN_PORT_DDI_D_LANES: 90 return "PORT_DDI_D_LANES"; 91 case POWER_DOMAIN_PORT_DDI_E_LANES: 92 return "PORT_DDI_E_LANES"; 93 case POWER_DOMAIN_PORT_DDI_F_LANES: 94 return "PORT_DDI_F_LANES"; 95 case POWER_DOMAIN_PORT_DDI_A_IO: 96 return "PORT_DDI_A_IO"; 97 case POWER_DOMAIN_PORT_DDI_B_IO: 98 return "PORT_DDI_B_IO"; 99 case POWER_DOMAIN_PORT_DDI_C_IO: 100 return "PORT_DDI_C_IO"; 101 case POWER_DOMAIN_PORT_DDI_D_IO: 102 return "PORT_DDI_D_IO"; 103 case POWER_DOMAIN_PORT_DDI_E_IO: 104 return "PORT_DDI_E_IO"; 105 case POWER_DOMAIN_PORT_DDI_F_IO: 106 return "PORT_DDI_F_IO"; 107 case POWER_DOMAIN_PORT_DSI: 108 return "PORT_DSI"; 109 case POWER_DOMAIN_PORT_CRT: 110 return "PORT_CRT"; 111 case POWER_DOMAIN_PORT_OTHER: 112 return "PORT_OTHER"; 113 case POWER_DOMAIN_VGA: 114 return "VGA"; 115 case POWER_DOMAIN_AUDIO: 116 return "AUDIO"; 117 case POWER_DOMAIN_PLLS: 118 return "PLLS"; 119 case POWER_DOMAIN_AUX_A: 120 return "AUX_A"; 121 case POWER_DOMAIN_AUX_B: 122 return "AUX_B"; 123 case POWER_DOMAIN_AUX_C: 124 return "AUX_C"; 125 case POWER_DOMAIN_AUX_D: 126 return "AUX_D"; 127 case POWER_DOMAIN_AUX_E: 128 return "AUX_E"; 129 case POWER_DOMAIN_AUX_F: 130 return "AUX_F"; 131 case POWER_DOMAIN_AUX_IO_A: 132 return "AUX_IO_A"; 133 case POWER_DOMAIN_AUX_TBT1: 134 return "AUX_TBT1"; 135 case POWER_DOMAIN_AUX_TBT2: 136 return "AUX_TBT2"; 137 case POWER_DOMAIN_AUX_TBT3: 138 return "AUX_TBT3"; 139 case POWER_DOMAIN_AUX_TBT4: 140 return "AUX_TBT4"; 141 case POWER_DOMAIN_GMBUS: 142 return "GMBUS"; 143 case POWER_DOMAIN_INIT: 144 return "INIT"; 145 case POWER_DOMAIN_MODESET: 146 return "MODESET"; 147 case POWER_DOMAIN_GT_IRQ: 148 return "GT_IRQ"; 149 default: 150 MISSING_CASE(domain); 151 return "?"; 152 } 153 } 154 155 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 156 struct i915_power_well *power_well) 157 { 158 DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name); 159 power_well->desc->ops->enable(dev_priv, power_well); 160 power_well->hw_enabled = true; 161 } 162 163 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 164 struct i915_power_well *power_well) 165 { 166 DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name); 167 power_well->hw_enabled = false; 168 power_well->desc->ops->disable(dev_priv, power_well); 169 } 170 171 static void intel_power_well_get(struct drm_i915_private *dev_priv, 172 struct i915_power_well *power_well) 173 { 174 if (!power_well->count++) 175 intel_power_well_enable(dev_priv, power_well); 176 } 177 178 static void intel_power_well_put(struct drm_i915_private *dev_priv, 179 struct i915_power_well *power_well) 180 { 181 WARN(!power_well->count, "Use count on power well %s is already zero", 182 power_well->desc->name); 183 184 if (!--power_well->count) 185 intel_power_well_disable(dev_priv, power_well); 186 } 187 188 /** 189 * __intel_display_power_is_enabled - unlocked check for a power domain 190 * @dev_priv: i915 device instance 191 * @domain: power domain to check 192 * 193 * This is the unlocked version of intel_display_power_is_enabled() and should 194 * only be used from error capture and recovery code where deadlocks are 195 * possible. 196 * 197 * Returns: 198 * True when the power domain is enabled, false otherwise. 199 */ 200 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 201 enum intel_display_power_domain domain) 202 { 203 struct i915_power_well *power_well; 204 bool is_enabled; 205 206 if (dev_priv->runtime_pm.suspended) 207 return false; 208 209 is_enabled = true; 210 211 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { 212 if (power_well->desc->always_on) 213 continue; 214 215 if (!power_well->hw_enabled) { 216 is_enabled = false; 217 break; 218 } 219 } 220 221 return is_enabled; 222 } 223 224 /** 225 * intel_display_power_is_enabled - check for a power domain 226 * @dev_priv: i915 device instance 227 * @domain: power domain to check 228 * 229 * This function can be used to check the hw power domain state. It is mostly 230 * used in hardware state readout functions. Everywhere else code should rely 231 * upon explicit power domain reference counting to ensure that the hardware 232 * block is powered up before accessing it. 233 * 234 * Callers must hold the relevant modesetting locks to ensure that concurrent 235 * threads can't disable the power well while the caller tries to read a few 236 * registers. 237 * 238 * Returns: 239 * True when the power domain is enabled, false otherwise. 240 */ 241 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 242 enum intel_display_power_domain domain) 243 { 244 struct i915_power_domains *power_domains; 245 bool ret; 246 247 power_domains = &dev_priv->power_domains; 248 249 mutex_lock(&power_domains->lock); 250 ret = __intel_display_power_is_enabled(dev_priv, domain); 251 mutex_unlock(&power_domains->lock); 252 253 return ret; 254 } 255 256 /* 257 * Starting with Haswell, we have a "Power Down Well" that can be turned off 258 * when not needed anymore. We have 4 registers that can request the power well 259 * to be enabled, and it will only be disabled if none of the registers is 260 * requesting it to be enabled. 261 */ 262 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 263 u8 irq_pipe_mask, bool has_vga) 264 { 265 struct pci_dev *pdev = dev_priv->drm.pdev; 266 267 /* 268 * After we re-enable the power well, if we touch VGA register 0x3d5 269 * we'll get unclaimed register interrupts. This stops after we write 270 * anything to the VGA MSR register. The vgacon module uses this 271 * register all the time, so if we unbind our driver and, as a 272 * consequence, bind vgacon, we'll get stuck in an infinite loop at 273 * console_unlock(). So make here we touch the VGA MSR register, making 274 * sure vgacon can keep working normally without triggering interrupts 275 * and error messages. 276 */ 277 if (has_vga) { 278 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 279 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 280 vga_put(pdev, VGA_RSRC_LEGACY_IO); 281 } 282 283 if (irq_pipe_mask) 284 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 285 } 286 287 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 288 u8 irq_pipe_mask) 289 { 290 if (irq_pipe_mask) 291 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 292 } 293 294 295 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 296 struct i915_power_well *power_well) 297 { 298 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 299 int pw_idx = power_well->desc->hsw.idx; 300 301 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 302 WARN_ON(intel_wait_for_register(dev_priv, 303 regs->driver, 304 HSW_PWR_WELL_CTL_STATE(pw_idx), 305 HSW_PWR_WELL_CTL_STATE(pw_idx), 306 1)); 307 } 308 309 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 310 const struct i915_power_well_regs *regs, 311 int pw_idx) 312 { 313 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 314 u32 ret; 315 316 ret = I915_READ(regs->bios) & req_mask ? 1 : 0; 317 ret |= I915_READ(regs->driver) & req_mask ? 2 : 0; 318 if (regs->kvmr.reg) 319 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0; 320 ret |= I915_READ(regs->debug) & req_mask ? 8 : 0; 321 322 return ret; 323 } 324 325 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 326 struct i915_power_well *power_well) 327 { 328 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 329 int pw_idx = power_well->desc->hsw.idx; 330 bool disabled; 331 u32 reqs; 332 333 /* 334 * Bspec doesn't require waiting for PWs to get disabled, but still do 335 * this for paranoia. The known cases where a PW will be forced on: 336 * - a KVMR request on any power well via the KVMR request register 337 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 338 * DEBUG request registers 339 * Skip the wait in case any of the request bits are set and print a 340 * diagnostic message. 341 */ 342 wait_for((disabled = !(I915_READ(regs->driver) & 343 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 344 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); 345 if (disabled) 346 return; 347 348 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 349 power_well->desc->name, 350 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 351 } 352 353 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 354 enum skl_power_gate pg) 355 { 356 /* Timeout 5us for PG#0, for other PGs 1us */ 357 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, 358 SKL_FUSE_PG_DIST_STATUS(pg), 359 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 360 } 361 362 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 363 struct i915_power_well *power_well) 364 { 365 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 366 int pw_idx = power_well->desc->hsw.idx; 367 bool wait_fuses = power_well->desc->hsw.has_fuses; 368 enum skl_power_gate uninitialized_var(pg); 369 u32 val; 370 371 if (wait_fuses) { 372 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 373 SKL_PW_CTL_IDX_TO_PG(pw_idx); 374 /* 375 * For PW1 we have to wait both for the PW0/PG0 fuse state 376 * before enabling the power well and PW1/PG1's own fuse 377 * state after the enabling. For all other power wells with 378 * fuses we only have to wait for that PW/PG's fuse state 379 * after the enabling. 380 */ 381 if (pg == SKL_PG1) 382 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 383 } 384 385 val = I915_READ(regs->driver); 386 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); 387 hsw_wait_for_power_well_enable(dev_priv, power_well); 388 389 /* Display WA #1178: cnl */ 390 if (IS_CANNONLAKE(dev_priv) && 391 pw_idx >= GLK_PW_CTL_IDX_AUX_B && 392 pw_idx <= CNL_PW_CTL_IDX_AUX_F) { 393 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); 394 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; 395 I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val); 396 } 397 398 if (wait_fuses) 399 gen9_wait_for_power_well_fuses(dev_priv, pg); 400 401 hsw_power_well_post_enable(dev_priv, 402 power_well->desc->hsw.irq_pipe_mask, 403 power_well->desc->hsw.has_vga); 404 } 405 406 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 407 struct i915_power_well *power_well) 408 { 409 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 410 int pw_idx = power_well->desc->hsw.idx; 411 u32 val; 412 413 hsw_power_well_pre_disable(dev_priv, 414 power_well->desc->hsw.irq_pipe_mask); 415 416 val = I915_READ(regs->driver); 417 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); 418 hsw_wait_for_power_well_disable(dev_priv, power_well); 419 } 420 421 #define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 422 423 static void 424 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 425 struct i915_power_well *power_well) 426 { 427 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 428 int pw_idx = power_well->desc->hsw.idx; 429 enum port port = ICL_AUX_PW_TO_PORT(pw_idx); 430 u32 val; 431 432 val = I915_READ(regs->driver); 433 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); 434 435 val = I915_READ(ICL_PORT_CL_DW12(port)); 436 I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); 437 438 hsw_wait_for_power_well_enable(dev_priv, power_well); 439 } 440 441 static void 442 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 443 struct i915_power_well *power_well) 444 { 445 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 446 int pw_idx = power_well->desc->hsw.idx; 447 enum port port = ICL_AUX_PW_TO_PORT(pw_idx); 448 u32 val; 449 450 val = I915_READ(ICL_PORT_CL_DW12(port)); 451 I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX); 452 453 val = I915_READ(regs->driver); 454 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); 455 456 hsw_wait_for_power_well_disable(dev_priv, power_well); 457 } 458 459 /* 460 * We should only use the power well if we explicitly asked the hardware to 461 * enable it, so check if it's enabled and also check if we've requested it to 462 * be enabled. 463 */ 464 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 465 struct i915_power_well *power_well) 466 { 467 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 468 int pw_idx = power_well->desc->hsw.idx; 469 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 470 HSW_PWR_WELL_CTL_STATE(pw_idx); 471 472 return (I915_READ(regs->driver) & mask) == mask; 473 } 474 475 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 476 { 477 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 478 "DC9 already programmed to be enabled.\n"); 479 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 480 "DC5 still not disabled to enable DC9.\n"); 481 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) & 482 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 483 "Power well 2 on.\n"); 484 WARN_ONCE(intel_irqs_enabled(dev_priv), 485 "Interrupts not disabled yet.\n"); 486 487 /* 488 * TODO: check for the following to verify the conditions to enter DC9 489 * state are satisfied: 490 * 1] Check relevant display engine registers to verify if mode set 491 * disable sequence was followed. 492 * 2] Check if display uninitialize sequence is initialized. 493 */ 494 } 495 496 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 497 { 498 WARN_ONCE(intel_irqs_enabled(dev_priv), 499 "Interrupts not disabled yet.\n"); 500 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 501 "DC5 still not disabled.\n"); 502 503 /* 504 * TODO: check for the following to verify DC9 state was indeed 505 * entered before programming to disable it: 506 * 1] Check relevant display engine registers to verify if mode 507 * set disable sequence was followed. 508 * 2] Check if display uninitialize sequence is initialized. 509 */ 510 } 511 512 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 513 u32 state) 514 { 515 int rewrites = 0; 516 int rereads = 0; 517 u32 v; 518 519 I915_WRITE(DC_STATE_EN, state); 520 521 /* It has been observed that disabling the dc6 state sometimes 522 * doesn't stick and dmc keeps returning old value. Make sure 523 * the write really sticks enough times and also force rewrite until 524 * we are confident that state is exactly what we want. 525 */ 526 do { 527 v = I915_READ(DC_STATE_EN); 528 529 if (v != state) { 530 I915_WRITE(DC_STATE_EN, state); 531 rewrites++; 532 rereads = 0; 533 } else if (rereads++ > 5) { 534 break; 535 } 536 537 } while (rewrites < 100); 538 539 if (v != state) 540 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 541 state, v); 542 543 /* Most of the times we need one retry, avoid spam */ 544 if (rewrites > 1) 545 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 546 state, rewrites); 547 } 548 549 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 550 { 551 u32 mask; 552 553 mask = DC_STATE_EN_UPTO_DC5; 554 if (IS_GEN9_LP(dev_priv)) 555 mask |= DC_STATE_EN_DC9; 556 else 557 mask |= DC_STATE_EN_UPTO_DC6; 558 559 return mask; 560 } 561 562 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 563 { 564 u32 val; 565 566 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 567 568 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 569 dev_priv->csr.dc_state, val); 570 dev_priv->csr.dc_state = val; 571 } 572 573 /** 574 * gen9_set_dc_state - set target display C power state 575 * @dev_priv: i915 device instance 576 * @state: target DC power state 577 * - DC_STATE_DISABLE 578 * - DC_STATE_EN_UPTO_DC5 579 * - DC_STATE_EN_UPTO_DC6 580 * - DC_STATE_EN_DC9 581 * 582 * Signal to DMC firmware/HW the target DC power state passed in @state. 583 * DMC/HW can turn off individual display clocks and power rails when entering 584 * a deeper DC power state (higher in number) and turns these back when exiting 585 * that state to a shallower power state (lower in number). The HW will decide 586 * when to actually enter a given state on an on-demand basis, for instance 587 * depending on the active state of display pipes. The state of display 588 * registers backed by affected power rails are saved/restored as needed. 589 * 590 * Based on the above enabling a deeper DC power state is asynchronous wrt. 591 * enabling it. Disabling a deeper power state is synchronous: for instance 592 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 593 * back on and register state is restored. This is guaranteed by the MMIO write 594 * to DC_STATE_EN blocking until the state is restored. 595 */ 596 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 597 { 598 uint32_t val; 599 uint32_t mask; 600 601 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 602 state &= dev_priv->csr.allowed_dc_mask; 603 604 val = I915_READ(DC_STATE_EN); 605 mask = gen9_dc_mask(dev_priv); 606 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 607 val & mask, state); 608 609 /* Check if DMC is ignoring our DC state requests */ 610 if ((val & mask) != dev_priv->csr.dc_state) 611 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 612 dev_priv->csr.dc_state, val & mask); 613 614 val &= ~mask; 615 val |= state; 616 617 gen9_write_dc_state(dev_priv, val); 618 619 dev_priv->csr.dc_state = val & mask; 620 } 621 622 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 623 { 624 assert_can_enable_dc9(dev_priv); 625 626 DRM_DEBUG_KMS("Enabling DC9\n"); 627 628 intel_power_sequencer_reset(dev_priv); 629 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 630 } 631 632 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 633 { 634 assert_can_disable_dc9(dev_priv); 635 636 DRM_DEBUG_KMS("Disabling DC9\n"); 637 638 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 639 640 intel_pps_unlock_regs_wa(dev_priv); 641 } 642 643 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 644 { 645 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 646 "CSR program storage start is NULL\n"); 647 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 648 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 649 } 650 651 static struct i915_power_well * 652 lookup_power_well(struct drm_i915_private *dev_priv, 653 enum i915_power_well_id power_well_id) 654 { 655 struct i915_power_well *power_well; 656 657 for_each_power_well(dev_priv, power_well) 658 if (power_well->desc->id == power_well_id) 659 return power_well; 660 661 /* 662 * It's not feasible to add error checking code to the callers since 663 * this condition really shouldn't happen and it doesn't even make sense 664 * to abort things like display initialization sequences. Just return 665 * the first power well and hope the WARN gets reported so we can fix 666 * our driver. 667 */ 668 WARN(1, "Power well %d not defined for this platform\n", power_well_id); 669 return &dev_priv->power_domains.power_wells[0]; 670 } 671 672 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 673 { 674 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 675 SKL_DISP_PW_2); 676 677 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 678 679 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 680 "DC5 already programmed to be enabled.\n"); 681 assert_rpm_wakelock_held(dev_priv); 682 683 assert_csr_loaded(dev_priv); 684 } 685 686 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 687 { 688 assert_can_enable_dc5(dev_priv); 689 690 DRM_DEBUG_KMS("Enabling DC5\n"); 691 692 /* Wa Display #1183: skl,kbl,cfl */ 693 if (IS_GEN9_BC(dev_priv)) 694 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 695 SKL_SELECT_ALTERNATE_DC_EXIT); 696 697 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 698 } 699 700 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 701 { 702 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 703 "Backlight is not disabled.\n"); 704 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 705 "DC6 already programmed to be enabled.\n"); 706 707 assert_csr_loaded(dev_priv); 708 } 709 710 static void skl_enable_dc6(struct drm_i915_private *dev_priv) 711 { 712 assert_can_enable_dc6(dev_priv); 713 714 DRM_DEBUG_KMS("Enabling DC6\n"); 715 716 /* Wa Display #1183: skl,kbl,cfl */ 717 if (IS_GEN9_BC(dev_priv)) 718 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 719 SKL_SELECT_ALTERNATE_DC_EXIT); 720 721 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 722 } 723 724 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 725 struct i915_power_well *power_well) 726 { 727 const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; 728 int pw_idx = power_well->desc->hsw.idx; 729 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 730 u32 bios_req = I915_READ(regs->bios); 731 732 /* Take over the request bit if set by BIOS. */ 733 if (bios_req & mask) { 734 u32 drv_req = I915_READ(regs->driver); 735 736 if (!(drv_req & mask)) 737 I915_WRITE(regs->driver, drv_req | mask); 738 I915_WRITE(regs->bios, bios_req & ~mask); 739 } 740 } 741 742 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 743 struct i915_power_well *power_well) 744 { 745 bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy); 746 } 747 748 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 749 struct i915_power_well *power_well) 750 { 751 bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy); 752 } 753 754 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 755 struct i915_power_well *power_well) 756 { 757 return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy); 758 } 759 760 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 761 { 762 struct i915_power_well *power_well; 763 764 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A); 765 if (power_well->count > 0) 766 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy); 767 768 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 769 if (power_well->count > 0) 770 bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy); 771 772 if (IS_GEMINILAKE(dev_priv)) { 773 power_well = lookup_power_well(dev_priv, 774 GLK_DISP_PW_DPIO_CMN_C); 775 if (power_well->count > 0) 776 bxt_ddi_phy_verify_state(dev_priv, 777 power_well->desc->bxt.phy); 778 } 779 } 780 781 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 782 struct i915_power_well *power_well) 783 { 784 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 785 } 786 787 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 788 { 789 u32 tmp = I915_READ(DBUF_CTL); 790 791 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 792 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 793 "Unexpected DBuf power power state (0x%08x)\n", tmp); 794 } 795 796 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 797 struct i915_power_well *power_well) 798 { 799 struct intel_cdclk_state cdclk_state = {}; 800 801 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 802 803 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); 804 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 805 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); 806 807 gen9_assert_dbuf_enabled(dev_priv); 808 809 if (IS_GEN9_LP(dev_priv)) 810 bxt_verify_ddi_phy_power_wells(dev_priv); 811 } 812 813 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 814 struct i915_power_well *power_well) 815 { 816 if (!dev_priv->csr.dmc_payload) 817 return; 818 819 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 820 skl_enable_dc6(dev_priv); 821 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 822 gen9_enable_dc5(dev_priv); 823 } 824 825 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 826 struct i915_power_well *power_well) 827 { 828 } 829 830 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 831 struct i915_power_well *power_well) 832 { 833 } 834 835 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 836 struct i915_power_well *power_well) 837 { 838 return true; 839 } 840 841 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 842 struct i915_power_well *power_well) 843 { 844 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) 845 i830_enable_pipe(dev_priv, PIPE_A); 846 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) 847 i830_enable_pipe(dev_priv, PIPE_B); 848 } 849 850 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 851 struct i915_power_well *power_well) 852 { 853 i830_disable_pipe(dev_priv, PIPE_B); 854 i830_disable_pipe(dev_priv, PIPE_A); 855 } 856 857 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 858 struct i915_power_well *power_well) 859 { 860 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && 861 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 862 } 863 864 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 865 struct i915_power_well *power_well) 866 { 867 if (power_well->count > 0) 868 i830_pipes_power_well_enable(dev_priv, power_well); 869 else 870 i830_pipes_power_well_disable(dev_priv, power_well); 871 } 872 873 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 874 struct i915_power_well *power_well, bool enable) 875 { 876 int pw_idx = power_well->desc->vlv.idx; 877 u32 mask; 878 u32 state; 879 u32 ctrl; 880 881 mask = PUNIT_PWRGT_MASK(pw_idx); 882 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 883 PUNIT_PWRGT_PWR_GATE(pw_idx); 884 885 mutex_lock(&dev_priv->pcu_lock); 886 887 #define COND \ 888 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 889 890 if (COND) 891 goto out; 892 893 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 894 ctrl &= ~mask; 895 ctrl |= state; 896 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 897 898 if (wait_for(COND, 100)) 899 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 900 state, 901 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 902 903 #undef COND 904 905 out: 906 mutex_unlock(&dev_priv->pcu_lock); 907 } 908 909 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 910 struct i915_power_well *power_well) 911 { 912 vlv_set_power_well(dev_priv, power_well, true); 913 } 914 915 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 916 struct i915_power_well *power_well) 917 { 918 vlv_set_power_well(dev_priv, power_well, false); 919 } 920 921 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 922 struct i915_power_well *power_well) 923 { 924 int pw_idx = power_well->desc->vlv.idx; 925 bool enabled = false; 926 u32 mask; 927 u32 state; 928 u32 ctrl; 929 930 mask = PUNIT_PWRGT_MASK(pw_idx); 931 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 932 933 mutex_lock(&dev_priv->pcu_lock); 934 935 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 936 /* 937 * We only ever set the power-on and power-gate states, anything 938 * else is unexpected. 939 */ 940 WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && 941 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 942 if (state == ctrl) 943 enabled = true; 944 945 /* 946 * A transient state at this point would mean some unexpected party 947 * is poking at the power controls too. 948 */ 949 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 950 WARN_ON(ctrl != state); 951 952 mutex_unlock(&dev_priv->pcu_lock); 953 954 return enabled; 955 } 956 957 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 958 { 959 u32 val; 960 961 /* 962 * On driver load, a pipe may be active and driving a DSI display. 963 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 964 * (and never recovering) in this case. intel_dsi_post_disable() will 965 * clear it when we turn off the display. 966 */ 967 val = I915_READ(DSPCLK_GATE_D); 968 val &= DPOUNIT_CLOCK_GATE_DISABLE; 969 val |= VRHUNIT_CLOCK_GATE_DISABLE; 970 I915_WRITE(DSPCLK_GATE_D, val); 971 972 /* 973 * Disable trickle feed and enable pnd deadline calculation 974 */ 975 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 976 I915_WRITE(CBR1_VLV, 0); 977 978 WARN_ON(dev_priv->rawclk_freq == 0); 979 980 I915_WRITE(RAWCLK_FREQ_VLV, 981 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 982 } 983 984 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 985 { 986 struct intel_encoder *encoder; 987 enum pipe pipe; 988 989 /* 990 * Enable the CRI clock source so we can get at the 991 * display and the reference clock for VGA 992 * hotplug / manual detection. Supposedly DSI also 993 * needs the ref clock up and running. 994 * 995 * CHV DPLL B/C have some issues if VGA mode is enabled. 996 */ 997 for_each_pipe(dev_priv, pipe) { 998 u32 val = I915_READ(DPLL(pipe)); 999 1000 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1001 if (pipe != PIPE_A) 1002 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1003 1004 I915_WRITE(DPLL(pipe), val); 1005 } 1006 1007 vlv_init_display_clock_gating(dev_priv); 1008 1009 spin_lock_irq(&dev_priv->irq_lock); 1010 valleyview_enable_display_irqs(dev_priv); 1011 spin_unlock_irq(&dev_priv->irq_lock); 1012 1013 /* 1014 * During driver initialization/resume we can avoid restoring the 1015 * part of the HW/SW state that will be inited anyway explicitly. 1016 */ 1017 if (dev_priv->power_domains.initializing) 1018 return; 1019 1020 intel_hpd_init(dev_priv); 1021 1022 /* Re-enable the ADPA, if we have one */ 1023 for_each_intel_encoder(&dev_priv->drm, encoder) { 1024 if (encoder->type == INTEL_OUTPUT_ANALOG) 1025 intel_crt_reset(&encoder->base); 1026 } 1027 1028 i915_redisable_vga_power_on(dev_priv); 1029 1030 intel_pps_unlock_regs_wa(dev_priv); 1031 } 1032 1033 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1034 { 1035 spin_lock_irq(&dev_priv->irq_lock); 1036 valleyview_disable_display_irqs(dev_priv); 1037 spin_unlock_irq(&dev_priv->irq_lock); 1038 1039 /* make sure we're done processing display irqs */ 1040 synchronize_irq(dev_priv->drm.irq); 1041 1042 intel_power_sequencer_reset(dev_priv); 1043 1044 /* Prevent us from re-enabling polling on accident in late suspend */ 1045 if (!dev_priv->drm.dev->power.is_suspended) 1046 intel_hpd_poll_init(dev_priv); 1047 } 1048 1049 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1050 struct i915_power_well *power_well) 1051 { 1052 vlv_set_power_well(dev_priv, power_well, true); 1053 1054 vlv_display_power_well_init(dev_priv); 1055 } 1056 1057 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1058 struct i915_power_well *power_well) 1059 { 1060 vlv_display_power_well_deinit(dev_priv); 1061 1062 vlv_set_power_well(dev_priv, power_well, false); 1063 } 1064 1065 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1066 struct i915_power_well *power_well) 1067 { 1068 /* since ref/cri clock was enabled */ 1069 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1070 1071 vlv_set_power_well(dev_priv, power_well, true); 1072 1073 /* 1074 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1075 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1076 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1077 * b. The other bits such as sfr settings / modesel may all 1078 * be set to 0. 1079 * 1080 * This should only be done on init and resume from S3 with 1081 * both PLLs disabled, or we risk losing DPIO and PLL 1082 * synchronization. 1083 */ 1084 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1085 } 1086 1087 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1088 struct i915_power_well *power_well) 1089 { 1090 enum pipe pipe; 1091 1092 for_each_pipe(dev_priv, pipe) 1093 assert_pll_disabled(dev_priv, pipe); 1094 1095 /* Assert common reset */ 1096 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1097 1098 vlv_set_power_well(dev_priv, power_well, false); 1099 } 1100 1101 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 1102 1103 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1104 1105 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1106 { 1107 struct i915_power_well *cmn_bc = 1108 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1109 struct i915_power_well *cmn_d = 1110 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1111 u32 phy_control = dev_priv->chv_phy_control; 1112 u32 phy_status = 0; 1113 u32 phy_status_mask = 0xffffffff; 1114 1115 /* 1116 * The BIOS can leave the PHY is some weird state 1117 * where it doesn't fully power down some parts. 1118 * Disable the asserts until the PHY has been fully 1119 * reset (ie. the power well has been disabled at 1120 * least once). 1121 */ 1122 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1123 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1124 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1125 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1126 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1127 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1128 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1129 1130 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1131 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1132 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1133 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1134 1135 if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) { 1136 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1137 1138 /* this assumes override is only used to enable lanes */ 1139 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1140 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1141 1142 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1143 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1144 1145 /* CL1 is on whenever anything is on in either channel */ 1146 if (BITS_SET(phy_control, 1147 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1148 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1149 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1150 1151 /* 1152 * The DPLLB check accounts for the pipe B + port A usage 1153 * with CL2 powered up but all the lanes in the second channel 1154 * powered down. 1155 */ 1156 if (BITS_SET(phy_control, 1157 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1158 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1159 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1160 1161 if (BITS_SET(phy_control, 1162 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1163 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1164 if (BITS_SET(phy_control, 1165 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1166 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1167 1168 if (BITS_SET(phy_control, 1169 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1170 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1171 if (BITS_SET(phy_control, 1172 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1173 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1174 } 1175 1176 if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) { 1177 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1178 1179 /* this assumes override is only used to enable lanes */ 1180 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1181 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1182 1183 if (BITS_SET(phy_control, 1184 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1185 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1186 1187 if (BITS_SET(phy_control, 1188 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1189 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1190 if (BITS_SET(phy_control, 1191 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1192 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1193 } 1194 1195 phy_status &= phy_status_mask; 1196 1197 /* 1198 * The PHY may be busy with some initial calibration and whatnot, 1199 * so the power state can take a while to actually change. 1200 */ 1201 if (intel_wait_for_register(dev_priv, 1202 DISPLAY_PHY_STATUS, 1203 phy_status_mask, 1204 phy_status, 1205 10)) 1206 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1207 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1208 phy_status, dev_priv->chv_phy_control); 1209 } 1210 1211 #undef BITS_SET 1212 1213 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1214 struct i915_power_well *power_well) 1215 { 1216 enum dpio_phy phy; 1217 enum pipe pipe; 1218 uint32_t tmp; 1219 1220 WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && 1221 power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); 1222 1223 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { 1224 pipe = PIPE_A; 1225 phy = DPIO_PHY0; 1226 } else { 1227 pipe = PIPE_C; 1228 phy = DPIO_PHY1; 1229 } 1230 1231 /* since ref/cri clock was enabled */ 1232 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1233 vlv_set_power_well(dev_priv, power_well, true); 1234 1235 /* Poll for phypwrgood signal */ 1236 if (intel_wait_for_register(dev_priv, 1237 DISPLAY_PHY_STATUS, 1238 PHY_POWERGOOD(phy), 1239 PHY_POWERGOOD(phy), 1240 1)) 1241 DRM_ERROR("Display PHY %d is not power up\n", phy); 1242 1243 mutex_lock(&dev_priv->sb_lock); 1244 1245 /* Enable dynamic power down */ 1246 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1247 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1248 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1249 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1250 1251 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { 1252 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1253 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1254 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1255 } else { 1256 /* 1257 * Force the non-existing CL2 off. BXT does this 1258 * too, so maybe it saves some power even though 1259 * CL2 doesn't exist? 1260 */ 1261 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1262 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1263 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1264 } 1265 1266 mutex_unlock(&dev_priv->sb_lock); 1267 1268 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1269 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1270 1271 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1272 phy, dev_priv->chv_phy_control); 1273 1274 assert_chv_phy_status(dev_priv); 1275 } 1276 1277 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1278 struct i915_power_well *power_well) 1279 { 1280 enum dpio_phy phy; 1281 1282 WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && 1283 power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); 1284 1285 if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { 1286 phy = DPIO_PHY0; 1287 assert_pll_disabled(dev_priv, PIPE_A); 1288 assert_pll_disabled(dev_priv, PIPE_B); 1289 } else { 1290 phy = DPIO_PHY1; 1291 assert_pll_disabled(dev_priv, PIPE_C); 1292 } 1293 1294 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1295 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1296 1297 vlv_set_power_well(dev_priv, power_well, false); 1298 1299 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1300 phy, dev_priv->chv_phy_control); 1301 1302 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1303 dev_priv->chv_phy_assert[phy] = true; 1304 1305 assert_chv_phy_status(dev_priv); 1306 } 1307 1308 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1309 enum dpio_channel ch, bool override, unsigned int mask) 1310 { 1311 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1312 u32 reg, val, expected, actual; 1313 1314 /* 1315 * The BIOS can leave the PHY is some weird state 1316 * where it doesn't fully power down some parts. 1317 * Disable the asserts until the PHY has been fully 1318 * reset (ie. the power well has been disabled at 1319 * least once). 1320 */ 1321 if (!dev_priv->chv_phy_assert[phy]) 1322 return; 1323 1324 if (ch == DPIO_CH0) 1325 reg = _CHV_CMN_DW0_CH0; 1326 else 1327 reg = _CHV_CMN_DW6_CH1; 1328 1329 mutex_lock(&dev_priv->sb_lock); 1330 val = vlv_dpio_read(dev_priv, pipe, reg); 1331 mutex_unlock(&dev_priv->sb_lock); 1332 1333 /* 1334 * This assumes !override is only used when the port is disabled. 1335 * All lanes should power down even without the override when 1336 * the port is disabled. 1337 */ 1338 if (!override || mask == 0xf) { 1339 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1340 /* 1341 * If CH1 common lane is not active anymore 1342 * (eg. for pipe B DPLL) the entire channel will 1343 * shut down, which causes the common lane registers 1344 * to read as 0. That means we can't actually check 1345 * the lane power down status bits, but as the entire 1346 * register reads as 0 it's a good indication that the 1347 * channel is indeed entirely powered down. 1348 */ 1349 if (ch == DPIO_CH1 && val == 0) 1350 expected = 0; 1351 } else if (mask != 0x0) { 1352 expected = DPIO_ANYDL_POWERDOWN; 1353 } else { 1354 expected = 0; 1355 } 1356 1357 if (ch == DPIO_CH0) 1358 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1359 else 1360 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1361 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1362 1363 WARN(actual != expected, 1364 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1365 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1366 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1367 reg, val); 1368 } 1369 1370 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1371 enum dpio_channel ch, bool override) 1372 { 1373 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1374 bool was_override; 1375 1376 mutex_lock(&power_domains->lock); 1377 1378 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1379 1380 if (override == was_override) 1381 goto out; 1382 1383 if (override) 1384 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1385 else 1386 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1387 1388 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1389 1390 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1391 phy, ch, dev_priv->chv_phy_control); 1392 1393 assert_chv_phy_status(dev_priv); 1394 1395 out: 1396 mutex_unlock(&power_domains->lock); 1397 1398 return was_override; 1399 } 1400 1401 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1402 bool override, unsigned int mask) 1403 { 1404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1405 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1406 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1407 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1408 1409 mutex_lock(&power_domains->lock); 1410 1411 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1412 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1413 1414 if (override) 1415 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1416 else 1417 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1418 1419 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1420 1421 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1422 phy, ch, mask, dev_priv->chv_phy_control); 1423 1424 assert_chv_phy_status(dev_priv); 1425 1426 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1427 1428 mutex_unlock(&power_domains->lock); 1429 } 1430 1431 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1432 struct i915_power_well *power_well) 1433 { 1434 enum pipe pipe = PIPE_A; 1435 bool enabled; 1436 u32 state, ctrl; 1437 1438 mutex_lock(&dev_priv->pcu_lock); 1439 1440 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1441 /* 1442 * We only ever set the power-on and power-gate states, anything 1443 * else is unexpected. 1444 */ 1445 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1446 enabled = state == DP_SSS_PWR_ON(pipe); 1447 1448 /* 1449 * A transient state at this point would mean some unexpected party 1450 * is poking at the power controls too. 1451 */ 1452 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1453 WARN_ON(ctrl << 16 != state); 1454 1455 mutex_unlock(&dev_priv->pcu_lock); 1456 1457 return enabled; 1458 } 1459 1460 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1461 struct i915_power_well *power_well, 1462 bool enable) 1463 { 1464 enum pipe pipe = PIPE_A; 1465 u32 state; 1466 u32 ctrl; 1467 1468 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1469 1470 mutex_lock(&dev_priv->pcu_lock); 1471 1472 #define COND \ 1473 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1474 1475 if (COND) 1476 goto out; 1477 1478 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1479 ctrl &= ~DP_SSC_MASK(pipe); 1480 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1481 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1482 1483 if (wait_for(COND, 100)) 1484 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1485 state, 1486 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1487 1488 #undef COND 1489 1490 out: 1491 mutex_unlock(&dev_priv->pcu_lock); 1492 } 1493 1494 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1495 struct i915_power_well *power_well) 1496 { 1497 chv_set_pipe_power_well(dev_priv, power_well, true); 1498 1499 vlv_display_power_well_init(dev_priv); 1500 } 1501 1502 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1503 struct i915_power_well *power_well) 1504 { 1505 vlv_display_power_well_deinit(dev_priv); 1506 1507 chv_set_pipe_power_well(dev_priv, power_well, false); 1508 } 1509 1510 static void 1511 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1512 enum intel_display_power_domain domain) 1513 { 1514 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1515 struct i915_power_well *power_well; 1516 1517 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) 1518 intel_power_well_get(dev_priv, power_well); 1519 1520 power_domains->domain_use_count[domain]++; 1521 } 1522 1523 /** 1524 * intel_display_power_get - grab a power domain reference 1525 * @dev_priv: i915 device instance 1526 * @domain: power domain to reference 1527 * 1528 * This function grabs a power domain reference for @domain and ensures that the 1529 * power domain and all its parents are powered up. Therefore users should only 1530 * grab a reference to the innermost power domain they need. 1531 * 1532 * Any power domain reference obtained by this function must have a symmetric 1533 * call to intel_display_power_put() to release the reference again. 1534 */ 1535 void intel_display_power_get(struct drm_i915_private *dev_priv, 1536 enum intel_display_power_domain domain) 1537 { 1538 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1539 1540 intel_runtime_pm_get(dev_priv); 1541 1542 mutex_lock(&power_domains->lock); 1543 1544 __intel_display_power_get_domain(dev_priv, domain); 1545 1546 mutex_unlock(&power_domains->lock); 1547 } 1548 1549 /** 1550 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1551 * @dev_priv: i915 device instance 1552 * @domain: power domain to reference 1553 * 1554 * This function grabs a power domain reference for @domain and ensures that the 1555 * power domain and all its parents are powered up. Therefore users should only 1556 * grab a reference to the innermost power domain they need. 1557 * 1558 * Any power domain reference obtained by this function must have a symmetric 1559 * call to intel_display_power_put() to release the reference again. 1560 */ 1561 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1562 enum intel_display_power_domain domain) 1563 { 1564 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1565 bool is_enabled; 1566 1567 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1568 return false; 1569 1570 mutex_lock(&power_domains->lock); 1571 1572 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1573 __intel_display_power_get_domain(dev_priv, domain); 1574 is_enabled = true; 1575 } else { 1576 is_enabled = false; 1577 } 1578 1579 mutex_unlock(&power_domains->lock); 1580 1581 if (!is_enabled) 1582 intel_runtime_pm_put(dev_priv); 1583 1584 return is_enabled; 1585 } 1586 1587 /** 1588 * intel_display_power_put - release a power domain reference 1589 * @dev_priv: i915 device instance 1590 * @domain: power domain to reference 1591 * 1592 * This function drops the power domain reference obtained by 1593 * intel_display_power_get() and might power down the corresponding hardware 1594 * block right away if this is the last reference. 1595 */ 1596 void intel_display_power_put(struct drm_i915_private *dev_priv, 1597 enum intel_display_power_domain domain) 1598 { 1599 struct i915_power_domains *power_domains; 1600 struct i915_power_well *power_well; 1601 1602 power_domains = &dev_priv->power_domains; 1603 1604 mutex_lock(&power_domains->lock); 1605 1606 WARN(!power_domains->domain_use_count[domain], 1607 "Use count on domain %s is already zero\n", 1608 intel_display_power_domain_str(domain)); 1609 power_domains->domain_use_count[domain]--; 1610 1611 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) 1612 intel_power_well_put(dev_priv, power_well); 1613 1614 mutex_unlock(&power_domains->lock); 1615 1616 intel_runtime_pm_put(dev_priv); 1617 } 1618 1619 #define I830_PIPES_POWER_DOMAINS ( \ 1620 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1621 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1622 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1623 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1624 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1625 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1626 BIT_ULL(POWER_DOMAIN_INIT)) 1627 1628 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1629 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1630 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1631 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1632 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1633 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1634 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1635 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1636 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1637 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1638 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1639 BIT_ULL(POWER_DOMAIN_VGA) | \ 1640 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1641 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1642 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1643 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1644 BIT_ULL(POWER_DOMAIN_INIT)) 1645 1646 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1647 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1648 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1649 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1650 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1651 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1652 BIT_ULL(POWER_DOMAIN_INIT)) 1653 1654 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1655 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1656 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1657 BIT_ULL(POWER_DOMAIN_INIT)) 1658 1659 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1660 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1661 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1662 BIT_ULL(POWER_DOMAIN_INIT)) 1663 1664 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1665 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1666 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1667 BIT_ULL(POWER_DOMAIN_INIT)) 1668 1669 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1670 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1671 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1672 BIT_ULL(POWER_DOMAIN_INIT)) 1673 1674 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1675 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1676 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1677 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1678 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1679 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1680 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1681 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1682 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1683 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1684 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1685 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1686 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1687 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1688 BIT_ULL(POWER_DOMAIN_VGA) | \ 1689 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1690 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1691 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1692 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1693 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1694 BIT_ULL(POWER_DOMAIN_INIT)) 1695 1696 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1697 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1698 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1699 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1700 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1701 BIT_ULL(POWER_DOMAIN_INIT)) 1702 1703 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1704 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1705 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1706 BIT_ULL(POWER_DOMAIN_INIT)) 1707 1708 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1709 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1710 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1711 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1712 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1713 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1714 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1715 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1716 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1717 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1718 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1719 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1720 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1721 BIT_ULL(POWER_DOMAIN_VGA) | \ 1722 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1723 BIT_ULL(POWER_DOMAIN_INIT)) 1724 1725 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1726 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1727 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1728 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1729 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1730 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1731 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1732 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1733 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1734 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1735 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1736 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1737 BIT_ULL(POWER_DOMAIN_VGA) | \ 1738 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1739 BIT_ULL(POWER_DOMAIN_INIT)) 1740 1741 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1742 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1743 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1744 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1745 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1746 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1747 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1748 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1749 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1750 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1751 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1752 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 1753 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1754 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1755 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1756 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1757 BIT_ULL(POWER_DOMAIN_VGA) | \ 1758 BIT_ULL(POWER_DOMAIN_INIT)) 1759 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ 1760 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1761 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ 1762 BIT_ULL(POWER_DOMAIN_INIT)) 1763 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1764 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1765 BIT_ULL(POWER_DOMAIN_INIT)) 1766 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1767 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1768 BIT_ULL(POWER_DOMAIN_INIT)) 1769 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ 1770 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1771 BIT_ULL(POWER_DOMAIN_INIT)) 1772 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1773 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1774 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1775 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1776 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1777 BIT_ULL(POWER_DOMAIN_INIT)) 1778 1779 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1780 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1781 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1782 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1783 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1784 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1785 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1786 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1787 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1788 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1789 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1790 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1791 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1792 BIT_ULL(POWER_DOMAIN_VGA) | \ 1793 BIT_ULL(POWER_DOMAIN_INIT)) 1794 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1795 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1796 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1797 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1798 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1799 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1800 BIT_ULL(POWER_DOMAIN_INIT)) 1801 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 1802 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1803 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1804 BIT_ULL(POWER_DOMAIN_INIT)) 1805 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 1806 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1807 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1808 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1809 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1810 BIT_ULL(POWER_DOMAIN_INIT)) 1811 1812 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1813 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1814 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1815 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1816 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1817 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1818 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1819 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1820 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1821 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1822 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1823 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1824 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1825 BIT_ULL(POWER_DOMAIN_VGA) | \ 1826 BIT_ULL(POWER_DOMAIN_INIT)) 1827 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ 1828 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) 1829 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1830 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) 1831 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1832 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) 1833 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ 1834 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1835 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1836 BIT_ULL(POWER_DOMAIN_INIT)) 1837 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ 1838 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1839 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1840 BIT_ULL(POWER_DOMAIN_INIT)) 1841 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ 1842 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1843 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1844 BIT_ULL(POWER_DOMAIN_INIT)) 1845 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1846 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1847 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \ 1848 BIT_ULL(POWER_DOMAIN_INIT)) 1849 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1850 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1851 BIT_ULL(POWER_DOMAIN_INIT)) 1852 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1853 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1854 BIT_ULL(POWER_DOMAIN_INIT)) 1855 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1856 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1857 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1858 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1859 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1860 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1861 BIT_ULL(POWER_DOMAIN_INIT)) 1862 1863 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1864 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1865 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1866 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1867 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1868 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1869 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1870 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1871 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1872 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1873 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1874 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \ 1875 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1876 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1877 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1878 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1879 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1880 BIT_ULL(POWER_DOMAIN_VGA) | \ 1881 BIT_ULL(POWER_DOMAIN_INIT)) 1882 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ 1883 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1884 BIT_ULL(POWER_DOMAIN_INIT)) 1885 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ 1886 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1887 BIT_ULL(POWER_DOMAIN_INIT)) 1888 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ 1889 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1890 BIT_ULL(POWER_DOMAIN_INIT)) 1891 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ 1892 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1893 BIT_ULL(POWER_DOMAIN_INIT)) 1894 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1895 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1896 BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \ 1897 BIT_ULL(POWER_DOMAIN_INIT)) 1898 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1899 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1900 BIT_ULL(POWER_DOMAIN_INIT)) 1901 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1902 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1903 BIT_ULL(POWER_DOMAIN_INIT)) 1904 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ 1905 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1906 BIT_ULL(POWER_DOMAIN_INIT)) 1907 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \ 1908 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1909 BIT_ULL(POWER_DOMAIN_INIT)) 1910 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \ 1911 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \ 1912 BIT_ULL(POWER_DOMAIN_INIT)) 1913 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1914 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1915 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1916 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1917 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1918 BIT_ULL(POWER_DOMAIN_INIT)) 1919 1920 /* 1921 * ICL PW_0/PG_0 domains (HW/DMC control): 1922 * - PCI 1923 * - clocks except port PLL 1924 * - central power except FBC 1925 * - shared functions except pipe interrupts, pipe MBUS, DBUF registers 1926 * ICL PW_1/PG_1 domains (HW/DMC control): 1927 * - DBUF function 1928 * - PIPE_A and its planes, except VGA 1929 * - transcoder EDP + PSR 1930 * - transcoder DSI 1931 * - DDI_A 1932 * - FBC 1933 */ 1934 #define ICL_PW_4_POWER_DOMAINS ( \ 1935 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1936 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1937 BIT_ULL(POWER_DOMAIN_INIT)) 1938 /* VDSC/joining */ 1939 #define ICL_PW_3_POWER_DOMAINS ( \ 1940 ICL_PW_4_POWER_DOMAINS | \ 1941 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1942 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1943 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1944 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1945 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1946 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1947 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1948 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1949 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1950 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1951 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1952 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 1953 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ 1954 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \ 1955 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \ 1956 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1957 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1958 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1959 BIT_ULL(POWER_DOMAIN_AUX_E) | \ 1960 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1961 BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \ 1962 BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \ 1963 BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \ 1964 BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \ 1965 BIT_ULL(POWER_DOMAIN_VGA) | \ 1966 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1967 BIT_ULL(POWER_DOMAIN_INIT)) 1968 /* 1969 * - transcoder WD 1970 * - KVMR (HW control) 1971 */ 1972 #define ICL_PW_2_POWER_DOMAINS ( \ 1973 ICL_PW_3_POWER_DOMAINS | \ 1974 BIT_ULL(POWER_DOMAIN_INIT)) 1975 /* 1976 * - eDP/DSI VDSC 1977 * - KVMR (HW control) 1978 */ 1979 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1980 ICL_PW_2_POWER_DOMAINS | \ 1981 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1982 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1983 BIT_ULL(POWER_DOMAIN_INIT)) 1984 1985 #define ICL_DDI_IO_A_POWER_DOMAINS ( \ 1986 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) 1987 #define ICL_DDI_IO_B_POWER_DOMAINS ( \ 1988 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) 1989 #define ICL_DDI_IO_C_POWER_DOMAINS ( \ 1990 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) 1991 #define ICL_DDI_IO_D_POWER_DOMAINS ( \ 1992 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO)) 1993 #define ICL_DDI_IO_E_POWER_DOMAINS ( \ 1994 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO)) 1995 #define ICL_DDI_IO_F_POWER_DOMAINS ( \ 1996 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)) 1997 1998 #define ICL_AUX_A_IO_POWER_DOMAINS ( \ 1999 BIT_ULL(POWER_DOMAIN_AUX_A)) 2000 #define ICL_AUX_B_IO_POWER_DOMAINS ( \ 2001 BIT_ULL(POWER_DOMAIN_AUX_B)) 2002 #define ICL_AUX_C_IO_POWER_DOMAINS ( \ 2003 BIT_ULL(POWER_DOMAIN_AUX_C)) 2004 #define ICL_AUX_D_IO_POWER_DOMAINS ( \ 2005 BIT_ULL(POWER_DOMAIN_AUX_D)) 2006 #define ICL_AUX_E_IO_POWER_DOMAINS ( \ 2007 BIT_ULL(POWER_DOMAIN_AUX_E)) 2008 #define ICL_AUX_F_IO_POWER_DOMAINS ( \ 2009 BIT_ULL(POWER_DOMAIN_AUX_F)) 2010 #define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \ 2011 BIT_ULL(POWER_DOMAIN_AUX_TBT1)) 2012 #define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \ 2013 BIT_ULL(POWER_DOMAIN_AUX_TBT2)) 2014 #define ICL_AUX_TBT3_IO_POWER_DOMAINS ( \ 2015 BIT_ULL(POWER_DOMAIN_AUX_TBT3)) 2016 #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \ 2017 BIT_ULL(POWER_DOMAIN_AUX_TBT4)) 2018 2019 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 2020 .sync_hw = i9xx_power_well_sync_hw_noop, 2021 .enable = i9xx_always_on_power_well_noop, 2022 .disable = i9xx_always_on_power_well_noop, 2023 .is_enabled = i9xx_always_on_power_well_enabled, 2024 }; 2025 2026 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 2027 .sync_hw = i9xx_power_well_sync_hw_noop, 2028 .enable = chv_pipe_power_well_enable, 2029 .disable = chv_pipe_power_well_disable, 2030 .is_enabled = chv_pipe_power_well_enabled, 2031 }; 2032 2033 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 2034 .sync_hw = i9xx_power_well_sync_hw_noop, 2035 .enable = chv_dpio_cmn_power_well_enable, 2036 .disable = chv_dpio_cmn_power_well_disable, 2037 .is_enabled = vlv_power_well_enabled, 2038 }; 2039 2040 static const struct i915_power_well_desc i9xx_always_on_power_well[] = { 2041 { 2042 .name = "always-on", 2043 .always_on = 1, 2044 .domains = POWER_DOMAIN_MASK, 2045 .ops = &i9xx_always_on_power_well_ops, 2046 .id = DISP_PW_ID_NONE, 2047 }, 2048 }; 2049 2050 static const struct i915_power_well_ops i830_pipes_power_well_ops = { 2051 .sync_hw = i830_pipes_power_well_sync_hw, 2052 .enable = i830_pipes_power_well_enable, 2053 .disable = i830_pipes_power_well_disable, 2054 .is_enabled = i830_pipes_power_well_enabled, 2055 }; 2056 2057 static const struct i915_power_well_desc i830_power_wells[] = { 2058 { 2059 .name = "always-on", 2060 .always_on = 1, 2061 .domains = POWER_DOMAIN_MASK, 2062 .ops = &i9xx_always_on_power_well_ops, 2063 .id = DISP_PW_ID_NONE, 2064 }, 2065 { 2066 .name = "pipes", 2067 .domains = I830_PIPES_POWER_DOMAINS, 2068 .ops = &i830_pipes_power_well_ops, 2069 .id = DISP_PW_ID_NONE, 2070 }, 2071 }; 2072 2073 static const struct i915_power_well_ops hsw_power_well_ops = { 2074 .sync_hw = hsw_power_well_sync_hw, 2075 .enable = hsw_power_well_enable, 2076 .disable = hsw_power_well_disable, 2077 .is_enabled = hsw_power_well_enabled, 2078 }; 2079 2080 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 2081 .sync_hw = i9xx_power_well_sync_hw_noop, 2082 .enable = gen9_dc_off_power_well_enable, 2083 .disable = gen9_dc_off_power_well_disable, 2084 .is_enabled = gen9_dc_off_power_well_enabled, 2085 }; 2086 2087 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 2088 .sync_hw = i9xx_power_well_sync_hw_noop, 2089 .enable = bxt_dpio_cmn_power_well_enable, 2090 .disable = bxt_dpio_cmn_power_well_disable, 2091 .is_enabled = bxt_dpio_cmn_power_well_enabled, 2092 }; 2093 2094 static const struct i915_power_well_regs hsw_power_well_regs = { 2095 .bios = HSW_PWR_WELL_CTL1, 2096 .driver = HSW_PWR_WELL_CTL2, 2097 .kvmr = HSW_PWR_WELL_CTL3, 2098 .debug = HSW_PWR_WELL_CTL4, 2099 }; 2100 2101 static const struct i915_power_well_desc hsw_power_wells[] = { 2102 { 2103 .name = "always-on", 2104 .always_on = 1, 2105 .domains = POWER_DOMAIN_MASK, 2106 .ops = &i9xx_always_on_power_well_ops, 2107 .id = DISP_PW_ID_NONE, 2108 }, 2109 { 2110 .name = "display", 2111 .domains = HSW_DISPLAY_POWER_DOMAINS, 2112 .ops = &hsw_power_well_ops, 2113 .id = HSW_DISP_PW_GLOBAL, 2114 { 2115 .hsw.regs = &hsw_power_well_regs, 2116 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 2117 .hsw.has_vga = true, 2118 }, 2119 }, 2120 }; 2121 2122 static const struct i915_power_well_desc bdw_power_wells[] = { 2123 { 2124 .name = "always-on", 2125 .always_on = 1, 2126 .domains = POWER_DOMAIN_MASK, 2127 .ops = &i9xx_always_on_power_well_ops, 2128 .id = DISP_PW_ID_NONE, 2129 }, 2130 { 2131 .name = "display", 2132 .domains = BDW_DISPLAY_POWER_DOMAINS, 2133 .ops = &hsw_power_well_ops, 2134 .id = HSW_DISP_PW_GLOBAL, 2135 { 2136 .hsw.regs = &hsw_power_well_regs, 2137 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 2138 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2139 .hsw.has_vga = true, 2140 }, 2141 }, 2142 }; 2143 2144 static const struct i915_power_well_ops vlv_display_power_well_ops = { 2145 .sync_hw = i9xx_power_well_sync_hw_noop, 2146 .enable = vlv_display_power_well_enable, 2147 .disable = vlv_display_power_well_disable, 2148 .is_enabled = vlv_power_well_enabled, 2149 }; 2150 2151 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2152 .sync_hw = i9xx_power_well_sync_hw_noop, 2153 .enable = vlv_dpio_cmn_power_well_enable, 2154 .disable = vlv_dpio_cmn_power_well_disable, 2155 .is_enabled = vlv_power_well_enabled, 2156 }; 2157 2158 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2159 .sync_hw = i9xx_power_well_sync_hw_noop, 2160 .enable = vlv_power_well_enable, 2161 .disable = vlv_power_well_disable, 2162 .is_enabled = vlv_power_well_enabled, 2163 }; 2164 2165 static const struct i915_power_well_desc vlv_power_wells[] = { 2166 { 2167 .name = "always-on", 2168 .always_on = 1, 2169 .domains = POWER_DOMAIN_MASK, 2170 .ops = &i9xx_always_on_power_well_ops, 2171 .id = DISP_PW_ID_NONE, 2172 }, 2173 { 2174 .name = "display", 2175 .domains = VLV_DISPLAY_POWER_DOMAINS, 2176 .ops = &vlv_display_power_well_ops, 2177 .id = VLV_DISP_PW_DISP2D, 2178 { 2179 .vlv.idx = PUNIT_PWGT_IDX_DISP2D, 2180 }, 2181 }, 2182 { 2183 .name = "dpio-tx-b-01", 2184 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2185 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2186 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2187 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2188 .ops = &vlv_dpio_power_well_ops, 2189 .id = DISP_PW_ID_NONE, 2190 { 2191 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01, 2192 }, 2193 }, 2194 { 2195 .name = "dpio-tx-b-23", 2196 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2197 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2198 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2199 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2200 .ops = &vlv_dpio_power_well_ops, 2201 .id = DISP_PW_ID_NONE, 2202 { 2203 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23, 2204 }, 2205 }, 2206 { 2207 .name = "dpio-tx-c-01", 2208 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2209 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2210 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2211 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2212 .ops = &vlv_dpio_power_well_ops, 2213 .id = DISP_PW_ID_NONE, 2214 { 2215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01, 2216 }, 2217 }, 2218 { 2219 .name = "dpio-tx-c-23", 2220 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2221 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2222 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2223 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2224 .ops = &vlv_dpio_power_well_ops, 2225 .id = DISP_PW_ID_NONE, 2226 { 2227 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23, 2228 }, 2229 }, 2230 { 2231 .name = "dpio-common", 2232 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2233 .ops = &vlv_dpio_cmn_power_well_ops, 2234 .id = VLV_DISP_PW_DPIO_CMN_BC, 2235 { 2236 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 2237 }, 2238 }, 2239 }; 2240 2241 static const struct i915_power_well_desc chv_power_wells[] = { 2242 { 2243 .name = "always-on", 2244 .always_on = 1, 2245 .domains = POWER_DOMAIN_MASK, 2246 .ops = &i9xx_always_on_power_well_ops, 2247 .id = DISP_PW_ID_NONE, 2248 }, 2249 { 2250 .name = "display", 2251 /* 2252 * Pipe A power well is the new disp2d well. Pipe B and C 2253 * power wells don't actually exist. Pipe A power well is 2254 * required for any pipe to work. 2255 */ 2256 .domains = CHV_DISPLAY_POWER_DOMAINS, 2257 .ops = &chv_pipe_power_well_ops, 2258 .id = DISP_PW_ID_NONE, 2259 }, 2260 { 2261 .name = "dpio-common-bc", 2262 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2263 .ops = &chv_dpio_cmn_power_well_ops, 2264 .id = VLV_DISP_PW_DPIO_CMN_BC, 2265 { 2266 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 2267 }, 2268 }, 2269 { 2270 .name = "dpio-common-d", 2271 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2272 .ops = &chv_dpio_cmn_power_well_ops, 2273 .id = CHV_DISP_PW_DPIO_CMN_D, 2274 { 2275 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, 2276 }, 2277 }, 2278 }; 2279 2280 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2281 enum i915_power_well_id power_well_id) 2282 { 2283 struct i915_power_well *power_well; 2284 bool ret; 2285 2286 power_well = lookup_power_well(dev_priv, power_well_id); 2287 ret = power_well->desc->ops->is_enabled(dev_priv, power_well); 2288 2289 return ret; 2290 } 2291 2292 static const struct i915_power_well_desc skl_power_wells[] = { 2293 { 2294 .name = "always-on", 2295 .always_on = 1, 2296 .domains = POWER_DOMAIN_MASK, 2297 .ops = &i9xx_always_on_power_well_ops, 2298 .id = DISP_PW_ID_NONE, 2299 }, 2300 { 2301 .name = "power well 1", 2302 /* Handled by the DMC firmware */ 2303 .domains = 0, 2304 .ops = &hsw_power_well_ops, 2305 .id = SKL_DISP_PW_1, 2306 { 2307 .hsw.regs = &hsw_power_well_regs, 2308 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 2309 .hsw.has_fuses = true, 2310 }, 2311 }, 2312 { 2313 .name = "MISC IO power well", 2314 /* Handled by the DMC firmware */ 2315 .domains = 0, 2316 .ops = &hsw_power_well_ops, 2317 .id = SKL_DISP_PW_MISC_IO, 2318 { 2319 .hsw.regs = &hsw_power_well_regs, 2320 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO, 2321 }, 2322 }, 2323 { 2324 .name = "DC off", 2325 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2326 .ops = &gen9_dc_off_power_well_ops, 2327 .id = DISP_PW_ID_NONE, 2328 }, 2329 { 2330 .name = "power well 2", 2331 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2332 .ops = &hsw_power_well_ops, 2333 .id = SKL_DISP_PW_2, 2334 { 2335 .hsw.regs = &hsw_power_well_regs, 2336 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 2337 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2338 .hsw.has_vga = true, 2339 .hsw.has_fuses = true, 2340 }, 2341 }, 2342 { 2343 .name = "DDI A/E IO power well", 2344 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, 2345 .ops = &hsw_power_well_ops, 2346 .id = DISP_PW_ID_NONE, 2347 { 2348 .hsw.regs = &hsw_power_well_regs, 2349 .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E, 2350 }, 2351 }, 2352 { 2353 .name = "DDI B IO power well", 2354 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2355 .ops = &hsw_power_well_ops, 2356 .id = DISP_PW_ID_NONE, 2357 { 2358 .hsw.regs = &hsw_power_well_regs, 2359 .hsw.idx = SKL_PW_CTL_IDX_DDI_B, 2360 }, 2361 }, 2362 { 2363 .name = "DDI C IO power well", 2364 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2365 .ops = &hsw_power_well_ops, 2366 .id = DISP_PW_ID_NONE, 2367 { 2368 .hsw.regs = &hsw_power_well_regs, 2369 .hsw.idx = SKL_PW_CTL_IDX_DDI_C, 2370 }, 2371 }, 2372 { 2373 .name = "DDI D IO power well", 2374 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, 2375 .ops = &hsw_power_well_ops, 2376 .id = DISP_PW_ID_NONE, 2377 { 2378 .hsw.regs = &hsw_power_well_regs, 2379 .hsw.idx = SKL_PW_CTL_IDX_DDI_D, 2380 }, 2381 }, 2382 }; 2383 2384 static const struct i915_power_well_desc bxt_power_wells[] = { 2385 { 2386 .name = "always-on", 2387 .always_on = 1, 2388 .domains = POWER_DOMAIN_MASK, 2389 .ops = &i9xx_always_on_power_well_ops, 2390 .id = DISP_PW_ID_NONE, 2391 }, 2392 { 2393 .name = "power well 1", 2394 .domains = 0, 2395 .ops = &hsw_power_well_ops, 2396 .id = SKL_DISP_PW_1, 2397 { 2398 .hsw.regs = &hsw_power_well_regs, 2399 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 2400 .hsw.has_fuses = true, 2401 }, 2402 }, 2403 { 2404 .name = "DC off", 2405 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2406 .ops = &gen9_dc_off_power_well_ops, 2407 .id = DISP_PW_ID_NONE, 2408 }, 2409 { 2410 .name = "power well 2", 2411 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2412 .ops = &hsw_power_well_ops, 2413 .id = SKL_DISP_PW_2, 2414 { 2415 .hsw.regs = &hsw_power_well_regs, 2416 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 2417 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2418 .hsw.has_vga = true, 2419 .hsw.has_fuses = true, 2420 }, 2421 }, 2422 { 2423 .name = "dpio-common-a", 2424 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2425 .ops = &bxt_dpio_cmn_power_well_ops, 2426 .id = BXT_DISP_PW_DPIO_CMN_A, 2427 { 2428 .bxt.phy = DPIO_PHY1, 2429 }, 2430 }, 2431 { 2432 .name = "dpio-common-bc", 2433 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2434 .ops = &bxt_dpio_cmn_power_well_ops, 2435 .id = VLV_DISP_PW_DPIO_CMN_BC, 2436 { 2437 .bxt.phy = DPIO_PHY0, 2438 }, 2439 }, 2440 }; 2441 2442 static const struct i915_power_well_desc glk_power_wells[] = { 2443 { 2444 .name = "always-on", 2445 .always_on = 1, 2446 .domains = POWER_DOMAIN_MASK, 2447 .ops = &i9xx_always_on_power_well_ops, 2448 .id = DISP_PW_ID_NONE, 2449 }, 2450 { 2451 .name = "power well 1", 2452 /* Handled by the DMC firmware */ 2453 .domains = 0, 2454 .ops = &hsw_power_well_ops, 2455 .id = SKL_DISP_PW_1, 2456 { 2457 .hsw.regs = &hsw_power_well_regs, 2458 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 2459 .hsw.has_fuses = true, 2460 }, 2461 }, 2462 { 2463 .name = "DC off", 2464 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, 2465 .ops = &gen9_dc_off_power_well_ops, 2466 .id = DISP_PW_ID_NONE, 2467 }, 2468 { 2469 .name = "power well 2", 2470 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2471 .ops = &hsw_power_well_ops, 2472 .id = SKL_DISP_PW_2, 2473 { 2474 .hsw.regs = &hsw_power_well_regs, 2475 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 2476 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2477 .hsw.has_vga = true, 2478 .hsw.has_fuses = true, 2479 }, 2480 }, 2481 { 2482 .name = "dpio-common-a", 2483 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, 2484 .ops = &bxt_dpio_cmn_power_well_ops, 2485 .id = BXT_DISP_PW_DPIO_CMN_A, 2486 { 2487 .bxt.phy = DPIO_PHY1, 2488 }, 2489 }, 2490 { 2491 .name = "dpio-common-b", 2492 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, 2493 .ops = &bxt_dpio_cmn_power_well_ops, 2494 .id = VLV_DISP_PW_DPIO_CMN_BC, 2495 { 2496 .bxt.phy = DPIO_PHY0, 2497 }, 2498 }, 2499 { 2500 .name = "dpio-common-c", 2501 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, 2502 .ops = &bxt_dpio_cmn_power_well_ops, 2503 .id = GLK_DISP_PW_DPIO_CMN_C, 2504 { 2505 .bxt.phy = DPIO_PHY2, 2506 }, 2507 }, 2508 { 2509 .name = "AUX A", 2510 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, 2511 .ops = &hsw_power_well_ops, 2512 .id = DISP_PW_ID_NONE, 2513 { 2514 .hsw.regs = &hsw_power_well_regs, 2515 .hsw.idx = GLK_PW_CTL_IDX_AUX_A, 2516 }, 2517 }, 2518 { 2519 .name = "AUX B", 2520 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, 2521 .ops = &hsw_power_well_ops, 2522 .id = DISP_PW_ID_NONE, 2523 { 2524 .hsw.regs = &hsw_power_well_regs, 2525 .hsw.idx = GLK_PW_CTL_IDX_AUX_B, 2526 }, 2527 }, 2528 { 2529 .name = "AUX C", 2530 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, 2531 .ops = &hsw_power_well_ops, 2532 .id = DISP_PW_ID_NONE, 2533 { 2534 .hsw.regs = &hsw_power_well_regs, 2535 .hsw.idx = GLK_PW_CTL_IDX_AUX_C, 2536 }, 2537 }, 2538 { 2539 .name = "DDI A IO power well", 2540 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, 2541 .ops = &hsw_power_well_ops, 2542 .id = DISP_PW_ID_NONE, 2543 { 2544 .hsw.regs = &hsw_power_well_regs, 2545 .hsw.idx = GLK_PW_CTL_IDX_DDI_A, 2546 }, 2547 }, 2548 { 2549 .name = "DDI B IO power well", 2550 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2551 .ops = &hsw_power_well_ops, 2552 .id = DISP_PW_ID_NONE, 2553 { 2554 .hsw.regs = &hsw_power_well_regs, 2555 .hsw.idx = SKL_PW_CTL_IDX_DDI_B, 2556 }, 2557 }, 2558 { 2559 .name = "DDI C IO power well", 2560 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2561 .ops = &hsw_power_well_ops, 2562 .id = DISP_PW_ID_NONE, 2563 { 2564 .hsw.regs = &hsw_power_well_regs, 2565 .hsw.idx = SKL_PW_CTL_IDX_DDI_C, 2566 }, 2567 }, 2568 }; 2569 2570 static const struct i915_power_well_desc cnl_power_wells[] = { 2571 { 2572 .name = "always-on", 2573 .always_on = 1, 2574 .domains = POWER_DOMAIN_MASK, 2575 .ops = &i9xx_always_on_power_well_ops, 2576 .id = DISP_PW_ID_NONE, 2577 }, 2578 { 2579 .name = "power well 1", 2580 /* Handled by the DMC firmware */ 2581 .domains = 0, 2582 .ops = &hsw_power_well_ops, 2583 .id = SKL_DISP_PW_1, 2584 { 2585 .hsw.regs = &hsw_power_well_regs, 2586 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 2587 .hsw.has_fuses = true, 2588 }, 2589 }, 2590 { 2591 .name = "AUX A", 2592 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, 2593 .ops = &hsw_power_well_ops, 2594 .id = DISP_PW_ID_NONE, 2595 { 2596 .hsw.regs = &hsw_power_well_regs, 2597 .hsw.idx = GLK_PW_CTL_IDX_AUX_A, 2598 }, 2599 }, 2600 { 2601 .name = "AUX B", 2602 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, 2603 .ops = &hsw_power_well_ops, 2604 .id = DISP_PW_ID_NONE, 2605 { 2606 .hsw.regs = &hsw_power_well_regs, 2607 .hsw.idx = GLK_PW_CTL_IDX_AUX_B, 2608 }, 2609 }, 2610 { 2611 .name = "AUX C", 2612 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, 2613 .ops = &hsw_power_well_ops, 2614 .id = DISP_PW_ID_NONE, 2615 { 2616 .hsw.regs = &hsw_power_well_regs, 2617 .hsw.idx = GLK_PW_CTL_IDX_AUX_C, 2618 }, 2619 }, 2620 { 2621 .name = "AUX D", 2622 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, 2623 .ops = &hsw_power_well_ops, 2624 .id = DISP_PW_ID_NONE, 2625 { 2626 .hsw.regs = &hsw_power_well_regs, 2627 .hsw.idx = CNL_PW_CTL_IDX_AUX_D, 2628 }, 2629 }, 2630 { 2631 .name = "DC off", 2632 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, 2633 .ops = &gen9_dc_off_power_well_ops, 2634 .id = DISP_PW_ID_NONE, 2635 }, 2636 { 2637 .name = "power well 2", 2638 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2639 .ops = &hsw_power_well_ops, 2640 .id = SKL_DISP_PW_2, 2641 { 2642 .hsw.regs = &hsw_power_well_regs, 2643 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 2644 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2645 .hsw.has_vga = true, 2646 .hsw.has_fuses = true, 2647 }, 2648 }, 2649 { 2650 .name = "DDI A IO power well", 2651 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, 2652 .ops = &hsw_power_well_ops, 2653 .id = DISP_PW_ID_NONE, 2654 { 2655 .hsw.regs = &hsw_power_well_regs, 2656 .hsw.idx = GLK_PW_CTL_IDX_DDI_A, 2657 }, 2658 }, 2659 { 2660 .name = "DDI B IO power well", 2661 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, 2662 .ops = &hsw_power_well_ops, 2663 .id = DISP_PW_ID_NONE, 2664 { 2665 .hsw.regs = &hsw_power_well_regs, 2666 .hsw.idx = SKL_PW_CTL_IDX_DDI_B, 2667 }, 2668 }, 2669 { 2670 .name = "DDI C IO power well", 2671 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, 2672 .ops = &hsw_power_well_ops, 2673 .id = DISP_PW_ID_NONE, 2674 { 2675 .hsw.regs = &hsw_power_well_regs, 2676 .hsw.idx = SKL_PW_CTL_IDX_DDI_C, 2677 }, 2678 }, 2679 { 2680 .name = "DDI D IO power well", 2681 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, 2682 .ops = &hsw_power_well_ops, 2683 .id = DISP_PW_ID_NONE, 2684 { 2685 .hsw.regs = &hsw_power_well_regs, 2686 .hsw.idx = SKL_PW_CTL_IDX_DDI_D, 2687 }, 2688 }, 2689 { 2690 .name = "DDI F IO power well", 2691 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, 2692 .ops = &hsw_power_well_ops, 2693 .id = DISP_PW_ID_NONE, 2694 { 2695 .hsw.regs = &hsw_power_well_regs, 2696 .hsw.idx = CNL_PW_CTL_IDX_DDI_F, 2697 }, 2698 }, 2699 { 2700 .name = "AUX F", 2701 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, 2702 .ops = &hsw_power_well_ops, 2703 .id = DISP_PW_ID_NONE, 2704 { 2705 .hsw.regs = &hsw_power_well_regs, 2706 .hsw.idx = CNL_PW_CTL_IDX_AUX_F, 2707 }, 2708 }, 2709 }; 2710 2711 static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = { 2712 .sync_hw = hsw_power_well_sync_hw, 2713 .enable = icl_combo_phy_aux_power_well_enable, 2714 .disable = icl_combo_phy_aux_power_well_disable, 2715 .is_enabled = hsw_power_well_enabled, 2716 }; 2717 2718 static const struct i915_power_well_regs icl_aux_power_well_regs = { 2719 .bios = ICL_PWR_WELL_CTL_AUX1, 2720 .driver = ICL_PWR_WELL_CTL_AUX2, 2721 .debug = ICL_PWR_WELL_CTL_AUX4, 2722 }; 2723 2724 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2725 .bios = ICL_PWR_WELL_CTL_DDI1, 2726 .driver = ICL_PWR_WELL_CTL_DDI2, 2727 .debug = ICL_PWR_WELL_CTL_DDI4, 2728 }; 2729 2730 static const struct i915_power_well_desc icl_power_wells[] = { 2731 { 2732 .name = "always-on", 2733 .always_on = 1, 2734 .domains = POWER_DOMAIN_MASK, 2735 .ops = &i9xx_always_on_power_well_ops, 2736 .id = DISP_PW_ID_NONE, 2737 }, 2738 { 2739 .name = "power well 1", 2740 /* Handled by the DMC firmware */ 2741 .domains = 0, 2742 .ops = &hsw_power_well_ops, 2743 .id = SKL_DISP_PW_1, 2744 { 2745 .hsw.regs = &hsw_power_well_regs, 2746 .hsw.idx = ICL_PW_CTL_IDX_PW_1, 2747 .hsw.has_fuses = true, 2748 }, 2749 }, 2750 { 2751 .name = "power well 2", 2752 .domains = ICL_PW_2_POWER_DOMAINS, 2753 .ops = &hsw_power_well_ops, 2754 .id = SKL_DISP_PW_2, 2755 { 2756 .hsw.regs = &hsw_power_well_regs, 2757 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 2758 .hsw.has_fuses = true, 2759 }, 2760 }, 2761 { 2762 .name = "DC off", 2763 .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS, 2764 .ops = &gen9_dc_off_power_well_ops, 2765 .id = DISP_PW_ID_NONE, 2766 }, 2767 { 2768 .name = "power well 3", 2769 .domains = ICL_PW_3_POWER_DOMAINS, 2770 .ops = &hsw_power_well_ops, 2771 .id = DISP_PW_ID_NONE, 2772 { 2773 .hsw.regs = &hsw_power_well_regs, 2774 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 2775 .hsw.irq_pipe_mask = BIT(PIPE_B), 2776 .hsw.has_vga = true, 2777 .hsw.has_fuses = true, 2778 }, 2779 }, 2780 { 2781 .name = "DDI A IO", 2782 .domains = ICL_DDI_IO_A_POWER_DOMAINS, 2783 .ops = &hsw_power_well_ops, 2784 .id = DISP_PW_ID_NONE, 2785 { 2786 .hsw.regs = &icl_ddi_power_well_regs, 2787 .hsw.idx = ICL_PW_CTL_IDX_DDI_A, 2788 }, 2789 }, 2790 { 2791 .name = "DDI B IO", 2792 .domains = ICL_DDI_IO_B_POWER_DOMAINS, 2793 .ops = &hsw_power_well_ops, 2794 .id = DISP_PW_ID_NONE, 2795 { 2796 .hsw.regs = &icl_ddi_power_well_regs, 2797 .hsw.idx = ICL_PW_CTL_IDX_DDI_B, 2798 }, 2799 }, 2800 { 2801 .name = "DDI C IO", 2802 .domains = ICL_DDI_IO_C_POWER_DOMAINS, 2803 .ops = &hsw_power_well_ops, 2804 .id = DISP_PW_ID_NONE, 2805 { 2806 .hsw.regs = &icl_ddi_power_well_regs, 2807 .hsw.idx = ICL_PW_CTL_IDX_DDI_C, 2808 }, 2809 }, 2810 { 2811 .name = "DDI D IO", 2812 .domains = ICL_DDI_IO_D_POWER_DOMAINS, 2813 .ops = &hsw_power_well_ops, 2814 .id = DISP_PW_ID_NONE, 2815 { 2816 .hsw.regs = &icl_ddi_power_well_regs, 2817 .hsw.idx = ICL_PW_CTL_IDX_DDI_D, 2818 }, 2819 }, 2820 { 2821 .name = "DDI E IO", 2822 .domains = ICL_DDI_IO_E_POWER_DOMAINS, 2823 .ops = &hsw_power_well_ops, 2824 .id = DISP_PW_ID_NONE, 2825 { 2826 .hsw.regs = &icl_ddi_power_well_regs, 2827 .hsw.idx = ICL_PW_CTL_IDX_DDI_E, 2828 }, 2829 }, 2830 { 2831 .name = "DDI F IO", 2832 .domains = ICL_DDI_IO_F_POWER_DOMAINS, 2833 .ops = &hsw_power_well_ops, 2834 .id = DISP_PW_ID_NONE, 2835 { 2836 .hsw.regs = &icl_ddi_power_well_regs, 2837 .hsw.idx = ICL_PW_CTL_IDX_DDI_F, 2838 }, 2839 }, 2840 { 2841 .name = "AUX A", 2842 .domains = ICL_AUX_A_IO_POWER_DOMAINS, 2843 .ops = &icl_combo_phy_aux_power_well_ops, 2844 .id = DISP_PW_ID_NONE, 2845 { 2846 .hsw.regs = &icl_aux_power_well_regs, 2847 .hsw.idx = ICL_PW_CTL_IDX_AUX_A, 2848 }, 2849 }, 2850 { 2851 .name = "AUX B", 2852 .domains = ICL_AUX_B_IO_POWER_DOMAINS, 2853 .ops = &icl_combo_phy_aux_power_well_ops, 2854 .id = DISP_PW_ID_NONE, 2855 { 2856 .hsw.regs = &icl_aux_power_well_regs, 2857 .hsw.idx = ICL_PW_CTL_IDX_AUX_B, 2858 }, 2859 }, 2860 { 2861 .name = "AUX C", 2862 .domains = ICL_AUX_C_IO_POWER_DOMAINS, 2863 .ops = &hsw_power_well_ops, 2864 .id = DISP_PW_ID_NONE, 2865 { 2866 .hsw.regs = &icl_aux_power_well_regs, 2867 .hsw.idx = ICL_PW_CTL_IDX_AUX_C, 2868 }, 2869 }, 2870 { 2871 .name = "AUX D", 2872 .domains = ICL_AUX_D_IO_POWER_DOMAINS, 2873 .ops = &hsw_power_well_ops, 2874 .id = DISP_PW_ID_NONE, 2875 { 2876 .hsw.regs = &icl_aux_power_well_regs, 2877 .hsw.idx = ICL_PW_CTL_IDX_AUX_D, 2878 }, 2879 }, 2880 { 2881 .name = "AUX E", 2882 .domains = ICL_AUX_E_IO_POWER_DOMAINS, 2883 .ops = &hsw_power_well_ops, 2884 .id = DISP_PW_ID_NONE, 2885 { 2886 .hsw.regs = &icl_aux_power_well_regs, 2887 .hsw.idx = ICL_PW_CTL_IDX_AUX_E, 2888 }, 2889 }, 2890 { 2891 .name = "AUX F", 2892 .domains = ICL_AUX_F_IO_POWER_DOMAINS, 2893 .ops = &hsw_power_well_ops, 2894 .id = DISP_PW_ID_NONE, 2895 { 2896 .hsw.regs = &icl_aux_power_well_regs, 2897 .hsw.idx = ICL_PW_CTL_IDX_AUX_F, 2898 }, 2899 }, 2900 { 2901 .name = "AUX TBT1", 2902 .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS, 2903 .ops = &hsw_power_well_ops, 2904 .id = DISP_PW_ID_NONE, 2905 { 2906 .hsw.regs = &icl_aux_power_well_regs, 2907 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1, 2908 }, 2909 }, 2910 { 2911 .name = "AUX TBT2", 2912 .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS, 2913 .ops = &hsw_power_well_ops, 2914 .id = DISP_PW_ID_NONE, 2915 { 2916 .hsw.regs = &icl_aux_power_well_regs, 2917 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2, 2918 }, 2919 }, 2920 { 2921 .name = "AUX TBT3", 2922 .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS, 2923 .ops = &hsw_power_well_ops, 2924 .id = DISP_PW_ID_NONE, 2925 { 2926 .hsw.regs = &icl_aux_power_well_regs, 2927 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3, 2928 }, 2929 }, 2930 { 2931 .name = "AUX TBT4", 2932 .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS, 2933 .ops = &hsw_power_well_ops, 2934 .id = DISP_PW_ID_NONE, 2935 { 2936 .hsw.regs = &icl_aux_power_well_regs, 2937 .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4, 2938 }, 2939 }, 2940 { 2941 .name = "power well 4", 2942 .domains = ICL_PW_4_POWER_DOMAINS, 2943 .ops = &hsw_power_well_ops, 2944 .id = DISP_PW_ID_NONE, 2945 { 2946 .hsw.regs = &hsw_power_well_regs, 2947 .hsw.idx = ICL_PW_CTL_IDX_PW_4, 2948 .hsw.has_fuses = true, 2949 .hsw.irq_pipe_mask = BIT(PIPE_C), 2950 }, 2951 }, 2952 }; 2953 2954 static int 2955 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2956 int disable_power_well) 2957 { 2958 if (disable_power_well >= 0) 2959 return !!disable_power_well; 2960 2961 return 1; 2962 } 2963 2964 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2965 int enable_dc) 2966 { 2967 uint32_t mask; 2968 int requested_dc; 2969 int max_dc; 2970 2971 if (IS_GEN9_BC(dev_priv) || INTEL_INFO(dev_priv)->gen >= 10) { 2972 max_dc = 2; 2973 mask = 0; 2974 } else if (IS_GEN9_LP(dev_priv)) { 2975 max_dc = 1; 2976 /* 2977 * DC9 has a separate HW flow from the rest of the DC states, 2978 * not depending on the DMC firmware. It's needed by system 2979 * suspend/resume, so allow it unconditionally. 2980 */ 2981 mask = DC_STATE_EN_DC9; 2982 } else { 2983 max_dc = 0; 2984 mask = 0; 2985 } 2986 2987 if (!i915_modparams.disable_power_well) 2988 max_dc = 0; 2989 2990 if (enable_dc >= 0 && enable_dc <= max_dc) { 2991 requested_dc = enable_dc; 2992 } else if (enable_dc == -1) { 2993 requested_dc = max_dc; 2994 } else if (enable_dc > max_dc && enable_dc <= 2) { 2995 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2996 enable_dc, max_dc); 2997 requested_dc = max_dc; 2998 } else { 2999 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 3000 requested_dc = max_dc; 3001 } 3002 3003 if (requested_dc > 1) 3004 mask |= DC_STATE_EN_UPTO_DC6; 3005 if (requested_dc > 0) 3006 mask |= DC_STATE_EN_UPTO_DC5; 3007 3008 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 3009 3010 return mask; 3011 } 3012 3013 static int 3014 __set_power_wells(struct i915_power_domains *power_domains, 3015 const struct i915_power_well_desc *power_well_descs, 3016 int power_well_count) 3017 { 3018 u64 power_well_ids = 0; 3019 int i; 3020 3021 power_domains->power_well_count = power_well_count; 3022 power_domains->power_wells = 3023 kcalloc(power_well_count, 3024 sizeof(*power_domains->power_wells), 3025 GFP_KERNEL); 3026 if (!power_domains->power_wells) 3027 return -ENOMEM; 3028 3029 for (i = 0; i < power_well_count; i++) { 3030 enum i915_power_well_id id = power_well_descs[i].id; 3031 3032 power_domains->power_wells[i].desc = &power_well_descs[i]; 3033 3034 if (id == DISP_PW_ID_NONE) 3035 continue; 3036 3037 WARN_ON(id >= sizeof(power_well_ids) * 8); 3038 WARN_ON(power_well_ids & BIT_ULL(id)); 3039 power_well_ids |= BIT_ULL(id); 3040 } 3041 3042 return 0; 3043 } 3044 3045 #define set_power_wells(power_domains, __power_well_descs) \ 3046 __set_power_wells(power_domains, __power_well_descs, \ 3047 ARRAY_SIZE(__power_well_descs)) 3048 3049 /** 3050 * intel_power_domains_init - initializes the power domain structures 3051 * @dev_priv: i915 device instance 3052 * 3053 * Initializes the power domain structures for @dev_priv depending upon the 3054 * supported platform. 3055 */ 3056 int intel_power_domains_init(struct drm_i915_private *dev_priv) 3057 { 3058 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3059 int err; 3060 3061 i915_modparams.disable_power_well = 3062 sanitize_disable_power_well_option(dev_priv, 3063 i915_modparams.disable_power_well); 3064 dev_priv->csr.allowed_dc_mask = 3065 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); 3066 3067 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); 3068 3069 mutex_init(&power_domains->lock); 3070 3071 /* 3072 * The enabling order will be from lower to higher indexed wells, 3073 * the disabling order is reversed. 3074 */ 3075 if (IS_ICELAKE(dev_priv)) { 3076 err = set_power_wells(power_domains, icl_power_wells); 3077 } else if (IS_HASWELL(dev_priv)) { 3078 err = set_power_wells(power_domains, hsw_power_wells); 3079 } else if (IS_BROADWELL(dev_priv)) { 3080 err = set_power_wells(power_domains, bdw_power_wells); 3081 } else if (IS_GEN9_BC(dev_priv)) { 3082 err = set_power_wells(power_domains, skl_power_wells); 3083 } else if (IS_CANNONLAKE(dev_priv)) { 3084 err = set_power_wells(power_domains, cnl_power_wells); 3085 3086 /* 3087 * DDI and Aux IO are getting enabled for all ports 3088 * regardless the presence or use. So, in order to avoid 3089 * timeouts, lets remove them from the list 3090 * for the SKUs without port F. 3091 */ 3092 if (!IS_CNL_WITH_PORT_F(dev_priv)) 3093 power_domains->power_well_count -= 2; 3094 3095 } else if (IS_BROXTON(dev_priv)) { 3096 err = set_power_wells(power_domains, bxt_power_wells); 3097 } else if (IS_GEMINILAKE(dev_priv)) { 3098 err = set_power_wells(power_domains, glk_power_wells); 3099 } else if (IS_CHERRYVIEW(dev_priv)) { 3100 err = set_power_wells(power_domains, chv_power_wells); 3101 } else if (IS_VALLEYVIEW(dev_priv)) { 3102 err = set_power_wells(power_domains, vlv_power_wells); 3103 } else if (IS_I830(dev_priv)) { 3104 err = set_power_wells(power_domains, i830_power_wells); 3105 } else { 3106 err = set_power_wells(power_domains, i9xx_always_on_power_well); 3107 } 3108 3109 return err; 3110 } 3111 3112 /** 3113 * intel_power_domains_cleanup - clean up power domains resources 3114 * @dev_priv: i915 device instance 3115 * 3116 * Release any resources acquired by intel_power_domains_init() 3117 */ 3118 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv) 3119 { 3120 kfree(dev_priv->power_domains.power_wells); 3121 } 3122 3123 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 3124 { 3125 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3126 struct i915_power_well *power_well; 3127 3128 mutex_lock(&power_domains->lock); 3129 for_each_power_well(dev_priv, power_well) { 3130 power_well->desc->ops->sync_hw(dev_priv, power_well); 3131 power_well->hw_enabled = 3132 power_well->desc->ops->is_enabled(dev_priv, power_well); 3133 } 3134 mutex_unlock(&power_domains->lock); 3135 } 3136 3137 static inline 3138 bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, 3139 i915_reg_t reg, bool enable) 3140 { 3141 u32 val, status; 3142 3143 val = I915_READ(reg); 3144 val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST); 3145 I915_WRITE(reg, val); 3146 POSTING_READ(reg); 3147 udelay(10); 3148 3149 status = I915_READ(reg) & DBUF_POWER_STATE; 3150 if ((enable && !status) || (!enable && status)) { 3151 DRM_ERROR("DBus power %s timeout!\n", 3152 enable ? "enable" : "disable"); 3153 return false; 3154 } 3155 return true; 3156 } 3157 3158 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 3159 { 3160 intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); 3161 } 3162 3163 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 3164 { 3165 intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); 3166 } 3167 3168 static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) 3169 { 3170 if (INTEL_GEN(dev_priv) < 11) 3171 return 1; 3172 return 2; 3173 } 3174 3175 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 3176 u8 req_slices) 3177 { 3178 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; 3179 u32 val; 3180 bool ret; 3181 3182 if (req_slices > intel_dbuf_max_slices(dev_priv)) { 3183 DRM_ERROR("Invalid number of dbuf slices requested\n"); 3184 return; 3185 } 3186 3187 if (req_slices == hw_enabled_slices || req_slices == 0) 3188 return; 3189 3190 val = I915_READ(DBUF_CTL_S2); 3191 if (req_slices > hw_enabled_slices) 3192 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); 3193 else 3194 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); 3195 3196 if (ret) 3197 dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; 3198 } 3199 3200 static void icl_dbuf_enable(struct drm_i915_private *dev_priv) 3201 { 3202 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST); 3203 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST); 3204 POSTING_READ(DBUF_CTL_S2); 3205 3206 udelay(10); 3207 3208 if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || 3209 !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) 3210 DRM_ERROR("DBuf power enable timeout\n"); 3211 else 3212 dev_priv->wm.skl_hw.ddb.enabled_slices = 2; 3213 } 3214 3215 static void icl_dbuf_disable(struct drm_i915_private *dev_priv) 3216 { 3217 I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); 3218 I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); 3219 POSTING_READ(DBUF_CTL_S2); 3220 3221 udelay(10); 3222 3223 if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || 3224 (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) 3225 DRM_ERROR("DBuf power disable timeout!\n"); 3226 else 3227 dev_priv->wm.skl_hw.ddb.enabled_slices = 0; 3228 } 3229 3230 static void icl_mbus_init(struct drm_i915_private *dev_priv) 3231 { 3232 uint32_t val; 3233 3234 val = MBUS_ABOX_BT_CREDIT_POOL1(16) | 3235 MBUS_ABOX_BT_CREDIT_POOL2(16) | 3236 MBUS_ABOX_B_CREDIT(1) | 3237 MBUS_ABOX_BW_CREDIT(1); 3238 3239 I915_WRITE(MBUS_ABOX_CTL, val); 3240 } 3241 3242 static void skl_display_core_init(struct drm_i915_private *dev_priv, 3243 bool resume) 3244 { 3245 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3246 struct i915_power_well *well; 3247 uint32_t val; 3248 3249 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3250 3251 /* enable PCH reset handshake */ 3252 val = I915_READ(HSW_NDE_RSTWRN_OPT); 3253 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 3254 3255 /* enable PG1 and Misc I/O */ 3256 mutex_lock(&power_domains->lock); 3257 3258 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3259 intel_power_well_enable(dev_priv, well); 3260 3261 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 3262 intel_power_well_enable(dev_priv, well); 3263 3264 mutex_unlock(&power_domains->lock); 3265 3266 skl_init_cdclk(dev_priv); 3267 3268 gen9_dbuf_enable(dev_priv); 3269 3270 if (resume && dev_priv->csr.dmc_payload) 3271 intel_csr_load_program(dev_priv); 3272 } 3273 3274 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 3275 { 3276 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3277 struct i915_power_well *well; 3278 3279 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3280 3281 gen9_dbuf_disable(dev_priv); 3282 3283 skl_uninit_cdclk(dev_priv); 3284 3285 /* The spec doesn't call for removing the reset handshake flag */ 3286 /* disable PG1 and Misc I/O */ 3287 3288 mutex_lock(&power_domains->lock); 3289 3290 /* 3291 * BSpec says to keep the MISC IO power well enabled here, only 3292 * remove our request for power well 1. 3293 * Note that even though the driver's request is removed power well 1 3294 * may stay enabled after this due to DMC's own request on it. 3295 */ 3296 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3297 intel_power_well_disable(dev_priv, well); 3298 3299 mutex_unlock(&power_domains->lock); 3300 3301 usleep_range(10, 30); /* 10 us delay per Bspec */ 3302 } 3303 3304 void bxt_display_core_init(struct drm_i915_private *dev_priv, 3305 bool resume) 3306 { 3307 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3308 struct i915_power_well *well; 3309 uint32_t val; 3310 3311 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3312 3313 /* 3314 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 3315 * or else the reset will hang because there is no PCH to respond. 3316 * Move the handshake programming to initialization sequence. 3317 * Previously was left up to BIOS. 3318 */ 3319 val = I915_READ(HSW_NDE_RSTWRN_OPT); 3320 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 3321 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 3322 3323 /* Enable PG1 */ 3324 mutex_lock(&power_domains->lock); 3325 3326 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3327 intel_power_well_enable(dev_priv, well); 3328 3329 mutex_unlock(&power_domains->lock); 3330 3331 bxt_init_cdclk(dev_priv); 3332 3333 gen9_dbuf_enable(dev_priv); 3334 3335 if (resume && dev_priv->csr.dmc_payload) 3336 intel_csr_load_program(dev_priv); 3337 } 3338 3339 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 3340 { 3341 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3342 struct i915_power_well *well; 3343 3344 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3345 3346 gen9_dbuf_disable(dev_priv); 3347 3348 bxt_uninit_cdclk(dev_priv); 3349 3350 /* The spec doesn't call for removing the reset handshake flag */ 3351 3352 /* 3353 * Disable PW1 (PG1). 3354 * Note that even though the driver's request is removed power well 1 3355 * may stay enabled after this due to DMC's own request on it. 3356 */ 3357 mutex_lock(&power_domains->lock); 3358 3359 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3360 intel_power_well_disable(dev_priv, well); 3361 3362 mutex_unlock(&power_domains->lock); 3363 3364 usleep_range(10, 30); /* 10 us delay per Bspec */ 3365 } 3366 3367 enum { 3368 PROCMON_0_85V_DOT_0, 3369 PROCMON_0_95V_DOT_0, 3370 PROCMON_0_95V_DOT_1, 3371 PROCMON_1_05V_DOT_0, 3372 PROCMON_1_05V_DOT_1, 3373 }; 3374 3375 static const struct cnl_procmon { 3376 u32 dw1, dw9, dw10; 3377 } cnl_procmon_values[] = { 3378 [PROCMON_0_85V_DOT_0] = 3379 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 3380 [PROCMON_0_95V_DOT_0] = 3381 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 3382 [PROCMON_0_95V_DOT_1] = 3383 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 3384 [PROCMON_1_05V_DOT_0] = 3385 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 3386 [PROCMON_1_05V_DOT_1] = 3387 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 3388 }; 3389 3390 /* 3391 * CNL has just one set of registers, while ICL has two sets: one for port A and 3392 * the other for port B. The CNL registers are equivalent to the ICL port A 3393 * registers, that's why we call the ICL macros even though the function has CNL 3394 * on its name. 3395 */ 3396 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 3397 enum port port) 3398 { 3399 const struct cnl_procmon *procmon; 3400 u32 val; 3401 3402 val = I915_READ(ICL_PORT_COMP_DW3(port)); 3403 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 3404 default: 3405 MISSING_CASE(val); 3406 /* fall through */ 3407 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 3408 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 3409 break; 3410 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 3411 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 3412 break; 3413 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 3414 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 3415 break; 3416 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 3417 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 3418 break; 3419 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 3420 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 3421 break; 3422 } 3423 3424 val = I915_READ(ICL_PORT_COMP_DW1(port)); 3425 val &= ~((0xff << 16) | 0xff); 3426 val |= procmon->dw1; 3427 I915_WRITE(ICL_PORT_COMP_DW1(port), val); 3428 3429 I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); 3430 I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); 3431 } 3432 3433 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) 3434 { 3435 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3436 struct i915_power_well *well; 3437 u32 val; 3438 3439 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3440 3441 /* 1. Enable PCH Reset Handshake */ 3442 val = I915_READ(HSW_NDE_RSTWRN_OPT); 3443 val |= RESET_PCH_HANDSHAKE_ENABLE; 3444 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 3445 3446 /* 2. Enable Comp */ 3447 val = I915_READ(CHICKEN_MISC_2); 3448 val &= ~CNL_COMP_PWR_DOWN; 3449 I915_WRITE(CHICKEN_MISC_2, val); 3450 3451 /* Dummy PORT_A to get the correct CNL register from the ICL macro */ 3452 cnl_set_procmon_ref_values(dev_priv, PORT_A); 3453 3454 val = I915_READ(CNL_PORT_COMP_DW0); 3455 val |= COMP_INIT; 3456 I915_WRITE(CNL_PORT_COMP_DW0, val); 3457 3458 /* 3. */ 3459 val = I915_READ(CNL_PORT_CL1CM_DW5); 3460 val |= CL_POWER_DOWN_ENABLE; 3461 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 3462 3463 /* 3464 * 4. Enable Power Well 1 (PG1). 3465 * The AUX IO power wells will be enabled on demand. 3466 */ 3467 mutex_lock(&power_domains->lock); 3468 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3469 intel_power_well_enable(dev_priv, well); 3470 mutex_unlock(&power_domains->lock); 3471 3472 /* 5. Enable CD clock */ 3473 cnl_init_cdclk(dev_priv); 3474 3475 /* 6. Enable DBUF */ 3476 gen9_dbuf_enable(dev_priv); 3477 3478 if (resume && dev_priv->csr.dmc_payload) 3479 intel_csr_load_program(dev_priv); 3480 } 3481 3482 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) 3483 { 3484 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3485 struct i915_power_well *well; 3486 u32 val; 3487 3488 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3489 3490 /* 1. Disable all display engine functions -> aready done */ 3491 3492 /* 2. Disable DBUF */ 3493 gen9_dbuf_disable(dev_priv); 3494 3495 /* 3. Disable CD clock */ 3496 cnl_uninit_cdclk(dev_priv); 3497 3498 /* 3499 * 4. Disable Power Well 1 (PG1). 3500 * The AUX IO power wells are toggled on demand, so they are already 3501 * disabled at this point. 3502 */ 3503 mutex_lock(&power_domains->lock); 3504 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3505 intel_power_well_disable(dev_priv, well); 3506 mutex_unlock(&power_domains->lock); 3507 3508 usleep_range(10, 30); /* 10 us delay per Bspec */ 3509 3510 /* 5. Disable Comp */ 3511 val = I915_READ(CHICKEN_MISC_2); 3512 val |= CNL_COMP_PWR_DOWN; 3513 I915_WRITE(CHICKEN_MISC_2, val); 3514 } 3515 3516 static void icl_display_core_init(struct drm_i915_private *dev_priv, 3517 bool resume) 3518 { 3519 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3520 struct i915_power_well *well; 3521 enum port port; 3522 u32 val; 3523 3524 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3525 3526 /* 1. Enable PCH reset handshake. */ 3527 val = I915_READ(HSW_NDE_RSTWRN_OPT); 3528 val |= RESET_PCH_HANDSHAKE_ENABLE; 3529 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 3530 3531 for (port = PORT_A; port <= PORT_B; port++) { 3532 /* 2. Enable DDI combo PHY comp. */ 3533 val = I915_READ(ICL_PHY_MISC(port)); 3534 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 3535 I915_WRITE(ICL_PHY_MISC(port), val); 3536 3537 cnl_set_procmon_ref_values(dev_priv, port); 3538 3539 val = I915_READ(ICL_PORT_COMP_DW0(port)); 3540 val |= COMP_INIT; 3541 I915_WRITE(ICL_PORT_COMP_DW0(port), val); 3542 3543 /* 3. Set power down enable. */ 3544 val = I915_READ(ICL_PORT_CL_DW5(port)); 3545 val |= CL_POWER_DOWN_ENABLE; 3546 I915_WRITE(ICL_PORT_CL_DW5(port), val); 3547 } 3548 3549 /* 3550 * 4. Enable Power Well 1 (PG1). 3551 * The AUX IO power wells will be enabled on demand. 3552 */ 3553 mutex_lock(&power_domains->lock); 3554 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3555 intel_power_well_enable(dev_priv, well); 3556 mutex_unlock(&power_domains->lock); 3557 3558 /* 5. Enable CDCLK. */ 3559 icl_init_cdclk(dev_priv); 3560 3561 /* 6. Enable DBUF. */ 3562 icl_dbuf_enable(dev_priv); 3563 3564 /* 7. Setup MBUS. */ 3565 icl_mbus_init(dev_priv); 3566 } 3567 3568 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 3569 { 3570 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3571 struct i915_power_well *well; 3572 enum port port; 3573 u32 val; 3574 3575 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 3576 3577 /* 1. Disable all display engine functions -> aready done */ 3578 3579 /* 2. Disable DBUF */ 3580 icl_dbuf_disable(dev_priv); 3581 3582 /* 3. Disable CD clock */ 3583 icl_uninit_cdclk(dev_priv); 3584 3585 /* 3586 * 4. Disable Power Well 1 (PG1). 3587 * The AUX IO power wells are toggled on demand, so they are already 3588 * disabled at this point. 3589 */ 3590 mutex_lock(&power_domains->lock); 3591 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 3592 intel_power_well_disable(dev_priv, well); 3593 mutex_unlock(&power_domains->lock); 3594 3595 /* 5. Disable Comp */ 3596 for (port = PORT_A; port <= PORT_B; port++) { 3597 val = I915_READ(ICL_PHY_MISC(port)); 3598 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 3599 I915_WRITE(ICL_PHY_MISC(port), val); 3600 } 3601 } 3602 3603 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 3604 { 3605 struct i915_power_well *cmn_bc = 3606 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 3607 struct i915_power_well *cmn_d = 3608 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 3609 3610 /* 3611 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 3612 * workaround never ever read DISPLAY_PHY_CONTROL, and 3613 * instead maintain a shadow copy ourselves. Use the actual 3614 * power well state and lane status to reconstruct the 3615 * expected initial value. 3616 */ 3617 dev_priv->chv_phy_control = 3618 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 3619 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 3620 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 3621 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 3622 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 3623 3624 /* 3625 * If all lanes are disabled we leave the override disabled 3626 * with all power down bits cleared to match the state we 3627 * would use after disabling the port. Otherwise enable the 3628 * override and set the lane powerdown bits accding to the 3629 * current lane status. 3630 */ 3631 if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) { 3632 uint32_t status = I915_READ(DPLL(PIPE_A)); 3633 unsigned int mask; 3634 3635 mask = status & DPLL_PORTB_READY_MASK; 3636 if (mask == 0xf) 3637 mask = 0x0; 3638 else 3639 dev_priv->chv_phy_control |= 3640 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 3641 3642 dev_priv->chv_phy_control |= 3643 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 3644 3645 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 3646 if (mask == 0xf) 3647 mask = 0x0; 3648 else 3649 dev_priv->chv_phy_control |= 3650 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 3651 3652 dev_priv->chv_phy_control |= 3653 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 3654 3655 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 3656 3657 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 3658 } else { 3659 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 3660 } 3661 3662 if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) { 3663 uint32_t status = I915_READ(DPIO_PHY_STATUS); 3664 unsigned int mask; 3665 3666 mask = status & DPLL_PORTD_READY_MASK; 3667 3668 if (mask == 0xf) 3669 mask = 0x0; 3670 else 3671 dev_priv->chv_phy_control |= 3672 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 3673 3674 dev_priv->chv_phy_control |= 3675 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 3676 3677 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 3678 3679 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 3680 } else { 3681 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 3682 } 3683 3684 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 3685 3686 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 3687 dev_priv->chv_phy_control); 3688 } 3689 3690 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 3691 { 3692 struct i915_power_well *cmn = 3693 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 3694 struct i915_power_well *disp2d = 3695 lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D); 3696 3697 /* If the display might be already active skip this */ 3698 if (cmn->desc->ops->is_enabled(dev_priv, cmn) && 3699 disp2d->desc->ops->is_enabled(dev_priv, disp2d) && 3700 I915_READ(DPIO_CTL) & DPIO_CMNRST) 3701 return; 3702 3703 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 3704 3705 /* cmnlane needs DPLL registers */ 3706 disp2d->desc->ops->enable(dev_priv, disp2d); 3707 3708 /* 3709 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 3710 * Need to assert and de-assert PHY SB reset by gating the 3711 * common lane power, then un-gating it. 3712 * Simply ungating isn't enough to reset the PHY enough to get 3713 * ports and lanes running. 3714 */ 3715 cmn->desc->ops->disable(dev_priv, cmn); 3716 } 3717 3718 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); 3719 3720 /** 3721 * intel_power_domains_init_hw - initialize hardware power domain state 3722 * @dev_priv: i915 device instance 3723 * @resume: Called from resume code paths or not 3724 * 3725 * This function initializes the hardware power domain state and enables all 3726 * power wells belonging to the INIT power domain. Power wells in other 3727 * domains (and not in the INIT domain) are referenced or disabled by 3728 * intel_modeset_readout_hw_state(). After that the reference count of each 3729 * power well must match its HW enabled state, see 3730 * intel_power_domains_verify_state(). 3731 * 3732 * It will return with power domains disabled (to be enabled later by 3733 * intel_power_domains_enable()) and must be paired with 3734 * intel_power_domains_fini_hw(). 3735 */ 3736 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 3737 { 3738 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3739 3740 power_domains->initializing = true; 3741 3742 if (IS_ICELAKE(dev_priv)) { 3743 icl_display_core_init(dev_priv, resume); 3744 } else if (IS_CANNONLAKE(dev_priv)) { 3745 cnl_display_core_init(dev_priv, resume); 3746 } else if (IS_GEN9_BC(dev_priv)) { 3747 skl_display_core_init(dev_priv, resume); 3748 } else if (IS_GEN9_LP(dev_priv)) { 3749 bxt_display_core_init(dev_priv, resume); 3750 } else if (IS_CHERRYVIEW(dev_priv)) { 3751 mutex_lock(&power_domains->lock); 3752 chv_phy_control_init(dev_priv); 3753 mutex_unlock(&power_domains->lock); 3754 } else if (IS_VALLEYVIEW(dev_priv)) { 3755 mutex_lock(&power_domains->lock); 3756 vlv_cmnlane_wa(dev_priv); 3757 mutex_unlock(&power_domains->lock); 3758 } 3759 3760 /* 3761 * Keep all power wells enabled for any dependent HW access during 3762 * initialization and to make sure we keep BIOS enabled display HW 3763 * resources powered until display HW readout is complete. We drop 3764 * this reference in intel_power_domains_enable(). 3765 */ 3766 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3767 /* Disable power support if the user asked so. */ 3768 if (!i915_modparams.disable_power_well) 3769 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3770 intel_power_domains_sync_hw(dev_priv); 3771 3772 power_domains->initializing = false; 3773 } 3774 3775 /** 3776 * intel_power_domains_fini_hw - deinitialize hw power domain state 3777 * @dev_priv: i915 device instance 3778 * 3779 * De-initializes the display power domain HW state. It also ensures that the 3780 * device stays powered up so that the driver can be reloaded. 3781 * 3782 * It must be called with power domains already disabled (after a call to 3783 * intel_power_domains_disable()) and must be paired with 3784 * intel_power_domains_init_hw(). 3785 */ 3786 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv) 3787 { 3788 /* Keep the power well enabled, but cancel its rpm wakeref. */ 3789 intel_runtime_pm_put(dev_priv); 3790 3791 /* Remove the refcount we took to keep power well support disabled. */ 3792 if (!i915_modparams.disable_power_well) 3793 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3794 3795 intel_power_domains_verify_state(dev_priv); 3796 } 3797 3798 /** 3799 * intel_power_domains_enable - enable toggling of display power wells 3800 * @dev_priv: i915 device instance 3801 * 3802 * Enable the ondemand enabling/disabling of the display power wells. Note that 3803 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled 3804 * only at specific points of the display modeset sequence, thus they are not 3805 * affected by the intel_power_domains_enable()/disable() calls. The purpose 3806 * of these function is to keep the rest of power wells enabled until the end 3807 * of display HW readout (which will acquire the power references reflecting 3808 * the current HW state). 3809 */ 3810 void intel_power_domains_enable(struct drm_i915_private *dev_priv) 3811 { 3812 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3813 3814 intel_power_domains_verify_state(dev_priv); 3815 } 3816 3817 /** 3818 * intel_power_domains_disable - disable toggling of display power wells 3819 * @dev_priv: i915 device instance 3820 * 3821 * Disable the ondemand enabling/disabling of the display power wells. See 3822 * intel_power_domains_enable() for which power wells this call controls. 3823 */ 3824 void intel_power_domains_disable(struct drm_i915_private *dev_priv) 3825 { 3826 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3827 3828 intel_power_domains_verify_state(dev_priv); 3829 } 3830 3831 /** 3832 * intel_power_domains_suspend - suspend power domain state 3833 * @dev_priv: i915 device instance 3834 * @suspend_mode: specifies the target suspend state (idle, mem, hibernation) 3835 * 3836 * This function prepares the hardware power domain state before entering 3837 * system suspend. 3838 * 3839 * It must be called with power domains already disabled (after a call to 3840 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 3841 */ 3842 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, 3843 enum i915_drm_suspend_mode suspend_mode) 3844 { 3845 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3846 3847 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3848 3849 /* 3850 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 3851 * support don't manually deinit the power domains. This also means the 3852 * CSR/DMC firmware will stay active, it will power down any HW 3853 * resources as required and also enable deeper system power states 3854 * that would be blocked if the firmware was inactive. 3855 */ 3856 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC9) && 3857 suspend_mode == I915_DRM_SUSPEND_IDLE && 3858 dev_priv->csr.dmc_payload != NULL) { 3859 intel_power_domains_verify_state(dev_priv); 3860 return; 3861 } 3862 3863 /* 3864 * Even if power well support was disabled we still want to disable 3865 * power wells if power domains must be deinitialized for suspend. 3866 */ 3867 if (!i915_modparams.disable_power_well) { 3868 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3869 intel_power_domains_verify_state(dev_priv); 3870 } 3871 3872 if (IS_ICELAKE(dev_priv)) 3873 icl_display_core_uninit(dev_priv); 3874 else if (IS_CANNONLAKE(dev_priv)) 3875 cnl_display_core_uninit(dev_priv); 3876 else if (IS_GEN9_BC(dev_priv)) 3877 skl_display_core_uninit(dev_priv); 3878 else if (IS_GEN9_LP(dev_priv)) 3879 bxt_display_core_uninit(dev_priv); 3880 3881 power_domains->display_core_suspended = true; 3882 } 3883 3884 /** 3885 * intel_power_domains_resume - resume power domain state 3886 * @dev_priv: i915 device instance 3887 * 3888 * This function resume the hardware power domain state during system resume. 3889 * 3890 * It will return with power domain support disabled (to be enabled later by 3891 * intel_power_domains_enable()) and must be paired with 3892 * intel_power_domains_suspend(). 3893 */ 3894 void intel_power_domains_resume(struct drm_i915_private *dev_priv) 3895 { 3896 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3897 3898 if (power_domains->display_core_suspended) { 3899 intel_power_domains_init_hw(dev_priv, true); 3900 power_domains->display_core_suspended = false; 3901 } else { 3902 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3903 } 3904 3905 intel_power_domains_verify_state(dev_priv); 3906 } 3907 3908 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 3909 3910 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) 3911 { 3912 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3913 struct i915_power_well *power_well; 3914 3915 for_each_power_well(dev_priv, power_well) { 3916 enum intel_display_power_domain domain; 3917 3918 DRM_DEBUG_DRIVER("%-25s %d\n", 3919 power_well->desc->name, power_well->count); 3920 3921 for_each_power_domain(domain, power_well->desc->domains) 3922 DRM_DEBUG_DRIVER(" %-23s %d\n", 3923 intel_display_power_domain_str(domain), 3924 power_domains->domain_use_count[domain]); 3925 } 3926 } 3927 3928 /** 3929 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 3930 * @dev_priv: i915 device instance 3931 * 3932 * Verify if the reference count of each power well matches its HW enabled 3933 * state and the total refcount of the domains it belongs to. This must be 3934 * called after modeset HW state sanitization, which is responsible for 3935 * acquiring reference counts for any power wells in use and disabling the 3936 * ones left on by BIOS but not required by any active output. 3937 */ 3938 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) 3939 { 3940 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3941 struct i915_power_well *power_well; 3942 bool dump_domain_info; 3943 3944 mutex_lock(&power_domains->lock); 3945 3946 dump_domain_info = false; 3947 for_each_power_well(dev_priv, power_well) { 3948 enum intel_display_power_domain domain; 3949 int domains_count; 3950 bool enabled; 3951 3952 /* 3953 * Power wells not belonging to any domain (like the MISC_IO 3954 * and PW1 power wells) are under FW control, so ignore them, 3955 * since their state can change asynchronously. 3956 */ 3957 if (!power_well->desc->domains) 3958 continue; 3959 3960 enabled = power_well->desc->ops->is_enabled(dev_priv, 3961 power_well); 3962 if ((power_well->count || power_well->desc->always_on) != 3963 enabled) 3964 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", 3965 power_well->desc->name, 3966 power_well->count, enabled); 3967 3968 domains_count = 0; 3969 for_each_power_domain(domain, power_well->desc->domains) 3970 domains_count += power_domains->domain_use_count[domain]; 3971 3972 if (power_well->count != domains_count) { 3973 DRM_ERROR("power well %s refcount/domain refcount mismatch " 3974 "(refcount %d/domains refcount %d)\n", 3975 power_well->desc->name, power_well->count, 3976 domains_count); 3977 dump_domain_info = true; 3978 } 3979 } 3980 3981 if (dump_domain_info) { 3982 static bool dumped; 3983 3984 if (!dumped) { 3985 intel_power_domains_dump_info(dev_priv); 3986 dumped = true; 3987 } 3988 } 3989 3990 mutex_unlock(&power_domains->lock); 3991 } 3992 3993 #else 3994 3995 static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) 3996 { 3997 } 3998 3999 #endif 4000 4001 /** 4002 * intel_runtime_pm_get - grab a runtime pm reference 4003 * @dev_priv: i915 device instance 4004 * 4005 * This function grabs a device-level runtime pm reference (mostly used for GEM 4006 * code to ensure the GTT or GT is on) and ensures that it is powered up. 4007 * 4008 * Any runtime pm reference obtained by this function must have a symmetric 4009 * call to intel_runtime_pm_put() to release the reference again. 4010 */ 4011 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 4012 { 4013 struct pci_dev *pdev = dev_priv->drm.pdev; 4014 struct device *kdev = &pdev->dev; 4015 int ret; 4016 4017 ret = pm_runtime_get_sync(kdev); 4018 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 4019 4020 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 4021 assert_rpm_wakelock_held(dev_priv); 4022 } 4023 4024 /** 4025 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 4026 * @dev_priv: i915 device instance 4027 * 4028 * This function grabs a device-level runtime pm reference if the device is 4029 * already in use and ensures that it is powered up. It is illegal to try 4030 * and access the HW should intel_runtime_pm_get_if_in_use() report failure. 4031 * 4032 * Any runtime pm reference obtained by this function must have a symmetric 4033 * call to intel_runtime_pm_put() to release the reference again. 4034 * 4035 * Returns: True if the wakeref was acquired, or False otherwise. 4036 */ 4037 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 4038 { 4039 if (IS_ENABLED(CONFIG_PM)) { 4040 struct pci_dev *pdev = dev_priv->drm.pdev; 4041 struct device *kdev = &pdev->dev; 4042 4043 /* 4044 * In cases runtime PM is disabled by the RPM core and we get 4045 * an -EINVAL return value we are not supposed to call this 4046 * function, since the power state is undefined. This applies 4047 * atm to the late/early system suspend/resume handlers. 4048 */ 4049 if (pm_runtime_get_if_in_use(kdev) <= 0) 4050 return false; 4051 } 4052 4053 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 4054 assert_rpm_wakelock_held(dev_priv); 4055 4056 return true; 4057 } 4058 4059 /** 4060 * intel_runtime_pm_get_noresume - grab a runtime pm reference 4061 * @dev_priv: i915 device instance 4062 * 4063 * This function grabs a device-level runtime pm reference (mostly used for GEM 4064 * code to ensure the GTT or GT is on). 4065 * 4066 * It will _not_ power up the device but instead only check that it's powered 4067 * on. Therefore it is only valid to call this functions from contexts where 4068 * the device is known to be powered up and where trying to power it up would 4069 * result in hilarity and deadlocks. That pretty much means only the system 4070 * suspend/resume code where this is used to grab runtime pm references for 4071 * delayed setup down in work items. 4072 * 4073 * Any runtime pm reference obtained by this function must have a symmetric 4074 * call to intel_runtime_pm_put() to release the reference again. 4075 */ 4076 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 4077 { 4078 struct pci_dev *pdev = dev_priv->drm.pdev; 4079 struct device *kdev = &pdev->dev; 4080 4081 assert_rpm_wakelock_held(dev_priv); 4082 pm_runtime_get_noresume(kdev); 4083 4084 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 4085 } 4086 4087 /** 4088 * intel_runtime_pm_put - release a runtime pm reference 4089 * @dev_priv: i915 device instance 4090 * 4091 * This function drops the device-level runtime pm reference obtained by 4092 * intel_runtime_pm_get() and might power down the corresponding 4093 * hardware block right away if this is the last reference. 4094 */ 4095 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 4096 { 4097 struct pci_dev *pdev = dev_priv->drm.pdev; 4098 struct device *kdev = &pdev->dev; 4099 4100 assert_rpm_wakelock_held(dev_priv); 4101 atomic_dec(&dev_priv->runtime_pm.wakeref_count); 4102 4103 pm_runtime_mark_last_busy(kdev); 4104 pm_runtime_put_autosuspend(kdev); 4105 } 4106 4107 /** 4108 * intel_runtime_pm_enable - enable runtime pm 4109 * @dev_priv: i915 device instance 4110 * 4111 * This function enables runtime pm at the end of the driver load sequence. 4112 * 4113 * Note that this function does currently not enable runtime pm for the 4114 * subordinate display power domains. That is done by 4115 * intel_power_domains_enable(). 4116 */ 4117 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 4118 { 4119 struct pci_dev *pdev = dev_priv->drm.pdev; 4120 struct device *kdev = &pdev->dev; 4121 4122 /* 4123 * Disable the system suspend direct complete optimization, which can 4124 * leave the device suspended skipping the driver's suspend handlers 4125 * if the device was already runtime suspended. This is needed due to 4126 * the difference in our runtime and system suspend sequence and 4127 * becaue the HDA driver may require us to enable the audio power 4128 * domain during system suspend. 4129 */ 4130 dev_pm_set_driver_flags(kdev, DPM_FLAG_NEVER_SKIP); 4131 4132 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */ 4133 pm_runtime_mark_last_busy(kdev); 4134 4135 /* 4136 * Take a permanent reference to disable the RPM functionality and drop 4137 * it only when unloading the driver. Use the low level get/put helpers, 4138 * so the driver's own RPM reference tracking asserts also work on 4139 * platforms without RPM support. 4140 */ 4141 if (!HAS_RUNTIME_PM(dev_priv)) { 4142 int ret; 4143 4144 pm_runtime_dont_use_autosuspend(kdev); 4145 ret = pm_runtime_get_sync(kdev); 4146 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 4147 } else { 4148 pm_runtime_use_autosuspend(kdev); 4149 } 4150 4151 /* 4152 * The core calls the driver load handler with an RPM reference held. 4153 * We drop that here and will reacquire it during unloading in 4154 * intel_power_domains_fini(). 4155 */ 4156 pm_runtime_put_autosuspend(kdev); 4157 } 4158 4159 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) 4160 { 4161 struct pci_dev *pdev = dev_priv->drm.pdev; 4162 struct device *kdev = &pdev->dev; 4163 4164 /* Transfer rpm ownership back to core */ 4165 WARN(pm_runtime_get_sync(&dev_priv->drm.pdev->dev) < 0, 4166 "Failed to pass rpm ownership back to core\n"); 4167 4168 pm_runtime_dont_use_autosuspend(kdev); 4169 4170 if (!HAS_RUNTIME_PM(dev_priv)) 4171 pm_runtime_put(kdev); 4172 } 4173