1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 53 for (i = 0; \ 54 i < (power_domains)->power_well_count && \ 55 ((power_well) = &(power_domains)->power_wells[i]); \ 56 i++) \ 57 for_each_if ((power_well)->domains & (domain_mask)) 58 59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 60 for (i = (power_domains)->power_well_count - 1; \ 61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 62 i--) \ 63 for_each_if ((power_well)->domains & (domain_mask)) 64 65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 66 int power_well_id); 67 68 const char * 69 intel_display_power_domain_str(enum intel_display_power_domain domain) 70 { 71 switch (domain) { 72 case POWER_DOMAIN_PIPE_A: 73 return "PIPE_A"; 74 case POWER_DOMAIN_PIPE_B: 75 return "PIPE_B"; 76 case POWER_DOMAIN_PIPE_C: 77 return "PIPE_C"; 78 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 79 return "PIPE_A_PANEL_FITTER"; 80 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 81 return "PIPE_B_PANEL_FITTER"; 82 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 83 return "PIPE_C_PANEL_FITTER"; 84 case POWER_DOMAIN_TRANSCODER_A: 85 return "TRANSCODER_A"; 86 case POWER_DOMAIN_TRANSCODER_B: 87 return "TRANSCODER_B"; 88 case POWER_DOMAIN_TRANSCODER_C: 89 return "TRANSCODER_C"; 90 case POWER_DOMAIN_TRANSCODER_EDP: 91 return "TRANSCODER_EDP"; 92 case POWER_DOMAIN_PORT_DDI_A_LANES: 93 return "PORT_DDI_A_LANES"; 94 case POWER_DOMAIN_PORT_DDI_B_LANES: 95 return "PORT_DDI_B_LANES"; 96 case POWER_DOMAIN_PORT_DDI_C_LANES: 97 return "PORT_DDI_C_LANES"; 98 case POWER_DOMAIN_PORT_DDI_D_LANES: 99 return "PORT_DDI_D_LANES"; 100 case POWER_DOMAIN_PORT_DDI_E_LANES: 101 return "PORT_DDI_E_LANES"; 102 case POWER_DOMAIN_PORT_DSI: 103 return "PORT_DSI"; 104 case POWER_DOMAIN_PORT_CRT: 105 return "PORT_CRT"; 106 case POWER_DOMAIN_PORT_OTHER: 107 return "PORT_OTHER"; 108 case POWER_DOMAIN_VGA: 109 return "VGA"; 110 case POWER_DOMAIN_AUDIO: 111 return "AUDIO"; 112 case POWER_DOMAIN_PLLS: 113 return "PLLS"; 114 case POWER_DOMAIN_AUX_A: 115 return "AUX_A"; 116 case POWER_DOMAIN_AUX_B: 117 return "AUX_B"; 118 case POWER_DOMAIN_AUX_C: 119 return "AUX_C"; 120 case POWER_DOMAIN_AUX_D: 121 return "AUX_D"; 122 case POWER_DOMAIN_GMBUS: 123 return "GMBUS"; 124 case POWER_DOMAIN_INIT: 125 return "INIT"; 126 case POWER_DOMAIN_MODESET: 127 return "MODESET"; 128 default: 129 MISSING_CASE(domain); 130 return "?"; 131 } 132 } 133 134 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 135 struct i915_power_well *power_well) 136 { 137 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 138 power_well->ops->enable(dev_priv, power_well); 139 power_well->hw_enabled = true; 140 } 141 142 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 143 struct i915_power_well *power_well) 144 { 145 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 146 power_well->hw_enabled = false; 147 power_well->ops->disable(dev_priv, power_well); 148 } 149 150 /* 151 * We should only use the power well if we explicitly asked the hardware to 152 * enable it, so check if it's enabled and also check if we've requested it to 153 * be enabled. 154 */ 155 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 156 struct i915_power_well *power_well) 157 { 158 return I915_READ(HSW_PWR_WELL_DRIVER) == 159 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 160 } 161 162 /** 163 * __intel_display_power_is_enabled - unlocked check for a power domain 164 * @dev_priv: i915 device instance 165 * @domain: power domain to check 166 * 167 * This is the unlocked version of intel_display_power_is_enabled() and should 168 * only be used from error capture and recovery code where deadlocks are 169 * possible. 170 * 171 * Returns: 172 * True when the power domain is enabled, false otherwise. 173 */ 174 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 175 enum intel_display_power_domain domain) 176 { 177 struct i915_power_domains *power_domains; 178 struct i915_power_well *power_well; 179 bool is_enabled; 180 int i; 181 182 if (dev_priv->pm.suspended) 183 return false; 184 185 power_domains = &dev_priv->power_domains; 186 187 is_enabled = true; 188 189 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 190 if (power_well->always_on) 191 continue; 192 193 if (!power_well->hw_enabled) { 194 is_enabled = false; 195 break; 196 } 197 } 198 199 return is_enabled; 200 } 201 202 /** 203 * intel_display_power_is_enabled - check for a power domain 204 * @dev_priv: i915 device instance 205 * @domain: power domain to check 206 * 207 * This function can be used to check the hw power domain state. It is mostly 208 * used in hardware state readout functions. Everywhere else code should rely 209 * upon explicit power domain reference counting to ensure that the hardware 210 * block is powered up before accessing it. 211 * 212 * Callers must hold the relevant modesetting locks to ensure that concurrent 213 * threads can't disable the power well while the caller tries to read a few 214 * registers. 215 * 216 * Returns: 217 * True when the power domain is enabled, false otherwise. 218 */ 219 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 220 enum intel_display_power_domain domain) 221 { 222 struct i915_power_domains *power_domains; 223 bool ret; 224 225 power_domains = &dev_priv->power_domains; 226 227 mutex_lock(&power_domains->lock); 228 ret = __intel_display_power_is_enabled(dev_priv, domain); 229 mutex_unlock(&power_domains->lock); 230 231 return ret; 232 } 233 234 /** 235 * intel_display_set_init_power - set the initial power domain state 236 * @dev_priv: i915 device instance 237 * @enable: whether to enable or disable the initial power domain state 238 * 239 * For simplicity our driver load/unload and system suspend/resume code assumes 240 * that all power domains are always enabled. This functions controls the state 241 * of this little hack. While the initial power domain state is enabled runtime 242 * pm is effectively disabled. 243 */ 244 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 245 bool enable) 246 { 247 if (dev_priv->power_domains.init_power_on == enable) 248 return; 249 250 if (enable) 251 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 252 else 253 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 254 255 dev_priv->power_domains.init_power_on = enable; 256 } 257 258 /* 259 * Starting with Haswell, we have a "Power Down Well" that can be turned off 260 * when not needed anymore. We have 4 registers that can request the power well 261 * to be enabled, and it will only be disabled if none of the registers is 262 * requesting it to be enabled. 263 */ 264 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 265 { 266 struct drm_device *dev = dev_priv->dev; 267 268 /* 269 * After we re-enable the power well, if we touch VGA register 0x3d5 270 * we'll get unclaimed register interrupts. This stops after we write 271 * anything to the VGA MSR register. The vgacon module uses this 272 * register all the time, so if we unbind our driver and, as a 273 * consequence, bind vgacon, we'll get stuck in an infinite loop at 274 * console_unlock(). So make here we touch the VGA MSR register, making 275 * sure vgacon can keep working normally without triggering interrupts 276 * and error messages. 277 */ 278 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 279 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 280 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 281 282 if (IS_BROADWELL(dev)) 283 gen8_irq_power_well_post_enable(dev_priv, 284 1 << PIPE_C | 1 << PIPE_B); 285 } 286 287 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 288 struct i915_power_well *power_well) 289 { 290 struct drm_device *dev = dev_priv->dev; 291 292 /* 293 * After we re-enable the power well, if we touch VGA register 0x3d5 294 * we'll get unclaimed register interrupts. This stops after we write 295 * anything to the VGA MSR register. The vgacon module uses this 296 * register all the time, so if we unbind our driver and, as a 297 * consequence, bind vgacon, we'll get stuck in an infinite loop at 298 * console_unlock(). So make here we touch the VGA MSR register, making 299 * sure vgacon can keep working normally without triggering interrupts 300 * and error messages. 301 */ 302 if (power_well->data == SKL_DISP_PW_2) { 303 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 304 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 305 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 306 307 gen8_irq_power_well_post_enable(dev_priv, 308 1 << PIPE_C | 1 << PIPE_B); 309 } 310 } 311 312 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 313 struct i915_power_well *power_well, bool enable) 314 { 315 bool is_enabled, enable_requested; 316 uint32_t tmp; 317 318 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 319 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 320 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 321 322 if (enable) { 323 if (!enable_requested) 324 I915_WRITE(HSW_PWR_WELL_DRIVER, 325 HSW_PWR_WELL_ENABLE_REQUEST); 326 327 if (!is_enabled) { 328 DRM_DEBUG_KMS("Enabling power well\n"); 329 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 330 HSW_PWR_WELL_STATE_ENABLED), 20)) 331 DRM_ERROR("Timeout enabling power well\n"); 332 hsw_power_well_post_enable(dev_priv); 333 } 334 335 } else { 336 if (enable_requested) { 337 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 338 POSTING_READ(HSW_PWR_WELL_DRIVER); 339 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 340 } 341 } 342 } 343 344 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 345 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 346 BIT(POWER_DOMAIN_PIPE_B) | \ 347 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 348 BIT(POWER_DOMAIN_PIPE_C) | \ 349 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 350 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 351 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 352 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 353 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 354 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 355 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 356 BIT(POWER_DOMAIN_AUX_B) | \ 357 BIT(POWER_DOMAIN_AUX_C) | \ 358 BIT(POWER_DOMAIN_AUX_D) | \ 359 BIT(POWER_DOMAIN_AUDIO) | \ 360 BIT(POWER_DOMAIN_VGA) | \ 361 BIT(POWER_DOMAIN_INIT)) 362 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 363 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 364 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 365 BIT(POWER_DOMAIN_INIT)) 366 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 367 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 368 BIT(POWER_DOMAIN_INIT)) 369 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 370 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 371 BIT(POWER_DOMAIN_INIT)) 372 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 373 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 374 BIT(POWER_DOMAIN_INIT)) 375 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 376 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 377 BIT(POWER_DOMAIN_MODESET) | \ 378 BIT(POWER_DOMAIN_AUX_A) | \ 379 BIT(POWER_DOMAIN_INIT)) 380 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 381 (POWER_DOMAIN_MASK & ~( \ 382 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 383 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \ 384 BIT(POWER_DOMAIN_INIT)) 385 386 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 387 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 388 BIT(POWER_DOMAIN_PIPE_B) | \ 389 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 390 BIT(POWER_DOMAIN_PIPE_C) | \ 391 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 392 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 393 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 394 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 395 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 396 BIT(POWER_DOMAIN_AUX_B) | \ 397 BIT(POWER_DOMAIN_AUX_C) | \ 398 BIT(POWER_DOMAIN_AUDIO) | \ 399 BIT(POWER_DOMAIN_VGA) | \ 400 BIT(POWER_DOMAIN_GMBUS) | \ 401 BIT(POWER_DOMAIN_INIT)) 402 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 403 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 404 BIT(POWER_DOMAIN_PIPE_A) | \ 405 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 406 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 407 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 408 BIT(POWER_DOMAIN_AUX_A) | \ 409 BIT(POWER_DOMAIN_PLLS) | \ 410 BIT(POWER_DOMAIN_INIT)) 411 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 412 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 413 BIT(POWER_DOMAIN_MODESET) | \ 414 BIT(POWER_DOMAIN_AUX_A) | \ 415 BIT(POWER_DOMAIN_INIT)) 416 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 417 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 418 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ 419 BIT(POWER_DOMAIN_INIT)) 420 421 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 422 { 423 struct drm_device *dev = dev_priv->dev; 424 425 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); 426 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 427 "DC9 already programmed to be enabled.\n"); 428 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 429 "DC5 still not disabled to enable DC9.\n"); 430 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 431 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 432 433 /* 434 * TODO: check for the following to verify the conditions to enter DC9 435 * state are satisfied: 436 * 1] Check relevant display engine registers to verify if mode set 437 * disable sequence was followed. 438 * 2] Check if display uninitialize sequence is initialized. 439 */ 440 } 441 442 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 443 { 444 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 445 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 446 "DC9 already programmed to be disabled.\n"); 447 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 448 "DC5 still not disabled.\n"); 449 450 /* 451 * TODO: check for the following to verify DC9 state was indeed 452 * entered before programming to disable it: 453 * 1] Check relevant display engine registers to verify if mode 454 * set disable sequence was followed. 455 * 2] Check if display uninitialize sequence is initialized. 456 */ 457 } 458 459 static void gen9_set_dc_state_debugmask_memory_up( 460 struct drm_i915_private *dev_priv) 461 { 462 uint32_t val; 463 464 /* The below bit doesn't need to be cleared ever afterwards */ 465 val = I915_READ(DC_STATE_DEBUG); 466 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { 467 val |= DC_STATE_DEBUG_MASK_MEMORY_UP; 468 I915_WRITE(DC_STATE_DEBUG, val); 469 POSTING_READ(DC_STATE_DEBUG); 470 } 471 } 472 473 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 474 { 475 uint32_t val; 476 uint32_t mask; 477 478 mask = DC_STATE_EN_UPTO_DC5; 479 if (IS_BROXTON(dev_priv)) 480 mask |= DC_STATE_EN_DC9; 481 else 482 mask |= DC_STATE_EN_UPTO_DC6; 483 484 WARN_ON_ONCE(state & ~mask); 485 486 if (i915.enable_dc == 0) 487 state = DC_STATE_DISABLE; 488 else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5) 489 state = DC_STATE_EN_UPTO_DC5; 490 491 if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) 492 gen9_set_dc_state_debugmask_memory_up(dev_priv); 493 494 val = I915_READ(DC_STATE_EN); 495 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 496 val & mask, state); 497 val &= ~mask; 498 val |= state; 499 I915_WRITE(DC_STATE_EN, val); 500 POSTING_READ(DC_STATE_EN); 501 } 502 503 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 504 { 505 assert_can_enable_dc9(dev_priv); 506 507 DRM_DEBUG_KMS("Enabling DC9\n"); 508 509 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 510 } 511 512 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 513 { 514 assert_can_disable_dc9(dev_priv); 515 516 DRM_DEBUG_KMS("Disabling DC9\n"); 517 518 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 519 } 520 521 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 522 { 523 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 524 "CSR program storage start is NULL\n"); 525 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 526 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 527 } 528 529 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 530 { 531 struct drm_device *dev = dev_priv->dev; 532 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 533 SKL_DISP_PW_2); 534 535 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); 536 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 537 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 538 539 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 540 "DC5 already programmed to be enabled.\n"); 541 assert_rpm_wakelock_held(dev_priv); 542 543 assert_csr_loaded(dev_priv); 544 } 545 546 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) 547 { 548 /* 549 * During initialization, the firmware may not be loaded yet. 550 * We still want to make sure that the DC enabling flag is cleared. 551 */ 552 if (dev_priv->power_domains.initializing) 553 return; 554 555 assert_rpm_wakelock_held(dev_priv); 556 } 557 558 static void gen9_enable_dc5(struct drm_i915_private *dev_priv) 559 { 560 assert_can_enable_dc5(dev_priv); 561 562 DRM_DEBUG_KMS("Enabling DC5\n"); 563 564 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 565 } 566 567 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 568 { 569 struct drm_device *dev = dev_priv->dev; 570 571 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); 572 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 573 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 574 "Backlight is not disabled.\n"); 575 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 576 "DC6 already programmed to be enabled.\n"); 577 578 assert_csr_loaded(dev_priv); 579 } 580 581 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) 582 { 583 /* 584 * During initialization, the firmware may not be loaded yet. 585 * We still want to make sure that the DC enabling flag is cleared. 586 */ 587 if (dev_priv->power_domains.initializing) 588 return; 589 590 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 591 "DC6 already programmed to be disabled.\n"); 592 } 593 594 static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv) 595 { 596 assert_can_disable_dc5(dev_priv); 597 598 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) 599 assert_can_disable_dc6(dev_priv); 600 601 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 602 } 603 604 void skl_enable_dc6(struct drm_i915_private *dev_priv) 605 { 606 assert_can_enable_dc6(dev_priv); 607 608 DRM_DEBUG_KMS("Enabling DC6\n"); 609 610 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 611 612 } 613 614 void skl_disable_dc6(struct drm_i915_private *dev_priv) 615 { 616 assert_can_disable_dc6(dev_priv); 617 618 DRM_DEBUG_KMS("Disabling DC6\n"); 619 620 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 621 } 622 623 static void skl_set_power_well(struct drm_i915_private *dev_priv, 624 struct i915_power_well *power_well, bool enable) 625 { 626 struct drm_device *dev = dev_priv->dev; 627 uint32_t tmp, fuse_status; 628 uint32_t req_mask, state_mask; 629 bool is_enabled, enable_requested, check_fuse_status = false; 630 631 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 632 fuse_status = I915_READ(SKL_FUSE_STATUS); 633 634 switch (power_well->data) { 635 case SKL_DISP_PW_1: 636 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 637 SKL_FUSE_PG0_DIST_STATUS), 1)) { 638 DRM_ERROR("PG0 not enabled\n"); 639 return; 640 } 641 break; 642 case SKL_DISP_PW_2: 643 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 644 DRM_ERROR("PG1 in disabled state\n"); 645 return; 646 } 647 break; 648 case SKL_DISP_PW_DDI_A_E: 649 case SKL_DISP_PW_DDI_B: 650 case SKL_DISP_PW_DDI_C: 651 case SKL_DISP_PW_DDI_D: 652 case SKL_DISP_PW_MISC_IO: 653 break; 654 default: 655 WARN(1, "Unknown power well %lu\n", power_well->data); 656 return; 657 } 658 659 req_mask = SKL_POWER_WELL_REQ(power_well->data); 660 enable_requested = tmp & req_mask; 661 state_mask = SKL_POWER_WELL_STATE(power_well->data); 662 is_enabled = tmp & state_mask; 663 664 if (enable) { 665 if (!enable_requested) { 666 WARN((tmp & state_mask) && 667 !I915_READ(HSW_PWR_WELL_BIOS), 668 "Invalid for power well status to be enabled, unless done by the BIOS, \ 669 when request is to disable!\n"); 670 if (power_well->data == SKL_DISP_PW_2) { 671 /* 672 * DDI buffer programming unnecessary during 673 * driver-load/resume as it's already done 674 * during modeset initialization then. It's 675 * also invalid here as encoder list is still 676 * uninitialized. 677 */ 678 if (!dev_priv->power_domains.initializing) 679 intel_prepare_ddi(dev); 680 } 681 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 682 } 683 684 if (!is_enabled) { 685 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 686 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 687 state_mask), 1)) 688 DRM_ERROR("%s enable timeout\n", 689 power_well->name); 690 check_fuse_status = true; 691 } 692 } else { 693 if (enable_requested) { 694 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 695 POSTING_READ(HSW_PWR_WELL_DRIVER); 696 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 697 } 698 } 699 700 if (check_fuse_status) { 701 if (power_well->data == SKL_DISP_PW_1) { 702 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 703 SKL_FUSE_PG1_DIST_STATUS), 1)) 704 DRM_ERROR("PG1 distributing status timeout\n"); 705 } else if (power_well->data == SKL_DISP_PW_2) { 706 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 707 SKL_FUSE_PG2_DIST_STATUS), 1)) 708 DRM_ERROR("PG2 distributing status timeout\n"); 709 } 710 } 711 712 if (enable && !is_enabled) 713 skl_power_well_post_enable(dev_priv, power_well); 714 } 715 716 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 717 struct i915_power_well *power_well) 718 { 719 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 720 721 /* 722 * We're taking over the BIOS, so clear any requests made by it since 723 * the driver is in charge now. 724 */ 725 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 726 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 727 } 728 729 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 730 struct i915_power_well *power_well) 731 { 732 hsw_set_power_well(dev_priv, power_well, true); 733 } 734 735 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 736 struct i915_power_well *power_well) 737 { 738 hsw_set_power_well(dev_priv, power_well, false); 739 } 740 741 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 742 struct i915_power_well *power_well) 743 { 744 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 745 SKL_POWER_WELL_STATE(power_well->data); 746 747 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 748 } 749 750 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 751 struct i915_power_well *power_well) 752 { 753 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 754 755 /* Clear any request made by BIOS as driver is taking over */ 756 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 757 } 758 759 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 760 struct i915_power_well *power_well) 761 { 762 skl_set_power_well(dev_priv, power_well, true); 763 } 764 765 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 766 struct i915_power_well *power_well) 767 { 768 skl_set_power_well(dev_priv, power_well, false); 769 } 770 771 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 772 struct i915_power_well *power_well) 773 { 774 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 775 } 776 777 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 778 struct i915_power_well *power_well) 779 { 780 gen9_disable_dc5_dc6(dev_priv); 781 } 782 783 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 784 struct i915_power_well *power_well) 785 { 786 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) 787 skl_enable_dc6(dev_priv); 788 else 789 gen9_enable_dc5(dev_priv); 790 } 791 792 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, 793 struct i915_power_well *power_well) 794 { 795 if (power_well->count > 0) { 796 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 797 } else { 798 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && 799 i915.enable_dc != 1) 800 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 801 else 802 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 803 } 804 } 805 806 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 807 struct i915_power_well *power_well) 808 { 809 } 810 811 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 812 struct i915_power_well *power_well) 813 { 814 return true; 815 } 816 817 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 818 struct i915_power_well *power_well, bool enable) 819 { 820 enum punit_power_well power_well_id = power_well->data; 821 u32 mask; 822 u32 state; 823 u32 ctrl; 824 825 mask = PUNIT_PWRGT_MASK(power_well_id); 826 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 827 PUNIT_PWRGT_PWR_GATE(power_well_id); 828 829 mutex_lock(&dev_priv->rps.hw_lock); 830 831 #define COND \ 832 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 833 834 if (COND) 835 goto out; 836 837 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 838 ctrl &= ~mask; 839 ctrl |= state; 840 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 841 842 if (wait_for(COND, 100)) 843 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 844 state, 845 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 846 847 #undef COND 848 849 out: 850 mutex_unlock(&dev_priv->rps.hw_lock); 851 } 852 853 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 854 struct i915_power_well *power_well) 855 { 856 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 857 } 858 859 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 860 struct i915_power_well *power_well) 861 { 862 vlv_set_power_well(dev_priv, power_well, true); 863 } 864 865 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 866 struct i915_power_well *power_well) 867 { 868 vlv_set_power_well(dev_priv, power_well, false); 869 } 870 871 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 872 struct i915_power_well *power_well) 873 { 874 int power_well_id = power_well->data; 875 bool enabled = false; 876 u32 mask; 877 u32 state; 878 u32 ctrl; 879 880 mask = PUNIT_PWRGT_MASK(power_well_id); 881 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 882 883 mutex_lock(&dev_priv->rps.hw_lock); 884 885 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 886 /* 887 * We only ever set the power-on and power-gate states, anything 888 * else is unexpected. 889 */ 890 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 891 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 892 if (state == ctrl) 893 enabled = true; 894 895 /* 896 * A transient state at this point would mean some unexpected party 897 * is poking at the power controls too. 898 */ 899 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 900 WARN_ON(ctrl != state); 901 902 mutex_unlock(&dev_priv->rps.hw_lock); 903 904 return enabled; 905 } 906 907 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 908 { 909 enum pipe pipe; 910 911 /* 912 * Enable the CRI clock source so we can get at the 913 * display and the reference clock for VGA 914 * hotplug / manual detection. Supposedly DSI also 915 * needs the ref clock up and running. 916 * 917 * CHV DPLL B/C have some issues if VGA mode is enabled. 918 */ 919 for_each_pipe(dev_priv->dev, pipe) { 920 u32 val = I915_READ(DPLL(pipe)); 921 922 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 923 if (pipe != PIPE_A) 924 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 925 926 I915_WRITE(DPLL(pipe), val); 927 } 928 929 spin_lock_irq(&dev_priv->irq_lock); 930 valleyview_enable_display_irqs(dev_priv); 931 spin_unlock_irq(&dev_priv->irq_lock); 932 933 /* 934 * During driver initialization/resume we can avoid restoring the 935 * part of the HW/SW state that will be inited anyway explicitly. 936 */ 937 if (dev_priv->power_domains.initializing) 938 return; 939 940 intel_hpd_init(dev_priv); 941 942 i915_redisable_vga_power_on(dev_priv->dev); 943 } 944 945 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 946 { 947 spin_lock_irq(&dev_priv->irq_lock); 948 valleyview_disable_display_irqs(dev_priv); 949 spin_unlock_irq(&dev_priv->irq_lock); 950 951 vlv_power_sequencer_reset(dev_priv); 952 } 953 954 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 955 struct i915_power_well *power_well) 956 { 957 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 958 959 vlv_set_power_well(dev_priv, power_well, true); 960 961 vlv_display_power_well_init(dev_priv); 962 } 963 964 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 965 struct i915_power_well *power_well) 966 { 967 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 968 969 vlv_display_power_well_deinit(dev_priv); 970 971 vlv_set_power_well(dev_priv, power_well, false); 972 } 973 974 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 975 struct i915_power_well *power_well) 976 { 977 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 978 979 /* since ref/cri clock was enabled */ 980 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 981 982 vlv_set_power_well(dev_priv, power_well, true); 983 984 /* 985 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 986 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 987 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 988 * b. The other bits such as sfr settings / modesel may all 989 * be set to 0. 990 * 991 * This should only be done on init and resume from S3 with 992 * both PLLs disabled, or we risk losing DPIO and PLL 993 * synchronization. 994 */ 995 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 996 } 997 998 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 999 struct i915_power_well *power_well) 1000 { 1001 enum pipe pipe; 1002 1003 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1004 1005 for_each_pipe(dev_priv, pipe) 1006 assert_pll_disabled(dev_priv, pipe); 1007 1008 /* Assert common reset */ 1009 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1010 1011 vlv_set_power_well(dev_priv, power_well, false); 1012 } 1013 1014 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1015 1016 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1017 int power_well_id) 1018 { 1019 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1020 int i; 1021 1022 for (i = 0; i < power_domains->power_well_count; i++) { 1023 struct i915_power_well *power_well; 1024 1025 power_well = &power_domains->power_wells[i]; 1026 if (power_well->data == power_well_id) 1027 return power_well; 1028 } 1029 1030 return NULL; 1031 } 1032 1033 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1034 1035 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1036 { 1037 struct i915_power_well *cmn_bc = 1038 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1039 struct i915_power_well *cmn_d = 1040 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1041 u32 phy_control = dev_priv->chv_phy_control; 1042 u32 phy_status = 0; 1043 u32 phy_status_mask = 0xffffffff; 1044 u32 tmp; 1045 1046 /* 1047 * The BIOS can leave the PHY is some weird state 1048 * where it doesn't fully power down some parts. 1049 * Disable the asserts until the PHY has been fully 1050 * reset (ie. the power well has been disabled at 1051 * least once). 1052 */ 1053 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1054 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1055 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1056 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1057 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1058 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1059 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1060 1061 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1062 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1063 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1064 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1065 1066 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1067 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1068 1069 /* this assumes override is only used to enable lanes */ 1070 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1071 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1072 1073 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1074 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1075 1076 /* CL1 is on whenever anything is on in either channel */ 1077 if (BITS_SET(phy_control, 1078 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1079 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1080 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1081 1082 /* 1083 * The DPLLB check accounts for the pipe B + port A usage 1084 * with CL2 powered up but all the lanes in the second channel 1085 * powered down. 1086 */ 1087 if (BITS_SET(phy_control, 1088 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1089 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1090 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1091 1092 if (BITS_SET(phy_control, 1093 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1094 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1095 if (BITS_SET(phy_control, 1096 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1097 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1098 1099 if (BITS_SET(phy_control, 1100 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1101 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1102 if (BITS_SET(phy_control, 1103 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1104 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1105 } 1106 1107 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1108 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1109 1110 /* this assumes override is only used to enable lanes */ 1111 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1112 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1113 1114 if (BITS_SET(phy_control, 1115 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1116 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1117 1118 if (BITS_SET(phy_control, 1119 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1120 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1121 if (BITS_SET(phy_control, 1122 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1123 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1124 } 1125 1126 phy_status &= phy_status_mask; 1127 1128 /* 1129 * The PHY may be busy with some initial calibration and whatnot, 1130 * so the power state can take a while to actually change. 1131 */ 1132 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) 1133 WARN(phy_status != tmp, 1134 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1135 tmp, phy_status, dev_priv->chv_phy_control); 1136 } 1137 1138 #undef BITS_SET 1139 1140 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1141 struct i915_power_well *power_well) 1142 { 1143 enum dpio_phy phy; 1144 enum pipe pipe; 1145 uint32_t tmp; 1146 1147 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1148 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1149 1150 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1151 pipe = PIPE_A; 1152 phy = DPIO_PHY0; 1153 } else { 1154 pipe = PIPE_C; 1155 phy = DPIO_PHY1; 1156 } 1157 1158 /* since ref/cri clock was enabled */ 1159 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1160 vlv_set_power_well(dev_priv, power_well, true); 1161 1162 /* Poll for phypwrgood signal */ 1163 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 1164 DRM_ERROR("Display PHY %d is not power up\n", phy); 1165 1166 mutex_lock(&dev_priv->sb_lock); 1167 1168 /* Enable dynamic power down */ 1169 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1170 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1171 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1172 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1173 1174 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1175 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1176 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1177 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1178 } else { 1179 /* 1180 * Force the non-existing CL2 off. BXT does this 1181 * too, so maybe it saves some power even though 1182 * CL2 doesn't exist? 1183 */ 1184 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1185 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1186 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1187 } 1188 1189 mutex_unlock(&dev_priv->sb_lock); 1190 1191 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1192 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1193 1194 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1195 phy, dev_priv->chv_phy_control); 1196 1197 assert_chv_phy_status(dev_priv); 1198 } 1199 1200 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1201 struct i915_power_well *power_well) 1202 { 1203 enum dpio_phy phy; 1204 1205 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1206 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1207 1208 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1209 phy = DPIO_PHY0; 1210 assert_pll_disabled(dev_priv, PIPE_A); 1211 assert_pll_disabled(dev_priv, PIPE_B); 1212 } else { 1213 phy = DPIO_PHY1; 1214 assert_pll_disabled(dev_priv, PIPE_C); 1215 } 1216 1217 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1218 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1219 1220 vlv_set_power_well(dev_priv, power_well, false); 1221 1222 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1223 phy, dev_priv->chv_phy_control); 1224 1225 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1226 dev_priv->chv_phy_assert[phy] = true; 1227 1228 assert_chv_phy_status(dev_priv); 1229 } 1230 1231 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1232 enum dpio_channel ch, bool override, unsigned int mask) 1233 { 1234 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1235 u32 reg, val, expected, actual; 1236 1237 /* 1238 * The BIOS can leave the PHY is some weird state 1239 * where it doesn't fully power down some parts. 1240 * Disable the asserts until the PHY has been fully 1241 * reset (ie. the power well has been disabled at 1242 * least once). 1243 */ 1244 if (!dev_priv->chv_phy_assert[phy]) 1245 return; 1246 1247 if (ch == DPIO_CH0) 1248 reg = _CHV_CMN_DW0_CH0; 1249 else 1250 reg = _CHV_CMN_DW6_CH1; 1251 1252 mutex_lock(&dev_priv->sb_lock); 1253 val = vlv_dpio_read(dev_priv, pipe, reg); 1254 mutex_unlock(&dev_priv->sb_lock); 1255 1256 /* 1257 * This assumes !override is only used when the port is disabled. 1258 * All lanes should power down even without the override when 1259 * the port is disabled. 1260 */ 1261 if (!override || mask == 0xf) { 1262 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1263 /* 1264 * If CH1 common lane is not active anymore 1265 * (eg. for pipe B DPLL) the entire channel will 1266 * shut down, which causes the common lane registers 1267 * to read as 0. That means we can't actually check 1268 * the lane power down status bits, but as the entire 1269 * register reads as 0 it's a good indication that the 1270 * channel is indeed entirely powered down. 1271 */ 1272 if (ch == DPIO_CH1 && val == 0) 1273 expected = 0; 1274 } else if (mask != 0x0) { 1275 expected = DPIO_ANYDL_POWERDOWN; 1276 } else { 1277 expected = 0; 1278 } 1279 1280 if (ch == DPIO_CH0) 1281 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1282 else 1283 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1284 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1285 1286 WARN(actual != expected, 1287 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1288 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1289 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1290 reg, val); 1291 } 1292 1293 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1294 enum dpio_channel ch, bool override) 1295 { 1296 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1297 bool was_override; 1298 1299 mutex_lock(&power_domains->lock); 1300 1301 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1302 1303 if (override == was_override) 1304 goto out; 1305 1306 if (override) 1307 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1308 else 1309 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1310 1311 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1312 1313 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1314 phy, ch, dev_priv->chv_phy_control); 1315 1316 assert_chv_phy_status(dev_priv); 1317 1318 out: 1319 mutex_unlock(&power_domains->lock); 1320 1321 return was_override; 1322 } 1323 1324 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1325 bool override, unsigned int mask) 1326 { 1327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1328 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1329 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1330 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1331 1332 mutex_lock(&power_domains->lock); 1333 1334 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1335 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1336 1337 if (override) 1338 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1339 else 1340 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1341 1342 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1343 1344 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1345 phy, ch, mask, dev_priv->chv_phy_control); 1346 1347 assert_chv_phy_status(dev_priv); 1348 1349 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1350 1351 mutex_unlock(&power_domains->lock); 1352 } 1353 1354 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1355 struct i915_power_well *power_well) 1356 { 1357 enum pipe pipe = power_well->data; 1358 bool enabled; 1359 u32 state, ctrl; 1360 1361 mutex_lock(&dev_priv->rps.hw_lock); 1362 1363 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1364 /* 1365 * We only ever set the power-on and power-gate states, anything 1366 * else is unexpected. 1367 */ 1368 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1369 enabled = state == DP_SSS_PWR_ON(pipe); 1370 1371 /* 1372 * A transient state at this point would mean some unexpected party 1373 * is poking at the power controls too. 1374 */ 1375 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1376 WARN_ON(ctrl << 16 != state); 1377 1378 mutex_unlock(&dev_priv->rps.hw_lock); 1379 1380 return enabled; 1381 } 1382 1383 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1384 struct i915_power_well *power_well, 1385 bool enable) 1386 { 1387 enum pipe pipe = power_well->data; 1388 u32 state; 1389 u32 ctrl; 1390 1391 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1392 1393 mutex_lock(&dev_priv->rps.hw_lock); 1394 1395 #define COND \ 1396 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1397 1398 if (COND) 1399 goto out; 1400 1401 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1402 ctrl &= ~DP_SSC_MASK(pipe); 1403 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1404 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1405 1406 if (wait_for(COND, 100)) 1407 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1408 state, 1409 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1410 1411 #undef COND 1412 1413 out: 1414 mutex_unlock(&dev_priv->rps.hw_lock); 1415 } 1416 1417 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1418 struct i915_power_well *power_well) 1419 { 1420 WARN_ON_ONCE(power_well->data != PIPE_A); 1421 1422 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1423 } 1424 1425 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1426 struct i915_power_well *power_well) 1427 { 1428 WARN_ON_ONCE(power_well->data != PIPE_A); 1429 1430 chv_set_pipe_power_well(dev_priv, power_well, true); 1431 1432 vlv_display_power_well_init(dev_priv); 1433 } 1434 1435 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1436 struct i915_power_well *power_well) 1437 { 1438 WARN_ON_ONCE(power_well->data != PIPE_A); 1439 1440 vlv_display_power_well_deinit(dev_priv); 1441 1442 chv_set_pipe_power_well(dev_priv, power_well, false); 1443 } 1444 1445 /** 1446 * intel_display_power_get - grab a power domain reference 1447 * @dev_priv: i915 device instance 1448 * @domain: power domain to reference 1449 * 1450 * This function grabs a power domain reference for @domain and ensures that the 1451 * power domain and all its parents are powered up. Therefore users should only 1452 * grab a reference to the innermost power domain they need. 1453 * 1454 * Any power domain reference obtained by this function must have a symmetric 1455 * call to intel_display_power_put() to release the reference again. 1456 */ 1457 void intel_display_power_get(struct drm_i915_private *dev_priv, 1458 enum intel_display_power_domain domain) 1459 { 1460 struct i915_power_domains *power_domains; 1461 struct i915_power_well *power_well; 1462 int i; 1463 1464 intel_runtime_pm_get(dev_priv); 1465 1466 power_domains = &dev_priv->power_domains; 1467 1468 mutex_lock(&power_domains->lock); 1469 1470 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1471 if (!power_well->count++) 1472 intel_power_well_enable(dev_priv, power_well); 1473 } 1474 1475 power_domains->domain_use_count[domain]++; 1476 1477 mutex_unlock(&power_domains->lock); 1478 } 1479 1480 /** 1481 * intel_display_power_put - release a power domain reference 1482 * @dev_priv: i915 device instance 1483 * @domain: power domain to reference 1484 * 1485 * This function drops the power domain reference obtained by 1486 * intel_display_power_get() and might power down the corresponding hardware 1487 * block right away if this is the last reference. 1488 */ 1489 void intel_display_power_put(struct drm_i915_private *dev_priv, 1490 enum intel_display_power_domain domain) 1491 { 1492 struct i915_power_domains *power_domains; 1493 struct i915_power_well *power_well; 1494 int i; 1495 1496 power_domains = &dev_priv->power_domains; 1497 1498 mutex_lock(&power_domains->lock); 1499 1500 WARN(!power_domains->domain_use_count[domain], 1501 "Use count on domain %s is already zero\n", 1502 intel_display_power_domain_str(domain)); 1503 power_domains->domain_use_count[domain]--; 1504 1505 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1506 WARN(!power_well->count, 1507 "Use count on power well %s is already zero", 1508 power_well->name); 1509 1510 if (!--power_well->count) 1511 intel_power_well_disable(dev_priv, power_well); 1512 } 1513 1514 mutex_unlock(&power_domains->lock); 1515 1516 intel_runtime_pm_put(dev_priv); 1517 } 1518 1519 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1520 BIT(POWER_DOMAIN_PIPE_A) | \ 1521 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1522 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1523 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1524 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1525 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1526 BIT(POWER_DOMAIN_PORT_CRT) | \ 1527 BIT(POWER_DOMAIN_PLLS) | \ 1528 BIT(POWER_DOMAIN_AUX_A) | \ 1529 BIT(POWER_DOMAIN_AUX_B) | \ 1530 BIT(POWER_DOMAIN_AUX_C) | \ 1531 BIT(POWER_DOMAIN_AUX_D) | \ 1532 BIT(POWER_DOMAIN_GMBUS) | \ 1533 BIT(POWER_DOMAIN_INIT)) 1534 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1535 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 1536 BIT(POWER_DOMAIN_INIT)) 1537 1538 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1539 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1540 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1541 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1542 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1543 BIT(POWER_DOMAIN_INIT)) 1544 1545 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 1546 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 1547 1548 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1549 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1550 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1551 BIT(POWER_DOMAIN_PORT_CRT) | \ 1552 BIT(POWER_DOMAIN_AUX_B) | \ 1553 BIT(POWER_DOMAIN_AUX_C) | \ 1554 BIT(POWER_DOMAIN_INIT)) 1555 1556 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1557 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1558 BIT(POWER_DOMAIN_AUX_B) | \ 1559 BIT(POWER_DOMAIN_INIT)) 1560 1561 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1562 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1563 BIT(POWER_DOMAIN_AUX_B) | \ 1564 BIT(POWER_DOMAIN_INIT)) 1565 1566 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1567 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1568 BIT(POWER_DOMAIN_AUX_C) | \ 1569 BIT(POWER_DOMAIN_INIT)) 1570 1571 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1572 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1573 BIT(POWER_DOMAIN_AUX_C) | \ 1574 BIT(POWER_DOMAIN_INIT)) 1575 1576 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1577 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1578 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1579 BIT(POWER_DOMAIN_AUX_B) | \ 1580 BIT(POWER_DOMAIN_AUX_C) | \ 1581 BIT(POWER_DOMAIN_INIT)) 1582 1583 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1584 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1585 BIT(POWER_DOMAIN_AUX_D) | \ 1586 BIT(POWER_DOMAIN_INIT)) 1587 1588 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1589 .sync_hw = i9xx_always_on_power_well_noop, 1590 .enable = i9xx_always_on_power_well_noop, 1591 .disable = i9xx_always_on_power_well_noop, 1592 .is_enabled = i9xx_always_on_power_well_enabled, 1593 }; 1594 1595 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1596 .sync_hw = chv_pipe_power_well_sync_hw, 1597 .enable = chv_pipe_power_well_enable, 1598 .disable = chv_pipe_power_well_disable, 1599 .is_enabled = chv_pipe_power_well_enabled, 1600 }; 1601 1602 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1603 .sync_hw = vlv_power_well_sync_hw, 1604 .enable = chv_dpio_cmn_power_well_enable, 1605 .disable = chv_dpio_cmn_power_well_disable, 1606 .is_enabled = vlv_power_well_enabled, 1607 }; 1608 1609 static struct i915_power_well i9xx_always_on_power_well[] = { 1610 { 1611 .name = "always-on", 1612 .always_on = 1, 1613 .domains = POWER_DOMAIN_MASK, 1614 .ops = &i9xx_always_on_power_well_ops, 1615 }, 1616 }; 1617 1618 static const struct i915_power_well_ops hsw_power_well_ops = { 1619 .sync_hw = hsw_power_well_sync_hw, 1620 .enable = hsw_power_well_enable, 1621 .disable = hsw_power_well_disable, 1622 .is_enabled = hsw_power_well_enabled, 1623 }; 1624 1625 static const struct i915_power_well_ops skl_power_well_ops = { 1626 .sync_hw = skl_power_well_sync_hw, 1627 .enable = skl_power_well_enable, 1628 .disable = skl_power_well_disable, 1629 .is_enabled = skl_power_well_enabled, 1630 }; 1631 1632 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1633 .sync_hw = gen9_dc_off_power_well_sync_hw, 1634 .enable = gen9_dc_off_power_well_enable, 1635 .disable = gen9_dc_off_power_well_disable, 1636 .is_enabled = gen9_dc_off_power_well_enabled, 1637 }; 1638 1639 static struct i915_power_well hsw_power_wells[] = { 1640 { 1641 .name = "always-on", 1642 .always_on = 1, 1643 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 1644 .ops = &i9xx_always_on_power_well_ops, 1645 }, 1646 { 1647 .name = "display", 1648 .domains = HSW_DISPLAY_POWER_DOMAINS, 1649 .ops = &hsw_power_well_ops, 1650 }, 1651 }; 1652 1653 static struct i915_power_well bdw_power_wells[] = { 1654 { 1655 .name = "always-on", 1656 .always_on = 1, 1657 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 1658 .ops = &i9xx_always_on_power_well_ops, 1659 }, 1660 { 1661 .name = "display", 1662 .domains = BDW_DISPLAY_POWER_DOMAINS, 1663 .ops = &hsw_power_well_ops, 1664 }, 1665 }; 1666 1667 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1668 .sync_hw = vlv_power_well_sync_hw, 1669 .enable = vlv_display_power_well_enable, 1670 .disable = vlv_display_power_well_disable, 1671 .is_enabled = vlv_power_well_enabled, 1672 }; 1673 1674 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1675 .sync_hw = vlv_power_well_sync_hw, 1676 .enable = vlv_dpio_cmn_power_well_enable, 1677 .disable = vlv_dpio_cmn_power_well_disable, 1678 .is_enabled = vlv_power_well_enabled, 1679 }; 1680 1681 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1682 .sync_hw = vlv_power_well_sync_hw, 1683 .enable = vlv_power_well_enable, 1684 .disable = vlv_power_well_disable, 1685 .is_enabled = vlv_power_well_enabled, 1686 }; 1687 1688 static struct i915_power_well vlv_power_wells[] = { 1689 { 1690 .name = "always-on", 1691 .always_on = 1, 1692 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1693 .ops = &i9xx_always_on_power_well_ops, 1694 .data = PUNIT_POWER_WELL_ALWAYS_ON, 1695 }, 1696 { 1697 .name = "display", 1698 .domains = VLV_DISPLAY_POWER_DOMAINS, 1699 .data = PUNIT_POWER_WELL_DISP2D, 1700 .ops = &vlv_display_power_well_ops, 1701 }, 1702 { 1703 .name = "dpio-tx-b-01", 1704 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1705 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1706 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1707 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1708 .ops = &vlv_dpio_power_well_ops, 1709 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1710 }, 1711 { 1712 .name = "dpio-tx-b-23", 1713 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1714 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1715 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1716 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1717 .ops = &vlv_dpio_power_well_ops, 1718 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1719 }, 1720 { 1721 .name = "dpio-tx-c-01", 1722 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1723 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1724 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1725 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1726 .ops = &vlv_dpio_power_well_ops, 1727 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1728 }, 1729 { 1730 .name = "dpio-tx-c-23", 1731 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1732 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1733 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1734 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1735 .ops = &vlv_dpio_power_well_ops, 1736 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1737 }, 1738 { 1739 .name = "dpio-common", 1740 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1741 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1742 .ops = &vlv_dpio_cmn_power_well_ops, 1743 }, 1744 }; 1745 1746 static struct i915_power_well chv_power_wells[] = { 1747 { 1748 .name = "always-on", 1749 .always_on = 1, 1750 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1751 .ops = &i9xx_always_on_power_well_ops, 1752 }, 1753 { 1754 .name = "display", 1755 /* 1756 * Pipe A power well is the new disp2d well. Pipe B and C 1757 * power wells don't actually exist. Pipe A power well is 1758 * required for any pipe to work. 1759 */ 1760 .domains = VLV_DISPLAY_POWER_DOMAINS, 1761 .data = PIPE_A, 1762 .ops = &chv_pipe_power_well_ops, 1763 }, 1764 { 1765 .name = "dpio-common-bc", 1766 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1767 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1768 .ops = &chv_dpio_cmn_power_well_ops, 1769 }, 1770 { 1771 .name = "dpio-common-d", 1772 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1773 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1774 .ops = &chv_dpio_cmn_power_well_ops, 1775 }, 1776 }; 1777 1778 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1779 int power_well_id) 1780 { 1781 struct i915_power_well *power_well; 1782 bool ret; 1783 1784 power_well = lookup_power_well(dev_priv, power_well_id); 1785 ret = power_well->ops->is_enabled(dev_priv, power_well); 1786 1787 return ret; 1788 } 1789 1790 static struct i915_power_well skl_power_wells[] = { 1791 { 1792 .name = "always-on", 1793 .always_on = 1, 1794 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1795 .ops = &i9xx_always_on_power_well_ops, 1796 .data = SKL_DISP_PW_ALWAYS_ON, 1797 }, 1798 { 1799 .name = "power well 1", 1800 /* Handled by the DMC firmware */ 1801 .domains = 0, 1802 .ops = &skl_power_well_ops, 1803 .data = SKL_DISP_PW_1, 1804 }, 1805 { 1806 .name = "MISC IO power well", 1807 /* Handled by the DMC firmware */ 1808 .domains = 0, 1809 .ops = &skl_power_well_ops, 1810 .data = SKL_DISP_PW_MISC_IO, 1811 }, 1812 { 1813 .name = "DC off", 1814 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 1815 .ops = &gen9_dc_off_power_well_ops, 1816 .data = SKL_DISP_PW_DC_OFF, 1817 }, 1818 { 1819 .name = "power well 2", 1820 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1821 .ops = &skl_power_well_ops, 1822 .data = SKL_DISP_PW_2, 1823 }, 1824 { 1825 .name = "DDI A/E power well", 1826 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1827 .ops = &skl_power_well_ops, 1828 .data = SKL_DISP_PW_DDI_A_E, 1829 }, 1830 { 1831 .name = "DDI B power well", 1832 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1833 .ops = &skl_power_well_ops, 1834 .data = SKL_DISP_PW_DDI_B, 1835 }, 1836 { 1837 .name = "DDI C power well", 1838 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1839 .ops = &skl_power_well_ops, 1840 .data = SKL_DISP_PW_DDI_C, 1841 }, 1842 { 1843 .name = "DDI D power well", 1844 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1845 .ops = &skl_power_well_ops, 1846 .data = SKL_DISP_PW_DDI_D, 1847 }, 1848 }; 1849 1850 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv) 1851 { 1852 struct i915_power_well *well; 1853 1854 if (!IS_SKYLAKE(dev_priv)) 1855 return; 1856 1857 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1858 intel_power_well_enable(dev_priv, well); 1859 1860 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1861 intel_power_well_enable(dev_priv, well); 1862 } 1863 1864 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv) 1865 { 1866 struct i915_power_well *well; 1867 1868 if (!IS_SKYLAKE(dev_priv)) 1869 return; 1870 1871 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1872 intel_power_well_disable(dev_priv, well); 1873 1874 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1875 intel_power_well_disable(dev_priv, well); 1876 } 1877 1878 static struct i915_power_well bxt_power_wells[] = { 1879 { 1880 .name = "always-on", 1881 .always_on = 1, 1882 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1883 .ops = &i9xx_always_on_power_well_ops, 1884 }, 1885 { 1886 .name = "power well 1", 1887 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1888 .ops = &skl_power_well_ops, 1889 .data = SKL_DISP_PW_1, 1890 }, 1891 { 1892 .name = "DC off", 1893 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 1894 .ops = &gen9_dc_off_power_well_ops, 1895 .data = SKL_DISP_PW_DC_OFF, 1896 }, 1897 { 1898 .name = "power well 2", 1899 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1900 .ops = &skl_power_well_ops, 1901 .data = SKL_DISP_PW_2, 1902 }, 1903 }; 1904 1905 static int 1906 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 1907 int disable_power_well) 1908 { 1909 if (disable_power_well >= 0) 1910 return !!disable_power_well; 1911 1912 if (IS_BROXTON(dev_priv)) { 1913 DRM_DEBUG_KMS("Disabling display power well support\n"); 1914 return 0; 1915 } 1916 1917 return 1; 1918 } 1919 1920 #define set_power_wells(power_domains, __power_wells) ({ \ 1921 (power_domains)->power_wells = (__power_wells); \ 1922 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 1923 }) 1924 1925 /** 1926 * intel_power_domains_init - initializes the power domain structures 1927 * @dev_priv: i915 device instance 1928 * 1929 * Initializes the power domain structures for @dev_priv depending upon the 1930 * supported platform. 1931 */ 1932 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1933 { 1934 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1935 1936 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 1937 i915.disable_power_well); 1938 1939 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 1940 1941 mutex_init(&power_domains->lock); 1942 1943 /* 1944 * The enabling order will be from lower to higher indexed wells, 1945 * the disabling order is reversed. 1946 */ 1947 if (IS_HASWELL(dev_priv->dev)) { 1948 set_power_wells(power_domains, hsw_power_wells); 1949 } else if (IS_BROADWELL(dev_priv->dev)) { 1950 set_power_wells(power_domains, bdw_power_wells); 1951 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { 1952 set_power_wells(power_domains, skl_power_wells); 1953 } else if (IS_BROXTON(dev_priv->dev)) { 1954 set_power_wells(power_domains, bxt_power_wells); 1955 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1956 set_power_wells(power_domains, chv_power_wells); 1957 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 1958 set_power_wells(power_domains, vlv_power_wells); 1959 } else { 1960 set_power_wells(power_domains, i9xx_always_on_power_well); 1961 } 1962 1963 return 0; 1964 } 1965 1966 /** 1967 * intel_power_domains_fini - finalizes the power domain structures 1968 * @dev_priv: i915 device instance 1969 * 1970 * Finalizes the power domain structures for @dev_priv depending upon the 1971 * supported platform. This function also disables runtime pm and ensures that 1972 * the device stays powered up so that the driver can be reloaded. 1973 */ 1974 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 1975 { 1976 struct device *device = &dev_priv->dev->pdev->dev; 1977 1978 /* 1979 * The i915.ko module is still not prepared to be loaded when 1980 * the power well is not enabled, so just enable it in case 1981 * we're going to unload/reload. 1982 * The following also reacquires the RPM reference the core passed 1983 * to the driver during loading, which is dropped in 1984 * intel_runtime_pm_enable(). We have to hand back the control of the 1985 * device to the core with this reference held. 1986 */ 1987 intel_display_set_init_power(dev_priv, true); 1988 1989 /* Remove the refcount we took to keep power well support disabled. */ 1990 if (!i915.disable_power_well) 1991 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 1992 1993 /* 1994 * Remove the refcount we took in intel_runtime_pm_enable() in case 1995 * the platform doesn't support runtime PM. 1996 */ 1997 if (!HAS_RUNTIME_PM(dev_priv)) 1998 pm_runtime_put(device); 1999 } 2000 2001 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2002 { 2003 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2004 struct i915_power_well *power_well; 2005 int i; 2006 2007 mutex_lock(&power_domains->lock); 2008 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 2009 power_well->ops->sync_hw(dev_priv, power_well); 2010 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2011 power_well); 2012 } 2013 mutex_unlock(&power_domains->lock); 2014 } 2015 2016 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2017 bool resume) 2018 { 2019 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2020 uint32_t val; 2021 2022 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2023 2024 /* enable PCH reset handshake */ 2025 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2026 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2027 2028 /* enable PG1 and Misc I/O */ 2029 mutex_lock(&power_domains->lock); 2030 skl_pw1_misc_io_init(dev_priv); 2031 mutex_unlock(&power_domains->lock); 2032 2033 if (!resume) 2034 return; 2035 2036 skl_init_cdclk(dev_priv); 2037 2038 if (dev_priv->csr.dmc_payload) 2039 intel_csr_load_program(dev_priv); 2040 } 2041 2042 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2043 { 2044 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2045 2046 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2047 2048 skl_uninit_cdclk(dev_priv); 2049 2050 /* The spec doesn't call for removing the reset handshake flag */ 2051 /* disable PG1 and Misc I/O */ 2052 mutex_lock(&power_domains->lock); 2053 skl_pw1_misc_io_fini(dev_priv); 2054 mutex_unlock(&power_domains->lock); 2055 } 2056 2057 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2058 { 2059 struct i915_power_well *cmn_bc = 2060 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2061 struct i915_power_well *cmn_d = 2062 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2063 2064 /* 2065 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2066 * workaround never ever read DISPLAY_PHY_CONTROL, and 2067 * instead maintain a shadow copy ourselves. Use the actual 2068 * power well state and lane status to reconstruct the 2069 * expected initial value. 2070 */ 2071 dev_priv->chv_phy_control = 2072 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2073 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2074 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2075 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2076 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2077 2078 /* 2079 * If all lanes are disabled we leave the override disabled 2080 * with all power down bits cleared to match the state we 2081 * would use after disabling the port. Otherwise enable the 2082 * override and set the lane powerdown bits accding to the 2083 * current lane status. 2084 */ 2085 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2086 uint32_t status = I915_READ(DPLL(PIPE_A)); 2087 unsigned int mask; 2088 2089 mask = status & DPLL_PORTB_READY_MASK; 2090 if (mask == 0xf) 2091 mask = 0x0; 2092 else 2093 dev_priv->chv_phy_control |= 2094 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2095 2096 dev_priv->chv_phy_control |= 2097 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2098 2099 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2100 if (mask == 0xf) 2101 mask = 0x0; 2102 else 2103 dev_priv->chv_phy_control |= 2104 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2105 2106 dev_priv->chv_phy_control |= 2107 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2108 2109 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2110 2111 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2112 } else { 2113 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2114 } 2115 2116 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2117 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2118 unsigned int mask; 2119 2120 mask = status & DPLL_PORTD_READY_MASK; 2121 2122 if (mask == 0xf) 2123 mask = 0x0; 2124 else 2125 dev_priv->chv_phy_control |= 2126 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2127 2128 dev_priv->chv_phy_control |= 2129 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2130 2131 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2132 2133 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2134 } else { 2135 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2136 } 2137 2138 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2139 2140 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2141 dev_priv->chv_phy_control); 2142 } 2143 2144 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2145 { 2146 struct i915_power_well *cmn = 2147 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2148 struct i915_power_well *disp2d = 2149 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2150 2151 /* If the display might be already active skip this */ 2152 if (cmn->ops->is_enabled(dev_priv, cmn) && 2153 disp2d->ops->is_enabled(dev_priv, disp2d) && 2154 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2155 return; 2156 2157 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2158 2159 /* cmnlane needs DPLL registers */ 2160 disp2d->ops->enable(dev_priv, disp2d); 2161 2162 /* 2163 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2164 * Need to assert and de-assert PHY SB reset by gating the 2165 * common lane power, then un-gating it. 2166 * Simply ungating isn't enough to reset the PHY enough to get 2167 * ports and lanes running. 2168 */ 2169 cmn->ops->disable(dev_priv, cmn); 2170 } 2171 2172 /** 2173 * intel_power_domains_init_hw - initialize hardware power domain state 2174 * @dev_priv: i915 device instance 2175 * 2176 * This function initializes the hardware power domain state and enables all 2177 * power domains using intel_display_set_init_power(). 2178 */ 2179 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2180 { 2181 struct drm_device *dev = dev_priv->dev; 2182 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2183 2184 power_domains->initializing = true; 2185 2186 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 2187 skl_display_core_init(dev_priv, resume); 2188 } else if (IS_CHERRYVIEW(dev)) { 2189 mutex_lock(&power_domains->lock); 2190 chv_phy_control_init(dev_priv); 2191 mutex_unlock(&power_domains->lock); 2192 } else if (IS_VALLEYVIEW(dev)) { 2193 mutex_lock(&power_domains->lock); 2194 vlv_cmnlane_wa(dev_priv); 2195 mutex_unlock(&power_domains->lock); 2196 } 2197 2198 /* For now, we need the power well to be always enabled. */ 2199 intel_display_set_init_power(dev_priv, true); 2200 /* Disable power support if the user asked so. */ 2201 if (!i915.disable_power_well) 2202 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 2203 intel_power_domains_sync_hw(dev_priv); 2204 power_domains->initializing = false; 2205 } 2206 2207 /** 2208 * intel_power_domains_suspend - suspend power domain state 2209 * @dev_priv: i915 device instance 2210 * 2211 * This function prepares the hardware power domain state before entering 2212 * system suspend. It must be paired with intel_power_domains_init_hw(). 2213 */ 2214 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2215 { 2216 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2217 skl_display_core_uninit(dev_priv); 2218 2219 /* 2220 * Even if power well support was disabled we still want to disable 2221 * power wells while we are system suspended. 2222 */ 2223 if (!i915.disable_power_well) 2224 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2225 } 2226 2227 /** 2228 * intel_runtime_pm_get - grab a runtime pm reference 2229 * @dev_priv: i915 device instance 2230 * 2231 * This function grabs a device-level runtime pm reference (mostly used for GEM 2232 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2233 * 2234 * Any runtime pm reference obtained by this function must have a symmetric 2235 * call to intel_runtime_pm_put() to release the reference again. 2236 */ 2237 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2238 { 2239 struct drm_device *dev = dev_priv->dev; 2240 struct device *device = &dev->pdev->dev; 2241 2242 pm_runtime_get_sync(device); 2243 2244 atomic_inc(&dev_priv->pm.wakeref_count); 2245 assert_rpm_wakelock_held(dev_priv); 2246 } 2247 2248 /** 2249 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2250 * @dev_priv: i915 device instance 2251 * 2252 * This function grabs a device-level runtime pm reference (mostly used for GEM 2253 * code to ensure the GTT or GT is on). 2254 * 2255 * It will _not_ power up the device but instead only check that it's powered 2256 * on. Therefore it is only valid to call this functions from contexts where 2257 * the device is known to be powered up and where trying to power it up would 2258 * result in hilarity and deadlocks. That pretty much means only the system 2259 * suspend/resume code where this is used to grab runtime pm references for 2260 * delayed setup down in work items. 2261 * 2262 * Any runtime pm reference obtained by this function must have a symmetric 2263 * call to intel_runtime_pm_put() to release the reference again. 2264 */ 2265 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2266 { 2267 struct drm_device *dev = dev_priv->dev; 2268 struct device *device = &dev->pdev->dev; 2269 2270 assert_rpm_wakelock_held(dev_priv); 2271 pm_runtime_get_noresume(device); 2272 2273 atomic_inc(&dev_priv->pm.wakeref_count); 2274 } 2275 2276 /** 2277 * intel_runtime_pm_put - release a runtime pm reference 2278 * @dev_priv: i915 device instance 2279 * 2280 * This function drops the device-level runtime pm reference obtained by 2281 * intel_runtime_pm_get() and might power down the corresponding 2282 * hardware block right away if this is the last reference. 2283 */ 2284 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2285 { 2286 struct drm_device *dev = dev_priv->dev; 2287 struct device *device = &dev->pdev->dev; 2288 2289 assert_rpm_wakelock_held(dev_priv); 2290 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) 2291 atomic_inc(&dev_priv->pm.atomic_seq); 2292 2293 pm_runtime_mark_last_busy(device); 2294 pm_runtime_put_autosuspend(device); 2295 } 2296 2297 /** 2298 * intel_runtime_pm_enable - enable runtime pm 2299 * @dev_priv: i915 device instance 2300 * 2301 * This function enables runtime pm at the end of the driver load sequence. 2302 * 2303 * Note that this function does currently not enable runtime pm for the 2304 * subordinate display power domains. That is only done on the first modeset 2305 * using intel_display_set_init_power(). 2306 */ 2307 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2308 { 2309 struct drm_device *dev = dev_priv->dev; 2310 struct device *device = &dev->pdev->dev; 2311 2312 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2313 pm_runtime_mark_last_busy(device); 2314 2315 /* 2316 * Take a permanent reference to disable the RPM functionality and drop 2317 * it only when unloading the driver. Use the low level get/put helpers, 2318 * so the driver's own RPM reference tracking asserts also work on 2319 * platforms without RPM support. 2320 */ 2321 if (!HAS_RUNTIME_PM(dev)) { 2322 pm_runtime_dont_use_autosuspend(device); 2323 pm_runtime_get_sync(device); 2324 } else { 2325 pm_runtime_use_autosuspend(device); 2326 } 2327 2328 /* 2329 * The core calls the driver load handler with an RPM reference held. 2330 * We drop that here and will reacquire it during unloading in 2331 * intel_power_domains_fini(). 2332 */ 2333 pm_runtime_put_autosuspend(device); 2334 } 2335 2336