1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 #define GEN9_ENABLE_DC5(dev) 0 53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) 54 55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 56 for (i = 0; \ 57 i < (power_domains)->power_well_count && \ 58 ((power_well) = &(power_domains)->power_wells[i]); \ 59 i++) \ 60 if ((power_well)->domains & (domain_mask)) 61 62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 63 for (i = (power_domains)->power_well_count - 1; \ 64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 65 i--) \ 66 if ((power_well)->domains & (domain_mask)) 67 68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 69 int power_well_id); 70 71 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 72 struct i915_power_well *power_well) 73 { 74 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 75 power_well->ops->enable(dev_priv, power_well); 76 power_well->hw_enabled = true; 77 } 78 79 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 80 struct i915_power_well *power_well) 81 { 82 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 83 power_well->hw_enabled = false; 84 power_well->ops->disable(dev_priv, power_well); 85 } 86 87 /* 88 * We should only use the power well if we explicitly asked the hardware to 89 * enable it, so check if it's enabled and also check if we've requested it to 90 * be enabled. 91 */ 92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 93 struct i915_power_well *power_well) 94 { 95 return I915_READ(HSW_PWR_WELL_DRIVER) == 96 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 97 } 98 99 /** 100 * __intel_display_power_is_enabled - unlocked check for a power domain 101 * @dev_priv: i915 device instance 102 * @domain: power domain to check 103 * 104 * This is the unlocked version of intel_display_power_is_enabled() and should 105 * only be used from error capture and recovery code where deadlocks are 106 * possible. 107 * 108 * Returns: 109 * True when the power domain is enabled, false otherwise. 110 */ 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 112 enum intel_display_power_domain domain) 113 { 114 struct i915_power_domains *power_domains; 115 struct i915_power_well *power_well; 116 bool is_enabled; 117 int i; 118 119 if (dev_priv->pm.suspended) 120 return false; 121 122 power_domains = &dev_priv->power_domains; 123 124 is_enabled = true; 125 126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 127 if (power_well->always_on) 128 continue; 129 130 if (!power_well->hw_enabled) { 131 is_enabled = false; 132 break; 133 } 134 } 135 136 return is_enabled; 137 } 138 139 /** 140 * intel_display_power_is_enabled - check for a power domain 141 * @dev_priv: i915 device instance 142 * @domain: power domain to check 143 * 144 * This function can be used to check the hw power domain state. It is mostly 145 * used in hardware state readout functions. Everywhere else code should rely 146 * upon explicit power domain reference counting to ensure that the hardware 147 * block is powered up before accessing it. 148 * 149 * Callers must hold the relevant modesetting locks to ensure that concurrent 150 * threads can't disable the power well while the caller tries to read a few 151 * registers. 152 * 153 * Returns: 154 * True when the power domain is enabled, false otherwise. 155 */ 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 157 enum intel_display_power_domain domain) 158 { 159 struct i915_power_domains *power_domains; 160 bool ret; 161 162 power_domains = &dev_priv->power_domains; 163 164 mutex_lock(&power_domains->lock); 165 ret = __intel_display_power_is_enabled(dev_priv, domain); 166 mutex_unlock(&power_domains->lock); 167 168 return ret; 169 } 170 171 /** 172 * intel_display_set_init_power - set the initial power domain state 173 * @dev_priv: i915 device instance 174 * @enable: whether to enable or disable the initial power domain state 175 * 176 * For simplicity our driver load/unload and system suspend/resume code assumes 177 * that all power domains are always enabled. This functions controls the state 178 * of this little hack. While the initial power domain state is enabled runtime 179 * pm is effectively disabled. 180 */ 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 182 bool enable) 183 { 184 if (dev_priv->power_domains.init_power_on == enable) 185 return; 186 187 if (enable) 188 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 189 else 190 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 191 192 dev_priv->power_domains.init_power_on = enable; 193 } 194 195 /* 196 * Starting with Haswell, we have a "Power Down Well" that can be turned off 197 * when not needed anymore. We have 4 registers that can request the power well 198 * to be enabled, and it will only be disabled if none of the registers is 199 * requesting it to be enabled. 200 */ 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 202 { 203 struct drm_device *dev = dev_priv->dev; 204 205 /* 206 * After we re-enable the power well, if we touch VGA register 0x3d5 207 * we'll get unclaimed register interrupts. This stops after we write 208 * anything to the VGA MSR register. The vgacon module uses this 209 * register all the time, so if we unbind our driver and, as a 210 * consequence, bind vgacon, we'll get stuck in an infinite loop at 211 * console_unlock(). So make here we touch the VGA MSR register, making 212 * sure vgacon can keep working normally without triggering interrupts 213 * and error messages. 214 */ 215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 216 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 217 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 218 219 if (IS_BROADWELL(dev)) 220 gen8_irq_power_well_post_enable(dev_priv, 221 1 << PIPE_C | 1 << PIPE_B); 222 } 223 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 225 struct i915_power_well *power_well) 226 { 227 struct drm_device *dev = dev_priv->dev; 228 229 /* 230 * After we re-enable the power well, if we touch VGA register 0x3d5 231 * we'll get unclaimed register interrupts. This stops after we write 232 * anything to the VGA MSR register. The vgacon module uses this 233 * register all the time, so if we unbind our driver and, as a 234 * consequence, bind vgacon, we'll get stuck in an infinite loop at 235 * console_unlock(). So make here we touch the VGA MSR register, making 236 * sure vgacon can keep working normally without triggering interrupts 237 * and error messages. 238 */ 239 if (power_well->data == SKL_DISP_PW_2) { 240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 241 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 242 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 243 244 gen8_irq_power_well_post_enable(dev_priv, 245 1 << PIPE_C | 1 << PIPE_B); 246 } 247 248 if (power_well->data == SKL_DISP_PW_1) { 249 if (!dev_priv->power_domains.initializing) 250 intel_prepare_ddi(dev); 251 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); 252 } 253 } 254 255 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 256 struct i915_power_well *power_well, bool enable) 257 { 258 bool is_enabled, enable_requested; 259 uint32_t tmp; 260 261 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 262 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 263 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 264 265 if (enable) { 266 if (!enable_requested) 267 I915_WRITE(HSW_PWR_WELL_DRIVER, 268 HSW_PWR_WELL_ENABLE_REQUEST); 269 270 if (!is_enabled) { 271 DRM_DEBUG_KMS("Enabling power well\n"); 272 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 273 HSW_PWR_WELL_STATE_ENABLED), 20)) 274 DRM_ERROR("Timeout enabling power well\n"); 275 hsw_power_well_post_enable(dev_priv); 276 } 277 278 } else { 279 if (enable_requested) { 280 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 281 POSTING_READ(HSW_PWR_WELL_DRIVER); 282 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 283 } 284 } 285 } 286 287 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 288 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 289 BIT(POWER_DOMAIN_PIPE_B) | \ 290 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 291 BIT(POWER_DOMAIN_PIPE_C) | \ 292 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 293 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 294 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 295 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 296 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 297 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 298 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 299 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 300 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 301 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ 302 BIT(POWER_DOMAIN_AUX_B) | \ 303 BIT(POWER_DOMAIN_AUX_C) | \ 304 BIT(POWER_DOMAIN_AUX_D) | \ 305 BIT(POWER_DOMAIN_AUDIO) | \ 306 BIT(POWER_DOMAIN_VGA) | \ 307 BIT(POWER_DOMAIN_INIT)) 308 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 309 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 310 BIT(POWER_DOMAIN_PLLS) | \ 311 BIT(POWER_DOMAIN_PIPE_A) | \ 312 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 313 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 314 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 315 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 316 BIT(POWER_DOMAIN_AUX_A) | \ 317 BIT(POWER_DOMAIN_INIT)) 318 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 319 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 320 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 321 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ 322 BIT(POWER_DOMAIN_INIT)) 323 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 324 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 325 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 326 BIT(POWER_DOMAIN_INIT)) 327 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 328 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 329 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 330 BIT(POWER_DOMAIN_INIT)) 331 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 332 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 333 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 334 BIT(POWER_DOMAIN_INIT)) 335 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ 336 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 337 BIT(POWER_DOMAIN_PLLS) | \ 338 BIT(POWER_DOMAIN_INIT)) 339 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 340 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 341 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 342 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ 343 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ 344 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ 345 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ 346 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ 347 BIT(POWER_DOMAIN_INIT)) 348 349 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 350 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 351 BIT(POWER_DOMAIN_PIPE_B) | \ 352 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 353 BIT(POWER_DOMAIN_PIPE_C) | \ 354 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 355 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 356 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 357 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 358 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 359 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 360 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 361 BIT(POWER_DOMAIN_AUX_B) | \ 362 BIT(POWER_DOMAIN_AUX_C) | \ 363 BIT(POWER_DOMAIN_AUDIO) | \ 364 BIT(POWER_DOMAIN_VGA) | \ 365 BIT(POWER_DOMAIN_INIT)) 366 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 367 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 368 BIT(POWER_DOMAIN_PIPE_A) | \ 369 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 370 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 371 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 372 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 373 BIT(POWER_DOMAIN_AUX_A) | \ 374 BIT(POWER_DOMAIN_PLLS) | \ 375 BIT(POWER_DOMAIN_INIT)) 376 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 377 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 378 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ 379 BIT(POWER_DOMAIN_INIT)) 380 381 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 382 { 383 struct drm_device *dev = dev_priv->dev; 384 385 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); 386 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 387 "DC9 already programmed to be enabled.\n"); 388 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 389 "DC5 still not disabled to enable DC9.\n"); 390 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 391 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 392 393 /* 394 * TODO: check for the following to verify the conditions to enter DC9 395 * state are satisfied: 396 * 1] Check relevant display engine registers to verify if mode set 397 * disable sequence was followed. 398 * 2] Check if display uninitialize sequence is initialized. 399 */ 400 } 401 402 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 403 { 404 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 405 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 406 "DC9 already programmed to be disabled.\n"); 407 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 408 "DC5 still not disabled.\n"); 409 410 /* 411 * TODO: check for the following to verify DC9 state was indeed 412 * entered before programming to disable it: 413 * 1] Check relevant display engine registers to verify if mode 414 * set disable sequence was followed. 415 * 2] Check if display uninitialize sequence is initialized. 416 */ 417 } 418 419 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 420 { 421 uint32_t val; 422 423 assert_can_enable_dc9(dev_priv); 424 425 DRM_DEBUG_KMS("Enabling DC9\n"); 426 427 val = I915_READ(DC_STATE_EN); 428 val |= DC_STATE_EN_DC9; 429 I915_WRITE(DC_STATE_EN, val); 430 POSTING_READ(DC_STATE_EN); 431 } 432 433 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 434 { 435 uint32_t val; 436 437 assert_can_disable_dc9(dev_priv); 438 439 DRM_DEBUG_KMS("Disabling DC9\n"); 440 441 val = I915_READ(DC_STATE_EN); 442 val &= ~DC_STATE_EN_DC9; 443 I915_WRITE(DC_STATE_EN, val); 444 POSTING_READ(DC_STATE_EN); 445 } 446 447 static void gen9_set_dc_state_debugmask_memory_up( 448 struct drm_i915_private *dev_priv) 449 { 450 uint32_t val; 451 452 /* The below bit doesn't need to be cleared ever afterwards */ 453 val = I915_READ(DC_STATE_DEBUG); 454 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { 455 val |= DC_STATE_DEBUG_MASK_MEMORY_UP; 456 I915_WRITE(DC_STATE_DEBUG, val); 457 POSTING_READ(DC_STATE_DEBUG); 458 } 459 } 460 461 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 462 { 463 struct drm_device *dev = dev_priv->dev; 464 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 465 SKL_DISP_PW_2); 466 467 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); 468 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 469 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 470 471 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 472 "DC5 already programmed to be enabled.\n"); 473 WARN_ONCE(dev_priv->pm.suspended, 474 "DC5 cannot be enabled, if platform is runtime-suspended.\n"); 475 476 assert_csr_loaded(dev_priv); 477 } 478 479 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) 480 { 481 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 482 SKL_DISP_PW_2); 483 /* 484 * During initialization, the firmware may not be loaded yet. 485 * We still want to make sure that the DC enabling flag is cleared. 486 */ 487 if (dev_priv->power_domains.initializing) 488 return; 489 490 WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); 491 WARN_ONCE(dev_priv->pm.suspended, 492 "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); 493 } 494 495 static void gen9_enable_dc5(struct drm_i915_private *dev_priv) 496 { 497 uint32_t val; 498 499 assert_can_enable_dc5(dev_priv); 500 501 DRM_DEBUG_KMS("Enabling DC5\n"); 502 503 gen9_set_dc_state_debugmask_memory_up(dev_priv); 504 505 val = I915_READ(DC_STATE_EN); 506 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; 507 val |= DC_STATE_EN_UPTO_DC5; 508 I915_WRITE(DC_STATE_EN, val); 509 POSTING_READ(DC_STATE_EN); 510 } 511 512 static void gen9_disable_dc5(struct drm_i915_private *dev_priv) 513 { 514 uint32_t val; 515 516 assert_can_disable_dc5(dev_priv); 517 518 DRM_DEBUG_KMS("Disabling DC5\n"); 519 520 val = I915_READ(DC_STATE_EN); 521 val &= ~DC_STATE_EN_UPTO_DC5; 522 I915_WRITE(DC_STATE_EN, val); 523 POSTING_READ(DC_STATE_EN); 524 } 525 526 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 527 { 528 struct drm_device *dev = dev_priv->dev; 529 530 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); 531 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 532 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 533 "Backlight is not disabled.\n"); 534 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 535 "DC6 already programmed to be enabled.\n"); 536 537 assert_csr_loaded(dev_priv); 538 } 539 540 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) 541 { 542 /* 543 * During initialization, the firmware may not be loaded yet. 544 * We still want to make sure that the DC enabling flag is cleared. 545 */ 546 if (dev_priv->power_domains.initializing) 547 return; 548 549 assert_csr_loaded(dev_priv); 550 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 551 "DC6 already programmed to be disabled.\n"); 552 } 553 554 static void skl_enable_dc6(struct drm_i915_private *dev_priv) 555 { 556 uint32_t val; 557 558 assert_can_enable_dc6(dev_priv); 559 560 DRM_DEBUG_KMS("Enabling DC6\n"); 561 562 gen9_set_dc_state_debugmask_memory_up(dev_priv); 563 564 val = I915_READ(DC_STATE_EN); 565 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; 566 val |= DC_STATE_EN_UPTO_DC6; 567 I915_WRITE(DC_STATE_EN, val); 568 POSTING_READ(DC_STATE_EN); 569 } 570 571 static void skl_disable_dc6(struct drm_i915_private *dev_priv) 572 { 573 uint32_t val; 574 575 assert_can_disable_dc6(dev_priv); 576 577 DRM_DEBUG_KMS("Disabling DC6\n"); 578 579 val = I915_READ(DC_STATE_EN); 580 val &= ~DC_STATE_EN_UPTO_DC6; 581 I915_WRITE(DC_STATE_EN, val); 582 POSTING_READ(DC_STATE_EN); 583 } 584 585 static void skl_set_power_well(struct drm_i915_private *dev_priv, 586 struct i915_power_well *power_well, bool enable) 587 { 588 struct drm_device *dev = dev_priv->dev; 589 uint32_t tmp, fuse_status; 590 uint32_t req_mask, state_mask; 591 bool is_enabled, enable_requested, check_fuse_status = false; 592 593 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 594 fuse_status = I915_READ(SKL_FUSE_STATUS); 595 596 switch (power_well->data) { 597 case SKL_DISP_PW_1: 598 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 599 SKL_FUSE_PG0_DIST_STATUS), 1)) { 600 DRM_ERROR("PG0 not enabled\n"); 601 return; 602 } 603 break; 604 case SKL_DISP_PW_2: 605 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 606 DRM_ERROR("PG1 in disabled state\n"); 607 return; 608 } 609 break; 610 case SKL_DISP_PW_DDI_A_E: 611 case SKL_DISP_PW_DDI_B: 612 case SKL_DISP_PW_DDI_C: 613 case SKL_DISP_PW_DDI_D: 614 case SKL_DISP_PW_MISC_IO: 615 break; 616 default: 617 WARN(1, "Unknown power well %lu\n", power_well->data); 618 return; 619 } 620 621 req_mask = SKL_POWER_WELL_REQ(power_well->data); 622 enable_requested = tmp & req_mask; 623 state_mask = SKL_POWER_WELL_STATE(power_well->data); 624 is_enabled = tmp & state_mask; 625 626 if (enable) { 627 if (!enable_requested) { 628 WARN((tmp & state_mask) && 629 !I915_READ(HSW_PWR_WELL_BIOS), 630 "Invalid for power well status to be enabled, unless done by the BIOS, \ 631 when request is to disable!\n"); 632 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && 633 power_well->data == SKL_DISP_PW_2) { 634 if (SKL_ENABLE_DC6(dev)) { 635 skl_disable_dc6(dev_priv); 636 /* 637 * DDI buffer programming unnecessary during driver-load/resume 638 * as it's already done during modeset initialization then. 639 * It's also invalid here as encoder list is still uninitialized. 640 */ 641 if (!dev_priv->power_domains.initializing) 642 intel_prepare_ddi(dev); 643 } else { 644 gen9_disable_dc5(dev_priv); 645 } 646 } 647 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 648 } 649 650 if (!is_enabled) { 651 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 652 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 653 state_mask), 1)) 654 DRM_ERROR("%s enable timeout\n", 655 power_well->name); 656 check_fuse_status = true; 657 } 658 } else { 659 if (enable_requested) { 660 if (IS_SKYLAKE(dev) && 661 (power_well->data == SKL_DISP_PW_1) && 662 (intel_csr_load_status_get(dev_priv) == FW_LOADED)) 663 DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); 664 else { 665 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 666 POSTING_READ(HSW_PWR_WELL_DRIVER); 667 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 668 } 669 670 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && 671 power_well->data == SKL_DISP_PW_2) { 672 enum csr_state state; 673 /* TODO: wait for a completion event or 674 * similar here instead of busy 675 * waiting using wait_for function. 676 */ 677 wait_for((state = intel_csr_load_status_get(dev_priv)) != 678 FW_UNINITIALIZED, 1000); 679 if (state != FW_LOADED) 680 DRM_DEBUG("CSR firmware not ready (%d)\n", 681 state); 682 else 683 if (SKL_ENABLE_DC6(dev)) 684 skl_enable_dc6(dev_priv); 685 else 686 gen9_enable_dc5(dev_priv); 687 } 688 } 689 } 690 691 if (check_fuse_status) { 692 if (power_well->data == SKL_DISP_PW_1) { 693 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 694 SKL_FUSE_PG1_DIST_STATUS), 1)) 695 DRM_ERROR("PG1 distributing status timeout\n"); 696 } else if (power_well->data == SKL_DISP_PW_2) { 697 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 698 SKL_FUSE_PG2_DIST_STATUS), 1)) 699 DRM_ERROR("PG2 distributing status timeout\n"); 700 } 701 } 702 703 if (enable && !is_enabled) 704 skl_power_well_post_enable(dev_priv, power_well); 705 } 706 707 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 708 struct i915_power_well *power_well) 709 { 710 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 711 712 /* 713 * We're taking over the BIOS, so clear any requests made by it since 714 * the driver is in charge now. 715 */ 716 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 717 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 718 } 719 720 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 721 struct i915_power_well *power_well) 722 { 723 hsw_set_power_well(dev_priv, power_well, true); 724 } 725 726 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 727 struct i915_power_well *power_well) 728 { 729 hsw_set_power_well(dev_priv, power_well, false); 730 } 731 732 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 733 struct i915_power_well *power_well) 734 { 735 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 736 SKL_POWER_WELL_STATE(power_well->data); 737 738 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 739 } 740 741 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 742 struct i915_power_well *power_well) 743 { 744 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 745 746 /* Clear any request made by BIOS as driver is taking over */ 747 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 748 } 749 750 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 751 struct i915_power_well *power_well) 752 { 753 skl_set_power_well(dev_priv, power_well, true); 754 } 755 756 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 757 struct i915_power_well *power_well) 758 { 759 skl_set_power_well(dev_priv, power_well, false); 760 } 761 762 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 763 struct i915_power_well *power_well) 764 { 765 } 766 767 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 768 struct i915_power_well *power_well) 769 { 770 return true; 771 } 772 773 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 774 struct i915_power_well *power_well, bool enable) 775 { 776 enum punit_power_well power_well_id = power_well->data; 777 u32 mask; 778 u32 state; 779 u32 ctrl; 780 781 mask = PUNIT_PWRGT_MASK(power_well_id); 782 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 783 PUNIT_PWRGT_PWR_GATE(power_well_id); 784 785 mutex_lock(&dev_priv->rps.hw_lock); 786 787 #define COND \ 788 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 789 790 if (COND) 791 goto out; 792 793 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 794 ctrl &= ~mask; 795 ctrl |= state; 796 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 797 798 if (wait_for(COND, 100)) 799 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 800 state, 801 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 802 803 #undef COND 804 805 out: 806 mutex_unlock(&dev_priv->rps.hw_lock); 807 } 808 809 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 810 struct i915_power_well *power_well) 811 { 812 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 813 } 814 815 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 816 struct i915_power_well *power_well) 817 { 818 vlv_set_power_well(dev_priv, power_well, true); 819 } 820 821 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 822 struct i915_power_well *power_well) 823 { 824 vlv_set_power_well(dev_priv, power_well, false); 825 } 826 827 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 828 struct i915_power_well *power_well) 829 { 830 int power_well_id = power_well->data; 831 bool enabled = false; 832 u32 mask; 833 u32 state; 834 u32 ctrl; 835 836 mask = PUNIT_PWRGT_MASK(power_well_id); 837 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 838 839 mutex_lock(&dev_priv->rps.hw_lock); 840 841 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 842 /* 843 * We only ever set the power-on and power-gate states, anything 844 * else is unexpected. 845 */ 846 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 847 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 848 if (state == ctrl) 849 enabled = true; 850 851 /* 852 * A transient state at this point would mean some unexpected party 853 * is poking at the power controls too. 854 */ 855 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 856 WARN_ON(ctrl != state); 857 858 mutex_unlock(&dev_priv->rps.hw_lock); 859 860 return enabled; 861 } 862 863 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 864 { 865 enum pipe pipe; 866 867 /* 868 * Enable the CRI clock source so we can get at the 869 * display and the reference clock for VGA 870 * hotplug / manual detection. Supposedly DSI also 871 * needs the ref clock up and running. 872 * 873 * CHV DPLL B/C have some issues if VGA mode is enabled. 874 */ 875 for_each_pipe(dev_priv->dev, pipe) { 876 u32 val = I915_READ(DPLL(pipe)); 877 878 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 879 if (pipe != PIPE_A) 880 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 881 882 I915_WRITE(DPLL(pipe), val); 883 } 884 885 spin_lock_irq(&dev_priv->irq_lock); 886 valleyview_enable_display_irqs(dev_priv); 887 spin_unlock_irq(&dev_priv->irq_lock); 888 889 /* 890 * During driver initialization/resume we can avoid restoring the 891 * part of the HW/SW state that will be inited anyway explicitly. 892 */ 893 if (dev_priv->power_domains.initializing) 894 return; 895 896 intel_hpd_init(dev_priv); 897 898 i915_redisable_vga_power_on(dev_priv->dev); 899 } 900 901 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 902 { 903 spin_lock_irq(&dev_priv->irq_lock); 904 valleyview_disable_display_irqs(dev_priv); 905 spin_unlock_irq(&dev_priv->irq_lock); 906 907 vlv_power_sequencer_reset(dev_priv); 908 } 909 910 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 911 struct i915_power_well *power_well) 912 { 913 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 914 915 vlv_set_power_well(dev_priv, power_well, true); 916 917 vlv_display_power_well_init(dev_priv); 918 } 919 920 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 921 struct i915_power_well *power_well) 922 { 923 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 924 925 vlv_display_power_well_deinit(dev_priv); 926 927 vlv_set_power_well(dev_priv, power_well, false); 928 } 929 930 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 931 struct i915_power_well *power_well) 932 { 933 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 934 935 /* since ref/cri clock was enabled */ 936 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 937 938 vlv_set_power_well(dev_priv, power_well, true); 939 940 /* 941 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 942 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 943 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 944 * b. The other bits such as sfr settings / modesel may all 945 * be set to 0. 946 * 947 * This should only be done on init and resume from S3 with 948 * both PLLs disabled, or we risk losing DPIO and PLL 949 * synchronization. 950 */ 951 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 952 } 953 954 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 955 struct i915_power_well *power_well) 956 { 957 enum pipe pipe; 958 959 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 960 961 for_each_pipe(dev_priv, pipe) 962 assert_pll_disabled(dev_priv, pipe); 963 964 /* Assert common reset */ 965 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 966 967 vlv_set_power_well(dev_priv, power_well, false); 968 } 969 970 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 971 972 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 973 int power_well_id) 974 { 975 struct i915_power_domains *power_domains = &dev_priv->power_domains; 976 struct i915_power_well *power_well; 977 int i; 978 979 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 980 if (power_well->data == power_well_id) 981 return power_well; 982 } 983 984 return NULL; 985 } 986 987 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 988 989 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 990 { 991 struct i915_power_well *cmn_bc = 992 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 993 struct i915_power_well *cmn_d = 994 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 995 u32 phy_control = dev_priv->chv_phy_control; 996 u32 phy_status = 0; 997 u32 phy_status_mask = 0xffffffff; 998 u32 tmp; 999 1000 /* 1001 * The BIOS can leave the PHY is some weird state 1002 * where it doesn't fully power down some parts. 1003 * Disable the asserts until the PHY has been fully 1004 * reset (ie. the power well has been disabled at 1005 * least once). 1006 */ 1007 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1008 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1009 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1010 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1011 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1012 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1013 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1014 1015 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1016 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1017 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1018 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1019 1020 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1021 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1022 1023 /* this assumes override is only used to enable lanes */ 1024 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1025 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1026 1027 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1028 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1029 1030 /* CL1 is on whenever anything is on in either channel */ 1031 if (BITS_SET(phy_control, 1032 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1033 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1034 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1035 1036 /* 1037 * The DPLLB check accounts for the pipe B + port A usage 1038 * with CL2 powered up but all the lanes in the second channel 1039 * powered down. 1040 */ 1041 if (BITS_SET(phy_control, 1042 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1043 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1044 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1045 1046 if (BITS_SET(phy_control, 1047 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1048 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1049 if (BITS_SET(phy_control, 1050 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1051 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1052 1053 if (BITS_SET(phy_control, 1054 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1055 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1056 if (BITS_SET(phy_control, 1057 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1058 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1059 } 1060 1061 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1062 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1063 1064 /* this assumes override is only used to enable lanes */ 1065 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1066 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1067 1068 if (BITS_SET(phy_control, 1069 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1070 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1071 1072 if (BITS_SET(phy_control, 1073 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1074 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1075 if (BITS_SET(phy_control, 1076 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1077 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1078 } 1079 1080 phy_status &= phy_status_mask; 1081 1082 /* 1083 * The PHY may be busy with some initial calibration and whatnot, 1084 * so the power state can take a while to actually change. 1085 */ 1086 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) 1087 WARN(phy_status != tmp, 1088 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1089 tmp, phy_status, dev_priv->chv_phy_control); 1090 } 1091 1092 #undef BITS_SET 1093 1094 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1095 struct i915_power_well *power_well) 1096 { 1097 enum dpio_phy phy; 1098 enum pipe pipe; 1099 uint32_t tmp; 1100 1101 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1102 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1103 1104 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1105 pipe = PIPE_A; 1106 phy = DPIO_PHY0; 1107 } else { 1108 pipe = PIPE_C; 1109 phy = DPIO_PHY1; 1110 } 1111 1112 /* since ref/cri clock was enabled */ 1113 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1114 vlv_set_power_well(dev_priv, power_well, true); 1115 1116 /* Poll for phypwrgood signal */ 1117 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 1118 DRM_ERROR("Display PHY %d is not power up\n", phy); 1119 1120 mutex_lock(&dev_priv->sb_lock); 1121 1122 /* Enable dynamic power down */ 1123 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1124 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1125 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1126 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1127 1128 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1129 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1130 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1131 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1132 } else { 1133 /* 1134 * Force the non-existing CL2 off. BXT does this 1135 * too, so maybe it saves some power even though 1136 * CL2 doesn't exist? 1137 */ 1138 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1139 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1140 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1141 } 1142 1143 mutex_unlock(&dev_priv->sb_lock); 1144 1145 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1146 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1147 1148 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1149 phy, dev_priv->chv_phy_control); 1150 1151 assert_chv_phy_status(dev_priv); 1152 } 1153 1154 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1155 struct i915_power_well *power_well) 1156 { 1157 enum dpio_phy phy; 1158 1159 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1160 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1161 1162 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1163 phy = DPIO_PHY0; 1164 assert_pll_disabled(dev_priv, PIPE_A); 1165 assert_pll_disabled(dev_priv, PIPE_B); 1166 } else { 1167 phy = DPIO_PHY1; 1168 assert_pll_disabled(dev_priv, PIPE_C); 1169 } 1170 1171 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1172 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1173 1174 vlv_set_power_well(dev_priv, power_well, false); 1175 1176 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1177 phy, dev_priv->chv_phy_control); 1178 1179 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1180 dev_priv->chv_phy_assert[phy] = true; 1181 1182 assert_chv_phy_status(dev_priv); 1183 } 1184 1185 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1186 enum dpio_channel ch, bool override, unsigned int mask) 1187 { 1188 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1189 u32 reg, val, expected, actual; 1190 1191 /* 1192 * The BIOS can leave the PHY is some weird state 1193 * where it doesn't fully power down some parts. 1194 * Disable the asserts until the PHY has been fully 1195 * reset (ie. the power well has been disabled at 1196 * least once). 1197 */ 1198 if (!dev_priv->chv_phy_assert[phy]) 1199 return; 1200 1201 if (ch == DPIO_CH0) 1202 reg = _CHV_CMN_DW0_CH0; 1203 else 1204 reg = _CHV_CMN_DW6_CH1; 1205 1206 mutex_lock(&dev_priv->sb_lock); 1207 val = vlv_dpio_read(dev_priv, pipe, reg); 1208 mutex_unlock(&dev_priv->sb_lock); 1209 1210 /* 1211 * This assumes !override is only used when the port is disabled. 1212 * All lanes should power down even without the override when 1213 * the port is disabled. 1214 */ 1215 if (!override || mask == 0xf) { 1216 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1217 /* 1218 * If CH1 common lane is not active anymore 1219 * (eg. for pipe B DPLL) the entire channel will 1220 * shut down, which causes the common lane registers 1221 * to read as 0. That means we can't actually check 1222 * the lane power down status bits, but as the entire 1223 * register reads as 0 it's a good indication that the 1224 * channel is indeed entirely powered down. 1225 */ 1226 if (ch == DPIO_CH1 && val == 0) 1227 expected = 0; 1228 } else if (mask != 0x0) { 1229 expected = DPIO_ANYDL_POWERDOWN; 1230 } else { 1231 expected = 0; 1232 } 1233 1234 if (ch == DPIO_CH0) 1235 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1236 else 1237 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1238 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1239 1240 WARN(actual != expected, 1241 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1242 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1243 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1244 reg, val); 1245 } 1246 1247 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1248 enum dpio_channel ch, bool override) 1249 { 1250 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1251 bool was_override; 1252 1253 mutex_lock(&power_domains->lock); 1254 1255 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1256 1257 if (override == was_override) 1258 goto out; 1259 1260 if (override) 1261 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1262 else 1263 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1264 1265 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1266 1267 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1268 phy, ch, dev_priv->chv_phy_control); 1269 1270 assert_chv_phy_status(dev_priv); 1271 1272 out: 1273 mutex_unlock(&power_domains->lock); 1274 1275 return was_override; 1276 } 1277 1278 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1279 bool override, unsigned int mask) 1280 { 1281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1282 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1283 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1284 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1285 1286 mutex_lock(&power_domains->lock); 1287 1288 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1289 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1290 1291 if (override) 1292 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1293 else 1294 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1295 1296 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1297 1298 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1299 phy, ch, mask, dev_priv->chv_phy_control); 1300 1301 assert_chv_phy_status(dev_priv); 1302 1303 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1304 1305 mutex_unlock(&power_domains->lock); 1306 } 1307 1308 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1309 struct i915_power_well *power_well) 1310 { 1311 enum pipe pipe = power_well->data; 1312 bool enabled; 1313 u32 state, ctrl; 1314 1315 mutex_lock(&dev_priv->rps.hw_lock); 1316 1317 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1318 /* 1319 * We only ever set the power-on and power-gate states, anything 1320 * else is unexpected. 1321 */ 1322 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1323 enabled = state == DP_SSS_PWR_ON(pipe); 1324 1325 /* 1326 * A transient state at this point would mean some unexpected party 1327 * is poking at the power controls too. 1328 */ 1329 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1330 WARN_ON(ctrl << 16 != state); 1331 1332 mutex_unlock(&dev_priv->rps.hw_lock); 1333 1334 return enabled; 1335 } 1336 1337 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1338 struct i915_power_well *power_well, 1339 bool enable) 1340 { 1341 enum pipe pipe = power_well->data; 1342 u32 state; 1343 u32 ctrl; 1344 1345 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1346 1347 mutex_lock(&dev_priv->rps.hw_lock); 1348 1349 #define COND \ 1350 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1351 1352 if (COND) 1353 goto out; 1354 1355 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1356 ctrl &= ~DP_SSC_MASK(pipe); 1357 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1358 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1359 1360 if (wait_for(COND, 100)) 1361 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1362 state, 1363 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1364 1365 #undef COND 1366 1367 out: 1368 mutex_unlock(&dev_priv->rps.hw_lock); 1369 } 1370 1371 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1372 struct i915_power_well *power_well) 1373 { 1374 WARN_ON_ONCE(power_well->data != PIPE_A); 1375 1376 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1377 } 1378 1379 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1380 struct i915_power_well *power_well) 1381 { 1382 WARN_ON_ONCE(power_well->data != PIPE_A); 1383 1384 chv_set_pipe_power_well(dev_priv, power_well, true); 1385 1386 vlv_display_power_well_init(dev_priv); 1387 } 1388 1389 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1390 struct i915_power_well *power_well) 1391 { 1392 WARN_ON_ONCE(power_well->data != PIPE_A); 1393 1394 vlv_display_power_well_deinit(dev_priv); 1395 1396 chv_set_pipe_power_well(dev_priv, power_well, false); 1397 } 1398 1399 /** 1400 * intel_display_power_get - grab a power domain reference 1401 * @dev_priv: i915 device instance 1402 * @domain: power domain to reference 1403 * 1404 * This function grabs a power domain reference for @domain and ensures that the 1405 * power domain and all its parents are powered up. Therefore users should only 1406 * grab a reference to the innermost power domain they need. 1407 * 1408 * Any power domain reference obtained by this function must have a symmetric 1409 * call to intel_display_power_put() to release the reference again. 1410 */ 1411 void intel_display_power_get(struct drm_i915_private *dev_priv, 1412 enum intel_display_power_domain domain) 1413 { 1414 struct i915_power_domains *power_domains; 1415 struct i915_power_well *power_well; 1416 int i; 1417 1418 intel_runtime_pm_get(dev_priv); 1419 1420 power_domains = &dev_priv->power_domains; 1421 1422 mutex_lock(&power_domains->lock); 1423 1424 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1425 if (!power_well->count++) 1426 intel_power_well_enable(dev_priv, power_well); 1427 } 1428 1429 power_domains->domain_use_count[domain]++; 1430 1431 mutex_unlock(&power_domains->lock); 1432 } 1433 1434 /** 1435 * intel_display_power_put - release a power domain reference 1436 * @dev_priv: i915 device instance 1437 * @domain: power domain to reference 1438 * 1439 * This function drops the power domain reference obtained by 1440 * intel_display_power_get() and might power down the corresponding hardware 1441 * block right away if this is the last reference. 1442 */ 1443 void intel_display_power_put(struct drm_i915_private *dev_priv, 1444 enum intel_display_power_domain domain) 1445 { 1446 struct i915_power_domains *power_domains; 1447 struct i915_power_well *power_well; 1448 int i; 1449 1450 power_domains = &dev_priv->power_domains; 1451 1452 mutex_lock(&power_domains->lock); 1453 1454 WARN_ON(!power_domains->domain_use_count[domain]); 1455 power_domains->domain_use_count[domain]--; 1456 1457 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1458 WARN_ON(!power_well->count); 1459 1460 if (!--power_well->count && i915.disable_power_well) 1461 intel_power_well_disable(dev_priv, power_well); 1462 } 1463 1464 mutex_unlock(&power_domains->lock); 1465 1466 intel_runtime_pm_put(dev_priv); 1467 } 1468 1469 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1470 BIT(POWER_DOMAIN_PIPE_A) | \ 1471 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1472 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 1473 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 1474 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1475 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1476 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1477 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1478 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 1479 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 1480 BIT(POWER_DOMAIN_PORT_CRT) | \ 1481 BIT(POWER_DOMAIN_PLLS) | \ 1482 BIT(POWER_DOMAIN_AUX_A) | \ 1483 BIT(POWER_DOMAIN_AUX_B) | \ 1484 BIT(POWER_DOMAIN_AUX_C) | \ 1485 BIT(POWER_DOMAIN_AUX_D) | \ 1486 BIT(POWER_DOMAIN_INIT)) 1487 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1488 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 1489 BIT(POWER_DOMAIN_INIT)) 1490 1491 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1492 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1493 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1494 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1495 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1496 BIT(POWER_DOMAIN_INIT)) 1497 1498 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 1499 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 1500 1501 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1502 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1503 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1504 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1505 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1506 BIT(POWER_DOMAIN_PORT_CRT) | \ 1507 BIT(POWER_DOMAIN_AUX_B) | \ 1508 BIT(POWER_DOMAIN_AUX_C) | \ 1509 BIT(POWER_DOMAIN_INIT)) 1510 1511 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1512 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1513 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1514 BIT(POWER_DOMAIN_AUX_B) | \ 1515 BIT(POWER_DOMAIN_INIT)) 1516 1517 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1518 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1519 BIT(POWER_DOMAIN_AUX_B) | \ 1520 BIT(POWER_DOMAIN_INIT)) 1521 1522 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1523 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1524 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1525 BIT(POWER_DOMAIN_AUX_C) | \ 1526 BIT(POWER_DOMAIN_INIT)) 1527 1528 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1529 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1530 BIT(POWER_DOMAIN_AUX_C) | \ 1531 BIT(POWER_DOMAIN_INIT)) 1532 1533 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1534 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1535 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1536 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1537 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1538 BIT(POWER_DOMAIN_AUX_B) | \ 1539 BIT(POWER_DOMAIN_AUX_C) | \ 1540 BIT(POWER_DOMAIN_INIT)) 1541 1542 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1543 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 1544 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 1545 BIT(POWER_DOMAIN_AUX_D) | \ 1546 BIT(POWER_DOMAIN_INIT)) 1547 1548 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1549 .sync_hw = i9xx_always_on_power_well_noop, 1550 .enable = i9xx_always_on_power_well_noop, 1551 .disable = i9xx_always_on_power_well_noop, 1552 .is_enabled = i9xx_always_on_power_well_enabled, 1553 }; 1554 1555 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1556 .sync_hw = chv_pipe_power_well_sync_hw, 1557 .enable = chv_pipe_power_well_enable, 1558 .disable = chv_pipe_power_well_disable, 1559 .is_enabled = chv_pipe_power_well_enabled, 1560 }; 1561 1562 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1563 .sync_hw = vlv_power_well_sync_hw, 1564 .enable = chv_dpio_cmn_power_well_enable, 1565 .disable = chv_dpio_cmn_power_well_disable, 1566 .is_enabled = vlv_power_well_enabled, 1567 }; 1568 1569 static struct i915_power_well i9xx_always_on_power_well[] = { 1570 { 1571 .name = "always-on", 1572 .always_on = 1, 1573 .domains = POWER_DOMAIN_MASK, 1574 .ops = &i9xx_always_on_power_well_ops, 1575 }, 1576 }; 1577 1578 static const struct i915_power_well_ops hsw_power_well_ops = { 1579 .sync_hw = hsw_power_well_sync_hw, 1580 .enable = hsw_power_well_enable, 1581 .disable = hsw_power_well_disable, 1582 .is_enabled = hsw_power_well_enabled, 1583 }; 1584 1585 static const struct i915_power_well_ops skl_power_well_ops = { 1586 .sync_hw = skl_power_well_sync_hw, 1587 .enable = skl_power_well_enable, 1588 .disable = skl_power_well_disable, 1589 .is_enabled = skl_power_well_enabled, 1590 }; 1591 1592 static struct i915_power_well hsw_power_wells[] = { 1593 { 1594 .name = "always-on", 1595 .always_on = 1, 1596 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 1597 .ops = &i9xx_always_on_power_well_ops, 1598 }, 1599 { 1600 .name = "display", 1601 .domains = HSW_DISPLAY_POWER_DOMAINS, 1602 .ops = &hsw_power_well_ops, 1603 }, 1604 }; 1605 1606 static struct i915_power_well bdw_power_wells[] = { 1607 { 1608 .name = "always-on", 1609 .always_on = 1, 1610 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 1611 .ops = &i9xx_always_on_power_well_ops, 1612 }, 1613 { 1614 .name = "display", 1615 .domains = BDW_DISPLAY_POWER_DOMAINS, 1616 .ops = &hsw_power_well_ops, 1617 }, 1618 }; 1619 1620 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1621 .sync_hw = vlv_power_well_sync_hw, 1622 .enable = vlv_display_power_well_enable, 1623 .disable = vlv_display_power_well_disable, 1624 .is_enabled = vlv_power_well_enabled, 1625 }; 1626 1627 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1628 .sync_hw = vlv_power_well_sync_hw, 1629 .enable = vlv_dpio_cmn_power_well_enable, 1630 .disable = vlv_dpio_cmn_power_well_disable, 1631 .is_enabled = vlv_power_well_enabled, 1632 }; 1633 1634 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1635 .sync_hw = vlv_power_well_sync_hw, 1636 .enable = vlv_power_well_enable, 1637 .disable = vlv_power_well_disable, 1638 .is_enabled = vlv_power_well_enabled, 1639 }; 1640 1641 static struct i915_power_well vlv_power_wells[] = { 1642 { 1643 .name = "always-on", 1644 .always_on = 1, 1645 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1646 .ops = &i9xx_always_on_power_well_ops, 1647 }, 1648 { 1649 .name = "display", 1650 .domains = VLV_DISPLAY_POWER_DOMAINS, 1651 .data = PUNIT_POWER_WELL_DISP2D, 1652 .ops = &vlv_display_power_well_ops, 1653 }, 1654 { 1655 .name = "dpio-tx-b-01", 1656 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1657 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1658 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1659 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1660 .ops = &vlv_dpio_power_well_ops, 1661 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1662 }, 1663 { 1664 .name = "dpio-tx-b-23", 1665 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1666 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1667 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1668 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1669 .ops = &vlv_dpio_power_well_ops, 1670 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1671 }, 1672 { 1673 .name = "dpio-tx-c-01", 1674 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1675 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1676 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1677 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1678 .ops = &vlv_dpio_power_well_ops, 1679 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1680 }, 1681 { 1682 .name = "dpio-tx-c-23", 1683 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1684 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1685 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1686 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1687 .ops = &vlv_dpio_power_well_ops, 1688 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1689 }, 1690 { 1691 .name = "dpio-common", 1692 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1693 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1694 .ops = &vlv_dpio_cmn_power_well_ops, 1695 }, 1696 }; 1697 1698 static struct i915_power_well chv_power_wells[] = { 1699 { 1700 .name = "always-on", 1701 .always_on = 1, 1702 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1703 .ops = &i9xx_always_on_power_well_ops, 1704 }, 1705 { 1706 .name = "display", 1707 /* 1708 * Pipe A power well is the new disp2d well. Pipe B and C 1709 * power wells don't actually exist. Pipe A power well is 1710 * required for any pipe to work. 1711 */ 1712 .domains = VLV_DISPLAY_POWER_DOMAINS, 1713 .data = PIPE_A, 1714 .ops = &chv_pipe_power_well_ops, 1715 }, 1716 { 1717 .name = "dpio-common-bc", 1718 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1719 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1720 .ops = &chv_dpio_cmn_power_well_ops, 1721 }, 1722 { 1723 .name = "dpio-common-d", 1724 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1725 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1726 .ops = &chv_dpio_cmn_power_well_ops, 1727 }, 1728 }; 1729 1730 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1731 int power_well_id) 1732 { 1733 struct i915_power_well *power_well; 1734 bool ret; 1735 1736 power_well = lookup_power_well(dev_priv, power_well_id); 1737 ret = power_well->ops->is_enabled(dev_priv, power_well); 1738 1739 return ret; 1740 } 1741 1742 static struct i915_power_well skl_power_wells[] = { 1743 { 1744 .name = "always-on", 1745 .always_on = 1, 1746 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1747 .ops = &i9xx_always_on_power_well_ops, 1748 }, 1749 { 1750 .name = "power well 1", 1751 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1752 .ops = &skl_power_well_ops, 1753 .data = SKL_DISP_PW_1, 1754 }, 1755 { 1756 .name = "MISC IO power well", 1757 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, 1758 .ops = &skl_power_well_ops, 1759 .data = SKL_DISP_PW_MISC_IO, 1760 }, 1761 { 1762 .name = "power well 2", 1763 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1764 .ops = &skl_power_well_ops, 1765 .data = SKL_DISP_PW_2, 1766 }, 1767 { 1768 .name = "DDI A/E power well", 1769 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1770 .ops = &skl_power_well_ops, 1771 .data = SKL_DISP_PW_DDI_A_E, 1772 }, 1773 { 1774 .name = "DDI B power well", 1775 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1776 .ops = &skl_power_well_ops, 1777 .data = SKL_DISP_PW_DDI_B, 1778 }, 1779 { 1780 .name = "DDI C power well", 1781 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1782 .ops = &skl_power_well_ops, 1783 .data = SKL_DISP_PW_DDI_C, 1784 }, 1785 { 1786 .name = "DDI D power well", 1787 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1788 .ops = &skl_power_well_ops, 1789 .data = SKL_DISP_PW_DDI_D, 1790 }, 1791 }; 1792 1793 static struct i915_power_well bxt_power_wells[] = { 1794 { 1795 .name = "always-on", 1796 .always_on = 1, 1797 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1798 .ops = &i9xx_always_on_power_well_ops, 1799 }, 1800 { 1801 .name = "power well 1", 1802 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1803 .ops = &skl_power_well_ops, 1804 .data = SKL_DISP_PW_1, 1805 }, 1806 { 1807 .name = "power well 2", 1808 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1809 .ops = &skl_power_well_ops, 1810 .data = SKL_DISP_PW_2, 1811 } 1812 }; 1813 1814 static int 1815 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 1816 int disable_power_well) 1817 { 1818 if (disable_power_well >= 0) 1819 return !!disable_power_well; 1820 1821 if (IS_SKYLAKE(dev_priv)) { 1822 DRM_DEBUG_KMS("Disabling display power well support\n"); 1823 return 0; 1824 } 1825 1826 return 1; 1827 } 1828 1829 #define set_power_wells(power_domains, __power_wells) ({ \ 1830 (power_domains)->power_wells = (__power_wells); \ 1831 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 1832 }) 1833 1834 /** 1835 * intel_power_domains_init - initializes the power domain structures 1836 * @dev_priv: i915 device instance 1837 * 1838 * Initializes the power domain structures for @dev_priv depending upon the 1839 * supported platform. 1840 */ 1841 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1842 { 1843 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1844 1845 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 1846 i915.disable_power_well); 1847 1848 mutex_init(&power_domains->lock); 1849 1850 /* 1851 * The enabling order will be from lower to higher indexed wells, 1852 * the disabling order is reversed. 1853 */ 1854 if (IS_HASWELL(dev_priv->dev)) { 1855 set_power_wells(power_domains, hsw_power_wells); 1856 } else if (IS_BROADWELL(dev_priv->dev)) { 1857 set_power_wells(power_domains, bdw_power_wells); 1858 } else if (IS_SKYLAKE(dev_priv->dev)) { 1859 set_power_wells(power_domains, skl_power_wells); 1860 } else if (IS_BROXTON(dev_priv->dev)) { 1861 set_power_wells(power_domains, bxt_power_wells); 1862 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1863 set_power_wells(power_domains, chv_power_wells); 1864 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 1865 set_power_wells(power_domains, vlv_power_wells); 1866 } else { 1867 set_power_wells(power_domains, i9xx_always_on_power_well); 1868 } 1869 1870 return 0; 1871 } 1872 1873 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) 1874 { 1875 struct drm_device *dev = dev_priv->dev; 1876 struct device *device = &dev->pdev->dev; 1877 1878 if (!HAS_RUNTIME_PM(dev)) 1879 return; 1880 1881 if (!intel_enable_rc6(dev)) 1882 return; 1883 1884 /* Make sure we're not suspended first. */ 1885 pm_runtime_get_sync(device); 1886 } 1887 1888 /** 1889 * intel_power_domains_fini - finalizes the power domain structures 1890 * @dev_priv: i915 device instance 1891 * 1892 * Finalizes the power domain structures for @dev_priv depending upon the 1893 * supported platform. This function also disables runtime pm and ensures that 1894 * the device stays powered up so that the driver can be reloaded. 1895 */ 1896 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 1897 { 1898 intel_runtime_pm_disable(dev_priv); 1899 1900 /* The i915.ko module is still not prepared to be loaded when 1901 * the power well is not enabled, so just enable it in case 1902 * we're going to unload/reload. */ 1903 intel_display_set_init_power(dev_priv, true); 1904 } 1905 1906 static void intel_power_domains_resume(struct drm_i915_private *dev_priv) 1907 { 1908 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1909 struct i915_power_well *power_well; 1910 int i; 1911 1912 mutex_lock(&power_domains->lock); 1913 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1914 power_well->ops->sync_hw(dev_priv, power_well); 1915 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 1916 power_well); 1917 } 1918 mutex_unlock(&power_domains->lock); 1919 } 1920 1921 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1922 { 1923 struct i915_power_well *cmn_bc = 1924 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1925 struct i915_power_well *cmn_d = 1926 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1927 1928 /* 1929 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1930 * workaround never ever read DISPLAY_PHY_CONTROL, and 1931 * instead maintain a shadow copy ourselves. Use the actual 1932 * power well state and lane status to reconstruct the 1933 * expected initial value. 1934 */ 1935 dev_priv->chv_phy_control = 1936 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1937 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1938 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 1939 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 1940 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 1941 1942 /* 1943 * If all lanes are disabled we leave the override disabled 1944 * with all power down bits cleared to match the state we 1945 * would use after disabling the port. Otherwise enable the 1946 * override and set the lane powerdown bits accding to the 1947 * current lane status. 1948 */ 1949 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1950 uint32_t status = I915_READ(DPLL(PIPE_A)); 1951 unsigned int mask; 1952 1953 mask = status & DPLL_PORTB_READY_MASK; 1954 if (mask == 0xf) 1955 mask = 0x0; 1956 else 1957 dev_priv->chv_phy_control |= 1958 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1959 1960 dev_priv->chv_phy_control |= 1961 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1962 1963 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1964 if (mask == 0xf) 1965 mask = 0x0; 1966 else 1967 dev_priv->chv_phy_control |= 1968 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1969 1970 dev_priv->chv_phy_control |= 1971 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1972 1973 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1974 1975 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 1976 } else { 1977 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 1978 } 1979 1980 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1981 uint32_t status = I915_READ(DPIO_PHY_STATUS); 1982 unsigned int mask; 1983 1984 mask = status & DPLL_PORTD_READY_MASK; 1985 1986 if (mask == 0xf) 1987 mask = 0x0; 1988 else 1989 dev_priv->chv_phy_control |= 1990 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1991 1992 dev_priv->chv_phy_control |= 1993 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1994 1995 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1996 1997 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 1998 } else { 1999 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2000 } 2001 2002 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2003 2004 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2005 dev_priv->chv_phy_control); 2006 } 2007 2008 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2009 { 2010 struct i915_power_well *cmn = 2011 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2012 struct i915_power_well *disp2d = 2013 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2014 2015 /* If the display might be already active skip this */ 2016 if (cmn->ops->is_enabled(dev_priv, cmn) && 2017 disp2d->ops->is_enabled(dev_priv, disp2d) && 2018 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2019 return; 2020 2021 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2022 2023 /* cmnlane needs DPLL registers */ 2024 disp2d->ops->enable(dev_priv, disp2d); 2025 2026 /* 2027 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2028 * Need to assert and de-assert PHY SB reset by gating the 2029 * common lane power, then un-gating it. 2030 * Simply ungating isn't enough to reset the PHY enough to get 2031 * ports and lanes running. 2032 */ 2033 cmn->ops->disable(dev_priv, cmn); 2034 } 2035 2036 /** 2037 * intel_power_domains_init_hw - initialize hardware power domain state 2038 * @dev_priv: i915 device instance 2039 * 2040 * This function initializes the hardware power domain state and enables all 2041 * power domains using intel_display_set_init_power(). 2042 */ 2043 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) 2044 { 2045 struct drm_device *dev = dev_priv->dev; 2046 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2047 2048 power_domains->initializing = true; 2049 2050 if (IS_CHERRYVIEW(dev)) { 2051 mutex_lock(&power_domains->lock); 2052 chv_phy_control_init(dev_priv); 2053 mutex_unlock(&power_domains->lock); 2054 } else if (IS_VALLEYVIEW(dev)) { 2055 mutex_lock(&power_domains->lock); 2056 vlv_cmnlane_wa(dev_priv); 2057 mutex_unlock(&power_domains->lock); 2058 } 2059 2060 /* For now, we need the power well to be always enabled. */ 2061 intel_display_set_init_power(dev_priv, true); 2062 intel_power_domains_resume(dev_priv); 2063 power_domains->initializing = false; 2064 } 2065 2066 /** 2067 * intel_aux_display_runtime_get - grab an auxiliary power domain reference 2068 * @dev_priv: i915 device instance 2069 * 2070 * This function grabs a power domain reference for the auxiliary power domain 2071 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its 2072 * parents are powered up. Therefore users should only grab a reference to the 2073 * innermost power domain they need. 2074 * 2075 * Any power domain reference obtained by this function must have a symmetric 2076 * call to intel_aux_display_runtime_put() to release the reference again. 2077 */ 2078 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 2079 { 2080 intel_runtime_pm_get(dev_priv); 2081 } 2082 2083 /** 2084 * intel_aux_display_runtime_put - release an auxiliary power domain reference 2085 * @dev_priv: i915 device instance 2086 * 2087 * This function drops the auxiliary power domain reference obtained by 2088 * intel_aux_display_runtime_get() and might power down the corresponding 2089 * hardware block right away if this is the last reference. 2090 */ 2091 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 2092 { 2093 intel_runtime_pm_put(dev_priv); 2094 } 2095 2096 /** 2097 * intel_runtime_pm_get - grab a runtime pm reference 2098 * @dev_priv: i915 device instance 2099 * 2100 * This function grabs a device-level runtime pm reference (mostly used for GEM 2101 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2102 * 2103 * Any runtime pm reference obtained by this function must have a symmetric 2104 * call to intel_runtime_pm_put() to release the reference again. 2105 */ 2106 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2107 { 2108 struct drm_device *dev = dev_priv->dev; 2109 struct device *device = &dev->pdev->dev; 2110 2111 if (!HAS_RUNTIME_PM(dev)) 2112 return; 2113 2114 pm_runtime_get_sync(device); 2115 WARN(dev_priv->pm.suspended, "Device still suspended.\n"); 2116 } 2117 2118 /** 2119 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2120 * @dev_priv: i915 device instance 2121 * 2122 * This function grabs a device-level runtime pm reference (mostly used for GEM 2123 * code to ensure the GTT or GT is on). 2124 * 2125 * It will _not_ power up the device but instead only check that it's powered 2126 * on. Therefore it is only valid to call this functions from contexts where 2127 * the device is known to be powered up and where trying to power it up would 2128 * result in hilarity and deadlocks. That pretty much means only the system 2129 * suspend/resume code where this is used to grab runtime pm references for 2130 * delayed setup down in work items. 2131 * 2132 * Any runtime pm reference obtained by this function must have a symmetric 2133 * call to intel_runtime_pm_put() to release the reference again. 2134 */ 2135 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2136 { 2137 struct drm_device *dev = dev_priv->dev; 2138 struct device *device = &dev->pdev->dev; 2139 2140 if (!HAS_RUNTIME_PM(dev)) 2141 return; 2142 2143 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); 2144 pm_runtime_get_noresume(device); 2145 } 2146 2147 /** 2148 * intel_runtime_pm_put - release a runtime pm reference 2149 * @dev_priv: i915 device instance 2150 * 2151 * This function drops the device-level runtime pm reference obtained by 2152 * intel_runtime_pm_get() and might power down the corresponding 2153 * hardware block right away if this is the last reference. 2154 */ 2155 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2156 { 2157 struct drm_device *dev = dev_priv->dev; 2158 struct device *device = &dev->pdev->dev; 2159 2160 if (!HAS_RUNTIME_PM(dev)) 2161 return; 2162 2163 pm_runtime_mark_last_busy(device); 2164 pm_runtime_put_autosuspend(device); 2165 } 2166 2167 /** 2168 * intel_runtime_pm_enable - enable runtime pm 2169 * @dev_priv: i915 device instance 2170 * 2171 * This function enables runtime pm at the end of the driver load sequence. 2172 * 2173 * Note that this function does currently not enable runtime pm for the 2174 * subordinate display power domains. That is only done on the first modeset 2175 * using intel_display_set_init_power(). 2176 */ 2177 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2178 { 2179 struct drm_device *dev = dev_priv->dev; 2180 struct device *device = &dev->pdev->dev; 2181 2182 if (!HAS_RUNTIME_PM(dev)) 2183 return; 2184 2185 /* 2186 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 2187 * requirement. 2188 */ 2189 if (!intel_enable_rc6(dev)) { 2190 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 2191 return; 2192 } 2193 2194 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2195 pm_runtime_mark_last_busy(device); 2196 pm_runtime_use_autosuspend(device); 2197 2198 pm_runtime_put_autosuspend(device); 2199 } 2200 2201