1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 53 for (i = 0; \ 54 i < (power_domains)->power_well_count && \ 55 ((power_well) = &(power_domains)->power_wells[i]); \ 56 i++) \ 57 if ((power_well)->domains & (domain_mask)) 58 59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 60 for (i = (power_domains)->power_well_count - 1; \ 61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 62 i--) \ 63 if ((power_well)->domains & (domain_mask)) 64 65 /* 66 * We should only use the power well if we explicitly asked the hardware to 67 * enable it, so check if it's enabled and also check if we've requested it to 68 * be enabled. 69 */ 70 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 71 struct i915_power_well *power_well) 72 { 73 return I915_READ(HSW_PWR_WELL_DRIVER) == 74 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 75 } 76 77 /** 78 * __intel_display_power_is_enabled - unlocked check for a power domain 79 * @dev_priv: i915 device instance 80 * @domain: power domain to check 81 * 82 * This is the unlocked version of intel_display_power_is_enabled() and should 83 * only be used from error capture and recovery code where deadlocks are 84 * possible. 85 * 86 * Returns: 87 * True when the power domain is enabled, false otherwise. 88 */ 89 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 90 enum intel_display_power_domain domain) 91 { 92 struct i915_power_domains *power_domains; 93 struct i915_power_well *power_well; 94 bool is_enabled; 95 int i; 96 97 if (dev_priv->pm.suspended) 98 return false; 99 100 power_domains = &dev_priv->power_domains; 101 102 is_enabled = true; 103 104 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 105 if (power_well->always_on) 106 continue; 107 108 if (!power_well->hw_enabled) { 109 is_enabled = false; 110 break; 111 } 112 } 113 114 return is_enabled; 115 } 116 117 /** 118 * intel_display_power_is_enabled - unlocked check for a power domain 119 * @dev_priv: i915 device instance 120 * @domain: power domain to check 121 * 122 * This function can be used to check the hw power domain state. It is mostly 123 * used in hardware state readout functions. Everywhere else code should rely 124 * upon explicit power domain reference counting to ensure that the hardware 125 * block is powered up before accessing it. 126 * 127 * Callers must hold the relevant modesetting locks to ensure that concurrent 128 * threads can't disable the power well while the caller tries to read a few 129 * registers. 130 * 131 * Returns: 132 * True when the power domain is enabled, false otherwise. 133 */ 134 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 135 enum intel_display_power_domain domain) 136 { 137 struct i915_power_domains *power_domains; 138 bool ret; 139 140 power_domains = &dev_priv->power_domains; 141 142 mutex_lock(&power_domains->lock); 143 ret = __intel_display_power_is_enabled(dev_priv, domain); 144 mutex_unlock(&power_domains->lock); 145 146 return ret; 147 } 148 149 /** 150 * intel_display_set_init_power - set the initial power domain state 151 * @dev_priv: i915 device instance 152 * @enable: whether to enable or disable the initial power domain state 153 * 154 * For simplicity our driver load/unload and system suspend/resume code assumes 155 * that all power domains are always enabled. This functions controls the state 156 * of this little hack. While the initial power domain state is enabled runtime 157 * pm is effectively disabled. 158 */ 159 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 160 bool enable) 161 { 162 if (dev_priv->power_domains.init_power_on == enable) 163 return; 164 165 if (enable) 166 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 167 else 168 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 169 170 dev_priv->power_domains.init_power_on = enable; 171 } 172 173 /* 174 * Starting with Haswell, we have a "Power Down Well" that can be turned off 175 * when not needed anymore. We have 4 registers that can request the power well 176 * to be enabled, and it will only be disabled if none of the registers is 177 * requesting it to be enabled. 178 */ 179 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 180 { 181 struct drm_device *dev = dev_priv->dev; 182 183 /* 184 * After we re-enable the power well, if we touch VGA register 0x3d5 185 * we'll get unclaimed register interrupts. This stops after we write 186 * anything to the VGA MSR register. The vgacon module uses this 187 * register all the time, so if we unbind our driver and, as a 188 * consequence, bind vgacon, we'll get stuck in an infinite loop at 189 * console_unlock(). So make here we touch the VGA MSR register, making 190 * sure vgacon can keep working normally without triggering interrupts 191 * and error messages. 192 */ 193 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 194 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 195 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 196 197 if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) 198 gen8_irq_power_well_post_enable(dev_priv); 199 } 200 201 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 202 struct i915_power_well *power_well, bool enable) 203 { 204 bool is_enabled, enable_requested; 205 uint32_t tmp; 206 207 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 208 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 209 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 210 211 if (enable) { 212 if (!enable_requested) 213 I915_WRITE(HSW_PWR_WELL_DRIVER, 214 HSW_PWR_WELL_ENABLE_REQUEST); 215 216 if (!is_enabled) { 217 DRM_DEBUG_KMS("Enabling power well\n"); 218 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 219 HSW_PWR_WELL_STATE_ENABLED), 20)) 220 DRM_ERROR("Timeout enabling power well\n"); 221 hsw_power_well_post_enable(dev_priv); 222 } 223 224 } else { 225 if (enable_requested) { 226 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 227 POSTING_READ(HSW_PWR_WELL_DRIVER); 228 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 229 } 230 } 231 } 232 233 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 234 struct i915_power_well *power_well) 235 { 236 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 237 238 /* 239 * We're taking over the BIOS, so clear any requests made by it since 240 * the driver is in charge now. 241 */ 242 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 243 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 244 } 245 246 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 247 struct i915_power_well *power_well) 248 { 249 hsw_set_power_well(dev_priv, power_well, true); 250 } 251 252 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 253 struct i915_power_well *power_well) 254 { 255 hsw_set_power_well(dev_priv, power_well, false); 256 } 257 258 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 259 struct i915_power_well *power_well) 260 { 261 } 262 263 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 264 struct i915_power_well *power_well) 265 { 266 return true; 267 } 268 269 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 270 struct i915_power_well *power_well, bool enable) 271 { 272 enum punit_power_well power_well_id = power_well->data; 273 u32 mask; 274 u32 state; 275 u32 ctrl; 276 277 mask = PUNIT_PWRGT_MASK(power_well_id); 278 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 279 PUNIT_PWRGT_PWR_GATE(power_well_id); 280 281 mutex_lock(&dev_priv->rps.hw_lock); 282 283 #define COND \ 284 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 285 286 if (COND) 287 goto out; 288 289 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 290 ctrl &= ~mask; 291 ctrl |= state; 292 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 293 294 if (wait_for(COND, 100)) 295 DRM_ERROR("timout setting power well state %08x (%08x)\n", 296 state, 297 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 298 299 #undef COND 300 301 out: 302 mutex_unlock(&dev_priv->rps.hw_lock); 303 } 304 305 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 306 struct i915_power_well *power_well) 307 { 308 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 309 } 310 311 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 312 struct i915_power_well *power_well) 313 { 314 vlv_set_power_well(dev_priv, power_well, true); 315 } 316 317 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 318 struct i915_power_well *power_well) 319 { 320 vlv_set_power_well(dev_priv, power_well, false); 321 } 322 323 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 324 struct i915_power_well *power_well) 325 { 326 int power_well_id = power_well->data; 327 bool enabled = false; 328 u32 mask; 329 u32 state; 330 u32 ctrl; 331 332 mask = PUNIT_PWRGT_MASK(power_well_id); 333 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 334 335 mutex_lock(&dev_priv->rps.hw_lock); 336 337 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 338 /* 339 * We only ever set the power-on and power-gate states, anything 340 * else is unexpected. 341 */ 342 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 343 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 344 if (state == ctrl) 345 enabled = true; 346 347 /* 348 * A transient state at this point would mean some unexpected party 349 * is poking at the power controls too. 350 */ 351 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 352 WARN_ON(ctrl != state); 353 354 mutex_unlock(&dev_priv->rps.hw_lock); 355 356 return enabled; 357 } 358 359 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 360 struct i915_power_well *power_well) 361 { 362 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 363 364 vlv_set_power_well(dev_priv, power_well, true); 365 366 spin_lock_irq(&dev_priv->irq_lock); 367 valleyview_enable_display_irqs(dev_priv); 368 spin_unlock_irq(&dev_priv->irq_lock); 369 370 /* 371 * During driver initialization/resume we can avoid restoring the 372 * part of the HW/SW state that will be inited anyway explicitly. 373 */ 374 if (dev_priv->power_domains.initializing) 375 return; 376 377 intel_hpd_init(dev_priv); 378 379 i915_redisable_vga_power_on(dev_priv->dev); 380 } 381 382 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 383 struct i915_power_well *power_well) 384 { 385 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 386 387 spin_lock_irq(&dev_priv->irq_lock); 388 valleyview_disable_display_irqs(dev_priv); 389 spin_unlock_irq(&dev_priv->irq_lock); 390 391 vlv_set_power_well(dev_priv, power_well, false); 392 393 vlv_power_sequencer_reset(dev_priv); 394 } 395 396 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 397 struct i915_power_well *power_well) 398 { 399 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 400 401 /* 402 * Enable the CRI clock source so we can get at the 403 * display and the reference clock for VGA 404 * hotplug / manual detection. 405 */ 406 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | 407 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 408 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 409 410 vlv_set_power_well(dev_priv, power_well, true); 411 412 /* 413 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 414 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 415 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 416 * b. The other bits such as sfr settings / modesel may all 417 * be set to 0. 418 * 419 * This should only be done on init and resume from S3 with 420 * both PLLs disabled, or we risk losing DPIO and PLL 421 * synchronization. 422 */ 423 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 424 } 425 426 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 427 struct i915_power_well *power_well) 428 { 429 enum pipe pipe; 430 431 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 432 433 for_each_pipe(dev_priv, pipe) 434 assert_pll_disabled(dev_priv, pipe); 435 436 /* Assert common reset */ 437 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 438 439 vlv_set_power_well(dev_priv, power_well, false); 440 } 441 442 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 443 struct i915_power_well *power_well) 444 { 445 enum dpio_phy phy; 446 447 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 448 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 449 450 /* 451 * Enable the CRI clock source so we can get at the 452 * display and the reference clock for VGA 453 * hotplug / manual detection. 454 */ 455 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 456 phy = DPIO_PHY0; 457 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | 458 DPLL_REFA_CLK_ENABLE_VLV); 459 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | 460 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 461 } else { 462 phy = DPIO_PHY1; 463 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | 464 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 465 } 466 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 467 vlv_set_power_well(dev_priv, power_well, true); 468 469 /* Poll for phypwrgood signal */ 470 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 471 DRM_ERROR("Display PHY %d is not power up\n", phy); 472 473 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | 474 PHY_COM_LANE_RESET_DEASSERT(phy)); 475 } 476 477 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 478 struct i915_power_well *power_well) 479 { 480 enum dpio_phy phy; 481 482 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 483 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 484 485 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 486 phy = DPIO_PHY0; 487 assert_pll_disabled(dev_priv, PIPE_A); 488 assert_pll_disabled(dev_priv, PIPE_B); 489 } else { 490 phy = DPIO_PHY1; 491 assert_pll_disabled(dev_priv, PIPE_C); 492 } 493 494 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & 495 ~PHY_COM_LANE_RESET_DEASSERT(phy)); 496 497 vlv_set_power_well(dev_priv, power_well, false); 498 } 499 500 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 501 struct i915_power_well *power_well) 502 { 503 enum pipe pipe = power_well->data; 504 bool enabled; 505 u32 state, ctrl; 506 507 mutex_lock(&dev_priv->rps.hw_lock); 508 509 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 510 /* 511 * We only ever set the power-on and power-gate states, anything 512 * else is unexpected. 513 */ 514 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 515 enabled = state == DP_SSS_PWR_ON(pipe); 516 517 /* 518 * A transient state at this point would mean some unexpected party 519 * is poking at the power controls too. 520 */ 521 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 522 WARN_ON(ctrl << 16 != state); 523 524 mutex_unlock(&dev_priv->rps.hw_lock); 525 526 return enabled; 527 } 528 529 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 530 struct i915_power_well *power_well, 531 bool enable) 532 { 533 enum pipe pipe = power_well->data; 534 u32 state; 535 u32 ctrl; 536 537 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 538 539 mutex_lock(&dev_priv->rps.hw_lock); 540 541 #define COND \ 542 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 543 544 if (COND) 545 goto out; 546 547 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 548 ctrl &= ~DP_SSC_MASK(pipe); 549 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 550 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 551 552 if (wait_for(COND, 100)) 553 DRM_ERROR("timout setting power well state %08x (%08x)\n", 554 state, 555 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 556 557 #undef COND 558 559 out: 560 mutex_unlock(&dev_priv->rps.hw_lock); 561 } 562 563 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 564 struct i915_power_well *power_well) 565 { 566 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 567 } 568 569 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 570 struct i915_power_well *power_well) 571 { 572 WARN_ON_ONCE(power_well->data != PIPE_A && 573 power_well->data != PIPE_B && 574 power_well->data != PIPE_C); 575 576 chv_set_pipe_power_well(dev_priv, power_well, true); 577 578 if (power_well->data == PIPE_A) { 579 spin_lock_irq(&dev_priv->irq_lock); 580 valleyview_enable_display_irqs(dev_priv); 581 spin_unlock_irq(&dev_priv->irq_lock); 582 583 /* 584 * During driver initialization/resume we can avoid restoring the 585 * part of the HW/SW state that will be inited anyway explicitly. 586 */ 587 if (dev_priv->power_domains.initializing) 588 return; 589 590 intel_hpd_init(dev_priv); 591 592 i915_redisable_vga_power_on(dev_priv->dev); 593 } 594 } 595 596 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 597 struct i915_power_well *power_well) 598 { 599 WARN_ON_ONCE(power_well->data != PIPE_A && 600 power_well->data != PIPE_B && 601 power_well->data != PIPE_C); 602 603 if (power_well->data == PIPE_A) { 604 spin_lock_irq(&dev_priv->irq_lock); 605 valleyview_disable_display_irqs(dev_priv); 606 spin_unlock_irq(&dev_priv->irq_lock); 607 } 608 609 chv_set_pipe_power_well(dev_priv, power_well, false); 610 611 if (power_well->data == PIPE_A) 612 vlv_power_sequencer_reset(dev_priv); 613 } 614 615 /** 616 * intel_display_power_get - grab a power domain reference 617 * @dev_priv: i915 device instance 618 * @domain: power domain to reference 619 * 620 * This function grabs a power domain reference for @domain and ensures that the 621 * power domain and all its parents are powered up. Therefore users should only 622 * grab a reference to the innermost power domain they need. 623 * 624 * Any power domain reference obtained by this function must have a symmetric 625 * call to intel_display_power_put() to release the reference again. 626 */ 627 void intel_display_power_get(struct drm_i915_private *dev_priv, 628 enum intel_display_power_domain domain) 629 { 630 struct i915_power_domains *power_domains; 631 struct i915_power_well *power_well; 632 int i; 633 634 intel_runtime_pm_get(dev_priv); 635 636 power_domains = &dev_priv->power_domains; 637 638 mutex_lock(&power_domains->lock); 639 640 for_each_power_well(i, power_well, BIT(domain), power_domains) { 641 if (!power_well->count++) { 642 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 643 power_well->ops->enable(dev_priv, power_well); 644 power_well->hw_enabled = true; 645 } 646 } 647 648 power_domains->domain_use_count[domain]++; 649 650 mutex_unlock(&power_domains->lock); 651 } 652 653 /** 654 * intel_display_power_put - release a power domain reference 655 * @dev_priv: i915 device instance 656 * @domain: power domain to reference 657 * 658 * This function drops the power domain reference obtained by 659 * intel_display_power_get() and might power down the corresponding hardware 660 * block right away if this is the last reference. 661 */ 662 void intel_display_power_put(struct drm_i915_private *dev_priv, 663 enum intel_display_power_domain domain) 664 { 665 struct i915_power_domains *power_domains; 666 struct i915_power_well *power_well; 667 int i; 668 669 power_domains = &dev_priv->power_domains; 670 671 mutex_lock(&power_domains->lock); 672 673 WARN_ON(!power_domains->domain_use_count[domain]); 674 power_domains->domain_use_count[domain]--; 675 676 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 677 WARN_ON(!power_well->count); 678 679 if (!--power_well->count && i915.disable_power_well) { 680 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 681 power_well->hw_enabled = false; 682 power_well->ops->disable(dev_priv, power_well); 683 } 684 } 685 686 mutex_unlock(&power_domains->lock); 687 688 intel_runtime_pm_put(dev_priv); 689 } 690 691 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 692 693 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 694 BIT(POWER_DOMAIN_PIPE_A) | \ 695 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 696 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 697 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 698 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 699 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 700 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 701 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 702 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 703 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 704 BIT(POWER_DOMAIN_PORT_CRT) | \ 705 BIT(POWER_DOMAIN_PLLS) | \ 706 BIT(POWER_DOMAIN_INIT)) 707 #define HSW_DISPLAY_POWER_DOMAINS ( \ 708 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 709 BIT(POWER_DOMAIN_INIT)) 710 711 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 712 HSW_ALWAYS_ON_POWER_DOMAINS | \ 713 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 714 #define BDW_DISPLAY_POWER_DOMAINS ( \ 715 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 716 BIT(POWER_DOMAIN_INIT)) 717 718 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 719 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 720 721 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 722 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 723 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 724 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 725 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 726 BIT(POWER_DOMAIN_PORT_CRT) | \ 727 BIT(POWER_DOMAIN_INIT)) 728 729 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 730 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 731 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 732 BIT(POWER_DOMAIN_INIT)) 733 734 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 735 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 736 BIT(POWER_DOMAIN_INIT)) 737 738 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 739 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 740 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 741 BIT(POWER_DOMAIN_INIT)) 742 743 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 744 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 745 BIT(POWER_DOMAIN_INIT)) 746 747 #define CHV_PIPE_A_POWER_DOMAINS ( \ 748 BIT(POWER_DOMAIN_PIPE_A) | \ 749 BIT(POWER_DOMAIN_INIT)) 750 751 #define CHV_PIPE_B_POWER_DOMAINS ( \ 752 BIT(POWER_DOMAIN_PIPE_B) | \ 753 BIT(POWER_DOMAIN_INIT)) 754 755 #define CHV_PIPE_C_POWER_DOMAINS ( \ 756 BIT(POWER_DOMAIN_PIPE_C) | \ 757 BIT(POWER_DOMAIN_INIT)) 758 759 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 760 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 761 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 762 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 763 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 764 BIT(POWER_DOMAIN_INIT)) 765 766 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 767 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 768 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 769 BIT(POWER_DOMAIN_INIT)) 770 771 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ 772 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 773 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 774 BIT(POWER_DOMAIN_INIT)) 775 776 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ 777 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 778 BIT(POWER_DOMAIN_INIT)) 779 780 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 781 .sync_hw = i9xx_always_on_power_well_noop, 782 .enable = i9xx_always_on_power_well_noop, 783 .disable = i9xx_always_on_power_well_noop, 784 .is_enabled = i9xx_always_on_power_well_enabled, 785 }; 786 787 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 788 .sync_hw = chv_pipe_power_well_sync_hw, 789 .enable = chv_pipe_power_well_enable, 790 .disable = chv_pipe_power_well_disable, 791 .is_enabled = chv_pipe_power_well_enabled, 792 }; 793 794 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 795 .sync_hw = vlv_power_well_sync_hw, 796 .enable = chv_dpio_cmn_power_well_enable, 797 .disable = chv_dpio_cmn_power_well_disable, 798 .is_enabled = vlv_power_well_enabled, 799 }; 800 801 static struct i915_power_well i9xx_always_on_power_well[] = { 802 { 803 .name = "always-on", 804 .always_on = 1, 805 .domains = POWER_DOMAIN_MASK, 806 .ops = &i9xx_always_on_power_well_ops, 807 }, 808 }; 809 810 static const struct i915_power_well_ops hsw_power_well_ops = { 811 .sync_hw = hsw_power_well_sync_hw, 812 .enable = hsw_power_well_enable, 813 .disable = hsw_power_well_disable, 814 .is_enabled = hsw_power_well_enabled, 815 }; 816 817 static struct i915_power_well hsw_power_wells[] = { 818 { 819 .name = "always-on", 820 .always_on = 1, 821 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 822 .ops = &i9xx_always_on_power_well_ops, 823 }, 824 { 825 .name = "display", 826 .domains = HSW_DISPLAY_POWER_DOMAINS, 827 .ops = &hsw_power_well_ops, 828 }, 829 }; 830 831 static struct i915_power_well bdw_power_wells[] = { 832 { 833 .name = "always-on", 834 .always_on = 1, 835 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 836 .ops = &i9xx_always_on_power_well_ops, 837 }, 838 { 839 .name = "display", 840 .domains = BDW_DISPLAY_POWER_DOMAINS, 841 .ops = &hsw_power_well_ops, 842 }, 843 }; 844 845 static const struct i915_power_well_ops vlv_display_power_well_ops = { 846 .sync_hw = vlv_power_well_sync_hw, 847 .enable = vlv_display_power_well_enable, 848 .disable = vlv_display_power_well_disable, 849 .is_enabled = vlv_power_well_enabled, 850 }; 851 852 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 853 .sync_hw = vlv_power_well_sync_hw, 854 .enable = vlv_dpio_cmn_power_well_enable, 855 .disable = vlv_dpio_cmn_power_well_disable, 856 .is_enabled = vlv_power_well_enabled, 857 }; 858 859 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 860 .sync_hw = vlv_power_well_sync_hw, 861 .enable = vlv_power_well_enable, 862 .disable = vlv_power_well_disable, 863 .is_enabled = vlv_power_well_enabled, 864 }; 865 866 static struct i915_power_well vlv_power_wells[] = { 867 { 868 .name = "always-on", 869 .always_on = 1, 870 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 871 .ops = &i9xx_always_on_power_well_ops, 872 }, 873 { 874 .name = "display", 875 .domains = VLV_DISPLAY_POWER_DOMAINS, 876 .data = PUNIT_POWER_WELL_DISP2D, 877 .ops = &vlv_display_power_well_ops, 878 }, 879 { 880 .name = "dpio-tx-b-01", 881 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 882 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 883 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 884 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 885 .ops = &vlv_dpio_power_well_ops, 886 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 887 }, 888 { 889 .name = "dpio-tx-b-23", 890 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 891 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 892 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 893 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 894 .ops = &vlv_dpio_power_well_ops, 895 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 896 }, 897 { 898 .name = "dpio-tx-c-01", 899 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 900 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 901 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 902 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 903 .ops = &vlv_dpio_power_well_ops, 904 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 905 }, 906 { 907 .name = "dpio-tx-c-23", 908 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 909 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 910 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 911 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 912 .ops = &vlv_dpio_power_well_ops, 913 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 914 }, 915 { 916 .name = "dpio-common", 917 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 918 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 919 .ops = &vlv_dpio_cmn_power_well_ops, 920 }, 921 }; 922 923 static struct i915_power_well chv_power_wells[] = { 924 { 925 .name = "always-on", 926 .always_on = 1, 927 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 928 .ops = &i9xx_always_on_power_well_ops, 929 }, 930 #if 0 931 { 932 .name = "display", 933 .domains = VLV_DISPLAY_POWER_DOMAINS, 934 .data = PUNIT_POWER_WELL_DISP2D, 935 .ops = &vlv_display_power_well_ops, 936 }, 937 #endif 938 { 939 .name = "pipe-a", 940 /* 941 * FIXME: pipe A power well seems to be the new disp2d well. 942 * At least all registers seem to be housed there. Figure 943 * out if this a a temporary situation in pre-production 944 * hardware or a permanent state of affairs. 945 */ 946 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, 947 .data = PIPE_A, 948 .ops = &chv_pipe_power_well_ops, 949 }, 950 #if 0 951 { 952 .name = "pipe-b", 953 .domains = CHV_PIPE_B_POWER_DOMAINS, 954 .data = PIPE_B, 955 .ops = &chv_pipe_power_well_ops, 956 }, 957 { 958 .name = "pipe-c", 959 .domains = CHV_PIPE_C_POWER_DOMAINS, 960 .data = PIPE_C, 961 .ops = &chv_pipe_power_well_ops, 962 }, 963 #endif 964 { 965 .name = "dpio-common-bc", 966 /* 967 * XXX: cmnreset for one PHY seems to disturb the other. 968 * As a workaround keep both powered on at the same 969 * time for now. 970 */ 971 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, 972 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 973 .ops = &chv_dpio_cmn_power_well_ops, 974 }, 975 { 976 .name = "dpio-common-d", 977 /* 978 * XXX: cmnreset for one PHY seems to disturb the other. 979 * As a workaround keep both powered on at the same 980 * time for now. 981 */ 982 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, 983 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 984 .ops = &chv_dpio_cmn_power_well_ops, 985 }, 986 #if 0 987 { 988 .name = "dpio-tx-b-01", 989 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 990 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, 991 .ops = &vlv_dpio_power_well_ops, 992 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 993 }, 994 { 995 .name = "dpio-tx-b-23", 996 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 997 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, 998 .ops = &vlv_dpio_power_well_ops, 999 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1000 }, 1001 { 1002 .name = "dpio-tx-c-01", 1003 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1004 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1005 .ops = &vlv_dpio_power_well_ops, 1006 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1007 }, 1008 { 1009 .name = "dpio-tx-c-23", 1010 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1011 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1012 .ops = &vlv_dpio_power_well_ops, 1013 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1014 }, 1015 { 1016 .name = "dpio-tx-d-01", 1017 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | 1018 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, 1019 .ops = &vlv_dpio_power_well_ops, 1020 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, 1021 }, 1022 { 1023 .name = "dpio-tx-d-23", 1024 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | 1025 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, 1026 .ops = &vlv_dpio_power_well_ops, 1027 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, 1028 }, 1029 #endif 1030 }; 1031 1032 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1033 enum punit_power_well power_well_id) 1034 { 1035 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1036 struct i915_power_well *power_well; 1037 int i; 1038 1039 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1040 if (power_well->data == power_well_id) 1041 return power_well; 1042 } 1043 1044 return NULL; 1045 } 1046 1047 #define set_power_wells(power_domains, __power_wells) ({ \ 1048 (power_domains)->power_wells = (__power_wells); \ 1049 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 1050 }) 1051 1052 /** 1053 * intel_power_domains_init - initializes the power domain structures 1054 * @dev_priv: i915 device instance 1055 * 1056 * Initializes the power domain structures for @dev_priv depending upon the 1057 * supported platform. 1058 */ 1059 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1060 { 1061 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1062 1063 mutex_init(&power_domains->lock); 1064 1065 /* 1066 * The enabling order will be from lower to higher indexed wells, 1067 * the disabling order is reversed. 1068 */ 1069 if (IS_HASWELL(dev_priv->dev)) { 1070 set_power_wells(power_domains, hsw_power_wells); 1071 } else if (IS_BROADWELL(dev_priv->dev)) { 1072 set_power_wells(power_domains, bdw_power_wells); 1073 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1074 set_power_wells(power_domains, chv_power_wells); 1075 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 1076 set_power_wells(power_domains, vlv_power_wells); 1077 } else { 1078 set_power_wells(power_domains, i9xx_always_on_power_well); 1079 } 1080 1081 return 0; 1082 } 1083 1084 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) 1085 { 1086 struct drm_device *dev = dev_priv->dev; 1087 struct device *device = &dev->pdev->dev; 1088 1089 if (!HAS_RUNTIME_PM(dev)) 1090 return; 1091 1092 if (!intel_enable_rc6(dev)) 1093 return; 1094 1095 /* Make sure we're not suspended first. */ 1096 pm_runtime_get_sync(device); 1097 pm_runtime_disable(device); 1098 } 1099 1100 /** 1101 * intel_power_domains_fini - finalizes the power domain structures 1102 * @dev_priv: i915 device instance 1103 * 1104 * Finalizes the power domain structures for @dev_priv depending upon the 1105 * supported platform. This function also disables runtime pm and ensures that 1106 * the device stays powered up so that the driver can be reloaded. 1107 */ 1108 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 1109 { 1110 intel_runtime_pm_disable(dev_priv); 1111 1112 /* The i915.ko module is still not prepared to be loaded when 1113 * the power well is not enabled, so just enable it in case 1114 * we're going to unload/reload. */ 1115 intel_display_set_init_power(dev_priv, true); 1116 } 1117 1118 static void intel_power_domains_resume(struct drm_i915_private *dev_priv) 1119 { 1120 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1121 struct i915_power_well *power_well; 1122 int i; 1123 1124 mutex_lock(&power_domains->lock); 1125 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1126 power_well->ops->sync_hw(dev_priv, power_well); 1127 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 1128 power_well); 1129 } 1130 mutex_unlock(&power_domains->lock); 1131 } 1132 1133 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1134 { 1135 struct i915_power_well *cmn = 1136 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1137 struct i915_power_well *disp2d = 1138 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 1139 1140 /* If the display might be already active skip this */ 1141 if (cmn->ops->is_enabled(dev_priv, cmn) && 1142 disp2d->ops->is_enabled(dev_priv, disp2d) && 1143 I915_READ(DPIO_CTL) & DPIO_CMNRST) 1144 return; 1145 1146 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 1147 1148 /* cmnlane needs DPLL registers */ 1149 disp2d->ops->enable(dev_priv, disp2d); 1150 1151 /* 1152 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1153 * Need to assert and de-assert PHY SB reset by gating the 1154 * common lane power, then un-gating it. 1155 * Simply ungating isn't enough to reset the PHY enough to get 1156 * ports and lanes running. 1157 */ 1158 cmn->ops->disable(dev_priv, cmn); 1159 } 1160 1161 /** 1162 * intel_power_domains_init_hw - initialize hardware power domain state 1163 * @dev_priv: i915 device instance 1164 * 1165 * This function initializes the hardware power domain state and enables all 1166 * power domains using intel_display_set_init_power(). 1167 */ 1168 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) 1169 { 1170 struct drm_device *dev = dev_priv->dev; 1171 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1172 1173 power_domains->initializing = true; 1174 1175 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { 1176 mutex_lock(&power_domains->lock); 1177 vlv_cmnlane_wa(dev_priv); 1178 mutex_unlock(&power_domains->lock); 1179 } 1180 1181 /* For now, we need the power well to be always enabled. */ 1182 intel_display_set_init_power(dev_priv, true); 1183 intel_power_domains_resume(dev_priv); 1184 power_domains->initializing = false; 1185 } 1186 1187 /** 1188 * intel_aux_display_runtime_get - grab an auxilliary power domain reference 1189 * @dev_priv: i915 device instance 1190 * 1191 * This function grabs a power domain reference for the auxiliary power domain 1192 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its 1193 * parents are powered up. Therefore users should only grab a reference to the 1194 * innermost power domain they need. 1195 * 1196 * Any power domain reference obtained by this function must have a symmetric 1197 * call to intel_aux_display_runtime_put() to release the reference again. 1198 */ 1199 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 1200 { 1201 intel_runtime_pm_get(dev_priv); 1202 } 1203 1204 /** 1205 * intel_aux_display_runtime_put - release an auxilliary power domain reference 1206 * @dev_priv: i915 device instance 1207 * 1208 * This function drops the auxilliary power domain reference obtained by 1209 * intel_aux_display_runtime_get() and might power down the corresponding 1210 * hardware block right away if this is the last reference. 1211 */ 1212 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 1213 { 1214 intel_runtime_pm_put(dev_priv); 1215 } 1216 1217 /** 1218 * intel_runtime_pm_get - grab a runtime pm reference 1219 * @dev_priv: i915 device instance 1220 * 1221 * This function grabs a device-level runtime pm reference (mostly used for GEM 1222 * code to ensure the GTT or GT is on) and ensures that it is powered up. 1223 * 1224 * Any runtime pm reference obtained by this function must have a symmetric 1225 * call to intel_runtime_pm_put() to release the reference again. 1226 */ 1227 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 1228 { 1229 struct drm_device *dev = dev_priv->dev; 1230 struct device *device = &dev->pdev->dev; 1231 1232 if (!HAS_RUNTIME_PM(dev)) 1233 return; 1234 1235 pm_runtime_get_sync(device); 1236 WARN(dev_priv->pm.suspended, "Device still suspended.\n"); 1237 } 1238 1239 /** 1240 * intel_runtime_pm_get_noresume - grab a runtime pm reference 1241 * @dev_priv: i915 device instance 1242 * 1243 * This function grabs a device-level runtime pm reference (mostly used for GEM 1244 * code to ensure the GTT or GT is on). 1245 * 1246 * It will _not_ power up the device but instead only check that it's powered 1247 * on. Therefore it is only valid to call this functions from contexts where 1248 * the device is known to be powered up and where trying to power it up would 1249 * result in hilarity and deadlocks. That pretty much means only the system 1250 * suspend/resume code where this is used to grab runtime pm references for 1251 * delayed setup down in work items. 1252 * 1253 * Any runtime pm reference obtained by this function must have a symmetric 1254 * call to intel_runtime_pm_put() to release the reference again. 1255 */ 1256 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 1257 { 1258 struct drm_device *dev = dev_priv->dev; 1259 struct device *device = &dev->pdev->dev; 1260 1261 if (!HAS_RUNTIME_PM(dev)) 1262 return; 1263 1264 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); 1265 pm_runtime_get_noresume(device); 1266 } 1267 1268 /** 1269 * intel_runtime_pm_put - release a runtime pm reference 1270 * @dev_priv: i915 device instance 1271 * 1272 * This function drops the device-level runtime pm reference obtained by 1273 * intel_runtime_pm_get() and might power down the corresponding 1274 * hardware block right away if this is the last reference. 1275 */ 1276 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 1277 { 1278 struct drm_device *dev = dev_priv->dev; 1279 struct device *device = &dev->pdev->dev; 1280 1281 if (!HAS_RUNTIME_PM(dev)) 1282 return; 1283 1284 pm_runtime_mark_last_busy(device); 1285 pm_runtime_put_autosuspend(device); 1286 } 1287 1288 /** 1289 * intel_runtime_pm_enable - enable runtime pm 1290 * @dev_priv: i915 device instance 1291 * 1292 * This function enables runtime pm at the end of the driver load sequence. 1293 * 1294 * Note that this function does currently not enable runtime pm for the 1295 * subordinate display power domains. That is only done on the first modeset 1296 * using intel_display_set_init_power(). 1297 */ 1298 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 1299 { 1300 struct drm_device *dev = dev_priv->dev; 1301 struct device *device = &dev->pdev->dev; 1302 1303 if (!HAS_RUNTIME_PM(dev)) 1304 return; 1305 1306 pm_runtime_set_active(device); 1307 1308 /* 1309 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 1310 * requirement. 1311 */ 1312 if (!intel_enable_rc6(dev)) { 1313 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 1314 return; 1315 } 1316 1317 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 1318 pm_runtime_mark_last_busy(device); 1319 pm_runtime_use_autosuspend(device); 1320 1321 pm_runtime_put_autosuspend(device); 1322 } 1323 1324