1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 53 enum i915_power_well_id power_well_id); 54 55 static struct i915_power_well * 56 lookup_power_well(struct drm_i915_private *dev_priv, 57 enum i915_power_well_id power_well_id); 58 59 const char * 60 intel_display_power_domain_str(enum intel_display_power_domain domain) 61 { 62 switch (domain) { 63 case POWER_DOMAIN_PIPE_A: 64 return "PIPE_A"; 65 case POWER_DOMAIN_PIPE_B: 66 return "PIPE_B"; 67 case POWER_DOMAIN_PIPE_C: 68 return "PIPE_C"; 69 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 70 return "PIPE_A_PANEL_FITTER"; 71 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 72 return "PIPE_B_PANEL_FITTER"; 73 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 74 return "PIPE_C_PANEL_FITTER"; 75 case POWER_DOMAIN_TRANSCODER_A: 76 return "TRANSCODER_A"; 77 case POWER_DOMAIN_TRANSCODER_B: 78 return "TRANSCODER_B"; 79 case POWER_DOMAIN_TRANSCODER_C: 80 return "TRANSCODER_C"; 81 case POWER_DOMAIN_TRANSCODER_EDP: 82 return "TRANSCODER_EDP"; 83 case POWER_DOMAIN_TRANSCODER_DSI_A: 84 return "TRANSCODER_DSI_A"; 85 case POWER_DOMAIN_TRANSCODER_DSI_C: 86 return "TRANSCODER_DSI_C"; 87 case POWER_DOMAIN_PORT_DDI_A_LANES: 88 return "PORT_DDI_A_LANES"; 89 case POWER_DOMAIN_PORT_DDI_B_LANES: 90 return "PORT_DDI_B_LANES"; 91 case POWER_DOMAIN_PORT_DDI_C_LANES: 92 return "PORT_DDI_C_LANES"; 93 case POWER_DOMAIN_PORT_DDI_D_LANES: 94 return "PORT_DDI_D_LANES"; 95 case POWER_DOMAIN_PORT_DDI_E_LANES: 96 return "PORT_DDI_E_LANES"; 97 case POWER_DOMAIN_PORT_DDI_A_IO: 98 return "PORT_DDI_A_IO"; 99 case POWER_DOMAIN_PORT_DDI_B_IO: 100 return "PORT_DDI_B_IO"; 101 case POWER_DOMAIN_PORT_DDI_C_IO: 102 return "PORT_DDI_C_IO"; 103 case POWER_DOMAIN_PORT_DDI_D_IO: 104 return "PORT_DDI_D_IO"; 105 case POWER_DOMAIN_PORT_DDI_E_IO: 106 return "PORT_DDI_E_IO"; 107 case POWER_DOMAIN_PORT_DSI: 108 return "PORT_DSI"; 109 case POWER_DOMAIN_PORT_CRT: 110 return "PORT_CRT"; 111 case POWER_DOMAIN_PORT_OTHER: 112 return "PORT_OTHER"; 113 case POWER_DOMAIN_VGA: 114 return "VGA"; 115 case POWER_DOMAIN_AUDIO: 116 return "AUDIO"; 117 case POWER_DOMAIN_PLLS: 118 return "PLLS"; 119 case POWER_DOMAIN_AUX_A: 120 return "AUX_A"; 121 case POWER_DOMAIN_AUX_B: 122 return "AUX_B"; 123 case POWER_DOMAIN_AUX_C: 124 return "AUX_C"; 125 case POWER_DOMAIN_AUX_D: 126 return "AUX_D"; 127 case POWER_DOMAIN_GMBUS: 128 return "GMBUS"; 129 case POWER_DOMAIN_INIT: 130 return "INIT"; 131 case POWER_DOMAIN_MODESET: 132 return "MODESET"; 133 default: 134 MISSING_CASE(domain); 135 return "?"; 136 } 137 } 138 139 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 140 struct i915_power_well *power_well) 141 { 142 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 143 power_well->ops->enable(dev_priv, power_well); 144 power_well->hw_enabled = true; 145 } 146 147 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 148 struct i915_power_well *power_well) 149 { 150 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 151 power_well->hw_enabled = false; 152 power_well->ops->disable(dev_priv, power_well); 153 } 154 155 static void intel_power_well_get(struct drm_i915_private *dev_priv, 156 struct i915_power_well *power_well) 157 { 158 if (!power_well->count++) 159 intel_power_well_enable(dev_priv, power_well); 160 } 161 162 static void intel_power_well_put(struct drm_i915_private *dev_priv, 163 struct i915_power_well *power_well) 164 { 165 WARN(!power_well->count, "Use count on power well %s is already zero", 166 power_well->name); 167 168 if (!--power_well->count) 169 intel_power_well_disable(dev_priv, power_well); 170 } 171 172 /** 173 * __intel_display_power_is_enabled - unlocked check for a power domain 174 * @dev_priv: i915 device instance 175 * @domain: power domain to check 176 * 177 * This is the unlocked version of intel_display_power_is_enabled() and should 178 * only be used from error capture and recovery code where deadlocks are 179 * possible. 180 * 181 * Returns: 182 * True when the power domain is enabled, false otherwise. 183 */ 184 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 185 enum intel_display_power_domain domain) 186 { 187 struct i915_power_well *power_well; 188 bool is_enabled; 189 190 if (dev_priv->runtime_pm.suspended) 191 return false; 192 193 is_enabled = true; 194 195 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { 196 if (power_well->always_on) 197 continue; 198 199 if (!power_well->hw_enabled) { 200 is_enabled = false; 201 break; 202 } 203 } 204 205 return is_enabled; 206 } 207 208 /** 209 * intel_display_power_is_enabled - check for a power domain 210 * @dev_priv: i915 device instance 211 * @domain: power domain to check 212 * 213 * This function can be used to check the hw power domain state. It is mostly 214 * used in hardware state readout functions. Everywhere else code should rely 215 * upon explicit power domain reference counting to ensure that the hardware 216 * block is powered up before accessing it. 217 * 218 * Callers must hold the relevant modesetting locks to ensure that concurrent 219 * threads can't disable the power well while the caller tries to read a few 220 * registers. 221 * 222 * Returns: 223 * True when the power domain is enabled, false otherwise. 224 */ 225 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 226 enum intel_display_power_domain domain) 227 { 228 struct i915_power_domains *power_domains; 229 bool ret; 230 231 power_domains = &dev_priv->power_domains; 232 233 mutex_lock(&power_domains->lock); 234 ret = __intel_display_power_is_enabled(dev_priv, domain); 235 mutex_unlock(&power_domains->lock); 236 237 return ret; 238 } 239 240 /** 241 * intel_display_set_init_power - set the initial power domain state 242 * @dev_priv: i915 device instance 243 * @enable: whether to enable or disable the initial power domain state 244 * 245 * For simplicity our driver load/unload and system suspend/resume code assumes 246 * that all power domains are always enabled. This functions controls the state 247 * of this little hack. While the initial power domain state is enabled runtime 248 * pm is effectively disabled. 249 */ 250 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 251 bool enable) 252 { 253 if (dev_priv->power_domains.init_power_on == enable) 254 return; 255 256 if (enable) 257 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 258 else 259 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 260 261 dev_priv->power_domains.init_power_on = enable; 262 } 263 264 /* 265 * Starting with Haswell, we have a "Power Down Well" that can be turned off 266 * when not needed anymore. We have 4 registers that can request the power well 267 * to be enabled, and it will only be disabled if none of the registers is 268 * requesting it to be enabled. 269 */ 270 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 271 u8 irq_pipe_mask, bool has_vga) 272 { 273 struct pci_dev *pdev = dev_priv->drm.pdev; 274 275 /* 276 * After we re-enable the power well, if we touch VGA register 0x3d5 277 * we'll get unclaimed register interrupts. This stops after we write 278 * anything to the VGA MSR register. The vgacon module uses this 279 * register all the time, so if we unbind our driver and, as a 280 * consequence, bind vgacon, we'll get stuck in an infinite loop at 281 * console_unlock(). So make here we touch the VGA MSR register, making 282 * sure vgacon can keep working normally without triggering interrupts 283 * and error messages. 284 */ 285 if (has_vga) { 286 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 287 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 288 vga_put(pdev, VGA_RSRC_LEGACY_IO); 289 } 290 291 if (irq_pipe_mask) 292 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 293 } 294 295 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 296 u8 irq_pipe_mask) 297 { 298 if (irq_pipe_mask) 299 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 300 } 301 302 303 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 304 struct i915_power_well *power_well) 305 { 306 enum i915_power_well_id id = power_well->id; 307 308 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 309 WARN_ON(intel_wait_for_register(dev_priv, 310 HSW_PWR_WELL_CTL_DRIVER(id), 311 HSW_PWR_WELL_CTL_STATE(id), 312 HSW_PWR_WELL_CTL_STATE(id), 313 1)); 314 } 315 316 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 317 enum i915_power_well_id id) 318 { 319 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); 320 u32 ret; 321 322 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; 323 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; 324 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; 325 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; 326 327 return ret; 328 } 329 330 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 331 struct i915_power_well *power_well) 332 { 333 enum i915_power_well_id id = power_well->id; 334 bool disabled; 335 u32 reqs; 336 337 /* 338 * Bspec doesn't require waiting for PWs to get disabled, but still do 339 * this for paranoia. The known cases where a PW will be forced on: 340 * - a KVMR request on any power well via the KVMR request register 341 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 342 * DEBUG request registers 343 * Skip the wait in case any of the request bits are set and print a 344 * diagnostic message. 345 */ 346 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 347 HSW_PWR_WELL_CTL_STATE(id))) || 348 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); 349 if (disabled) 350 return; 351 352 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 353 power_well->name, 354 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 355 } 356 357 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 358 enum skl_power_gate pg) 359 { 360 /* Timeout 5us for PG#0, for other PGs 1us */ 361 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, 362 SKL_FUSE_PG_DIST_STATUS(pg), 363 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 364 } 365 366 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 367 struct i915_power_well *power_well) 368 { 369 enum i915_power_well_id id = power_well->id; 370 bool wait_fuses = power_well->hsw.has_fuses; 371 enum skl_power_gate uninitialized_var(pg); 372 u32 val; 373 374 if (wait_fuses) { 375 pg = SKL_PW_TO_PG(id); 376 /* 377 * For PW1 we have to wait both for the PW0/PG0 fuse state 378 * before enabling the power well and PW1/PG1's own fuse 379 * state after the enabling. For all other power wells with 380 * fuses we only have to wait for that PW/PG's fuse state 381 * after the enabling. 382 */ 383 if (pg == SKL_PG1) 384 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 385 } 386 387 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 388 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); 389 hsw_wait_for_power_well_enable(dev_priv, power_well); 390 391 if (wait_fuses) 392 gen9_wait_for_power_well_fuses(dev_priv, pg); 393 394 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, 395 power_well->hsw.has_vga); 396 } 397 398 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 399 struct i915_power_well *power_well) 400 { 401 enum i915_power_well_id id = power_well->id; 402 u32 val; 403 404 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); 405 406 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 407 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), 408 val & ~HSW_PWR_WELL_CTL_REQ(id)); 409 hsw_wait_for_power_well_disable(dev_priv, power_well); 410 } 411 412 /* 413 * We should only use the power well if we explicitly asked the hardware to 414 * enable it, so check if it's enabled and also check if we've requested it to 415 * be enabled. 416 */ 417 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 418 struct i915_power_well *power_well) 419 { 420 enum i915_power_well_id id = power_well->id; 421 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); 422 423 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; 424 } 425 426 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 427 { 428 enum i915_power_well_id id = SKL_DISP_PW_2; 429 430 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 431 "DC9 already programmed to be enabled.\n"); 432 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 433 "DC5 still not disabled to enable DC9.\n"); 434 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 435 HSW_PWR_WELL_CTL_REQ(id), 436 "Power well 2 on.\n"); 437 WARN_ONCE(intel_irqs_enabled(dev_priv), 438 "Interrupts not disabled yet.\n"); 439 440 /* 441 * TODO: check for the following to verify the conditions to enter DC9 442 * state are satisfied: 443 * 1] Check relevant display engine registers to verify if mode set 444 * disable sequence was followed. 445 * 2] Check if display uninitialize sequence is initialized. 446 */ 447 } 448 449 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 450 { 451 WARN_ONCE(intel_irqs_enabled(dev_priv), 452 "Interrupts not disabled yet.\n"); 453 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 454 "DC5 still not disabled.\n"); 455 456 /* 457 * TODO: check for the following to verify DC9 state was indeed 458 * entered before programming to disable it: 459 * 1] Check relevant display engine registers to verify if mode 460 * set disable sequence was followed. 461 * 2] Check if display uninitialize sequence is initialized. 462 */ 463 } 464 465 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 466 u32 state) 467 { 468 int rewrites = 0; 469 int rereads = 0; 470 u32 v; 471 472 I915_WRITE(DC_STATE_EN, state); 473 474 /* It has been observed that disabling the dc6 state sometimes 475 * doesn't stick and dmc keeps returning old value. Make sure 476 * the write really sticks enough times and also force rewrite until 477 * we are confident that state is exactly what we want. 478 */ 479 do { 480 v = I915_READ(DC_STATE_EN); 481 482 if (v != state) { 483 I915_WRITE(DC_STATE_EN, state); 484 rewrites++; 485 rereads = 0; 486 } else if (rereads++ > 5) { 487 break; 488 } 489 490 } while (rewrites < 100); 491 492 if (v != state) 493 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 494 state, v); 495 496 /* Most of the times we need one retry, avoid spam */ 497 if (rewrites > 1) 498 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 499 state, rewrites); 500 } 501 502 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 503 { 504 u32 mask; 505 506 mask = DC_STATE_EN_UPTO_DC5; 507 if (IS_GEN9_LP(dev_priv)) 508 mask |= DC_STATE_EN_DC9; 509 else 510 mask |= DC_STATE_EN_UPTO_DC6; 511 512 return mask; 513 } 514 515 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 516 { 517 u32 val; 518 519 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 520 521 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 522 dev_priv->csr.dc_state, val); 523 dev_priv->csr.dc_state = val; 524 } 525 526 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 527 { 528 uint32_t val; 529 uint32_t mask; 530 531 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 532 state &= dev_priv->csr.allowed_dc_mask; 533 534 val = I915_READ(DC_STATE_EN); 535 mask = gen9_dc_mask(dev_priv); 536 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 537 val & mask, state); 538 539 /* Check if DMC is ignoring our DC state requests */ 540 if ((val & mask) != dev_priv->csr.dc_state) 541 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 542 dev_priv->csr.dc_state, val & mask); 543 544 val &= ~mask; 545 val |= state; 546 547 gen9_write_dc_state(dev_priv, val); 548 549 dev_priv->csr.dc_state = val & mask; 550 } 551 552 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 553 { 554 assert_can_enable_dc9(dev_priv); 555 556 DRM_DEBUG_KMS("Enabling DC9\n"); 557 558 intel_power_sequencer_reset(dev_priv); 559 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 560 } 561 562 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 563 { 564 assert_can_disable_dc9(dev_priv); 565 566 DRM_DEBUG_KMS("Disabling DC9\n"); 567 568 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 569 570 intel_pps_unlock_regs_wa(dev_priv); 571 } 572 573 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 574 { 575 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 576 "CSR program storage start is NULL\n"); 577 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 578 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 579 } 580 581 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 582 { 583 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 584 SKL_DISP_PW_2); 585 586 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 587 588 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 589 "DC5 already programmed to be enabled.\n"); 590 assert_rpm_wakelock_held(dev_priv); 591 592 assert_csr_loaded(dev_priv); 593 } 594 595 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 596 { 597 assert_can_enable_dc5(dev_priv); 598 599 DRM_DEBUG_KMS("Enabling DC5\n"); 600 601 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 602 } 603 604 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 605 { 606 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 607 "Backlight is not disabled.\n"); 608 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 609 "DC6 already programmed to be enabled.\n"); 610 611 assert_csr_loaded(dev_priv); 612 } 613 614 void skl_enable_dc6(struct drm_i915_private *dev_priv) 615 { 616 assert_can_enable_dc6(dev_priv); 617 618 DRM_DEBUG_KMS("Enabling DC6\n"); 619 620 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 621 622 } 623 624 void skl_disable_dc6(struct drm_i915_private *dev_priv) 625 { 626 DRM_DEBUG_KMS("Disabling DC6\n"); 627 628 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 629 } 630 631 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 632 struct i915_power_well *power_well) 633 { 634 enum i915_power_well_id id = power_well->id; 635 u32 mask = HSW_PWR_WELL_CTL_REQ(id); 636 u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); 637 638 /* Take over the request bit if set by BIOS. */ 639 if (bios_req & mask) { 640 u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 641 642 if (!(drv_req & mask)) 643 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); 644 I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); 645 } 646 } 647 648 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 649 struct i915_power_well *power_well) 650 { 651 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); 652 } 653 654 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 655 struct i915_power_well *power_well) 656 { 657 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); 658 } 659 660 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 661 struct i915_power_well *power_well) 662 { 663 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); 664 } 665 666 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 667 { 668 struct i915_power_well *power_well; 669 670 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 671 if (power_well->count > 0) 672 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 673 674 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); 675 if (power_well->count > 0) 676 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 677 678 if (IS_GEMINILAKE(dev_priv)) { 679 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); 680 if (power_well->count > 0) 681 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 682 } 683 } 684 685 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 686 struct i915_power_well *power_well) 687 { 688 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 689 } 690 691 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 692 { 693 u32 tmp = I915_READ(DBUF_CTL); 694 695 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 696 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 697 "Unexpected DBuf power power state (0x%08x)\n", tmp); 698 } 699 700 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 701 struct i915_power_well *power_well) 702 { 703 struct intel_cdclk_state cdclk_state = {}; 704 705 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 706 707 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); 708 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 709 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); 710 711 gen9_assert_dbuf_enabled(dev_priv); 712 713 if (IS_GEN9_LP(dev_priv)) 714 bxt_verify_ddi_phy_power_wells(dev_priv); 715 } 716 717 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 718 struct i915_power_well *power_well) 719 { 720 if (!dev_priv->csr.dmc_payload) 721 return; 722 723 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 724 skl_enable_dc6(dev_priv); 725 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 726 gen9_enable_dc5(dev_priv); 727 } 728 729 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 730 struct i915_power_well *power_well) 731 { 732 } 733 734 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 735 struct i915_power_well *power_well) 736 { 737 } 738 739 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 740 struct i915_power_well *power_well) 741 { 742 return true; 743 } 744 745 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 746 struct i915_power_well *power_well) 747 { 748 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) 749 i830_enable_pipe(dev_priv, PIPE_A); 750 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) 751 i830_enable_pipe(dev_priv, PIPE_B); 752 } 753 754 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 755 struct i915_power_well *power_well) 756 { 757 i830_disable_pipe(dev_priv, PIPE_B); 758 i830_disable_pipe(dev_priv, PIPE_A); 759 } 760 761 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 762 struct i915_power_well *power_well) 763 { 764 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && 765 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 766 } 767 768 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 769 struct i915_power_well *power_well) 770 { 771 if (power_well->count > 0) 772 i830_pipes_power_well_enable(dev_priv, power_well); 773 else 774 i830_pipes_power_well_disable(dev_priv, power_well); 775 } 776 777 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 778 struct i915_power_well *power_well, bool enable) 779 { 780 enum i915_power_well_id power_well_id = power_well->id; 781 u32 mask; 782 u32 state; 783 u32 ctrl; 784 785 mask = PUNIT_PWRGT_MASK(power_well_id); 786 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 787 PUNIT_PWRGT_PWR_GATE(power_well_id); 788 789 mutex_lock(&dev_priv->pcu_lock); 790 791 #define COND \ 792 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 793 794 if (COND) 795 goto out; 796 797 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 798 ctrl &= ~mask; 799 ctrl |= state; 800 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 801 802 if (wait_for(COND, 100)) 803 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 804 state, 805 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 806 807 #undef COND 808 809 out: 810 mutex_unlock(&dev_priv->pcu_lock); 811 } 812 813 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 814 struct i915_power_well *power_well) 815 { 816 vlv_set_power_well(dev_priv, power_well, true); 817 } 818 819 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 820 struct i915_power_well *power_well) 821 { 822 vlv_set_power_well(dev_priv, power_well, false); 823 } 824 825 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 826 struct i915_power_well *power_well) 827 { 828 enum i915_power_well_id power_well_id = power_well->id; 829 bool enabled = false; 830 u32 mask; 831 u32 state; 832 u32 ctrl; 833 834 mask = PUNIT_PWRGT_MASK(power_well_id); 835 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 836 837 mutex_lock(&dev_priv->pcu_lock); 838 839 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 840 /* 841 * We only ever set the power-on and power-gate states, anything 842 * else is unexpected. 843 */ 844 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 845 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 846 if (state == ctrl) 847 enabled = true; 848 849 /* 850 * A transient state at this point would mean some unexpected party 851 * is poking at the power controls too. 852 */ 853 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 854 WARN_ON(ctrl != state); 855 856 mutex_unlock(&dev_priv->pcu_lock); 857 858 return enabled; 859 } 860 861 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 862 { 863 u32 val; 864 865 /* 866 * On driver load, a pipe may be active and driving a DSI display. 867 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 868 * (and never recovering) in this case. intel_dsi_post_disable() will 869 * clear it when we turn off the display. 870 */ 871 val = I915_READ(DSPCLK_GATE_D); 872 val &= DPOUNIT_CLOCK_GATE_DISABLE; 873 val |= VRHUNIT_CLOCK_GATE_DISABLE; 874 I915_WRITE(DSPCLK_GATE_D, val); 875 876 /* 877 * Disable trickle feed and enable pnd deadline calculation 878 */ 879 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 880 I915_WRITE(CBR1_VLV, 0); 881 882 WARN_ON(dev_priv->rawclk_freq == 0); 883 884 I915_WRITE(RAWCLK_FREQ_VLV, 885 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 886 } 887 888 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 889 { 890 struct intel_encoder *encoder; 891 enum pipe pipe; 892 893 /* 894 * Enable the CRI clock source so we can get at the 895 * display and the reference clock for VGA 896 * hotplug / manual detection. Supposedly DSI also 897 * needs the ref clock up and running. 898 * 899 * CHV DPLL B/C have some issues if VGA mode is enabled. 900 */ 901 for_each_pipe(dev_priv, pipe) { 902 u32 val = I915_READ(DPLL(pipe)); 903 904 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 905 if (pipe != PIPE_A) 906 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 907 908 I915_WRITE(DPLL(pipe), val); 909 } 910 911 vlv_init_display_clock_gating(dev_priv); 912 913 spin_lock_irq(&dev_priv->irq_lock); 914 valleyview_enable_display_irqs(dev_priv); 915 spin_unlock_irq(&dev_priv->irq_lock); 916 917 /* 918 * During driver initialization/resume we can avoid restoring the 919 * part of the HW/SW state that will be inited anyway explicitly. 920 */ 921 if (dev_priv->power_domains.initializing) 922 return; 923 924 intel_hpd_init(dev_priv); 925 926 /* Re-enable the ADPA, if we have one */ 927 for_each_intel_encoder(&dev_priv->drm, encoder) { 928 if (encoder->type == INTEL_OUTPUT_ANALOG) 929 intel_crt_reset(&encoder->base); 930 } 931 932 i915_redisable_vga_power_on(dev_priv); 933 934 intel_pps_unlock_regs_wa(dev_priv); 935 } 936 937 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 938 { 939 spin_lock_irq(&dev_priv->irq_lock); 940 valleyview_disable_display_irqs(dev_priv); 941 spin_unlock_irq(&dev_priv->irq_lock); 942 943 /* make sure we're done processing display irqs */ 944 synchronize_irq(dev_priv->drm.irq); 945 946 intel_power_sequencer_reset(dev_priv); 947 948 /* Prevent us from re-enabling polling on accident in late suspend */ 949 if (!dev_priv->drm.dev->power.is_suspended) 950 intel_hpd_poll_init(dev_priv); 951 } 952 953 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 954 struct i915_power_well *power_well) 955 { 956 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 957 958 vlv_set_power_well(dev_priv, power_well, true); 959 960 vlv_display_power_well_init(dev_priv); 961 } 962 963 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 964 struct i915_power_well *power_well) 965 { 966 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 967 968 vlv_display_power_well_deinit(dev_priv); 969 970 vlv_set_power_well(dev_priv, power_well, false); 971 } 972 973 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 974 struct i915_power_well *power_well) 975 { 976 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 977 978 /* since ref/cri clock was enabled */ 979 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 980 981 vlv_set_power_well(dev_priv, power_well, true); 982 983 /* 984 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 985 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 986 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 987 * b. The other bits such as sfr settings / modesel may all 988 * be set to 0. 989 * 990 * This should only be done on init and resume from S3 with 991 * both PLLs disabled, or we risk losing DPIO and PLL 992 * synchronization. 993 */ 994 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 995 } 996 997 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 998 struct i915_power_well *power_well) 999 { 1000 enum pipe pipe; 1001 1002 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1003 1004 for_each_pipe(dev_priv, pipe) 1005 assert_pll_disabled(dev_priv, pipe); 1006 1007 /* Assert common reset */ 1008 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1009 1010 vlv_set_power_well(dev_priv, power_well, false); 1011 } 1012 1013 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 1014 1015 static struct i915_power_well * 1016 lookup_power_well(struct drm_i915_private *dev_priv, 1017 enum i915_power_well_id power_well_id) 1018 { 1019 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1020 int i; 1021 1022 for (i = 0; i < power_domains->power_well_count; i++) { 1023 struct i915_power_well *power_well; 1024 1025 power_well = &power_domains->power_wells[i]; 1026 if (power_well->id == power_well_id) 1027 return power_well; 1028 } 1029 1030 return NULL; 1031 } 1032 1033 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1034 1035 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1036 { 1037 struct i915_power_well *cmn_bc = 1038 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1039 struct i915_power_well *cmn_d = 1040 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1041 u32 phy_control = dev_priv->chv_phy_control; 1042 u32 phy_status = 0; 1043 u32 phy_status_mask = 0xffffffff; 1044 1045 /* 1046 * The BIOS can leave the PHY is some weird state 1047 * where it doesn't fully power down some parts. 1048 * Disable the asserts until the PHY has been fully 1049 * reset (ie. the power well has been disabled at 1050 * least once). 1051 */ 1052 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1053 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1054 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1055 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1056 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1057 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1058 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1059 1060 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1061 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1062 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1063 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1064 1065 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1066 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1067 1068 /* this assumes override is only used to enable lanes */ 1069 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1070 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1071 1072 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1073 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1074 1075 /* CL1 is on whenever anything is on in either channel */ 1076 if (BITS_SET(phy_control, 1077 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1078 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1079 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1080 1081 /* 1082 * The DPLLB check accounts for the pipe B + port A usage 1083 * with CL2 powered up but all the lanes in the second channel 1084 * powered down. 1085 */ 1086 if (BITS_SET(phy_control, 1087 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1088 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1089 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1090 1091 if (BITS_SET(phy_control, 1092 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1093 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1094 if (BITS_SET(phy_control, 1095 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1096 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1097 1098 if (BITS_SET(phy_control, 1099 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1100 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1101 if (BITS_SET(phy_control, 1102 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1103 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1104 } 1105 1106 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1107 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1108 1109 /* this assumes override is only used to enable lanes */ 1110 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1111 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1112 1113 if (BITS_SET(phy_control, 1114 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1115 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1116 1117 if (BITS_SET(phy_control, 1118 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1119 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1120 if (BITS_SET(phy_control, 1121 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1122 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1123 } 1124 1125 phy_status &= phy_status_mask; 1126 1127 /* 1128 * The PHY may be busy with some initial calibration and whatnot, 1129 * so the power state can take a while to actually change. 1130 */ 1131 if (intel_wait_for_register(dev_priv, 1132 DISPLAY_PHY_STATUS, 1133 phy_status_mask, 1134 phy_status, 1135 10)) 1136 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1137 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1138 phy_status, dev_priv->chv_phy_control); 1139 } 1140 1141 #undef BITS_SET 1142 1143 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1144 struct i915_power_well *power_well) 1145 { 1146 enum dpio_phy phy; 1147 enum pipe pipe; 1148 uint32_t tmp; 1149 1150 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1151 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1152 1153 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1154 pipe = PIPE_A; 1155 phy = DPIO_PHY0; 1156 } else { 1157 pipe = PIPE_C; 1158 phy = DPIO_PHY1; 1159 } 1160 1161 /* since ref/cri clock was enabled */ 1162 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1163 vlv_set_power_well(dev_priv, power_well, true); 1164 1165 /* Poll for phypwrgood signal */ 1166 if (intel_wait_for_register(dev_priv, 1167 DISPLAY_PHY_STATUS, 1168 PHY_POWERGOOD(phy), 1169 PHY_POWERGOOD(phy), 1170 1)) 1171 DRM_ERROR("Display PHY %d is not power up\n", phy); 1172 1173 mutex_lock(&dev_priv->sb_lock); 1174 1175 /* Enable dynamic power down */ 1176 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1177 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1178 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1179 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1180 1181 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1182 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1183 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1184 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1185 } else { 1186 /* 1187 * Force the non-existing CL2 off. BXT does this 1188 * too, so maybe it saves some power even though 1189 * CL2 doesn't exist? 1190 */ 1191 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1192 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1193 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1194 } 1195 1196 mutex_unlock(&dev_priv->sb_lock); 1197 1198 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1199 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1200 1201 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1202 phy, dev_priv->chv_phy_control); 1203 1204 assert_chv_phy_status(dev_priv); 1205 } 1206 1207 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1208 struct i915_power_well *power_well) 1209 { 1210 enum dpio_phy phy; 1211 1212 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1213 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1214 1215 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1216 phy = DPIO_PHY0; 1217 assert_pll_disabled(dev_priv, PIPE_A); 1218 assert_pll_disabled(dev_priv, PIPE_B); 1219 } else { 1220 phy = DPIO_PHY1; 1221 assert_pll_disabled(dev_priv, PIPE_C); 1222 } 1223 1224 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1225 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1226 1227 vlv_set_power_well(dev_priv, power_well, false); 1228 1229 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1230 phy, dev_priv->chv_phy_control); 1231 1232 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1233 dev_priv->chv_phy_assert[phy] = true; 1234 1235 assert_chv_phy_status(dev_priv); 1236 } 1237 1238 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1239 enum dpio_channel ch, bool override, unsigned int mask) 1240 { 1241 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1242 u32 reg, val, expected, actual; 1243 1244 /* 1245 * The BIOS can leave the PHY is some weird state 1246 * where it doesn't fully power down some parts. 1247 * Disable the asserts until the PHY has been fully 1248 * reset (ie. the power well has been disabled at 1249 * least once). 1250 */ 1251 if (!dev_priv->chv_phy_assert[phy]) 1252 return; 1253 1254 if (ch == DPIO_CH0) 1255 reg = _CHV_CMN_DW0_CH0; 1256 else 1257 reg = _CHV_CMN_DW6_CH1; 1258 1259 mutex_lock(&dev_priv->sb_lock); 1260 val = vlv_dpio_read(dev_priv, pipe, reg); 1261 mutex_unlock(&dev_priv->sb_lock); 1262 1263 /* 1264 * This assumes !override is only used when the port is disabled. 1265 * All lanes should power down even without the override when 1266 * the port is disabled. 1267 */ 1268 if (!override || mask == 0xf) { 1269 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1270 /* 1271 * If CH1 common lane is not active anymore 1272 * (eg. for pipe B DPLL) the entire channel will 1273 * shut down, which causes the common lane registers 1274 * to read as 0. That means we can't actually check 1275 * the lane power down status bits, but as the entire 1276 * register reads as 0 it's a good indication that the 1277 * channel is indeed entirely powered down. 1278 */ 1279 if (ch == DPIO_CH1 && val == 0) 1280 expected = 0; 1281 } else if (mask != 0x0) { 1282 expected = DPIO_ANYDL_POWERDOWN; 1283 } else { 1284 expected = 0; 1285 } 1286 1287 if (ch == DPIO_CH0) 1288 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1289 else 1290 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1291 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1292 1293 WARN(actual != expected, 1294 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1295 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1296 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1297 reg, val); 1298 } 1299 1300 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1301 enum dpio_channel ch, bool override) 1302 { 1303 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1304 bool was_override; 1305 1306 mutex_lock(&power_domains->lock); 1307 1308 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1309 1310 if (override == was_override) 1311 goto out; 1312 1313 if (override) 1314 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1315 else 1316 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1317 1318 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1319 1320 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1321 phy, ch, dev_priv->chv_phy_control); 1322 1323 assert_chv_phy_status(dev_priv); 1324 1325 out: 1326 mutex_unlock(&power_domains->lock); 1327 1328 return was_override; 1329 } 1330 1331 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1332 bool override, unsigned int mask) 1333 { 1334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1335 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1336 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1337 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1338 1339 mutex_lock(&power_domains->lock); 1340 1341 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1342 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1343 1344 if (override) 1345 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1346 else 1347 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1348 1349 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1350 1351 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1352 phy, ch, mask, dev_priv->chv_phy_control); 1353 1354 assert_chv_phy_status(dev_priv); 1355 1356 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1357 1358 mutex_unlock(&power_domains->lock); 1359 } 1360 1361 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1362 struct i915_power_well *power_well) 1363 { 1364 enum pipe pipe = PIPE_A; 1365 bool enabled; 1366 u32 state, ctrl; 1367 1368 mutex_lock(&dev_priv->pcu_lock); 1369 1370 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1371 /* 1372 * We only ever set the power-on and power-gate states, anything 1373 * else is unexpected. 1374 */ 1375 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1376 enabled = state == DP_SSS_PWR_ON(pipe); 1377 1378 /* 1379 * A transient state at this point would mean some unexpected party 1380 * is poking at the power controls too. 1381 */ 1382 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1383 WARN_ON(ctrl << 16 != state); 1384 1385 mutex_unlock(&dev_priv->pcu_lock); 1386 1387 return enabled; 1388 } 1389 1390 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1391 struct i915_power_well *power_well, 1392 bool enable) 1393 { 1394 enum pipe pipe = PIPE_A; 1395 u32 state; 1396 u32 ctrl; 1397 1398 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1399 1400 mutex_lock(&dev_priv->pcu_lock); 1401 1402 #define COND \ 1403 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1404 1405 if (COND) 1406 goto out; 1407 1408 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1409 ctrl &= ~DP_SSC_MASK(pipe); 1410 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1411 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1412 1413 if (wait_for(COND, 100)) 1414 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1415 state, 1416 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1417 1418 #undef COND 1419 1420 out: 1421 mutex_unlock(&dev_priv->pcu_lock); 1422 } 1423 1424 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1425 struct i915_power_well *power_well) 1426 { 1427 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1428 1429 chv_set_pipe_power_well(dev_priv, power_well, true); 1430 1431 vlv_display_power_well_init(dev_priv); 1432 } 1433 1434 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1435 struct i915_power_well *power_well) 1436 { 1437 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1438 1439 vlv_display_power_well_deinit(dev_priv); 1440 1441 chv_set_pipe_power_well(dev_priv, power_well, false); 1442 } 1443 1444 static void 1445 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1446 enum intel_display_power_domain domain) 1447 { 1448 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1449 struct i915_power_well *power_well; 1450 1451 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) 1452 intel_power_well_get(dev_priv, power_well); 1453 1454 power_domains->domain_use_count[domain]++; 1455 } 1456 1457 /** 1458 * intel_display_power_get - grab a power domain reference 1459 * @dev_priv: i915 device instance 1460 * @domain: power domain to reference 1461 * 1462 * This function grabs a power domain reference for @domain and ensures that the 1463 * power domain and all its parents are powered up. Therefore users should only 1464 * grab a reference to the innermost power domain they need. 1465 * 1466 * Any power domain reference obtained by this function must have a symmetric 1467 * call to intel_display_power_put() to release the reference again. 1468 */ 1469 void intel_display_power_get(struct drm_i915_private *dev_priv, 1470 enum intel_display_power_domain domain) 1471 { 1472 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1473 1474 intel_runtime_pm_get(dev_priv); 1475 1476 mutex_lock(&power_domains->lock); 1477 1478 __intel_display_power_get_domain(dev_priv, domain); 1479 1480 mutex_unlock(&power_domains->lock); 1481 } 1482 1483 /** 1484 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1485 * @dev_priv: i915 device instance 1486 * @domain: power domain to reference 1487 * 1488 * This function grabs a power domain reference for @domain and ensures that the 1489 * power domain and all its parents are powered up. Therefore users should only 1490 * grab a reference to the innermost power domain they need. 1491 * 1492 * Any power domain reference obtained by this function must have a symmetric 1493 * call to intel_display_power_put() to release the reference again. 1494 */ 1495 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1496 enum intel_display_power_domain domain) 1497 { 1498 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1499 bool is_enabled; 1500 1501 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1502 return false; 1503 1504 mutex_lock(&power_domains->lock); 1505 1506 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1507 __intel_display_power_get_domain(dev_priv, domain); 1508 is_enabled = true; 1509 } else { 1510 is_enabled = false; 1511 } 1512 1513 mutex_unlock(&power_domains->lock); 1514 1515 if (!is_enabled) 1516 intel_runtime_pm_put(dev_priv); 1517 1518 return is_enabled; 1519 } 1520 1521 /** 1522 * intel_display_power_put - release a power domain reference 1523 * @dev_priv: i915 device instance 1524 * @domain: power domain to reference 1525 * 1526 * This function drops the power domain reference obtained by 1527 * intel_display_power_get() and might power down the corresponding hardware 1528 * block right away if this is the last reference. 1529 */ 1530 void intel_display_power_put(struct drm_i915_private *dev_priv, 1531 enum intel_display_power_domain domain) 1532 { 1533 struct i915_power_domains *power_domains; 1534 struct i915_power_well *power_well; 1535 1536 power_domains = &dev_priv->power_domains; 1537 1538 mutex_lock(&power_domains->lock); 1539 1540 WARN(!power_domains->domain_use_count[domain], 1541 "Use count on domain %s is already zero\n", 1542 intel_display_power_domain_str(domain)); 1543 power_domains->domain_use_count[domain]--; 1544 1545 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) 1546 intel_power_well_put(dev_priv, power_well); 1547 1548 mutex_unlock(&power_domains->lock); 1549 1550 intel_runtime_pm_put(dev_priv); 1551 } 1552 1553 #define I830_PIPES_POWER_DOMAINS ( \ 1554 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1555 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1556 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1557 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1558 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1559 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1560 BIT_ULL(POWER_DOMAIN_INIT)) 1561 1562 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1563 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1564 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1565 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1566 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1567 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1568 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1569 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1570 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1571 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1572 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1573 BIT_ULL(POWER_DOMAIN_VGA) | \ 1574 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1575 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1576 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1577 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1578 BIT_ULL(POWER_DOMAIN_INIT)) 1579 1580 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1581 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1582 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1583 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1584 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1585 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1586 BIT_ULL(POWER_DOMAIN_INIT)) 1587 1588 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1589 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1590 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1591 BIT_ULL(POWER_DOMAIN_INIT)) 1592 1593 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1594 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1595 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1596 BIT_ULL(POWER_DOMAIN_INIT)) 1597 1598 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1599 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1600 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1601 BIT_ULL(POWER_DOMAIN_INIT)) 1602 1603 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1604 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1605 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1606 BIT_ULL(POWER_DOMAIN_INIT)) 1607 1608 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1609 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1610 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1611 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1612 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1613 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1614 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1615 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1616 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1617 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1618 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1619 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1620 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1621 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1622 BIT_ULL(POWER_DOMAIN_VGA) | \ 1623 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1624 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1625 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1626 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1627 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1628 BIT_ULL(POWER_DOMAIN_INIT)) 1629 1630 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1631 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1632 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1633 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1634 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1635 BIT_ULL(POWER_DOMAIN_INIT)) 1636 1637 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1638 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1639 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1640 BIT_ULL(POWER_DOMAIN_INIT)) 1641 1642 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1643 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1644 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1645 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1646 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1647 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1648 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1649 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1650 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1651 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1652 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1653 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1654 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1655 BIT_ULL(POWER_DOMAIN_VGA) | \ 1656 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1657 BIT_ULL(POWER_DOMAIN_INIT)) 1658 1659 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1660 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1661 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1662 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1663 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1664 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1665 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1666 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1667 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1668 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1669 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1670 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1671 BIT_ULL(POWER_DOMAIN_VGA) | \ 1672 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1673 BIT_ULL(POWER_DOMAIN_INIT)) 1674 1675 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1676 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1677 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1678 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1679 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1680 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1681 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1682 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1683 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1684 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1685 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1686 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 1687 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1688 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1689 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1690 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1691 BIT_ULL(POWER_DOMAIN_VGA) | \ 1692 BIT_ULL(POWER_DOMAIN_INIT)) 1693 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ 1694 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1695 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ 1696 BIT_ULL(POWER_DOMAIN_INIT)) 1697 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1698 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1699 BIT_ULL(POWER_DOMAIN_INIT)) 1700 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1701 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1702 BIT_ULL(POWER_DOMAIN_INIT)) 1703 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ 1704 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1705 BIT_ULL(POWER_DOMAIN_INIT)) 1706 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1707 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1708 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1709 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1710 BIT_ULL(POWER_DOMAIN_INIT)) 1711 1712 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1713 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1714 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1715 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1716 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1717 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1718 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1719 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1720 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1721 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1722 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1723 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1724 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1725 BIT_ULL(POWER_DOMAIN_VGA) | \ 1726 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1727 BIT_ULL(POWER_DOMAIN_INIT)) 1728 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1729 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1730 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1731 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1732 BIT_ULL(POWER_DOMAIN_INIT)) 1733 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 1734 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1735 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1736 BIT_ULL(POWER_DOMAIN_INIT)) 1737 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 1738 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1739 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1740 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1741 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1742 BIT_ULL(POWER_DOMAIN_INIT)) 1743 1744 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1745 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1746 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1747 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1748 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1749 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1750 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1751 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1752 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1753 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1754 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1755 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1756 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1757 BIT_ULL(POWER_DOMAIN_VGA) | \ 1758 BIT_ULL(POWER_DOMAIN_INIT)) 1759 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ 1760 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) 1761 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1762 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) 1763 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1764 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) 1765 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ 1766 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1767 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1768 BIT_ULL(POWER_DOMAIN_INIT)) 1769 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ 1770 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1771 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1772 BIT_ULL(POWER_DOMAIN_INIT)) 1773 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ 1774 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1775 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1776 BIT_ULL(POWER_DOMAIN_INIT)) 1777 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1778 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1779 BIT_ULL(POWER_DOMAIN_INIT)) 1780 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1781 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1782 BIT_ULL(POWER_DOMAIN_INIT)) 1783 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1784 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1785 BIT_ULL(POWER_DOMAIN_INIT)) 1786 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1787 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1788 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1789 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1790 BIT_ULL(POWER_DOMAIN_INIT)) 1791 1792 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1793 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1794 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1795 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1796 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1797 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1798 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1799 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1800 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1801 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1802 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1803 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1804 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1805 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1806 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1807 BIT_ULL(POWER_DOMAIN_VGA) | \ 1808 BIT_ULL(POWER_DOMAIN_INIT)) 1809 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ 1810 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1811 BIT_ULL(POWER_DOMAIN_INIT)) 1812 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ 1813 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1814 BIT_ULL(POWER_DOMAIN_INIT)) 1815 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ 1816 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1817 BIT_ULL(POWER_DOMAIN_INIT)) 1818 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ 1819 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1820 BIT_ULL(POWER_DOMAIN_INIT)) 1821 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1822 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1823 BIT_ULL(POWER_DOMAIN_INIT)) 1824 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1825 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1826 BIT_ULL(POWER_DOMAIN_INIT)) 1827 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1828 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1829 BIT_ULL(POWER_DOMAIN_INIT)) 1830 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ 1831 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1832 BIT_ULL(POWER_DOMAIN_INIT)) 1833 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1834 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1835 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1836 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1837 BIT_ULL(POWER_DOMAIN_INIT)) 1838 1839 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1840 .sync_hw = i9xx_power_well_sync_hw_noop, 1841 .enable = i9xx_always_on_power_well_noop, 1842 .disable = i9xx_always_on_power_well_noop, 1843 .is_enabled = i9xx_always_on_power_well_enabled, 1844 }; 1845 1846 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1847 .sync_hw = i9xx_power_well_sync_hw_noop, 1848 .enable = chv_pipe_power_well_enable, 1849 .disable = chv_pipe_power_well_disable, 1850 .is_enabled = chv_pipe_power_well_enabled, 1851 }; 1852 1853 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1854 .sync_hw = i9xx_power_well_sync_hw_noop, 1855 .enable = chv_dpio_cmn_power_well_enable, 1856 .disable = chv_dpio_cmn_power_well_disable, 1857 .is_enabled = vlv_power_well_enabled, 1858 }; 1859 1860 static struct i915_power_well i9xx_always_on_power_well[] = { 1861 { 1862 .name = "always-on", 1863 .always_on = 1, 1864 .domains = POWER_DOMAIN_MASK, 1865 .ops = &i9xx_always_on_power_well_ops, 1866 .id = I915_DISP_PW_ALWAYS_ON, 1867 }, 1868 }; 1869 1870 static const struct i915_power_well_ops i830_pipes_power_well_ops = { 1871 .sync_hw = i830_pipes_power_well_sync_hw, 1872 .enable = i830_pipes_power_well_enable, 1873 .disable = i830_pipes_power_well_disable, 1874 .is_enabled = i830_pipes_power_well_enabled, 1875 }; 1876 1877 static struct i915_power_well i830_power_wells[] = { 1878 { 1879 .name = "always-on", 1880 .always_on = 1, 1881 .domains = POWER_DOMAIN_MASK, 1882 .ops = &i9xx_always_on_power_well_ops, 1883 .id = I915_DISP_PW_ALWAYS_ON, 1884 }, 1885 { 1886 .name = "pipes", 1887 .domains = I830_PIPES_POWER_DOMAINS, 1888 .ops = &i830_pipes_power_well_ops, 1889 .id = I830_DISP_PW_PIPES, 1890 }, 1891 }; 1892 1893 static const struct i915_power_well_ops hsw_power_well_ops = { 1894 .sync_hw = hsw_power_well_sync_hw, 1895 .enable = hsw_power_well_enable, 1896 .disable = hsw_power_well_disable, 1897 .is_enabled = hsw_power_well_enabled, 1898 }; 1899 1900 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1901 .sync_hw = i9xx_power_well_sync_hw_noop, 1902 .enable = gen9_dc_off_power_well_enable, 1903 .disable = gen9_dc_off_power_well_disable, 1904 .is_enabled = gen9_dc_off_power_well_enabled, 1905 }; 1906 1907 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1908 .sync_hw = i9xx_power_well_sync_hw_noop, 1909 .enable = bxt_dpio_cmn_power_well_enable, 1910 .disable = bxt_dpio_cmn_power_well_disable, 1911 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1912 }; 1913 1914 static struct i915_power_well hsw_power_wells[] = { 1915 { 1916 .name = "always-on", 1917 .always_on = 1, 1918 .domains = POWER_DOMAIN_MASK, 1919 .ops = &i9xx_always_on_power_well_ops, 1920 .id = I915_DISP_PW_ALWAYS_ON, 1921 }, 1922 { 1923 .name = "display", 1924 .domains = HSW_DISPLAY_POWER_DOMAINS, 1925 .ops = &hsw_power_well_ops, 1926 .id = HSW_DISP_PW_GLOBAL, 1927 { 1928 .hsw.has_vga = true, 1929 }, 1930 }, 1931 }; 1932 1933 static struct i915_power_well bdw_power_wells[] = { 1934 { 1935 .name = "always-on", 1936 .always_on = 1, 1937 .domains = POWER_DOMAIN_MASK, 1938 .ops = &i9xx_always_on_power_well_ops, 1939 .id = I915_DISP_PW_ALWAYS_ON, 1940 }, 1941 { 1942 .name = "display", 1943 .domains = BDW_DISPLAY_POWER_DOMAINS, 1944 .ops = &hsw_power_well_ops, 1945 .id = HSW_DISP_PW_GLOBAL, 1946 { 1947 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 1948 .hsw.has_vga = true, 1949 }, 1950 }, 1951 }; 1952 1953 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1954 .sync_hw = i9xx_power_well_sync_hw_noop, 1955 .enable = vlv_display_power_well_enable, 1956 .disable = vlv_display_power_well_disable, 1957 .is_enabled = vlv_power_well_enabled, 1958 }; 1959 1960 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1961 .sync_hw = i9xx_power_well_sync_hw_noop, 1962 .enable = vlv_dpio_cmn_power_well_enable, 1963 .disable = vlv_dpio_cmn_power_well_disable, 1964 .is_enabled = vlv_power_well_enabled, 1965 }; 1966 1967 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1968 .sync_hw = i9xx_power_well_sync_hw_noop, 1969 .enable = vlv_power_well_enable, 1970 .disable = vlv_power_well_disable, 1971 .is_enabled = vlv_power_well_enabled, 1972 }; 1973 1974 static struct i915_power_well vlv_power_wells[] = { 1975 { 1976 .name = "always-on", 1977 .always_on = 1, 1978 .domains = POWER_DOMAIN_MASK, 1979 .ops = &i9xx_always_on_power_well_ops, 1980 .id = I915_DISP_PW_ALWAYS_ON, 1981 }, 1982 { 1983 .name = "display", 1984 .domains = VLV_DISPLAY_POWER_DOMAINS, 1985 .id = PUNIT_POWER_WELL_DISP2D, 1986 .ops = &vlv_display_power_well_ops, 1987 }, 1988 { 1989 .name = "dpio-tx-b-01", 1990 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1991 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1992 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1993 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1994 .ops = &vlv_dpio_power_well_ops, 1995 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1996 }, 1997 { 1998 .name = "dpio-tx-b-23", 1999 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2000 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2001 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2002 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2003 .ops = &vlv_dpio_power_well_ops, 2004 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 2005 }, 2006 { 2007 .name = "dpio-tx-c-01", 2008 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2009 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2010 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2011 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2012 .ops = &vlv_dpio_power_well_ops, 2013 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 2014 }, 2015 { 2016 .name = "dpio-tx-c-23", 2017 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2018 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2019 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2020 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2021 .ops = &vlv_dpio_power_well_ops, 2022 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 2023 }, 2024 { 2025 .name = "dpio-common", 2026 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2027 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2028 .ops = &vlv_dpio_cmn_power_well_ops, 2029 }, 2030 }; 2031 2032 static struct i915_power_well chv_power_wells[] = { 2033 { 2034 .name = "always-on", 2035 .always_on = 1, 2036 .domains = POWER_DOMAIN_MASK, 2037 .ops = &i9xx_always_on_power_well_ops, 2038 .id = I915_DISP_PW_ALWAYS_ON, 2039 }, 2040 { 2041 .name = "display", 2042 /* 2043 * Pipe A power well is the new disp2d well. Pipe B and C 2044 * power wells don't actually exist. Pipe A power well is 2045 * required for any pipe to work. 2046 */ 2047 .domains = CHV_DISPLAY_POWER_DOMAINS, 2048 .id = CHV_DISP_PW_PIPE_A, 2049 .ops = &chv_pipe_power_well_ops, 2050 }, 2051 { 2052 .name = "dpio-common-bc", 2053 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2054 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2055 .ops = &chv_dpio_cmn_power_well_ops, 2056 }, 2057 { 2058 .name = "dpio-common-d", 2059 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2060 .id = PUNIT_POWER_WELL_DPIO_CMN_D, 2061 .ops = &chv_dpio_cmn_power_well_ops, 2062 }, 2063 }; 2064 2065 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2066 enum i915_power_well_id power_well_id) 2067 { 2068 struct i915_power_well *power_well; 2069 bool ret; 2070 2071 power_well = lookup_power_well(dev_priv, power_well_id); 2072 ret = power_well->ops->is_enabled(dev_priv, power_well); 2073 2074 return ret; 2075 } 2076 2077 static struct i915_power_well skl_power_wells[] = { 2078 { 2079 .name = "always-on", 2080 .always_on = 1, 2081 .domains = POWER_DOMAIN_MASK, 2082 .ops = &i9xx_always_on_power_well_ops, 2083 .id = I915_DISP_PW_ALWAYS_ON, 2084 }, 2085 { 2086 .name = "power well 1", 2087 /* Handled by the DMC firmware */ 2088 .domains = 0, 2089 .ops = &hsw_power_well_ops, 2090 .id = SKL_DISP_PW_1, 2091 { 2092 .hsw.has_fuses = true, 2093 }, 2094 }, 2095 { 2096 .name = "MISC IO power well", 2097 /* Handled by the DMC firmware */ 2098 .domains = 0, 2099 .ops = &hsw_power_well_ops, 2100 .id = SKL_DISP_PW_MISC_IO, 2101 }, 2102 { 2103 .name = "DC off", 2104 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2105 .ops = &gen9_dc_off_power_well_ops, 2106 .id = SKL_DISP_PW_DC_OFF, 2107 }, 2108 { 2109 .name = "power well 2", 2110 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2111 .ops = &hsw_power_well_ops, 2112 .id = SKL_DISP_PW_2, 2113 { 2114 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2115 .hsw.has_vga = true, 2116 .hsw.has_fuses = true, 2117 }, 2118 }, 2119 { 2120 .name = "DDI A/E IO power well", 2121 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, 2122 .ops = &hsw_power_well_ops, 2123 .id = SKL_DISP_PW_DDI_A_E, 2124 }, 2125 { 2126 .name = "DDI B IO power well", 2127 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2128 .ops = &hsw_power_well_ops, 2129 .id = SKL_DISP_PW_DDI_B, 2130 }, 2131 { 2132 .name = "DDI C IO power well", 2133 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2134 .ops = &hsw_power_well_ops, 2135 .id = SKL_DISP_PW_DDI_C, 2136 }, 2137 { 2138 .name = "DDI D IO power well", 2139 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, 2140 .ops = &hsw_power_well_ops, 2141 .id = SKL_DISP_PW_DDI_D, 2142 }, 2143 }; 2144 2145 static struct i915_power_well bxt_power_wells[] = { 2146 { 2147 .name = "always-on", 2148 .always_on = 1, 2149 .domains = POWER_DOMAIN_MASK, 2150 .ops = &i9xx_always_on_power_well_ops, 2151 .id = I915_DISP_PW_ALWAYS_ON, 2152 }, 2153 { 2154 .name = "power well 1", 2155 .domains = 0, 2156 .ops = &hsw_power_well_ops, 2157 .id = SKL_DISP_PW_1, 2158 { 2159 .hsw.has_fuses = true, 2160 }, 2161 }, 2162 { 2163 .name = "DC off", 2164 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2165 .ops = &gen9_dc_off_power_well_ops, 2166 .id = SKL_DISP_PW_DC_OFF, 2167 }, 2168 { 2169 .name = "power well 2", 2170 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2171 .ops = &hsw_power_well_ops, 2172 .id = SKL_DISP_PW_2, 2173 { 2174 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2175 .hsw.has_vga = true, 2176 .hsw.has_fuses = true, 2177 }, 2178 }, 2179 { 2180 .name = "dpio-common-a", 2181 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2182 .ops = &bxt_dpio_cmn_power_well_ops, 2183 .id = BXT_DPIO_CMN_A, 2184 { 2185 .bxt.phy = DPIO_PHY1, 2186 }, 2187 }, 2188 { 2189 .name = "dpio-common-bc", 2190 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2191 .ops = &bxt_dpio_cmn_power_well_ops, 2192 .id = BXT_DPIO_CMN_BC, 2193 { 2194 .bxt.phy = DPIO_PHY0, 2195 }, 2196 }, 2197 }; 2198 2199 static struct i915_power_well glk_power_wells[] = { 2200 { 2201 .name = "always-on", 2202 .always_on = 1, 2203 .domains = POWER_DOMAIN_MASK, 2204 .ops = &i9xx_always_on_power_well_ops, 2205 .id = I915_DISP_PW_ALWAYS_ON, 2206 }, 2207 { 2208 .name = "power well 1", 2209 /* Handled by the DMC firmware */ 2210 .domains = 0, 2211 .ops = &hsw_power_well_ops, 2212 .id = SKL_DISP_PW_1, 2213 { 2214 .hsw.has_fuses = true, 2215 }, 2216 }, 2217 { 2218 .name = "DC off", 2219 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, 2220 .ops = &gen9_dc_off_power_well_ops, 2221 .id = SKL_DISP_PW_DC_OFF, 2222 }, 2223 { 2224 .name = "power well 2", 2225 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2226 .ops = &hsw_power_well_ops, 2227 .id = SKL_DISP_PW_2, 2228 { 2229 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2230 .hsw.has_vga = true, 2231 .hsw.has_fuses = true, 2232 }, 2233 }, 2234 { 2235 .name = "dpio-common-a", 2236 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, 2237 .ops = &bxt_dpio_cmn_power_well_ops, 2238 .id = BXT_DPIO_CMN_A, 2239 { 2240 .bxt.phy = DPIO_PHY1, 2241 }, 2242 }, 2243 { 2244 .name = "dpio-common-b", 2245 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, 2246 .ops = &bxt_dpio_cmn_power_well_ops, 2247 .id = BXT_DPIO_CMN_BC, 2248 { 2249 .bxt.phy = DPIO_PHY0, 2250 }, 2251 }, 2252 { 2253 .name = "dpio-common-c", 2254 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, 2255 .ops = &bxt_dpio_cmn_power_well_ops, 2256 .id = GLK_DPIO_CMN_C, 2257 { 2258 .bxt.phy = DPIO_PHY2, 2259 }, 2260 }, 2261 { 2262 .name = "AUX A", 2263 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, 2264 .ops = &hsw_power_well_ops, 2265 .id = GLK_DISP_PW_AUX_A, 2266 }, 2267 { 2268 .name = "AUX B", 2269 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, 2270 .ops = &hsw_power_well_ops, 2271 .id = GLK_DISP_PW_AUX_B, 2272 }, 2273 { 2274 .name = "AUX C", 2275 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, 2276 .ops = &hsw_power_well_ops, 2277 .id = GLK_DISP_PW_AUX_C, 2278 }, 2279 { 2280 .name = "DDI A IO power well", 2281 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, 2282 .ops = &hsw_power_well_ops, 2283 .id = GLK_DISP_PW_DDI_A, 2284 }, 2285 { 2286 .name = "DDI B IO power well", 2287 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2288 .ops = &hsw_power_well_ops, 2289 .id = SKL_DISP_PW_DDI_B, 2290 }, 2291 { 2292 .name = "DDI C IO power well", 2293 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2294 .ops = &hsw_power_well_ops, 2295 .id = SKL_DISP_PW_DDI_C, 2296 }, 2297 }; 2298 2299 static struct i915_power_well cnl_power_wells[] = { 2300 { 2301 .name = "always-on", 2302 .always_on = 1, 2303 .domains = POWER_DOMAIN_MASK, 2304 .ops = &i9xx_always_on_power_well_ops, 2305 .id = I915_DISP_PW_ALWAYS_ON, 2306 }, 2307 { 2308 .name = "power well 1", 2309 /* Handled by the DMC firmware */ 2310 .domains = 0, 2311 .ops = &hsw_power_well_ops, 2312 .id = SKL_DISP_PW_1, 2313 { 2314 .hsw.has_fuses = true, 2315 }, 2316 }, 2317 { 2318 .name = "AUX A", 2319 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, 2320 .ops = &hsw_power_well_ops, 2321 .id = CNL_DISP_PW_AUX_A, 2322 }, 2323 { 2324 .name = "AUX B", 2325 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, 2326 .ops = &hsw_power_well_ops, 2327 .id = CNL_DISP_PW_AUX_B, 2328 }, 2329 { 2330 .name = "AUX C", 2331 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, 2332 .ops = &hsw_power_well_ops, 2333 .id = CNL_DISP_PW_AUX_C, 2334 }, 2335 { 2336 .name = "AUX D", 2337 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, 2338 .ops = &hsw_power_well_ops, 2339 .id = CNL_DISP_PW_AUX_D, 2340 }, 2341 { 2342 .name = "DC off", 2343 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, 2344 .ops = &gen9_dc_off_power_well_ops, 2345 .id = SKL_DISP_PW_DC_OFF, 2346 }, 2347 { 2348 .name = "power well 2", 2349 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2350 .ops = &hsw_power_well_ops, 2351 .id = SKL_DISP_PW_2, 2352 { 2353 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2354 .hsw.has_vga = true, 2355 .hsw.has_fuses = true, 2356 }, 2357 }, 2358 { 2359 .name = "DDI A IO power well", 2360 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, 2361 .ops = &hsw_power_well_ops, 2362 .id = CNL_DISP_PW_DDI_A, 2363 }, 2364 { 2365 .name = "DDI B IO power well", 2366 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, 2367 .ops = &hsw_power_well_ops, 2368 .id = SKL_DISP_PW_DDI_B, 2369 }, 2370 { 2371 .name = "DDI C IO power well", 2372 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, 2373 .ops = &hsw_power_well_ops, 2374 .id = SKL_DISP_PW_DDI_C, 2375 }, 2376 { 2377 .name = "DDI D IO power well", 2378 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, 2379 .ops = &hsw_power_well_ops, 2380 .id = SKL_DISP_PW_DDI_D, 2381 }, 2382 }; 2383 2384 static int 2385 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2386 int disable_power_well) 2387 { 2388 if (disable_power_well >= 0) 2389 return !!disable_power_well; 2390 2391 return 1; 2392 } 2393 2394 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2395 int enable_dc) 2396 { 2397 uint32_t mask; 2398 int requested_dc; 2399 int max_dc; 2400 2401 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { 2402 max_dc = 2; 2403 mask = 0; 2404 } else if (IS_GEN9_LP(dev_priv)) { 2405 max_dc = 1; 2406 /* 2407 * DC9 has a separate HW flow from the rest of the DC states, 2408 * not depending on the DMC firmware. It's needed by system 2409 * suspend/resume, so allow it unconditionally. 2410 */ 2411 mask = DC_STATE_EN_DC9; 2412 } else { 2413 max_dc = 0; 2414 mask = 0; 2415 } 2416 2417 if (!i915_modparams.disable_power_well) 2418 max_dc = 0; 2419 2420 if (enable_dc >= 0 && enable_dc <= max_dc) { 2421 requested_dc = enable_dc; 2422 } else if (enable_dc == -1) { 2423 requested_dc = max_dc; 2424 } else if (enable_dc > max_dc && enable_dc <= 2) { 2425 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2426 enable_dc, max_dc); 2427 requested_dc = max_dc; 2428 } else { 2429 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2430 requested_dc = max_dc; 2431 } 2432 2433 if (requested_dc > 1) 2434 mask |= DC_STATE_EN_UPTO_DC6; 2435 if (requested_dc > 0) 2436 mask |= DC_STATE_EN_UPTO_DC5; 2437 2438 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2439 2440 return mask; 2441 } 2442 2443 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) 2444 { 2445 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2446 u64 power_well_ids; 2447 int i; 2448 2449 power_well_ids = 0; 2450 for (i = 0; i < power_domains->power_well_count; i++) { 2451 enum i915_power_well_id id = power_domains->power_wells[i].id; 2452 2453 WARN_ON(id >= sizeof(power_well_ids) * 8); 2454 WARN_ON(power_well_ids & BIT_ULL(id)); 2455 power_well_ids |= BIT_ULL(id); 2456 } 2457 } 2458 2459 #define set_power_wells(power_domains, __power_wells) ({ \ 2460 (power_domains)->power_wells = (__power_wells); \ 2461 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2462 }) 2463 2464 /** 2465 * intel_power_domains_init - initializes the power domain structures 2466 * @dev_priv: i915 device instance 2467 * 2468 * Initializes the power domain structures for @dev_priv depending upon the 2469 * supported platform. 2470 */ 2471 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2472 { 2473 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2474 2475 i915_modparams.disable_power_well = 2476 sanitize_disable_power_well_option(dev_priv, 2477 i915_modparams.disable_power_well); 2478 dev_priv->csr.allowed_dc_mask = 2479 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); 2480 2481 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); 2482 2483 mutex_init(&power_domains->lock); 2484 2485 /* 2486 * The enabling order will be from lower to higher indexed wells, 2487 * the disabling order is reversed. 2488 */ 2489 if (IS_HASWELL(dev_priv)) { 2490 set_power_wells(power_domains, hsw_power_wells); 2491 } else if (IS_BROADWELL(dev_priv)) { 2492 set_power_wells(power_domains, bdw_power_wells); 2493 } else if (IS_GEN9_BC(dev_priv)) { 2494 set_power_wells(power_domains, skl_power_wells); 2495 } else if (IS_CANNONLAKE(dev_priv)) { 2496 set_power_wells(power_domains, cnl_power_wells); 2497 } else if (IS_BROXTON(dev_priv)) { 2498 set_power_wells(power_domains, bxt_power_wells); 2499 } else if (IS_GEMINILAKE(dev_priv)) { 2500 set_power_wells(power_domains, glk_power_wells); 2501 } else if (IS_CHERRYVIEW(dev_priv)) { 2502 set_power_wells(power_domains, chv_power_wells); 2503 } else if (IS_VALLEYVIEW(dev_priv)) { 2504 set_power_wells(power_domains, vlv_power_wells); 2505 } else if (IS_I830(dev_priv)) { 2506 set_power_wells(power_domains, i830_power_wells); 2507 } else { 2508 set_power_wells(power_domains, i9xx_always_on_power_well); 2509 } 2510 2511 assert_power_well_ids_unique(dev_priv); 2512 2513 return 0; 2514 } 2515 2516 /** 2517 * intel_power_domains_fini - finalizes the power domain structures 2518 * @dev_priv: i915 device instance 2519 * 2520 * Finalizes the power domain structures for @dev_priv depending upon the 2521 * supported platform. This function also disables runtime pm and ensures that 2522 * the device stays powered up so that the driver can be reloaded. 2523 */ 2524 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2525 { 2526 struct device *kdev = &dev_priv->drm.pdev->dev; 2527 2528 /* 2529 * The i915.ko module is still not prepared to be loaded when 2530 * the power well is not enabled, so just enable it in case 2531 * we're going to unload/reload. 2532 * The following also reacquires the RPM reference the core passed 2533 * to the driver during loading, which is dropped in 2534 * intel_runtime_pm_enable(). We have to hand back the control of the 2535 * device to the core with this reference held. 2536 */ 2537 intel_display_set_init_power(dev_priv, true); 2538 2539 /* Remove the refcount we took to keep power well support disabled. */ 2540 if (!i915_modparams.disable_power_well) 2541 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2542 2543 /* 2544 * Remove the refcount we took in intel_runtime_pm_enable() in case 2545 * the platform doesn't support runtime PM. 2546 */ 2547 if (!HAS_RUNTIME_PM(dev_priv)) 2548 pm_runtime_put(kdev); 2549 } 2550 2551 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2552 { 2553 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2554 struct i915_power_well *power_well; 2555 2556 mutex_lock(&power_domains->lock); 2557 for_each_power_well(dev_priv, power_well) { 2558 power_well->ops->sync_hw(dev_priv, power_well); 2559 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2560 power_well); 2561 } 2562 mutex_unlock(&power_domains->lock); 2563 } 2564 2565 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 2566 { 2567 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 2568 POSTING_READ(DBUF_CTL); 2569 2570 udelay(10); 2571 2572 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 2573 DRM_ERROR("DBuf power enable timeout\n"); 2574 } 2575 2576 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 2577 { 2578 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 2579 POSTING_READ(DBUF_CTL); 2580 2581 udelay(10); 2582 2583 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 2584 DRM_ERROR("DBuf power disable timeout!\n"); 2585 } 2586 2587 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2588 bool resume) 2589 { 2590 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2591 struct i915_power_well *well; 2592 uint32_t val; 2593 2594 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2595 2596 /* enable PCH reset handshake */ 2597 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2598 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2599 2600 /* enable PG1 and Misc I/O */ 2601 mutex_lock(&power_domains->lock); 2602 2603 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2604 intel_power_well_enable(dev_priv, well); 2605 2606 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2607 intel_power_well_enable(dev_priv, well); 2608 2609 mutex_unlock(&power_domains->lock); 2610 2611 skl_init_cdclk(dev_priv); 2612 2613 gen9_dbuf_enable(dev_priv); 2614 2615 if (resume && dev_priv->csr.dmc_payload) 2616 intel_csr_load_program(dev_priv); 2617 } 2618 2619 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2620 { 2621 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2622 struct i915_power_well *well; 2623 2624 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2625 2626 gen9_dbuf_disable(dev_priv); 2627 2628 skl_uninit_cdclk(dev_priv); 2629 2630 /* The spec doesn't call for removing the reset handshake flag */ 2631 /* disable PG1 and Misc I/O */ 2632 2633 mutex_lock(&power_domains->lock); 2634 2635 /* 2636 * BSpec says to keep the MISC IO power well enabled here, only 2637 * remove our request for power well 1. 2638 * Note that even though the driver's request is removed power well 1 2639 * may stay enabled after this due to DMC's own request on it. 2640 */ 2641 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2642 intel_power_well_disable(dev_priv, well); 2643 2644 mutex_unlock(&power_domains->lock); 2645 2646 usleep_range(10, 30); /* 10 us delay per Bspec */ 2647 } 2648 2649 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2650 bool resume) 2651 { 2652 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2653 struct i915_power_well *well; 2654 uint32_t val; 2655 2656 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2657 2658 /* 2659 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2660 * or else the reset will hang because there is no PCH to respond. 2661 * Move the handshake programming to initialization sequence. 2662 * Previously was left up to BIOS. 2663 */ 2664 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2665 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2666 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2667 2668 /* Enable PG1 */ 2669 mutex_lock(&power_domains->lock); 2670 2671 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2672 intel_power_well_enable(dev_priv, well); 2673 2674 mutex_unlock(&power_domains->lock); 2675 2676 bxt_init_cdclk(dev_priv); 2677 2678 gen9_dbuf_enable(dev_priv); 2679 2680 if (resume && dev_priv->csr.dmc_payload) 2681 intel_csr_load_program(dev_priv); 2682 } 2683 2684 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2685 { 2686 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2687 struct i915_power_well *well; 2688 2689 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2690 2691 gen9_dbuf_disable(dev_priv); 2692 2693 bxt_uninit_cdclk(dev_priv); 2694 2695 /* The spec doesn't call for removing the reset handshake flag */ 2696 2697 /* 2698 * Disable PW1 (PG1). 2699 * Note that even though the driver's request is removed power well 1 2700 * may stay enabled after this due to DMC's own request on it. 2701 */ 2702 mutex_lock(&power_domains->lock); 2703 2704 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2705 intel_power_well_disable(dev_priv, well); 2706 2707 mutex_unlock(&power_domains->lock); 2708 2709 usleep_range(10, 30); /* 10 us delay per Bspec */ 2710 } 2711 2712 enum { 2713 PROCMON_0_85V_DOT_0, 2714 PROCMON_0_95V_DOT_0, 2715 PROCMON_0_95V_DOT_1, 2716 PROCMON_1_05V_DOT_0, 2717 PROCMON_1_05V_DOT_1, 2718 }; 2719 2720 static const struct cnl_procmon { 2721 u32 dw1, dw9, dw10; 2722 } cnl_procmon_values[] = { 2723 [PROCMON_0_85V_DOT_0] = 2724 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 2725 [PROCMON_0_95V_DOT_0] = 2726 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 2727 [PROCMON_0_95V_DOT_1] = 2728 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 2729 [PROCMON_1_05V_DOT_0] = 2730 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 2731 [PROCMON_1_05V_DOT_1] = 2732 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 2733 }; 2734 2735 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv) 2736 { 2737 const struct cnl_procmon *procmon; 2738 u32 val; 2739 2740 val = I915_READ(CNL_PORT_COMP_DW3); 2741 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 2742 default: 2743 MISSING_CASE(val); 2744 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 2745 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 2746 break; 2747 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 2748 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 2749 break; 2750 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 2751 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 2752 break; 2753 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 2754 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 2755 break; 2756 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 2757 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 2758 break; 2759 } 2760 2761 val = I915_READ(CNL_PORT_COMP_DW1); 2762 val &= ~((0xff << 16) | 0xff); 2763 val |= procmon->dw1; 2764 I915_WRITE(CNL_PORT_COMP_DW1, val); 2765 2766 I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9); 2767 I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10); 2768 } 2769 2770 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) 2771 { 2772 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2773 struct i915_power_well *well; 2774 u32 val; 2775 2776 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2777 2778 /* 1. Enable PCH Reset Handshake */ 2779 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2780 val |= RESET_PCH_HANDSHAKE_ENABLE; 2781 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2782 2783 /* 2. Enable Comp */ 2784 val = I915_READ(CHICKEN_MISC_2); 2785 val &= ~CNL_COMP_PWR_DOWN; 2786 I915_WRITE(CHICKEN_MISC_2, val); 2787 2788 cnl_set_procmon_ref_values(dev_priv); 2789 2790 val = I915_READ(CNL_PORT_COMP_DW0); 2791 val |= COMP_INIT; 2792 I915_WRITE(CNL_PORT_COMP_DW0, val); 2793 2794 /* 3. */ 2795 val = I915_READ(CNL_PORT_CL1CM_DW5); 2796 val |= CL_POWER_DOWN_ENABLE; 2797 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2798 2799 /* 2800 * 4. Enable Power Well 1 (PG1). 2801 * The AUX IO power wells will be enabled on demand. 2802 */ 2803 mutex_lock(&power_domains->lock); 2804 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2805 intel_power_well_enable(dev_priv, well); 2806 mutex_unlock(&power_domains->lock); 2807 2808 /* 5. Enable CD clock */ 2809 cnl_init_cdclk(dev_priv); 2810 2811 /* 6. Enable DBUF */ 2812 gen9_dbuf_enable(dev_priv); 2813 2814 if (resume && dev_priv->csr.dmc_payload) 2815 intel_csr_load_program(dev_priv); 2816 } 2817 2818 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) 2819 { 2820 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2821 struct i915_power_well *well; 2822 u32 val; 2823 2824 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2825 2826 /* 1. Disable all display engine functions -> aready done */ 2827 2828 /* 2. Disable DBUF */ 2829 gen9_dbuf_disable(dev_priv); 2830 2831 /* 3. Disable CD clock */ 2832 cnl_uninit_cdclk(dev_priv); 2833 2834 /* 2835 * 4. Disable Power Well 1 (PG1). 2836 * The AUX IO power wells are toggled on demand, so they are already 2837 * disabled at this point. 2838 */ 2839 mutex_lock(&power_domains->lock); 2840 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2841 intel_power_well_disable(dev_priv, well); 2842 mutex_unlock(&power_domains->lock); 2843 2844 usleep_range(10, 30); /* 10 us delay per Bspec */ 2845 2846 /* 5. Disable Comp */ 2847 val = I915_READ(CHICKEN_MISC_2); 2848 val |= CNL_COMP_PWR_DOWN; 2849 I915_WRITE(CHICKEN_MISC_2, val); 2850 } 2851 2852 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2853 { 2854 struct i915_power_well *cmn_bc = 2855 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2856 struct i915_power_well *cmn_d = 2857 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2858 2859 /* 2860 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2861 * workaround never ever read DISPLAY_PHY_CONTROL, and 2862 * instead maintain a shadow copy ourselves. Use the actual 2863 * power well state and lane status to reconstruct the 2864 * expected initial value. 2865 */ 2866 dev_priv->chv_phy_control = 2867 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2868 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2869 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2870 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2871 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2872 2873 /* 2874 * If all lanes are disabled we leave the override disabled 2875 * with all power down bits cleared to match the state we 2876 * would use after disabling the port. Otherwise enable the 2877 * override and set the lane powerdown bits accding to the 2878 * current lane status. 2879 */ 2880 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2881 uint32_t status = I915_READ(DPLL(PIPE_A)); 2882 unsigned int mask; 2883 2884 mask = status & DPLL_PORTB_READY_MASK; 2885 if (mask == 0xf) 2886 mask = 0x0; 2887 else 2888 dev_priv->chv_phy_control |= 2889 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2890 2891 dev_priv->chv_phy_control |= 2892 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2893 2894 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2895 if (mask == 0xf) 2896 mask = 0x0; 2897 else 2898 dev_priv->chv_phy_control |= 2899 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2900 2901 dev_priv->chv_phy_control |= 2902 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2903 2904 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2905 2906 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2907 } else { 2908 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2909 } 2910 2911 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2912 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2913 unsigned int mask; 2914 2915 mask = status & DPLL_PORTD_READY_MASK; 2916 2917 if (mask == 0xf) 2918 mask = 0x0; 2919 else 2920 dev_priv->chv_phy_control |= 2921 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2922 2923 dev_priv->chv_phy_control |= 2924 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2925 2926 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2927 2928 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2929 } else { 2930 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2931 } 2932 2933 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2934 2935 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2936 dev_priv->chv_phy_control); 2937 } 2938 2939 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2940 { 2941 struct i915_power_well *cmn = 2942 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2943 struct i915_power_well *disp2d = 2944 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2945 2946 /* If the display might be already active skip this */ 2947 if (cmn->ops->is_enabled(dev_priv, cmn) && 2948 disp2d->ops->is_enabled(dev_priv, disp2d) && 2949 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2950 return; 2951 2952 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2953 2954 /* cmnlane needs DPLL registers */ 2955 disp2d->ops->enable(dev_priv, disp2d); 2956 2957 /* 2958 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2959 * Need to assert and de-assert PHY SB reset by gating the 2960 * common lane power, then un-gating it. 2961 * Simply ungating isn't enough to reset the PHY enough to get 2962 * ports and lanes running. 2963 */ 2964 cmn->ops->disable(dev_priv, cmn); 2965 } 2966 2967 /** 2968 * intel_power_domains_init_hw - initialize hardware power domain state 2969 * @dev_priv: i915 device instance 2970 * @resume: Called from resume code paths or not 2971 * 2972 * This function initializes the hardware power domain state and enables all 2973 * power wells belonging to the INIT power domain. Power wells in other 2974 * domains (and not in the INIT domain) are referenced or disabled during the 2975 * modeset state HW readout. After that the reference count of each power well 2976 * must match its HW enabled state, see intel_power_domains_verify_state(). 2977 */ 2978 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2979 { 2980 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2981 2982 power_domains->initializing = true; 2983 2984 if (IS_CANNONLAKE(dev_priv)) { 2985 cnl_display_core_init(dev_priv, resume); 2986 } else if (IS_GEN9_BC(dev_priv)) { 2987 skl_display_core_init(dev_priv, resume); 2988 } else if (IS_GEN9_LP(dev_priv)) { 2989 bxt_display_core_init(dev_priv, resume); 2990 } else if (IS_CHERRYVIEW(dev_priv)) { 2991 mutex_lock(&power_domains->lock); 2992 chv_phy_control_init(dev_priv); 2993 mutex_unlock(&power_domains->lock); 2994 } else if (IS_VALLEYVIEW(dev_priv)) { 2995 mutex_lock(&power_domains->lock); 2996 vlv_cmnlane_wa(dev_priv); 2997 mutex_unlock(&power_domains->lock); 2998 } 2999 3000 /* For now, we need the power well to be always enabled. */ 3001 intel_display_set_init_power(dev_priv, true); 3002 /* Disable power support if the user asked so. */ 3003 if (!i915_modparams.disable_power_well) 3004 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3005 intel_power_domains_sync_hw(dev_priv); 3006 power_domains->initializing = false; 3007 } 3008 3009 /** 3010 * intel_power_domains_suspend - suspend power domain state 3011 * @dev_priv: i915 device instance 3012 * 3013 * This function prepares the hardware power domain state before entering 3014 * system suspend. It must be paired with intel_power_domains_init_hw(). 3015 */ 3016 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 3017 { 3018 /* 3019 * Even if power well support was disabled we still want to disable 3020 * power wells while we are system suspended. 3021 */ 3022 if (!i915_modparams.disable_power_well) 3023 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3024 3025 if (IS_CANNONLAKE(dev_priv)) 3026 cnl_display_core_uninit(dev_priv); 3027 else if (IS_GEN9_BC(dev_priv)) 3028 skl_display_core_uninit(dev_priv); 3029 else if (IS_GEN9_LP(dev_priv)) 3030 bxt_display_core_uninit(dev_priv); 3031 } 3032 3033 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) 3034 { 3035 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3036 struct i915_power_well *power_well; 3037 3038 for_each_power_well(dev_priv, power_well) { 3039 enum intel_display_power_domain domain; 3040 3041 DRM_DEBUG_DRIVER("%-25s %d\n", 3042 power_well->name, power_well->count); 3043 3044 for_each_power_domain(domain, power_well->domains) 3045 DRM_DEBUG_DRIVER(" %-23s %d\n", 3046 intel_display_power_domain_str(domain), 3047 power_domains->domain_use_count[domain]); 3048 } 3049 } 3050 3051 /** 3052 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 3053 * @dev_priv: i915 device instance 3054 * 3055 * Verify if the reference count of each power well matches its HW enabled 3056 * state and the total refcount of the domains it belongs to. This must be 3057 * called after modeset HW state sanitization, which is responsible for 3058 * acquiring reference counts for any power wells in use and disabling the 3059 * ones left on by BIOS but not required by any active output. 3060 */ 3061 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) 3062 { 3063 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3064 struct i915_power_well *power_well; 3065 bool dump_domain_info; 3066 3067 mutex_lock(&power_domains->lock); 3068 3069 dump_domain_info = false; 3070 for_each_power_well(dev_priv, power_well) { 3071 enum intel_display_power_domain domain; 3072 int domains_count; 3073 bool enabled; 3074 3075 /* 3076 * Power wells not belonging to any domain (like the MISC_IO 3077 * and PW1 power wells) are under FW control, so ignore them, 3078 * since their state can change asynchronously. 3079 */ 3080 if (!power_well->domains) 3081 continue; 3082 3083 enabled = power_well->ops->is_enabled(dev_priv, power_well); 3084 if ((power_well->count || power_well->always_on) != enabled) 3085 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", 3086 power_well->name, power_well->count, enabled); 3087 3088 domains_count = 0; 3089 for_each_power_domain(domain, power_well->domains) 3090 domains_count += power_domains->domain_use_count[domain]; 3091 3092 if (power_well->count != domains_count) { 3093 DRM_ERROR("power well %s refcount/domain refcount mismatch " 3094 "(refcount %d/domains refcount %d)\n", 3095 power_well->name, power_well->count, 3096 domains_count); 3097 dump_domain_info = true; 3098 } 3099 } 3100 3101 if (dump_domain_info) { 3102 static bool dumped; 3103 3104 if (!dumped) { 3105 intel_power_domains_dump_info(dev_priv); 3106 dumped = true; 3107 } 3108 } 3109 3110 mutex_unlock(&power_domains->lock); 3111 } 3112 3113 /** 3114 * intel_runtime_pm_get - grab a runtime pm reference 3115 * @dev_priv: i915 device instance 3116 * 3117 * This function grabs a device-level runtime pm reference (mostly used for GEM 3118 * code to ensure the GTT or GT is on) and ensures that it is powered up. 3119 * 3120 * Any runtime pm reference obtained by this function must have a symmetric 3121 * call to intel_runtime_pm_put() to release the reference again. 3122 */ 3123 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 3124 { 3125 struct pci_dev *pdev = dev_priv->drm.pdev; 3126 struct device *kdev = &pdev->dev; 3127 int ret; 3128 3129 ret = pm_runtime_get_sync(kdev); 3130 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3131 3132 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3133 assert_rpm_wakelock_held(dev_priv); 3134 } 3135 3136 /** 3137 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 3138 * @dev_priv: i915 device instance 3139 * 3140 * This function grabs a device-level runtime pm reference if the device is 3141 * already in use and ensures that it is powered up. 3142 * 3143 * Any runtime pm reference obtained by this function must have a symmetric 3144 * call to intel_runtime_pm_put() to release the reference again. 3145 */ 3146 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 3147 { 3148 struct pci_dev *pdev = dev_priv->drm.pdev; 3149 struct device *kdev = &pdev->dev; 3150 3151 if (IS_ENABLED(CONFIG_PM)) { 3152 int ret = pm_runtime_get_if_in_use(kdev); 3153 3154 /* 3155 * In cases runtime PM is disabled by the RPM core and we get 3156 * an -EINVAL return value we are not supposed to call this 3157 * function, since the power state is undefined. This applies 3158 * atm to the late/early system suspend/resume handlers. 3159 */ 3160 WARN_ONCE(ret < 0, 3161 "pm_runtime_get_if_in_use() failed: %d\n", ret); 3162 if (ret <= 0) 3163 return false; 3164 } 3165 3166 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3167 assert_rpm_wakelock_held(dev_priv); 3168 3169 return true; 3170 } 3171 3172 /** 3173 * intel_runtime_pm_get_noresume - grab a runtime pm reference 3174 * @dev_priv: i915 device instance 3175 * 3176 * This function grabs a device-level runtime pm reference (mostly used for GEM 3177 * code to ensure the GTT or GT is on). 3178 * 3179 * It will _not_ power up the device but instead only check that it's powered 3180 * on. Therefore it is only valid to call this functions from contexts where 3181 * the device is known to be powered up and where trying to power it up would 3182 * result in hilarity and deadlocks. That pretty much means only the system 3183 * suspend/resume code where this is used to grab runtime pm references for 3184 * delayed setup down in work items. 3185 * 3186 * Any runtime pm reference obtained by this function must have a symmetric 3187 * call to intel_runtime_pm_put() to release the reference again. 3188 */ 3189 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 3190 { 3191 struct pci_dev *pdev = dev_priv->drm.pdev; 3192 struct device *kdev = &pdev->dev; 3193 3194 assert_rpm_wakelock_held(dev_priv); 3195 pm_runtime_get_noresume(kdev); 3196 3197 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3198 } 3199 3200 /** 3201 * intel_runtime_pm_put - release a runtime pm reference 3202 * @dev_priv: i915 device instance 3203 * 3204 * This function drops the device-level runtime pm reference obtained by 3205 * intel_runtime_pm_get() and might power down the corresponding 3206 * hardware block right away if this is the last reference. 3207 */ 3208 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 3209 { 3210 struct pci_dev *pdev = dev_priv->drm.pdev; 3211 struct device *kdev = &pdev->dev; 3212 3213 assert_rpm_wakelock_held(dev_priv); 3214 atomic_dec(&dev_priv->runtime_pm.wakeref_count); 3215 3216 pm_runtime_mark_last_busy(kdev); 3217 pm_runtime_put_autosuspend(kdev); 3218 } 3219 3220 /** 3221 * intel_runtime_pm_enable - enable runtime pm 3222 * @dev_priv: i915 device instance 3223 * 3224 * This function enables runtime pm at the end of the driver load sequence. 3225 * 3226 * Note that this function does currently not enable runtime pm for the 3227 * subordinate display power domains. That is only done on the first modeset 3228 * using intel_display_set_init_power(). 3229 */ 3230 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 3231 { 3232 struct pci_dev *pdev = dev_priv->drm.pdev; 3233 struct device *kdev = &pdev->dev; 3234 3235 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */ 3236 pm_runtime_mark_last_busy(kdev); 3237 3238 /* 3239 * Take a permanent reference to disable the RPM functionality and drop 3240 * it only when unloading the driver. Use the low level get/put helpers, 3241 * so the driver's own RPM reference tracking asserts also work on 3242 * platforms without RPM support. 3243 */ 3244 if (!HAS_RUNTIME_PM(dev_priv)) { 3245 int ret; 3246 3247 pm_runtime_dont_use_autosuspend(kdev); 3248 ret = pm_runtime_get_sync(kdev); 3249 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3250 } else { 3251 pm_runtime_use_autosuspend(kdev); 3252 } 3253 3254 /* 3255 * The core calls the driver load handler with an RPM reference held. 3256 * We drop that here and will reacquire it during unloading in 3257 * intel_power_domains_fini(). 3258 */ 3259 pm_runtime_put_autosuspend(kdev); 3260 } 3261