1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 53 enum i915_power_well_id power_well_id); 54 55 static struct i915_power_well * 56 lookup_power_well(struct drm_i915_private *dev_priv, 57 enum i915_power_well_id power_well_id); 58 59 const char * 60 intel_display_power_domain_str(enum intel_display_power_domain domain) 61 { 62 switch (domain) { 63 case POWER_DOMAIN_PIPE_A: 64 return "PIPE_A"; 65 case POWER_DOMAIN_PIPE_B: 66 return "PIPE_B"; 67 case POWER_DOMAIN_PIPE_C: 68 return "PIPE_C"; 69 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 70 return "PIPE_A_PANEL_FITTER"; 71 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 72 return "PIPE_B_PANEL_FITTER"; 73 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 74 return "PIPE_C_PANEL_FITTER"; 75 case POWER_DOMAIN_TRANSCODER_A: 76 return "TRANSCODER_A"; 77 case POWER_DOMAIN_TRANSCODER_B: 78 return "TRANSCODER_B"; 79 case POWER_DOMAIN_TRANSCODER_C: 80 return "TRANSCODER_C"; 81 case POWER_DOMAIN_TRANSCODER_EDP: 82 return "TRANSCODER_EDP"; 83 case POWER_DOMAIN_TRANSCODER_DSI_A: 84 return "TRANSCODER_DSI_A"; 85 case POWER_DOMAIN_TRANSCODER_DSI_C: 86 return "TRANSCODER_DSI_C"; 87 case POWER_DOMAIN_PORT_DDI_A_LANES: 88 return "PORT_DDI_A_LANES"; 89 case POWER_DOMAIN_PORT_DDI_B_LANES: 90 return "PORT_DDI_B_LANES"; 91 case POWER_DOMAIN_PORT_DDI_C_LANES: 92 return "PORT_DDI_C_LANES"; 93 case POWER_DOMAIN_PORT_DDI_D_LANES: 94 return "PORT_DDI_D_LANES"; 95 case POWER_DOMAIN_PORT_DDI_E_LANES: 96 return "PORT_DDI_E_LANES"; 97 case POWER_DOMAIN_PORT_DDI_F_LANES: 98 return "PORT_DDI_F_LANES"; 99 case POWER_DOMAIN_PORT_DDI_A_IO: 100 return "PORT_DDI_A_IO"; 101 case POWER_DOMAIN_PORT_DDI_B_IO: 102 return "PORT_DDI_B_IO"; 103 case POWER_DOMAIN_PORT_DDI_C_IO: 104 return "PORT_DDI_C_IO"; 105 case POWER_DOMAIN_PORT_DDI_D_IO: 106 return "PORT_DDI_D_IO"; 107 case POWER_DOMAIN_PORT_DDI_E_IO: 108 return "PORT_DDI_E_IO"; 109 case POWER_DOMAIN_PORT_DDI_F_IO: 110 return "PORT_DDI_F_IO"; 111 case POWER_DOMAIN_PORT_DSI: 112 return "PORT_DSI"; 113 case POWER_DOMAIN_PORT_CRT: 114 return "PORT_CRT"; 115 case POWER_DOMAIN_PORT_OTHER: 116 return "PORT_OTHER"; 117 case POWER_DOMAIN_VGA: 118 return "VGA"; 119 case POWER_DOMAIN_AUDIO: 120 return "AUDIO"; 121 case POWER_DOMAIN_PLLS: 122 return "PLLS"; 123 case POWER_DOMAIN_AUX_A: 124 return "AUX_A"; 125 case POWER_DOMAIN_AUX_B: 126 return "AUX_B"; 127 case POWER_DOMAIN_AUX_C: 128 return "AUX_C"; 129 case POWER_DOMAIN_AUX_D: 130 return "AUX_D"; 131 case POWER_DOMAIN_AUX_F: 132 return "AUX_F"; 133 case POWER_DOMAIN_GMBUS: 134 return "GMBUS"; 135 case POWER_DOMAIN_INIT: 136 return "INIT"; 137 case POWER_DOMAIN_MODESET: 138 return "MODESET"; 139 case POWER_DOMAIN_GT_IRQ: 140 return "GT_IRQ"; 141 default: 142 MISSING_CASE(domain); 143 return "?"; 144 } 145 } 146 147 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 148 struct i915_power_well *power_well) 149 { 150 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 151 power_well->ops->enable(dev_priv, power_well); 152 power_well->hw_enabled = true; 153 } 154 155 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 156 struct i915_power_well *power_well) 157 { 158 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 159 power_well->hw_enabled = false; 160 power_well->ops->disable(dev_priv, power_well); 161 } 162 163 static void intel_power_well_get(struct drm_i915_private *dev_priv, 164 struct i915_power_well *power_well) 165 { 166 if (!power_well->count++) 167 intel_power_well_enable(dev_priv, power_well); 168 } 169 170 static void intel_power_well_put(struct drm_i915_private *dev_priv, 171 struct i915_power_well *power_well) 172 { 173 WARN(!power_well->count, "Use count on power well %s is already zero", 174 power_well->name); 175 176 if (!--power_well->count) 177 intel_power_well_disable(dev_priv, power_well); 178 } 179 180 /** 181 * __intel_display_power_is_enabled - unlocked check for a power domain 182 * @dev_priv: i915 device instance 183 * @domain: power domain to check 184 * 185 * This is the unlocked version of intel_display_power_is_enabled() and should 186 * only be used from error capture and recovery code where deadlocks are 187 * possible. 188 * 189 * Returns: 190 * True when the power domain is enabled, false otherwise. 191 */ 192 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 193 enum intel_display_power_domain domain) 194 { 195 struct i915_power_well *power_well; 196 bool is_enabled; 197 198 if (dev_priv->runtime_pm.suspended) 199 return false; 200 201 is_enabled = true; 202 203 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { 204 if (power_well->always_on) 205 continue; 206 207 if (!power_well->hw_enabled) { 208 is_enabled = false; 209 break; 210 } 211 } 212 213 return is_enabled; 214 } 215 216 /** 217 * intel_display_power_is_enabled - check for a power domain 218 * @dev_priv: i915 device instance 219 * @domain: power domain to check 220 * 221 * This function can be used to check the hw power domain state. It is mostly 222 * used in hardware state readout functions. Everywhere else code should rely 223 * upon explicit power domain reference counting to ensure that the hardware 224 * block is powered up before accessing it. 225 * 226 * Callers must hold the relevant modesetting locks to ensure that concurrent 227 * threads can't disable the power well while the caller tries to read a few 228 * registers. 229 * 230 * Returns: 231 * True when the power domain is enabled, false otherwise. 232 */ 233 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 234 enum intel_display_power_domain domain) 235 { 236 struct i915_power_domains *power_domains; 237 bool ret; 238 239 power_domains = &dev_priv->power_domains; 240 241 mutex_lock(&power_domains->lock); 242 ret = __intel_display_power_is_enabled(dev_priv, domain); 243 mutex_unlock(&power_domains->lock); 244 245 return ret; 246 } 247 248 /** 249 * intel_display_set_init_power - set the initial power domain state 250 * @dev_priv: i915 device instance 251 * @enable: whether to enable or disable the initial power domain state 252 * 253 * For simplicity our driver load/unload and system suspend/resume code assumes 254 * that all power domains are always enabled. This functions controls the state 255 * of this little hack. While the initial power domain state is enabled runtime 256 * pm is effectively disabled. 257 */ 258 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 259 bool enable) 260 { 261 if (dev_priv->power_domains.init_power_on == enable) 262 return; 263 264 if (enable) 265 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 266 else 267 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 268 269 dev_priv->power_domains.init_power_on = enable; 270 } 271 272 /* 273 * Starting with Haswell, we have a "Power Down Well" that can be turned off 274 * when not needed anymore. We have 4 registers that can request the power well 275 * to be enabled, and it will only be disabled if none of the registers is 276 * requesting it to be enabled. 277 */ 278 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 279 u8 irq_pipe_mask, bool has_vga) 280 { 281 struct pci_dev *pdev = dev_priv->drm.pdev; 282 283 /* 284 * After we re-enable the power well, if we touch VGA register 0x3d5 285 * we'll get unclaimed register interrupts. This stops after we write 286 * anything to the VGA MSR register. The vgacon module uses this 287 * register all the time, so if we unbind our driver and, as a 288 * consequence, bind vgacon, we'll get stuck in an infinite loop at 289 * console_unlock(). So make here we touch the VGA MSR register, making 290 * sure vgacon can keep working normally without triggering interrupts 291 * and error messages. 292 */ 293 if (has_vga) { 294 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 295 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 296 vga_put(pdev, VGA_RSRC_LEGACY_IO); 297 } 298 299 if (irq_pipe_mask) 300 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 301 } 302 303 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 304 u8 irq_pipe_mask) 305 { 306 if (irq_pipe_mask) 307 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 308 } 309 310 311 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 312 struct i915_power_well *power_well) 313 { 314 enum i915_power_well_id id = power_well->id; 315 316 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 317 WARN_ON(intel_wait_for_register(dev_priv, 318 HSW_PWR_WELL_CTL_DRIVER(id), 319 HSW_PWR_WELL_CTL_STATE(id), 320 HSW_PWR_WELL_CTL_STATE(id), 321 1)); 322 } 323 324 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 325 enum i915_power_well_id id) 326 { 327 u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); 328 u32 ret; 329 330 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; 331 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; 332 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; 333 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; 334 335 return ret; 336 } 337 338 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 339 struct i915_power_well *power_well) 340 { 341 enum i915_power_well_id id = power_well->id; 342 bool disabled; 343 u32 reqs; 344 345 /* 346 * Bspec doesn't require waiting for PWs to get disabled, but still do 347 * this for paranoia. The known cases where a PW will be forced on: 348 * - a KVMR request on any power well via the KVMR request register 349 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 350 * DEBUG request registers 351 * Skip the wait in case any of the request bits are set and print a 352 * diagnostic message. 353 */ 354 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 355 HSW_PWR_WELL_CTL_STATE(id))) || 356 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); 357 if (disabled) 358 return; 359 360 DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 361 power_well->name, 362 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 363 } 364 365 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 366 enum skl_power_gate pg) 367 { 368 /* Timeout 5us for PG#0, for other PGs 1us */ 369 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, 370 SKL_FUSE_PG_DIST_STATUS(pg), 371 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 372 } 373 374 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 375 struct i915_power_well *power_well) 376 { 377 enum i915_power_well_id id = power_well->id; 378 bool wait_fuses = power_well->hsw.has_fuses; 379 enum skl_power_gate uninitialized_var(pg); 380 u32 val; 381 382 if (wait_fuses) { 383 pg = SKL_PW_TO_PG(id); 384 /* 385 * For PW1 we have to wait both for the PW0/PG0 fuse state 386 * before enabling the power well and PW1/PG1's own fuse 387 * state after the enabling. For all other power wells with 388 * fuses we only have to wait for that PW/PG's fuse state 389 * after the enabling. 390 */ 391 if (pg == SKL_PG1) 392 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 393 } 394 395 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 396 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); 397 hsw_wait_for_power_well_enable(dev_priv, power_well); 398 399 /* Display WA #1178: cnl */ 400 if (IS_CANNONLAKE(dev_priv) && 401 (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C || 402 id == CNL_DISP_PW_AUX_D || id == CNL_DISP_PW_AUX_F)) { 403 val = I915_READ(CNL_AUX_ANAOVRD1(id)); 404 val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; 405 I915_WRITE(CNL_AUX_ANAOVRD1(id), val); 406 } 407 408 if (wait_fuses) 409 gen9_wait_for_power_well_fuses(dev_priv, pg); 410 411 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, 412 power_well->hsw.has_vga); 413 } 414 415 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 416 struct i915_power_well *power_well) 417 { 418 enum i915_power_well_id id = power_well->id; 419 u32 val; 420 421 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); 422 423 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 424 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), 425 val & ~HSW_PWR_WELL_CTL_REQ(id)); 426 hsw_wait_for_power_well_disable(dev_priv, power_well); 427 } 428 429 /* 430 * We should only use the power well if we explicitly asked the hardware to 431 * enable it, so check if it's enabled and also check if we've requested it to 432 * be enabled. 433 */ 434 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 435 struct i915_power_well *power_well) 436 { 437 enum i915_power_well_id id = power_well->id; 438 u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); 439 440 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; 441 } 442 443 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 444 { 445 enum i915_power_well_id id = SKL_DISP_PW_2; 446 447 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 448 "DC9 already programmed to be enabled.\n"); 449 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 450 "DC5 still not disabled to enable DC9.\n"); 451 WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & 452 HSW_PWR_WELL_CTL_REQ(id), 453 "Power well 2 on.\n"); 454 WARN_ONCE(intel_irqs_enabled(dev_priv), 455 "Interrupts not disabled yet.\n"); 456 457 /* 458 * TODO: check for the following to verify the conditions to enter DC9 459 * state are satisfied: 460 * 1] Check relevant display engine registers to verify if mode set 461 * disable sequence was followed. 462 * 2] Check if display uninitialize sequence is initialized. 463 */ 464 } 465 466 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 467 { 468 WARN_ONCE(intel_irqs_enabled(dev_priv), 469 "Interrupts not disabled yet.\n"); 470 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 471 "DC5 still not disabled.\n"); 472 473 /* 474 * TODO: check for the following to verify DC9 state was indeed 475 * entered before programming to disable it: 476 * 1] Check relevant display engine registers to verify if mode 477 * set disable sequence was followed. 478 * 2] Check if display uninitialize sequence is initialized. 479 */ 480 } 481 482 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 483 u32 state) 484 { 485 int rewrites = 0; 486 int rereads = 0; 487 u32 v; 488 489 I915_WRITE(DC_STATE_EN, state); 490 491 /* It has been observed that disabling the dc6 state sometimes 492 * doesn't stick and dmc keeps returning old value. Make sure 493 * the write really sticks enough times and also force rewrite until 494 * we are confident that state is exactly what we want. 495 */ 496 do { 497 v = I915_READ(DC_STATE_EN); 498 499 if (v != state) { 500 I915_WRITE(DC_STATE_EN, state); 501 rewrites++; 502 rereads = 0; 503 } else if (rereads++ > 5) { 504 break; 505 } 506 507 } while (rewrites < 100); 508 509 if (v != state) 510 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 511 state, v); 512 513 /* Most of the times we need one retry, avoid spam */ 514 if (rewrites > 1) 515 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 516 state, rewrites); 517 } 518 519 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 520 { 521 u32 mask; 522 523 mask = DC_STATE_EN_UPTO_DC5; 524 if (IS_GEN9_LP(dev_priv)) 525 mask |= DC_STATE_EN_DC9; 526 else 527 mask |= DC_STATE_EN_UPTO_DC6; 528 529 return mask; 530 } 531 532 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 533 { 534 u32 val; 535 536 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 537 538 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 539 dev_priv->csr.dc_state, val); 540 dev_priv->csr.dc_state = val; 541 } 542 543 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 544 { 545 uint32_t val; 546 uint32_t mask; 547 548 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 549 state &= dev_priv->csr.allowed_dc_mask; 550 551 val = I915_READ(DC_STATE_EN); 552 mask = gen9_dc_mask(dev_priv); 553 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 554 val & mask, state); 555 556 /* Check if DMC is ignoring our DC state requests */ 557 if ((val & mask) != dev_priv->csr.dc_state) 558 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 559 dev_priv->csr.dc_state, val & mask); 560 561 val &= ~mask; 562 val |= state; 563 564 gen9_write_dc_state(dev_priv, val); 565 566 dev_priv->csr.dc_state = val & mask; 567 } 568 569 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 570 { 571 assert_can_enable_dc9(dev_priv); 572 573 DRM_DEBUG_KMS("Enabling DC9\n"); 574 575 intel_power_sequencer_reset(dev_priv); 576 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 577 } 578 579 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 580 { 581 assert_can_disable_dc9(dev_priv); 582 583 DRM_DEBUG_KMS("Disabling DC9\n"); 584 585 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 586 587 intel_pps_unlock_regs_wa(dev_priv); 588 } 589 590 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 591 { 592 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 593 "CSR program storage start is NULL\n"); 594 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 595 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 596 } 597 598 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 599 { 600 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 601 SKL_DISP_PW_2); 602 603 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 604 605 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 606 "DC5 already programmed to be enabled.\n"); 607 assert_rpm_wakelock_held(dev_priv); 608 609 assert_csr_loaded(dev_priv); 610 } 611 612 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 613 { 614 assert_can_enable_dc5(dev_priv); 615 616 DRM_DEBUG_KMS("Enabling DC5\n"); 617 618 /* Wa Display #1183: skl,kbl,cfl */ 619 if (IS_GEN9_BC(dev_priv)) 620 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 621 SKL_SELECT_ALTERNATE_DC_EXIT); 622 623 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 624 } 625 626 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 627 { 628 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 629 "Backlight is not disabled.\n"); 630 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 631 "DC6 already programmed to be enabled.\n"); 632 633 assert_csr_loaded(dev_priv); 634 } 635 636 void skl_enable_dc6(struct drm_i915_private *dev_priv) 637 { 638 assert_can_enable_dc6(dev_priv); 639 640 DRM_DEBUG_KMS("Enabling DC6\n"); 641 642 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 643 644 } 645 646 void skl_disable_dc6(struct drm_i915_private *dev_priv) 647 { 648 DRM_DEBUG_KMS("Disabling DC6\n"); 649 650 /* Wa Display #1183: skl,kbl,cfl */ 651 if (IS_GEN9_BC(dev_priv)) 652 I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | 653 SKL_SELECT_ALTERNATE_DC_EXIT); 654 655 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 656 } 657 658 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 659 struct i915_power_well *power_well) 660 { 661 enum i915_power_well_id id = power_well->id; 662 u32 mask = HSW_PWR_WELL_CTL_REQ(id); 663 u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); 664 665 /* Take over the request bit if set by BIOS. */ 666 if (bios_req & mask) { 667 u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); 668 669 if (!(drv_req & mask)) 670 I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); 671 I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); 672 } 673 } 674 675 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 676 struct i915_power_well *power_well) 677 { 678 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); 679 } 680 681 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 682 struct i915_power_well *power_well) 683 { 684 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); 685 } 686 687 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 688 struct i915_power_well *power_well) 689 { 690 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); 691 } 692 693 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 694 { 695 struct i915_power_well *power_well; 696 697 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 698 if (power_well->count > 0) 699 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 700 701 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); 702 if (power_well->count > 0) 703 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 704 705 if (IS_GEMINILAKE(dev_priv)) { 706 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); 707 if (power_well->count > 0) 708 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); 709 } 710 } 711 712 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 713 struct i915_power_well *power_well) 714 { 715 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 716 } 717 718 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 719 { 720 u32 tmp = I915_READ(DBUF_CTL); 721 722 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 723 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 724 "Unexpected DBuf power power state (0x%08x)\n", tmp); 725 } 726 727 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 728 struct i915_power_well *power_well) 729 { 730 struct intel_cdclk_state cdclk_state = {}; 731 732 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 733 734 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); 735 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 736 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); 737 738 gen9_assert_dbuf_enabled(dev_priv); 739 740 if (IS_GEN9_LP(dev_priv)) 741 bxt_verify_ddi_phy_power_wells(dev_priv); 742 } 743 744 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 745 struct i915_power_well *power_well) 746 { 747 if (!dev_priv->csr.dmc_payload) 748 return; 749 750 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 751 skl_enable_dc6(dev_priv); 752 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 753 gen9_enable_dc5(dev_priv); 754 } 755 756 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 757 struct i915_power_well *power_well) 758 { 759 } 760 761 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 762 struct i915_power_well *power_well) 763 { 764 } 765 766 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 767 struct i915_power_well *power_well) 768 { 769 return true; 770 } 771 772 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 773 struct i915_power_well *power_well) 774 { 775 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) 776 i830_enable_pipe(dev_priv, PIPE_A); 777 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) 778 i830_enable_pipe(dev_priv, PIPE_B); 779 } 780 781 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 782 struct i915_power_well *power_well) 783 { 784 i830_disable_pipe(dev_priv, PIPE_B); 785 i830_disable_pipe(dev_priv, PIPE_A); 786 } 787 788 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 789 struct i915_power_well *power_well) 790 { 791 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && 792 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 793 } 794 795 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 796 struct i915_power_well *power_well) 797 { 798 if (power_well->count > 0) 799 i830_pipes_power_well_enable(dev_priv, power_well); 800 else 801 i830_pipes_power_well_disable(dev_priv, power_well); 802 } 803 804 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 805 struct i915_power_well *power_well, bool enable) 806 { 807 enum i915_power_well_id power_well_id = power_well->id; 808 u32 mask; 809 u32 state; 810 u32 ctrl; 811 812 mask = PUNIT_PWRGT_MASK(power_well_id); 813 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 814 PUNIT_PWRGT_PWR_GATE(power_well_id); 815 816 mutex_lock(&dev_priv->pcu_lock); 817 818 #define COND \ 819 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 820 821 if (COND) 822 goto out; 823 824 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 825 ctrl &= ~mask; 826 ctrl |= state; 827 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 828 829 if (wait_for(COND, 100)) 830 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 831 state, 832 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 833 834 #undef COND 835 836 out: 837 mutex_unlock(&dev_priv->pcu_lock); 838 } 839 840 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 841 struct i915_power_well *power_well) 842 { 843 vlv_set_power_well(dev_priv, power_well, true); 844 } 845 846 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 847 struct i915_power_well *power_well) 848 { 849 vlv_set_power_well(dev_priv, power_well, false); 850 } 851 852 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 853 struct i915_power_well *power_well) 854 { 855 enum i915_power_well_id power_well_id = power_well->id; 856 bool enabled = false; 857 u32 mask; 858 u32 state; 859 u32 ctrl; 860 861 mask = PUNIT_PWRGT_MASK(power_well_id); 862 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 863 864 mutex_lock(&dev_priv->pcu_lock); 865 866 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 867 /* 868 * We only ever set the power-on and power-gate states, anything 869 * else is unexpected. 870 */ 871 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 872 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 873 if (state == ctrl) 874 enabled = true; 875 876 /* 877 * A transient state at this point would mean some unexpected party 878 * is poking at the power controls too. 879 */ 880 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 881 WARN_ON(ctrl != state); 882 883 mutex_unlock(&dev_priv->pcu_lock); 884 885 return enabled; 886 } 887 888 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 889 { 890 u32 val; 891 892 /* 893 * On driver load, a pipe may be active and driving a DSI display. 894 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 895 * (and never recovering) in this case. intel_dsi_post_disable() will 896 * clear it when we turn off the display. 897 */ 898 val = I915_READ(DSPCLK_GATE_D); 899 val &= DPOUNIT_CLOCK_GATE_DISABLE; 900 val |= VRHUNIT_CLOCK_GATE_DISABLE; 901 I915_WRITE(DSPCLK_GATE_D, val); 902 903 /* 904 * Disable trickle feed and enable pnd deadline calculation 905 */ 906 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 907 I915_WRITE(CBR1_VLV, 0); 908 909 WARN_ON(dev_priv->rawclk_freq == 0); 910 911 I915_WRITE(RAWCLK_FREQ_VLV, 912 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 913 } 914 915 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 916 { 917 struct intel_encoder *encoder; 918 enum pipe pipe; 919 920 /* 921 * Enable the CRI clock source so we can get at the 922 * display and the reference clock for VGA 923 * hotplug / manual detection. Supposedly DSI also 924 * needs the ref clock up and running. 925 * 926 * CHV DPLL B/C have some issues if VGA mode is enabled. 927 */ 928 for_each_pipe(dev_priv, pipe) { 929 u32 val = I915_READ(DPLL(pipe)); 930 931 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 932 if (pipe != PIPE_A) 933 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 934 935 I915_WRITE(DPLL(pipe), val); 936 } 937 938 vlv_init_display_clock_gating(dev_priv); 939 940 spin_lock_irq(&dev_priv->irq_lock); 941 valleyview_enable_display_irqs(dev_priv); 942 spin_unlock_irq(&dev_priv->irq_lock); 943 944 /* 945 * During driver initialization/resume we can avoid restoring the 946 * part of the HW/SW state that will be inited anyway explicitly. 947 */ 948 if (dev_priv->power_domains.initializing) 949 return; 950 951 intel_hpd_init(dev_priv); 952 953 /* Re-enable the ADPA, if we have one */ 954 for_each_intel_encoder(&dev_priv->drm, encoder) { 955 if (encoder->type == INTEL_OUTPUT_ANALOG) 956 intel_crt_reset(&encoder->base); 957 } 958 959 i915_redisable_vga_power_on(dev_priv); 960 961 intel_pps_unlock_regs_wa(dev_priv); 962 } 963 964 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 965 { 966 spin_lock_irq(&dev_priv->irq_lock); 967 valleyview_disable_display_irqs(dev_priv); 968 spin_unlock_irq(&dev_priv->irq_lock); 969 970 /* make sure we're done processing display irqs */ 971 synchronize_irq(dev_priv->drm.irq); 972 973 intel_power_sequencer_reset(dev_priv); 974 975 /* Prevent us from re-enabling polling on accident in late suspend */ 976 if (!dev_priv->drm.dev->power.is_suspended) 977 intel_hpd_poll_init(dev_priv); 978 } 979 980 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 981 struct i915_power_well *power_well) 982 { 983 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 984 985 vlv_set_power_well(dev_priv, power_well, true); 986 987 vlv_display_power_well_init(dev_priv); 988 } 989 990 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 991 struct i915_power_well *power_well) 992 { 993 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D); 994 995 vlv_display_power_well_deinit(dev_priv); 996 997 vlv_set_power_well(dev_priv, power_well, false); 998 } 999 1000 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1001 struct i915_power_well *power_well) 1002 { 1003 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1004 1005 /* since ref/cri clock was enabled */ 1006 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1007 1008 vlv_set_power_well(dev_priv, power_well, true); 1009 1010 /* 1011 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1012 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1013 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1014 * b. The other bits such as sfr settings / modesel may all 1015 * be set to 0. 1016 * 1017 * This should only be done on init and resume from S3 with 1018 * both PLLs disabled, or we risk losing DPIO and PLL 1019 * synchronization. 1020 */ 1021 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1022 } 1023 1024 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1025 struct i915_power_well *power_well) 1026 { 1027 enum pipe pipe; 1028 1029 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC); 1030 1031 for_each_pipe(dev_priv, pipe) 1032 assert_pll_disabled(dev_priv, pipe); 1033 1034 /* Assert common reset */ 1035 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1036 1037 vlv_set_power_well(dev_priv, power_well, false); 1038 } 1039 1040 #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) 1041 1042 static struct i915_power_well * 1043 lookup_power_well(struct drm_i915_private *dev_priv, 1044 enum i915_power_well_id power_well_id) 1045 { 1046 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1047 int i; 1048 1049 for (i = 0; i < power_domains->power_well_count; i++) { 1050 struct i915_power_well *power_well; 1051 1052 power_well = &power_domains->power_wells[i]; 1053 if (power_well->id == power_well_id) 1054 return power_well; 1055 } 1056 1057 return NULL; 1058 } 1059 1060 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1061 1062 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1063 { 1064 struct i915_power_well *cmn_bc = 1065 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1066 struct i915_power_well *cmn_d = 1067 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1068 u32 phy_control = dev_priv->chv_phy_control; 1069 u32 phy_status = 0; 1070 u32 phy_status_mask = 0xffffffff; 1071 1072 /* 1073 * The BIOS can leave the PHY is some weird state 1074 * where it doesn't fully power down some parts. 1075 * Disable the asserts until the PHY has been fully 1076 * reset (ie. the power well has been disabled at 1077 * least once). 1078 */ 1079 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1080 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1081 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1082 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1083 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1084 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1085 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1086 1087 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1088 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1089 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1090 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1091 1092 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1093 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1094 1095 /* this assumes override is only used to enable lanes */ 1096 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1097 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1098 1099 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1100 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1101 1102 /* CL1 is on whenever anything is on in either channel */ 1103 if (BITS_SET(phy_control, 1104 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1105 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1106 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1107 1108 /* 1109 * The DPLLB check accounts for the pipe B + port A usage 1110 * with CL2 powered up but all the lanes in the second channel 1111 * powered down. 1112 */ 1113 if (BITS_SET(phy_control, 1114 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1115 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1116 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1117 1118 if (BITS_SET(phy_control, 1119 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1120 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1121 if (BITS_SET(phy_control, 1122 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1123 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1124 1125 if (BITS_SET(phy_control, 1126 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1127 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1128 if (BITS_SET(phy_control, 1129 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1130 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1131 } 1132 1133 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1134 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1135 1136 /* this assumes override is only used to enable lanes */ 1137 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1138 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1139 1140 if (BITS_SET(phy_control, 1141 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1142 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1143 1144 if (BITS_SET(phy_control, 1145 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1146 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1147 if (BITS_SET(phy_control, 1148 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1149 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1150 } 1151 1152 phy_status &= phy_status_mask; 1153 1154 /* 1155 * The PHY may be busy with some initial calibration and whatnot, 1156 * so the power state can take a while to actually change. 1157 */ 1158 if (intel_wait_for_register(dev_priv, 1159 DISPLAY_PHY_STATUS, 1160 phy_status_mask, 1161 phy_status, 1162 10)) 1163 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1164 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1165 phy_status, dev_priv->chv_phy_control); 1166 } 1167 1168 #undef BITS_SET 1169 1170 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1171 struct i915_power_well *power_well) 1172 { 1173 enum dpio_phy phy; 1174 enum pipe pipe; 1175 uint32_t tmp; 1176 1177 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1178 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1179 1180 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1181 pipe = PIPE_A; 1182 phy = DPIO_PHY0; 1183 } else { 1184 pipe = PIPE_C; 1185 phy = DPIO_PHY1; 1186 } 1187 1188 /* since ref/cri clock was enabled */ 1189 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1190 vlv_set_power_well(dev_priv, power_well, true); 1191 1192 /* Poll for phypwrgood signal */ 1193 if (intel_wait_for_register(dev_priv, 1194 DISPLAY_PHY_STATUS, 1195 PHY_POWERGOOD(phy), 1196 PHY_POWERGOOD(phy), 1197 1)) 1198 DRM_ERROR("Display PHY %d is not power up\n", phy); 1199 1200 mutex_lock(&dev_priv->sb_lock); 1201 1202 /* Enable dynamic power down */ 1203 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1204 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1205 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1206 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1207 1208 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1209 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1210 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1211 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1212 } else { 1213 /* 1214 * Force the non-existing CL2 off. BXT does this 1215 * too, so maybe it saves some power even though 1216 * CL2 doesn't exist? 1217 */ 1218 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1219 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1220 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1221 } 1222 1223 mutex_unlock(&dev_priv->sb_lock); 1224 1225 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1226 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1227 1228 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1229 phy, dev_priv->chv_phy_control); 1230 1231 assert_chv_phy_status(dev_priv); 1232 } 1233 1234 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1235 struct i915_power_well *power_well) 1236 { 1237 enum dpio_phy phy; 1238 1239 WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC && 1240 power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D); 1241 1242 if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1243 phy = DPIO_PHY0; 1244 assert_pll_disabled(dev_priv, PIPE_A); 1245 assert_pll_disabled(dev_priv, PIPE_B); 1246 } else { 1247 phy = DPIO_PHY1; 1248 assert_pll_disabled(dev_priv, PIPE_C); 1249 } 1250 1251 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1252 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1253 1254 vlv_set_power_well(dev_priv, power_well, false); 1255 1256 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1257 phy, dev_priv->chv_phy_control); 1258 1259 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1260 dev_priv->chv_phy_assert[phy] = true; 1261 1262 assert_chv_phy_status(dev_priv); 1263 } 1264 1265 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1266 enum dpio_channel ch, bool override, unsigned int mask) 1267 { 1268 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1269 u32 reg, val, expected, actual; 1270 1271 /* 1272 * The BIOS can leave the PHY is some weird state 1273 * where it doesn't fully power down some parts. 1274 * Disable the asserts until the PHY has been fully 1275 * reset (ie. the power well has been disabled at 1276 * least once). 1277 */ 1278 if (!dev_priv->chv_phy_assert[phy]) 1279 return; 1280 1281 if (ch == DPIO_CH0) 1282 reg = _CHV_CMN_DW0_CH0; 1283 else 1284 reg = _CHV_CMN_DW6_CH1; 1285 1286 mutex_lock(&dev_priv->sb_lock); 1287 val = vlv_dpio_read(dev_priv, pipe, reg); 1288 mutex_unlock(&dev_priv->sb_lock); 1289 1290 /* 1291 * This assumes !override is only used when the port is disabled. 1292 * All lanes should power down even without the override when 1293 * the port is disabled. 1294 */ 1295 if (!override || mask == 0xf) { 1296 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1297 /* 1298 * If CH1 common lane is not active anymore 1299 * (eg. for pipe B DPLL) the entire channel will 1300 * shut down, which causes the common lane registers 1301 * to read as 0. That means we can't actually check 1302 * the lane power down status bits, but as the entire 1303 * register reads as 0 it's a good indication that the 1304 * channel is indeed entirely powered down. 1305 */ 1306 if (ch == DPIO_CH1 && val == 0) 1307 expected = 0; 1308 } else if (mask != 0x0) { 1309 expected = DPIO_ANYDL_POWERDOWN; 1310 } else { 1311 expected = 0; 1312 } 1313 1314 if (ch == DPIO_CH0) 1315 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1316 else 1317 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1318 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1319 1320 WARN(actual != expected, 1321 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1322 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1323 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1324 reg, val); 1325 } 1326 1327 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1328 enum dpio_channel ch, bool override) 1329 { 1330 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1331 bool was_override; 1332 1333 mutex_lock(&power_domains->lock); 1334 1335 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1336 1337 if (override == was_override) 1338 goto out; 1339 1340 if (override) 1341 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1342 else 1343 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1344 1345 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1346 1347 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1348 phy, ch, dev_priv->chv_phy_control); 1349 1350 assert_chv_phy_status(dev_priv); 1351 1352 out: 1353 mutex_unlock(&power_domains->lock); 1354 1355 return was_override; 1356 } 1357 1358 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1359 bool override, unsigned int mask) 1360 { 1361 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1362 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1363 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1364 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1365 1366 mutex_lock(&power_domains->lock); 1367 1368 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1369 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1370 1371 if (override) 1372 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1373 else 1374 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1375 1376 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1377 1378 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1379 phy, ch, mask, dev_priv->chv_phy_control); 1380 1381 assert_chv_phy_status(dev_priv); 1382 1383 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1384 1385 mutex_unlock(&power_domains->lock); 1386 } 1387 1388 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1389 struct i915_power_well *power_well) 1390 { 1391 enum pipe pipe = PIPE_A; 1392 bool enabled; 1393 u32 state, ctrl; 1394 1395 mutex_lock(&dev_priv->pcu_lock); 1396 1397 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1398 /* 1399 * We only ever set the power-on and power-gate states, anything 1400 * else is unexpected. 1401 */ 1402 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1403 enabled = state == DP_SSS_PWR_ON(pipe); 1404 1405 /* 1406 * A transient state at this point would mean some unexpected party 1407 * is poking at the power controls too. 1408 */ 1409 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1410 WARN_ON(ctrl << 16 != state); 1411 1412 mutex_unlock(&dev_priv->pcu_lock); 1413 1414 return enabled; 1415 } 1416 1417 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1418 struct i915_power_well *power_well, 1419 bool enable) 1420 { 1421 enum pipe pipe = PIPE_A; 1422 u32 state; 1423 u32 ctrl; 1424 1425 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1426 1427 mutex_lock(&dev_priv->pcu_lock); 1428 1429 #define COND \ 1430 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1431 1432 if (COND) 1433 goto out; 1434 1435 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1436 ctrl &= ~DP_SSC_MASK(pipe); 1437 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1438 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1439 1440 if (wait_for(COND, 100)) 1441 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1442 state, 1443 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1444 1445 #undef COND 1446 1447 out: 1448 mutex_unlock(&dev_priv->pcu_lock); 1449 } 1450 1451 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1452 struct i915_power_well *power_well) 1453 { 1454 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1455 1456 chv_set_pipe_power_well(dev_priv, power_well, true); 1457 1458 vlv_display_power_well_init(dev_priv); 1459 } 1460 1461 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1462 struct i915_power_well *power_well) 1463 { 1464 WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); 1465 1466 vlv_display_power_well_deinit(dev_priv); 1467 1468 chv_set_pipe_power_well(dev_priv, power_well, false); 1469 } 1470 1471 static void 1472 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1473 enum intel_display_power_domain domain) 1474 { 1475 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1476 struct i915_power_well *power_well; 1477 1478 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) 1479 intel_power_well_get(dev_priv, power_well); 1480 1481 power_domains->domain_use_count[domain]++; 1482 } 1483 1484 /** 1485 * intel_display_power_get - grab a power domain reference 1486 * @dev_priv: i915 device instance 1487 * @domain: power domain to reference 1488 * 1489 * This function grabs a power domain reference for @domain and ensures that the 1490 * power domain and all its parents are powered up. Therefore users should only 1491 * grab a reference to the innermost power domain they need. 1492 * 1493 * Any power domain reference obtained by this function must have a symmetric 1494 * call to intel_display_power_put() to release the reference again. 1495 */ 1496 void intel_display_power_get(struct drm_i915_private *dev_priv, 1497 enum intel_display_power_domain domain) 1498 { 1499 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1500 1501 intel_runtime_pm_get(dev_priv); 1502 1503 mutex_lock(&power_domains->lock); 1504 1505 __intel_display_power_get_domain(dev_priv, domain); 1506 1507 mutex_unlock(&power_domains->lock); 1508 } 1509 1510 /** 1511 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1512 * @dev_priv: i915 device instance 1513 * @domain: power domain to reference 1514 * 1515 * This function grabs a power domain reference for @domain and ensures that the 1516 * power domain and all its parents are powered up. Therefore users should only 1517 * grab a reference to the innermost power domain they need. 1518 * 1519 * Any power domain reference obtained by this function must have a symmetric 1520 * call to intel_display_power_put() to release the reference again. 1521 */ 1522 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1523 enum intel_display_power_domain domain) 1524 { 1525 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1526 bool is_enabled; 1527 1528 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1529 return false; 1530 1531 mutex_lock(&power_domains->lock); 1532 1533 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1534 __intel_display_power_get_domain(dev_priv, domain); 1535 is_enabled = true; 1536 } else { 1537 is_enabled = false; 1538 } 1539 1540 mutex_unlock(&power_domains->lock); 1541 1542 if (!is_enabled) 1543 intel_runtime_pm_put(dev_priv); 1544 1545 return is_enabled; 1546 } 1547 1548 /** 1549 * intel_display_power_put - release a power domain reference 1550 * @dev_priv: i915 device instance 1551 * @domain: power domain to reference 1552 * 1553 * This function drops the power domain reference obtained by 1554 * intel_display_power_get() and might power down the corresponding hardware 1555 * block right away if this is the last reference. 1556 */ 1557 void intel_display_power_put(struct drm_i915_private *dev_priv, 1558 enum intel_display_power_domain domain) 1559 { 1560 struct i915_power_domains *power_domains; 1561 struct i915_power_well *power_well; 1562 1563 power_domains = &dev_priv->power_domains; 1564 1565 mutex_lock(&power_domains->lock); 1566 1567 WARN(!power_domains->domain_use_count[domain], 1568 "Use count on domain %s is already zero\n", 1569 intel_display_power_domain_str(domain)); 1570 power_domains->domain_use_count[domain]--; 1571 1572 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) 1573 intel_power_well_put(dev_priv, power_well); 1574 1575 mutex_unlock(&power_domains->lock); 1576 1577 intel_runtime_pm_put(dev_priv); 1578 } 1579 1580 #define I830_PIPES_POWER_DOMAINS ( \ 1581 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1582 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1583 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1584 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1585 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1586 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1587 BIT_ULL(POWER_DOMAIN_INIT)) 1588 1589 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1590 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1591 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1592 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1593 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1594 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1595 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1596 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1597 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1598 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1599 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1600 BIT_ULL(POWER_DOMAIN_VGA) | \ 1601 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1602 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1603 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1604 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1605 BIT_ULL(POWER_DOMAIN_INIT)) 1606 1607 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1608 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1609 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1610 BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ 1611 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1612 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1613 BIT_ULL(POWER_DOMAIN_INIT)) 1614 1615 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1616 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1617 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1618 BIT_ULL(POWER_DOMAIN_INIT)) 1619 1620 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1621 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1622 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1623 BIT_ULL(POWER_DOMAIN_INIT)) 1624 1625 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1626 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1627 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1628 BIT_ULL(POWER_DOMAIN_INIT)) 1629 1630 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1631 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1632 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1633 BIT_ULL(POWER_DOMAIN_INIT)) 1634 1635 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1636 BIT_ULL(POWER_DOMAIN_PIPE_A) | \ 1637 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1638 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1639 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1640 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1641 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1642 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1643 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1644 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1645 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1646 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1647 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1648 BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ 1649 BIT_ULL(POWER_DOMAIN_VGA) | \ 1650 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1651 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1652 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1653 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1654 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1655 BIT_ULL(POWER_DOMAIN_INIT)) 1656 1657 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1658 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1659 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1660 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1661 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1662 BIT_ULL(POWER_DOMAIN_INIT)) 1663 1664 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1665 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1666 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1667 BIT_ULL(POWER_DOMAIN_INIT)) 1668 1669 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1670 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1671 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1672 BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1673 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1674 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1675 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1676 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1677 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1678 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1679 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1680 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1681 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1682 BIT_ULL(POWER_DOMAIN_VGA) | \ 1683 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1684 BIT_ULL(POWER_DOMAIN_INIT)) 1685 1686 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1687 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1688 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1689 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1690 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1691 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1692 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1693 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1694 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1695 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1696 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1697 BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1698 BIT_ULL(POWER_DOMAIN_VGA) | \ 1699 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1700 BIT_ULL(POWER_DOMAIN_INIT)) 1701 1702 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1703 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1704 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1705 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1706 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1707 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1708 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1709 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1710 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1711 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1712 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1713 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 1714 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1715 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1716 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1717 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1718 BIT_ULL(POWER_DOMAIN_VGA) | \ 1719 BIT_ULL(POWER_DOMAIN_INIT)) 1720 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ 1721 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1722 BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ 1723 BIT_ULL(POWER_DOMAIN_INIT)) 1724 #define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1725 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1726 BIT_ULL(POWER_DOMAIN_INIT)) 1727 #define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1728 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1729 BIT_ULL(POWER_DOMAIN_INIT)) 1730 #define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ 1731 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1732 BIT_ULL(POWER_DOMAIN_INIT)) 1733 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1734 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1735 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1736 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1737 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1738 BIT_ULL(POWER_DOMAIN_INIT)) 1739 1740 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1741 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1742 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1743 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1744 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1745 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1746 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1747 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1748 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1749 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1750 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1751 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1752 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1753 BIT_ULL(POWER_DOMAIN_VGA) | \ 1754 BIT_ULL(POWER_DOMAIN_INIT)) 1755 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1756 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1757 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1758 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1759 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1760 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1761 BIT_ULL(POWER_DOMAIN_INIT)) 1762 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 1763 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1764 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1765 BIT_ULL(POWER_DOMAIN_INIT)) 1766 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 1767 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1768 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1769 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1770 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1771 BIT_ULL(POWER_DOMAIN_INIT)) 1772 1773 #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1774 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1775 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1776 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1777 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1778 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1779 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1780 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1781 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1782 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1783 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1784 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1785 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1786 BIT_ULL(POWER_DOMAIN_VGA) | \ 1787 BIT_ULL(POWER_DOMAIN_INIT)) 1788 #define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ 1789 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) 1790 #define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ 1791 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) 1792 #define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ 1793 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) 1794 #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ 1795 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1796 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1797 BIT_ULL(POWER_DOMAIN_INIT)) 1798 #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ 1799 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1800 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1801 BIT_ULL(POWER_DOMAIN_INIT)) 1802 #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ 1803 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1804 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1805 BIT_ULL(POWER_DOMAIN_INIT)) 1806 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1807 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1808 BIT_ULL(POWER_DOMAIN_INIT)) 1809 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1810 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1811 BIT_ULL(POWER_DOMAIN_INIT)) 1812 #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1813 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1814 BIT_ULL(POWER_DOMAIN_INIT)) 1815 #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1816 GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1817 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1818 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1819 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1820 BIT_ULL(POWER_DOMAIN_GMBUS) | \ 1821 BIT_ULL(POWER_DOMAIN_INIT)) 1822 1823 #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 1824 BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ 1825 BIT_ULL(POWER_DOMAIN_PIPE_B) | \ 1826 BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ 1827 BIT_ULL(POWER_DOMAIN_PIPE_C) | \ 1828 BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ 1829 BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1830 BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1831 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1832 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1833 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1834 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \ 1835 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1836 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1837 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1838 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1839 BIT_ULL(POWER_DOMAIN_AUDIO) | \ 1840 BIT_ULL(POWER_DOMAIN_VGA) | \ 1841 BIT_ULL(POWER_DOMAIN_INIT)) 1842 #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ 1843 BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ 1844 BIT_ULL(POWER_DOMAIN_INIT)) 1845 #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ 1846 BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ 1847 BIT_ULL(POWER_DOMAIN_INIT)) 1848 #define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ 1849 BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ 1850 BIT_ULL(POWER_DOMAIN_INIT)) 1851 #define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ 1852 BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ 1853 BIT_ULL(POWER_DOMAIN_INIT)) 1854 #define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ 1855 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1856 BIT_ULL(POWER_DOMAIN_INIT)) 1857 #define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ 1858 BIT_ULL(POWER_DOMAIN_AUX_B) | \ 1859 BIT_ULL(POWER_DOMAIN_INIT)) 1860 #define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ 1861 BIT_ULL(POWER_DOMAIN_AUX_C) | \ 1862 BIT_ULL(POWER_DOMAIN_INIT)) 1863 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ 1864 BIT_ULL(POWER_DOMAIN_AUX_D) | \ 1865 BIT_ULL(POWER_DOMAIN_INIT)) 1866 #define CNL_DISPLAY_AUX_F_POWER_DOMAINS ( \ 1867 BIT_ULL(POWER_DOMAIN_AUX_F) | \ 1868 BIT_ULL(POWER_DOMAIN_INIT)) 1869 #define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \ 1870 BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \ 1871 BIT_ULL(POWER_DOMAIN_INIT)) 1872 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 1873 CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 1874 BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ 1875 BIT_ULL(POWER_DOMAIN_MODESET) | \ 1876 BIT_ULL(POWER_DOMAIN_AUX_A) | \ 1877 BIT_ULL(POWER_DOMAIN_INIT)) 1878 1879 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1880 .sync_hw = i9xx_power_well_sync_hw_noop, 1881 .enable = i9xx_always_on_power_well_noop, 1882 .disable = i9xx_always_on_power_well_noop, 1883 .is_enabled = i9xx_always_on_power_well_enabled, 1884 }; 1885 1886 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1887 .sync_hw = i9xx_power_well_sync_hw_noop, 1888 .enable = chv_pipe_power_well_enable, 1889 .disable = chv_pipe_power_well_disable, 1890 .is_enabled = chv_pipe_power_well_enabled, 1891 }; 1892 1893 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1894 .sync_hw = i9xx_power_well_sync_hw_noop, 1895 .enable = chv_dpio_cmn_power_well_enable, 1896 .disable = chv_dpio_cmn_power_well_disable, 1897 .is_enabled = vlv_power_well_enabled, 1898 }; 1899 1900 static struct i915_power_well i9xx_always_on_power_well[] = { 1901 { 1902 .name = "always-on", 1903 .always_on = 1, 1904 .domains = POWER_DOMAIN_MASK, 1905 .ops = &i9xx_always_on_power_well_ops, 1906 .id = I915_DISP_PW_ALWAYS_ON, 1907 }, 1908 }; 1909 1910 static const struct i915_power_well_ops i830_pipes_power_well_ops = { 1911 .sync_hw = i830_pipes_power_well_sync_hw, 1912 .enable = i830_pipes_power_well_enable, 1913 .disable = i830_pipes_power_well_disable, 1914 .is_enabled = i830_pipes_power_well_enabled, 1915 }; 1916 1917 static struct i915_power_well i830_power_wells[] = { 1918 { 1919 .name = "always-on", 1920 .always_on = 1, 1921 .domains = POWER_DOMAIN_MASK, 1922 .ops = &i9xx_always_on_power_well_ops, 1923 .id = I915_DISP_PW_ALWAYS_ON, 1924 }, 1925 { 1926 .name = "pipes", 1927 .domains = I830_PIPES_POWER_DOMAINS, 1928 .ops = &i830_pipes_power_well_ops, 1929 .id = I830_DISP_PW_PIPES, 1930 }, 1931 }; 1932 1933 static const struct i915_power_well_ops hsw_power_well_ops = { 1934 .sync_hw = hsw_power_well_sync_hw, 1935 .enable = hsw_power_well_enable, 1936 .disable = hsw_power_well_disable, 1937 .is_enabled = hsw_power_well_enabled, 1938 }; 1939 1940 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1941 .sync_hw = i9xx_power_well_sync_hw_noop, 1942 .enable = gen9_dc_off_power_well_enable, 1943 .disable = gen9_dc_off_power_well_disable, 1944 .is_enabled = gen9_dc_off_power_well_enabled, 1945 }; 1946 1947 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1948 .sync_hw = i9xx_power_well_sync_hw_noop, 1949 .enable = bxt_dpio_cmn_power_well_enable, 1950 .disable = bxt_dpio_cmn_power_well_disable, 1951 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1952 }; 1953 1954 static struct i915_power_well hsw_power_wells[] = { 1955 { 1956 .name = "always-on", 1957 .always_on = 1, 1958 .domains = POWER_DOMAIN_MASK, 1959 .ops = &i9xx_always_on_power_well_ops, 1960 .id = I915_DISP_PW_ALWAYS_ON, 1961 }, 1962 { 1963 .name = "display", 1964 .domains = HSW_DISPLAY_POWER_DOMAINS, 1965 .ops = &hsw_power_well_ops, 1966 .id = HSW_DISP_PW_GLOBAL, 1967 { 1968 .hsw.has_vga = true, 1969 }, 1970 }, 1971 }; 1972 1973 static struct i915_power_well bdw_power_wells[] = { 1974 { 1975 .name = "always-on", 1976 .always_on = 1, 1977 .domains = POWER_DOMAIN_MASK, 1978 .ops = &i9xx_always_on_power_well_ops, 1979 .id = I915_DISP_PW_ALWAYS_ON, 1980 }, 1981 { 1982 .name = "display", 1983 .domains = BDW_DISPLAY_POWER_DOMAINS, 1984 .ops = &hsw_power_well_ops, 1985 .id = HSW_DISP_PW_GLOBAL, 1986 { 1987 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 1988 .hsw.has_vga = true, 1989 }, 1990 }, 1991 }; 1992 1993 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1994 .sync_hw = i9xx_power_well_sync_hw_noop, 1995 .enable = vlv_display_power_well_enable, 1996 .disable = vlv_display_power_well_disable, 1997 .is_enabled = vlv_power_well_enabled, 1998 }; 1999 2000 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2001 .sync_hw = i9xx_power_well_sync_hw_noop, 2002 .enable = vlv_dpio_cmn_power_well_enable, 2003 .disable = vlv_dpio_cmn_power_well_disable, 2004 .is_enabled = vlv_power_well_enabled, 2005 }; 2006 2007 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2008 .sync_hw = i9xx_power_well_sync_hw_noop, 2009 .enable = vlv_power_well_enable, 2010 .disable = vlv_power_well_disable, 2011 .is_enabled = vlv_power_well_enabled, 2012 }; 2013 2014 static struct i915_power_well vlv_power_wells[] = { 2015 { 2016 .name = "always-on", 2017 .always_on = 1, 2018 .domains = POWER_DOMAIN_MASK, 2019 .ops = &i9xx_always_on_power_well_ops, 2020 .id = I915_DISP_PW_ALWAYS_ON, 2021 }, 2022 { 2023 .name = "display", 2024 .domains = VLV_DISPLAY_POWER_DOMAINS, 2025 .id = PUNIT_POWER_WELL_DISP2D, 2026 .ops = &vlv_display_power_well_ops, 2027 }, 2028 { 2029 .name = "dpio-tx-b-01", 2030 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2031 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2032 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2033 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2034 .ops = &vlv_dpio_power_well_ops, 2035 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 2036 }, 2037 { 2038 .name = "dpio-tx-b-23", 2039 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2040 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2041 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2042 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2043 .ops = &vlv_dpio_power_well_ops, 2044 .id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 2045 }, 2046 { 2047 .name = "dpio-tx-c-01", 2048 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2049 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2050 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2051 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2052 .ops = &vlv_dpio_power_well_ops, 2053 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 2054 }, 2055 { 2056 .name = "dpio-tx-c-23", 2057 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2058 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2059 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2060 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2061 .ops = &vlv_dpio_power_well_ops, 2062 .id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 2063 }, 2064 { 2065 .name = "dpio-common", 2066 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2067 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2068 .ops = &vlv_dpio_cmn_power_well_ops, 2069 }, 2070 }; 2071 2072 static struct i915_power_well chv_power_wells[] = { 2073 { 2074 .name = "always-on", 2075 .always_on = 1, 2076 .domains = POWER_DOMAIN_MASK, 2077 .ops = &i9xx_always_on_power_well_ops, 2078 .id = I915_DISP_PW_ALWAYS_ON, 2079 }, 2080 { 2081 .name = "display", 2082 /* 2083 * Pipe A power well is the new disp2d well. Pipe B and C 2084 * power wells don't actually exist. Pipe A power well is 2085 * required for any pipe to work. 2086 */ 2087 .domains = CHV_DISPLAY_POWER_DOMAINS, 2088 .id = CHV_DISP_PW_PIPE_A, 2089 .ops = &chv_pipe_power_well_ops, 2090 }, 2091 { 2092 .name = "dpio-common-bc", 2093 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2094 .id = PUNIT_POWER_WELL_DPIO_CMN_BC, 2095 .ops = &chv_dpio_cmn_power_well_ops, 2096 }, 2097 { 2098 .name = "dpio-common-d", 2099 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2100 .id = PUNIT_POWER_WELL_DPIO_CMN_D, 2101 .ops = &chv_dpio_cmn_power_well_ops, 2102 }, 2103 }; 2104 2105 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2106 enum i915_power_well_id power_well_id) 2107 { 2108 struct i915_power_well *power_well; 2109 bool ret; 2110 2111 power_well = lookup_power_well(dev_priv, power_well_id); 2112 ret = power_well->ops->is_enabled(dev_priv, power_well); 2113 2114 return ret; 2115 } 2116 2117 static struct i915_power_well skl_power_wells[] = { 2118 { 2119 .name = "always-on", 2120 .always_on = 1, 2121 .domains = POWER_DOMAIN_MASK, 2122 .ops = &i9xx_always_on_power_well_ops, 2123 .id = I915_DISP_PW_ALWAYS_ON, 2124 }, 2125 { 2126 .name = "power well 1", 2127 /* Handled by the DMC firmware */ 2128 .domains = 0, 2129 .ops = &hsw_power_well_ops, 2130 .id = SKL_DISP_PW_1, 2131 { 2132 .hsw.has_fuses = true, 2133 }, 2134 }, 2135 { 2136 .name = "MISC IO power well", 2137 /* Handled by the DMC firmware */ 2138 .domains = 0, 2139 .ops = &hsw_power_well_ops, 2140 .id = SKL_DISP_PW_MISC_IO, 2141 }, 2142 { 2143 .name = "DC off", 2144 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2145 .ops = &gen9_dc_off_power_well_ops, 2146 .id = SKL_DISP_PW_DC_OFF, 2147 }, 2148 { 2149 .name = "power well 2", 2150 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2151 .ops = &hsw_power_well_ops, 2152 .id = SKL_DISP_PW_2, 2153 { 2154 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2155 .hsw.has_vga = true, 2156 .hsw.has_fuses = true, 2157 }, 2158 }, 2159 { 2160 .name = "DDI A/E IO power well", 2161 .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, 2162 .ops = &hsw_power_well_ops, 2163 .id = SKL_DISP_PW_DDI_A_E, 2164 }, 2165 { 2166 .name = "DDI B IO power well", 2167 .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2168 .ops = &hsw_power_well_ops, 2169 .id = SKL_DISP_PW_DDI_B, 2170 }, 2171 { 2172 .name = "DDI C IO power well", 2173 .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2174 .ops = &hsw_power_well_ops, 2175 .id = SKL_DISP_PW_DDI_C, 2176 }, 2177 { 2178 .name = "DDI D IO power well", 2179 .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, 2180 .ops = &hsw_power_well_ops, 2181 .id = SKL_DISP_PW_DDI_D, 2182 }, 2183 }; 2184 2185 static struct i915_power_well bxt_power_wells[] = { 2186 { 2187 .name = "always-on", 2188 .always_on = 1, 2189 .domains = POWER_DOMAIN_MASK, 2190 .ops = &i9xx_always_on_power_well_ops, 2191 .id = I915_DISP_PW_ALWAYS_ON, 2192 }, 2193 { 2194 .name = "power well 1", 2195 .domains = 0, 2196 .ops = &hsw_power_well_ops, 2197 .id = SKL_DISP_PW_1, 2198 { 2199 .hsw.has_fuses = true, 2200 }, 2201 }, 2202 { 2203 .name = "DC off", 2204 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2205 .ops = &gen9_dc_off_power_well_ops, 2206 .id = SKL_DISP_PW_DC_OFF, 2207 }, 2208 { 2209 .name = "power well 2", 2210 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2211 .ops = &hsw_power_well_ops, 2212 .id = SKL_DISP_PW_2, 2213 { 2214 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2215 .hsw.has_vga = true, 2216 .hsw.has_fuses = true, 2217 }, 2218 }, 2219 { 2220 .name = "dpio-common-a", 2221 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2222 .ops = &bxt_dpio_cmn_power_well_ops, 2223 .id = BXT_DPIO_CMN_A, 2224 { 2225 .bxt.phy = DPIO_PHY1, 2226 }, 2227 }, 2228 { 2229 .name = "dpio-common-bc", 2230 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2231 .ops = &bxt_dpio_cmn_power_well_ops, 2232 .id = BXT_DPIO_CMN_BC, 2233 { 2234 .bxt.phy = DPIO_PHY0, 2235 }, 2236 }, 2237 }; 2238 2239 static struct i915_power_well glk_power_wells[] = { 2240 { 2241 .name = "always-on", 2242 .always_on = 1, 2243 .domains = POWER_DOMAIN_MASK, 2244 .ops = &i9xx_always_on_power_well_ops, 2245 .id = I915_DISP_PW_ALWAYS_ON, 2246 }, 2247 { 2248 .name = "power well 1", 2249 /* Handled by the DMC firmware */ 2250 .domains = 0, 2251 .ops = &hsw_power_well_ops, 2252 .id = SKL_DISP_PW_1, 2253 { 2254 .hsw.has_fuses = true, 2255 }, 2256 }, 2257 { 2258 .name = "DC off", 2259 .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS, 2260 .ops = &gen9_dc_off_power_well_ops, 2261 .id = SKL_DISP_PW_DC_OFF, 2262 }, 2263 { 2264 .name = "power well 2", 2265 .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2266 .ops = &hsw_power_well_ops, 2267 .id = SKL_DISP_PW_2, 2268 { 2269 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2270 .hsw.has_vga = true, 2271 .hsw.has_fuses = true, 2272 }, 2273 }, 2274 { 2275 .name = "dpio-common-a", 2276 .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, 2277 .ops = &bxt_dpio_cmn_power_well_ops, 2278 .id = BXT_DPIO_CMN_A, 2279 { 2280 .bxt.phy = DPIO_PHY1, 2281 }, 2282 }, 2283 { 2284 .name = "dpio-common-b", 2285 .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, 2286 .ops = &bxt_dpio_cmn_power_well_ops, 2287 .id = BXT_DPIO_CMN_BC, 2288 { 2289 .bxt.phy = DPIO_PHY0, 2290 }, 2291 }, 2292 { 2293 .name = "dpio-common-c", 2294 .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, 2295 .ops = &bxt_dpio_cmn_power_well_ops, 2296 .id = GLK_DPIO_CMN_C, 2297 { 2298 .bxt.phy = DPIO_PHY2, 2299 }, 2300 }, 2301 { 2302 .name = "AUX A", 2303 .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, 2304 .ops = &hsw_power_well_ops, 2305 .id = GLK_DISP_PW_AUX_A, 2306 }, 2307 { 2308 .name = "AUX B", 2309 .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, 2310 .ops = &hsw_power_well_ops, 2311 .id = GLK_DISP_PW_AUX_B, 2312 }, 2313 { 2314 .name = "AUX C", 2315 .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, 2316 .ops = &hsw_power_well_ops, 2317 .id = GLK_DISP_PW_AUX_C, 2318 }, 2319 { 2320 .name = "DDI A IO power well", 2321 .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, 2322 .ops = &hsw_power_well_ops, 2323 .id = GLK_DISP_PW_DDI_A, 2324 }, 2325 { 2326 .name = "DDI B IO power well", 2327 .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, 2328 .ops = &hsw_power_well_ops, 2329 .id = SKL_DISP_PW_DDI_B, 2330 }, 2331 { 2332 .name = "DDI C IO power well", 2333 .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, 2334 .ops = &hsw_power_well_ops, 2335 .id = SKL_DISP_PW_DDI_C, 2336 }, 2337 }; 2338 2339 static struct i915_power_well cnl_power_wells[] = { 2340 { 2341 .name = "always-on", 2342 .always_on = 1, 2343 .domains = POWER_DOMAIN_MASK, 2344 .ops = &i9xx_always_on_power_well_ops, 2345 .id = I915_DISP_PW_ALWAYS_ON, 2346 }, 2347 { 2348 .name = "power well 1", 2349 /* Handled by the DMC firmware */ 2350 .domains = 0, 2351 .ops = &hsw_power_well_ops, 2352 .id = SKL_DISP_PW_1, 2353 { 2354 .hsw.has_fuses = true, 2355 }, 2356 }, 2357 { 2358 .name = "AUX A", 2359 .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, 2360 .ops = &hsw_power_well_ops, 2361 .id = CNL_DISP_PW_AUX_A, 2362 }, 2363 { 2364 .name = "AUX B", 2365 .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, 2366 .ops = &hsw_power_well_ops, 2367 .id = CNL_DISP_PW_AUX_B, 2368 }, 2369 { 2370 .name = "AUX C", 2371 .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, 2372 .ops = &hsw_power_well_ops, 2373 .id = CNL_DISP_PW_AUX_C, 2374 }, 2375 { 2376 .name = "AUX D", 2377 .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, 2378 .ops = &hsw_power_well_ops, 2379 .id = CNL_DISP_PW_AUX_D, 2380 }, 2381 { 2382 .name = "DC off", 2383 .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS, 2384 .ops = &gen9_dc_off_power_well_ops, 2385 .id = SKL_DISP_PW_DC_OFF, 2386 }, 2387 { 2388 .name = "power well 2", 2389 .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2390 .ops = &hsw_power_well_ops, 2391 .id = SKL_DISP_PW_2, 2392 { 2393 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 2394 .hsw.has_vga = true, 2395 .hsw.has_fuses = true, 2396 }, 2397 }, 2398 { 2399 .name = "DDI A IO power well", 2400 .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, 2401 .ops = &hsw_power_well_ops, 2402 .id = CNL_DISP_PW_DDI_A, 2403 }, 2404 { 2405 .name = "DDI B IO power well", 2406 .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, 2407 .ops = &hsw_power_well_ops, 2408 .id = SKL_DISP_PW_DDI_B, 2409 }, 2410 { 2411 .name = "DDI C IO power well", 2412 .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, 2413 .ops = &hsw_power_well_ops, 2414 .id = SKL_DISP_PW_DDI_C, 2415 }, 2416 { 2417 .name = "DDI D IO power well", 2418 .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, 2419 .ops = &hsw_power_well_ops, 2420 .id = SKL_DISP_PW_DDI_D, 2421 }, 2422 { 2423 .name = "DDI F IO power well", 2424 .domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS, 2425 .ops = &hsw_power_well_ops, 2426 .id = CNL_DISP_PW_DDI_F, 2427 }, 2428 { 2429 .name = "AUX F", 2430 .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS, 2431 .ops = &hsw_power_well_ops, 2432 .id = CNL_DISP_PW_AUX_F, 2433 }, 2434 }; 2435 2436 static int 2437 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2438 int disable_power_well) 2439 { 2440 if (disable_power_well >= 0) 2441 return !!disable_power_well; 2442 2443 return 1; 2444 } 2445 2446 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2447 int enable_dc) 2448 { 2449 uint32_t mask; 2450 int requested_dc; 2451 int max_dc; 2452 2453 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { 2454 max_dc = 2; 2455 mask = 0; 2456 } else if (IS_GEN9_LP(dev_priv)) { 2457 max_dc = 1; 2458 /* 2459 * DC9 has a separate HW flow from the rest of the DC states, 2460 * not depending on the DMC firmware. It's needed by system 2461 * suspend/resume, so allow it unconditionally. 2462 */ 2463 mask = DC_STATE_EN_DC9; 2464 } else { 2465 max_dc = 0; 2466 mask = 0; 2467 } 2468 2469 if (!i915_modparams.disable_power_well) 2470 max_dc = 0; 2471 2472 if (enable_dc >= 0 && enable_dc <= max_dc) { 2473 requested_dc = enable_dc; 2474 } else if (enable_dc == -1) { 2475 requested_dc = max_dc; 2476 } else if (enable_dc > max_dc && enable_dc <= 2) { 2477 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2478 enable_dc, max_dc); 2479 requested_dc = max_dc; 2480 } else { 2481 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2482 requested_dc = max_dc; 2483 } 2484 2485 if (requested_dc > 1) 2486 mask |= DC_STATE_EN_UPTO_DC6; 2487 if (requested_dc > 0) 2488 mask |= DC_STATE_EN_UPTO_DC5; 2489 2490 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2491 2492 return mask; 2493 } 2494 2495 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) 2496 { 2497 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2498 u64 power_well_ids; 2499 int i; 2500 2501 power_well_ids = 0; 2502 for (i = 0; i < power_domains->power_well_count; i++) { 2503 enum i915_power_well_id id = power_domains->power_wells[i].id; 2504 2505 WARN_ON(id >= sizeof(power_well_ids) * 8); 2506 WARN_ON(power_well_ids & BIT_ULL(id)); 2507 power_well_ids |= BIT_ULL(id); 2508 } 2509 } 2510 2511 #define set_power_wells(power_domains, __power_wells) ({ \ 2512 (power_domains)->power_wells = (__power_wells); \ 2513 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2514 }) 2515 2516 /** 2517 * intel_power_domains_init - initializes the power domain structures 2518 * @dev_priv: i915 device instance 2519 * 2520 * Initializes the power domain structures for @dev_priv depending upon the 2521 * supported platform. 2522 */ 2523 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2524 { 2525 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2526 2527 i915_modparams.disable_power_well = 2528 sanitize_disable_power_well_option(dev_priv, 2529 i915_modparams.disable_power_well); 2530 dev_priv->csr.allowed_dc_mask = 2531 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); 2532 2533 BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); 2534 2535 mutex_init(&power_domains->lock); 2536 2537 /* 2538 * The enabling order will be from lower to higher indexed wells, 2539 * the disabling order is reversed. 2540 */ 2541 if (IS_HASWELL(dev_priv)) { 2542 set_power_wells(power_domains, hsw_power_wells); 2543 } else if (IS_BROADWELL(dev_priv)) { 2544 set_power_wells(power_domains, bdw_power_wells); 2545 } else if (IS_GEN9_BC(dev_priv)) { 2546 set_power_wells(power_domains, skl_power_wells); 2547 } else if (IS_CANNONLAKE(dev_priv)) { 2548 set_power_wells(power_domains, cnl_power_wells); 2549 2550 /* 2551 * DDI and Aux IO are getting enabled for all ports 2552 * regardless the presence or use. So, in order to avoid 2553 * timeouts, lets remove them from the list 2554 * for the SKUs without port F. 2555 */ 2556 if (!IS_CNL_WITH_PORT_F(dev_priv)) 2557 power_domains->power_well_count -= 2; 2558 2559 } else if (IS_BROXTON(dev_priv)) { 2560 set_power_wells(power_domains, bxt_power_wells); 2561 } else if (IS_GEMINILAKE(dev_priv)) { 2562 set_power_wells(power_domains, glk_power_wells); 2563 } else if (IS_CHERRYVIEW(dev_priv)) { 2564 set_power_wells(power_domains, chv_power_wells); 2565 } else if (IS_VALLEYVIEW(dev_priv)) { 2566 set_power_wells(power_domains, vlv_power_wells); 2567 } else if (IS_I830(dev_priv)) { 2568 set_power_wells(power_domains, i830_power_wells); 2569 } else { 2570 set_power_wells(power_domains, i9xx_always_on_power_well); 2571 } 2572 2573 assert_power_well_ids_unique(dev_priv); 2574 2575 return 0; 2576 } 2577 2578 /** 2579 * intel_power_domains_fini - finalizes the power domain structures 2580 * @dev_priv: i915 device instance 2581 * 2582 * Finalizes the power domain structures for @dev_priv depending upon the 2583 * supported platform. This function also disables runtime pm and ensures that 2584 * the device stays powered up so that the driver can be reloaded. 2585 */ 2586 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2587 { 2588 struct device *kdev = &dev_priv->drm.pdev->dev; 2589 2590 /* 2591 * The i915.ko module is still not prepared to be loaded when 2592 * the power well is not enabled, so just enable it in case 2593 * we're going to unload/reload. 2594 * The following also reacquires the RPM reference the core passed 2595 * to the driver during loading, which is dropped in 2596 * intel_runtime_pm_enable(). We have to hand back the control of the 2597 * device to the core with this reference held. 2598 */ 2599 intel_display_set_init_power(dev_priv, true); 2600 2601 /* Remove the refcount we took to keep power well support disabled. */ 2602 if (!i915_modparams.disable_power_well) 2603 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2604 2605 /* 2606 * Remove the refcount we took in intel_runtime_pm_enable() in case 2607 * the platform doesn't support runtime PM. 2608 */ 2609 if (!HAS_RUNTIME_PM(dev_priv)) 2610 pm_runtime_put(kdev); 2611 } 2612 2613 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2614 { 2615 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2616 struct i915_power_well *power_well; 2617 2618 mutex_lock(&power_domains->lock); 2619 for_each_power_well(dev_priv, power_well) { 2620 power_well->ops->sync_hw(dev_priv, power_well); 2621 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2622 power_well); 2623 } 2624 mutex_unlock(&power_domains->lock); 2625 } 2626 2627 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 2628 { 2629 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 2630 POSTING_READ(DBUF_CTL); 2631 2632 udelay(10); 2633 2634 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 2635 DRM_ERROR("DBuf power enable timeout\n"); 2636 } 2637 2638 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 2639 { 2640 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 2641 POSTING_READ(DBUF_CTL); 2642 2643 udelay(10); 2644 2645 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 2646 DRM_ERROR("DBuf power disable timeout!\n"); 2647 } 2648 2649 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2650 bool resume) 2651 { 2652 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2653 struct i915_power_well *well; 2654 uint32_t val; 2655 2656 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2657 2658 /* enable PCH reset handshake */ 2659 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2660 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2661 2662 /* enable PG1 and Misc I/O */ 2663 mutex_lock(&power_domains->lock); 2664 2665 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2666 intel_power_well_enable(dev_priv, well); 2667 2668 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2669 intel_power_well_enable(dev_priv, well); 2670 2671 mutex_unlock(&power_domains->lock); 2672 2673 skl_init_cdclk(dev_priv); 2674 2675 gen9_dbuf_enable(dev_priv); 2676 2677 if (resume && dev_priv->csr.dmc_payload) 2678 intel_csr_load_program(dev_priv); 2679 } 2680 2681 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2682 { 2683 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2684 struct i915_power_well *well; 2685 2686 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2687 2688 gen9_dbuf_disable(dev_priv); 2689 2690 skl_uninit_cdclk(dev_priv); 2691 2692 /* The spec doesn't call for removing the reset handshake flag */ 2693 /* disable PG1 and Misc I/O */ 2694 2695 mutex_lock(&power_domains->lock); 2696 2697 /* 2698 * BSpec says to keep the MISC IO power well enabled here, only 2699 * remove our request for power well 1. 2700 * Note that even though the driver's request is removed power well 1 2701 * may stay enabled after this due to DMC's own request on it. 2702 */ 2703 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2704 intel_power_well_disable(dev_priv, well); 2705 2706 mutex_unlock(&power_domains->lock); 2707 2708 usleep_range(10, 30); /* 10 us delay per Bspec */ 2709 } 2710 2711 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2712 bool resume) 2713 { 2714 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2715 struct i915_power_well *well; 2716 uint32_t val; 2717 2718 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2719 2720 /* 2721 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2722 * or else the reset will hang because there is no PCH to respond. 2723 * Move the handshake programming to initialization sequence. 2724 * Previously was left up to BIOS. 2725 */ 2726 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2727 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2728 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2729 2730 /* Enable PG1 */ 2731 mutex_lock(&power_domains->lock); 2732 2733 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2734 intel_power_well_enable(dev_priv, well); 2735 2736 mutex_unlock(&power_domains->lock); 2737 2738 bxt_init_cdclk(dev_priv); 2739 2740 gen9_dbuf_enable(dev_priv); 2741 2742 if (resume && dev_priv->csr.dmc_payload) 2743 intel_csr_load_program(dev_priv); 2744 } 2745 2746 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2747 { 2748 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2749 struct i915_power_well *well; 2750 2751 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2752 2753 gen9_dbuf_disable(dev_priv); 2754 2755 bxt_uninit_cdclk(dev_priv); 2756 2757 /* The spec doesn't call for removing the reset handshake flag */ 2758 2759 /* 2760 * Disable PW1 (PG1). 2761 * Note that even though the driver's request is removed power well 1 2762 * may stay enabled after this due to DMC's own request on it. 2763 */ 2764 mutex_lock(&power_domains->lock); 2765 2766 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2767 intel_power_well_disable(dev_priv, well); 2768 2769 mutex_unlock(&power_domains->lock); 2770 2771 usleep_range(10, 30); /* 10 us delay per Bspec */ 2772 } 2773 2774 enum { 2775 PROCMON_0_85V_DOT_0, 2776 PROCMON_0_95V_DOT_0, 2777 PROCMON_0_95V_DOT_1, 2778 PROCMON_1_05V_DOT_0, 2779 PROCMON_1_05V_DOT_1, 2780 }; 2781 2782 static const struct cnl_procmon { 2783 u32 dw1, dw9, dw10; 2784 } cnl_procmon_values[] = { 2785 [PROCMON_0_85V_DOT_0] = 2786 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 2787 [PROCMON_0_95V_DOT_0] = 2788 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 2789 [PROCMON_0_95V_DOT_1] = 2790 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 2791 [PROCMON_1_05V_DOT_0] = 2792 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 2793 [PROCMON_1_05V_DOT_1] = 2794 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 2795 }; 2796 2797 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv) 2798 { 2799 const struct cnl_procmon *procmon; 2800 u32 val; 2801 2802 val = I915_READ(CNL_PORT_COMP_DW3); 2803 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 2804 default: 2805 MISSING_CASE(val); 2806 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 2807 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 2808 break; 2809 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 2810 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 2811 break; 2812 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 2813 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 2814 break; 2815 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 2816 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 2817 break; 2818 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 2819 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 2820 break; 2821 } 2822 2823 val = I915_READ(CNL_PORT_COMP_DW1); 2824 val &= ~((0xff << 16) | 0xff); 2825 val |= procmon->dw1; 2826 I915_WRITE(CNL_PORT_COMP_DW1, val); 2827 2828 I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9); 2829 I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10); 2830 } 2831 2832 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) 2833 { 2834 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2835 struct i915_power_well *well; 2836 u32 val; 2837 2838 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2839 2840 /* 1. Enable PCH Reset Handshake */ 2841 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2842 val |= RESET_PCH_HANDSHAKE_ENABLE; 2843 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2844 2845 /* 2. Enable Comp */ 2846 val = I915_READ(CHICKEN_MISC_2); 2847 val &= ~CNL_COMP_PWR_DOWN; 2848 I915_WRITE(CHICKEN_MISC_2, val); 2849 2850 cnl_set_procmon_ref_values(dev_priv); 2851 2852 val = I915_READ(CNL_PORT_COMP_DW0); 2853 val |= COMP_INIT; 2854 I915_WRITE(CNL_PORT_COMP_DW0, val); 2855 2856 /* 3. */ 2857 val = I915_READ(CNL_PORT_CL1CM_DW5); 2858 val |= CL_POWER_DOWN_ENABLE; 2859 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2860 2861 /* 2862 * 4. Enable Power Well 1 (PG1). 2863 * The AUX IO power wells will be enabled on demand. 2864 */ 2865 mutex_lock(&power_domains->lock); 2866 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2867 intel_power_well_enable(dev_priv, well); 2868 mutex_unlock(&power_domains->lock); 2869 2870 /* 5. Enable CD clock */ 2871 cnl_init_cdclk(dev_priv); 2872 2873 /* 6. Enable DBUF */ 2874 gen9_dbuf_enable(dev_priv); 2875 2876 if (resume && dev_priv->csr.dmc_payload) 2877 intel_csr_load_program(dev_priv); 2878 } 2879 2880 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) 2881 { 2882 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2883 struct i915_power_well *well; 2884 u32 val; 2885 2886 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2887 2888 /* 1. Disable all display engine functions -> aready done */ 2889 2890 /* 2. Disable DBUF */ 2891 gen9_dbuf_disable(dev_priv); 2892 2893 /* 3. Disable CD clock */ 2894 cnl_uninit_cdclk(dev_priv); 2895 2896 /* 2897 * 4. Disable Power Well 1 (PG1). 2898 * The AUX IO power wells are toggled on demand, so they are already 2899 * disabled at this point. 2900 */ 2901 mutex_lock(&power_domains->lock); 2902 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2903 intel_power_well_disable(dev_priv, well); 2904 mutex_unlock(&power_domains->lock); 2905 2906 usleep_range(10, 30); /* 10 us delay per Bspec */ 2907 2908 /* 5. Disable Comp */ 2909 val = I915_READ(CHICKEN_MISC_2); 2910 val |= CNL_COMP_PWR_DOWN; 2911 I915_WRITE(CHICKEN_MISC_2, val); 2912 } 2913 2914 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2915 { 2916 struct i915_power_well *cmn_bc = 2917 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2918 struct i915_power_well *cmn_d = 2919 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2920 2921 /* 2922 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2923 * workaround never ever read DISPLAY_PHY_CONTROL, and 2924 * instead maintain a shadow copy ourselves. Use the actual 2925 * power well state and lane status to reconstruct the 2926 * expected initial value. 2927 */ 2928 dev_priv->chv_phy_control = 2929 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2930 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2931 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2932 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2933 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2934 2935 /* 2936 * If all lanes are disabled we leave the override disabled 2937 * with all power down bits cleared to match the state we 2938 * would use after disabling the port. Otherwise enable the 2939 * override and set the lane powerdown bits accding to the 2940 * current lane status. 2941 */ 2942 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2943 uint32_t status = I915_READ(DPLL(PIPE_A)); 2944 unsigned int mask; 2945 2946 mask = status & DPLL_PORTB_READY_MASK; 2947 if (mask == 0xf) 2948 mask = 0x0; 2949 else 2950 dev_priv->chv_phy_control |= 2951 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2952 2953 dev_priv->chv_phy_control |= 2954 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2955 2956 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2957 if (mask == 0xf) 2958 mask = 0x0; 2959 else 2960 dev_priv->chv_phy_control |= 2961 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2962 2963 dev_priv->chv_phy_control |= 2964 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2965 2966 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2967 2968 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2969 } else { 2970 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2971 } 2972 2973 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2974 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2975 unsigned int mask; 2976 2977 mask = status & DPLL_PORTD_READY_MASK; 2978 2979 if (mask == 0xf) 2980 mask = 0x0; 2981 else 2982 dev_priv->chv_phy_control |= 2983 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2984 2985 dev_priv->chv_phy_control |= 2986 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2987 2988 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2989 2990 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2991 } else { 2992 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2993 } 2994 2995 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2996 2997 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2998 dev_priv->chv_phy_control); 2999 } 3000 3001 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 3002 { 3003 struct i915_power_well *cmn = 3004 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 3005 struct i915_power_well *disp2d = 3006 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 3007 3008 /* If the display might be already active skip this */ 3009 if (cmn->ops->is_enabled(dev_priv, cmn) && 3010 disp2d->ops->is_enabled(dev_priv, disp2d) && 3011 I915_READ(DPIO_CTL) & DPIO_CMNRST) 3012 return; 3013 3014 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 3015 3016 /* cmnlane needs DPLL registers */ 3017 disp2d->ops->enable(dev_priv, disp2d); 3018 3019 /* 3020 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 3021 * Need to assert and de-assert PHY SB reset by gating the 3022 * common lane power, then un-gating it. 3023 * Simply ungating isn't enough to reset the PHY enough to get 3024 * ports and lanes running. 3025 */ 3026 cmn->ops->disable(dev_priv, cmn); 3027 } 3028 3029 /** 3030 * intel_power_domains_init_hw - initialize hardware power domain state 3031 * @dev_priv: i915 device instance 3032 * @resume: Called from resume code paths or not 3033 * 3034 * This function initializes the hardware power domain state and enables all 3035 * power wells belonging to the INIT power domain. Power wells in other 3036 * domains (and not in the INIT domain) are referenced or disabled during the 3037 * modeset state HW readout. After that the reference count of each power well 3038 * must match its HW enabled state, see intel_power_domains_verify_state(). 3039 */ 3040 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 3041 { 3042 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3043 3044 power_domains->initializing = true; 3045 3046 if (IS_CANNONLAKE(dev_priv)) { 3047 cnl_display_core_init(dev_priv, resume); 3048 } else if (IS_GEN9_BC(dev_priv)) { 3049 skl_display_core_init(dev_priv, resume); 3050 } else if (IS_GEN9_LP(dev_priv)) { 3051 bxt_display_core_init(dev_priv, resume); 3052 } else if (IS_CHERRYVIEW(dev_priv)) { 3053 mutex_lock(&power_domains->lock); 3054 chv_phy_control_init(dev_priv); 3055 mutex_unlock(&power_domains->lock); 3056 } else if (IS_VALLEYVIEW(dev_priv)) { 3057 mutex_lock(&power_domains->lock); 3058 vlv_cmnlane_wa(dev_priv); 3059 mutex_unlock(&power_domains->lock); 3060 } 3061 3062 /* For now, we need the power well to be always enabled. */ 3063 intel_display_set_init_power(dev_priv, true); 3064 /* Disable power support if the user asked so. */ 3065 if (!i915_modparams.disable_power_well) 3066 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 3067 intel_power_domains_sync_hw(dev_priv); 3068 power_domains->initializing = false; 3069 } 3070 3071 /** 3072 * intel_power_domains_suspend - suspend power domain state 3073 * @dev_priv: i915 device instance 3074 * 3075 * This function prepares the hardware power domain state before entering 3076 * system suspend. It must be paired with intel_power_domains_init_hw(). 3077 */ 3078 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 3079 { 3080 /* 3081 * Even if power well support was disabled we still want to disable 3082 * power wells while we are system suspended. 3083 */ 3084 if (!i915_modparams.disable_power_well) 3085 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 3086 3087 if (IS_CANNONLAKE(dev_priv)) 3088 cnl_display_core_uninit(dev_priv); 3089 else if (IS_GEN9_BC(dev_priv)) 3090 skl_display_core_uninit(dev_priv); 3091 else if (IS_GEN9_LP(dev_priv)) 3092 bxt_display_core_uninit(dev_priv); 3093 } 3094 3095 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) 3096 { 3097 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3098 struct i915_power_well *power_well; 3099 3100 for_each_power_well(dev_priv, power_well) { 3101 enum intel_display_power_domain domain; 3102 3103 DRM_DEBUG_DRIVER("%-25s %d\n", 3104 power_well->name, power_well->count); 3105 3106 for_each_power_domain(domain, power_well->domains) 3107 DRM_DEBUG_DRIVER(" %-23s %d\n", 3108 intel_display_power_domain_str(domain), 3109 power_domains->domain_use_count[domain]); 3110 } 3111 } 3112 3113 /** 3114 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 3115 * @dev_priv: i915 device instance 3116 * 3117 * Verify if the reference count of each power well matches its HW enabled 3118 * state and the total refcount of the domains it belongs to. This must be 3119 * called after modeset HW state sanitization, which is responsible for 3120 * acquiring reference counts for any power wells in use and disabling the 3121 * ones left on by BIOS but not required by any active output. 3122 */ 3123 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) 3124 { 3125 struct i915_power_domains *power_domains = &dev_priv->power_domains; 3126 struct i915_power_well *power_well; 3127 bool dump_domain_info; 3128 3129 mutex_lock(&power_domains->lock); 3130 3131 dump_domain_info = false; 3132 for_each_power_well(dev_priv, power_well) { 3133 enum intel_display_power_domain domain; 3134 int domains_count; 3135 bool enabled; 3136 3137 /* 3138 * Power wells not belonging to any domain (like the MISC_IO 3139 * and PW1 power wells) are under FW control, so ignore them, 3140 * since their state can change asynchronously. 3141 */ 3142 if (!power_well->domains) 3143 continue; 3144 3145 enabled = power_well->ops->is_enabled(dev_priv, power_well); 3146 if ((power_well->count || power_well->always_on) != enabled) 3147 DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", 3148 power_well->name, power_well->count, enabled); 3149 3150 domains_count = 0; 3151 for_each_power_domain(domain, power_well->domains) 3152 domains_count += power_domains->domain_use_count[domain]; 3153 3154 if (power_well->count != domains_count) { 3155 DRM_ERROR("power well %s refcount/domain refcount mismatch " 3156 "(refcount %d/domains refcount %d)\n", 3157 power_well->name, power_well->count, 3158 domains_count); 3159 dump_domain_info = true; 3160 } 3161 } 3162 3163 if (dump_domain_info) { 3164 static bool dumped; 3165 3166 if (!dumped) { 3167 intel_power_domains_dump_info(dev_priv); 3168 dumped = true; 3169 } 3170 } 3171 3172 mutex_unlock(&power_domains->lock); 3173 } 3174 3175 /** 3176 * intel_runtime_pm_get - grab a runtime pm reference 3177 * @dev_priv: i915 device instance 3178 * 3179 * This function grabs a device-level runtime pm reference (mostly used for GEM 3180 * code to ensure the GTT or GT is on) and ensures that it is powered up. 3181 * 3182 * Any runtime pm reference obtained by this function must have a symmetric 3183 * call to intel_runtime_pm_put() to release the reference again. 3184 */ 3185 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 3186 { 3187 struct pci_dev *pdev = dev_priv->drm.pdev; 3188 struct device *kdev = &pdev->dev; 3189 int ret; 3190 3191 ret = pm_runtime_get_sync(kdev); 3192 WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3193 3194 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3195 assert_rpm_wakelock_held(dev_priv); 3196 } 3197 3198 /** 3199 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 3200 * @dev_priv: i915 device instance 3201 * 3202 * This function grabs a device-level runtime pm reference if the device is 3203 * already in use and ensures that it is powered up. 3204 * 3205 * Any runtime pm reference obtained by this function must have a symmetric 3206 * call to intel_runtime_pm_put() to release the reference again. 3207 */ 3208 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 3209 { 3210 struct pci_dev *pdev = dev_priv->drm.pdev; 3211 struct device *kdev = &pdev->dev; 3212 3213 if (IS_ENABLED(CONFIG_PM)) { 3214 int ret = pm_runtime_get_if_in_use(kdev); 3215 3216 /* 3217 * In cases runtime PM is disabled by the RPM core and we get 3218 * an -EINVAL return value we are not supposed to call this 3219 * function, since the power state is undefined. This applies 3220 * atm to the late/early system suspend/resume handlers. 3221 */ 3222 WARN_ONCE(ret < 0, 3223 "pm_runtime_get_if_in_use() failed: %d\n", ret); 3224 if (ret <= 0) 3225 return false; 3226 } 3227 3228 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3229 assert_rpm_wakelock_held(dev_priv); 3230 3231 return true; 3232 } 3233 3234 /** 3235 * intel_runtime_pm_get_noresume - grab a runtime pm reference 3236 * @dev_priv: i915 device instance 3237 * 3238 * This function grabs a device-level runtime pm reference (mostly used for GEM 3239 * code to ensure the GTT or GT is on). 3240 * 3241 * It will _not_ power up the device but instead only check that it's powered 3242 * on. Therefore it is only valid to call this functions from contexts where 3243 * the device is known to be powered up and where trying to power it up would 3244 * result in hilarity and deadlocks. That pretty much means only the system 3245 * suspend/resume code where this is used to grab runtime pm references for 3246 * delayed setup down in work items. 3247 * 3248 * Any runtime pm reference obtained by this function must have a symmetric 3249 * call to intel_runtime_pm_put() to release the reference again. 3250 */ 3251 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 3252 { 3253 struct pci_dev *pdev = dev_priv->drm.pdev; 3254 struct device *kdev = &pdev->dev; 3255 3256 assert_rpm_wakelock_held(dev_priv); 3257 pm_runtime_get_noresume(kdev); 3258 3259 atomic_inc(&dev_priv->runtime_pm.wakeref_count); 3260 } 3261 3262 /** 3263 * intel_runtime_pm_put - release a runtime pm reference 3264 * @dev_priv: i915 device instance 3265 * 3266 * This function drops the device-level runtime pm reference obtained by 3267 * intel_runtime_pm_get() and might power down the corresponding 3268 * hardware block right away if this is the last reference. 3269 */ 3270 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 3271 { 3272 struct pci_dev *pdev = dev_priv->drm.pdev; 3273 struct device *kdev = &pdev->dev; 3274 3275 assert_rpm_wakelock_held(dev_priv); 3276 atomic_dec(&dev_priv->runtime_pm.wakeref_count); 3277 3278 pm_runtime_mark_last_busy(kdev); 3279 pm_runtime_put_autosuspend(kdev); 3280 } 3281 3282 /** 3283 * intel_runtime_pm_enable - enable runtime pm 3284 * @dev_priv: i915 device instance 3285 * 3286 * This function enables runtime pm at the end of the driver load sequence. 3287 * 3288 * Note that this function does currently not enable runtime pm for the 3289 * subordinate display power domains. That is only done on the first modeset 3290 * using intel_display_set_init_power(). 3291 */ 3292 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 3293 { 3294 struct pci_dev *pdev = dev_priv->drm.pdev; 3295 struct device *kdev = &pdev->dev; 3296 3297 pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */ 3298 pm_runtime_mark_last_busy(kdev); 3299 3300 /* 3301 * Take a permanent reference to disable the RPM functionality and drop 3302 * it only when unloading the driver. Use the low level get/put helpers, 3303 * so the driver's own RPM reference tracking asserts also work on 3304 * platforms without RPM support. 3305 */ 3306 if (!HAS_RUNTIME_PM(dev_priv)) { 3307 int ret; 3308 3309 pm_runtime_dont_use_autosuspend(kdev); 3310 ret = pm_runtime_get_sync(kdev); 3311 WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret); 3312 } else { 3313 pm_runtime_use_autosuspend(kdev); 3314 } 3315 3316 /* 3317 * The core calls the driver load handler with an RPM reference held. 3318 * We drop that here and will reacquire it during unloading in 3319 * intel_power_domains_fini(). 3320 */ 3321 pm_runtime_put_autosuspend(kdev); 3322 } 3323