1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 #define GEN9_ENABLE_DC5(dev) 0 53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) 54 55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 56 for (i = 0; \ 57 i < (power_domains)->power_well_count && \ 58 ((power_well) = &(power_domains)->power_wells[i]); \ 59 i++) \ 60 if ((power_well)->domains & (domain_mask)) 61 62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 63 for (i = (power_domains)->power_well_count - 1; \ 64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 65 i--) \ 66 if ((power_well)->domains & (domain_mask)) 67 68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 69 int power_well_id); 70 71 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 72 struct i915_power_well *power_well) 73 { 74 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 75 power_well->ops->enable(dev_priv, power_well); 76 power_well->hw_enabled = true; 77 } 78 79 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 80 struct i915_power_well *power_well) 81 { 82 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 83 power_well->hw_enabled = false; 84 power_well->ops->disable(dev_priv, power_well); 85 } 86 87 /* 88 * We should only use the power well if we explicitly asked the hardware to 89 * enable it, so check if it's enabled and also check if we've requested it to 90 * be enabled. 91 */ 92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 93 struct i915_power_well *power_well) 94 { 95 return I915_READ(HSW_PWR_WELL_DRIVER) == 96 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 97 } 98 99 /** 100 * __intel_display_power_is_enabled - unlocked check for a power domain 101 * @dev_priv: i915 device instance 102 * @domain: power domain to check 103 * 104 * This is the unlocked version of intel_display_power_is_enabled() and should 105 * only be used from error capture and recovery code where deadlocks are 106 * possible. 107 * 108 * Returns: 109 * True when the power domain is enabled, false otherwise. 110 */ 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 112 enum intel_display_power_domain domain) 113 { 114 struct i915_power_domains *power_domains; 115 struct i915_power_well *power_well; 116 bool is_enabled; 117 int i; 118 119 if (dev_priv->pm.suspended) 120 return false; 121 122 power_domains = &dev_priv->power_domains; 123 124 is_enabled = true; 125 126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 127 if (power_well->always_on) 128 continue; 129 130 if (!power_well->hw_enabled) { 131 is_enabled = false; 132 break; 133 } 134 } 135 136 return is_enabled; 137 } 138 139 /** 140 * intel_display_power_is_enabled - check for a power domain 141 * @dev_priv: i915 device instance 142 * @domain: power domain to check 143 * 144 * This function can be used to check the hw power domain state. It is mostly 145 * used in hardware state readout functions. Everywhere else code should rely 146 * upon explicit power domain reference counting to ensure that the hardware 147 * block is powered up before accessing it. 148 * 149 * Callers must hold the relevant modesetting locks to ensure that concurrent 150 * threads can't disable the power well while the caller tries to read a few 151 * registers. 152 * 153 * Returns: 154 * True when the power domain is enabled, false otherwise. 155 */ 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 157 enum intel_display_power_domain domain) 158 { 159 struct i915_power_domains *power_domains; 160 bool ret; 161 162 power_domains = &dev_priv->power_domains; 163 164 mutex_lock(&power_domains->lock); 165 ret = __intel_display_power_is_enabled(dev_priv, domain); 166 mutex_unlock(&power_domains->lock); 167 168 return ret; 169 } 170 171 /** 172 * intel_display_set_init_power - set the initial power domain state 173 * @dev_priv: i915 device instance 174 * @enable: whether to enable or disable the initial power domain state 175 * 176 * For simplicity our driver load/unload and system suspend/resume code assumes 177 * that all power domains are always enabled. This functions controls the state 178 * of this little hack. While the initial power domain state is enabled runtime 179 * pm is effectively disabled. 180 */ 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 182 bool enable) 183 { 184 if (dev_priv->power_domains.init_power_on == enable) 185 return; 186 187 if (enable) 188 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 189 else 190 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 191 192 dev_priv->power_domains.init_power_on = enable; 193 } 194 195 /* 196 * Starting with Haswell, we have a "Power Down Well" that can be turned off 197 * when not needed anymore. We have 4 registers that can request the power well 198 * to be enabled, and it will only be disabled if none of the registers is 199 * requesting it to be enabled. 200 */ 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 202 { 203 struct drm_device *dev = dev_priv->dev; 204 205 /* 206 * After we re-enable the power well, if we touch VGA register 0x3d5 207 * we'll get unclaimed register interrupts. This stops after we write 208 * anything to the VGA MSR register. The vgacon module uses this 209 * register all the time, so if we unbind our driver and, as a 210 * consequence, bind vgacon, we'll get stuck in an infinite loop at 211 * console_unlock(). So make here we touch the VGA MSR register, making 212 * sure vgacon can keep working normally without triggering interrupts 213 * and error messages. 214 */ 215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 216 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 217 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 218 219 if (IS_BROADWELL(dev)) 220 gen8_irq_power_well_post_enable(dev_priv, 221 1 << PIPE_C | 1 << PIPE_B); 222 } 223 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 225 struct i915_power_well *power_well) 226 { 227 struct drm_device *dev = dev_priv->dev; 228 229 /* 230 * After we re-enable the power well, if we touch VGA register 0x3d5 231 * we'll get unclaimed register interrupts. This stops after we write 232 * anything to the VGA MSR register. The vgacon module uses this 233 * register all the time, so if we unbind our driver and, as a 234 * consequence, bind vgacon, we'll get stuck in an infinite loop at 235 * console_unlock(). So make here we touch the VGA MSR register, making 236 * sure vgacon can keep working normally without triggering interrupts 237 * and error messages. 238 */ 239 if (power_well->data == SKL_DISP_PW_2) { 240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 241 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 242 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 243 244 gen8_irq_power_well_post_enable(dev_priv, 245 1 << PIPE_C | 1 << PIPE_B); 246 } 247 248 if (power_well->data == SKL_DISP_PW_1) { 249 intel_prepare_ddi(dev); 250 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); 251 } 252 } 253 254 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 255 struct i915_power_well *power_well, bool enable) 256 { 257 bool is_enabled, enable_requested; 258 uint32_t tmp; 259 260 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 261 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 262 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 263 264 if (enable) { 265 if (!enable_requested) 266 I915_WRITE(HSW_PWR_WELL_DRIVER, 267 HSW_PWR_WELL_ENABLE_REQUEST); 268 269 if (!is_enabled) { 270 DRM_DEBUG_KMS("Enabling power well\n"); 271 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 272 HSW_PWR_WELL_STATE_ENABLED), 20)) 273 DRM_ERROR("Timeout enabling power well\n"); 274 hsw_power_well_post_enable(dev_priv); 275 } 276 277 } else { 278 if (enable_requested) { 279 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 280 POSTING_READ(HSW_PWR_WELL_DRIVER); 281 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 282 } 283 } 284 } 285 286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 287 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 288 BIT(POWER_DOMAIN_PIPE_B) | \ 289 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 290 BIT(POWER_DOMAIN_PIPE_C) | \ 291 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 292 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 293 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 294 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 295 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 296 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 297 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 298 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 299 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 300 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ 301 BIT(POWER_DOMAIN_AUX_B) | \ 302 BIT(POWER_DOMAIN_AUX_C) | \ 303 BIT(POWER_DOMAIN_AUX_D) | \ 304 BIT(POWER_DOMAIN_AUDIO) | \ 305 BIT(POWER_DOMAIN_VGA) | \ 306 BIT(POWER_DOMAIN_INIT)) 307 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 308 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 309 BIT(POWER_DOMAIN_PLLS) | \ 310 BIT(POWER_DOMAIN_PIPE_A) | \ 311 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 312 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 313 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 314 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 315 BIT(POWER_DOMAIN_AUX_A) | \ 316 BIT(POWER_DOMAIN_INIT)) 317 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 318 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 319 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 320 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \ 321 BIT(POWER_DOMAIN_INIT)) 322 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 323 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 324 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 325 BIT(POWER_DOMAIN_INIT)) 326 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 327 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 328 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 329 BIT(POWER_DOMAIN_INIT)) 330 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 331 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 332 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 333 BIT(POWER_DOMAIN_INIT)) 334 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ 335 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 336 BIT(POWER_DOMAIN_PLLS) | \ 337 BIT(POWER_DOMAIN_INIT)) 338 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 339 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 340 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 341 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ 342 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ 343 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ 344 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ 345 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ 346 BIT(POWER_DOMAIN_INIT)) 347 348 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 349 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 350 BIT(POWER_DOMAIN_PIPE_B) | \ 351 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 352 BIT(POWER_DOMAIN_PIPE_C) | \ 353 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 354 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 355 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 356 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 357 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 358 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 359 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 360 BIT(POWER_DOMAIN_AUX_B) | \ 361 BIT(POWER_DOMAIN_AUX_C) | \ 362 BIT(POWER_DOMAIN_AUDIO) | \ 363 BIT(POWER_DOMAIN_VGA) | \ 364 BIT(POWER_DOMAIN_INIT)) 365 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 366 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 367 BIT(POWER_DOMAIN_PIPE_A) | \ 368 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 369 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 370 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 371 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 372 BIT(POWER_DOMAIN_AUX_A) | \ 373 BIT(POWER_DOMAIN_PLLS) | \ 374 BIT(POWER_DOMAIN_INIT)) 375 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 376 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 377 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ 378 BIT(POWER_DOMAIN_INIT)) 379 380 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 381 { 382 struct drm_device *dev = dev_priv->dev; 383 384 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); 385 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 386 "DC9 already programmed to be enabled.\n"); 387 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 388 "DC5 still not disabled to enable DC9.\n"); 389 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 390 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 391 392 /* 393 * TODO: check for the following to verify the conditions to enter DC9 394 * state are satisfied: 395 * 1] Check relevant display engine registers to verify if mode set 396 * disable sequence was followed. 397 * 2] Check if display uninitialize sequence is initialized. 398 */ 399 } 400 401 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 402 { 403 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 404 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 405 "DC9 already programmed to be disabled.\n"); 406 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 407 "DC5 still not disabled.\n"); 408 409 /* 410 * TODO: check for the following to verify DC9 state was indeed 411 * entered before programming to disable it: 412 * 1] Check relevant display engine registers to verify if mode 413 * set disable sequence was followed. 414 * 2] Check if display uninitialize sequence is initialized. 415 */ 416 } 417 418 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 419 { 420 uint32_t val; 421 422 assert_can_enable_dc9(dev_priv); 423 424 DRM_DEBUG_KMS("Enabling DC9\n"); 425 426 val = I915_READ(DC_STATE_EN); 427 val |= DC_STATE_EN_DC9; 428 I915_WRITE(DC_STATE_EN, val); 429 POSTING_READ(DC_STATE_EN); 430 } 431 432 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 433 { 434 uint32_t val; 435 436 assert_can_disable_dc9(dev_priv); 437 438 DRM_DEBUG_KMS("Disabling DC9\n"); 439 440 val = I915_READ(DC_STATE_EN); 441 val &= ~DC_STATE_EN_DC9; 442 I915_WRITE(DC_STATE_EN, val); 443 POSTING_READ(DC_STATE_EN); 444 } 445 446 static void gen9_set_dc_state_debugmask_memory_up( 447 struct drm_i915_private *dev_priv) 448 { 449 uint32_t val; 450 451 /* The below bit doesn't need to be cleared ever afterwards */ 452 val = I915_READ(DC_STATE_DEBUG); 453 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { 454 val |= DC_STATE_DEBUG_MASK_MEMORY_UP; 455 I915_WRITE(DC_STATE_DEBUG, val); 456 POSTING_READ(DC_STATE_DEBUG); 457 } 458 } 459 460 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 461 { 462 struct drm_device *dev = dev_priv->dev; 463 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 464 SKL_DISP_PW_2); 465 466 WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); 467 WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 468 WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 469 470 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 471 "DC5 already programmed to be enabled.\n"); 472 WARN(dev_priv->pm.suspended, 473 "DC5 cannot be enabled, if platform is runtime-suspended.\n"); 474 475 assert_csr_loaded(dev_priv); 476 } 477 478 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) 479 { 480 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 481 SKL_DISP_PW_2); 482 /* 483 * During initialization, the firmware may not be loaded yet. 484 * We still want to make sure that the DC enabling flag is cleared. 485 */ 486 if (dev_priv->power_domains.initializing) 487 return; 488 489 WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); 490 WARN(dev_priv->pm.suspended, 491 "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); 492 } 493 494 static void gen9_enable_dc5(struct drm_i915_private *dev_priv) 495 { 496 uint32_t val; 497 498 assert_can_enable_dc5(dev_priv); 499 500 DRM_DEBUG_KMS("Enabling DC5\n"); 501 502 gen9_set_dc_state_debugmask_memory_up(dev_priv); 503 504 val = I915_READ(DC_STATE_EN); 505 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; 506 val |= DC_STATE_EN_UPTO_DC5; 507 I915_WRITE(DC_STATE_EN, val); 508 POSTING_READ(DC_STATE_EN); 509 } 510 511 static void gen9_disable_dc5(struct drm_i915_private *dev_priv) 512 { 513 uint32_t val; 514 515 assert_can_disable_dc5(dev_priv); 516 517 DRM_DEBUG_KMS("Disabling DC5\n"); 518 519 val = I915_READ(DC_STATE_EN); 520 val &= ~DC_STATE_EN_UPTO_DC5; 521 I915_WRITE(DC_STATE_EN, val); 522 POSTING_READ(DC_STATE_EN); 523 } 524 525 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 526 { 527 struct drm_device *dev = dev_priv->dev; 528 529 WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); 530 WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 531 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 532 "Backlight is not disabled.\n"); 533 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 534 "DC6 already programmed to be enabled.\n"); 535 536 assert_csr_loaded(dev_priv); 537 } 538 539 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) 540 { 541 /* 542 * During initialization, the firmware may not be loaded yet. 543 * We still want to make sure that the DC enabling flag is cleared. 544 */ 545 if (dev_priv->power_domains.initializing) 546 return; 547 548 assert_csr_loaded(dev_priv); 549 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 550 "DC6 already programmed to be disabled.\n"); 551 } 552 553 static void skl_enable_dc6(struct drm_i915_private *dev_priv) 554 { 555 uint32_t val; 556 557 assert_can_enable_dc6(dev_priv); 558 559 DRM_DEBUG_KMS("Enabling DC6\n"); 560 561 gen9_set_dc_state_debugmask_memory_up(dev_priv); 562 563 val = I915_READ(DC_STATE_EN); 564 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; 565 val |= DC_STATE_EN_UPTO_DC6; 566 I915_WRITE(DC_STATE_EN, val); 567 POSTING_READ(DC_STATE_EN); 568 } 569 570 static void skl_disable_dc6(struct drm_i915_private *dev_priv) 571 { 572 uint32_t val; 573 574 assert_can_disable_dc6(dev_priv); 575 576 DRM_DEBUG_KMS("Disabling DC6\n"); 577 578 val = I915_READ(DC_STATE_EN); 579 val &= ~DC_STATE_EN_UPTO_DC6; 580 I915_WRITE(DC_STATE_EN, val); 581 POSTING_READ(DC_STATE_EN); 582 } 583 584 static void skl_set_power_well(struct drm_i915_private *dev_priv, 585 struct i915_power_well *power_well, bool enable) 586 { 587 struct drm_device *dev = dev_priv->dev; 588 uint32_t tmp, fuse_status; 589 uint32_t req_mask, state_mask; 590 bool is_enabled, enable_requested, check_fuse_status = false; 591 592 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 593 fuse_status = I915_READ(SKL_FUSE_STATUS); 594 595 switch (power_well->data) { 596 case SKL_DISP_PW_1: 597 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 598 SKL_FUSE_PG0_DIST_STATUS), 1)) { 599 DRM_ERROR("PG0 not enabled\n"); 600 return; 601 } 602 break; 603 case SKL_DISP_PW_2: 604 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 605 DRM_ERROR("PG1 in disabled state\n"); 606 return; 607 } 608 break; 609 case SKL_DISP_PW_DDI_A_E: 610 case SKL_DISP_PW_DDI_B: 611 case SKL_DISP_PW_DDI_C: 612 case SKL_DISP_PW_DDI_D: 613 case SKL_DISP_PW_MISC_IO: 614 break; 615 default: 616 WARN(1, "Unknown power well %lu\n", power_well->data); 617 return; 618 } 619 620 req_mask = SKL_POWER_WELL_REQ(power_well->data); 621 enable_requested = tmp & req_mask; 622 state_mask = SKL_POWER_WELL_STATE(power_well->data); 623 is_enabled = tmp & state_mask; 624 625 if (enable) { 626 if (!enable_requested) { 627 WARN((tmp & state_mask) && 628 !I915_READ(HSW_PWR_WELL_BIOS), 629 "Invalid for power well status to be enabled, unless done by the BIOS, \ 630 when request is to disable!\n"); 631 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && 632 power_well->data == SKL_DISP_PW_2) { 633 if (SKL_ENABLE_DC6(dev)) { 634 skl_disable_dc6(dev_priv); 635 /* 636 * DDI buffer programming unnecessary during driver-load/resume 637 * as it's already done during modeset initialization then. 638 * It's also invalid here as encoder list is still uninitialized. 639 */ 640 if (!dev_priv->power_domains.initializing) 641 intel_prepare_ddi(dev); 642 } else { 643 gen9_disable_dc5(dev_priv); 644 } 645 } 646 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 647 } 648 649 if (!is_enabled) { 650 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 651 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 652 state_mask), 1)) 653 DRM_ERROR("%s enable timeout\n", 654 power_well->name); 655 check_fuse_status = true; 656 } 657 } else { 658 if (enable_requested) { 659 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 660 POSTING_READ(HSW_PWR_WELL_DRIVER); 661 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 662 663 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && 664 power_well->data == SKL_DISP_PW_2) { 665 enum csr_state state; 666 /* TODO: wait for a completion event or 667 * similar here instead of busy 668 * waiting using wait_for function. 669 */ 670 wait_for((state = intel_csr_load_status_get(dev_priv)) != 671 FW_UNINITIALIZED, 1000); 672 if (state != FW_LOADED) 673 DRM_ERROR("CSR firmware not ready (%d)\n", 674 state); 675 else 676 if (SKL_ENABLE_DC6(dev)) 677 skl_enable_dc6(dev_priv); 678 else 679 gen9_enable_dc5(dev_priv); 680 } 681 } 682 } 683 684 if (check_fuse_status) { 685 if (power_well->data == SKL_DISP_PW_1) { 686 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 687 SKL_FUSE_PG1_DIST_STATUS), 1)) 688 DRM_ERROR("PG1 distributing status timeout\n"); 689 } else if (power_well->data == SKL_DISP_PW_2) { 690 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 691 SKL_FUSE_PG2_DIST_STATUS), 1)) 692 DRM_ERROR("PG2 distributing status timeout\n"); 693 } 694 } 695 696 if (enable && !is_enabled) 697 skl_power_well_post_enable(dev_priv, power_well); 698 } 699 700 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 701 struct i915_power_well *power_well) 702 { 703 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 704 705 /* 706 * We're taking over the BIOS, so clear any requests made by it since 707 * the driver is in charge now. 708 */ 709 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 710 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 711 } 712 713 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 714 struct i915_power_well *power_well) 715 { 716 hsw_set_power_well(dev_priv, power_well, true); 717 } 718 719 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 720 struct i915_power_well *power_well) 721 { 722 hsw_set_power_well(dev_priv, power_well, false); 723 } 724 725 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 726 struct i915_power_well *power_well) 727 { 728 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 729 SKL_POWER_WELL_STATE(power_well->data); 730 731 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 732 } 733 734 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 735 struct i915_power_well *power_well) 736 { 737 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 738 739 /* Clear any request made by BIOS as driver is taking over */ 740 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 741 } 742 743 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 744 struct i915_power_well *power_well) 745 { 746 skl_set_power_well(dev_priv, power_well, true); 747 } 748 749 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 750 struct i915_power_well *power_well) 751 { 752 skl_set_power_well(dev_priv, power_well, false); 753 } 754 755 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 756 struct i915_power_well *power_well) 757 { 758 } 759 760 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 761 struct i915_power_well *power_well) 762 { 763 return true; 764 } 765 766 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 767 struct i915_power_well *power_well, bool enable) 768 { 769 enum punit_power_well power_well_id = power_well->data; 770 u32 mask; 771 u32 state; 772 u32 ctrl; 773 774 mask = PUNIT_PWRGT_MASK(power_well_id); 775 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 776 PUNIT_PWRGT_PWR_GATE(power_well_id); 777 778 mutex_lock(&dev_priv->rps.hw_lock); 779 780 #define COND \ 781 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 782 783 if (COND) 784 goto out; 785 786 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 787 ctrl &= ~mask; 788 ctrl |= state; 789 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 790 791 if (wait_for(COND, 100)) 792 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 793 state, 794 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 795 796 #undef COND 797 798 out: 799 mutex_unlock(&dev_priv->rps.hw_lock); 800 } 801 802 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 803 struct i915_power_well *power_well) 804 { 805 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 806 } 807 808 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 809 struct i915_power_well *power_well) 810 { 811 vlv_set_power_well(dev_priv, power_well, true); 812 } 813 814 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 815 struct i915_power_well *power_well) 816 { 817 vlv_set_power_well(dev_priv, power_well, false); 818 } 819 820 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 821 struct i915_power_well *power_well) 822 { 823 int power_well_id = power_well->data; 824 bool enabled = false; 825 u32 mask; 826 u32 state; 827 u32 ctrl; 828 829 mask = PUNIT_PWRGT_MASK(power_well_id); 830 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 831 832 mutex_lock(&dev_priv->rps.hw_lock); 833 834 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 835 /* 836 * We only ever set the power-on and power-gate states, anything 837 * else is unexpected. 838 */ 839 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 840 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 841 if (state == ctrl) 842 enabled = true; 843 844 /* 845 * A transient state at this point would mean some unexpected party 846 * is poking at the power controls too. 847 */ 848 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 849 WARN_ON(ctrl != state); 850 851 mutex_unlock(&dev_priv->rps.hw_lock); 852 853 return enabled; 854 } 855 856 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 857 { 858 859 spin_lock_irq(&dev_priv->irq_lock); 860 valleyview_enable_display_irqs(dev_priv); 861 spin_unlock_irq(&dev_priv->irq_lock); 862 863 /* 864 * During driver initialization/resume we can avoid restoring the 865 * part of the HW/SW state that will be inited anyway explicitly. 866 */ 867 if (dev_priv->power_domains.initializing) 868 return; 869 870 intel_hpd_init(dev_priv); 871 872 i915_redisable_vga_power_on(dev_priv->dev); 873 } 874 875 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 876 { 877 spin_lock_irq(&dev_priv->irq_lock); 878 valleyview_disable_display_irqs(dev_priv); 879 spin_unlock_irq(&dev_priv->irq_lock); 880 881 vlv_power_sequencer_reset(dev_priv); 882 } 883 884 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 885 struct i915_power_well *power_well) 886 { 887 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 888 889 vlv_set_power_well(dev_priv, power_well, true); 890 891 vlv_display_power_well_init(dev_priv); 892 } 893 894 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 895 struct i915_power_well *power_well) 896 { 897 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 898 899 vlv_display_power_well_deinit(dev_priv); 900 901 vlv_set_power_well(dev_priv, power_well, false); 902 } 903 904 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 905 struct i915_power_well *power_well) 906 { 907 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 908 909 /* 910 * Enable the CRI clock source so we can get at the 911 * display and the reference clock for VGA 912 * hotplug / manual detection. 913 */ 914 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | 915 DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 916 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 917 918 vlv_set_power_well(dev_priv, power_well, true); 919 920 /* 921 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 922 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 923 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 924 * b. The other bits such as sfr settings / modesel may all 925 * be set to 0. 926 * 927 * This should only be done on init and resume from S3 with 928 * both PLLs disabled, or we risk losing DPIO and PLL 929 * synchronization. 930 */ 931 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 932 } 933 934 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 935 struct i915_power_well *power_well) 936 { 937 enum pipe pipe; 938 939 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 940 941 for_each_pipe(dev_priv, pipe) 942 assert_pll_disabled(dev_priv, pipe); 943 944 /* Assert common reset */ 945 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 946 947 vlv_set_power_well(dev_priv, power_well, false); 948 } 949 950 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 951 struct i915_power_well *power_well) 952 { 953 enum dpio_phy phy; 954 955 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 956 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 957 958 /* 959 * Enable the CRI clock source so we can get at the 960 * display and the reference clock for VGA 961 * hotplug / manual detection. 962 */ 963 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 964 phy = DPIO_PHY0; 965 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | 966 DPLL_REF_CLK_ENABLE_VLV); 967 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | 968 DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 969 } else { 970 phy = DPIO_PHY1; 971 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS | 972 DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 973 } 974 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 975 vlv_set_power_well(dev_priv, power_well, true); 976 977 /* Poll for phypwrgood signal */ 978 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 979 DRM_ERROR("Display PHY %d is not power up\n", phy); 980 981 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 982 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 983 } 984 985 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 986 struct i915_power_well *power_well) 987 { 988 enum dpio_phy phy; 989 990 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 991 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 992 993 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 994 phy = DPIO_PHY0; 995 assert_pll_disabled(dev_priv, PIPE_A); 996 assert_pll_disabled(dev_priv, PIPE_B); 997 } else { 998 phy = DPIO_PHY1; 999 assert_pll_disabled(dev_priv, PIPE_C); 1000 } 1001 1002 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1003 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1004 1005 vlv_set_power_well(dev_priv, power_well, false); 1006 } 1007 1008 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1009 struct i915_power_well *power_well) 1010 { 1011 enum pipe pipe = power_well->data; 1012 bool enabled; 1013 u32 state, ctrl; 1014 1015 mutex_lock(&dev_priv->rps.hw_lock); 1016 1017 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1018 /* 1019 * We only ever set the power-on and power-gate states, anything 1020 * else is unexpected. 1021 */ 1022 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1023 enabled = state == DP_SSS_PWR_ON(pipe); 1024 1025 /* 1026 * A transient state at this point would mean some unexpected party 1027 * is poking at the power controls too. 1028 */ 1029 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1030 WARN_ON(ctrl << 16 != state); 1031 1032 mutex_unlock(&dev_priv->rps.hw_lock); 1033 1034 return enabled; 1035 } 1036 1037 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1038 struct i915_power_well *power_well, 1039 bool enable) 1040 { 1041 enum pipe pipe = power_well->data; 1042 u32 state; 1043 u32 ctrl; 1044 1045 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1046 1047 mutex_lock(&dev_priv->rps.hw_lock); 1048 1049 #define COND \ 1050 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1051 1052 if (COND) 1053 goto out; 1054 1055 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1056 ctrl &= ~DP_SSC_MASK(pipe); 1057 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1058 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1059 1060 if (wait_for(COND, 100)) 1061 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1062 state, 1063 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1064 1065 #undef COND 1066 1067 out: 1068 mutex_unlock(&dev_priv->rps.hw_lock); 1069 } 1070 1071 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1072 struct i915_power_well *power_well) 1073 { 1074 WARN_ON_ONCE(power_well->data != PIPE_A); 1075 1076 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1077 } 1078 1079 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1080 struct i915_power_well *power_well) 1081 { 1082 WARN_ON_ONCE(power_well->data != PIPE_A); 1083 1084 chv_set_pipe_power_well(dev_priv, power_well, true); 1085 1086 vlv_display_power_well_init(dev_priv); 1087 } 1088 1089 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1090 struct i915_power_well *power_well) 1091 { 1092 WARN_ON_ONCE(power_well->data != PIPE_A); 1093 1094 vlv_display_power_well_deinit(dev_priv); 1095 1096 chv_set_pipe_power_well(dev_priv, power_well, false); 1097 } 1098 1099 /** 1100 * intel_display_power_get - grab a power domain reference 1101 * @dev_priv: i915 device instance 1102 * @domain: power domain to reference 1103 * 1104 * This function grabs a power domain reference for @domain and ensures that the 1105 * power domain and all its parents are powered up. Therefore users should only 1106 * grab a reference to the innermost power domain they need. 1107 * 1108 * Any power domain reference obtained by this function must have a symmetric 1109 * call to intel_display_power_put() to release the reference again. 1110 */ 1111 void intel_display_power_get(struct drm_i915_private *dev_priv, 1112 enum intel_display_power_domain domain) 1113 { 1114 struct i915_power_domains *power_domains; 1115 struct i915_power_well *power_well; 1116 int i; 1117 1118 intel_runtime_pm_get(dev_priv); 1119 1120 power_domains = &dev_priv->power_domains; 1121 1122 mutex_lock(&power_domains->lock); 1123 1124 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1125 if (!power_well->count++) 1126 intel_power_well_enable(dev_priv, power_well); 1127 } 1128 1129 power_domains->domain_use_count[domain]++; 1130 1131 mutex_unlock(&power_domains->lock); 1132 } 1133 1134 /** 1135 * intel_display_power_put - release a power domain reference 1136 * @dev_priv: i915 device instance 1137 * @domain: power domain to reference 1138 * 1139 * This function drops the power domain reference obtained by 1140 * intel_display_power_get() and might power down the corresponding hardware 1141 * block right away if this is the last reference. 1142 */ 1143 void intel_display_power_put(struct drm_i915_private *dev_priv, 1144 enum intel_display_power_domain domain) 1145 { 1146 struct i915_power_domains *power_domains; 1147 struct i915_power_well *power_well; 1148 int i; 1149 1150 power_domains = &dev_priv->power_domains; 1151 1152 mutex_lock(&power_domains->lock); 1153 1154 WARN_ON(!power_domains->domain_use_count[domain]); 1155 power_domains->domain_use_count[domain]--; 1156 1157 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1158 WARN_ON(!power_well->count); 1159 1160 if (!--power_well->count && i915.disable_power_well) 1161 intel_power_well_disable(dev_priv, power_well); 1162 } 1163 1164 mutex_unlock(&power_domains->lock); 1165 1166 intel_runtime_pm_put(dev_priv); 1167 } 1168 1169 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1170 1171 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1172 BIT(POWER_DOMAIN_PIPE_A) | \ 1173 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1174 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 1175 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 1176 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1177 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1178 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1179 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1180 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 1181 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 1182 BIT(POWER_DOMAIN_PORT_CRT) | \ 1183 BIT(POWER_DOMAIN_PLLS) | \ 1184 BIT(POWER_DOMAIN_AUX_A) | \ 1185 BIT(POWER_DOMAIN_AUX_B) | \ 1186 BIT(POWER_DOMAIN_AUX_C) | \ 1187 BIT(POWER_DOMAIN_AUX_D) | \ 1188 BIT(POWER_DOMAIN_INIT)) 1189 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1190 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 1191 BIT(POWER_DOMAIN_INIT)) 1192 1193 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1194 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1195 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1196 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1197 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1198 BIT(POWER_DOMAIN_INIT)) 1199 1200 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 1201 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 1202 1203 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1204 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1205 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1206 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1207 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1208 BIT(POWER_DOMAIN_PORT_CRT) | \ 1209 BIT(POWER_DOMAIN_AUX_B) | \ 1210 BIT(POWER_DOMAIN_AUX_C) | \ 1211 BIT(POWER_DOMAIN_INIT)) 1212 1213 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1214 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1215 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1216 BIT(POWER_DOMAIN_AUX_B) | \ 1217 BIT(POWER_DOMAIN_INIT)) 1218 1219 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1220 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1221 BIT(POWER_DOMAIN_AUX_B) | \ 1222 BIT(POWER_DOMAIN_INIT)) 1223 1224 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1225 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1226 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1227 BIT(POWER_DOMAIN_AUX_C) | \ 1228 BIT(POWER_DOMAIN_INIT)) 1229 1230 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1231 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1232 BIT(POWER_DOMAIN_AUX_C) | \ 1233 BIT(POWER_DOMAIN_INIT)) 1234 1235 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1236 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 1237 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 1238 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 1239 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 1240 BIT(POWER_DOMAIN_AUX_B) | \ 1241 BIT(POWER_DOMAIN_AUX_C) | \ 1242 BIT(POWER_DOMAIN_INIT)) 1243 1244 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1245 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 1246 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 1247 BIT(POWER_DOMAIN_AUX_D) | \ 1248 BIT(POWER_DOMAIN_INIT)) 1249 1250 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1251 .sync_hw = i9xx_always_on_power_well_noop, 1252 .enable = i9xx_always_on_power_well_noop, 1253 .disable = i9xx_always_on_power_well_noop, 1254 .is_enabled = i9xx_always_on_power_well_enabled, 1255 }; 1256 1257 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1258 .sync_hw = chv_pipe_power_well_sync_hw, 1259 .enable = chv_pipe_power_well_enable, 1260 .disable = chv_pipe_power_well_disable, 1261 .is_enabled = chv_pipe_power_well_enabled, 1262 }; 1263 1264 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1265 .sync_hw = vlv_power_well_sync_hw, 1266 .enable = chv_dpio_cmn_power_well_enable, 1267 .disable = chv_dpio_cmn_power_well_disable, 1268 .is_enabled = vlv_power_well_enabled, 1269 }; 1270 1271 static struct i915_power_well i9xx_always_on_power_well[] = { 1272 { 1273 .name = "always-on", 1274 .always_on = 1, 1275 .domains = POWER_DOMAIN_MASK, 1276 .ops = &i9xx_always_on_power_well_ops, 1277 }, 1278 }; 1279 1280 static const struct i915_power_well_ops hsw_power_well_ops = { 1281 .sync_hw = hsw_power_well_sync_hw, 1282 .enable = hsw_power_well_enable, 1283 .disable = hsw_power_well_disable, 1284 .is_enabled = hsw_power_well_enabled, 1285 }; 1286 1287 static const struct i915_power_well_ops skl_power_well_ops = { 1288 .sync_hw = skl_power_well_sync_hw, 1289 .enable = skl_power_well_enable, 1290 .disable = skl_power_well_disable, 1291 .is_enabled = skl_power_well_enabled, 1292 }; 1293 1294 static struct i915_power_well hsw_power_wells[] = { 1295 { 1296 .name = "always-on", 1297 .always_on = 1, 1298 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 1299 .ops = &i9xx_always_on_power_well_ops, 1300 }, 1301 { 1302 .name = "display", 1303 .domains = HSW_DISPLAY_POWER_DOMAINS, 1304 .ops = &hsw_power_well_ops, 1305 }, 1306 }; 1307 1308 static struct i915_power_well bdw_power_wells[] = { 1309 { 1310 .name = "always-on", 1311 .always_on = 1, 1312 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 1313 .ops = &i9xx_always_on_power_well_ops, 1314 }, 1315 { 1316 .name = "display", 1317 .domains = BDW_DISPLAY_POWER_DOMAINS, 1318 .ops = &hsw_power_well_ops, 1319 }, 1320 }; 1321 1322 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1323 .sync_hw = vlv_power_well_sync_hw, 1324 .enable = vlv_display_power_well_enable, 1325 .disable = vlv_display_power_well_disable, 1326 .is_enabled = vlv_power_well_enabled, 1327 }; 1328 1329 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1330 .sync_hw = vlv_power_well_sync_hw, 1331 .enable = vlv_dpio_cmn_power_well_enable, 1332 .disable = vlv_dpio_cmn_power_well_disable, 1333 .is_enabled = vlv_power_well_enabled, 1334 }; 1335 1336 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1337 .sync_hw = vlv_power_well_sync_hw, 1338 .enable = vlv_power_well_enable, 1339 .disable = vlv_power_well_disable, 1340 .is_enabled = vlv_power_well_enabled, 1341 }; 1342 1343 static struct i915_power_well vlv_power_wells[] = { 1344 { 1345 .name = "always-on", 1346 .always_on = 1, 1347 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1348 .ops = &i9xx_always_on_power_well_ops, 1349 }, 1350 { 1351 .name = "display", 1352 .domains = VLV_DISPLAY_POWER_DOMAINS, 1353 .data = PUNIT_POWER_WELL_DISP2D, 1354 .ops = &vlv_display_power_well_ops, 1355 }, 1356 { 1357 .name = "dpio-tx-b-01", 1358 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1359 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1360 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1361 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1362 .ops = &vlv_dpio_power_well_ops, 1363 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1364 }, 1365 { 1366 .name = "dpio-tx-b-23", 1367 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1368 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1369 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1370 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1371 .ops = &vlv_dpio_power_well_ops, 1372 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1373 }, 1374 { 1375 .name = "dpio-tx-c-01", 1376 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1377 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1378 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1379 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1380 .ops = &vlv_dpio_power_well_ops, 1381 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1382 }, 1383 { 1384 .name = "dpio-tx-c-23", 1385 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1386 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1387 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1388 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1389 .ops = &vlv_dpio_power_well_ops, 1390 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1391 }, 1392 { 1393 .name = "dpio-common", 1394 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1395 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1396 .ops = &vlv_dpio_cmn_power_well_ops, 1397 }, 1398 }; 1399 1400 static struct i915_power_well chv_power_wells[] = { 1401 { 1402 .name = "always-on", 1403 .always_on = 1, 1404 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1405 .ops = &i9xx_always_on_power_well_ops, 1406 }, 1407 { 1408 .name = "display", 1409 /* 1410 * Pipe A power well is the new disp2d well. Pipe B and C 1411 * power wells don't actually exist. Pipe A power well is 1412 * required for any pipe to work. 1413 */ 1414 .domains = VLV_DISPLAY_POWER_DOMAINS, 1415 .data = PIPE_A, 1416 .ops = &chv_pipe_power_well_ops, 1417 }, 1418 { 1419 .name = "dpio-common-bc", 1420 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1421 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1422 .ops = &chv_dpio_cmn_power_well_ops, 1423 }, 1424 { 1425 .name = "dpio-common-d", 1426 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1427 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1428 .ops = &chv_dpio_cmn_power_well_ops, 1429 }, 1430 }; 1431 1432 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1433 int power_well_id) 1434 { 1435 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1436 struct i915_power_well *power_well; 1437 int i; 1438 1439 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1440 if (power_well->data == power_well_id) 1441 return power_well; 1442 } 1443 1444 return NULL; 1445 } 1446 1447 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1448 int power_well_id) 1449 { 1450 struct i915_power_well *power_well; 1451 bool ret; 1452 1453 power_well = lookup_power_well(dev_priv, power_well_id); 1454 ret = power_well->ops->is_enabled(dev_priv, power_well); 1455 1456 return ret; 1457 } 1458 1459 static struct i915_power_well skl_power_wells[] = { 1460 { 1461 .name = "always-on", 1462 .always_on = 1, 1463 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1464 .ops = &i9xx_always_on_power_well_ops, 1465 }, 1466 { 1467 .name = "power well 1", 1468 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1469 .ops = &skl_power_well_ops, 1470 .data = SKL_DISP_PW_1, 1471 }, 1472 { 1473 .name = "MISC IO power well", 1474 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, 1475 .ops = &skl_power_well_ops, 1476 .data = SKL_DISP_PW_MISC_IO, 1477 }, 1478 { 1479 .name = "power well 2", 1480 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1481 .ops = &skl_power_well_ops, 1482 .data = SKL_DISP_PW_2, 1483 }, 1484 { 1485 .name = "DDI A/E power well", 1486 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1487 .ops = &skl_power_well_ops, 1488 .data = SKL_DISP_PW_DDI_A_E, 1489 }, 1490 { 1491 .name = "DDI B power well", 1492 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1493 .ops = &skl_power_well_ops, 1494 .data = SKL_DISP_PW_DDI_B, 1495 }, 1496 { 1497 .name = "DDI C power well", 1498 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1499 .ops = &skl_power_well_ops, 1500 .data = SKL_DISP_PW_DDI_C, 1501 }, 1502 { 1503 .name = "DDI D power well", 1504 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1505 .ops = &skl_power_well_ops, 1506 .data = SKL_DISP_PW_DDI_D, 1507 }, 1508 }; 1509 1510 static struct i915_power_well bxt_power_wells[] = { 1511 { 1512 .name = "always-on", 1513 .always_on = 1, 1514 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1515 .ops = &i9xx_always_on_power_well_ops, 1516 }, 1517 { 1518 .name = "power well 1", 1519 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1520 .ops = &skl_power_well_ops, 1521 .data = SKL_DISP_PW_1, 1522 }, 1523 { 1524 .name = "power well 2", 1525 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1526 .ops = &skl_power_well_ops, 1527 .data = SKL_DISP_PW_2, 1528 } 1529 }; 1530 1531 #define set_power_wells(power_domains, __power_wells) ({ \ 1532 (power_domains)->power_wells = (__power_wells); \ 1533 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 1534 }) 1535 1536 /** 1537 * intel_power_domains_init - initializes the power domain structures 1538 * @dev_priv: i915 device instance 1539 * 1540 * Initializes the power domain structures for @dev_priv depending upon the 1541 * supported platform. 1542 */ 1543 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1544 { 1545 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1546 1547 mutex_init(&power_domains->lock); 1548 1549 /* 1550 * The enabling order will be from lower to higher indexed wells, 1551 * the disabling order is reversed. 1552 */ 1553 if (IS_HASWELL(dev_priv->dev)) { 1554 set_power_wells(power_domains, hsw_power_wells); 1555 } else if (IS_BROADWELL(dev_priv->dev)) { 1556 set_power_wells(power_domains, bdw_power_wells); 1557 } else if (IS_SKYLAKE(dev_priv->dev)) { 1558 set_power_wells(power_domains, skl_power_wells); 1559 } else if (IS_BROXTON(dev_priv->dev)) { 1560 set_power_wells(power_domains, bxt_power_wells); 1561 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1562 set_power_wells(power_domains, chv_power_wells); 1563 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 1564 set_power_wells(power_domains, vlv_power_wells); 1565 } else { 1566 set_power_wells(power_domains, i9xx_always_on_power_well); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) 1573 { 1574 struct drm_device *dev = dev_priv->dev; 1575 struct device *device = &dev->pdev->dev; 1576 1577 if (!HAS_RUNTIME_PM(dev)) 1578 return; 1579 1580 if (!intel_enable_rc6(dev)) 1581 return; 1582 1583 /* Make sure we're not suspended first. */ 1584 pm_runtime_get_sync(device); 1585 pm_runtime_disable(device); 1586 } 1587 1588 /** 1589 * intel_power_domains_fini - finalizes the power domain structures 1590 * @dev_priv: i915 device instance 1591 * 1592 * Finalizes the power domain structures for @dev_priv depending upon the 1593 * supported platform. This function also disables runtime pm and ensures that 1594 * the device stays powered up so that the driver can be reloaded. 1595 */ 1596 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 1597 { 1598 intel_runtime_pm_disable(dev_priv); 1599 1600 /* The i915.ko module is still not prepared to be loaded when 1601 * the power well is not enabled, so just enable it in case 1602 * we're going to unload/reload. */ 1603 intel_display_set_init_power(dev_priv, true); 1604 } 1605 1606 static void intel_power_domains_resume(struct drm_i915_private *dev_priv) 1607 { 1608 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1609 struct i915_power_well *power_well; 1610 int i; 1611 1612 mutex_lock(&power_domains->lock); 1613 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1614 power_well->ops->sync_hw(dev_priv, power_well); 1615 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 1616 power_well); 1617 } 1618 mutex_unlock(&power_domains->lock); 1619 } 1620 1621 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1622 { 1623 struct i915_power_well *cmn_bc = 1624 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1625 struct i915_power_well *cmn_d = 1626 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1627 1628 /* 1629 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 1630 * workaround never ever read DISPLAY_PHY_CONTROL, and 1631 * instead maintain a shadow copy ourselves. Use the actual 1632 * power well state to reconstruct the expected initial 1633 * value. 1634 */ 1635 dev_priv->chv_phy_control = 1636 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1637 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1638 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | 1639 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | 1640 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); 1641 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) 1642 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1643 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) 1644 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1645 } 1646 1647 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1648 { 1649 struct i915_power_well *cmn = 1650 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1651 struct i915_power_well *disp2d = 1652 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 1653 1654 /* If the display might be already active skip this */ 1655 if (cmn->ops->is_enabled(dev_priv, cmn) && 1656 disp2d->ops->is_enabled(dev_priv, disp2d) && 1657 I915_READ(DPIO_CTL) & DPIO_CMNRST) 1658 return; 1659 1660 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 1661 1662 /* cmnlane needs DPLL registers */ 1663 disp2d->ops->enable(dev_priv, disp2d); 1664 1665 /* 1666 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1667 * Need to assert and de-assert PHY SB reset by gating the 1668 * common lane power, then un-gating it. 1669 * Simply ungating isn't enough to reset the PHY enough to get 1670 * ports and lanes running. 1671 */ 1672 cmn->ops->disable(dev_priv, cmn); 1673 } 1674 1675 /** 1676 * intel_power_domains_init_hw - initialize hardware power domain state 1677 * @dev_priv: i915 device instance 1678 * 1679 * This function initializes the hardware power domain state and enables all 1680 * power domains using intel_display_set_init_power(). 1681 */ 1682 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) 1683 { 1684 struct drm_device *dev = dev_priv->dev; 1685 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1686 1687 power_domains->initializing = true; 1688 1689 if (IS_CHERRYVIEW(dev)) { 1690 chv_phy_control_init(dev_priv); 1691 } else if (IS_VALLEYVIEW(dev)) { 1692 mutex_lock(&power_domains->lock); 1693 vlv_cmnlane_wa(dev_priv); 1694 mutex_unlock(&power_domains->lock); 1695 } 1696 1697 /* For now, we need the power well to be always enabled. */ 1698 intel_display_set_init_power(dev_priv, true); 1699 intel_power_domains_resume(dev_priv); 1700 power_domains->initializing = false; 1701 } 1702 1703 /** 1704 * intel_aux_display_runtime_get - grab an auxiliary power domain reference 1705 * @dev_priv: i915 device instance 1706 * 1707 * This function grabs a power domain reference for the auxiliary power domain 1708 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its 1709 * parents are powered up. Therefore users should only grab a reference to the 1710 * innermost power domain they need. 1711 * 1712 * Any power domain reference obtained by this function must have a symmetric 1713 * call to intel_aux_display_runtime_put() to release the reference again. 1714 */ 1715 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 1716 { 1717 intel_runtime_pm_get(dev_priv); 1718 } 1719 1720 /** 1721 * intel_aux_display_runtime_put - release an auxiliary power domain reference 1722 * @dev_priv: i915 device instance 1723 * 1724 * This function drops the auxiliary power domain reference obtained by 1725 * intel_aux_display_runtime_get() and might power down the corresponding 1726 * hardware block right away if this is the last reference. 1727 */ 1728 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 1729 { 1730 intel_runtime_pm_put(dev_priv); 1731 } 1732 1733 /** 1734 * intel_runtime_pm_get - grab a runtime pm reference 1735 * @dev_priv: i915 device instance 1736 * 1737 * This function grabs a device-level runtime pm reference (mostly used for GEM 1738 * code to ensure the GTT or GT is on) and ensures that it is powered up. 1739 * 1740 * Any runtime pm reference obtained by this function must have a symmetric 1741 * call to intel_runtime_pm_put() to release the reference again. 1742 */ 1743 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 1744 { 1745 struct drm_device *dev = dev_priv->dev; 1746 struct device *device = &dev->pdev->dev; 1747 1748 if (!HAS_RUNTIME_PM(dev)) 1749 return; 1750 1751 pm_runtime_get_sync(device); 1752 WARN(dev_priv->pm.suspended, "Device still suspended.\n"); 1753 } 1754 1755 /** 1756 * intel_runtime_pm_get_noresume - grab a runtime pm reference 1757 * @dev_priv: i915 device instance 1758 * 1759 * This function grabs a device-level runtime pm reference (mostly used for GEM 1760 * code to ensure the GTT or GT is on). 1761 * 1762 * It will _not_ power up the device but instead only check that it's powered 1763 * on. Therefore it is only valid to call this functions from contexts where 1764 * the device is known to be powered up and where trying to power it up would 1765 * result in hilarity and deadlocks. That pretty much means only the system 1766 * suspend/resume code where this is used to grab runtime pm references for 1767 * delayed setup down in work items. 1768 * 1769 * Any runtime pm reference obtained by this function must have a symmetric 1770 * call to intel_runtime_pm_put() to release the reference again. 1771 */ 1772 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 1773 { 1774 struct drm_device *dev = dev_priv->dev; 1775 struct device *device = &dev->pdev->dev; 1776 1777 if (!HAS_RUNTIME_PM(dev)) 1778 return; 1779 1780 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); 1781 pm_runtime_get_noresume(device); 1782 } 1783 1784 /** 1785 * intel_runtime_pm_put - release a runtime pm reference 1786 * @dev_priv: i915 device instance 1787 * 1788 * This function drops the device-level runtime pm reference obtained by 1789 * intel_runtime_pm_get() and might power down the corresponding 1790 * hardware block right away if this is the last reference. 1791 */ 1792 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 1793 { 1794 struct drm_device *dev = dev_priv->dev; 1795 struct device *device = &dev->pdev->dev; 1796 1797 if (!HAS_RUNTIME_PM(dev)) 1798 return; 1799 1800 pm_runtime_mark_last_busy(device); 1801 pm_runtime_put_autosuspend(device); 1802 } 1803 1804 /** 1805 * intel_runtime_pm_enable - enable runtime pm 1806 * @dev_priv: i915 device instance 1807 * 1808 * This function enables runtime pm at the end of the driver load sequence. 1809 * 1810 * Note that this function does currently not enable runtime pm for the 1811 * subordinate display power domains. That is only done on the first modeset 1812 * using intel_display_set_init_power(). 1813 */ 1814 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 1815 { 1816 struct drm_device *dev = dev_priv->dev; 1817 struct device *device = &dev->pdev->dev; 1818 1819 if (!HAS_RUNTIME_PM(dev)) 1820 return; 1821 1822 pm_runtime_set_active(device); 1823 1824 /* 1825 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 1826 * requirement. 1827 */ 1828 if (!intel_enable_rc6(dev)) { 1829 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 1830 return; 1831 } 1832 1833 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 1834 pm_runtime_mark_last_busy(device); 1835 pm_runtime_use_autosuspend(device); 1836 1837 pm_runtime_put_autosuspend(device); 1838 } 1839 1840