1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_PCI_CONFIG_H__
7 #define __INTEL_PCI_CONFIG_H__
8 
9 /* PCI BARs */
10 #define GTTMMADR_BAR				0
11 #define GEN2_GTTMMADR_BAR			1
12 #define GFXMEM_BAR				2
13 #define GTT_APERTURE_BAR			GFXMEM_BAR
14 #define GEN12_LMEM_BAR				GFXMEM_BAR
15 
16 /* BSM in include/drm/i915_drm.h */
17 
18 #define MCHBAR_I915				0x44
19 #define MCHBAR_I965				0x48
20 #define   MCHBAR_SIZE				(4 * 4096)
21 
22 #define DEVEN					0x54
23 #define   DEVEN_MCHBAR_EN			(1 << 28)
24 
25 #define HPLLCC					0xc0 /* 85x only */
26 #define   GC_CLOCK_CONTROL_MASK			(0x7 << 0)
27 #define   GC_CLOCK_133_200			(0 << 0)
28 #define   GC_CLOCK_100_200			(1 << 0)
29 #define   GC_CLOCK_100_133			(2 << 0)
30 #define   GC_CLOCK_133_266			(3 << 0)
31 #define   GC_CLOCK_133_200_2			(4 << 0)
32 #define   GC_CLOCK_133_266_2			(5 << 0)
33 #define   GC_CLOCK_166_266			(6 << 0)
34 #define   GC_CLOCK_166_250			(7 << 0)
35 
36 #define I915_GDRST				0xc0
37 #define   GRDOM_FULL				(0 << 2)
38 #define   GRDOM_RENDER				(1 << 2)
39 #define   GRDOM_MEDIA				(3 << 2)
40 #define   GRDOM_MASK				(3 << 2)
41 #define   GRDOM_RESET_STATUS			(1 << 1)
42 #define   GRDOM_RESET_ENABLE			(1 << 0)
43 
44 /* BSpec only has register offset, PCI device and bit found empirically */
45 #define I830_CLOCK_GATE				0xc8 /* device 0 */
46 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
47 
48 #define GCDGMBUS				0xcc
49 
50 #define GCFGC2					0xda
51 #define GCFGC					0xf0 /* 915+ only */
52 #define   GC_LOW_FREQUENCY_ENABLE		(1 << 7)
53 #define   GC_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
54 #define   GC_DISPLAY_CLOCK_333_320_MHZ		(4 << 4)
55 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV		(0 << 4)
56 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV		(1 << 4)
57 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV		(2 << 4)
58 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV		(5 << 4)
59 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV		(6 << 4)
60 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV		(7 << 4)
61 #define   GC_DISPLAY_CLOCK_MASK			(7 << 4)
62 #define   GM45_GC_RENDER_CLOCK_MASK		(0xf << 0)
63 #define   GM45_GC_RENDER_CLOCK_266_MHZ		(8 << 0)
64 #define   GM45_GC_RENDER_CLOCK_320_MHZ		(9 << 0)
65 #define   GM45_GC_RENDER_CLOCK_400_MHZ		(0xb << 0)
66 #define   GM45_GC_RENDER_CLOCK_533_MHZ		(0xc << 0)
67 #define   I965_GC_RENDER_CLOCK_MASK		(0xf << 0)
68 #define   I965_GC_RENDER_CLOCK_267_MHZ		(2 << 0)
69 #define   I965_GC_RENDER_CLOCK_333_MHZ		(3 << 0)
70 #define   I965_GC_RENDER_CLOCK_444_MHZ		(4 << 0)
71 #define   I965_GC_RENDER_CLOCK_533_MHZ		(5 << 0)
72 #define   I945_GC_RENDER_CLOCK_MASK		(7 << 0)
73 #define   I945_GC_RENDER_CLOCK_166_MHZ		(0 << 0)
74 #define   I945_GC_RENDER_CLOCK_200_MHZ		(1 << 0)
75 #define   I945_GC_RENDER_CLOCK_250_MHZ		(3 << 0)
76 #define   I945_GC_RENDER_CLOCK_400_MHZ		(5 << 0)
77 #define   I915_GC_RENDER_CLOCK_MASK		(7 << 0)
78 #define   I915_GC_RENDER_CLOCK_166_MHZ		(0 << 0)
79 #define   I915_GC_RENDER_CLOCK_200_MHZ		(1 << 0)
80 #define   I915_GC_RENDER_CLOCK_333_MHZ		(4 << 0)
81 
82 #define ASLE					0xe4
83 #define ASLS					0xfc
84 
85 #define SWSCI					0xe8
86 #define   SWSCI_SCISEL				(1 << 15)
87 #define   SWSCI_GSSCIE				(1 << 0)
88 
89 /* legacy/combination backlight modes, also called LBB */
90 #define LBPC					0xf4
91 
92 #endif /* __INTEL_PCI_CONFIG_H__ */
93