1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_step.h" 31 32 #include "display/intel_display_limits.h" 33 34 #include "gt/intel_engine_types.h" 35 #include "gt/intel_context_types.h" 36 #include "gt/intel_sseu.h" 37 38 struct drm_printer; 39 struct drm_i915_private; 40 struct intel_gt_definition; 41 42 /* Keep in gen based order, and chronological order within a gen */ 43 enum intel_platform { 44 INTEL_PLATFORM_UNINITIALIZED = 0, 45 /* gen2 */ 46 INTEL_I830, 47 INTEL_I845G, 48 INTEL_I85X, 49 INTEL_I865G, 50 /* gen3 */ 51 INTEL_I915G, 52 INTEL_I915GM, 53 INTEL_I945G, 54 INTEL_I945GM, 55 INTEL_G33, 56 INTEL_PINEVIEW, 57 /* gen4 */ 58 INTEL_I965G, 59 INTEL_I965GM, 60 INTEL_G45, 61 INTEL_GM45, 62 /* gen5 */ 63 INTEL_IRONLAKE, 64 /* gen6 */ 65 INTEL_SANDYBRIDGE, 66 /* gen7 */ 67 INTEL_IVYBRIDGE, 68 INTEL_VALLEYVIEW, 69 INTEL_HASWELL, 70 /* gen8 */ 71 INTEL_BROADWELL, 72 INTEL_CHERRYVIEW, 73 /* gen9 */ 74 INTEL_SKYLAKE, 75 INTEL_BROXTON, 76 INTEL_KABYLAKE, 77 INTEL_GEMINILAKE, 78 INTEL_COFFEELAKE, 79 INTEL_COMETLAKE, 80 /* gen11 */ 81 INTEL_ICELAKE, 82 INTEL_ELKHARTLAKE, 83 INTEL_JASPERLAKE, 84 /* gen12 */ 85 INTEL_TIGERLAKE, 86 INTEL_ROCKETLAKE, 87 INTEL_DG1, 88 INTEL_ALDERLAKE_S, 89 INTEL_ALDERLAKE_P, 90 INTEL_XEHPSDV, 91 INTEL_DG2, 92 INTEL_PONTEVECCHIO, 93 INTEL_METEORLAKE, 94 INTEL_MAX_PLATFORMS 95 }; 96 97 /* 98 * Subplatform bits share the same namespace per parent platform. In other words 99 * it is fine for the same bit to be used on multiple parent platforms. 100 */ 101 102 #define INTEL_SUBPLATFORM_BITS (3) 103 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) 104 105 /* HSW/BDW/SKL/KBL/CFL */ 106 #define INTEL_SUBPLATFORM_ULT (0) 107 #define INTEL_SUBPLATFORM_ULX (1) 108 109 /* ICL */ 110 #define INTEL_SUBPLATFORM_PORTF (0) 111 112 /* TGL */ 113 #define INTEL_SUBPLATFORM_UY (0) 114 115 /* DG2 */ 116 #define INTEL_SUBPLATFORM_G10 0 117 #define INTEL_SUBPLATFORM_G11 1 118 #define INTEL_SUBPLATFORM_G12 2 119 120 /* ADL */ 121 #define INTEL_SUBPLATFORM_RPL 0 122 123 /* ADL-P */ 124 /* 125 * As #define INTEL_SUBPLATFORM_RPL 0 will apply 126 * here too, SUBPLATFORM_N will have different 127 * bit set 128 */ 129 #define INTEL_SUBPLATFORM_N 1 130 #define INTEL_SUBPLATFORM_RPLU 2 131 132 /* MTL */ 133 #define INTEL_SUBPLATFORM_M 0 134 #define INTEL_SUBPLATFORM_P 1 135 136 enum intel_ppgtt_type { 137 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 138 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 139 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 140 }; 141 142 #define DEV_INFO_FOR_EACH_FLAG(func) \ 143 func(is_mobile); \ 144 func(is_lp); \ 145 func(require_force_probe); \ 146 func(is_dgfx); \ 147 /* Keep has_* in alphabetical order */ \ 148 func(has_64bit_reloc); \ 149 func(has_64k_pages); \ 150 func(gpu_reset_clobbers_display); \ 151 func(has_reset_engine); \ 152 func(has_3d_pipeline); \ 153 func(has_4tile); \ 154 func(has_flat_ccs); \ 155 func(has_global_mocs); \ 156 func(has_gmd_id); \ 157 func(has_gt_uc); \ 158 func(has_heci_pxp); \ 159 func(has_heci_gscfi); \ 160 func(has_guc_deprivilege); \ 161 func(has_l3_ccs_read); \ 162 func(has_l3_dpf); \ 163 func(has_llc); \ 164 func(has_logical_ring_contexts); \ 165 func(has_logical_ring_elsq); \ 166 func(has_media_ratio_mode); \ 167 func(has_mslice_steering); \ 168 func(has_oa_bpc_reporting); \ 169 func(has_oa_slice_contrib_limits); \ 170 func(has_one_eu_per_fuse_bit); \ 171 func(has_pxp); \ 172 func(has_rc6); \ 173 func(has_rc6p); \ 174 func(has_rps); \ 175 func(has_runtime_pm); \ 176 func(has_snoop); \ 177 func(has_coherent_ggtt); \ 178 func(tuning_thread_rr_after_dep); \ 179 func(unfenced_needs_alignment); \ 180 func(hws_needs_physical); 181 182 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 183 /* Keep in alphabetical order */ \ 184 func(cursor_needs_physical); \ 185 func(has_cdclk_crawl); \ 186 func(has_cdclk_squash); \ 187 func(has_ddi); \ 188 func(has_dp_mst); \ 189 func(has_dsb); \ 190 func(has_fpga_dbg); \ 191 func(has_gmch); \ 192 func(has_hotplug); \ 193 func(has_hti); \ 194 func(has_ipc); \ 195 func(has_modular_fia); \ 196 func(has_overlay); \ 197 func(has_psr); \ 198 func(has_psr_hw_tracking); \ 199 func(overlay_needs_physical); \ 200 func(supports_tv); 201 202 struct intel_ip_version { 203 u8 ver; 204 u8 rel; 205 u8 step; 206 }; 207 208 struct intel_runtime_info { 209 /* 210 * Single "graphics" IP version that represents 211 * render, compute and copy behavior. 212 */ 213 struct { 214 struct intel_ip_version ip; 215 } graphics; 216 struct { 217 struct intel_ip_version ip; 218 } media; 219 struct { 220 struct intel_ip_version ip; 221 } display; 222 223 /* 224 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 225 * single runtime conditionals, and also to provide groundwork for 226 * future per platform, or per SKU build optimizations. 227 * 228 * Array can be extended when necessary if the corresponding 229 * BUILD_BUG_ON is hit. 230 */ 231 u32 platform_mask[2]; 232 233 u16 device_id; 234 235 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ 236 237 u32 rawclk_freq; 238 239 struct intel_step_info step; 240 241 unsigned int page_sizes; /* page sizes supported by the HW */ 242 243 enum intel_ppgtt_type ppgtt_type; 244 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 245 246 u32 memory_regions; /* regions supported by the HW */ 247 248 bool has_pooled_eu; 249 250 /* display */ 251 struct { 252 u8 pipe_mask; 253 u8 cpu_transcoder_mask; 254 255 u8 num_sprites[I915_MAX_PIPES]; 256 u8 num_scalers[I915_MAX_PIPES]; 257 258 u8 fbc_mask; 259 260 bool has_hdcp; 261 bool has_dmc; 262 bool has_dsc; 263 }; 264 }; 265 266 struct intel_device_info { 267 enum intel_platform platform; 268 269 unsigned int dma_mask_size; /* available DMA address bits */ 270 271 const struct intel_gt_definition *extra_gt_list; 272 273 u8 gt; /* GT number, 0 if undefined */ 274 275 #define DEFINE_FLAG(name) u8 name:1 276 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 277 #undef DEFINE_FLAG 278 279 struct { 280 u8 abox_mask; 281 282 struct { 283 u16 size; /* in blocks */ 284 u8 slice_mask; 285 } dbuf; 286 287 #define DEFINE_FLAG(name) u8 name:1 288 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 289 #undef DEFINE_FLAG 290 291 /* Global register offset for the display engine */ 292 u32 mmio_offset; 293 294 /* Register offsets for the various display pipes and transcoders */ 295 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 296 u32 trans_offsets[I915_MAX_TRANSCODERS]; 297 u32 cursor_offsets[I915_MAX_PIPES]; 298 299 struct { 300 u32 degamma_lut_size; 301 u32 gamma_lut_size; 302 u32 degamma_lut_tests; 303 u32 gamma_lut_tests; 304 } color; 305 } display; 306 307 /* 308 * Initial runtime info. Do not access outside of i915_driver_create(). 309 */ 310 const struct intel_runtime_info __runtime; 311 }; 312 313 struct intel_driver_caps { 314 unsigned int scheduler; 315 bool has_logical_contexts:1; 316 }; 317 318 const char *intel_platform_name(enum intel_platform platform); 319 320 void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv); 321 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 322 323 void intel_device_info_print(const struct intel_device_info *info, 324 const struct intel_runtime_info *runtime, 325 struct drm_printer *p); 326 327 void intel_driver_caps_print(const struct intel_driver_caps *caps, 328 struct drm_printer *p); 329 330 #endif 331