1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_display.h" 31 32 struct drm_printer; 33 struct drm_i915_private; 34 35 /* Keep in gen based order, and chronological order within a gen */ 36 enum intel_platform { 37 INTEL_PLATFORM_UNINITIALIZED = 0, 38 /* gen2 */ 39 INTEL_I830, 40 INTEL_I845G, 41 INTEL_I85X, 42 INTEL_I865G, 43 /* gen3 */ 44 INTEL_I915G, 45 INTEL_I915GM, 46 INTEL_I945G, 47 INTEL_I945GM, 48 INTEL_G33, 49 INTEL_PINEVIEW, 50 /* gen4 */ 51 INTEL_I965G, 52 INTEL_I965GM, 53 INTEL_G45, 54 INTEL_GM45, 55 /* gen5 */ 56 INTEL_IRONLAKE, 57 /* gen6 */ 58 INTEL_SANDYBRIDGE, 59 /* gen7 */ 60 INTEL_IVYBRIDGE, 61 INTEL_VALLEYVIEW, 62 INTEL_HASWELL, 63 /* gen8 */ 64 INTEL_BROADWELL, 65 INTEL_CHERRYVIEW, 66 /* gen9 */ 67 INTEL_SKYLAKE, 68 INTEL_BROXTON, 69 INTEL_KABYLAKE, 70 INTEL_GEMINILAKE, 71 INTEL_COFFEELAKE, 72 /* gen10 */ 73 INTEL_CANNONLAKE, 74 /* gen11 */ 75 INTEL_ICELAKE, 76 INTEL_MAX_PLATFORMS 77 }; 78 79 enum intel_ppgtt { 80 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 81 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 82 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 83 INTEL_PPGTT_FULL_4LVL, 84 }; 85 86 #define DEV_INFO_FOR_EACH_FLAG(func) \ 87 func(is_mobile); \ 88 func(is_lp); \ 89 func(is_alpha_support); \ 90 /* Keep has_* in alphabetical order */ \ 91 func(has_64bit_reloc); \ 92 func(has_csr); \ 93 func(has_ddi); \ 94 func(has_dp_mst); \ 95 func(has_reset_engine); \ 96 func(has_fbc); \ 97 func(has_fpga_dbg); \ 98 func(has_gmch_display); \ 99 func(has_guc); \ 100 func(has_guc_ct); \ 101 func(has_hotplug); \ 102 func(has_l3_dpf); \ 103 func(has_llc); \ 104 func(has_logical_ring_contexts); \ 105 func(has_logical_ring_elsq); \ 106 func(has_logical_ring_preemption); \ 107 func(has_overlay); \ 108 func(has_pooled_eu); \ 109 func(has_psr); \ 110 func(has_rc6); \ 111 func(has_rc6p); \ 112 func(has_runtime_pm); \ 113 func(has_snoop); \ 114 func(has_coherent_ggtt); \ 115 func(unfenced_needs_alignment); \ 116 func(cursor_needs_physical); \ 117 func(hws_needs_physical); \ 118 func(overlay_needs_physical); \ 119 func(supports_tv); \ 120 func(has_ipc); 121 122 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 123 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 124 125 struct sseu_dev_info { 126 u8 slice_mask; 127 u8 subslice_mask[GEN_MAX_SUBSLICES]; 128 u16 eu_total; 129 u8 eu_per_subslice; 130 u8 min_eu_in_pool; 131 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 132 u8 subslice_7eu[3]; 133 u8 has_slice_pg:1; 134 u8 has_subslice_pg:1; 135 u8 has_eu_pg:1; 136 137 /* Topology fields */ 138 u8 max_slices; 139 u8 max_subslices; 140 u8 max_eus_per_subslice; 141 142 /* We don't have more than 8 eus per subslice at the moment and as we 143 * store eus enabled using bits, no need to multiply by eus per 144 * subslice. 145 */ 146 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES]; 147 }; 148 149 typedef u8 intel_ring_mask_t; 150 151 struct intel_device_info { 152 u16 device_id; 153 u16 gen_mask; 154 155 u8 gen; 156 u8 gt; /* GT number, 0 if undefined */ 157 u8 num_rings; 158 intel_ring_mask_t ring_mask; /* Rings supported by the HW */ 159 160 enum intel_platform platform; 161 u32 platform_mask; 162 163 enum intel_ppgtt ppgtt; 164 unsigned int page_sizes; /* page sizes supported by the HW */ 165 166 u32 display_mmio_offset; 167 168 u8 num_pipes; 169 u8 num_sprites[I915_MAX_PIPES]; 170 u8 num_scalers[I915_MAX_PIPES]; 171 172 #define DEFINE_FLAG(name) u8 name:1 173 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 174 #undef DEFINE_FLAG 175 u16 ddb_size; /* in blocks */ 176 177 /* Register offsets for the various display pipes and transcoders */ 178 int pipe_offsets[I915_MAX_TRANSCODERS]; 179 int trans_offsets[I915_MAX_TRANSCODERS]; 180 int cursor_offsets[I915_MAX_PIPES]; 181 182 /* Slice/subslice/EU info */ 183 struct sseu_dev_info sseu; 184 185 u32 cs_timestamp_frequency_khz; 186 187 /* Enabled (not fused off) media engine bitmasks. */ 188 u8 vdbox_enable; 189 u8 vebox_enable; 190 191 struct color_luts { 192 u16 degamma_lut_size; 193 u16 gamma_lut_size; 194 } color; 195 }; 196 197 struct intel_driver_caps { 198 unsigned int scheduler; 199 bool has_logical_contexts:1; 200 }; 201 202 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) 203 { 204 unsigned int i, total = 0; 205 206 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) 207 total += hweight8(sseu->subslice_mask[i]); 208 209 return total; 210 } 211 212 static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, 213 int slice, int subslice) 214 { 215 int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, 216 BITS_PER_BYTE); 217 int slice_stride = sseu->max_subslices * subslice_stride; 218 219 return slice * slice_stride + subslice * subslice_stride; 220 } 221 222 static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, 223 int slice, int subslice) 224 { 225 int i, offset = sseu_eu_idx(sseu, slice, subslice); 226 u16 eu_mask = 0; 227 228 for (i = 0; 229 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { 230 eu_mask |= ((u16) sseu->eu_mask[offset + i]) << 231 (i * BITS_PER_BYTE); 232 } 233 234 return eu_mask; 235 } 236 237 static inline void sseu_set_eus(struct sseu_dev_info *sseu, 238 int slice, int subslice, u16 eu_mask) 239 { 240 int i, offset = sseu_eu_idx(sseu, slice, subslice); 241 242 for (i = 0; 243 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { 244 sseu->eu_mask[offset + i] = 245 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 246 } 247 } 248 249 const char *intel_platform_name(enum intel_platform platform); 250 251 void intel_device_info_runtime_init(struct intel_device_info *info); 252 void intel_device_info_dump(const struct intel_device_info *info, 253 struct drm_printer *p); 254 void intel_device_info_dump_flags(const struct intel_device_info *info, 255 struct drm_printer *p); 256 void intel_device_info_dump_runtime(const struct intel_device_info *info, 257 struct drm_printer *p); 258 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, 259 struct drm_printer *p); 260 261 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); 262 263 void intel_driver_caps_print(const struct intel_driver_caps *caps, 264 struct drm_printer *p); 265 266 #endif 267