1 /*
2  * Copyright © 2014-2017 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
27 
28 #include <uapi/drm/i915_drm.h>
29 
30 #include "intel_step.h"
31 
32 #include "display/intel_display.h"
33 
34 #include "gt/intel_engine_types.h"
35 #include "gt/intel_context_types.h"
36 #include "gt/intel_sseu.h"
37 
38 struct drm_printer;
39 struct drm_i915_private;
40 
41 /* Keep in gen based order, and chronological order within a gen */
42 enum intel_platform {
43 	INTEL_PLATFORM_UNINITIALIZED = 0,
44 	/* gen2 */
45 	INTEL_I830,
46 	INTEL_I845G,
47 	INTEL_I85X,
48 	INTEL_I865G,
49 	/* gen3 */
50 	INTEL_I915G,
51 	INTEL_I915GM,
52 	INTEL_I945G,
53 	INTEL_I945GM,
54 	INTEL_G33,
55 	INTEL_PINEVIEW,
56 	/* gen4 */
57 	INTEL_I965G,
58 	INTEL_I965GM,
59 	INTEL_G45,
60 	INTEL_GM45,
61 	/* gen5 */
62 	INTEL_IRONLAKE,
63 	/* gen6 */
64 	INTEL_SANDYBRIDGE,
65 	/* gen7 */
66 	INTEL_IVYBRIDGE,
67 	INTEL_VALLEYVIEW,
68 	INTEL_HASWELL,
69 	/* gen8 */
70 	INTEL_BROADWELL,
71 	INTEL_CHERRYVIEW,
72 	/* gen9 */
73 	INTEL_SKYLAKE,
74 	INTEL_BROXTON,
75 	INTEL_KABYLAKE,
76 	INTEL_GEMINILAKE,
77 	INTEL_COFFEELAKE,
78 	INTEL_COMETLAKE,
79 	/* gen11 */
80 	INTEL_ICELAKE,
81 	INTEL_ELKHARTLAKE,
82 	INTEL_JASPERLAKE,
83 	/* gen12 */
84 	INTEL_TIGERLAKE,
85 	INTEL_ROCKETLAKE,
86 	INTEL_DG1,
87 	INTEL_ALDERLAKE_S,
88 	INTEL_ALDERLAKE_P,
89 	INTEL_XEHPSDV,
90 	INTEL_DG2,
91 	INTEL_MAX_PLATFORMS
92 };
93 
94 /*
95  * Subplatform bits share the same namespace per parent platform. In other words
96  * it is fine for the same bit to be used on multiple parent platforms.
97  */
98 
99 #define INTEL_SUBPLATFORM_BITS (2)
100 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
101 
102 /* HSW/BDW/SKL/KBL/CFL */
103 #define INTEL_SUBPLATFORM_ULT	(0)
104 #define INTEL_SUBPLATFORM_ULX	(1)
105 
106 /* ICL */
107 #define INTEL_SUBPLATFORM_PORTF	(0)
108 
109 /* DG2 */
110 #define INTEL_SUBPLATFORM_G10	0
111 #define INTEL_SUBPLATFORM_G11	1
112 
113 /* ADL-S */
114 #define INTEL_SUBPLATFORM_RPL_S	0
115 
116 enum intel_ppgtt_type {
117 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
118 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
119 	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
120 };
121 
122 #define DEV_INFO_FOR_EACH_FLAG(func) \
123 	func(is_mobile); \
124 	func(is_lp); \
125 	func(require_force_probe); \
126 	func(is_dgfx); \
127 	/* Keep has_* in alphabetical order */ \
128 	func(has_64bit_reloc); \
129 	func(has_64k_pages); \
130 	func(gpu_reset_clobbers_display); \
131 	func(has_reset_engine); \
132 	func(has_global_mocs); \
133 	func(has_gt_uc); \
134 	func(has_l3_dpf); \
135 	func(has_llc); \
136 	func(has_logical_ring_contexts); \
137 	func(has_logical_ring_elsq); \
138 	func(has_mslices); \
139 	func(has_pooled_eu); \
140 	func(has_pxp); \
141 	func(has_rc6); \
142 	func(has_rc6p); \
143 	func(has_rps); \
144 	func(has_runtime_pm); \
145 	func(has_snoop); \
146 	func(has_coherent_ggtt); \
147 	func(unfenced_needs_alignment); \
148 	func(hws_needs_physical);
149 
150 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
151 	/* Keep in alphabetical order */ \
152 	func(cursor_needs_physical); \
153 	func(has_cdclk_crawl); \
154 	func(has_dmc); \
155 	func(has_ddi); \
156 	func(has_dp_mst); \
157 	func(has_dsb); \
158 	func(has_dsc); \
159 	func(has_fbc); \
160 	func(has_fpga_dbg); \
161 	func(has_gmch); \
162 	func(has_hdcp); \
163 	func(has_hotplug); \
164 	func(has_hti); \
165 	func(has_ipc); \
166 	func(has_modular_fia); \
167 	func(has_overlay); \
168 	func(has_psr); \
169 	func(has_psr_hw_tracking); \
170 	func(overlay_needs_physical); \
171 	func(supports_tv);
172 
173 struct ip_version {
174 	u8 ver;
175 	u8 rel;
176 };
177 
178 struct intel_device_info {
179 	struct ip_version graphics;
180 	struct ip_version media;
181 
182 	intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
183 
184 	enum intel_platform platform;
185 
186 	unsigned int dma_mask_size; /* available DMA address bits */
187 
188 	enum intel_ppgtt_type ppgtt_type;
189 	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
190 
191 	unsigned int page_sizes; /* page sizes supported by the HW */
192 
193 	u32 memory_regions; /* regions supported by the HW */
194 
195 	u32 display_mmio_offset;
196 
197 	u8 gt; /* GT number, 0 if undefined */
198 
199 #define DEFINE_FLAG(name) u8 name:1
200 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
201 #undef DEFINE_FLAG
202 
203 	struct {
204 		u8 ver;
205 		u8 rel;
206 
207 		u8 pipe_mask;
208 		u8 cpu_transcoder_mask;
209 		u8 abox_mask;
210 
211 #define DEFINE_FLAG(name) u8 name:1
212 		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
213 #undef DEFINE_FLAG
214 	} display;
215 
216 	struct {
217 		u16 size; /* in blocks */
218 		u8 slice_mask;
219 	} dbuf;
220 
221 	/* Register offsets for the various display pipes and transcoders */
222 	int pipe_offsets[I915_MAX_TRANSCODERS];
223 	int trans_offsets[I915_MAX_TRANSCODERS];
224 	int cursor_offsets[I915_MAX_PIPES];
225 
226 	struct color_luts {
227 		u32 degamma_lut_size;
228 		u32 gamma_lut_size;
229 		u32 degamma_lut_tests;
230 		u32 gamma_lut_tests;
231 	} color;
232 };
233 
234 struct intel_runtime_info {
235 	/*
236 	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
237 	 * into single runtime conditionals, and also to provide groundwork
238 	 * for future per platform, or per SKU build optimizations.
239 	 *
240 	 * Array can be extended when necessary if the corresponding
241 	 * BUILD_BUG_ON is hit.
242 	 */
243 	u32 platform_mask[2];
244 
245 	u16 device_id;
246 
247 	u8 num_sprites[I915_MAX_PIPES];
248 	u8 num_scalers[I915_MAX_PIPES];
249 
250 	u32 rawclk_freq;
251 
252 	struct intel_step_info step;
253 };
254 
255 struct intel_driver_caps {
256 	unsigned int scheduler;
257 	bool has_logical_contexts:1;
258 };
259 
260 const char *intel_platform_name(enum intel_platform platform);
261 
262 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
263 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
264 
265 void intel_device_info_print_static(const struct intel_device_info *info,
266 				    struct drm_printer *p);
267 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
268 				     struct drm_printer *p);
269 
270 void intel_driver_caps_print(const struct intel_driver_caps *caps,
271 			     struct drm_printer *p);
272 
273 #endif
274