1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_display.h" 31 32 struct drm_printer; 33 struct drm_i915_private; 34 35 /* Keep in gen based order, and chronological order within a gen */ 36 enum intel_platform { 37 INTEL_PLATFORM_UNINITIALIZED = 0, 38 /* gen2 */ 39 INTEL_I830, 40 INTEL_I845G, 41 INTEL_I85X, 42 INTEL_I865G, 43 /* gen3 */ 44 INTEL_I915G, 45 INTEL_I915GM, 46 INTEL_I945G, 47 INTEL_I945GM, 48 INTEL_G33, 49 INTEL_PINEVIEW, 50 /* gen4 */ 51 INTEL_I965G, 52 INTEL_I965GM, 53 INTEL_G45, 54 INTEL_GM45, 55 /* gen5 */ 56 INTEL_IRONLAKE, 57 /* gen6 */ 58 INTEL_SANDYBRIDGE, 59 /* gen7 */ 60 INTEL_IVYBRIDGE, 61 INTEL_VALLEYVIEW, 62 INTEL_HASWELL, 63 /* gen8 */ 64 INTEL_BROADWELL, 65 INTEL_CHERRYVIEW, 66 /* gen9 */ 67 INTEL_SKYLAKE, 68 INTEL_BROXTON, 69 INTEL_KABYLAKE, 70 INTEL_GEMINILAKE, 71 INTEL_COFFEELAKE, 72 /* gen10 */ 73 INTEL_CANNONLAKE, 74 /* gen11 */ 75 INTEL_ICELAKE, 76 INTEL_MAX_PLATFORMS 77 }; 78 79 enum intel_ppgtt { 80 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 81 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 82 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 83 INTEL_PPGTT_FULL_4LVL, 84 }; 85 86 #define DEV_INFO_FOR_EACH_FLAG(func) \ 87 func(is_mobile); \ 88 func(is_lp); \ 89 func(is_alpha_support); \ 90 /* Keep has_* in alphabetical order */ \ 91 func(has_64bit_reloc); \ 92 func(gpu_reset_clobbers_display); \ 93 func(has_reset_engine); \ 94 func(has_fpga_dbg); \ 95 func(has_guc); \ 96 func(has_guc_ct); \ 97 func(has_l3_dpf); \ 98 func(has_llc); \ 99 func(has_logical_ring_contexts); \ 100 func(has_logical_ring_elsq); \ 101 func(has_logical_ring_preemption); \ 102 func(has_pooled_eu); \ 103 func(has_rc6); \ 104 func(has_rc6p); \ 105 func(has_runtime_pm); \ 106 func(has_snoop); \ 107 func(has_coherent_ggtt); \ 108 func(unfenced_needs_alignment); \ 109 func(hws_needs_physical); 110 111 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 112 /* Keep in alphabetical order */ \ 113 func(cursor_needs_physical); \ 114 func(has_csr); \ 115 func(has_ddi); \ 116 func(has_dp_mst); \ 117 func(has_fbc); \ 118 func(has_gmch); \ 119 func(has_hotplug); \ 120 func(has_ipc); \ 121 func(has_overlay); \ 122 func(has_psr); \ 123 func(overlay_needs_physical); \ 124 func(supports_tv); 125 126 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 127 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 128 129 struct sseu_dev_info { 130 u8 slice_mask; 131 u8 subslice_mask[GEN_MAX_SLICES]; 132 u16 eu_total; 133 u8 eu_per_subslice; 134 u8 min_eu_in_pool; 135 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 136 u8 subslice_7eu[3]; 137 u8 has_slice_pg:1; 138 u8 has_subslice_pg:1; 139 u8 has_eu_pg:1; 140 141 /* Topology fields */ 142 u8 max_slices; 143 u8 max_subslices; 144 u8 max_eus_per_subslice; 145 146 /* We don't have more than 8 eus per subslice at the moment and as we 147 * store eus enabled using bits, no need to multiply by eus per 148 * subslice. 149 */ 150 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES]; 151 }; 152 153 typedef u8 intel_ring_mask_t; 154 155 struct intel_device_info { 156 u16 gen_mask; 157 158 u8 gen; 159 u8 gt; /* GT number, 0 if undefined */ 160 intel_ring_mask_t ring_mask; /* Rings supported by the HW */ 161 162 enum intel_platform platform; 163 u32 platform_mask; 164 165 enum intel_ppgtt ppgtt; 166 unsigned int page_sizes; /* page sizes supported by the HW */ 167 168 u32 display_mmio_offset; 169 170 u8 num_pipes; 171 172 #define DEFINE_FLAG(name) u8 name:1 173 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 174 #undef DEFINE_FLAG 175 176 struct { 177 #define DEFINE_FLAG(name) u8 name:1 178 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 179 #undef DEFINE_FLAG 180 } display; 181 182 u16 ddb_size; /* in blocks */ 183 184 /* Register offsets for the various display pipes and transcoders */ 185 int pipe_offsets[I915_MAX_TRANSCODERS]; 186 int trans_offsets[I915_MAX_TRANSCODERS]; 187 int cursor_offsets[I915_MAX_PIPES]; 188 189 struct color_luts { 190 u16 degamma_lut_size; 191 u16 gamma_lut_size; 192 u32 degamma_lut_tests; 193 u32 gamma_lut_tests; 194 } color; 195 }; 196 197 struct intel_runtime_info { 198 u16 device_id; 199 200 u8 num_sprites[I915_MAX_PIPES]; 201 u8 num_scalers[I915_MAX_PIPES]; 202 203 u8 num_rings; 204 205 /* Slice/subslice/EU info */ 206 struct sseu_dev_info sseu; 207 208 u32 cs_timestamp_frequency_khz; 209 210 /* Enabled (not fused off) media engine bitmasks. */ 211 u8 vdbox_enable; 212 u8 vebox_enable; 213 214 /* Media engine access to SFC per instance */ 215 u8 vdbox_sfc_access; 216 }; 217 218 struct intel_driver_caps { 219 unsigned int scheduler; 220 bool has_logical_contexts:1; 221 }; 222 223 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) 224 { 225 unsigned int i, total = 0; 226 227 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) 228 total += hweight8(sseu->subslice_mask[i]); 229 230 return total; 231 } 232 233 static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, 234 int slice, int subslice) 235 { 236 int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, 237 BITS_PER_BYTE); 238 int slice_stride = sseu->max_subslices * subslice_stride; 239 240 return slice * slice_stride + subslice * subslice_stride; 241 } 242 243 static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, 244 int slice, int subslice) 245 { 246 int i, offset = sseu_eu_idx(sseu, slice, subslice); 247 u16 eu_mask = 0; 248 249 for (i = 0; 250 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { 251 eu_mask |= ((u16) sseu->eu_mask[offset + i]) << 252 (i * BITS_PER_BYTE); 253 } 254 255 return eu_mask; 256 } 257 258 static inline void sseu_set_eus(struct sseu_dev_info *sseu, 259 int slice, int subslice, u16 eu_mask) 260 { 261 int i, offset = sseu_eu_idx(sseu, slice, subslice); 262 263 for (i = 0; 264 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { 265 sseu->eu_mask[offset + i] = 266 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 267 } 268 } 269 270 const char *intel_platform_name(enum intel_platform platform); 271 272 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 273 void intel_device_info_dump_flags(const struct intel_device_info *info, 274 struct drm_printer *p); 275 void intel_device_info_dump_runtime(const struct intel_runtime_info *info, 276 struct drm_printer *p); 277 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, 278 struct drm_printer *p); 279 280 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); 281 282 void intel_driver_caps_print(const struct intel_driver_caps *caps, 283 struct drm_printer *p); 284 285 #endif 286