1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_step.h" 31 32 #include "display/intel_display.h" 33 34 #include "gt/intel_engine_types.h" 35 #include "gt/intel_context_types.h" 36 #include "gt/intel_sseu.h" 37 38 struct drm_printer; 39 struct drm_i915_private; 40 41 /* Keep in gen based order, and chronological order within a gen */ 42 enum intel_platform { 43 INTEL_PLATFORM_UNINITIALIZED = 0, 44 /* gen2 */ 45 INTEL_I830, 46 INTEL_I845G, 47 INTEL_I85X, 48 INTEL_I865G, 49 /* gen3 */ 50 INTEL_I915G, 51 INTEL_I915GM, 52 INTEL_I945G, 53 INTEL_I945GM, 54 INTEL_G33, 55 INTEL_PINEVIEW, 56 /* gen4 */ 57 INTEL_I965G, 58 INTEL_I965GM, 59 INTEL_G45, 60 INTEL_GM45, 61 /* gen5 */ 62 INTEL_IRONLAKE, 63 /* gen6 */ 64 INTEL_SANDYBRIDGE, 65 /* gen7 */ 66 INTEL_IVYBRIDGE, 67 INTEL_VALLEYVIEW, 68 INTEL_HASWELL, 69 /* gen8 */ 70 INTEL_BROADWELL, 71 INTEL_CHERRYVIEW, 72 /* gen9 */ 73 INTEL_SKYLAKE, 74 INTEL_BROXTON, 75 INTEL_KABYLAKE, 76 INTEL_GEMINILAKE, 77 INTEL_COFFEELAKE, 78 INTEL_COMETLAKE, 79 /* gen10 */ 80 INTEL_CANNONLAKE, 81 /* gen11 */ 82 INTEL_ICELAKE, 83 INTEL_ELKHARTLAKE, 84 INTEL_JASPERLAKE, 85 /* gen12 */ 86 INTEL_TIGERLAKE, 87 INTEL_ROCKETLAKE, 88 INTEL_DG1, 89 INTEL_ALDERLAKE_S, 90 INTEL_MAX_PLATFORMS 91 }; 92 93 /* 94 * Subplatform bits share the same namespace per parent platform. In other words 95 * it is fine for the same bit to be used on multiple parent platforms. 96 */ 97 98 #define INTEL_SUBPLATFORM_BITS (2) 99 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) 100 101 /* HSW/BDW/SKL/KBL/CFL */ 102 #define INTEL_SUBPLATFORM_ULT (0) 103 #define INTEL_SUBPLATFORM_ULX (1) 104 105 /* CNL/ICL */ 106 #define INTEL_SUBPLATFORM_PORTF (0) 107 108 enum intel_ppgtt_type { 109 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 110 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 111 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 112 }; 113 114 #define DEV_INFO_FOR_EACH_FLAG(func) \ 115 func(is_mobile); \ 116 func(is_lp); \ 117 func(require_force_probe); \ 118 func(is_dgfx); \ 119 /* Keep has_* in alphabetical order */ \ 120 func(has_64bit_reloc); \ 121 func(gpu_reset_clobbers_display); \ 122 func(has_reset_engine); \ 123 func(has_global_mocs); \ 124 func(has_gt_uc); \ 125 func(has_l3_dpf); \ 126 func(has_llc); \ 127 func(has_logical_ring_contexts); \ 128 func(has_logical_ring_elsq); \ 129 func(has_master_unit_irq); \ 130 func(has_pooled_eu); \ 131 func(has_rc6); \ 132 func(has_rc6p); \ 133 func(has_rps); \ 134 func(has_runtime_pm); \ 135 func(has_snoop); \ 136 func(has_coherent_ggtt); \ 137 func(unfenced_needs_alignment); \ 138 func(hws_needs_physical); 139 140 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 141 /* Keep in alphabetical order */ \ 142 func(cursor_needs_physical); \ 143 func(has_csr); \ 144 func(has_ddi); \ 145 func(has_dp_mst); \ 146 func(has_dsb); \ 147 func(has_dsc); \ 148 func(has_fbc); \ 149 func(has_fpga_dbg); \ 150 func(has_gmch); \ 151 func(has_hdcp); \ 152 func(has_hotplug); \ 153 func(has_hti); \ 154 func(has_ipc); \ 155 func(has_modular_fia); \ 156 func(has_overlay); \ 157 func(has_psr); \ 158 func(has_psr_hw_tracking); \ 159 func(overlay_needs_physical); \ 160 func(supports_tv); 161 162 struct intel_device_info { 163 u16 gen_mask; 164 165 u8 gen; 166 u8 gt; /* GT number, 0 if undefined */ 167 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ 168 169 enum intel_platform platform; 170 171 unsigned int dma_mask_size; /* available DMA address bits */ 172 173 enum intel_ppgtt_type ppgtt_type; 174 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 175 176 unsigned int page_sizes; /* page sizes supported by the HW */ 177 178 u32 memory_regions; /* regions supported by the HW */ 179 180 u32 display_mmio_offset; 181 182 u8 pipe_mask; 183 u8 cpu_transcoder_mask; 184 185 u8 abox_mask; 186 187 #define DEFINE_FLAG(name) u8 name:1 188 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 189 #undef DEFINE_FLAG 190 191 struct { 192 u8 version; 193 194 #define DEFINE_FLAG(name) u8 name:1 195 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 196 #undef DEFINE_FLAG 197 } display; 198 199 u16 ddb_size; /* in blocks */ 200 u8 num_supported_dbuf_slices; /* number of DBuf slices */ 201 202 /* Register offsets for the various display pipes and transcoders */ 203 int pipe_offsets[I915_MAX_TRANSCODERS]; 204 int trans_offsets[I915_MAX_TRANSCODERS]; 205 int cursor_offsets[I915_MAX_PIPES]; 206 207 struct color_luts { 208 u32 degamma_lut_size; 209 u32 gamma_lut_size; 210 u32 degamma_lut_tests; 211 u32 gamma_lut_tests; 212 } color; 213 }; 214 215 struct intel_runtime_info { 216 /* 217 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 218 * into single runtime conditionals, and also to provide groundwork 219 * for future per platform, or per SKU build optimizations. 220 * 221 * Array can be extended when necessary if the corresponding 222 * BUILD_BUG_ON is hit. 223 */ 224 u32 platform_mask[2]; 225 226 u16 device_id; 227 228 u8 num_sprites[I915_MAX_PIPES]; 229 u8 num_scalers[I915_MAX_PIPES]; 230 231 u32 rawclk_freq; 232 233 struct intel_step_info step; 234 }; 235 236 struct intel_driver_caps { 237 unsigned int scheduler; 238 bool has_logical_contexts:1; 239 }; 240 241 const char *intel_platform_name(enum intel_platform platform); 242 243 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); 244 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 245 246 void intel_device_info_print_static(const struct intel_device_info *info, 247 struct drm_printer *p); 248 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 249 struct drm_printer *p); 250 251 void intel_driver_caps_print(const struct intel_driver_caps *caps, 252 struct drm_printer *p); 253 254 #endif 255