1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include "intel_display.h" 29 30 struct drm_printer; 31 struct drm_i915_private; 32 33 /* Keep in gen based order, and chronological order within a gen */ 34 enum intel_platform { 35 INTEL_PLATFORM_UNINITIALIZED = 0, 36 /* gen2 */ 37 INTEL_I830, 38 INTEL_I845G, 39 INTEL_I85X, 40 INTEL_I865G, 41 /* gen3 */ 42 INTEL_I915G, 43 INTEL_I915GM, 44 INTEL_I945G, 45 INTEL_I945GM, 46 INTEL_G33, 47 INTEL_PINEVIEW, 48 /* gen4 */ 49 INTEL_I965G, 50 INTEL_I965GM, 51 INTEL_G45, 52 INTEL_GM45, 53 /* gen5 */ 54 INTEL_IRONLAKE, 55 /* gen6 */ 56 INTEL_SANDYBRIDGE, 57 /* gen7 */ 58 INTEL_IVYBRIDGE, 59 INTEL_VALLEYVIEW, 60 INTEL_HASWELL, 61 /* gen8 */ 62 INTEL_BROADWELL, 63 INTEL_CHERRYVIEW, 64 /* gen9 */ 65 INTEL_SKYLAKE, 66 INTEL_BROXTON, 67 INTEL_KABYLAKE, 68 INTEL_GEMINILAKE, 69 INTEL_COFFEELAKE, 70 /* gen10 */ 71 INTEL_CANNONLAKE, 72 /* gen11 */ 73 INTEL_ICELAKE, 74 INTEL_MAX_PLATFORMS 75 }; 76 77 #define DEV_INFO_FOR_EACH_FLAG(func) \ 78 func(is_mobile); \ 79 func(is_lp); \ 80 func(is_alpha_support); \ 81 /* Keep has_* in alphabetical order */ \ 82 func(has_64bit_reloc); \ 83 func(has_aliasing_ppgtt); \ 84 func(has_csr); \ 85 func(has_ddi); \ 86 func(has_dp_mst); \ 87 func(has_reset_engine); \ 88 func(has_fbc); \ 89 func(has_fpga_dbg); \ 90 func(has_full_ppgtt); \ 91 func(has_full_48bit_ppgtt); \ 92 func(has_gmch_display); \ 93 func(has_guc); \ 94 func(has_guc_ct); \ 95 func(has_hotplug); \ 96 func(has_l3_dpf); \ 97 func(has_llc); \ 98 func(has_logical_ring_contexts); \ 99 func(has_logical_ring_preemption); \ 100 func(has_overlay); \ 101 func(has_pooled_eu); \ 102 func(has_psr); \ 103 func(has_rc6); \ 104 func(has_rc6p); \ 105 func(has_resource_streamer); \ 106 func(has_runtime_pm); \ 107 func(has_snoop); \ 108 func(unfenced_needs_alignment); \ 109 func(cursor_needs_physical); \ 110 func(hws_needs_physical); \ 111 func(overlay_needs_physical); \ 112 func(supports_tv); \ 113 func(has_ipc); 114 115 struct sseu_dev_info { 116 u8 slice_mask; 117 u8 subslice_mask; 118 u8 eu_total; 119 u8 eu_per_subslice; 120 u8 min_eu_in_pool; 121 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 122 u8 subslice_7eu[3]; 123 u8 has_slice_pg:1; 124 u8 has_subslice_pg:1; 125 u8 has_eu_pg:1; 126 }; 127 128 struct intel_device_info { 129 u16 device_id; 130 u16 gen_mask; 131 132 u8 gen; 133 u8 gt; /* GT number, 0 if undefined */ 134 u8 num_rings; 135 u8 ring_mask; /* Rings supported by the HW */ 136 137 enum intel_platform platform; 138 u32 platform_mask; 139 140 u32 display_mmio_offset; 141 142 u8 num_pipes; 143 u8 num_sprites[I915_MAX_PIPES]; 144 u8 num_scalers[I915_MAX_PIPES]; 145 146 unsigned int page_sizes; /* page sizes supported by the HW */ 147 148 #define DEFINE_FLAG(name) u8 name:1 149 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 150 #undef DEFINE_FLAG 151 u16 ddb_size; /* in blocks */ 152 153 /* Register offsets for the various display pipes and transcoders */ 154 int pipe_offsets[I915_MAX_TRANSCODERS]; 155 int trans_offsets[I915_MAX_TRANSCODERS]; 156 int palette_offsets[I915_MAX_PIPES]; 157 int cursor_offsets[I915_MAX_PIPES]; 158 159 /* Slice/subslice/EU info */ 160 struct sseu_dev_info sseu; 161 162 u32 cs_timestamp_frequency_khz; 163 164 struct color_luts { 165 u16 degamma_lut_size; 166 u16 gamma_lut_size; 167 } color; 168 }; 169 170 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) 171 { 172 return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); 173 } 174 175 const char *intel_platform_name(enum intel_platform platform); 176 177 void intel_device_info_runtime_init(struct intel_device_info *info); 178 void intel_device_info_dump(const struct intel_device_info *info, 179 struct drm_printer *p); 180 void intel_device_info_dump_flags(const struct intel_device_info *info, 181 struct drm_printer *p); 182 void intel_device_info_dump_runtime(const struct intel_device_info *info, 183 struct drm_printer *p); 184 185 #endif 186