1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_engine_types.h" 31 #include "intel_display.h" 32 33 struct drm_printer; 34 struct drm_i915_private; 35 36 /* Keep in gen based order, and chronological order within a gen */ 37 enum intel_platform { 38 INTEL_PLATFORM_UNINITIALIZED = 0, 39 /* gen2 */ 40 INTEL_I830, 41 INTEL_I845G, 42 INTEL_I85X, 43 INTEL_I865G, 44 /* gen3 */ 45 INTEL_I915G, 46 INTEL_I915GM, 47 INTEL_I945G, 48 INTEL_I945GM, 49 INTEL_G33, 50 INTEL_PINEVIEW, 51 /* gen4 */ 52 INTEL_I965G, 53 INTEL_I965GM, 54 INTEL_G45, 55 INTEL_GM45, 56 /* gen5 */ 57 INTEL_IRONLAKE, 58 /* gen6 */ 59 INTEL_SANDYBRIDGE, 60 /* gen7 */ 61 INTEL_IVYBRIDGE, 62 INTEL_VALLEYVIEW, 63 INTEL_HASWELL, 64 /* gen8 */ 65 INTEL_BROADWELL, 66 INTEL_CHERRYVIEW, 67 /* gen9 */ 68 INTEL_SKYLAKE, 69 INTEL_BROXTON, 70 INTEL_KABYLAKE, 71 INTEL_GEMINILAKE, 72 INTEL_COFFEELAKE, 73 /* gen10 */ 74 INTEL_CANNONLAKE, 75 /* gen11 */ 76 INTEL_ICELAKE, 77 INTEL_ELKHARTLAKE, 78 INTEL_MAX_PLATFORMS 79 }; 80 81 /* 82 * Subplatform bits share the same namespace per parent platform. In other words 83 * it is fine for the same bit to be used on multiple parent platforms. 84 */ 85 86 #define INTEL_SUBPLATFORM_BITS (3) 87 88 /* HSW/BDW/SKL/KBL/CFL */ 89 #define INTEL_SUBPLATFORM_ULT (0) 90 #define INTEL_SUBPLATFORM_ULX (1) 91 #define INTEL_SUBPLATFORM_AML (2) 92 93 /* CNL/ICL */ 94 #define INTEL_SUBPLATFORM_PORTF (0) 95 96 enum intel_ppgtt_type { 97 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 98 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 99 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 100 }; 101 102 #define DEV_INFO_FOR_EACH_FLAG(func) \ 103 func(is_mobile); \ 104 func(is_lp); \ 105 func(is_alpha_support); \ 106 /* Keep has_* in alphabetical order */ \ 107 func(has_64bit_reloc); \ 108 func(gpu_reset_clobbers_display); \ 109 func(has_reset_engine); \ 110 func(has_fpga_dbg); \ 111 func(has_guc); \ 112 func(has_guc_ct); \ 113 func(has_l3_dpf); \ 114 func(has_llc); \ 115 func(has_logical_ring_contexts); \ 116 func(has_logical_ring_elsq); \ 117 func(has_logical_ring_preemption); \ 118 func(has_pooled_eu); \ 119 func(has_rc6); \ 120 func(has_rc6p); \ 121 func(has_runtime_pm); \ 122 func(has_snoop); \ 123 func(has_coherent_ggtt); \ 124 func(unfenced_needs_alignment); \ 125 func(hws_needs_physical); 126 127 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 128 /* Keep in alphabetical order */ \ 129 func(cursor_needs_physical); \ 130 func(has_csr); \ 131 func(has_ddi); \ 132 func(has_dp_mst); \ 133 func(has_fbc); \ 134 func(has_gmch); \ 135 func(has_hotplug); \ 136 func(has_ipc); \ 137 func(has_overlay); \ 138 func(has_psr); \ 139 func(overlay_needs_physical); \ 140 func(supports_tv); 141 142 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 143 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 144 145 struct sseu_dev_info { 146 u8 slice_mask; 147 u8 subslice_mask[GEN_MAX_SLICES]; 148 u16 eu_total; 149 u8 eu_per_subslice; 150 u8 min_eu_in_pool; 151 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 152 u8 subslice_7eu[3]; 153 u8 has_slice_pg:1; 154 u8 has_subslice_pg:1; 155 u8 has_eu_pg:1; 156 157 /* Topology fields */ 158 u8 max_slices; 159 u8 max_subslices; 160 u8 max_eus_per_subslice; 161 162 /* We don't have more than 8 eus per subslice at the moment and as we 163 * store eus enabled using bits, no need to multiply by eus per 164 * subslice. 165 */ 166 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES]; 167 }; 168 169 struct intel_device_info { 170 u16 gen_mask; 171 172 u8 gen; 173 u8 gt; /* GT number, 0 if undefined */ 174 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ 175 176 enum intel_platform platform; 177 178 enum intel_ppgtt_type ppgtt_type; 179 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 180 181 unsigned int page_sizes; /* page sizes supported by the HW */ 182 183 u32 display_mmio_offset; 184 185 u8 num_pipes; 186 187 #define DEFINE_FLAG(name) u8 name:1 188 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 189 #undef DEFINE_FLAG 190 191 struct { 192 #define DEFINE_FLAG(name) u8 name:1 193 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 194 #undef DEFINE_FLAG 195 } display; 196 197 u16 ddb_size; /* in blocks */ 198 199 /* Register offsets for the various display pipes and transcoders */ 200 int pipe_offsets[I915_MAX_TRANSCODERS]; 201 int trans_offsets[I915_MAX_TRANSCODERS]; 202 int cursor_offsets[I915_MAX_PIPES]; 203 204 struct color_luts { 205 u16 degamma_lut_size; 206 u16 gamma_lut_size; 207 u32 degamma_lut_tests; 208 u32 gamma_lut_tests; 209 } color; 210 }; 211 212 struct intel_runtime_info { 213 /* 214 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 215 * into single runtime conditionals, and also to provide groundwork 216 * for future per platform, or per SKU build optimizations. 217 * 218 * Array can be extended when necessary if the corresponding 219 * BUILD_BUG_ON is hit. 220 */ 221 u32 platform_mask[2]; 222 223 u16 device_id; 224 225 u8 num_sprites[I915_MAX_PIPES]; 226 u8 num_scalers[I915_MAX_PIPES]; 227 228 u8 num_engines; 229 230 /* Slice/subslice/EU info */ 231 struct sseu_dev_info sseu; 232 233 u32 cs_timestamp_frequency_khz; 234 235 /* Media engine access to SFC per instance */ 236 u8 vdbox_sfc_access; 237 }; 238 239 struct intel_driver_caps { 240 unsigned int scheduler; 241 bool has_logical_contexts:1; 242 }; 243 244 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) 245 { 246 unsigned int i, total = 0; 247 248 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) 249 total += hweight8(sseu->subslice_mask[i]); 250 251 return total; 252 } 253 254 static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, 255 int slice, int subslice) 256 { 257 int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, 258 BITS_PER_BYTE); 259 int slice_stride = sseu->max_subslices * subslice_stride; 260 261 return slice * slice_stride + subslice * subslice_stride; 262 } 263 264 static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, 265 int slice, int subslice) 266 { 267 int i, offset = sseu_eu_idx(sseu, slice, subslice); 268 u16 eu_mask = 0; 269 270 for (i = 0; 271 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { 272 eu_mask |= ((u16) sseu->eu_mask[offset + i]) << 273 (i * BITS_PER_BYTE); 274 } 275 276 return eu_mask; 277 } 278 279 static inline void sseu_set_eus(struct sseu_dev_info *sseu, 280 int slice, int subslice, u16 eu_mask) 281 { 282 int i, offset = sseu_eu_idx(sseu, slice, subslice); 283 284 for (i = 0; 285 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { 286 sseu->eu_mask[offset + i] = 287 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 288 } 289 } 290 291 const char *intel_platform_name(enum intel_platform platform); 292 293 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); 294 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 295 void intel_device_info_dump_flags(const struct intel_device_info *info, 296 struct drm_printer *p); 297 void intel_device_info_dump_runtime(const struct intel_runtime_info *info, 298 struct drm_printer *p); 299 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, 300 struct drm_printer *p); 301 302 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); 303 304 void intel_driver_caps_print(const struct intel_driver_caps *caps, 305 struct drm_printer *p); 306 307 #endif 308