1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "intel_step.h" 31 32 #include "display/intel_display_device.h" 33 34 #include "gt/intel_engine_types.h" 35 #include "gt/intel_context_types.h" 36 #include "gt/intel_sseu.h" 37 38 #include "gem/i915_gem_object_types.h" 39 40 struct drm_printer; 41 struct drm_i915_private; 42 struct intel_gt_definition; 43 44 /* Keep in gen based order, and chronological order within a gen */ 45 enum intel_platform { 46 INTEL_PLATFORM_UNINITIALIZED = 0, 47 /* gen2 */ 48 INTEL_I830, 49 INTEL_I845G, 50 INTEL_I85X, 51 INTEL_I865G, 52 /* gen3 */ 53 INTEL_I915G, 54 INTEL_I915GM, 55 INTEL_I945G, 56 INTEL_I945GM, 57 INTEL_G33, 58 INTEL_PINEVIEW, 59 /* gen4 */ 60 INTEL_I965G, 61 INTEL_I965GM, 62 INTEL_G45, 63 INTEL_GM45, 64 /* gen5 */ 65 INTEL_IRONLAKE, 66 /* gen6 */ 67 INTEL_SANDYBRIDGE, 68 /* gen7 */ 69 INTEL_IVYBRIDGE, 70 INTEL_VALLEYVIEW, 71 INTEL_HASWELL, 72 /* gen8 */ 73 INTEL_BROADWELL, 74 INTEL_CHERRYVIEW, 75 /* gen9 */ 76 INTEL_SKYLAKE, 77 INTEL_BROXTON, 78 INTEL_KABYLAKE, 79 INTEL_GEMINILAKE, 80 INTEL_COFFEELAKE, 81 INTEL_COMETLAKE, 82 /* gen11 */ 83 INTEL_ICELAKE, 84 INTEL_ELKHARTLAKE, 85 INTEL_JASPERLAKE, 86 /* gen12 */ 87 INTEL_TIGERLAKE, 88 INTEL_ROCKETLAKE, 89 INTEL_DG1, 90 INTEL_ALDERLAKE_S, 91 INTEL_ALDERLAKE_P, 92 INTEL_XEHPSDV, 93 INTEL_DG2, 94 INTEL_PONTEVECCHIO, 95 INTEL_METEORLAKE, 96 INTEL_MAX_PLATFORMS 97 }; 98 99 /* 100 * Subplatform bits share the same namespace per parent platform. In other words 101 * it is fine for the same bit to be used on multiple parent platforms. 102 */ 103 104 #define INTEL_SUBPLATFORM_BITS (3) 105 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) 106 107 /* HSW/BDW/SKL/KBL/CFL */ 108 #define INTEL_SUBPLATFORM_ULT (0) 109 #define INTEL_SUBPLATFORM_ULX (1) 110 111 /* ICL */ 112 #define INTEL_SUBPLATFORM_PORTF (0) 113 114 /* TGL */ 115 #define INTEL_SUBPLATFORM_UY (0) 116 117 /* DG2 */ 118 #define INTEL_SUBPLATFORM_G10 0 119 #define INTEL_SUBPLATFORM_G11 1 120 #define INTEL_SUBPLATFORM_G12 2 121 122 /* ADL */ 123 #define INTEL_SUBPLATFORM_RPL 0 124 125 /* ADL-P */ 126 /* 127 * As #define INTEL_SUBPLATFORM_RPL 0 will apply 128 * here too, SUBPLATFORM_N will have different 129 * bit set 130 */ 131 #define INTEL_SUBPLATFORM_N 1 132 #define INTEL_SUBPLATFORM_RPLU 2 133 134 /* MTL */ 135 #define INTEL_SUBPLATFORM_M 0 136 #define INTEL_SUBPLATFORM_P 1 137 138 enum intel_ppgtt_type { 139 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 140 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 141 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 142 }; 143 144 #define DEV_INFO_FOR_EACH_FLAG(func) \ 145 func(is_mobile); \ 146 func(is_lp); \ 147 func(require_force_probe); \ 148 func(is_dgfx); \ 149 /* Keep has_* in alphabetical order */ \ 150 func(has_64bit_reloc); \ 151 func(has_64k_pages); \ 152 func(gpu_reset_clobbers_display); \ 153 func(has_reset_engine); \ 154 func(has_3d_pipeline); \ 155 func(has_4tile); \ 156 func(has_flat_ccs); \ 157 func(has_global_mocs); \ 158 func(has_gmd_id); \ 159 func(has_gt_uc); \ 160 func(has_heci_pxp); \ 161 func(has_heci_gscfi); \ 162 func(has_guc_deprivilege); \ 163 func(has_l3_ccs_read); \ 164 func(has_l3_dpf); \ 165 func(has_llc); \ 166 func(has_logical_ring_contexts); \ 167 func(has_logical_ring_elsq); \ 168 func(has_media_ratio_mode); \ 169 func(has_mslice_steering); \ 170 func(has_oa_bpc_reporting); \ 171 func(has_oa_slice_contrib_limits); \ 172 func(has_oam); \ 173 func(has_one_eu_per_fuse_bit); \ 174 func(has_pxp); \ 175 func(has_rc6); \ 176 func(has_rc6p); \ 177 func(has_rps); \ 178 func(has_runtime_pm); \ 179 func(has_snoop); \ 180 func(has_coherent_ggtt); \ 181 func(tuning_thread_rr_after_dep); \ 182 func(unfenced_needs_alignment); \ 183 func(hws_needs_physical); 184 185 struct intel_ip_version { 186 u8 ver; 187 u8 rel; 188 u8 step; 189 }; 190 191 struct intel_runtime_info { 192 /* 193 * Single "graphics" IP version that represents 194 * render, compute and copy behavior. 195 */ 196 struct { 197 struct intel_ip_version ip; 198 } graphics; 199 struct { 200 struct intel_ip_version ip; 201 } media; 202 203 /* 204 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 205 * single runtime conditionals, and also to provide groundwork for 206 * future per platform, or per SKU build optimizations. 207 * 208 * Array can be extended when necessary if the corresponding 209 * BUILD_BUG_ON is hit. 210 */ 211 u32 platform_mask[2]; 212 213 u16 device_id; 214 215 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ 216 217 u32 rawclk_freq; 218 219 struct intel_step_info step; 220 221 unsigned int page_sizes; /* page sizes supported by the HW */ 222 223 enum intel_ppgtt_type ppgtt_type; 224 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 225 226 u32 memory_regions; /* regions supported by the HW */ 227 228 bool has_pooled_eu; 229 }; 230 231 struct intel_device_info { 232 enum intel_platform platform; 233 234 unsigned int dma_mask_size; /* available DMA address bits */ 235 236 const struct intel_gt_definition *extra_gt_list; 237 238 u8 gt; /* GT number, 0 if undefined */ 239 240 #define DEFINE_FLAG(name) u8 name:1 241 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 242 #undef DEFINE_FLAG 243 244 const struct intel_display_device_info *display; 245 246 /* 247 * Initial runtime info. Do not access outside of i915_driver_create(). 248 */ 249 const struct intel_runtime_info __runtime; 250 251 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL]; 252 u32 max_pat_index; 253 }; 254 255 struct intel_driver_caps { 256 unsigned int scheduler; 257 bool has_logical_contexts:1; 258 }; 259 260 const char *intel_platform_name(enum intel_platform platform); 261 262 void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id, 263 const struct intel_device_info *match_info); 264 void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv); 265 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 266 267 void intel_device_info_print(const struct intel_device_info *info, 268 const struct intel_runtime_info *runtime, 269 struct drm_printer *p); 270 271 void intel_driver_caps_print(const struct intel_driver_caps *caps, 272 struct drm_printer *p); 273 274 #endif 275