1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include "i915_drv.h" 26 27 #define PLATFORM_NAME(x) [INTEL_##x] = #x 28 static const char * const platform_names[] = { 29 PLATFORM_NAME(I830), 30 PLATFORM_NAME(I845G), 31 PLATFORM_NAME(I85X), 32 PLATFORM_NAME(I865G), 33 PLATFORM_NAME(I915G), 34 PLATFORM_NAME(I915GM), 35 PLATFORM_NAME(I945G), 36 PLATFORM_NAME(I945GM), 37 PLATFORM_NAME(G33), 38 PLATFORM_NAME(PINEVIEW), 39 PLATFORM_NAME(I965G), 40 PLATFORM_NAME(I965GM), 41 PLATFORM_NAME(G45), 42 PLATFORM_NAME(GM45), 43 PLATFORM_NAME(IRONLAKE), 44 PLATFORM_NAME(SANDYBRIDGE), 45 PLATFORM_NAME(IVYBRIDGE), 46 PLATFORM_NAME(VALLEYVIEW), 47 PLATFORM_NAME(HASWELL), 48 PLATFORM_NAME(BROADWELL), 49 PLATFORM_NAME(CHERRYVIEW), 50 PLATFORM_NAME(SKYLAKE), 51 PLATFORM_NAME(BROXTON), 52 PLATFORM_NAME(KABYLAKE), 53 PLATFORM_NAME(GEMINILAKE), 54 PLATFORM_NAME(COFFEELAKE), 55 PLATFORM_NAME(CANNONLAKE), 56 }; 57 #undef PLATFORM_NAME 58 59 const char *intel_platform_name(enum intel_platform platform) 60 { 61 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 62 63 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 64 platform_names[platform] == NULL)) 65 return "<unknown>"; 66 67 return platform_names[platform]; 68 } 69 70 void intel_device_info_dump(struct drm_i915_private *dev_priv) 71 { 72 const struct intel_device_info *info = &dev_priv->info; 73 74 DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x", 75 intel_platform_name(info->platform), 76 info->gen, 77 dev_priv->drm.pdev->device, 78 dev_priv->drm.pdev->revision); 79 #define PRINT_FLAG(name) \ 80 DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name)) 81 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 82 #undef PRINT_FLAG 83 } 84 85 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) 86 { 87 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; 88 const u32 fuse2 = I915_READ(GEN8_FUSE2); 89 90 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 91 GEN10_F2_S_ENA_SHIFT; 92 sseu->subslice_mask = (1 << 4) - 1; 93 sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 94 GEN10_F2_SS_DIS_SHIFT); 95 96 sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0)); 97 sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1)); 98 sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2)); 99 sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) & 100 GEN10_EU_DIS_SS_MASK)); 101 102 /* 103 * CNL is expected to always have a uniform distribution 104 * of EU across subslices with the exception that any one 105 * EU in any one subslice may be fused off for die 106 * recovery. 107 */ 108 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 109 DIV_ROUND_UP(sseu->eu_total, 110 sseu_subslice_total(sseu)) : 0; 111 112 /* No restrictions on Power Gating */ 113 sseu->has_slice_pg = 1; 114 sseu->has_subslice_pg = 1; 115 sseu->has_eu_pg = 1; 116 } 117 118 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 119 { 120 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; 121 u32 fuse, eu_dis; 122 123 fuse = I915_READ(CHV_FUSE_GT); 124 125 sseu->slice_mask = BIT(0); 126 127 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 128 sseu->subslice_mask |= BIT(0); 129 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | 130 CHV_FGT_EU_DIS_SS0_R1_MASK); 131 sseu->eu_total += 8 - hweight32(eu_dis); 132 } 133 134 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 135 sseu->subslice_mask |= BIT(1); 136 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | 137 CHV_FGT_EU_DIS_SS1_R1_MASK); 138 sseu->eu_total += 8 - hweight32(eu_dis); 139 } 140 141 /* 142 * CHV expected to always have a uniform distribution of EU 143 * across subslices. 144 */ 145 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 146 sseu->eu_total / sseu_subslice_total(sseu) : 147 0; 148 /* 149 * CHV supports subslice power gating on devices with more than 150 * one subslice, and supports EU power gating on devices with 151 * more than one EU pair per subslice. 152 */ 153 sseu->has_slice_pg = 0; 154 sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; 155 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 156 } 157 158 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 159 { 160 struct intel_device_info *info = mkwrite_device_info(dev_priv); 161 struct sseu_dev_info *sseu = &info->sseu; 162 int s_max = 3, ss_max = 4, eu_max = 8; 163 int s, ss; 164 u32 fuse2, eu_disable; 165 u8 eu_mask = 0xff; 166 167 fuse2 = I915_READ(GEN8_FUSE2); 168 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 169 170 /* 171 * The subslice disable field is global, i.e. it applies 172 * to each of the enabled slices. 173 */ 174 sseu->subslice_mask = (1 << ss_max) - 1; 175 sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 176 GEN9_F2_SS_DIS_SHIFT); 177 178 /* 179 * Iterate through enabled slices and subslices to 180 * count the total enabled EU. 181 */ 182 for (s = 0; s < s_max; s++) { 183 if (!(sseu->slice_mask & BIT(s))) 184 /* skip disabled slice */ 185 continue; 186 187 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 188 for (ss = 0; ss < ss_max; ss++) { 189 int eu_per_ss; 190 191 if (!(sseu->subslice_mask & BIT(ss))) 192 /* skip disabled subslice */ 193 continue; 194 195 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & 196 eu_mask); 197 198 /* 199 * Record which subslice(s) has(have) 7 EUs. we 200 * can tune the hash used to spread work among 201 * subslices if they are unbalanced. 202 */ 203 if (eu_per_ss == 7) 204 sseu->subslice_7eu[s] |= BIT(ss); 205 206 sseu->eu_total += eu_per_ss; 207 } 208 } 209 210 /* 211 * SKL is expected to always have a uniform distribution 212 * of EU across subslices with the exception that any one 213 * EU in any one subslice may be fused off for die 214 * recovery. BXT is expected to be perfectly uniform in EU 215 * distribution. 216 */ 217 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 218 DIV_ROUND_UP(sseu->eu_total, 219 sseu_subslice_total(sseu)) : 0; 220 /* 221 * SKL+ supports slice power gating on devices with more than 222 * one slice, and supports EU power gating on devices with 223 * more than one EU pair per subslice. BXT+ supports subslice 224 * power gating on devices with more than one subslice, and 225 * supports EU power gating on devices with more than one EU 226 * pair per subslice. 227 */ 228 sseu->has_slice_pg = 229 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; 230 sseu->has_subslice_pg = 231 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; 232 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 233 234 if (IS_GEN9_LP(dev_priv)) { 235 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss))) 236 info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3; 237 238 sseu->min_eu_in_pool = 0; 239 if (info->has_pooled_eu) { 240 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 241 sseu->min_eu_in_pool = 3; 242 else if (IS_SS_DISABLED(1)) 243 sseu->min_eu_in_pool = 6; 244 else 245 sseu->min_eu_in_pool = 9; 246 } 247 #undef IS_SS_DISABLED 248 } 249 } 250 251 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) 252 { 253 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; 254 const int s_max = 3, ss_max = 3, eu_max = 8; 255 int s, ss; 256 u32 fuse2, eu_disable[3]; /* s_max */ 257 258 fuse2 = I915_READ(GEN8_FUSE2); 259 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 260 /* 261 * The subslice disable field is global, i.e. it applies 262 * to each of the enabled slices. 263 */ 264 sseu->subslice_mask = GENMASK(ss_max - 1, 0); 265 sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 266 GEN8_F2_SS_DIS_SHIFT); 267 268 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 269 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 270 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 271 (32 - GEN8_EU_DIS0_S1_SHIFT)); 272 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 273 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 274 (32 - GEN8_EU_DIS1_S2_SHIFT)); 275 276 /* 277 * Iterate through enabled slices and subslices to 278 * count the total enabled EU. 279 */ 280 for (s = 0; s < s_max; s++) { 281 if (!(sseu->slice_mask & BIT(s))) 282 /* skip disabled slice */ 283 continue; 284 285 for (ss = 0; ss < ss_max; ss++) { 286 u32 n_disabled; 287 288 if (!(sseu->subslice_mask & BIT(ss))) 289 /* skip disabled subslice */ 290 continue; 291 292 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); 293 294 /* 295 * Record which subslices have 7 EUs. 296 */ 297 if (eu_max - n_disabled == 7) 298 sseu->subslice_7eu[s] |= 1 << ss; 299 300 sseu->eu_total += eu_max - n_disabled; 301 } 302 } 303 304 /* 305 * BDW is expected to always have a uniform distribution of EU across 306 * subslices with the exception that any one EU in any one subslice may 307 * be fused off for die recovery. 308 */ 309 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 310 DIV_ROUND_UP(sseu->eu_total, 311 sseu_subslice_total(sseu)) : 0; 312 313 /* 314 * BDW supports slice power gating on devices with more than 315 * one slice. 316 */ 317 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 318 sseu->has_subslice_pg = 0; 319 sseu->has_eu_pg = 0; 320 } 321 322 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) 323 { 324 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); 325 u32 base_freq, frac_freq; 326 327 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> 328 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; 329 base_freq *= 1000; 330 331 frac_freq = ((ts_override & 332 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> 333 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); 334 frac_freq = 1000 / (frac_freq + 1); 335 336 return base_freq + frac_freq; 337 } 338 339 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 340 { 341 u32 f12_5_mhz = 12500; 342 u32 f19_2_mhz = 19200; 343 u32 f24_mhz = 24000; 344 345 if (INTEL_GEN(dev_priv) <= 4) { 346 /* PRMs say: 347 * 348 * "The value in this register increments once every 16 349 * hclks." (through the “Clocking Configuration” 350 * (“CLKCFG”) MCHBAR register) 351 */ 352 return dev_priv->rawclk_freq / 16; 353 } else if (INTEL_GEN(dev_priv) <= 8) { 354 /* PRMs say: 355 * 356 * "The PCU TSC counts 10ns increments; this timestamp 357 * reflects bits 38:3 of the TSC (i.e. 80ns granularity, 358 * rolling over every 1.5 hours). 359 */ 360 return f12_5_mhz; 361 } else if (INTEL_GEN(dev_priv) <= 9) { 362 u32 ctc_reg = I915_READ(CTC_MODE); 363 u32 freq = 0; 364 365 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 366 freq = read_reference_ts_freq(dev_priv); 367 } else { 368 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; 369 370 /* Now figure out how the command stream's timestamp 371 * register increments from this frequency (it might 372 * increment only every few clock cycle). 373 */ 374 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 375 CTC_SHIFT_PARAMETER_SHIFT); 376 } 377 378 return freq; 379 } else if (INTEL_GEN(dev_priv) <= 10) { 380 u32 ctc_reg = I915_READ(CTC_MODE); 381 u32 freq = 0; 382 u32 rpm_config_reg = 0; 383 384 /* First figure out the reference frequency. There are 2 ways 385 * we can compute the frequency, either through the 386 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE 387 * tells us which one we should use. 388 */ 389 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 390 freq = read_reference_ts_freq(dev_priv); 391 } else { 392 u32 crystal_clock; 393 394 rpm_config_reg = I915_READ(RPM_CONFIG0); 395 crystal_clock = (rpm_config_reg & 396 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 397 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 398 switch (crystal_clock) { 399 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 400 freq = f19_2_mhz; 401 break; 402 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 403 freq = f24_mhz; 404 break; 405 } 406 } 407 408 /* Now figure out how the command stream's timestamp register 409 * increments from this frequency (it might increment only 410 * every few clock cycle). 411 */ 412 freq >>= 3 - ((rpm_config_reg & 413 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 414 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 415 416 return freq; 417 } 418 419 DRM_ERROR("Unknown gen, unable to compute command stream timestamp frequency\n"); 420 return 0; 421 } 422 423 /* 424 * Determine various intel_device_info fields at runtime. 425 * 426 * Use it when either: 427 * - it's judged too laborious to fill n static structures with the limit 428 * when a simple if statement does the job, 429 * - run-time checks (eg read fuse/strap registers) are needed. 430 * 431 * This function needs to be called: 432 * - after the MMIO has been setup as we are reading registers, 433 * - after the PCH has been detected, 434 * - before the first usage of the fields it can tweak. 435 */ 436 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 437 { 438 struct intel_device_info *info = mkwrite_device_info(dev_priv); 439 enum pipe pipe; 440 441 if (INTEL_GEN(dev_priv) >= 10) { 442 for_each_pipe(dev_priv, pipe) 443 info->num_scalers[pipe] = 2; 444 } else if (INTEL_GEN(dev_priv) == 9) { 445 info->num_scalers[PIPE_A] = 2; 446 info->num_scalers[PIPE_B] = 2; 447 info->num_scalers[PIPE_C] = 1; 448 } 449 450 /* 451 * Skylake and Broxton currently don't expose the topmost plane as its 452 * use is exclusive with the legacy cursor and we only want to expose 453 * one of those, not both. Until we can safely expose the topmost plane 454 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 455 * we don't expose the topmost plane at all to prevent ABI breakage 456 * down the line. 457 */ 458 if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) 459 for_each_pipe(dev_priv, pipe) 460 info->num_sprites[pipe] = 3; 461 else if (IS_BROXTON(dev_priv)) { 462 info->num_sprites[PIPE_A] = 2; 463 info->num_sprites[PIPE_B] = 2; 464 info->num_sprites[PIPE_C] = 1; 465 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 466 for_each_pipe(dev_priv, pipe) 467 info->num_sprites[pipe] = 2; 468 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 469 for_each_pipe(dev_priv, pipe) 470 info->num_sprites[pipe] = 1; 471 } 472 473 if (i915_modparams.disable_display) { 474 DRM_INFO("Display disabled (module parameter)\n"); 475 info->num_pipes = 0; 476 } else if (info->num_pipes > 0 && 477 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && 478 HAS_PCH_SPLIT(dev_priv)) { 479 u32 fuse_strap = I915_READ(FUSE_STRAP); 480 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 481 482 /* 483 * SFUSE_STRAP is supposed to have a bit signalling the display 484 * is fused off. Unfortunately it seems that, at least in 485 * certain cases, fused off display means that PCH display 486 * reads don't land anywhere. In that case, we read 0s. 487 * 488 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 489 * should be set when taking over after the firmware. 490 */ 491 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 492 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 493 (HAS_PCH_CPT(dev_priv) && 494 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 495 DRM_INFO("Display fused off, disabling\n"); 496 info->num_pipes = 0; 497 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 498 DRM_INFO("PipeC fused off\n"); 499 info->num_pipes -= 1; 500 } 501 } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { 502 u32 dfsm = I915_READ(SKL_DFSM); 503 u8 disabled_mask = 0; 504 bool invalid; 505 int num_bits; 506 507 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) 508 disabled_mask |= BIT(PIPE_A); 509 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) 510 disabled_mask |= BIT(PIPE_B); 511 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) 512 disabled_mask |= BIT(PIPE_C); 513 514 num_bits = hweight8(disabled_mask); 515 516 switch (disabled_mask) { 517 case BIT(PIPE_A): 518 case BIT(PIPE_B): 519 case BIT(PIPE_A) | BIT(PIPE_B): 520 case BIT(PIPE_A) | BIT(PIPE_C): 521 invalid = true; 522 break; 523 default: 524 invalid = false; 525 } 526 527 if (num_bits > info->num_pipes || invalid) 528 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", 529 disabled_mask); 530 else 531 info->num_pipes -= num_bits; 532 } 533 534 /* Initialize slice/subslice/EU info */ 535 if (IS_CHERRYVIEW(dev_priv)) 536 cherryview_sseu_info_init(dev_priv); 537 else if (IS_BROADWELL(dev_priv)) 538 broadwell_sseu_info_init(dev_priv); 539 else if (INTEL_GEN(dev_priv) == 9) 540 gen9_sseu_info_init(dev_priv); 541 else if (INTEL_GEN(dev_priv) >= 10) 542 gen10_sseu_info_init(dev_priv); 543 544 /* Initialize command stream timestamp frequency */ 545 info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); 546 547 DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask); 548 DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask)); 549 DRM_DEBUG_DRIVER("subslice total: %u\n", 550 sseu_subslice_total(&info->sseu)); 551 DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask); 552 DRM_DEBUG_DRIVER("subslice per slice: %u\n", 553 hweight8(info->sseu.subslice_mask)); 554 DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total); 555 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice); 556 DRM_DEBUG_DRIVER("has slice power gating: %s\n", 557 info->sseu.has_slice_pg ? "y" : "n"); 558 DRM_DEBUG_DRIVER("has subslice power gating: %s\n", 559 info->sseu.has_subslice_pg ? "y" : "n"); 560 DRM_DEBUG_DRIVER("has EU power gating: %s\n", 561 info->sseu.has_eu_pg ? "y" : "n"); 562 DRM_DEBUG_DRIVER("CS timestamp frequency: %u kHz\n", 563 info->cs_timestamp_frequency_khz); 564 } 565