1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/string_helpers.h> 26 27 #include <drm/drm_print.h> 28 #include <drm/i915_pciids.h> 29 30 #include "display/intel_cdclk.h" 31 #include "display/intel_de.h" 32 #include "gt/intel_gt_regs.h" 33 #include "intel_device_info.h" 34 #include "i915_drv.h" 35 #include "i915_utils.h" 36 37 #define PLATFORM_NAME(x) [INTEL_##x] = #x 38 static const char * const platform_names[] = { 39 PLATFORM_NAME(I830), 40 PLATFORM_NAME(I845G), 41 PLATFORM_NAME(I85X), 42 PLATFORM_NAME(I865G), 43 PLATFORM_NAME(I915G), 44 PLATFORM_NAME(I915GM), 45 PLATFORM_NAME(I945G), 46 PLATFORM_NAME(I945GM), 47 PLATFORM_NAME(G33), 48 PLATFORM_NAME(PINEVIEW), 49 PLATFORM_NAME(I965G), 50 PLATFORM_NAME(I965GM), 51 PLATFORM_NAME(G45), 52 PLATFORM_NAME(GM45), 53 PLATFORM_NAME(IRONLAKE), 54 PLATFORM_NAME(SANDYBRIDGE), 55 PLATFORM_NAME(IVYBRIDGE), 56 PLATFORM_NAME(VALLEYVIEW), 57 PLATFORM_NAME(HASWELL), 58 PLATFORM_NAME(BROADWELL), 59 PLATFORM_NAME(CHERRYVIEW), 60 PLATFORM_NAME(SKYLAKE), 61 PLATFORM_NAME(BROXTON), 62 PLATFORM_NAME(KABYLAKE), 63 PLATFORM_NAME(GEMINILAKE), 64 PLATFORM_NAME(COFFEELAKE), 65 PLATFORM_NAME(COMETLAKE), 66 PLATFORM_NAME(ICELAKE), 67 PLATFORM_NAME(ELKHARTLAKE), 68 PLATFORM_NAME(JASPERLAKE), 69 PLATFORM_NAME(TIGERLAKE), 70 PLATFORM_NAME(ROCKETLAKE), 71 PLATFORM_NAME(DG1), 72 PLATFORM_NAME(ALDERLAKE_S), 73 PLATFORM_NAME(ALDERLAKE_P), 74 PLATFORM_NAME(XEHPSDV), 75 PLATFORM_NAME(DG2), 76 PLATFORM_NAME(PONTEVECCHIO), 77 PLATFORM_NAME(METEORLAKE), 78 }; 79 #undef PLATFORM_NAME 80 81 const char *intel_platform_name(enum intel_platform platform) 82 { 83 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 84 85 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 86 platform_names[platform] == NULL)) 87 return "<unknown>"; 88 89 return platform_names[platform]; 90 } 91 92 void intel_device_info_print(const struct intel_device_info *info, 93 const struct intel_runtime_info *runtime, 94 struct drm_printer *p) 95 { 96 if (runtime->graphics.ip.rel) 97 drm_printf(p, "graphics version: %u.%02u\n", 98 runtime->graphics.ip.ver, 99 runtime->graphics.ip.rel); 100 else 101 drm_printf(p, "graphics version: %u\n", 102 runtime->graphics.ip.ver); 103 104 if (runtime->media.ip.rel) 105 drm_printf(p, "media version: %u.%02u\n", 106 runtime->media.ip.ver, 107 runtime->media.ip.rel); 108 else 109 drm_printf(p, "media version: %u\n", 110 runtime->media.ip.ver); 111 112 if (runtime->display.ip.rel) 113 drm_printf(p, "display version: %u.%02u\n", 114 runtime->display.ip.ver, 115 runtime->display.ip.rel); 116 else 117 drm_printf(p, "display version: %u\n", 118 runtime->display.ip.ver); 119 120 drm_printf(p, "gt: %d\n", info->gt); 121 drm_printf(p, "memory-regions: %x\n", runtime->memory_regions); 122 drm_printf(p, "page-sizes: %x\n", runtime->page_sizes); 123 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 124 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size); 125 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type); 126 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 127 128 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 129 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 130 #undef PRINT_FLAG 131 132 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); 133 134 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name)) 135 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 136 #undef PRINT_FLAG 137 138 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); 139 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); 140 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); 141 142 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 143 } 144 145 #undef INTEL_VGA_DEVICE 146 #define INTEL_VGA_DEVICE(id, info) (id) 147 148 static const u16 subplatform_ult_ids[] = { 149 INTEL_HSW_ULT_GT1_IDS(0), 150 INTEL_HSW_ULT_GT2_IDS(0), 151 INTEL_HSW_ULT_GT3_IDS(0), 152 INTEL_BDW_ULT_GT1_IDS(0), 153 INTEL_BDW_ULT_GT2_IDS(0), 154 INTEL_BDW_ULT_GT3_IDS(0), 155 INTEL_BDW_ULT_RSVD_IDS(0), 156 INTEL_SKL_ULT_GT1_IDS(0), 157 INTEL_SKL_ULT_GT2_IDS(0), 158 INTEL_SKL_ULT_GT3_IDS(0), 159 INTEL_KBL_ULT_GT1_IDS(0), 160 INTEL_KBL_ULT_GT2_IDS(0), 161 INTEL_KBL_ULT_GT3_IDS(0), 162 INTEL_CFL_U_GT2_IDS(0), 163 INTEL_CFL_U_GT3_IDS(0), 164 INTEL_WHL_U_GT1_IDS(0), 165 INTEL_WHL_U_GT2_IDS(0), 166 INTEL_WHL_U_GT3_IDS(0), 167 INTEL_CML_U_GT1_IDS(0), 168 INTEL_CML_U_GT2_IDS(0), 169 }; 170 171 static const u16 subplatform_ulx_ids[] = { 172 INTEL_HSW_ULX_GT1_IDS(0), 173 INTEL_HSW_ULX_GT2_IDS(0), 174 INTEL_BDW_ULX_GT1_IDS(0), 175 INTEL_BDW_ULX_GT2_IDS(0), 176 INTEL_BDW_ULX_GT3_IDS(0), 177 INTEL_BDW_ULX_RSVD_IDS(0), 178 INTEL_SKL_ULX_GT1_IDS(0), 179 INTEL_SKL_ULX_GT2_IDS(0), 180 INTEL_KBL_ULX_GT1_IDS(0), 181 INTEL_KBL_ULX_GT2_IDS(0), 182 INTEL_AML_KBL_GT2_IDS(0), 183 INTEL_AML_CFL_GT2_IDS(0), 184 }; 185 186 static const u16 subplatform_portf_ids[] = { 187 INTEL_ICL_PORT_F_IDS(0), 188 }; 189 190 static const u16 subplatform_uy_ids[] = { 191 INTEL_TGL_12_GT2_IDS(0), 192 }; 193 194 static const u16 subplatform_n_ids[] = { 195 INTEL_ADLN_IDS(0), 196 }; 197 198 static const u16 subplatform_rpl_ids[] = { 199 INTEL_RPLS_IDS(0), 200 INTEL_RPLP_IDS(0), 201 }; 202 203 static const u16 subplatform_g10_ids[] = { 204 INTEL_DG2_G10_IDS(0), 205 INTEL_ATS_M150_IDS(0), 206 }; 207 208 static const u16 subplatform_g11_ids[] = { 209 INTEL_DG2_G11_IDS(0), 210 INTEL_ATS_M75_IDS(0), 211 }; 212 213 static const u16 subplatform_g12_ids[] = { 214 INTEL_DG2_G12_IDS(0), 215 }; 216 217 static const u16 subplatform_m_ids[] = { 218 INTEL_MTL_M_IDS(0), 219 }; 220 221 static const u16 subplatform_p_ids[] = { 222 INTEL_MTL_P_IDS(0), 223 }; 224 225 static bool find_devid(u16 id, const u16 *p, unsigned int num) 226 { 227 for (; num; num--, p++) { 228 if (*p == id) 229 return true; 230 } 231 232 return false; 233 } 234 235 static void intel_device_info_subplatform_init(struct drm_i915_private *i915) 236 { 237 const struct intel_device_info *info = INTEL_INFO(i915); 238 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 239 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 240 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 241 u16 devid = INTEL_DEVID(i915); 242 u32 mask = 0; 243 244 /* Make sure IS_<platform> checks are working. */ 245 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 246 247 /* Find and mark subplatform bits based on the PCI device id. */ 248 if (find_devid(devid, subplatform_ult_ids, 249 ARRAY_SIZE(subplatform_ult_ids))) { 250 mask = BIT(INTEL_SUBPLATFORM_ULT); 251 } else if (find_devid(devid, subplatform_ulx_ids, 252 ARRAY_SIZE(subplatform_ulx_ids))) { 253 mask = BIT(INTEL_SUBPLATFORM_ULX); 254 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 255 /* ULX machines are also considered ULT. */ 256 mask |= BIT(INTEL_SUBPLATFORM_ULT); 257 } 258 } else if (find_devid(devid, subplatform_portf_ids, 259 ARRAY_SIZE(subplatform_portf_ids))) { 260 mask = BIT(INTEL_SUBPLATFORM_PORTF); 261 } else if (find_devid(devid, subplatform_uy_ids, 262 ARRAY_SIZE(subplatform_uy_ids))) { 263 mask = BIT(INTEL_SUBPLATFORM_UY); 264 } else if (find_devid(devid, subplatform_n_ids, 265 ARRAY_SIZE(subplatform_n_ids))) { 266 mask = BIT(INTEL_SUBPLATFORM_N); 267 } else if (find_devid(devid, subplatform_rpl_ids, 268 ARRAY_SIZE(subplatform_rpl_ids))) { 269 mask = BIT(INTEL_SUBPLATFORM_RPL); 270 } else if (find_devid(devid, subplatform_g10_ids, 271 ARRAY_SIZE(subplatform_g10_ids))) { 272 mask = BIT(INTEL_SUBPLATFORM_G10); 273 } else if (find_devid(devid, subplatform_g11_ids, 274 ARRAY_SIZE(subplatform_g11_ids))) { 275 mask = BIT(INTEL_SUBPLATFORM_G11); 276 } else if (find_devid(devid, subplatform_g12_ids, 277 ARRAY_SIZE(subplatform_g12_ids))) { 278 mask = BIT(INTEL_SUBPLATFORM_G12); 279 } else if (find_devid(devid, subplatform_m_ids, 280 ARRAY_SIZE(subplatform_m_ids))) { 281 mask = BIT(INTEL_SUBPLATFORM_M); 282 } else if (find_devid(devid, subplatform_p_ids, 283 ARRAY_SIZE(subplatform_p_ids))) { 284 mask = BIT(INTEL_SUBPLATFORM_P); 285 } 286 287 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 288 289 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 290 } 291 292 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip) 293 { 294 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 295 void __iomem *addr; 296 u32 val; 297 u8 expected_ver = ip->ver; 298 u8 expected_rel = ip->rel; 299 300 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); 301 if (drm_WARN_ON(&i915->drm, !addr)) 302 return; 303 304 val = ioread32(addr); 305 pci_iounmap(pdev, addr); 306 307 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 308 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 309 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); 310 311 /* Sanity check against expected versions from device info */ 312 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) 313 drm_dbg(&i915->drm, 314 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n", 315 ip->ver, ip->rel, offset, val, expected_ver, expected_rel); 316 } 317 318 /* 319 * Setup the graphics version for the current device. This must be done before 320 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this 321 * function should be called very early in the driver initialization sequence. 322 * 323 * Regular MMIO access is not yet setup at the point this function is called so 324 * we peek at the appropriate MMIO offset directly. The GMD_ID register is 325 * part of an 'always on' power well by design, so we don't need to worry about 326 * forcewake while reading it. 327 */ 328 static void intel_ipver_early_init(struct drm_i915_private *i915) 329 { 330 struct intel_runtime_info *runtime = RUNTIME_INFO(i915); 331 332 if (!HAS_GMD_ID(i915)) { 333 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12); 334 /* 335 * On older platforms, graphics and media share the same ip 336 * version and release. 337 */ 338 RUNTIME_INFO(i915)->media.ip = 339 RUNTIME_INFO(i915)->graphics.ip; 340 return; 341 } 342 343 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), 344 &runtime->graphics.ip); 345 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_DISPLAY), 346 &runtime->display.ip); 347 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), 348 &runtime->media.ip); 349 } 350 351 /** 352 * intel_device_info_runtime_init_early - initialize early runtime info 353 * @i915: the i915 device 354 * 355 * Determine early intel_device_info fields at runtime. This function needs 356 * to be called before the MMIO has been setup. 357 */ 358 void intel_device_info_runtime_init_early(struct drm_i915_private *i915) 359 { 360 intel_ipver_early_init(i915); 361 intel_device_info_subplatform_init(i915); 362 } 363 364 /** 365 * intel_device_info_runtime_init - initialize runtime info 366 * @dev_priv: the i915 device 367 * 368 * Determine various intel_device_info fields at runtime. 369 * 370 * Use it when either: 371 * - it's judged too laborious to fill n static structures with the limit 372 * when a simple if statement does the job, 373 * - run-time checks (eg read fuse/strap registers) are needed. 374 * 375 * This function needs to be called: 376 * - after the MMIO has been setup as we are reading registers, 377 * - after the PCH has been detected, 378 * - before the first usage of the fields it can tweak. 379 */ 380 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 381 { 382 struct intel_device_info *info = mkwrite_device_info(dev_priv); 383 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 384 enum pipe pipe; 385 386 /* Wa_14011765242: adl-s A0,A1 */ 387 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) 388 for_each_pipe(dev_priv, pipe) 389 runtime->num_scalers[pipe] = 0; 390 else if (DISPLAY_VER(dev_priv) >= 11) { 391 for_each_pipe(dev_priv, pipe) 392 runtime->num_scalers[pipe] = 2; 393 } else if (DISPLAY_VER(dev_priv) >= 9) { 394 runtime->num_scalers[PIPE_A] = 2; 395 runtime->num_scalers[PIPE_B] = 2; 396 runtime->num_scalers[PIPE_C] = 1; 397 } 398 399 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 400 401 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 402 for_each_pipe(dev_priv, pipe) 403 runtime->num_sprites[pipe] = 4; 404 else if (DISPLAY_VER(dev_priv) >= 11) 405 for_each_pipe(dev_priv, pipe) 406 runtime->num_sprites[pipe] = 6; 407 else if (DISPLAY_VER(dev_priv) == 10) 408 for_each_pipe(dev_priv, pipe) 409 runtime->num_sprites[pipe] = 3; 410 else if (IS_BROXTON(dev_priv)) { 411 /* 412 * Skylake and Broxton currently don't expose the topmost plane as its 413 * use is exclusive with the legacy cursor and we only want to expose 414 * one of those, not both. Until we can safely expose the topmost plane 415 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 416 * we don't expose the topmost plane at all to prevent ABI breakage 417 * down the line. 418 */ 419 420 runtime->num_sprites[PIPE_A] = 2; 421 runtime->num_sprites[PIPE_B] = 2; 422 runtime->num_sprites[PIPE_C] = 1; 423 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 424 for_each_pipe(dev_priv, pipe) 425 runtime->num_sprites[pipe] = 2; 426 } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { 427 for_each_pipe(dev_priv, pipe) 428 runtime->num_sprites[pipe] = 1; 429 } 430 431 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && 432 HAS_PCH_SPLIT(dev_priv)) { 433 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 434 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); 435 436 /* 437 * SFUSE_STRAP is supposed to have a bit signalling the display 438 * is fused off. Unfortunately it seems that, at least in 439 * certain cases, fused off display means that PCH display 440 * reads don't land anywhere. In that case, we read 0s. 441 * 442 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 443 * should be set when taking over after the firmware. 444 */ 445 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 446 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 447 (HAS_PCH_CPT(dev_priv) && 448 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 449 drm_info(&dev_priv->drm, 450 "Display fused off, disabling\n"); 451 runtime->pipe_mask = 0; 452 runtime->cpu_transcoder_mask = 0; 453 runtime->fbc_mask = 0; 454 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 455 drm_info(&dev_priv->drm, "PipeC fused off\n"); 456 runtime->pipe_mask &= ~BIT(PIPE_C); 457 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 458 } 459 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { 460 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); 461 462 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 463 runtime->pipe_mask &= ~BIT(PIPE_A); 464 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 465 runtime->fbc_mask &= ~BIT(INTEL_FBC_A); 466 } 467 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 468 runtime->pipe_mask &= ~BIT(PIPE_B); 469 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 470 } 471 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 472 runtime->pipe_mask &= ~BIT(PIPE_C); 473 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 474 } 475 476 if (DISPLAY_VER(dev_priv) >= 12 && 477 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 478 runtime->pipe_mask &= ~BIT(PIPE_D); 479 runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 480 } 481 482 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 483 runtime->has_hdcp = 0; 484 485 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 486 runtime->fbc_mask = 0; 487 488 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 489 runtime->has_dmc = 0; 490 491 if (DISPLAY_VER(dev_priv) >= 10 && 492 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 493 runtime->has_dsc = 0; 494 } 495 496 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 497 drm_info(&dev_priv->drm, 498 "Disabling ppGTT for VT-d support\n"); 499 runtime->ppgtt_type = INTEL_PPGTT_NONE; 500 } 501 502 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 503 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 504 505 if (!HAS_DISPLAY(dev_priv)) { 506 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 507 DRIVER_ATOMIC); 508 memset(&info->display, 0, sizeof(info->display)); 509 510 runtime->cpu_transcoder_mask = 0; 511 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); 512 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); 513 runtime->fbc_mask = 0; 514 runtime->has_hdcp = false; 515 runtime->has_dmc = false; 516 runtime->has_dsc = false; 517 } 518 519 /* Disable nuclear pageflip by default on pre-g4x */ 520 if (!dev_priv->params.nuclear_pageflip && 521 DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 522 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; 523 } 524 525 void intel_driver_caps_print(const struct intel_driver_caps *caps, 526 struct drm_printer *p) 527 { 528 drm_printf(p, "Has logical contexts? %s\n", 529 str_yes_no(caps->has_logical_contexts)); 530 drm_printf(p, "scheduler: %x\n", caps->scheduler); 531 } 532