1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 #include <drm/i915_pciids.h> 27 28 #include "display/intel_cdclk.h" 29 #include "intel_device_info.h" 30 #include "i915_drv.h" 31 32 #define PLATFORM_NAME(x) [INTEL_##x] = #x 33 static const char * const platform_names[] = { 34 PLATFORM_NAME(I830), 35 PLATFORM_NAME(I845G), 36 PLATFORM_NAME(I85X), 37 PLATFORM_NAME(I865G), 38 PLATFORM_NAME(I915G), 39 PLATFORM_NAME(I915GM), 40 PLATFORM_NAME(I945G), 41 PLATFORM_NAME(I945GM), 42 PLATFORM_NAME(G33), 43 PLATFORM_NAME(PINEVIEW), 44 PLATFORM_NAME(I965G), 45 PLATFORM_NAME(I965GM), 46 PLATFORM_NAME(G45), 47 PLATFORM_NAME(GM45), 48 PLATFORM_NAME(IRONLAKE), 49 PLATFORM_NAME(SANDYBRIDGE), 50 PLATFORM_NAME(IVYBRIDGE), 51 PLATFORM_NAME(VALLEYVIEW), 52 PLATFORM_NAME(HASWELL), 53 PLATFORM_NAME(BROADWELL), 54 PLATFORM_NAME(CHERRYVIEW), 55 PLATFORM_NAME(SKYLAKE), 56 PLATFORM_NAME(BROXTON), 57 PLATFORM_NAME(KABYLAKE), 58 PLATFORM_NAME(GEMINILAKE), 59 PLATFORM_NAME(COFFEELAKE), 60 PLATFORM_NAME(CANNONLAKE), 61 PLATFORM_NAME(ICELAKE), 62 PLATFORM_NAME(ELKHARTLAKE), 63 PLATFORM_NAME(TIGERLAKE), 64 }; 65 #undef PLATFORM_NAME 66 67 const char *intel_platform_name(enum intel_platform platform) 68 { 69 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 70 71 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 72 platform_names[platform] == NULL)) 73 return "<unknown>"; 74 75 return platform_names[platform]; 76 } 77 78 static const char *iommu_name(void) 79 { 80 const char *msg = "n/a"; 81 82 #ifdef CONFIG_INTEL_IOMMU 83 msg = enableddisabled(intel_iommu_gfx_mapped); 84 #endif 85 86 return msg; 87 } 88 89 void intel_device_info_print_static(const struct intel_device_info *info, 90 struct drm_printer *p) 91 { 92 drm_printf(p, "engines: %x\n", info->engine_mask); 93 drm_printf(p, "gen: %d\n", info->gen); 94 drm_printf(p, "gt: %d\n", info->gt); 95 drm_printf(p, "iommu: %s\n", iommu_name()); 96 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 97 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 98 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 99 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 100 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 101 102 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); 103 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 104 #undef PRINT_FLAG 105 106 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 107 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 108 #undef PRINT_FLAG 109 } 110 111 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 112 { 113 int s; 114 115 drm_printf(p, "slice total: %u, mask=%04x\n", 116 hweight8(sseu->slice_mask), sseu->slice_mask); 117 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); 118 for (s = 0; s < sseu->max_slices; s++) { 119 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 120 s, intel_sseu_subslices_per_slice(sseu, s), 121 intel_sseu_get_subslices(sseu, s)); 122 } 123 drm_printf(p, "EU total: %u\n", sseu->eu_total); 124 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 125 drm_printf(p, "has slice power gating: %s\n", 126 yesno(sseu->has_slice_pg)); 127 drm_printf(p, "has subslice power gating: %s\n", 128 yesno(sseu->has_subslice_pg)); 129 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); 130 } 131 132 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 133 struct drm_printer *p) 134 { 135 sseu_dump(&info->sseu, p); 136 137 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 138 drm_printf(p, "CS timestamp frequency: %u kHz\n", 139 info->cs_timestamp_frequency_khz); 140 } 141 142 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, 143 int subslice) 144 { 145 int slice_stride = sseu->max_subslices * sseu->eu_stride; 146 147 return slice * slice_stride + subslice * sseu->eu_stride; 148 } 149 150 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 151 int subslice) 152 { 153 int i, offset = sseu_eu_idx(sseu, slice, subslice); 154 u16 eu_mask = 0; 155 156 for (i = 0; i < sseu->eu_stride; i++) { 157 eu_mask |= ((u16)sseu->eu_mask[offset + i]) << 158 (i * BITS_PER_BYTE); 159 } 160 161 return eu_mask; 162 } 163 164 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 165 u16 eu_mask) 166 { 167 int i, offset = sseu_eu_idx(sseu, slice, subslice); 168 169 for (i = 0; i < sseu->eu_stride; i++) { 170 sseu->eu_mask[offset + i] = 171 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 172 } 173 } 174 175 void intel_device_info_print_topology(const struct sseu_dev_info *sseu, 176 struct drm_printer *p) 177 { 178 int s, ss; 179 180 if (sseu->max_slices == 0) { 181 drm_printf(p, "Unavailable\n"); 182 return; 183 } 184 185 for (s = 0; s < sseu->max_slices; s++) { 186 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 187 s, intel_sseu_subslices_per_slice(sseu, s), 188 intel_sseu_get_subslices(sseu, s)); 189 190 for (ss = 0; ss < sseu->max_subslices; ss++) { 191 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 192 193 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 194 ss, hweight16(enabled_eus), enabled_eus); 195 } 196 } 197 } 198 199 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 200 { 201 u16 i, total = 0; 202 203 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) 204 total += hweight8(sseu->eu_mask[i]); 205 206 return total; 207 } 208 209 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 210 u8 s_en, u32 ss_en, u16 eu_en) 211 { 212 int s, ss; 213 214 /* ss_en represents entire subslice mask across all slices */ 215 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > 216 sizeof(ss_en) * BITS_PER_BYTE); 217 218 for (s = 0; s < sseu->max_slices; s++) { 219 if ((s_en & BIT(s)) == 0) 220 continue; 221 222 sseu->slice_mask |= BIT(s); 223 224 intel_sseu_set_subslices(sseu, s, ss_en); 225 226 for (ss = 0; ss < sseu->max_subslices; ss++) 227 if (intel_sseu_has_subslice(sseu, s, ss)) 228 sseu_set_eus(sseu, s, ss, eu_en); 229 } 230 sseu->eu_per_subslice = hweight16(eu_en); 231 sseu->eu_total = compute_eu_total(sseu); 232 } 233 234 static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) 235 { 236 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 237 u8 s_en; 238 u32 dss_en; 239 u16 eu_en = 0; 240 u8 eu_en_fuse; 241 int eu; 242 243 /* 244 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 245 * Instead of splitting these, provide userspace with an array 246 * of DSS to more closely represent the hardware resource. 247 */ 248 intel_sseu_set_info(sseu, 1, 6, 16); 249 250 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 251 252 dss_en = I915_READ(GEN12_GT_DSS_ENABLE); 253 254 /* one bit per pair of EUs */ 255 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 256 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 257 if (eu_en_fuse & BIT(eu)) 258 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 259 260 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); 261 262 /* TGL only supports slice-level power gating */ 263 sseu->has_slice_pg = 1; 264 } 265 266 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) 267 { 268 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 269 u8 s_en; 270 u32 ss_en; 271 u8 eu_en; 272 273 if (IS_ELKHARTLAKE(dev_priv)) 274 intel_sseu_set_info(sseu, 1, 4, 8); 275 else 276 intel_sseu_set_info(sseu, 1, 8, 8); 277 278 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 279 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); 280 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 281 282 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); 283 284 /* ICL has no power gating restrictions. */ 285 sseu->has_slice_pg = 1; 286 sseu->has_subslice_pg = 1; 287 sseu->has_eu_pg = 1; 288 } 289 290 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) 291 { 292 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 293 const u32 fuse2 = I915_READ(GEN8_FUSE2); 294 int s, ss; 295 const int eu_mask = 0xff; 296 u32 subslice_mask, eu_en; 297 298 intel_sseu_set_info(sseu, 6, 4, 8); 299 300 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 301 GEN10_F2_S_ENA_SHIFT; 302 303 /* Slice0 */ 304 eu_en = ~I915_READ(GEN8_EU_DISABLE0); 305 for (ss = 0; ss < sseu->max_subslices; ss++) 306 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); 307 /* Slice1 */ 308 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); 309 eu_en = ~I915_READ(GEN8_EU_DISABLE1); 310 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); 311 /* Slice2 */ 312 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); 313 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); 314 /* Slice3 */ 315 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); 316 eu_en = ~I915_READ(GEN8_EU_DISABLE2); 317 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); 318 /* Slice4 */ 319 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); 320 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); 321 /* Slice5 */ 322 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); 323 eu_en = ~I915_READ(GEN10_EU_DISABLE3); 324 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); 325 326 subslice_mask = (1 << 4) - 1; 327 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 328 GEN10_F2_SS_DIS_SHIFT); 329 330 for (s = 0; s < sseu->max_slices; s++) { 331 u32 subslice_mask_with_eus = subslice_mask; 332 333 for (ss = 0; ss < sseu->max_subslices; ss++) { 334 if (sseu_get_eus(sseu, s, ss) == 0) 335 subslice_mask_with_eus &= ~BIT(ss); 336 } 337 338 /* 339 * Slice0 can have up to 3 subslices, but there are only 2 in 340 * slice1/2. 341 */ 342 intel_sseu_set_subslices(sseu, s, s == 0 ? 343 subslice_mask_with_eus : 344 subslice_mask_with_eus & 0x3); 345 } 346 347 sseu->eu_total = compute_eu_total(sseu); 348 349 /* 350 * CNL is expected to always have a uniform distribution 351 * of EU across subslices with the exception that any one 352 * EU in any one subslice may be fused off for die 353 * recovery. 354 */ 355 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 356 DIV_ROUND_UP(sseu->eu_total, 357 intel_sseu_subslice_total(sseu)) : 358 0; 359 360 /* No restrictions on Power Gating */ 361 sseu->has_slice_pg = 1; 362 sseu->has_subslice_pg = 1; 363 sseu->has_eu_pg = 1; 364 } 365 366 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 367 { 368 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 369 u32 fuse; 370 u8 subslice_mask = 0; 371 372 fuse = I915_READ(CHV_FUSE_GT); 373 374 sseu->slice_mask = BIT(0); 375 intel_sseu_set_info(sseu, 1, 2, 8); 376 377 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 378 u8 disabled_mask = 379 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 380 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 381 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 382 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 383 384 subslice_mask |= BIT(0); 385 sseu_set_eus(sseu, 0, 0, ~disabled_mask); 386 } 387 388 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 389 u8 disabled_mask = 390 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 391 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 392 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 393 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 394 395 subslice_mask |= BIT(1); 396 sseu_set_eus(sseu, 0, 1, ~disabled_mask); 397 } 398 399 intel_sseu_set_subslices(sseu, 0, subslice_mask); 400 401 sseu->eu_total = compute_eu_total(sseu); 402 403 /* 404 * CHV expected to always have a uniform distribution of EU 405 * across subslices. 406 */ 407 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 408 sseu->eu_total / 409 intel_sseu_subslice_total(sseu) : 410 0; 411 /* 412 * CHV supports subslice power gating on devices with more than 413 * one subslice, and supports EU power gating on devices with 414 * more than one EU pair per subslice. 415 */ 416 sseu->has_slice_pg = 0; 417 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 418 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 419 } 420 421 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 422 { 423 struct intel_device_info *info = mkwrite_device_info(dev_priv); 424 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 425 int s, ss; 426 u32 fuse2, eu_disable, subslice_mask; 427 const u8 eu_mask = 0xff; 428 429 fuse2 = I915_READ(GEN8_FUSE2); 430 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 431 432 /* BXT has a single slice and at most 3 subslices. */ 433 intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, 434 IS_GEN9_LP(dev_priv) ? 3 : 4, 8); 435 436 /* 437 * The subslice disable field is global, i.e. it applies 438 * to each of the enabled slices. 439 */ 440 subslice_mask = (1 << sseu->max_subslices) - 1; 441 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 442 GEN9_F2_SS_DIS_SHIFT); 443 444 /* 445 * Iterate through enabled slices and subslices to 446 * count the total enabled EU. 447 */ 448 for (s = 0; s < sseu->max_slices; s++) { 449 if (!(sseu->slice_mask & BIT(s))) 450 /* skip disabled slice */ 451 continue; 452 453 intel_sseu_set_subslices(sseu, s, subslice_mask); 454 455 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 456 for (ss = 0; ss < sseu->max_subslices; ss++) { 457 int eu_per_ss; 458 u8 eu_disabled_mask; 459 460 if (!intel_sseu_has_subslice(sseu, s, ss)) 461 /* skip disabled subslice */ 462 continue; 463 464 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 465 466 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 467 468 eu_per_ss = sseu->max_eus_per_subslice - 469 hweight8(eu_disabled_mask); 470 471 /* 472 * Record which subslice(s) has(have) 7 EUs. we 473 * can tune the hash used to spread work among 474 * subslices if they are unbalanced. 475 */ 476 if (eu_per_ss == 7) 477 sseu->subslice_7eu[s] |= BIT(ss); 478 } 479 } 480 481 sseu->eu_total = compute_eu_total(sseu); 482 483 /* 484 * SKL is expected to always have a uniform distribution 485 * of EU across subslices with the exception that any one 486 * EU in any one subslice may be fused off for die 487 * recovery. BXT is expected to be perfectly uniform in EU 488 * distribution. 489 */ 490 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 491 DIV_ROUND_UP(sseu->eu_total, 492 intel_sseu_subslice_total(sseu)) : 493 0; 494 /* 495 * SKL+ supports slice power gating on devices with more than 496 * one slice, and supports EU power gating on devices with 497 * more than one EU pair per subslice. BXT+ supports subslice 498 * power gating on devices with more than one subslice, and 499 * supports EU power gating on devices with more than one EU 500 * pair per subslice. 501 */ 502 sseu->has_slice_pg = 503 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; 504 sseu->has_subslice_pg = 505 IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; 506 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 507 508 if (IS_GEN9_LP(dev_priv)) { 509 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) 510 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; 511 512 sseu->min_eu_in_pool = 0; 513 if (info->has_pooled_eu) { 514 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 515 sseu->min_eu_in_pool = 3; 516 else if (IS_SS_DISABLED(1)) 517 sseu->min_eu_in_pool = 6; 518 else 519 sseu->min_eu_in_pool = 9; 520 } 521 #undef IS_SS_DISABLED 522 } 523 } 524 525 static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) 526 { 527 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 528 int s, ss; 529 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 530 531 fuse2 = I915_READ(GEN8_FUSE2); 532 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 533 intel_sseu_set_info(sseu, 3, 3, 8); 534 535 /* 536 * The subslice disable field is global, i.e. it applies 537 * to each of the enabled slices. 538 */ 539 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 540 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 541 GEN8_F2_SS_DIS_SHIFT); 542 543 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 544 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 545 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 546 (32 - GEN8_EU_DIS0_S1_SHIFT)); 547 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 548 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 549 (32 - GEN8_EU_DIS1_S2_SHIFT)); 550 551 /* 552 * Iterate through enabled slices and subslices to 553 * count the total enabled EU. 554 */ 555 for (s = 0; s < sseu->max_slices; s++) { 556 if (!(sseu->slice_mask & BIT(s))) 557 /* skip disabled slice */ 558 continue; 559 560 intel_sseu_set_subslices(sseu, s, subslice_mask); 561 562 for (ss = 0; ss < sseu->max_subslices; ss++) { 563 u8 eu_disabled_mask; 564 u32 n_disabled; 565 566 if (!intel_sseu_has_subslice(sseu, s, ss)) 567 /* skip disabled subslice */ 568 continue; 569 570 eu_disabled_mask = 571 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 572 573 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 574 575 n_disabled = hweight8(eu_disabled_mask); 576 577 /* 578 * Record which subslices have 7 EUs. 579 */ 580 if (sseu->max_eus_per_subslice - n_disabled == 7) 581 sseu->subslice_7eu[s] |= 1 << ss; 582 } 583 } 584 585 sseu->eu_total = compute_eu_total(sseu); 586 587 /* 588 * BDW is expected to always have a uniform distribution of EU across 589 * subslices with the exception that any one EU in any one subslice may 590 * be fused off for die recovery. 591 */ 592 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 593 DIV_ROUND_UP(sseu->eu_total, 594 intel_sseu_subslice_total(sseu)) : 595 0; 596 597 /* 598 * BDW supports slice power gating on devices with more than 599 * one slice. 600 */ 601 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 602 sseu->has_subslice_pg = 0; 603 sseu->has_eu_pg = 0; 604 } 605 606 static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) 607 { 608 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 609 u32 fuse1; 610 u8 subslice_mask = 0; 611 int s, ss; 612 613 /* 614 * There isn't a register to tell us how many slices/subslices. We 615 * work off the PCI-ids here. 616 */ 617 switch (INTEL_INFO(dev_priv)->gt) { 618 default: 619 MISSING_CASE(INTEL_INFO(dev_priv)->gt); 620 /* fall through */ 621 case 1: 622 sseu->slice_mask = BIT(0); 623 subslice_mask = BIT(0); 624 break; 625 case 2: 626 sseu->slice_mask = BIT(0); 627 subslice_mask = BIT(0) | BIT(1); 628 break; 629 case 3: 630 sseu->slice_mask = BIT(0) | BIT(1); 631 subslice_mask = BIT(0) | BIT(1); 632 break; 633 } 634 635 fuse1 = I915_READ(HSW_PAVP_FUSE1); 636 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { 637 default: 638 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> 639 HSW_F1_EU_DIS_SHIFT); 640 /* fall through */ 641 case HSW_F1_EU_DIS_10EUS: 642 sseu->eu_per_subslice = 10; 643 break; 644 case HSW_F1_EU_DIS_8EUS: 645 sseu->eu_per_subslice = 8; 646 break; 647 case HSW_F1_EU_DIS_6EUS: 648 sseu->eu_per_subslice = 6; 649 break; 650 } 651 652 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 653 hweight8(subslice_mask), 654 sseu->eu_per_subslice); 655 656 for (s = 0; s < sseu->max_slices; s++) { 657 intel_sseu_set_subslices(sseu, s, subslice_mask); 658 659 for (ss = 0; ss < sseu->max_subslices; ss++) { 660 sseu_set_eus(sseu, s, ss, 661 (1UL << sseu->eu_per_subslice) - 1); 662 } 663 } 664 665 sseu->eu_total = compute_eu_total(sseu); 666 667 /* No powergating for you. */ 668 sseu->has_slice_pg = 0; 669 sseu->has_subslice_pg = 0; 670 sseu->has_eu_pg = 0; 671 } 672 673 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) 674 { 675 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); 676 u32 base_freq, frac_freq; 677 678 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> 679 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; 680 base_freq *= 1000; 681 682 frac_freq = ((ts_override & 683 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> 684 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); 685 frac_freq = 1000 / (frac_freq + 1); 686 687 return base_freq + frac_freq; 688 } 689 690 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 691 u32 rpm_config_reg) 692 { 693 u32 f19_2_mhz = 19200; 694 u32 f24_mhz = 24000; 695 u32 crystal_clock = (rpm_config_reg & 696 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 697 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 698 699 switch (crystal_clock) { 700 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 701 return f19_2_mhz; 702 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 703 return f24_mhz; 704 default: 705 MISSING_CASE(crystal_clock); 706 return 0; 707 } 708 } 709 710 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 711 u32 rpm_config_reg) 712 { 713 u32 f19_2_mhz = 19200; 714 u32 f24_mhz = 24000; 715 u32 f25_mhz = 25000; 716 u32 f38_4_mhz = 38400; 717 u32 crystal_clock = (rpm_config_reg & 718 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 719 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 720 721 switch (crystal_clock) { 722 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 723 return f24_mhz; 724 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 725 return f19_2_mhz; 726 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: 727 return f38_4_mhz; 728 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: 729 return f25_mhz; 730 default: 731 MISSING_CASE(crystal_clock); 732 return 0; 733 } 734 } 735 736 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 737 { 738 u32 f12_5_mhz = 12500; 739 u32 f19_2_mhz = 19200; 740 u32 f24_mhz = 24000; 741 742 if (INTEL_GEN(dev_priv) <= 4) { 743 /* PRMs say: 744 * 745 * "The value in this register increments once every 16 746 * hclks." (through the “Clocking Configuration” 747 * (“CLKCFG”) MCHBAR register) 748 */ 749 return RUNTIME_INFO(dev_priv)->rawclk_freq / 16; 750 } else if (INTEL_GEN(dev_priv) <= 8) { 751 /* PRMs say: 752 * 753 * "The PCU TSC counts 10ns increments; this timestamp 754 * reflects bits 38:3 of the TSC (i.e. 80ns granularity, 755 * rolling over every 1.5 hours). 756 */ 757 return f12_5_mhz; 758 } else if (INTEL_GEN(dev_priv) <= 9) { 759 u32 ctc_reg = I915_READ(CTC_MODE); 760 u32 freq = 0; 761 762 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 763 freq = read_reference_ts_freq(dev_priv); 764 } else { 765 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; 766 767 /* Now figure out how the command stream's timestamp 768 * register increments from this frequency (it might 769 * increment only every few clock cycle). 770 */ 771 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 772 CTC_SHIFT_PARAMETER_SHIFT); 773 } 774 775 return freq; 776 } else if (INTEL_GEN(dev_priv) <= 12) { 777 u32 ctc_reg = I915_READ(CTC_MODE); 778 u32 freq = 0; 779 780 /* First figure out the reference frequency. There are 2 ways 781 * we can compute the frequency, either through the 782 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE 783 * tells us which one we should use. 784 */ 785 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 786 freq = read_reference_ts_freq(dev_priv); 787 } else { 788 u32 rpm_config_reg = I915_READ(RPM_CONFIG0); 789 790 if (INTEL_GEN(dev_priv) <= 10) 791 freq = gen10_get_crystal_clock_freq(dev_priv, 792 rpm_config_reg); 793 else 794 freq = gen11_get_crystal_clock_freq(dev_priv, 795 rpm_config_reg); 796 797 /* Now figure out how the command stream's timestamp 798 * register increments from this frequency (it might 799 * increment only every few clock cycle). 800 */ 801 freq >>= 3 - ((rpm_config_reg & 802 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 803 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 804 } 805 806 return freq; 807 } 808 809 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); 810 return 0; 811 } 812 813 #undef INTEL_VGA_DEVICE 814 #define INTEL_VGA_DEVICE(id, info) (id) 815 816 static const u16 subplatform_ult_ids[] = { 817 INTEL_HSW_ULT_GT1_IDS(0), 818 INTEL_HSW_ULT_GT2_IDS(0), 819 INTEL_HSW_ULT_GT3_IDS(0), 820 INTEL_BDW_ULT_GT1_IDS(0), 821 INTEL_BDW_ULT_GT2_IDS(0), 822 INTEL_BDW_ULT_GT3_IDS(0), 823 INTEL_BDW_ULT_RSVD_IDS(0), 824 INTEL_SKL_ULT_GT1_IDS(0), 825 INTEL_SKL_ULT_GT2_IDS(0), 826 INTEL_SKL_ULT_GT3_IDS(0), 827 INTEL_KBL_ULT_GT1_IDS(0), 828 INTEL_KBL_ULT_GT2_IDS(0), 829 INTEL_KBL_ULT_GT3_IDS(0), 830 INTEL_CFL_U_GT2_IDS(0), 831 INTEL_CFL_U_GT3_IDS(0), 832 INTEL_WHL_U_GT1_IDS(0), 833 INTEL_WHL_U_GT2_IDS(0), 834 INTEL_WHL_U_GT3_IDS(0), 835 INTEL_CML_U_GT1_IDS(0), 836 INTEL_CML_U_GT2_IDS(0), 837 }; 838 839 static const u16 subplatform_ulx_ids[] = { 840 INTEL_HSW_ULX_GT1_IDS(0), 841 INTEL_HSW_ULX_GT2_IDS(0), 842 INTEL_BDW_ULX_GT1_IDS(0), 843 INTEL_BDW_ULX_GT2_IDS(0), 844 INTEL_BDW_ULX_GT3_IDS(0), 845 INTEL_BDW_ULX_RSVD_IDS(0), 846 INTEL_SKL_ULX_GT1_IDS(0), 847 INTEL_SKL_ULX_GT2_IDS(0), 848 INTEL_KBL_ULX_GT1_IDS(0), 849 INTEL_KBL_ULX_GT2_IDS(0), 850 INTEL_AML_KBL_GT2_IDS(0), 851 INTEL_AML_CFL_GT2_IDS(0), 852 }; 853 854 static const u16 subplatform_portf_ids[] = { 855 INTEL_CNL_PORT_F_IDS(0), 856 INTEL_ICL_PORT_F_IDS(0), 857 }; 858 859 static bool find_devid(u16 id, const u16 *p, unsigned int num) 860 { 861 for (; num; num--, p++) { 862 if (*p == id) 863 return true; 864 } 865 866 return false; 867 } 868 869 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 870 { 871 const struct intel_device_info *info = INTEL_INFO(i915); 872 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 873 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 874 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 875 u16 devid = INTEL_DEVID(i915); 876 u32 mask = 0; 877 878 /* Make sure IS_<platform> checks are working. */ 879 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 880 881 /* Find and mark subplatform bits based on the PCI device id. */ 882 if (find_devid(devid, subplatform_ult_ids, 883 ARRAY_SIZE(subplatform_ult_ids))) { 884 mask = BIT(INTEL_SUBPLATFORM_ULT); 885 } else if (find_devid(devid, subplatform_ulx_ids, 886 ARRAY_SIZE(subplatform_ulx_ids))) { 887 mask = BIT(INTEL_SUBPLATFORM_ULX); 888 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 889 /* ULX machines are also considered ULT. */ 890 mask |= BIT(INTEL_SUBPLATFORM_ULT); 891 } 892 } else if (find_devid(devid, subplatform_portf_ids, 893 ARRAY_SIZE(subplatform_portf_ids))) { 894 mask = BIT(INTEL_SUBPLATFORM_PORTF); 895 } 896 897 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); 898 899 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 900 } 901 902 /** 903 * intel_device_info_runtime_init - initialize runtime info 904 * @dev_priv: the i915 device 905 * 906 * Determine various intel_device_info fields at runtime. 907 * 908 * Use it when either: 909 * - it's judged too laborious to fill n static structures with the limit 910 * when a simple if statement does the job, 911 * - run-time checks (eg read fuse/strap registers) are needed. 912 * 913 * This function needs to be called: 914 * - after the MMIO has been setup as we are reading registers, 915 * - after the PCH has been detected, 916 * - before the first usage of the fields it can tweak. 917 */ 918 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 919 { 920 struct intel_device_info *info = mkwrite_device_info(dev_priv); 921 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 922 enum pipe pipe; 923 924 if (INTEL_GEN(dev_priv) >= 10) { 925 for_each_pipe(dev_priv, pipe) 926 runtime->num_scalers[pipe] = 2; 927 } else if (IS_GEN(dev_priv, 9)) { 928 runtime->num_scalers[PIPE_A] = 2; 929 runtime->num_scalers[PIPE_B] = 2; 930 runtime->num_scalers[PIPE_C] = 1; 931 } 932 933 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 934 935 if (INTEL_GEN(dev_priv) >= 11) 936 for_each_pipe(dev_priv, pipe) 937 runtime->num_sprites[pipe] = 6; 938 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) 939 for_each_pipe(dev_priv, pipe) 940 runtime->num_sprites[pipe] = 3; 941 else if (IS_BROXTON(dev_priv)) { 942 /* 943 * Skylake and Broxton currently don't expose the topmost plane as its 944 * use is exclusive with the legacy cursor and we only want to expose 945 * one of those, not both. Until we can safely expose the topmost plane 946 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 947 * we don't expose the topmost plane at all to prevent ABI breakage 948 * down the line. 949 */ 950 951 runtime->num_sprites[PIPE_A] = 2; 952 runtime->num_sprites[PIPE_B] = 2; 953 runtime->num_sprites[PIPE_C] = 1; 954 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 955 for_each_pipe(dev_priv, pipe) 956 runtime->num_sprites[pipe] = 2; 957 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 958 for_each_pipe(dev_priv, pipe) 959 runtime->num_sprites[pipe] = 1; 960 } 961 962 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && 963 HAS_PCH_SPLIT(dev_priv)) { 964 u32 fuse_strap = I915_READ(FUSE_STRAP); 965 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 966 967 /* 968 * SFUSE_STRAP is supposed to have a bit signalling the display 969 * is fused off. Unfortunately it seems that, at least in 970 * certain cases, fused off display means that PCH display 971 * reads don't land anywhere. In that case, we read 0s. 972 * 973 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 974 * should be set when taking over after the firmware. 975 */ 976 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 977 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 978 (HAS_PCH_CPT(dev_priv) && 979 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 980 drm_info(&dev_priv->drm, 981 "Display fused off, disabling\n"); 982 info->pipe_mask = 0; 983 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 984 drm_info(&dev_priv->drm, "PipeC fused off\n"); 985 info->pipe_mask &= ~BIT(PIPE_C); 986 } 987 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { 988 u32 dfsm = I915_READ(SKL_DFSM); 989 u8 enabled_mask = info->pipe_mask; 990 991 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) 992 enabled_mask &= ~BIT(PIPE_A); 993 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) 994 enabled_mask &= ~BIT(PIPE_B); 995 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) 996 enabled_mask &= ~BIT(PIPE_C); 997 if (INTEL_GEN(dev_priv) >= 12 && 998 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) 999 enabled_mask &= ~BIT(PIPE_D); 1000 1001 /* 1002 * At least one pipe should be enabled and if there are 1003 * disabled pipes, they should be the last ones, with no holes 1004 * in the mask. 1005 */ 1006 if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1)) 1007 drm_err(&dev_priv->drm, 1008 "invalid pipe fuse configuration: enabled_mask=0x%x\n", 1009 enabled_mask); 1010 else 1011 info->pipe_mask = enabled_mask; 1012 1013 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1014 info->display.has_hdcp = 0; 1015 1016 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1017 info->display.has_fbc = 0; 1018 1019 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1020 info->display.has_csr = 0; 1021 1022 if (INTEL_GEN(dev_priv) >= 10 && 1023 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 1024 info->display.has_dsc = 0; 1025 } 1026 1027 /* Initialize slice/subslice/EU info */ 1028 if (IS_HASWELL(dev_priv)) 1029 hsw_sseu_info_init(dev_priv); 1030 else if (IS_CHERRYVIEW(dev_priv)) 1031 cherryview_sseu_info_init(dev_priv); 1032 else if (IS_BROADWELL(dev_priv)) 1033 bdw_sseu_info_init(dev_priv); 1034 else if (IS_GEN(dev_priv, 9)) 1035 gen9_sseu_info_init(dev_priv); 1036 else if (IS_GEN(dev_priv, 10)) 1037 gen10_sseu_info_init(dev_priv); 1038 else if (IS_GEN(dev_priv, 11)) 1039 gen11_sseu_info_init(dev_priv); 1040 else if (INTEL_GEN(dev_priv) >= 12) 1041 gen12_sseu_info_init(dev_priv); 1042 1043 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { 1044 drm_info(&dev_priv->drm, 1045 "Disabling ppGTT for VT-d support\n"); 1046 info->ppgtt_type = INTEL_PPGTT_NONE; 1047 } 1048 1049 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 1050 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 1051 1052 /* Initialize command stream timestamp frequency */ 1053 runtime->cs_timestamp_frequency_khz = 1054 read_timestamp_frequency(dev_priv); 1055 if (runtime->cs_timestamp_frequency_khz) { 1056 runtime->cs_timestamp_period_ns = 1057 div_u64(1e6, runtime->cs_timestamp_frequency_khz); 1058 drm_dbg(&dev_priv->drm, 1059 "CS timestamp wraparound in %lldms\n", 1060 div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns, 1061 S32_MAX), 1062 USEC_PER_SEC)); 1063 } 1064 } 1065 1066 void intel_driver_caps_print(const struct intel_driver_caps *caps, 1067 struct drm_printer *p) 1068 { 1069 drm_printf(p, "Has logical contexts? %s\n", 1070 yesno(caps->has_logical_contexts)); 1071 drm_printf(p, "scheduler: %x\n", caps->scheduler); 1072 } 1073 1074 /* 1075 * Determine which engines are fused off in our particular hardware. Since the 1076 * fuse register is in the blitter powerwell, we need forcewake to be ready at 1077 * this point (but later we need to prune the forcewake domains for engines that 1078 * are indeed fused off). 1079 */ 1080 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 1081 { 1082 struct intel_device_info *info = mkwrite_device_info(dev_priv); 1083 unsigned int logical_vdbox = 0; 1084 unsigned int i; 1085 u32 media_fuse; 1086 u16 vdbox_mask; 1087 u16 vebox_mask; 1088 1089 if (INTEL_GEN(dev_priv) < 11) 1090 return; 1091 1092 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); 1093 1094 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 1095 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 1096 GEN11_GT_VEBOX_DISABLE_SHIFT; 1097 1098 for (i = 0; i < I915_MAX_VCS; i++) { 1099 if (!HAS_ENGINE(dev_priv, _VCS(i))) { 1100 vdbox_mask &= ~BIT(i); 1101 continue; 1102 } 1103 1104 if (!(BIT(i) & vdbox_mask)) { 1105 info->engine_mask &= ~BIT(_VCS(i)); 1106 drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i); 1107 continue; 1108 } 1109 1110 /* 1111 * In Gen11, only even numbered logical VDBOXes are 1112 * hooked up to an SFC (Scaler & Format Converter) unit. 1113 * In TGL each VDBOX has access to an SFC. 1114 */ 1115 if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0) 1116 RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); 1117 } 1118 drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", 1119 vdbox_mask, VDBOX_MASK(dev_priv)); 1120 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); 1121 1122 for (i = 0; i < I915_MAX_VECS; i++) { 1123 if (!HAS_ENGINE(dev_priv, _VECS(i))) { 1124 vebox_mask &= ~BIT(i); 1125 continue; 1126 } 1127 1128 if (!(BIT(i) & vebox_mask)) { 1129 info->engine_mask &= ~BIT(_VECS(i)); 1130 drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i); 1131 } 1132 } 1133 drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", 1134 vebox_mask, VEBOX_MASK(dev_priv)); 1135 GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); 1136 } 1137