1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 27 #include "intel_device_info.h" 28 #include "i915_drv.h" 29 30 #define PLATFORM_NAME(x) [INTEL_##x] = #x 31 static const char * const platform_names[] = { 32 PLATFORM_NAME(I830), 33 PLATFORM_NAME(I845G), 34 PLATFORM_NAME(I85X), 35 PLATFORM_NAME(I865G), 36 PLATFORM_NAME(I915G), 37 PLATFORM_NAME(I915GM), 38 PLATFORM_NAME(I945G), 39 PLATFORM_NAME(I945GM), 40 PLATFORM_NAME(G33), 41 PLATFORM_NAME(PINEVIEW), 42 PLATFORM_NAME(I965G), 43 PLATFORM_NAME(I965GM), 44 PLATFORM_NAME(G45), 45 PLATFORM_NAME(GM45), 46 PLATFORM_NAME(IRONLAKE), 47 PLATFORM_NAME(SANDYBRIDGE), 48 PLATFORM_NAME(IVYBRIDGE), 49 PLATFORM_NAME(VALLEYVIEW), 50 PLATFORM_NAME(HASWELL), 51 PLATFORM_NAME(BROADWELL), 52 PLATFORM_NAME(CHERRYVIEW), 53 PLATFORM_NAME(SKYLAKE), 54 PLATFORM_NAME(BROXTON), 55 PLATFORM_NAME(KABYLAKE), 56 PLATFORM_NAME(GEMINILAKE), 57 PLATFORM_NAME(COFFEELAKE), 58 PLATFORM_NAME(CANNONLAKE), 59 PLATFORM_NAME(ICELAKE), 60 PLATFORM_NAME(ELKHARTLAKE), 61 PLATFORM_NAME(TIGERLAKE), 62 }; 63 #undef PLATFORM_NAME 64 65 const char *intel_platform_name(enum intel_platform platform) 66 { 67 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 68 69 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 70 platform_names[platform] == NULL)) 71 return "<unknown>"; 72 73 return platform_names[platform]; 74 } 75 76 void intel_device_info_dump_flags(const struct intel_device_info *info, 77 struct drm_printer *p) 78 { 79 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); 80 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 81 #undef PRINT_FLAG 82 83 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 84 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 85 #undef PRINT_FLAG 86 } 87 88 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 89 { 90 int s; 91 92 drm_printf(p, "slice total: %u, mask=%04x\n", 93 hweight8(sseu->slice_mask), sseu->slice_mask); 94 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); 95 for (s = 0; s < sseu->max_slices; s++) { 96 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 97 s, intel_sseu_subslices_per_slice(sseu, s), 98 intel_sseu_get_subslices(sseu, s)); 99 } 100 drm_printf(p, "EU total: %u\n", sseu->eu_total); 101 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 102 drm_printf(p, "has slice power gating: %s\n", 103 yesno(sseu->has_slice_pg)); 104 drm_printf(p, "has subslice power gating: %s\n", 105 yesno(sseu->has_subslice_pg)); 106 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); 107 } 108 109 void intel_device_info_dump_runtime(const struct intel_runtime_info *info, 110 struct drm_printer *p) 111 { 112 sseu_dump(&info->sseu, p); 113 114 drm_printf(p, "CS timestamp frequency: %u kHz\n", 115 info->cs_timestamp_frequency_khz); 116 } 117 118 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, 119 int subslice) 120 { 121 int slice_stride = sseu->max_subslices * sseu->eu_stride; 122 123 return slice * slice_stride + subslice * sseu->eu_stride; 124 } 125 126 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 127 int subslice) 128 { 129 int i, offset = sseu_eu_idx(sseu, slice, subslice); 130 u16 eu_mask = 0; 131 132 for (i = 0; i < sseu->eu_stride; i++) { 133 eu_mask |= ((u16)sseu->eu_mask[offset + i]) << 134 (i * BITS_PER_BYTE); 135 } 136 137 return eu_mask; 138 } 139 140 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 141 u16 eu_mask) 142 { 143 int i, offset = sseu_eu_idx(sseu, slice, subslice); 144 145 for (i = 0; i < sseu->eu_stride; i++) { 146 sseu->eu_mask[offset + i] = 147 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 148 } 149 } 150 151 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, 152 struct drm_printer *p) 153 { 154 int s, ss; 155 156 if (sseu->max_slices == 0) { 157 drm_printf(p, "Unavailable\n"); 158 return; 159 } 160 161 for (s = 0; s < sseu->max_slices; s++) { 162 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 163 s, intel_sseu_subslices_per_slice(sseu, s), 164 intel_sseu_get_subslices(sseu, s)); 165 166 for (ss = 0; ss < sseu->max_subslices; ss++) { 167 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 168 169 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 170 ss, hweight16(enabled_eus), enabled_eus); 171 } 172 } 173 } 174 175 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 176 { 177 u16 i, total = 0; 178 179 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) 180 total += hweight8(sseu->eu_mask[i]); 181 182 return total; 183 } 184 185 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 186 u8 s_en, u32 ss_en, u16 eu_en) 187 { 188 int s, ss; 189 190 /* ss_en represents entire subslice mask across all slices */ 191 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > 192 sizeof(ss_en) * BITS_PER_BYTE); 193 194 for (s = 0; s < sseu->max_slices; s++) { 195 if ((s_en & BIT(s)) == 0) 196 continue; 197 198 sseu->slice_mask |= BIT(s); 199 200 intel_sseu_set_subslices(sseu, s, ss_en); 201 202 for (ss = 0; ss < sseu->max_subslices; ss++) 203 if (intel_sseu_has_subslice(sseu, s, ss)) 204 sseu_set_eus(sseu, s, ss, eu_en); 205 } 206 sseu->eu_per_subslice = hweight16(eu_en); 207 sseu->eu_total = compute_eu_total(sseu); 208 } 209 210 static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) 211 { 212 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 213 u8 s_en; 214 u32 dss_en; 215 u16 eu_en = 0; 216 u8 eu_en_fuse; 217 int eu; 218 219 /* 220 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 221 * Instead of splitting these, provide userspace with an array 222 * of DSS to more closely represent the hardware resource. 223 */ 224 intel_sseu_set_info(sseu, 1, 6, 16); 225 226 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 227 228 dss_en = I915_READ(GEN12_GT_DSS_ENABLE); 229 230 /* one bit per pair of EUs */ 231 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 232 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 233 if (eu_en_fuse & BIT(eu)) 234 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 235 236 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); 237 238 /* TGL only supports slice-level power gating */ 239 sseu->has_slice_pg = 1; 240 } 241 242 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) 243 { 244 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 245 u8 s_en; 246 u32 ss_en; 247 u8 eu_en; 248 249 if (IS_ELKHARTLAKE(dev_priv)) 250 intel_sseu_set_info(sseu, 1, 4, 8); 251 else 252 intel_sseu_set_info(sseu, 1, 8, 8); 253 254 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 255 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); 256 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 257 258 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); 259 260 /* ICL has no power gating restrictions. */ 261 sseu->has_slice_pg = 1; 262 sseu->has_subslice_pg = 1; 263 sseu->has_eu_pg = 1; 264 } 265 266 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) 267 { 268 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 269 const u32 fuse2 = I915_READ(GEN8_FUSE2); 270 int s, ss; 271 const int eu_mask = 0xff; 272 u32 subslice_mask, eu_en; 273 274 intel_sseu_set_info(sseu, 6, 4, 8); 275 276 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 277 GEN10_F2_S_ENA_SHIFT; 278 279 /* Slice0 */ 280 eu_en = ~I915_READ(GEN8_EU_DISABLE0); 281 for (ss = 0; ss < sseu->max_subslices; ss++) 282 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); 283 /* Slice1 */ 284 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); 285 eu_en = ~I915_READ(GEN8_EU_DISABLE1); 286 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); 287 /* Slice2 */ 288 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); 289 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); 290 /* Slice3 */ 291 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); 292 eu_en = ~I915_READ(GEN8_EU_DISABLE2); 293 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); 294 /* Slice4 */ 295 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); 296 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); 297 /* Slice5 */ 298 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); 299 eu_en = ~I915_READ(GEN10_EU_DISABLE3); 300 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); 301 302 subslice_mask = (1 << 4) - 1; 303 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 304 GEN10_F2_SS_DIS_SHIFT); 305 306 for (s = 0; s < sseu->max_slices; s++) { 307 u32 subslice_mask_with_eus = subslice_mask; 308 309 for (ss = 0; ss < sseu->max_subslices; ss++) { 310 if (sseu_get_eus(sseu, s, ss) == 0) 311 subslice_mask_with_eus &= ~BIT(ss); 312 } 313 314 /* 315 * Slice0 can have up to 3 subslices, but there are only 2 in 316 * slice1/2. 317 */ 318 intel_sseu_set_subslices(sseu, s, s == 0 ? 319 subslice_mask_with_eus : 320 subslice_mask_with_eus & 0x3); 321 } 322 323 sseu->eu_total = compute_eu_total(sseu); 324 325 /* 326 * CNL is expected to always have a uniform distribution 327 * of EU across subslices with the exception that any one 328 * EU in any one subslice may be fused off for die 329 * recovery. 330 */ 331 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 332 DIV_ROUND_UP(sseu->eu_total, 333 intel_sseu_subslice_total(sseu)) : 334 0; 335 336 /* No restrictions on Power Gating */ 337 sseu->has_slice_pg = 1; 338 sseu->has_subslice_pg = 1; 339 sseu->has_eu_pg = 1; 340 } 341 342 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 343 { 344 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 345 u32 fuse; 346 u8 subslice_mask = 0; 347 348 fuse = I915_READ(CHV_FUSE_GT); 349 350 sseu->slice_mask = BIT(0); 351 intel_sseu_set_info(sseu, 1, 2, 8); 352 353 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 354 u8 disabled_mask = 355 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 356 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 357 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 358 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 359 360 subslice_mask |= BIT(0); 361 sseu_set_eus(sseu, 0, 0, ~disabled_mask); 362 } 363 364 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 365 u8 disabled_mask = 366 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 367 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 368 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 369 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 370 371 subslice_mask |= BIT(1); 372 sseu_set_eus(sseu, 0, 1, ~disabled_mask); 373 } 374 375 intel_sseu_set_subslices(sseu, 0, subslice_mask); 376 377 sseu->eu_total = compute_eu_total(sseu); 378 379 /* 380 * CHV expected to always have a uniform distribution of EU 381 * across subslices. 382 */ 383 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 384 sseu->eu_total / 385 intel_sseu_subslice_total(sseu) : 386 0; 387 /* 388 * CHV supports subslice power gating on devices with more than 389 * one subslice, and supports EU power gating on devices with 390 * more than one EU pair per subslice. 391 */ 392 sseu->has_slice_pg = 0; 393 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 394 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 395 } 396 397 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 398 { 399 struct intel_device_info *info = mkwrite_device_info(dev_priv); 400 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 401 int s, ss; 402 u32 fuse2, eu_disable, subslice_mask; 403 const u8 eu_mask = 0xff; 404 405 fuse2 = I915_READ(GEN8_FUSE2); 406 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 407 408 /* BXT has a single slice and at most 3 subslices. */ 409 intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, 410 IS_GEN9_LP(dev_priv) ? 3 : 4, 8); 411 412 /* 413 * The subslice disable field is global, i.e. it applies 414 * to each of the enabled slices. 415 */ 416 subslice_mask = (1 << sseu->max_subslices) - 1; 417 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 418 GEN9_F2_SS_DIS_SHIFT); 419 420 /* 421 * Iterate through enabled slices and subslices to 422 * count the total enabled EU. 423 */ 424 for (s = 0; s < sseu->max_slices; s++) { 425 if (!(sseu->slice_mask & BIT(s))) 426 /* skip disabled slice */ 427 continue; 428 429 intel_sseu_set_subslices(sseu, s, subslice_mask); 430 431 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 432 for (ss = 0; ss < sseu->max_subslices; ss++) { 433 int eu_per_ss; 434 u8 eu_disabled_mask; 435 436 if (!intel_sseu_has_subslice(sseu, s, ss)) 437 /* skip disabled subslice */ 438 continue; 439 440 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 441 442 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 443 444 eu_per_ss = sseu->max_eus_per_subslice - 445 hweight8(eu_disabled_mask); 446 447 /* 448 * Record which subslice(s) has(have) 7 EUs. we 449 * can tune the hash used to spread work among 450 * subslices if they are unbalanced. 451 */ 452 if (eu_per_ss == 7) 453 sseu->subslice_7eu[s] |= BIT(ss); 454 } 455 } 456 457 sseu->eu_total = compute_eu_total(sseu); 458 459 /* 460 * SKL is expected to always have a uniform distribution 461 * of EU across subslices with the exception that any one 462 * EU in any one subslice may be fused off for die 463 * recovery. BXT is expected to be perfectly uniform in EU 464 * distribution. 465 */ 466 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 467 DIV_ROUND_UP(sseu->eu_total, 468 intel_sseu_subslice_total(sseu)) : 469 0; 470 /* 471 * SKL+ supports slice power gating on devices with more than 472 * one slice, and supports EU power gating on devices with 473 * more than one EU pair per subslice. BXT+ supports subslice 474 * power gating on devices with more than one subslice, and 475 * supports EU power gating on devices with more than one EU 476 * pair per subslice. 477 */ 478 sseu->has_slice_pg = 479 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; 480 sseu->has_subslice_pg = 481 IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; 482 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 483 484 if (IS_GEN9_LP(dev_priv)) { 485 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) 486 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; 487 488 sseu->min_eu_in_pool = 0; 489 if (info->has_pooled_eu) { 490 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 491 sseu->min_eu_in_pool = 3; 492 else if (IS_SS_DISABLED(1)) 493 sseu->min_eu_in_pool = 6; 494 else 495 sseu->min_eu_in_pool = 9; 496 } 497 #undef IS_SS_DISABLED 498 } 499 } 500 501 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) 502 { 503 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 504 int s, ss; 505 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 506 507 fuse2 = I915_READ(GEN8_FUSE2); 508 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 509 intel_sseu_set_info(sseu, 3, 3, 8); 510 511 /* 512 * The subslice disable field is global, i.e. it applies 513 * to each of the enabled slices. 514 */ 515 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 516 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 517 GEN8_F2_SS_DIS_SHIFT); 518 519 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 520 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 521 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 522 (32 - GEN8_EU_DIS0_S1_SHIFT)); 523 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 524 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 525 (32 - GEN8_EU_DIS1_S2_SHIFT)); 526 527 /* 528 * Iterate through enabled slices and subslices to 529 * count the total enabled EU. 530 */ 531 for (s = 0; s < sseu->max_slices; s++) { 532 if (!(sseu->slice_mask & BIT(s))) 533 /* skip disabled slice */ 534 continue; 535 536 intel_sseu_set_subslices(sseu, s, subslice_mask); 537 538 for (ss = 0; ss < sseu->max_subslices; ss++) { 539 u8 eu_disabled_mask; 540 u32 n_disabled; 541 542 if (!intel_sseu_has_subslice(sseu, s, ss)) 543 /* skip disabled subslice */ 544 continue; 545 546 eu_disabled_mask = 547 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 548 549 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 550 551 n_disabled = hweight8(eu_disabled_mask); 552 553 /* 554 * Record which subslices have 7 EUs. 555 */ 556 if (sseu->max_eus_per_subslice - n_disabled == 7) 557 sseu->subslice_7eu[s] |= 1 << ss; 558 } 559 } 560 561 sseu->eu_total = compute_eu_total(sseu); 562 563 /* 564 * BDW is expected to always have a uniform distribution of EU across 565 * subslices with the exception that any one EU in any one subslice may 566 * be fused off for die recovery. 567 */ 568 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 569 DIV_ROUND_UP(sseu->eu_total, 570 intel_sseu_subslice_total(sseu)) : 571 0; 572 573 /* 574 * BDW supports slice power gating on devices with more than 575 * one slice. 576 */ 577 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 578 sseu->has_subslice_pg = 0; 579 sseu->has_eu_pg = 0; 580 } 581 582 static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) 583 { 584 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 585 u32 fuse1; 586 u8 subslice_mask = 0; 587 int s, ss; 588 589 /* 590 * There isn't a register to tell us how many slices/subslices. We 591 * work off the PCI-ids here. 592 */ 593 switch (INTEL_INFO(dev_priv)->gt) { 594 default: 595 MISSING_CASE(INTEL_INFO(dev_priv)->gt); 596 /* fall through */ 597 case 1: 598 sseu->slice_mask = BIT(0); 599 subslice_mask = BIT(0); 600 break; 601 case 2: 602 sseu->slice_mask = BIT(0); 603 subslice_mask = BIT(0) | BIT(1); 604 break; 605 case 3: 606 sseu->slice_mask = BIT(0) | BIT(1); 607 subslice_mask = BIT(0) | BIT(1); 608 break; 609 } 610 611 fuse1 = I915_READ(HSW_PAVP_FUSE1); 612 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { 613 default: 614 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> 615 HSW_F1_EU_DIS_SHIFT); 616 /* fall through */ 617 case HSW_F1_EU_DIS_10EUS: 618 sseu->eu_per_subslice = 10; 619 break; 620 case HSW_F1_EU_DIS_8EUS: 621 sseu->eu_per_subslice = 8; 622 break; 623 case HSW_F1_EU_DIS_6EUS: 624 sseu->eu_per_subslice = 6; 625 break; 626 } 627 628 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 629 hweight8(subslice_mask), 630 sseu->eu_per_subslice); 631 632 for (s = 0; s < sseu->max_slices; s++) { 633 intel_sseu_set_subslices(sseu, s, subslice_mask); 634 635 for (ss = 0; ss < sseu->max_subslices; ss++) { 636 sseu_set_eus(sseu, s, ss, 637 (1UL << sseu->eu_per_subslice) - 1); 638 } 639 } 640 641 sseu->eu_total = compute_eu_total(sseu); 642 643 /* No powergating for you. */ 644 sseu->has_slice_pg = 0; 645 sseu->has_subslice_pg = 0; 646 sseu->has_eu_pg = 0; 647 } 648 649 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) 650 { 651 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); 652 u32 base_freq, frac_freq; 653 654 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> 655 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; 656 base_freq *= 1000; 657 658 frac_freq = ((ts_override & 659 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> 660 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); 661 frac_freq = 1000 / (frac_freq + 1); 662 663 return base_freq + frac_freq; 664 } 665 666 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 667 u32 rpm_config_reg) 668 { 669 u32 f19_2_mhz = 19200; 670 u32 f24_mhz = 24000; 671 u32 crystal_clock = (rpm_config_reg & 672 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 673 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 674 675 switch (crystal_clock) { 676 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 677 return f19_2_mhz; 678 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 679 return f24_mhz; 680 default: 681 MISSING_CASE(crystal_clock); 682 return 0; 683 } 684 } 685 686 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 687 u32 rpm_config_reg) 688 { 689 u32 f19_2_mhz = 19200; 690 u32 f24_mhz = 24000; 691 u32 f25_mhz = 25000; 692 u32 f38_4_mhz = 38400; 693 u32 crystal_clock = (rpm_config_reg & 694 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 695 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 696 697 switch (crystal_clock) { 698 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 699 return f24_mhz; 700 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 701 return f19_2_mhz; 702 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: 703 return f38_4_mhz; 704 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: 705 return f25_mhz; 706 default: 707 MISSING_CASE(crystal_clock); 708 return 0; 709 } 710 } 711 712 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 713 { 714 u32 f12_5_mhz = 12500; 715 u32 f19_2_mhz = 19200; 716 u32 f24_mhz = 24000; 717 718 if (INTEL_GEN(dev_priv) <= 4) { 719 /* PRMs say: 720 * 721 * "The value in this register increments once every 16 722 * hclks." (through the “Clocking Configuration” 723 * (“CLKCFG”) MCHBAR register) 724 */ 725 return dev_priv->rawclk_freq / 16; 726 } else if (INTEL_GEN(dev_priv) <= 8) { 727 /* PRMs say: 728 * 729 * "The PCU TSC counts 10ns increments; this timestamp 730 * reflects bits 38:3 of the TSC (i.e. 80ns granularity, 731 * rolling over every 1.5 hours). 732 */ 733 return f12_5_mhz; 734 } else if (INTEL_GEN(dev_priv) <= 9) { 735 u32 ctc_reg = I915_READ(CTC_MODE); 736 u32 freq = 0; 737 738 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 739 freq = read_reference_ts_freq(dev_priv); 740 } else { 741 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; 742 743 /* Now figure out how the command stream's timestamp 744 * register increments from this frequency (it might 745 * increment only every few clock cycle). 746 */ 747 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 748 CTC_SHIFT_PARAMETER_SHIFT); 749 } 750 751 return freq; 752 } else if (INTEL_GEN(dev_priv) <= 12) { 753 u32 ctc_reg = I915_READ(CTC_MODE); 754 u32 freq = 0; 755 756 /* First figure out the reference frequency. There are 2 ways 757 * we can compute the frequency, either through the 758 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE 759 * tells us which one we should use. 760 */ 761 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 762 freq = read_reference_ts_freq(dev_priv); 763 } else { 764 u32 rpm_config_reg = I915_READ(RPM_CONFIG0); 765 766 if (INTEL_GEN(dev_priv) <= 10) 767 freq = gen10_get_crystal_clock_freq(dev_priv, 768 rpm_config_reg); 769 else 770 freq = gen11_get_crystal_clock_freq(dev_priv, 771 rpm_config_reg); 772 773 /* Now figure out how the command stream's timestamp 774 * register increments from this frequency (it might 775 * increment only every few clock cycle). 776 */ 777 freq >>= 3 - ((rpm_config_reg & 778 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 779 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 780 } 781 782 return freq; 783 } 784 785 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); 786 return 0; 787 } 788 789 #undef INTEL_VGA_DEVICE 790 #define INTEL_VGA_DEVICE(id, info) (id) 791 792 static const u16 subplatform_ult_ids[] = { 793 INTEL_HSW_ULT_GT1_IDS(0), 794 INTEL_HSW_ULT_GT2_IDS(0), 795 INTEL_HSW_ULT_GT3_IDS(0), 796 INTEL_BDW_ULT_GT1_IDS(0), 797 INTEL_BDW_ULT_GT2_IDS(0), 798 INTEL_BDW_ULT_GT3_IDS(0), 799 INTEL_BDW_ULT_RSVD_IDS(0), 800 INTEL_SKL_ULT_GT1_IDS(0), 801 INTEL_SKL_ULT_GT2_IDS(0), 802 INTEL_SKL_ULT_GT3_IDS(0), 803 INTEL_KBL_ULT_GT1_IDS(0), 804 INTEL_KBL_ULT_GT2_IDS(0), 805 INTEL_KBL_ULT_GT3_IDS(0), 806 INTEL_CFL_U_GT2_IDS(0), 807 INTEL_CFL_U_GT3_IDS(0), 808 INTEL_WHL_U_GT1_IDS(0), 809 INTEL_WHL_U_GT2_IDS(0), 810 INTEL_WHL_U_GT3_IDS(0), 811 }; 812 813 static const u16 subplatform_ulx_ids[] = { 814 INTEL_HSW_ULX_GT1_IDS(0), 815 INTEL_HSW_ULX_GT2_IDS(0), 816 INTEL_BDW_ULX_GT1_IDS(0), 817 INTEL_BDW_ULX_GT2_IDS(0), 818 INTEL_BDW_ULX_GT3_IDS(0), 819 INTEL_BDW_ULX_RSVD_IDS(0), 820 INTEL_SKL_ULX_GT1_IDS(0), 821 INTEL_SKL_ULX_GT2_IDS(0), 822 INTEL_KBL_ULX_GT1_IDS(0), 823 INTEL_KBL_ULX_GT2_IDS(0), 824 INTEL_AML_KBL_GT2_IDS(0), 825 INTEL_AML_CFL_GT2_IDS(0), 826 }; 827 828 static const u16 subplatform_portf_ids[] = { 829 INTEL_CNL_PORT_F_IDS(0), 830 INTEL_ICL_PORT_F_IDS(0), 831 }; 832 833 static bool find_devid(u16 id, const u16 *p, unsigned int num) 834 { 835 for (; num; num--, p++) { 836 if (*p == id) 837 return true; 838 } 839 840 return false; 841 } 842 843 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 844 { 845 const struct intel_device_info *info = INTEL_INFO(i915); 846 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 847 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 848 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 849 u16 devid = INTEL_DEVID(i915); 850 u32 mask = 0; 851 852 /* Make sure IS_<platform> checks are working. */ 853 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 854 855 /* Find and mark subplatform bits based on the PCI device id. */ 856 if (find_devid(devid, subplatform_ult_ids, 857 ARRAY_SIZE(subplatform_ult_ids))) { 858 mask = BIT(INTEL_SUBPLATFORM_ULT); 859 } else if (find_devid(devid, subplatform_ulx_ids, 860 ARRAY_SIZE(subplatform_ulx_ids))) { 861 mask = BIT(INTEL_SUBPLATFORM_ULX); 862 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 863 /* ULX machines are also considered ULT. */ 864 mask |= BIT(INTEL_SUBPLATFORM_ULT); 865 } 866 } else if (find_devid(devid, subplatform_portf_ids, 867 ARRAY_SIZE(subplatform_portf_ids))) { 868 mask = BIT(INTEL_SUBPLATFORM_PORTF); 869 } 870 871 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); 872 873 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 874 } 875 876 /** 877 * intel_device_info_runtime_init - initialize runtime info 878 * @dev_priv: the i915 device 879 * 880 * Determine various intel_device_info fields at runtime. 881 * 882 * Use it when either: 883 * - it's judged too laborious to fill n static structures with the limit 884 * when a simple if statement does the job, 885 * - run-time checks (eg read fuse/strap registers) are needed. 886 * 887 * This function needs to be called: 888 * - after the MMIO has been setup as we are reading registers, 889 * - after the PCH has been detected, 890 * - before the first usage of the fields it can tweak. 891 */ 892 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 893 { 894 struct intel_device_info *info = mkwrite_device_info(dev_priv); 895 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 896 enum pipe pipe; 897 898 if (INTEL_GEN(dev_priv) >= 10) { 899 for_each_pipe(dev_priv, pipe) 900 runtime->num_scalers[pipe] = 2; 901 } else if (IS_GEN(dev_priv, 9)) { 902 runtime->num_scalers[PIPE_A] = 2; 903 runtime->num_scalers[PIPE_B] = 2; 904 runtime->num_scalers[PIPE_C] = 1; 905 } 906 907 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 908 909 if (INTEL_GEN(dev_priv) >= 11) 910 for_each_pipe(dev_priv, pipe) 911 runtime->num_sprites[pipe] = 6; 912 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) 913 for_each_pipe(dev_priv, pipe) 914 runtime->num_sprites[pipe] = 3; 915 else if (IS_BROXTON(dev_priv)) { 916 /* 917 * Skylake and Broxton currently don't expose the topmost plane as its 918 * use is exclusive with the legacy cursor and we only want to expose 919 * one of those, not both. Until we can safely expose the topmost plane 920 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 921 * we don't expose the topmost plane at all to prevent ABI breakage 922 * down the line. 923 */ 924 925 runtime->num_sprites[PIPE_A] = 2; 926 runtime->num_sprites[PIPE_B] = 2; 927 runtime->num_sprites[PIPE_C] = 1; 928 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 929 for_each_pipe(dev_priv, pipe) 930 runtime->num_sprites[pipe] = 2; 931 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 932 for_each_pipe(dev_priv, pipe) 933 runtime->num_sprites[pipe] = 1; 934 } 935 936 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && 937 HAS_PCH_SPLIT(dev_priv)) { 938 u32 fuse_strap = I915_READ(FUSE_STRAP); 939 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 940 941 /* 942 * SFUSE_STRAP is supposed to have a bit signalling the display 943 * is fused off. Unfortunately it seems that, at least in 944 * certain cases, fused off display means that PCH display 945 * reads don't land anywhere. In that case, we read 0s. 946 * 947 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 948 * should be set when taking over after the firmware. 949 */ 950 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 951 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 952 (HAS_PCH_CPT(dev_priv) && 953 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 954 DRM_INFO("Display fused off, disabling\n"); 955 info->pipe_mask = 0; 956 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 957 DRM_INFO("PipeC fused off\n"); 958 info->pipe_mask &= ~BIT(PIPE_C); 959 } 960 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { 961 u32 dfsm = I915_READ(SKL_DFSM); 962 u8 enabled_mask = info->pipe_mask; 963 964 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) 965 enabled_mask &= ~BIT(PIPE_A); 966 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) 967 enabled_mask &= ~BIT(PIPE_B); 968 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) 969 enabled_mask &= ~BIT(PIPE_C); 970 if (INTEL_GEN(dev_priv) >= 12 && 971 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) 972 enabled_mask &= ~BIT(PIPE_D); 973 974 /* 975 * At least one pipe should be enabled and if there are 976 * disabled pipes, they should be the last ones, with no holes 977 * in the mask. 978 */ 979 if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1)) 980 DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n", 981 enabled_mask); 982 else 983 info->pipe_mask = enabled_mask; 984 985 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 986 info->display.has_hdcp = 0; 987 988 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 989 info->display.has_fbc = 0; 990 991 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 992 info->display.has_csr = 0; 993 994 if (INTEL_GEN(dev_priv) >= 10 && 995 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 996 info->display.has_dsc = 0; 997 } 998 999 /* Initialize slice/subslice/EU info */ 1000 if (IS_HASWELL(dev_priv)) 1001 haswell_sseu_info_init(dev_priv); 1002 else if (IS_CHERRYVIEW(dev_priv)) 1003 cherryview_sseu_info_init(dev_priv); 1004 else if (IS_BROADWELL(dev_priv)) 1005 broadwell_sseu_info_init(dev_priv); 1006 else if (IS_GEN(dev_priv, 9)) 1007 gen9_sseu_info_init(dev_priv); 1008 else if (IS_GEN(dev_priv, 10)) 1009 gen10_sseu_info_init(dev_priv); 1010 else if (IS_GEN(dev_priv, 11)) 1011 gen11_sseu_info_init(dev_priv); 1012 else if (INTEL_GEN(dev_priv) >= 12) 1013 gen12_sseu_info_init(dev_priv); 1014 1015 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { 1016 DRM_INFO("Disabling ppGTT for VT-d support\n"); 1017 info->ppgtt_type = INTEL_PPGTT_NONE; 1018 } 1019 1020 /* Initialize command stream timestamp frequency */ 1021 runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); 1022 } 1023 1024 void intel_driver_caps_print(const struct intel_driver_caps *caps, 1025 struct drm_printer *p) 1026 { 1027 drm_printf(p, "Has logical contexts? %s\n", 1028 yesno(caps->has_logical_contexts)); 1029 drm_printf(p, "scheduler: %x\n", caps->scheduler); 1030 } 1031 1032 /* 1033 * Determine which engines are fused off in our particular hardware. Since the 1034 * fuse register is in the blitter powerwell, we need forcewake to be ready at 1035 * this point (but later we need to prune the forcewake domains for engines that 1036 * are indeed fused off). 1037 */ 1038 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 1039 { 1040 struct intel_device_info *info = mkwrite_device_info(dev_priv); 1041 unsigned int logical_vdbox = 0; 1042 unsigned int i; 1043 u32 media_fuse; 1044 u16 vdbox_mask; 1045 u16 vebox_mask; 1046 1047 if (INTEL_GEN(dev_priv) < 11) 1048 return; 1049 1050 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); 1051 1052 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 1053 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 1054 GEN11_GT_VEBOX_DISABLE_SHIFT; 1055 1056 for (i = 0; i < I915_MAX_VCS; i++) { 1057 if (!HAS_ENGINE(dev_priv, _VCS(i))) { 1058 vdbox_mask &= ~BIT(i); 1059 continue; 1060 } 1061 1062 if (!(BIT(i) & vdbox_mask)) { 1063 info->engine_mask &= ~BIT(_VCS(i)); 1064 DRM_DEBUG_DRIVER("vcs%u fused off\n", i); 1065 continue; 1066 } 1067 1068 /* 1069 * In Gen11, only even numbered logical VDBOXes are 1070 * hooked up to an SFC (Scaler & Format Converter) unit. 1071 * In TGL each VDBOX has access to an SFC. 1072 */ 1073 if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0) 1074 RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); 1075 } 1076 DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n", 1077 vdbox_mask, VDBOX_MASK(dev_priv)); 1078 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); 1079 1080 for (i = 0; i < I915_MAX_VECS; i++) { 1081 if (!HAS_ENGINE(dev_priv, _VECS(i))) { 1082 vebox_mask &= ~BIT(i); 1083 continue; 1084 } 1085 1086 if (!(BIT(i) & vebox_mask)) { 1087 info->engine_mask &= ~BIT(_VECS(i)); 1088 DRM_DEBUG_DRIVER("vecs%u fused off\n", i); 1089 } 1090 } 1091 DRM_DEBUG_DRIVER("vebox enable: %04x, instances: %04lx\n", 1092 vebox_mask, VEBOX_MASK(dev_priv)); 1093 GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); 1094 } 1095