1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <drm/drm_print.h>
26 
27 #include "intel_device_info.h"
28 #include "i915_drv.h"
29 
30 #define PLATFORM_NAME(x) [INTEL_##x] = #x
31 static const char * const platform_names[] = {
32 	PLATFORM_NAME(I830),
33 	PLATFORM_NAME(I845G),
34 	PLATFORM_NAME(I85X),
35 	PLATFORM_NAME(I865G),
36 	PLATFORM_NAME(I915G),
37 	PLATFORM_NAME(I915GM),
38 	PLATFORM_NAME(I945G),
39 	PLATFORM_NAME(I945GM),
40 	PLATFORM_NAME(G33),
41 	PLATFORM_NAME(PINEVIEW),
42 	PLATFORM_NAME(I965G),
43 	PLATFORM_NAME(I965GM),
44 	PLATFORM_NAME(G45),
45 	PLATFORM_NAME(GM45),
46 	PLATFORM_NAME(IRONLAKE),
47 	PLATFORM_NAME(SANDYBRIDGE),
48 	PLATFORM_NAME(IVYBRIDGE),
49 	PLATFORM_NAME(VALLEYVIEW),
50 	PLATFORM_NAME(HASWELL),
51 	PLATFORM_NAME(BROADWELL),
52 	PLATFORM_NAME(CHERRYVIEW),
53 	PLATFORM_NAME(SKYLAKE),
54 	PLATFORM_NAME(BROXTON),
55 	PLATFORM_NAME(KABYLAKE),
56 	PLATFORM_NAME(GEMINILAKE),
57 	PLATFORM_NAME(COFFEELAKE),
58 	PLATFORM_NAME(CANNONLAKE),
59 	PLATFORM_NAME(ICELAKE),
60 	PLATFORM_NAME(ELKHARTLAKE),
61 };
62 #undef PLATFORM_NAME
63 
64 const char *intel_platform_name(enum intel_platform platform)
65 {
66 	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
67 
68 	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
69 			 platform_names[platform] == NULL))
70 		return "<unknown>";
71 
72 	return platform_names[platform];
73 }
74 
75 void intel_device_info_dump_flags(const struct intel_device_info *info,
76 				  struct drm_printer *p)
77 {
78 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
79 	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
80 #undef PRINT_FLAG
81 
82 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
83 	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
84 #undef PRINT_FLAG
85 }
86 
87 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
88 {
89 	int s;
90 
91 	drm_printf(p, "slice total: %u, mask=%04x\n",
92 		   hweight8(sseu->slice_mask), sseu->slice_mask);
93 	drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
94 	for (s = 0; s < sseu->max_slices; s++) {
95 		drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
96 			   s, hweight8(sseu->subslice_mask[s]),
97 			   sseu->subslice_mask[s]);
98 	}
99 	drm_printf(p, "EU total: %u\n", sseu->eu_total);
100 	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
101 	drm_printf(p, "has slice power gating: %s\n",
102 		   yesno(sseu->has_slice_pg));
103 	drm_printf(p, "has subslice power gating: %s\n",
104 		   yesno(sseu->has_subslice_pg));
105 	drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
106 }
107 
108 void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
109 				    struct drm_printer *p)
110 {
111 	sseu_dump(&info->sseu, p);
112 
113 	drm_printf(p, "CS timestamp frequency: %u kHz\n",
114 		   info->cs_timestamp_frequency_khz);
115 }
116 
117 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
118 				     struct drm_printer *p)
119 {
120 	int s, ss;
121 
122 	if (sseu->max_slices == 0) {
123 		drm_printf(p, "Unavailable\n");
124 		return;
125 	}
126 
127 	for (s = 0; s < sseu->max_slices; s++) {
128 		drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
129 			   s, hweight8(sseu->subslice_mask[s]),
130 			   sseu->subslice_mask[s]);
131 
132 		for (ss = 0; ss < sseu->max_subslices; ss++) {
133 			u16 enabled_eus = sseu_get_eus(sseu, s, ss);
134 
135 			drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
136 				   ss, hweight16(enabled_eus), enabled_eus);
137 		}
138 	}
139 }
140 
141 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
142 {
143 	u16 i, total = 0;
144 
145 	for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
146 		total += hweight8(sseu->eu_mask[i]);
147 
148 	return total;
149 }
150 
151 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
152 {
153 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
154 	u8 s_en;
155 	u32 ss_en, ss_en_mask;
156 	u8 eu_en;
157 	int s;
158 
159 	if (IS_ELKHARTLAKE(dev_priv)) {
160 		sseu->max_slices = 1;
161 		sseu->max_subslices = 4;
162 		sseu->max_eus_per_subslice = 8;
163 	} else {
164 		sseu->max_slices = 1;
165 		sseu->max_subslices = 8;
166 		sseu->max_eus_per_subslice = 8;
167 	}
168 
169 	s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
170 	ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
171 	ss_en_mask = BIT(sseu->max_subslices) - 1;
172 	eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
173 
174 	for (s = 0; s < sseu->max_slices; s++) {
175 		if (s_en & BIT(s)) {
176 			int ss_idx = sseu->max_subslices * s;
177 			int ss;
178 
179 			sseu->slice_mask |= BIT(s);
180 			sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
181 			for (ss = 0; ss < sseu->max_subslices; ss++) {
182 				if (sseu->subslice_mask[s] & BIT(ss))
183 					sseu_set_eus(sseu, s, ss, eu_en);
184 			}
185 		}
186 	}
187 	sseu->eu_per_subslice = hweight8(eu_en);
188 	sseu->eu_total = compute_eu_total(sseu);
189 
190 	/* ICL has no power gating restrictions. */
191 	sseu->has_slice_pg = 1;
192 	sseu->has_subslice_pg = 1;
193 	sseu->has_eu_pg = 1;
194 }
195 
196 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
197 {
198 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
199 	const u32 fuse2 = I915_READ(GEN8_FUSE2);
200 	int s, ss;
201 	const int eu_mask = 0xff;
202 	u32 subslice_mask, eu_en;
203 
204 	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
205 			    GEN10_F2_S_ENA_SHIFT;
206 	sseu->max_slices = 6;
207 	sseu->max_subslices = 4;
208 	sseu->max_eus_per_subslice = 8;
209 
210 	subslice_mask = (1 << 4) - 1;
211 	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
212 			   GEN10_F2_SS_DIS_SHIFT);
213 
214 	/*
215 	 * Slice0 can have up to 3 subslices, but there are only 2 in
216 	 * slice1/2.
217 	 */
218 	sseu->subslice_mask[0] = subslice_mask;
219 	for (s = 1; s < sseu->max_slices; s++)
220 		sseu->subslice_mask[s] = subslice_mask & 0x3;
221 
222 	/* Slice0 */
223 	eu_en = ~I915_READ(GEN8_EU_DISABLE0);
224 	for (ss = 0; ss < sseu->max_subslices; ss++)
225 		sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
226 	/* Slice1 */
227 	sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
228 	eu_en = ~I915_READ(GEN8_EU_DISABLE1);
229 	sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
230 	/* Slice2 */
231 	sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
232 	sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
233 	/* Slice3 */
234 	sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
235 	eu_en = ~I915_READ(GEN8_EU_DISABLE2);
236 	sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
237 	/* Slice4 */
238 	sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
239 	sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
240 	/* Slice5 */
241 	sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
242 	eu_en = ~I915_READ(GEN10_EU_DISABLE3);
243 	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
244 
245 	/* Do a second pass where we mark the subslices disabled if all their
246 	 * eus are off.
247 	 */
248 	for (s = 0; s < sseu->max_slices; s++) {
249 		for (ss = 0; ss < sseu->max_subslices; ss++) {
250 			if (sseu_get_eus(sseu, s, ss) == 0)
251 				sseu->subslice_mask[s] &= ~BIT(ss);
252 		}
253 	}
254 
255 	sseu->eu_total = compute_eu_total(sseu);
256 
257 	/*
258 	 * CNL is expected to always have a uniform distribution
259 	 * of EU across subslices with the exception that any one
260 	 * EU in any one subslice may be fused off for die
261 	 * recovery.
262 	 */
263 	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
264 				DIV_ROUND_UP(sseu->eu_total,
265 					     sseu_subslice_total(sseu)) : 0;
266 
267 	/* No restrictions on Power Gating */
268 	sseu->has_slice_pg = 1;
269 	sseu->has_subslice_pg = 1;
270 	sseu->has_eu_pg = 1;
271 }
272 
273 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
274 {
275 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
276 	u32 fuse;
277 
278 	fuse = I915_READ(CHV_FUSE_GT);
279 
280 	sseu->slice_mask = BIT(0);
281 	sseu->max_slices = 1;
282 	sseu->max_subslices = 2;
283 	sseu->max_eus_per_subslice = 8;
284 
285 	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
286 		u8 disabled_mask =
287 			((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
288 			 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
289 			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
290 			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
291 
292 		sseu->subslice_mask[0] |= BIT(0);
293 		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
294 	}
295 
296 	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
297 		u8 disabled_mask =
298 			((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
299 			 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
300 			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
301 			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
302 
303 		sseu->subslice_mask[0] |= BIT(1);
304 		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
305 	}
306 
307 	sseu->eu_total = compute_eu_total(sseu);
308 
309 	/*
310 	 * CHV expected to always have a uniform distribution of EU
311 	 * across subslices.
312 	*/
313 	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
314 				sseu->eu_total / sseu_subslice_total(sseu) :
315 				0;
316 	/*
317 	 * CHV supports subslice power gating on devices with more than
318 	 * one subslice, and supports EU power gating on devices with
319 	 * more than one EU pair per subslice.
320 	*/
321 	sseu->has_slice_pg = 0;
322 	sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
323 	sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
324 }
325 
326 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
327 {
328 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
329 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
330 	int s, ss;
331 	u32 fuse2, eu_disable, subslice_mask;
332 	const u8 eu_mask = 0xff;
333 
334 	fuse2 = I915_READ(GEN8_FUSE2);
335 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
336 
337 	/* BXT has a single slice and at most 3 subslices. */
338 	sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
339 	sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
340 	sseu->max_eus_per_subslice = 8;
341 
342 	/*
343 	 * The subslice disable field is global, i.e. it applies
344 	 * to each of the enabled slices.
345 	*/
346 	subslice_mask = (1 << sseu->max_subslices) - 1;
347 	subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
348 			   GEN9_F2_SS_DIS_SHIFT);
349 
350 	/*
351 	 * Iterate through enabled slices and subslices to
352 	 * count the total enabled EU.
353 	*/
354 	for (s = 0; s < sseu->max_slices; s++) {
355 		if (!(sseu->slice_mask & BIT(s)))
356 			/* skip disabled slice */
357 			continue;
358 
359 		sseu->subslice_mask[s] = subslice_mask;
360 
361 		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
362 		for (ss = 0; ss < sseu->max_subslices; ss++) {
363 			int eu_per_ss;
364 			u8 eu_disabled_mask;
365 
366 			if (!(sseu->subslice_mask[s] & BIT(ss)))
367 				/* skip disabled subslice */
368 				continue;
369 
370 			eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
371 
372 			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
373 
374 			eu_per_ss = sseu->max_eus_per_subslice -
375 				hweight8(eu_disabled_mask);
376 
377 			/*
378 			 * Record which subslice(s) has(have) 7 EUs. we
379 			 * can tune the hash used to spread work among
380 			 * subslices if they are unbalanced.
381 			 */
382 			if (eu_per_ss == 7)
383 				sseu->subslice_7eu[s] |= BIT(ss);
384 		}
385 	}
386 
387 	sseu->eu_total = compute_eu_total(sseu);
388 
389 	/*
390 	 * SKL is expected to always have a uniform distribution
391 	 * of EU across subslices with the exception that any one
392 	 * EU in any one subslice may be fused off for die
393 	 * recovery. BXT is expected to be perfectly uniform in EU
394 	 * distribution.
395 	*/
396 	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
397 				DIV_ROUND_UP(sseu->eu_total,
398 					     sseu_subslice_total(sseu)) : 0;
399 	/*
400 	 * SKL+ supports slice power gating on devices with more than
401 	 * one slice, and supports EU power gating on devices with
402 	 * more than one EU pair per subslice. BXT+ supports subslice
403 	 * power gating on devices with more than one subslice, and
404 	 * supports EU power gating on devices with more than one EU
405 	 * pair per subslice.
406 	*/
407 	sseu->has_slice_pg =
408 		!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
409 	sseu->has_subslice_pg =
410 		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
411 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
412 
413 	if (IS_GEN9_LP(dev_priv)) {
414 #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask[0] & BIT(ss)))
415 		info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
416 
417 		sseu->min_eu_in_pool = 0;
418 		if (info->has_pooled_eu) {
419 			if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
420 				sseu->min_eu_in_pool = 3;
421 			else if (IS_SS_DISABLED(1))
422 				sseu->min_eu_in_pool = 6;
423 			else
424 				sseu->min_eu_in_pool = 9;
425 		}
426 #undef IS_SS_DISABLED
427 	}
428 }
429 
430 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
431 {
432 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
433 	int s, ss;
434 	u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
435 
436 	fuse2 = I915_READ(GEN8_FUSE2);
437 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
438 	sseu->max_slices = 3;
439 	sseu->max_subslices = 3;
440 	sseu->max_eus_per_subslice = 8;
441 
442 	/*
443 	 * The subslice disable field is global, i.e. it applies
444 	 * to each of the enabled slices.
445 	 */
446 	subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
447 	subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
448 			   GEN8_F2_SS_DIS_SHIFT);
449 
450 	eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
451 	eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
452 			((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
453 			 (32 - GEN8_EU_DIS0_S1_SHIFT));
454 	eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
455 			((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
456 			 (32 - GEN8_EU_DIS1_S2_SHIFT));
457 
458 	/*
459 	 * Iterate through enabled slices and subslices to
460 	 * count the total enabled EU.
461 	 */
462 	for (s = 0; s < sseu->max_slices; s++) {
463 		if (!(sseu->slice_mask & BIT(s)))
464 			/* skip disabled slice */
465 			continue;
466 
467 		sseu->subslice_mask[s] = subslice_mask;
468 
469 		for (ss = 0; ss < sseu->max_subslices; ss++) {
470 			u8 eu_disabled_mask;
471 			u32 n_disabled;
472 
473 			if (!(sseu->subslice_mask[s] & BIT(ss)))
474 				/* skip disabled subslice */
475 				continue;
476 
477 			eu_disabled_mask =
478 				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
479 
480 			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
481 
482 			n_disabled = hweight8(eu_disabled_mask);
483 
484 			/*
485 			 * Record which subslices have 7 EUs.
486 			 */
487 			if (sseu->max_eus_per_subslice - n_disabled == 7)
488 				sseu->subslice_7eu[s] |= 1 << ss;
489 		}
490 	}
491 
492 	sseu->eu_total = compute_eu_total(sseu);
493 
494 	/*
495 	 * BDW is expected to always have a uniform distribution of EU across
496 	 * subslices with the exception that any one EU in any one subslice may
497 	 * be fused off for die recovery.
498 	 */
499 	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
500 				DIV_ROUND_UP(sseu->eu_total,
501 					     sseu_subslice_total(sseu)) : 0;
502 
503 	/*
504 	 * BDW supports slice power gating on devices with more than
505 	 * one slice.
506 	 */
507 	sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
508 	sseu->has_subslice_pg = 0;
509 	sseu->has_eu_pg = 0;
510 }
511 
512 static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
513 {
514 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
515 	u32 fuse1;
516 	int s, ss;
517 
518 	/*
519 	 * There isn't a register to tell us how many slices/subslices. We
520 	 * work off the PCI-ids here.
521 	 */
522 	switch (INTEL_INFO(dev_priv)->gt) {
523 	default:
524 		MISSING_CASE(INTEL_INFO(dev_priv)->gt);
525 		/* fall through */
526 	case 1:
527 		sseu->slice_mask = BIT(0);
528 		sseu->subslice_mask[0] = BIT(0);
529 		break;
530 	case 2:
531 		sseu->slice_mask = BIT(0);
532 		sseu->subslice_mask[0] = BIT(0) | BIT(1);
533 		break;
534 	case 3:
535 		sseu->slice_mask = BIT(0) | BIT(1);
536 		sseu->subslice_mask[0] = BIT(0) | BIT(1);
537 		sseu->subslice_mask[1] = BIT(0) | BIT(1);
538 		break;
539 	}
540 
541 	sseu->max_slices = hweight8(sseu->slice_mask);
542 	sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
543 
544 	fuse1 = I915_READ(HSW_PAVP_FUSE1);
545 	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
546 	default:
547 		MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
548 			     HSW_F1_EU_DIS_SHIFT);
549 		/* fall through */
550 	case HSW_F1_EU_DIS_10EUS:
551 		sseu->eu_per_subslice = 10;
552 		break;
553 	case HSW_F1_EU_DIS_8EUS:
554 		sseu->eu_per_subslice = 8;
555 		break;
556 	case HSW_F1_EU_DIS_6EUS:
557 		sseu->eu_per_subslice = 6;
558 		break;
559 	}
560 	sseu->max_eus_per_subslice = sseu->eu_per_subslice;
561 
562 	for (s = 0; s < sseu->max_slices; s++) {
563 		for (ss = 0; ss < sseu->max_subslices; ss++) {
564 			sseu_set_eus(sseu, s, ss,
565 				     (1UL << sseu->eu_per_subslice) - 1);
566 		}
567 	}
568 
569 	sseu->eu_total = compute_eu_total(sseu);
570 
571 	/* No powergating for you. */
572 	sseu->has_slice_pg = 0;
573 	sseu->has_subslice_pg = 0;
574 	sseu->has_eu_pg = 0;
575 }
576 
577 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
578 {
579 	u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
580 	u32 base_freq, frac_freq;
581 
582 	base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
583 		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
584 	base_freq *= 1000;
585 
586 	frac_freq = ((ts_override &
587 		      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
588 		     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
589 	frac_freq = 1000 / (frac_freq + 1);
590 
591 	return base_freq + frac_freq;
592 }
593 
594 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
595 					u32 rpm_config_reg)
596 {
597 	u32 f19_2_mhz = 19200;
598 	u32 f24_mhz = 24000;
599 	u32 crystal_clock = (rpm_config_reg &
600 			     GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
601 			    GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
602 
603 	switch (crystal_clock) {
604 	case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
605 		return f19_2_mhz;
606 	case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
607 		return f24_mhz;
608 	default:
609 		MISSING_CASE(crystal_clock);
610 		return 0;
611 	}
612 }
613 
614 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
615 					u32 rpm_config_reg)
616 {
617 	u32 f19_2_mhz = 19200;
618 	u32 f24_mhz = 24000;
619 	u32 f25_mhz = 25000;
620 	u32 f38_4_mhz = 38400;
621 	u32 crystal_clock = (rpm_config_reg &
622 			     GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
623 			    GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
624 
625 	switch (crystal_clock) {
626 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
627 		return f24_mhz;
628 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
629 		return f19_2_mhz;
630 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
631 		return f38_4_mhz;
632 	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
633 		return f25_mhz;
634 	default:
635 		MISSING_CASE(crystal_clock);
636 		return 0;
637 	}
638 }
639 
640 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
641 {
642 	u32 f12_5_mhz = 12500;
643 	u32 f19_2_mhz = 19200;
644 	u32 f24_mhz = 24000;
645 
646 	if (INTEL_GEN(dev_priv) <= 4) {
647 		/* PRMs say:
648 		 *
649 		 *     "The value in this register increments once every 16
650 		 *      hclks." (through the “Clocking Configuration”
651 		 *      (“CLKCFG”) MCHBAR register)
652 		 */
653 		return dev_priv->rawclk_freq / 16;
654 	} else if (INTEL_GEN(dev_priv) <= 8) {
655 		/* PRMs say:
656 		 *
657 		 *     "The PCU TSC counts 10ns increments; this timestamp
658 		 *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
659 		 *      rolling over every 1.5 hours).
660 		 */
661 		return f12_5_mhz;
662 	} else if (INTEL_GEN(dev_priv) <= 9) {
663 		u32 ctc_reg = I915_READ(CTC_MODE);
664 		u32 freq = 0;
665 
666 		if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
667 			freq = read_reference_ts_freq(dev_priv);
668 		} else {
669 			freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
670 
671 			/* Now figure out how the command stream's timestamp
672 			 * register increments from this frequency (it might
673 			 * increment only every few clock cycle).
674 			 */
675 			freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
676 				      CTC_SHIFT_PARAMETER_SHIFT);
677 		}
678 
679 		return freq;
680 	} else if (INTEL_GEN(dev_priv) <= 11) {
681 		u32 ctc_reg = I915_READ(CTC_MODE);
682 		u32 freq = 0;
683 
684 		/* First figure out the reference frequency. There are 2 ways
685 		 * we can compute the frequency, either through the
686 		 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
687 		 * tells us which one we should use.
688 		 */
689 		if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
690 			freq = read_reference_ts_freq(dev_priv);
691 		} else {
692 			u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
693 
694 			if (INTEL_GEN(dev_priv) <= 10)
695 				freq = gen10_get_crystal_clock_freq(dev_priv,
696 								rpm_config_reg);
697 			else
698 				freq = gen11_get_crystal_clock_freq(dev_priv,
699 								rpm_config_reg);
700 
701 			/* Now figure out how the command stream's timestamp
702 			 * register increments from this frequency (it might
703 			 * increment only every few clock cycle).
704 			 */
705 			freq >>= 3 - ((rpm_config_reg &
706 				       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
707 				      GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
708 		}
709 
710 		return freq;
711 	}
712 
713 	MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
714 	return 0;
715 }
716 
717 #undef INTEL_VGA_DEVICE
718 #define INTEL_VGA_DEVICE(id, info) (id)
719 
720 static const u16 subplatform_ult_ids[] = {
721 	INTEL_HSW_ULT_GT1_IDS(0),
722 	INTEL_HSW_ULT_GT2_IDS(0),
723 	INTEL_HSW_ULT_GT3_IDS(0),
724 	INTEL_BDW_ULT_GT1_IDS(0),
725 	INTEL_BDW_ULT_GT2_IDS(0),
726 	INTEL_BDW_ULT_GT3_IDS(0),
727 	INTEL_BDW_ULT_RSVD_IDS(0),
728 	INTEL_SKL_ULT_GT1_IDS(0),
729 	INTEL_SKL_ULT_GT2_IDS(0),
730 	INTEL_SKL_ULT_GT3_IDS(0),
731 	INTEL_KBL_ULT_GT1_IDS(0),
732 	INTEL_KBL_ULT_GT2_IDS(0),
733 	INTEL_KBL_ULT_GT3_IDS(0),
734 	INTEL_CFL_U_GT2_IDS(0),
735 	INTEL_CFL_U_GT3_IDS(0),
736 	INTEL_WHL_U_GT1_IDS(0),
737 	INTEL_WHL_U_GT2_IDS(0),
738 	INTEL_WHL_U_GT3_IDS(0)
739 };
740 
741 static const u16 subplatform_ulx_ids[] = {
742 	INTEL_HSW_ULX_GT1_IDS(0),
743 	INTEL_HSW_ULX_GT2_IDS(0),
744 	INTEL_BDW_ULX_GT1_IDS(0),
745 	INTEL_BDW_ULX_GT2_IDS(0),
746 	INTEL_BDW_ULX_GT3_IDS(0),
747 	INTEL_BDW_ULX_RSVD_IDS(0),
748 	INTEL_SKL_ULX_GT1_IDS(0),
749 	INTEL_SKL_ULX_GT2_IDS(0),
750 	INTEL_KBL_ULX_GT1_IDS(0),
751 	INTEL_KBL_ULX_GT2_IDS(0)
752 };
753 
754 static const u16 subplatform_aml_ids[] = {
755 	INTEL_AML_KBL_GT2_IDS(0),
756 	INTEL_AML_CFL_GT2_IDS(0)
757 };
758 
759 static const u16 subplatform_portf_ids[] = {
760 	INTEL_CNL_PORT_F_IDS(0),
761 	INTEL_ICL_PORT_F_IDS(0)
762 };
763 
764 static bool find_devid(u16 id, const u16 *p, unsigned int num)
765 {
766 	for (; num; num--, p++) {
767 		if (*p == id)
768 			return true;
769 	}
770 
771 	return false;
772 }
773 
774 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
775 {
776 	const struct intel_device_info *info = INTEL_INFO(i915);
777 	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
778 	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
779 	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
780 	u16 devid = INTEL_DEVID(i915);
781 	u32 mask = 0;
782 
783 	/* Make sure IS_<platform> checks are working. */
784 	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
785 
786 	/* Find and mark subplatform bits based on the PCI device id. */
787 	if (find_devid(devid, subplatform_ult_ids,
788 		       ARRAY_SIZE(subplatform_ult_ids))) {
789 		mask = BIT(INTEL_SUBPLATFORM_ULT);
790 	} else if (find_devid(devid, subplatform_ulx_ids,
791 			      ARRAY_SIZE(subplatform_ulx_ids))) {
792 		mask = BIT(INTEL_SUBPLATFORM_ULX);
793 		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
794 			/* ULX machines are also considered ULT. */
795 			mask |= BIT(INTEL_SUBPLATFORM_ULT);
796 		}
797 	} else if (find_devid(devid, subplatform_aml_ids,
798 			      ARRAY_SIZE(subplatform_aml_ids))) {
799 		mask = BIT(INTEL_SUBPLATFORM_AML);
800 	} else if (find_devid(devid, subplatform_portf_ids,
801 			      ARRAY_SIZE(subplatform_portf_ids))) {
802 		mask = BIT(INTEL_SUBPLATFORM_PORTF);
803 	}
804 
805 	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
806 
807 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
808 }
809 
810 /**
811  * intel_device_info_runtime_init - initialize runtime info
812  * @dev_priv: the i915 device
813  *
814  * Determine various intel_device_info fields at runtime.
815  *
816  * Use it when either:
817  *   - it's judged too laborious to fill n static structures with the limit
818  *     when a simple if statement does the job,
819  *   - run-time checks (eg read fuse/strap registers) are needed.
820  *
821  * This function needs to be called:
822  *   - after the MMIO has been setup as we are reading registers,
823  *   - after the PCH has been detected,
824  *   - before the first usage of the fields it can tweak.
825  */
826 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
827 {
828 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
829 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
830 	enum pipe pipe;
831 
832 	if (INTEL_GEN(dev_priv) >= 10) {
833 		for_each_pipe(dev_priv, pipe)
834 			runtime->num_scalers[pipe] = 2;
835 	} else if (IS_GEN(dev_priv, 9)) {
836 		runtime->num_scalers[PIPE_A] = 2;
837 		runtime->num_scalers[PIPE_B] = 2;
838 		runtime->num_scalers[PIPE_C] = 1;
839 	}
840 
841 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
842 
843 	if (INTEL_GEN(dev_priv) >= 11)
844 		for_each_pipe(dev_priv, pipe)
845 			runtime->num_sprites[pipe] = 6;
846 	else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
847 		for_each_pipe(dev_priv, pipe)
848 			runtime->num_sprites[pipe] = 3;
849 	else if (IS_BROXTON(dev_priv)) {
850 		/*
851 		 * Skylake and Broxton currently don't expose the topmost plane as its
852 		 * use is exclusive with the legacy cursor and we only want to expose
853 		 * one of those, not both. Until we can safely expose the topmost plane
854 		 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
855 		 * we don't expose the topmost plane at all to prevent ABI breakage
856 		 * down the line.
857 		 */
858 
859 		runtime->num_sprites[PIPE_A] = 2;
860 		runtime->num_sprites[PIPE_B] = 2;
861 		runtime->num_sprites[PIPE_C] = 1;
862 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
863 		for_each_pipe(dev_priv, pipe)
864 			runtime->num_sprites[pipe] = 2;
865 	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
866 		for_each_pipe(dev_priv, pipe)
867 			runtime->num_sprites[pipe] = 1;
868 	}
869 
870 	if (i915_modparams.disable_display) {
871 		DRM_INFO("Display disabled (module parameter)\n");
872 		info->num_pipes = 0;
873 	} else if (HAS_DISPLAY(dev_priv) &&
874 		   (IS_GEN_RANGE(dev_priv, 7, 8)) &&
875 		   HAS_PCH_SPLIT(dev_priv)) {
876 		u32 fuse_strap = I915_READ(FUSE_STRAP);
877 		u32 sfuse_strap = I915_READ(SFUSE_STRAP);
878 
879 		/*
880 		 * SFUSE_STRAP is supposed to have a bit signalling the display
881 		 * is fused off. Unfortunately it seems that, at least in
882 		 * certain cases, fused off display means that PCH display
883 		 * reads don't land anywhere. In that case, we read 0s.
884 		 *
885 		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
886 		 * should be set when taking over after the firmware.
887 		 */
888 		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
889 		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
890 		    (HAS_PCH_CPT(dev_priv) &&
891 		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
892 			DRM_INFO("Display fused off, disabling\n");
893 			info->num_pipes = 0;
894 		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
895 			DRM_INFO("PipeC fused off\n");
896 			info->num_pipes -= 1;
897 		}
898 	} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
899 		u32 dfsm = I915_READ(SKL_DFSM);
900 		u8 disabled_mask = 0;
901 		bool invalid;
902 		int num_bits;
903 
904 		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
905 			disabled_mask |= BIT(PIPE_A);
906 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
907 			disabled_mask |= BIT(PIPE_B);
908 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
909 			disabled_mask |= BIT(PIPE_C);
910 
911 		num_bits = hweight8(disabled_mask);
912 
913 		switch (disabled_mask) {
914 		case BIT(PIPE_A):
915 		case BIT(PIPE_B):
916 		case BIT(PIPE_A) | BIT(PIPE_B):
917 		case BIT(PIPE_A) | BIT(PIPE_C):
918 			invalid = true;
919 			break;
920 		default:
921 			invalid = false;
922 		}
923 
924 		if (num_bits > info->num_pipes || invalid)
925 			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
926 				  disabled_mask);
927 		else
928 			info->num_pipes -= num_bits;
929 	}
930 
931 	/* Initialize slice/subslice/EU info */
932 	if (IS_HASWELL(dev_priv))
933 		haswell_sseu_info_init(dev_priv);
934 	else if (IS_CHERRYVIEW(dev_priv))
935 		cherryview_sseu_info_init(dev_priv);
936 	else if (IS_BROADWELL(dev_priv))
937 		broadwell_sseu_info_init(dev_priv);
938 	else if (IS_GEN(dev_priv, 9))
939 		gen9_sseu_info_init(dev_priv);
940 	else if (IS_GEN(dev_priv, 10))
941 		gen10_sseu_info_init(dev_priv);
942 	else if (INTEL_GEN(dev_priv) >= 11)
943 		gen11_sseu_info_init(dev_priv);
944 
945 	if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
946 		DRM_INFO("Disabling ppGTT for VT-d support\n");
947 		info->ppgtt_type = INTEL_PPGTT_NONE;
948 	}
949 
950 	/* Initialize command stream timestamp frequency */
951 	runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
952 }
953 
954 void intel_driver_caps_print(const struct intel_driver_caps *caps,
955 			     struct drm_printer *p)
956 {
957 	drm_printf(p, "Has logical contexts? %s\n",
958 		   yesno(caps->has_logical_contexts));
959 	drm_printf(p, "scheduler: %x\n", caps->scheduler);
960 }
961 
962 /*
963  * Determine which engines are fused off in our particular hardware. Since the
964  * fuse register is in the blitter powerwell, we need forcewake to be ready at
965  * this point (but later we need to prune the forcewake domains for engines that
966  * are indeed fused off).
967  */
968 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
969 {
970 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
971 	unsigned int logical_vdbox = 0;
972 	unsigned int i;
973 	u32 media_fuse;
974 	u16 vdbox_mask;
975 	u16 vebox_mask;
976 
977 	if (INTEL_GEN(dev_priv) < 11)
978 		return;
979 
980 	media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
981 
982 	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
983 	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
984 		      GEN11_GT_VEBOX_DISABLE_SHIFT;
985 
986 	for (i = 0; i < I915_MAX_VCS; i++) {
987 		if (!HAS_ENGINE(dev_priv, _VCS(i)))
988 			continue;
989 
990 		if (!(BIT(i) & vdbox_mask)) {
991 			info->engine_mask &= ~BIT(_VCS(i));
992 			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
993 			continue;
994 		}
995 
996 		/*
997 		 * In Gen11, only even numbered logical VDBOXes are
998 		 * hooked up to an SFC (Scaler & Format Converter) unit.
999 		 */
1000 		if (logical_vdbox++ % 2 == 0)
1001 			RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
1002 	}
1003 	DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
1004 			 vdbox_mask, VDBOX_MASK(dev_priv));
1005 	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
1006 
1007 	for (i = 0; i < I915_MAX_VECS; i++) {
1008 		if (!HAS_ENGINE(dev_priv, _VECS(i)))
1009 			continue;
1010 
1011 		if (!(BIT(i) & vebox_mask)) {
1012 			info->engine_mask &= ~BIT(_VECS(i));
1013 			DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
1014 		}
1015 	}
1016 	DRM_DEBUG_DRIVER("vebox enable: %04x, instances: %04lx\n",
1017 			 vebox_mask, VEBOX_MASK(dev_priv));
1018 	GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv));
1019 }
1020