1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 #include <drm/i915_pciids.h> 27 28 #include "display/intel_cdclk.h" 29 #include "display/intel_de.h" 30 #include "intel_device_info.h" 31 #include "i915_drv.h" 32 33 #define PLATFORM_NAME(x) [INTEL_##x] = #x 34 static const char * const platform_names[] = { 35 PLATFORM_NAME(I830), 36 PLATFORM_NAME(I845G), 37 PLATFORM_NAME(I85X), 38 PLATFORM_NAME(I865G), 39 PLATFORM_NAME(I915G), 40 PLATFORM_NAME(I915GM), 41 PLATFORM_NAME(I945G), 42 PLATFORM_NAME(I945GM), 43 PLATFORM_NAME(G33), 44 PLATFORM_NAME(PINEVIEW), 45 PLATFORM_NAME(I965G), 46 PLATFORM_NAME(I965GM), 47 PLATFORM_NAME(G45), 48 PLATFORM_NAME(GM45), 49 PLATFORM_NAME(IRONLAKE), 50 PLATFORM_NAME(SANDYBRIDGE), 51 PLATFORM_NAME(IVYBRIDGE), 52 PLATFORM_NAME(VALLEYVIEW), 53 PLATFORM_NAME(HASWELL), 54 PLATFORM_NAME(BROADWELL), 55 PLATFORM_NAME(CHERRYVIEW), 56 PLATFORM_NAME(SKYLAKE), 57 PLATFORM_NAME(BROXTON), 58 PLATFORM_NAME(KABYLAKE), 59 PLATFORM_NAME(GEMINILAKE), 60 PLATFORM_NAME(COFFEELAKE), 61 PLATFORM_NAME(COMETLAKE), 62 PLATFORM_NAME(CANNONLAKE), 63 PLATFORM_NAME(ICELAKE), 64 PLATFORM_NAME(ELKHARTLAKE), 65 PLATFORM_NAME(JASPERLAKE), 66 PLATFORM_NAME(TIGERLAKE), 67 PLATFORM_NAME(ROCKETLAKE), 68 PLATFORM_NAME(DG1), 69 PLATFORM_NAME(ALDERLAKE_S), 70 PLATFORM_NAME(ALDERLAKE_P), 71 }; 72 #undef PLATFORM_NAME 73 74 const char *intel_platform_name(enum intel_platform platform) 75 { 76 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 77 78 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 79 platform_names[platform] == NULL)) 80 return "<unknown>"; 81 82 return platform_names[platform]; 83 } 84 85 static const char *iommu_name(void) 86 { 87 const char *msg = "n/a"; 88 89 #ifdef CONFIG_INTEL_IOMMU 90 msg = enableddisabled(intel_iommu_gfx_mapped); 91 #endif 92 93 return msg; 94 } 95 96 void intel_device_info_print_static(const struct intel_device_info *info, 97 struct drm_printer *p) 98 { 99 drm_printf(p, "graphics_ver: %u\n", info->graphics_ver); 100 drm_printf(p, "media_ver: %u\n", info->media_ver); 101 drm_printf(p, "display_ver: %u\n", info->display.ver); 102 drm_printf(p, "gt: %d\n", info->gt); 103 drm_printf(p, "iommu: %s\n", iommu_name()); 104 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 105 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 106 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 107 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 108 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 109 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 110 111 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)) 112 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 113 #undef PRINT_FLAG 114 115 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 116 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 117 #undef PRINT_FLAG 118 } 119 120 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 121 struct drm_printer *p) 122 { 123 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 124 } 125 126 #undef INTEL_VGA_DEVICE 127 #define INTEL_VGA_DEVICE(id, info) (id) 128 129 static const u16 subplatform_ult_ids[] = { 130 INTEL_HSW_ULT_GT1_IDS(0), 131 INTEL_HSW_ULT_GT2_IDS(0), 132 INTEL_HSW_ULT_GT3_IDS(0), 133 INTEL_BDW_ULT_GT1_IDS(0), 134 INTEL_BDW_ULT_GT2_IDS(0), 135 INTEL_BDW_ULT_GT3_IDS(0), 136 INTEL_BDW_ULT_RSVD_IDS(0), 137 INTEL_SKL_ULT_GT1_IDS(0), 138 INTEL_SKL_ULT_GT2_IDS(0), 139 INTEL_SKL_ULT_GT3_IDS(0), 140 INTEL_KBL_ULT_GT1_IDS(0), 141 INTEL_KBL_ULT_GT2_IDS(0), 142 INTEL_KBL_ULT_GT3_IDS(0), 143 INTEL_CFL_U_GT2_IDS(0), 144 INTEL_CFL_U_GT3_IDS(0), 145 INTEL_WHL_U_GT1_IDS(0), 146 INTEL_WHL_U_GT2_IDS(0), 147 INTEL_WHL_U_GT3_IDS(0), 148 INTEL_CML_U_GT1_IDS(0), 149 INTEL_CML_U_GT2_IDS(0), 150 }; 151 152 static const u16 subplatform_ulx_ids[] = { 153 INTEL_HSW_ULX_GT1_IDS(0), 154 INTEL_HSW_ULX_GT2_IDS(0), 155 INTEL_BDW_ULX_GT1_IDS(0), 156 INTEL_BDW_ULX_GT2_IDS(0), 157 INTEL_BDW_ULX_GT3_IDS(0), 158 INTEL_BDW_ULX_RSVD_IDS(0), 159 INTEL_SKL_ULX_GT1_IDS(0), 160 INTEL_SKL_ULX_GT2_IDS(0), 161 INTEL_KBL_ULX_GT1_IDS(0), 162 INTEL_KBL_ULX_GT2_IDS(0), 163 INTEL_AML_KBL_GT2_IDS(0), 164 INTEL_AML_CFL_GT2_IDS(0), 165 }; 166 167 static const u16 subplatform_portf_ids[] = { 168 INTEL_CNL_PORT_F_IDS(0), 169 INTEL_ICL_PORT_F_IDS(0), 170 }; 171 172 static bool find_devid(u16 id, const u16 *p, unsigned int num) 173 { 174 for (; num; num--, p++) { 175 if (*p == id) 176 return true; 177 } 178 179 return false; 180 } 181 182 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 183 { 184 const struct intel_device_info *info = INTEL_INFO(i915); 185 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 186 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 187 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 188 u16 devid = INTEL_DEVID(i915); 189 u32 mask = 0; 190 191 /* Make sure IS_<platform> checks are working. */ 192 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 193 194 /* Find and mark subplatform bits based on the PCI device id. */ 195 if (find_devid(devid, subplatform_ult_ids, 196 ARRAY_SIZE(subplatform_ult_ids))) { 197 mask = BIT(INTEL_SUBPLATFORM_ULT); 198 } else if (find_devid(devid, subplatform_ulx_ids, 199 ARRAY_SIZE(subplatform_ulx_ids))) { 200 mask = BIT(INTEL_SUBPLATFORM_ULX); 201 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 202 /* ULX machines are also considered ULT. */ 203 mask |= BIT(INTEL_SUBPLATFORM_ULT); 204 } 205 } else if (find_devid(devid, subplatform_portf_ids, 206 ARRAY_SIZE(subplatform_portf_ids))) { 207 mask = BIT(INTEL_SUBPLATFORM_PORTF); 208 } 209 210 if (IS_TIGERLAKE(i915)) { 211 struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev); 212 213 root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list); 214 215 drm_WARN_ON(&i915->drm, mask); 216 drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) != 217 TGL_ROOT_DEVICE_ID); 218 219 switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) { 220 case TGL_ROOT_DEVICE_SKU_ULX: 221 mask = BIT(INTEL_SUBPLATFORM_ULX); 222 break; 223 case TGL_ROOT_DEVICE_SKU_ULT: 224 mask = BIT(INTEL_SUBPLATFORM_ULT); 225 break; 226 } 227 } 228 229 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 230 231 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 232 } 233 234 /** 235 * intel_device_info_runtime_init - initialize runtime info 236 * @dev_priv: the i915 device 237 * 238 * Determine various intel_device_info fields at runtime. 239 * 240 * Use it when either: 241 * - it's judged too laborious to fill n static structures with the limit 242 * when a simple if statement does the job, 243 * - run-time checks (eg read fuse/strap registers) are needed. 244 * 245 * This function needs to be called: 246 * - after the MMIO has been setup as we are reading registers, 247 * - after the PCH has been detected, 248 * - before the first usage of the fields it can tweak. 249 */ 250 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 251 { 252 struct intel_device_info *info = mkwrite_device_info(dev_priv); 253 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 254 enum pipe pipe; 255 256 /* Wa_14011765242: adl-s A0 */ 257 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) 258 for_each_pipe(dev_priv, pipe) 259 runtime->num_scalers[pipe] = 0; 260 else if (GRAPHICS_VER(dev_priv) >= 10) { 261 for_each_pipe(dev_priv, pipe) 262 runtime->num_scalers[pipe] = 2; 263 } else if (GRAPHICS_VER(dev_priv) == 9) { 264 runtime->num_scalers[PIPE_A] = 2; 265 runtime->num_scalers[PIPE_B] = 2; 266 runtime->num_scalers[PIPE_C] = 1; 267 } 268 269 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 270 271 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 272 for_each_pipe(dev_priv, pipe) 273 runtime->num_sprites[pipe] = 4; 274 else if (GRAPHICS_VER(dev_priv) >= 11) 275 for_each_pipe(dev_priv, pipe) 276 runtime->num_sprites[pipe] = 6; 277 else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) 278 for_each_pipe(dev_priv, pipe) 279 runtime->num_sprites[pipe] = 3; 280 else if (IS_BROXTON(dev_priv)) { 281 /* 282 * Skylake and Broxton currently don't expose the topmost plane as its 283 * use is exclusive with the legacy cursor and we only want to expose 284 * one of those, not both. Until we can safely expose the topmost plane 285 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 286 * we don't expose the topmost plane at all to prevent ABI breakage 287 * down the line. 288 */ 289 290 runtime->num_sprites[PIPE_A] = 2; 291 runtime->num_sprites[PIPE_B] = 2; 292 runtime->num_sprites[PIPE_C] = 1; 293 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 294 for_each_pipe(dev_priv, pipe) 295 runtime->num_sprites[pipe] = 2; 296 } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { 297 for_each_pipe(dev_priv, pipe) 298 runtime->num_sprites[pipe] = 1; 299 } 300 301 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && 302 HAS_PCH_SPLIT(dev_priv)) { 303 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 304 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); 305 306 /* 307 * SFUSE_STRAP is supposed to have a bit signalling the display 308 * is fused off. Unfortunately it seems that, at least in 309 * certain cases, fused off display means that PCH display 310 * reads don't land anywhere. In that case, we read 0s. 311 * 312 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 313 * should be set when taking over after the firmware. 314 */ 315 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 316 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 317 (HAS_PCH_CPT(dev_priv) && 318 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 319 drm_info(&dev_priv->drm, 320 "Display fused off, disabling\n"); 321 info->pipe_mask = 0; 322 info->cpu_transcoder_mask = 0; 323 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 324 drm_info(&dev_priv->drm, "PipeC fused off\n"); 325 info->pipe_mask &= ~BIT(PIPE_C); 326 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 327 } 328 } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) { 329 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); 330 331 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 332 info->pipe_mask &= ~BIT(PIPE_A); 333 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 334 } 335 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 336 info->pipe_mask &= ~BIT(PIPE_B); 337 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 338 } 339 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 340 info->pipe_mask &= ~BIT(PIPE_C); 341 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 342 } 343 if (GRAPHICS_VER(dev_priv) >= 12 && 344 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 345 info->pipe_mask &= ~BIT(PIPE_D); 346 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 347 } 348 349 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 350 info->display.has_hdcp = 0; 351 352 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 353 info->display.has_fbc = 0; 354 355 if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 356 info->display.has_dmc = 0; 357 358 if (GRAPHICS_VER(dev_priv) >= 10 && 359 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 360 info->display.has_dsc = 0; 361 } 362 363 if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) { 364 drm_info(&dev_priv->drm, 365 "Disabling ppGTT for VT-d support\n"); 366 info->ppgtt_type = INTEL_PPGTT_NONE; 367 } 368 369 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 370 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 371 372 if (!HAS_DISPLAY(dev_priv)) { 373 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 374 DRIVER_ATOMIC); 375 memset(&info->display, 0, sizeof(info->display)); 376 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); 377 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); 378 } 379 } 380 381 void intel_driver_caps_print(const struct intel_driver_caps *caps, 382 struct drm_printer *p) 383 { 384 drm_printf(p, "Has logical contexts? %s\n", 385 yesno(caps->has_logical_contexts)); 386 drm_printf(p, "scheduler: %x\n", caps->scheduler); 387 } 388