1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/string_helpers.h> 26 27 #include <drm/drm_print.h> 28 #include <drm/i915_pciids.h> 29 30 #include "display/intel_display_device.h" 31 #include "gt/intel_gt_regs.h" 32 #include "i915_drv.h" 33 #include "i915_reg.h" 34 #include "i915_utils.h" 35 #include "intel_device_info.h" 36 37 #define PLATFORM_NAME(x) [INTEL_##x] = #x 38 static const char * const platform_names[] = { 39 PLATFORM_NAME(I830), 40 PLATFORM_NAME(I845G), 41 PLATFORM_NAME(I85X), 42 PLATFORM_NAME(I865G), 43 PLATFORM_NAME(I915G), 44 PLATFORM_NAME(I915GM), 45 PLATFORM_NAME(I945G), 46 PLATFORM_NAME(I945GM), 47 PLATFORM_NAME(G33), 48 PLATFORM_NAME(PINEVIEW), 49 PLATFORM_NAME(I965G), 50 PLATFORM_NAME(I965GM), 51 PLATFORM_NAME(G45), 52 PLATFORM_NAME(GM45), 53 PLATFORM_NAME(IRONLAKE), 54 PLATFORM_NAME(SANDYBRIDGE), 55 PLATFORM_NAME(IVYBRIDGE), 56 PLATFORM_NAME(VALLEYVIEW), 57 PLATFORM_NAME(HASWELL), 58 PLATFORM_NAME(BROADWELL), 59 PLATFORM_NAME(CHERRYVIEW), 60 PLATFORM_NAME(SKYLAKE), 61 PLATFORM_NAME(BROXTON), 62 PLATFORM_NAME(KABYLAKE), 63 PLATFORM_NAME(GEMINILAKE), 64 PLATFORM_NAME(COFFEELAKE), 65 PLATFORM_NAME(COMETLAKE), 66 PLATFORM_NAME(ICELAKE), 67 PLATFORM_NAME(ELKHARTLAKE), 68 PLATFORM_NAME(JASPERLAKE), 69 PLATFORM_NAME(TIGERLAKE), 70 PLATFORM_NAME(ROCKETLAKE), 71 PLATFORM_NAME(DG1), 72 PLATFORM_NAME(ALDERLAKE_S), 73 PLATFORM_NAME(ALDERLAKE_P), 74 PLATFORM_NAME(XEHPSDV), 75 PLATFORM_NAME(DG2), 76 PLATFORM_NAME(PONTEVECCHIO), 77 PLATFORM_NAME(METEORLAKE), 78 }; 79 #undef PLATFORM_NAME 80 81 const char *intel_platform_name(enum intel_platform platform) 82 { 83 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 84 85 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 86 platform_names[platform] == NULL)) 87 return "<unknown>"; 88 89 return platform_names[platform]; 90 } 91 92 void intel_device_info_print(const struct intel_device_info *info, 93 const struct intel_runtime_info *runtime, 94 struct drm_printer *p) 95 { 96 const struct intel_display_runtime_info *display_runtime = 97 &info->display->__runtime_defaults; 98 99 if (runtime->graphics.ip.rel) 100 drm_printf(p, "graphics version: %u.%02u\n", 101 runtime->graphics.ip.ver, 102 runtime->graphics.ip.rel); 103 else 104 drm_printf(p, "graphics version: %u\n", 105 runtime->graphics.ip.ver); 106 107 if (runtime->media.ip.rel) 108 drm_printf(p, "media version: %u.%02u\n", 109 runtime->media.ip.ver, 110 runtime->media.ip.rel); 111 else 112 drm_printf(p, "media version: %u\n", 113 runtime->media.ip.ver); 114 115 if (display_runtime->ip.rel) 116 drm_printf(p, "display version: %u.%02u\n", 117 display_runtime->ip.ver, 118 display_runtime->ip.rel); 119 else 120 drm_printf(p, "display version: %u\n", 121 display_runtime->ip.ver); 122 123 drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step)); 124 drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step)); 125 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step)); 126 drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step)); 127 128 drm_printf(p, "gt: %d\n", info->gt); 129 drm_printf(p, "memory-regions: 0x%x\n", runtime->memory_regions); 130 drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes); 131 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 132 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size); 133 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type); 134 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 135 136 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 137 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 138 #undef PRINT_FLAG 139 140 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); 141 142 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name)) 143 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 144 #undef PRINT_FLAG 145 146 drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp)); 147 drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc)); 148 drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc)); 149 150 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 151 } 152 153 #undef INTEL_VGA_DEVICE 154 #define INTEL_VGA_DEVICE(id, info) (id) 155 156 static const u16 subplatform_ult_ids[] = { 157 INTEL_HSW_ULT_GT1_IDS(0), 158 INTEL_HSW_ULT_GT2_IDS(0), 159 INTEL_HSW_ULT_GT3_IDS(0), 160 INTEL_BDW_ULT_GT1_IDS(0), 161 INTEL_BDW_ULT_GT2_IDS(0), 162 INTEL_BDW_ULT_GT3_IDS(0), 163 INTEL_BDW_ULT_RSVD_IDS(0), 164 INTEL_SKL_ULT_GT1_IDS(0), 165 INTEL_SKL_ULT_GT2_IDS(0), 166 INTEL_SKL_ULT_GT3_IDS(0), 167 INTEL_KBL_ULT_GT1_IDS(0), 168 INTEL_KBL_ULT_GT2_IDS(0), 169 INTEL_KBL_ULT_GT3_IDS(0), 170 INTEL_CFL_U_GT2_IDS(0), 171 INTEL_CFL_U_GT3_IDS(0), 172 INTEL_WHL_U_GT1_IDS(0), 173 INTEL_WHL_U_GT2_IDS(0), 174 INTEL_WHL_U_GT3_IDS(0), 175 INTEL_CML_U_GT1_IDS(0), 176 INTEL_CML_U_GT2_IDS(0), 177 }; 178 179 static const u16 subplatform_ulx_ids[] = { 180 INTEL_HSW_ULX_GT1_IDS(0), 181 INTEL_HSW_ULX_GT2_IDS(0), 182 INTEL_BDW_ULX_GT1_IDS(0), 183 INTEL_BDW_ULX_GT2_IDS(0), 184 INTEL_BDW_ULX_GT3_IDS(0), 185 INTEL_BDW_ULX_RSVD_IDS(0), 186 INTEL_SKL_ULX_GT1_IDS(0), 187 INTEL_SKL_ULX_GT2_IDS(0), 188 INTEL_KBL_ULX_GT1_IDS(0), 189 INTEL_KBL_ULX_GT2_IDS(0), 190 INTEL_AML_KBL_GT2_IDS(0), 191 INTEL_AML_CFL_GT2_IDS(0), 192 }; 193 194 static const u16 subplatform_portf_ids[] = { 195 INTEL_ICL_PORT_F_IDS(0), 196 }; 197 198 static const u16 subplatform_uy_ids[] = { 199 INTEL_TGL_12_GT2_IDS(0), 200 }; 201 202 static const u16 subplatform_n_ids[] = { 203 INTEL_ADLN_IDS(0), 204 }; 205 206 static const u16 subplatform_rpl_ids[] = { 207 INTEL_RPLS_IDS(0), 208 INTEL_RPLP_IDS(0), 209 }; 210 211 static const u16 subplatform_rplu_ids[] = { 212 INTEL_RPLU_IDS(0), 213 }; 214 215 static const u16 subplatform_g10_ids[] = { 216 INTEL_DG2_G10_IDS(0), 217 INTEL_ATS_M150_IDS(0), 218 }; 219 220 static const u16 subplatform_g11_ids[] = { 221 INTEL_DG2_G11_IDS(0), 222 INTEL_ATS_M75_IDS(0), 223 }; 224 225 static const u16 subplatform_g12_ids[] = { 226 INTEL_DG2_G12_IDS(0), 227 }; 228 229 static const u16 subplatform_m_ids[] = { 230 INTEL_MTL_M_IDS(0), 231 }; 232 233 static const u16 subplatform_p_ids[] = { 234 INTEL_MTL_P_IDS(0), 235 }; 236 237 static bool find_devid(u16 id, const u16 *p, unsigned int num) 238 { 239 for (; num; num--, p++) { 240 if (*p == id) 241 return true; 242 } 243 244 return false; 245 } 246 247 static void intel_device_info_subplatform_init(struct drm_i915_private *i915) 248 { 249 const struct intel_device_info *info = INTEL_INFO(i915); 250 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 251 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 252 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 253 u16 devid = INTEL_DEVID(i915); 254 u32 mask = 0; 255 256 /* Make sure IS_<platform> checks are working. */ 257 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 258 259 /* Find and mark subplatform bits based on the PCI device id. */ 260 if (find_devid(devid, subplatform_ult_ids, 261 ARRAY_SIZE(subplatform_ult_ids))) { 262 mask = BIT(INTEL_SUBPLATFORM_ULT); 263 } else if (find_devid(devid, subplatform_ulx_ids, 264 ARRAY_SIZE(subplatform_ulx_ids))) { 265 mask = BIT(INTEL_SUBPLATFORM_ULX); 266 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 267 /* ULX machines are also considered ULT. */ 268 mask |= BIT(INTEL_SUBPLATFORM_ULT); 269 } 270 } else if (find_devid(devid, subplatform_portf_ids, 271 ARRAY_SIZE(subplatform_portf_ids))) { 272 mask = BIT(INTEL_SUBPLATFORM_PORTF); 273 } else if (find_devid(devid, subplatform_uy_ids, 274 ARRAY_SIZE(subplatform_uy_ids))) { 275 mask = BIT(INTEL_SUBPLATFORM_UY); 276 } else if (find_devid(devid, subplatform_n_ids, 277 ARRAY_SIZE(subplatform_n_ids))) { 278 mask = BIT(INTEL_SUBPLATFORM_N); 279 } else if (find_devid(devid, subplatform_rpl_ids, 280 ARRAY_SIZE(subplatform_rpl_ids))) { 281 mask = BIT(INTEL_SUBPLATFORM_RPL); 282 if (find_devid(devid, subplatform_rplu_ids, 283 ARRAY_SIZE(subplatform_rplu_ids))) 284 mask |= BIT(INTEL_SUBPLATFORM_RPLU); 285 } else if (find_devid(devid, subplatform_g10_ids, 286 ARRAY_SIZE(subplatform_g10_ids))) { 287 mask = BIT(INTEL_SUBPLATFORM_G10); 288 } else if (find_devid(devid, subplatform_g11_ids, 289 ARRAY_SIZE(subplatform_g11_ids))) { 290 mask = BIT(INTEL_SUBPLATFORM_G11); 291 } else if (find_devid(devid, subplatform_g12_ids, 292 ARRAY_SIZE(subplatform_g12_ids))) { 293 mask = BIT(INTEL_SUBPLATFORM_G12); 294 } else if (find_devid(devid, subplatform_m_ids, 295 ARRAY_SIZE(subplatform_m_ids))) { 296 mask = BIT(INTEL_SUBPLATFORM_M); 297 } else if (find_devid(devid, subplatform_p_ids, 298 ARRAY_SIZE(subplatform_p_ids))) { 299 mask = BIT(INTEL_SUBPLATFORM_P); 300 } 301 302 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 303 304 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 305 } 306 307 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip) 308 { 309 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 310 void __iomem *addr; 311 u32 val; 312 u8 expected_ver = ip->ver; 313 u8 expected_rel = ip->rel; 314 315 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); 316 if (drm_WARN_ON(&i915->drm, !addr)) 317 return; 318 319 val = ioread32(addr); 320 pci_iounmap(pdev, addr); 321 322 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 323 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 324 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); 325 326 /* Sanity check against expected versions from device info */ 327 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) 328 drm_dbg(&i915->drm, 329 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n", 330 ip->ver, ip->rel, offset, val, expected_ver, expected_rel); 331 } 332 333 /* 334 * Setup the graphics version for the current device. This must be done before 335 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this 336 * function should be called very early in the driver initialization sequence. 337 * 338 * Regular MMIO access is not yet setup at the point this function is called so 339 * we peek at the appropriate MMIO offset directly. The GMD_ID register is 340 * part of an 'always on' power well by design, so we don't need to worry about 341 * forcewake while reading it. 342 */ 343 static void intel_ipver_early_init(struct drm_i915_private *i915) 344 { 345 struct intel_runtime_info *runtime = RUNTIME_INFO(i915); 346 347 if (!HAS_GMD_ID(i915)) { 348 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12); 349 /* 350 * On older platforms, graphics and media share the same ip 351 * version and release. 352 */ 353 RUNTIME_INFO(i915)->media.ip = 354 RUNTIME_INFO(i915)->graphics.ip; 355 return; 356 } 357 358 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), 359 &runtime->graphics.ip); 360 /* Wa_22012778468 */ 361 if (runtime->graphics.ip.ver == 0x0 && 362 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) { 363 RUNTIME_INFO(i915)->graphics.ip.ver = 12; 364 RUNTIME_INFO(i915)->graphics.ip.rel = 70; 365 } 366 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), 367 &runtime->media.ip); 368 } 369 370 /** 371 * intel_device_info_runtime_init_early - initialize early runtime info 372 * @i915: the i915 device 373 * 374 * Determine early intel_device_info fields at runtime. This function needs 375 * to be called before the MMIO has been setup. 376 */ 377 void intel_device_info_runtime_init_early(struct drm_i915_private *i915) 378 { 379 intel_ipver_early_init(i915); 380 intel_device_info_subplatform_init(i915); 381 } 382 383 /* FIXME: Remove this, and make device info a const pointer to rodata. */ 384 static struct intel_device_info * 385 mkwrite_device_info(struct drm_i915_private *i915) 386 { 387 return (struct intel_device_info *)INTEL_INFO(i915); 388 } 389 390 static const struct intel_display_device_info no_display = {}; 391 392 /** 393 * intel_device_info_runtime_init - initialize runtime info 394 * @dev_priv: the i915 device 395 * 396 * Determine various intel_device_info fields at runtime. 397 * 398 * Use it when either: 399 * - it's judged too laborious to fill n static structures with the limit 400 * when a simple if statement does the job, 401 * - run-time checks (eg read fuse/strap registers) are needed. 402 * 403 * This function needs to be called: 404 * - after the MMIO has been setup as we are reading registers, 405 * - after the PCH has been detected, 406 * - before the first usage of the fields it can tweak. 407 */ 408 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 409 { 410 struct intel_device_info *info = mkwrite_device_info(dev_priv); 411 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 412 413 if (HAS_DISPLAY(dev_priv)) 414 intel_display_device_info_runtime_init(dev_priv); 415 416 /* Display may have been disabled by runtime init */ 417 if (!HAS_DISPLAY(dev_priv)) { 418 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 419 DRIVER_ATOMIC); 420 info->display = &no_display; 421 } 422 423 /* Disable nuclear pageflip by default on pre-g4x */ 424 if (!dev_priv->params.nuclear_pageflip && 425 DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 426 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; 427 428 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 429 430 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 431 drm_info(&dev_priv->drm, 432 "Disabling ppGTT for VT-d support\n"); 433 runtime->ppgtt_type = INTEL_PPGTT_NONE; 434 } 435 436 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 437 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 438 439 } 440 441 /* 442 * Set up device info and initial runtime info at driver create. 443 * 444 * Note: i915 is only an allocated blob of memory at this point. 445 */ 446 void intel_device_info_driver_create(struct drm_i915_private *i915, 447 u16 device_id, 448 const struct intel_device_info *match_info) 449 { 450 struct intel_device_info *info; 451 struct intel_runtime_info *runtime; 452 u16 ver, rel, step; 453 454 /* Setup the write-once "constant" device info */ 455 info = mkwrite_device_info(i915); 456 memcpy(info, match_info, sizeof(*info)); 457 458 /* Initialize initial runtime info from static const data and pdev. */ 459 runtime = RUNTIME_INFO(i915); 460 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 461 462 /* Probe display support */ 463 info->display = intel_display_device_probe(i915, info->has_gmd_id, 464 &ver, &rel, &step); 465 memcpy(DISPLAY_RUNTIME_INFO(i915), 466 &DISPLAY_INFO(i915)->__runtime_defaults, 467 sizeof(*DISPLAY_RUNTIME_INFO(i915))); 468 469 if (info->has_gmd_id) { 470 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver; 471 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; 472 DISPLAY_RUNTIME_INFO(i915)->ip.step = step; 473 } 474 475 runtime->device_id = device_id; 476 } 477 478 void intel_driver_caps_print(const struct intel_driver_caps *caps, 479 struct drm_printer *p) 480 { 481 drm_printf(p, "Has logical contexts? %s\n", 482 str_yes_no(caps->has_logical_contexts)); 483 drm_printf(p, "scheduler: 0x%x\n", caps->scheduler); 484 } 485