1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/string_helpers.h> 26 27 #include <drm/drm_print.h> 28 #include <drm/i915_pciids.h> 29 30 #include "display/intel_cdclk.h" 31 #include "display/intel_de.h" 32 #include "intel_device_info.h" 33 #include "i915_drv.h" 34 #include "i915_utils.h" 35 36 #define PLATFORM_NAME(x) [INTEL_##x] = #x 37 static const char * const platform_names[] = { 38 PLATFORM_NAME(I830), 39 PLATFORM_NAME(I845G), 40 PLATFORM_NAME(I85X), 41 PLATFORM_NAME(I865G), 42 PLATFORM_NAME(I915G), 43 PLATFORM_NAME(I915GM), 44 PLATFORM_NAME(I945G), 45 PLATFORM_NAME(I945GM), 46 PLATFORM_NAME(G33), 47 PLATFORM_NAME(PINEVIEW), 48 PLATFORM_NAME(I965G), 49 PLATFORM_NAME(I965GM), 50 PLATFORM_NAME(G45), 51 PLATFORM_NAME(GM45), 52 PLATFORM_NAME(IRONLAKE), 53 PLATFORM_NAME(SANDYBRIDGE), 54 PLATFORM_NAME(IVYBRIDGE), 55 PLATFORM_NAME(VALLEYVIEW), 56 PLATFORM_NAME(HASWELL), 57 PLATFORM_NAME(BROADWELL), 58 PLATFORM_NAME(CHERRYVIEW), 59 PLATFORM_NAME(SKYLAKE), 60 PLATFORM_NAME(BROXTON), 61 PLATFORM_NAME(KABYLAKE), 62 PLATFORM_NAME(GEMINILAKE), 63 PLATFORM_NAME(COFFEELAKE), 64 PLATFORM_NAME(COMETLAKE), 65 PLATFORM_NAME(ICELAKE), 66 PLATFORM_NAME(ELKHARTLAKE), 67 PLATFORM_NAME(JASPERLAKE), 68 PLATFORM_NAME(TIGERLAKE), 69 PLATFORM_NAME(ROCKETLAKE), 70 PLATFORM_NAME(DG1), 71 PLATFORM_NAME(ALDERLAKE_S), 72 PLATFORM_NAME(ALDERLAKE_P), 73 PLATFORM_NAME(XEHPSDV), 74 PLATFORM_NAME(DG2), 75 PLATFORM_NAME(PONTEVECCHIO), 76 PLATFORM_NAME(METEORLAKE), 77 }; 78 #undef PLATFORM_NAME 79 80 const char *intel_platform_name(enum intel_platform platform) 81 { 82 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 83 84 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 85 platform_names[platform] == NULL)) 86 return "<unknown>"; 87 88 return platform_names[platform]; 89 } 90 91 void intel_device_info_print_static(const struct intel_device_info *info, 92 struct drm_printer *p) 93 { 94 if (info->graphics.rel) 95 drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, 96 info->graphics.rel); 97 else 98 drm_printf(p, "graphics version: %u\n", info->graphics.ver); 99 100 if (info->media.rel) 101 drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); 102 else 103 drm_printf(p, "media version: %u\n", info->media.ver); 104 105 if (info->display.rel) 106 drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); 107 else 108 drm_printf(p, "display version: %u\n", info->display.ver); 109 110 drm_printf(p, "gt: %d\n", info->gt); 111 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 112 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 113 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 114 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 115 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 116 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 117 118 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 119 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 120 #undef PRINT_FLAG 121 122 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name)) 123 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 124 #undef PRINT_FLAG 125 } 126 127 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 128 struct drm_printer *p) 129 { 130 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 131 } 132 133 #undef INTEL_VGA_DEVICE 134 #define INTEL_VGA_DEVICE(id, info) (id) 135 136 static const u16 subplatform_ult_ids[] = { 137 INTEL_HSW_ULT_GT1_IDS(0), 138 INTEL_HSW_ULT_GT2_IDS(0), 139 INTEL_HSW_ULT_GT3_IDS(0), 140 INTEL_BDW_ULT_GT1_IDS(0), 141 INTEL_BDW_ULT_GT2_IDS(0), 142 INTEL_BDW_ULT_GT3_IDS(0), 143 INTEL_BDW_ULT_RSVD_IDS(0), 144 INTEL_SKL_ULT_GT1_IDS(0), 145 INTEL_SKL_ULT_GT2_IDS(0), 146 INTEL_SKL_ULT_GT3_IDS(0), 147 INTEL_KBL_ULT_GT1_IDS(0), 148 INTEL_KBL_ULT_GT2_IDS(0), 149 INTEL_KBL_ULT_GT3_IDS(0), 150 INTEL_CFL_U_GT2_IDS(0), 151 INTEL_CFL_U_GT3_IDS(0), 152 INTEL_WHL_U_GT1_IDS(0), 153 INTEL_WHL_U_GT2_IDS(0), 154 INTEL_WHL_U_GT3_IDS(0), 155 INTEL_CML_U_GT1_IDS(0), 156 INTEL_CML_U_GT2_IDS(0), 157 }; 158 159 static const u16 subplatform_ulx_ids[] = { 160 INTEL_HSW_ULX_GT1_IDS(0), 161 INTEL_HSW_ULX_GT2_IDS(0), 162 INTEL_BDW_ULX_GT1_IDS(0), 163 INTEL_BDW_ULX_GT2_IDS(0), 164 INTEL_BDW_ULX_GT3_IDS(0), 165 INTEL_BDW_ULX_RSVD_IDS(0), 166 INTEL_SKL_ULX_GT1_IDS(0), 167 INTEL_SKL_ULX_GT2_IDS(0), 168 INTEL_KBL_ULX_GT1_IDS(0), 169 INTEL_KBL_ULX_GT2_IDS(0), 170 INTEL_AML_KBL_GT2_IDS(0), 171 INTEL_AML_CFL_GT2_IDS(0), 172 }; 173 174 static const u16 subplatform_portf_ids[] = { 175 INTEL_ICL_PORT_F_IDS(0), 176 }; 177 178 static const u16 subplatform_uy_ids[] = { 179 INTEL_TGL_12_GT2_IDS(0), 180 }; 181 182 static const u16 subplatform_n_ids[] = { 183 INTEL_ADLN_IDS(0), 184 }; 185 186 static const u16 subplatform_rpl_ids[] = { 187 INTEL_RPLS_IDS(0), 188 INTEL_RPLP_IDS(0), 189 }; 190 191 static const u16 subplatform_g10_ids[] = { 192 INTEL_DG2_G10_IDS(0), 193 INTEL_ATS_M150_IDS(0), 194 }; 195 196 static const u16 subplatform_g11_ids[] = { 197 INTEL_DG2_G11_IDS(0), 198 INTEL_ATS_M75_IDS(0), 199 }; 200 201 static const u16 subplatform_g12_ids[] = { 202 INTEL_DG2_G12_IDS(0), 203 }; 204 205 static const u16 subplatform_m_ids[] = { 206 INTEL_MTL_M_IDS(0), 207 }; 208 209 static const u16 subplatform_p_ids[] = { 210 INTEL_MTL_P_IDS(0), 211 }; 212 213 static bool find_devid(u16 id, const u16 *p, unsigned int num) 214 { 215 for (; num; num--, p++) { 216 if (*p == id) 217 return true; 218 } 219 220 return false; 221 } 222 223 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 224 { 225 const struct intel_device_info *info = INTEL_INFO(i915); 226 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 227 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 228 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 229 u16 devid = INTEL_DEVID(i915); 230 u32 mask = 0; 231 232 /* Make sure IS_<platform> checks are working. */ 233 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 234 235 /* Find and mark subplatform bits based on the PCI device id. */ 236 if (find_devid(devid, subplatform_ult_ids, 237 ARRAY_SIZE(subplatform_ult_ids))) { 238 mask = BIT(INTEL_SUBPLATFORM_ULT); 239 } else if (find_devid(devid, subplatform_ulx_ids, 240 ARRAY_SIZE(subplatform_ulx_ids))) { 241 mask = BIT(INTEL_SUBPLATFORM_ULX); 242 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 243 /* ULX machines are also considered ULT. */ 244 mask |= BIT(INTEL_SUBPLATFORM_ULT); 245 } 246 } else if (find_devid(devid, subplatform_portf_ids, 247 ARRAY_SIZE(subplatform_portf_ids))) { 248 mask = BIT(INTEL_SUBPLATFORM_PORTF); 249 } else if (find_devid(devid, subplatform_uy_ids, 250 ARRAY_SIZE(subplatform_uy_ids))) { 251 mask = BIT(INTEL_SUBPLATFORM_UY); 252 } else if (find_devid(devid, subplatform_n_ids, 253 ARRAY_SIZE(subplatform_n_ids))) { 254 mask = BIT(INTEL_SUBPLATFORM_N); 255 } else if (find_devid(devid, subplatform_rpl_ids, 256 ARRAY_SIZE(subplatform_rpl_ids))) { 257 mask = BIT(INTEL_SUBPLATFORM_RPL); 258 } else if (find_devid(devid, subplatform_g10_ids, 259 ARRAY_SIZE(subplatform_g10_ids))) { 260 mask = BIT(INTEL_SUBPLATFORM_G10); 261 } else if (find_devid(devid, subplatform_g11_ids, 262 ARRAY_SIZE(subplatform_g11_ids))) { 263 mask = BIT(INTEL_SUBPLATFORM_G11); 264 } else if (find_devid(devid, subplatform_g12_ids, 265 ARRAY_SIZE(subplatform_g12_ids))) { 266 mask = BIT(INTEL_SUBPLATFORM_G12); 267 } else if (find_devid(devid, subplatform_m_ids, 268 ARRAY_SIZE(subplatform_m_ids))) { 269 mask = BIT(INTEL_SUBPLATFORM_M); 270 } else if (find_devid(devid, subplatform_p_ids, 271 ARRAY_SIZE(subplatform_p_ids))) { 272 mask = BIT(INTEL_SUBPLATFORM_P); 273 } 274 275 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 276 277 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 278 } 279 280 /** 281 * intel_device_info_runtime_init - initialize runtime info 282 * @dev_priv: the i915 device 283 * 284 * Determine various intel_device_info fields at runtime. 285 * 286 * Use it when either: 287 * - it's judged too laborious to fill n static structures with the limit 288 * when a simple if statement does the job, 289 * - run-time checks (eg read fuse/strap registers) are needed. 290 * 291 * This function needs to be called: 292 * - after the MMIO has been setup as we are reading registers, 293 * - after the PCH has been detected, 294 * - before the first usage of the fields it can tweak. 295 */ 296 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 297 { 298 struct intel_device_info *info = mkwrite_device_info(dev_priv); 299 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 300 enum pipe pipe; 301 302 /* Wa_14011765242: adl-s A0,A1 */ 303 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) 304 for_each_pipe(dev_priv, pipe) 305 runtime->num_scalers[pipe] = 0; 306 else if (DISPLAY_VER(dev_priv) >= 11) { 307 for_each_pipe(dev_priv, pipe) 308 runtime->num_scalers[pipe] = 2; 309 } else if (DISPLAY_VER(dev_priv) >= 9) { 310 runtime->num_scalers[PIPE_A] = 2; 311 runtime->num_scalers[PIPE_B] = 2; 312 runtime->num_scalers[PIPE_C] = 1; 313 } 314 315 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 316 317 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 318 for_each_pipe(dev_priv, pipe) 319 runtime->num_sprites[pipe] = 4; 320 else if (DISPLAY_VER(dev_priv) >= 11) 321 for_each_pipe(dev_priv, pipe) 322 runtime->num_sprites[pipe] = 6; 323 else if (DISPLAY_VER(dev_priv) == 10) 324 for_each_pipe(dev_priv, pipe) 325 runtime->num_sprites[pipe] = 3; 326 else if (IS_BROXTON(dev_priv)) { 327 /* 328 * Skylake and Broxton currently don't expose the topmost plane as its 329 * use is exclusive with the legacy cursor and we only want to expose 330 * one of those, not both. Until we can safely expose the topmost plane 331 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 332 * we don't expose the topmost plane at all to prevent ABI breakage 333 * down the line. 334 */ 335 336 runtime->num_sprites[PIPE_A] = 2; 337 runtime->num_sprites[PIPE_B] = 2; 338 runtime->num_sprites[PIPE_C] = 1; 339 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 340 for_each_pipe(dev_priv, pipe) 341 runtime->num_sprites[pipe] = 2; 342 } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { 343 for_each_pipe(dev_priv, pipe) 344 runtime->num_sprites[pipe] = 1; 345 } 346 347 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && 348 HAS_PCH_SPLIT(dev_priv)) { 349 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 350 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); 351 352 /* 353 * SFUSE_STRAP is supposed to have a bit signalling the display 354 * is fused off. Unfortunately it seems that, at least in 355 * certain cases, fused off display means that PCH display 356 * reads don't land anywhere. In that case, we read 0s. 357 * 358 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 359 * should be set when taking over after the firmware. 360 */ 361 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 362 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 363 (HAS_PCH_CPT(dev_priv) && 364 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 365 drm_info(&dev_priv->drm, 366 "Display fused off, disabling\n"); 367 info->display.pipe_mask = 0; 368 info->display.cpu_transcoder_mask = 0; 369 info->display.fbc_mask = 0; 370 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 371 drm_info(&dev_priv->drm, "PipeC fused off\n"); 372 info->display.pipe_mask &= ~BIT(PIPE_C); 373 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 374 } 375 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { 376 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); 377 378 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 379 info->display.pipe_mask &= ~BIT(PIPE_A); 380 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 381 info->display.fbc_mask &= ~BIT(INTEL_FBC_A); 382 } 383 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 384 info->display.pipe_mask &= ~BIT(PIPE_B); 385 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 386 } 387 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 388 info->display.pipe_mask &= ~BIT(PIPE_C); 389 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 390 } 391 392 if (DISPLAY_VER(dev_priv) >= 12 && 393 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 394 info->display.pipe_mask &= ~BIT(PIPE_D); 395 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 396 } 397 398 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 399 info->display.has_hdcp = 0; 400 401 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 402 info->display.fbc_mask = 0; 403 404 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 405 info->display.has_dmc = 0; 406 407 if (DISPLAY_VER(dev_priv) >= 10 && 408 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 409 info->display.has_dsc = 0; 410 } 411 412 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 413 drm_info(&dev_priv->drm, 414 "Disabling ppGTT for VT-d support\n"); 415 info->ppgtt_type = INTEL_PPGTT_NONE; 416 } 417 418 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 419 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 420 421 if (!HAS_DISPLAY(dev_priv)) { 422 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 423 DRIVER_ATOMIC); 424 memset(&info->display, 0, sizeof(info->display)); 425 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); 426 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); 427 } 428 } 429 430 void intel_driver_caps_print(const struct intel_driver_caps *caps, 431 struct drm_printer *p) 432 { 433 drm_printf(p, "Has logical contexts? %s\n", 434 str_yes_no(caps->has_logical_contexts)); 435 drm_printf(p, "scheduler: %x\n", caps->scheduler); 436 } 437