1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/string_helpers.h> 26 27 #include <drm/drm_print.h> 28 #include <drm/i915_pciids.h> 29 30 #include "display/intel_cdclk.h" 31 #include "display/intel_de.h" 32 #include "intel_device_info.h" 33 #include "i915_drv.h" 34 #include "i915_utils.h" 35 36 #define PLATFORM_NAME(x) [INTEL_##x] = #x 37 static const char * const platform_names[] = { 38 PLATFORM_NAME(I830), 39 PLATFORM_NAME(I845G), 40 PLATFORM_NAME(I85X), 41 PLATFORM_NAME(I865G), 42 PLATFORM_NAME(I915G), 43 PLATFORM_NAME(I915GM), 44 PLATFORM_NAME(I945G), 45 PLATFORM_NAME(I945GM), 46 PLATFORM_NAME(G33), 47 PLATFORM_NAME(PINEVIEW), 48 PLATFORM_NAME(I965G), 49 PLATFORM_NAME(I965GM), 50 PLATFORM_NAME(G45), 51 PLATFORM_NAME(GM45), 52 PLATFORM_NAME(IRONLAKE), 53 PLATFORM_NAME(SANDYBRIDGE), 54 PLATFORM_NAME(IVYBRIDGE), 55 PLATFORM_NAME(VALLEYVIEW), 56 PLATFORM_NAME(HASWELL), 57 PLATFORM_NAME(BROADWELL), 58 PLATFORM_NAME(CHERRYVIEW), 59 PLATFORM_NAME(SKYLAKE), 60 PLATFORM_NAME(BROXTON), 61 PLATFORM_NAME(KABYLAKE), 62 PLATFORM_NAME(GEMINILAKE), 63 PLATFORM_NAME(COFFEELAKE), 64 PLATFORM_NAME(COMETLAKE), 65 PLATFORM_NAME(ICELAKE), 66 PLATFORM_NAME(ELKHARTLAKE), 67 PLATFORM_NAME(JASPERLAKE), 68 PLATFORM_NAME(TIGERLAKE), 69 PLATFORM_NAME(ROCKETLAKE), 70 PLATFORM_NAME(DG1), 71 PLATFORM_NAME(ALDERLAKE_S), 72 PLATFORM_NAME(ALDERLAKE_P), 73 PLATFORM_NAME(XEHPSDV), 74 PLATFORM_NAME(DG2), 75 PLATFORM_NAME(PONTEVECCHIO), 76 }; 77 #undef PLATFORM_NAME 78 79 const char *intel_platform_name(enum intel_platform platform) 80 { 81 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 82 83 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 84 platform_names[platform] == NULL)) 85 return "<unknown>"; 86 87 return platform_names[platform]; 88 } 89 90 void intel_device_info_print_static(const struct intel_device_info *info, 91 struct drm_printer *p) 92 { 93 if (info->graphics.rel) 94 drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, 95 info->graphics.rel); 96 else 97 drm_printf(p, "graphics version: %u\n", info->graphics.ver); 98 99 if (info->media.rel) 100 drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); 101 else 102 drm_printf(p, "media version: %u\n", info->media.ver); 103 104 if (info->display.rel) 105 drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); 106 else 107 drm_printf(p, "display version: %u\n", info->display.ver); 108 109 drm_printf(p, "gt: %d\n", info->gt); 110 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 111 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 112 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 113 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 114 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 115 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 116 117 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 118 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 119 #undef PRINT_FLAG 120 121 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name)) 122 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 123 #undef PRINT_FLAG 124 } 125 126 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 127 struct drm_printer *p) 128 { 129 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 130 } 131 132 #undef INTEL_VGA_DEVICE 133 #define INTEL_VGA_DEVICE(id, info) (id) 134 135 static const u16 subplatform_ult_ids[] = { 136 INTEL_HSW_ULT_GT1_IDS(0), 137 INTEL_HSW_ULT_GT2_IDS(0), 138 INTEL_HSW_ULT_GT3_IDS(0), 139 INTEL_BDW_ULT_GT1_IDS(0), 140 INTEL_BDW_ULT_GT2_IDS(0), 141 INTEL_BDW_ULT_GT3_IDS(0), 142 INTEL_BDW_ULT_RSVD_IDS(0), 143 INTEL_SKL_ULT_GT1_IDS(0), 144 INTEL_SKL_ULT_GT2_IDS(0), 145 INTEL_SKL_ULT_GT3_IDS(0), 146 INTEL_KBL_ULT_GT1_IDS(0), 147 INTEL_KBL_ULT_GT2_IDS(0), 148 INTEL_KBL_ULT_GT3_IDS(0), 149 INTEL_CFL_U_GT2_IDS(0), 150 INTEL_CFL_U_GT3_IDS(0), 151 INTEL_WHL_U_GT1_IDS(0), 152 INTEL_WHL_U_GT2_IDS(0), 153 INTEL_WHL_U_GT3_IDS(0), 154 INTEL_CML_U_GT1_IDS(0), 155 INTEL_CML_U_GT2_IDS(0), 156 }; 157 158 static const u16 subplatform_ulx_ids[] = { 159 INTEL_HSW_ULX_GT1_IDS(0), 160 INTEL_HSW_ULX_GT2_IDS(0), 161 INTEL_BDW_ULX_GT1_IDS(0), 162 INTEL_BDW_ULX_GT2_IDS(0), 163 INTEL_BDW_ULX_GT3_IDS(0), 164 INTEL_BDW_ULX_RSVD_IDS(0), 165 INTEL_SKL_ULX_GT1_IDS(0), 166 INTEL_SKL_ULX_GT2_IDS(0), 167 INTEL_KBL_ULX_GT1_IDS(0), 168 INTEL_KBL_ULX_GT2_IDS(0), 169 INTEL_AML_KBL_GT2_IDS(0), 170 INTEL_AML_CFL_GT2_IDS(0), 171 }; 172 173 static const u16 subplatform_portf_ids[] = { 174 INTEL_ICL_PORT_F_IDS(0), 175 }; 176 177 static const u16 subplatform_uy_ids[] = { 178 INTEL_TGL_12_GT2_IDS(0), 179 }; 180 181 static const u16 subplatform_n_ids[] = { 182 INTEL_ADLN_IDS(0), 183 }; 184 185 static const u16 subplatform_rpl_ids[] = { 186 INTEL_RPLS_IDS(0), 187 INTEL_RPLP_IDS(0), 188 }; 189 190 static const u16 subplatform_g10_ids[] = { 191 INTEL_DG2_G10_IDS(0), 192 }; 193 194 static const u16 subplatform_g11_ids[] = { 195 INTEL_DG2_G11_IDS(0), 196 }; 197 198 static const u16 subplatform_g12_ids[] = { 199 INTEL_DG2_G12_IDS(0), 200 }; 201 202 static bool find_devid(u16 id, const u16 *p, unsigned int num) 203 { 204 for (; num; num--, p++) { 205 if (*p == id) 206 return true; 207 } 208 209 return false; 210 } 211 212 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 213 { 214 const struct intel_device_info *info = INTEL_INFO(i915); 215 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 216 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 217 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 218 u16 devid = INTEL_DEVID(i915); 219 u32 mask = 0; 220 221 /* Make sure IS_<platform> checks are working. */ 222 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 223 224 /* Find and mark subplatform bits based on the PCI device id. */ 225 if (find_devid(devid, subplatform_ult_ids, 226 ARRAY_SIZE(subplatform_ult_ids))) { 227 mask = BIT(INTEL_SUBPLATFORM_ULT); 228 } else if (find_devid(devid, subplatform_ulx_ids, 229 ARRAY_SIZE(subplatform_ulx_ids))) { 230 mask = BIT(INTEL_SUBPLATFORM_ULX); 231 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 232 /* ULX machines are also considered ULT. */ 233 mask |= BIT(INTEL_SUBPLATFORM_ULT); 234 } 235 } else if (find_devid(devid, subplatform_portf_ids, 236 ARRAY_SIZE(subplatform_portf_ids))) { 237 mask = BIT(INTEL_SUBPLATFORM_PORTF); 238 } else if (find_devid(devid, subplatform_uy_ids, 239 ARRAY_SIZE(subplatform_uy_ids))) { 240 mask = BIT(INTEL_SUBPLATFORM_UY); 241 } else if (find_devid(devid, subplatform_n_ids, 242 ARRAY_SIZE(subplatform_n_ids))) { 243 mask = BIT(INTEL_SUBPLATFORM_N); 244 } else if (find_devid(devid, subplatform_rpl_ids, 245 ARRAY_SIZE(subplatform_rpl_ids))) { 246 mask = BIT(INTEL_SUBPLATFORM_RPL); 247 } else if (find_devid(devid, subplatform_g10_ids, 248 ARRAY_SIZE(subplatform_g10_ids))) { 249 mask = BIT(INTEL_SUBPLATFORM_G10); 250 } else if (find_devid(devid, subplatform_g11_ids, 251 ARRAY_SIZE(subplatform_g11_ids))) { 252 mask = BIT(INTEL_SUBPLATFORM_G11); 253 } else if (find_devid(devid, subplatform_g12_ids, 254 ARRAY_SIZE(subplatform_g12_ids))) { 255 mask = BIT(INTEL_SUBPLATFORM_G12); 256 } 257 258 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 259 260 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 261 } 262 263 /** 264 * intel_device_info_runtime_init - initialize runtime info 265 * @dev_priv: the i915 device 266 * 267 * Determine various intel_device_info fields at runtime. 268 * 269 * Use it when either: 270 * - it's judged too laborious to fill n static structures with the limit 271 * when a simple if statement does the job, 272 * - run-time checks (eg read fuse/strap registers) are needed. 273 * 274 * This function needs to be called: 275 * - after the MMIO has been setup as we are reading registers, 276 * - after the PCH has been detected, 277 * - before the first usage of the fields it can tweak. 278 */ 279 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 280 { 281 struct intel_device_info *info = mkwrite_device_info(dev_priv); 282 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 283 enum pipe pipe; 284 285 /* Wa_14011765242: adl-s A0,A1 */ 286 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) 287 for_each_pipe(dev_priv, pipe) 288 runtime->num_scalers[pipe] = 0; 289 else if (DISPLAY_VER(dev_priv) >= 11) { 290 for_each_pipe(dev_priv, pipe) 291 runtime->num_scalers[pipe] = 2; 292 } else if (DISPLAY_VER(dev_priv) >= 9) { 293 runtime->num_scalers[PIPE_A] = 2; 294 runtime->num_scalers[PIPE_B] = 2; 295 runtime->num_scalers[PIPE_C] = 1; 296 } 297 298 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 299 300 if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 301 for_each_pipe(dev_priv, pipe) 302 runtime->num_sprites[pipe] = 4; 303 else if (DISPLAY_VER(dev_priv) >= 11) 304 for_each_pipe(dev_priv, pipe) 305 runtime->num_sprites[pipe] = 6; 306 else if (DISPLAY_VER(dev_priv) == 10) 307 for_each_pipe(dev_priv, pipe) 308 runtime->num_sprites[pipe] = 3; 309 else if (IS_BROXTON(dev_priv)) { 310 /* 311 * Skylake and Broxton currently don't expose the topmost plane as its 312 * use is exclusive with the legacy cursor and we only want to expose 313 * one of those, not both. Until we can safely expose the topmost plane 314 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 315 * we don't expose the topmost plane at all to prevent ABI breakage 316 * down the line. 317 */ 318 319 runtime->num_sprites[PIPE_A] = 2; 320 runtime->num_sprites[PIPE_B] = 2; 321 runtime->num_sprites[PIPE_C] = 1; 322 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 323 for_each_pipe(dev_priv, pipe) 324 runtime->num_sprites[pipe] = 2; 325 } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { 326 for_each_pipe(dev_priv, pipe) 327 runtime->num_sprites[pipe] = 1; 328 } 329 330 if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && 331 HAS_PCH_SPLIT(dev_priv)) { 332 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 333 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); 334 335 /* 336 * SFUSE_STRAP is supposed to have a bit signalling the display 337 * is fused off. Unfortunately it seems that, at least in 338 * certain cases, fused off display means that PCH display 339 * reads don't land anywhere. In that case, we read 0s. 340 * 341 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 342 * should be set when taking over after the firmware. 343 */ 344 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 345 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 346 (HAS_PCH_CPT(dev_priv) && 347 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 348 drm_info(&dev_priv->drm, 349 "Display fused off, disabling\n"); 350 info->display.pipe_mask = 0; 351 info->display.cpu_transcoder_mask = 0; 352 info->display.fbc_mask = 0; 353 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 354 drm_info(&dev_priv->drm, "PipeC fused off\n"); 355 info->display.pipe_mask &= ~BIT(PIPE_C); 356 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 357 } 358 } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { 359 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); 360 361 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 362 info->display.pipe_mask &= ~BIT(PIPE_A); 363 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 364 info->display.fbc_mask &= ~BIT(INTEL_FBC_A); 365 } 366 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 367 info->display.pipe_mask &= ~BIT(PIPE_B); 368 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 369 } 370 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 371 info->display.pipe_mask &= ~BIT(PIPE_C); 372 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 373 } 374 375 if (DISPLAY_VER(dev_priv) >= 12 && 376 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 377 info->display.pipe_mask &= ~BIT(PIPE_D); 378 info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 379 } 380 381 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 382 info->display.has_hdcp = 0; 383 384 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 385 info->display.fbc_mask = 0; 386 387 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 388 info->display.has_dmc = 0; 389 390 if (DISPLAY_VER(dev_priv) >= 10 && 391 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 392 info->display.has_dsc = 0; 393 } 394 395 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 396 drm_info(&dev_priv->drm, 397 "Disabling ppGTT for VT-d support\n"); 398 info->ppgtt_type = INTEL_PPGTT_NONE; 399 } 400 401 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 402 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 403 404 if (!HAS_DISPLAY(dev_priv)) { 405 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 406 DRIVER_ATOMIC); 407 memset(&info->display, 0, sizeof(info->display)); 408 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); 409 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); 410 } 411 } 412 413 void intel_driver_caps_print(const struct intel_driver_caps *caps, 414 struct drm_printer *p) 415 { 416 drm_printf(p, "Has logical contexts? %s\n", 417 str_yes_no(caps->has_logical_contexts)); 418 drm_printf(p, "scheduler: %x\n", caps->scheduler); 419 } 420