1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 #include <drm/i915_pciids.h> 27 28 #include "display/intel_cdclk.h" 29 #include "display/intel_de.h" 30 #include "intel_device_info.h" 31 #include "i915_drv.h" 32 33 #define PLATFORM_NAME(x) [INTEL_##x] = #x 34 static const char * const platform_names[] = { 35 PLATFORM_NAME(I830), 36 PLATFORM_NAME(I845G), 37 PLATFORM_NAME(I85X), 38 PLATFORM_NAME(I865G), 39 PLATFORM_NAME(I915G), 40 PLATFORM_NAME(I915GM), 41 PLATFORM_NAME(I945G), 42 PLATFORM_NAME(I945GM), 43 PLATFORM_NAME(G33), 44 PLATFORM_NAME(PINEVIEW), 45 PLATFORM_NAME(I965G), 46 PLATFORM_NAME(I965GM), 47 PLATFORM_NAME(G45), 48 PLATFORM_NAME(GM45), 49 PLATFORM_NAME(IRONLAKE), 50 PLATFORM_NAME(SANDYBRIDGE), 51 PLATFORM_NAME(IVYBRIDGE), 52 PLATFORM_NAME(VALLEYVIEW), 53 PLATFORM_NAME(HASWELL), 54 PLATFORM_NAME(BROADWELL), 55 PLATFORM_NAME(CHERRYVIEW), 56 PLATFORM_NAME(SKYLAKE), 57 PLATFORM_NAME(BROXTON), 58 PLATFORM_NAME(KABYLAKE), 59 PLATFORM_NAME(GEMINILAKE), 60 PLATFORM_NAME(COFFEELAKE), 61 PLATFORM_NAME(COMETLAKE), 62 PLATFORM_NAME(CANNONLAKE), 63 PLATFORM_NAME(ICELAKE), 64 PLATFORM_NAME(ELKHARTLAKE), 65 PLATFORM_NAME(JASPERLAKE), 66 PLATFORM_NAME(TIGERLAKE), 67 PLATFORM_NAME(ROCKETLAKE), 68 PLATFORM_NAME(DG1), 69 PLATFORM_NAME(ALDERLAKE_S), 70 }; 71 #undef PLATFORM_NAME 72 73 const char *intel_platform_name(enum intel_platform platform) 74 { 75 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 76 77 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 78 platform_names[platform] == NULL)) 79 return "<unknown>"; 80 81 return platform_names[platform]; 82 } 83 84 static const char *iommu_name(void) 85 { 86 const char *msg = "n/a"; 87 88 #ifdef CONFIG_INTEL_IOMMU 89 msg = enableddisabled(intel_iommu_gfx_mapped); 90 #endif 91 92 return msg; 93 } 94 95 void intel_device_info_print_static(const struct intel_device_info *info, 96 struct drm_printer *p) 97 { 98 drm_printf(p, "gen: %d\n", info->gen); 99 drm_printf(p, "gt: %d\n", info->gt); 100 drm_printf(p, "iommu: %s\n", iommu_name()); 101 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 102 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 103 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 104 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 105 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 106 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 107 108 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)) 109 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 110 #undef PRINT_FLAG 111 112 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 113 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 114 #undef PRINT_FLAG 115 } 116 117 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 118 struct drm_printer *p) 119 { 120 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 121 } 122 123 #undef INTEL_VGA_DEVICE 124 #define INTEL_VGA_DEVICE(id, info) (id) 125 126 static const u16 subplatform_ult_ids[] = { 127 INTEL_HSW_ULT_GT1_IDS(0), 128 INTEL_HSW_ULT_GT2_IDS(0), 129 INTEL_HSW_ULT_GT3_IDS(0), 130 INTEL_BDW_ULT_GT1_IDS(0), 131 INTEL_BDW_ULT_GT2_IDS(0), 132 INTEL_BDW_ULT_GT3_IDS(0), 133 INTEL_BDW_ULT_RSVD_IDS(0), 134 INTEL_SKL_ULT_GT1_IDS(0), 135 INTEL_SKL_ULT_GT2_IDS(0), 136 INTEL_SKL_ULT_GT3_IDS(0), 137 INTEL_KBL_ULT_GT1_IDS(0), 138 INTEL_KBL_ULT_GT2_IDS(0), 139 INTEL_KBL_ULT_GT3_IDS(0), 140 INTEL_CFL_U_GT2_IDS(0), 141 INTEL_CFL_U_GT3_IDS(0), 142 INTEL_WHL_U_GT1_IDS(0), 143 INTEL_WHL_U_GT2_IDS(0), 144 INTEL_WHL_U_GT3_IDS(0), 145 INTEL_CML_U_GT1_IDS(0), 146 INTEL_CML_U_GT2_IDS(0), 147 }; 148 149 static const u16 subplatform_ulx_ids[] = { 150 INTEL_HSW_ULX_GT1_IDS(0), 151 INTEL_HSW_ULX_GT2_IDS(0), 152 INTEL_BDW_ULX_GT1_IDS(0), 153 INTEL_BDW_ULX_GT2_IDS(0), 154 INTEL_BDW_ULX_GT3_IDS(0), 155 INTEL_BDW_ULX_RSVD_IDS(0), 156 INTEL_SKL_ULX_GT1_IDS(0), 157 INTEL_SKL_ULX_GT2_IDS(0), 158 INTEL_KBL_ULX_GT1_IDS(0), 159 INTEL_KBL_ULX_GT2_IDS(0), 160 INTEL_AML_KBL_GT2_IDS(0), 161 INTEL_AML_CFL_GT2_IDS(0), 162 }; 163 164 static const u16 subplatform_portf_ids[] = { 165 INTEL_CNL_PORT_F_IDS(0), 166 INTEL_ICL_PORT_F_IDS(0), 167 }; 168 169 static bool find_devid(u16 id, const u16 *p, unsigned int num) 170 { 171 for (; num; num--, p++) { 172 if (*p == id) 173 return true; 174 } 175 176 return false; 177 } 178 179 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 180 { 181 const struct intel_device_info *info = INTEL_INFO(i915); 182 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 183 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 184 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 185 u16 devid = INTEL_DEVID(i915); 186 u32 mask = 0; 187 188 /* Make sure IS_<platform> checks are working. */ 189 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 190 191 /* Find and mark subplatform bits based on the PCI device id. */ 192 if (find_devid(devid, subplatform_ult_ids, 193 ARRAY_SIZE(subplatform_ult_ids))) { 194 mask = BIT(INTEL_SUBPLATFORM_ULT); 195 } else if (find_devid(devid, subplatform_ulx_ids, 196 ARRAY_SIZE(subplatform_ulx_ids))) { 197 mask = BIT(INTEL_SUBPLATFORM_ULX); 198 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 199 /* ULX machines are also considered ULT. */ 200 mask |= BIT(INTEL_SUBPLATFORM_ULT); 201 } 202 } else if (find_devid(devid, subplatform_portf_ids, 203 ARRAY_SIZE(subplatform_portf_ids))) { 204 mask = BIT(INTEL_SUBPLATFORM_PORTF); 205 } 206 207 if (IS_TIGERLAKE(i915)) { 208 struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev); 209 210 root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list); 211 212 drm_WARN_ON(&i915->drm, mask); 213 drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) != 214 TGL_ROOT_DEVICE_ID); 215 216 switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) { 217 case TGL_ROOT_DEVICE_SKU_ULX: 218 mask = BIT(INTEL_SUBPLATFORM_ULX); 219 break; 220 case TGL_ROOT_DEVICE_SKU_ULT: 221 mask = BIT(INTEL_SUBPLATFORM_ULT); 222 break; 223 } 224 } 225 226 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 227 228 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 229 } 230 231 /** 232 * intel_device_info_runtime_init - initialize runtime info 233 * @dev_priv: the i915 device 234 * 235 * Determine various intel_device_info fields at runtime. 236 * 237 * Use it when either: 238 * - it's judged too laborious to fill n static structures with the limit 239 * when a simple if statement does the job, 240 * - run-time checks (eg read fuse/strap registers) are needed. 241 * 242 * This function needs to be called: 243 * - after the MMIO has been setup as we are reading registers, 244 * - after the PCH has been detected, 245 * - before the first usage of the fields it can tweak. 246 */ 247 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 248 { 249 struct intel_device_info *info = mkwrite_device_info(dev_priv); 250 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 251 enum pipe pipe; 252 253 /* Wa_14011765242: adl-s A0 */ 254 if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) 255 for_each_pipe(dev_priv, pipe) 256 runtime->num_scalers[pipe] = 0; 257 else if (INTEL_GEN(dev_priv) >= 10) { 258 for_each_pipe(dev_priv, pipe) 259 runtime->num_scalers[pipe] = 2; 260 } else if (IS_GEN(dev_priv, 9)) { 261 runtime->num_scalers[PIPE_A] = 2; 262 runtime->num_scalers[PIPE_B] = 2; 263 runtime->num_scalers[PIPE_C] = 1; 264 } 265 266 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 267 268 if (HAS_D12_PLANE_MINIMIZATION(dev_priv)) 269 for_each_pipe(dev_priv, pipe) 270 runtime->num_sprites[pipe] = 4; 271 else if (INTEL_GEN(dev_priv) >= 11) 272 for_each_pipe(dev_priv, pipe) 273 runtime->num_sprites[pipe] = 6; 274 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) 275 for_each_pipe(dev_priv, pipe) 276 runtime->num_sprites[pipe] = 3; 277 else if (IS_BROXTON(dev_priv)) { 278 /* 279 * Skylake and Broxton currently don't expose the topmost plane as its 280 * use is exclusive with the legacy cursor and we only want to expose 281 * one of those, not both. Until we can safely expose the topmost plane 282 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 283 * we don't expose the topmost plane at all to prevent ABI breakage 284 * down the line. 285 */ 286 287 runtime->num_sprites[PIPE_A] = 2; 288 runtime->num_sprites[PIPE_B] = 2; 289 runtime->num_sprites[PIPE_C] = 1; 290 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 291 for_each_pipe(dev_priv, pipe) 292 runtime->num_sprites[pipe] = 2; 293 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 294 for_each_pipe(dev_priv, pipe) 295 runtime->num_sprites[pipe] = 1; 296 } 297 298 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && 299 HAS_PCH_SPLIT(dev_priv)) { 300 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); 301 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); 302 303 /* 304 * SFUSE_STRAP is supposed to have a bit signalling the display 305 * is fused off. Unfortunately it seems that, at least in 306 * certain cases, fused off display means that PCH display 307 * reads don't land anywhere. In that case, we read 0s. 308 * 309 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 310 * should be set when taking over after the firmware. 311 */ 312 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 313 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 314 (HAS_PCH_CPT(dev_priv) && 315 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 316 drm_info(&dev_priv->drm, 317 "Display fused off, disabling\n"); 318 info->pipe_mask = 0; 319 info->cpu_transcoder_mask = 0; 320 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 321 drm_info(&dev_priv->drm, "PipeC fused off\n"); 322 info->pipe_mask &= ~BIT(PIPE_C); 323 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 324 } 325 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { 326 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); 327 328 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 329 info->pipe_mask &= ~BIT(PIPE_A); 330 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 331 } 332 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 333 info->pipe_mask &= ~BIT(PIPE_B); 334 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 335 } 336 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 337 info->pipe_mask &= ~BIT(PIPE_C); 338 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 339 } 340 if (INTEL_GEN(dev_priv) >= 12 && 341 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 342 info->pipe_mask &= ~BIT(PIPE_D); 343 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 344 } 345 346 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 347 info->display.has_hdcp = 0; 348 349 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 350 info->display.has_fbc = 0; 351 352 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 353 info->display.has_csr = 0; 354 355 if (INTEL_GEN(dev_priv) >= 10 && 356 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 357 info->display.has_dsc = 0; 358 } 359 360 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { 361 drm_info(&dev_priv->drm, 362 "Disabling ppGTT for VT-d support\n"); 363 info->ppgtt_type = INTEL_PPGTT_NONE; 364 } 365 366 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 367 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 368 369 if (!HAS_DISPLAY(dev_priv)) { 370 dev_priv->drm.driver_features &= ~(DRIVER_MODESET | 371 DRIVER_ATOMIC); 372 memset(&info->display, 0, sizeof(info->display)); 373 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); 374 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); 375 } 376 } 377 378 void intel_driver_caps_print(const struct intel_driver_caps *caps, 379 struct drm_printer *p) 380 { 381 drm_printf(p, "Has logical contexts? %s\n", 382 yesno(caps->has_logical_contexts)); 383 drm_printf(p, "scheduler: %x\n", caps->scheduler); 384 } 385