1 /* 2 * Copyright(c) 2011-2015 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef _I915_VGPU_H_ 25 #define _I915_VGPU_H_ 26 27 /* The MMIO offset of the shared info between guest and host emulator */ 28 #define VGT_PVINFO_PAGE 0x78000 29 #define VGT_PVINFO_SIZE 0x1000 30 31 /* 32 * The following structure pages are defined in GEN MMIO space 33 * for virtualization. (One page for now) 34 */ 35 #define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */ 36 #define VGT_VERSION_MAJOR 1 37 #define VGT_VERSION_MINOR 0 38 39 #define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor)) 40 #define INTEL_VGT_IF_VERSION \ 41 INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR) 42 43 struct vgt_if { 44 uint64_t magic; /* VGT_MAGIC */ 45 uint16_t version_major; 46 uint16_t version_minor; 47 uint32_t vgt_id; /* ID of vGT instance */ 48 uint32_t rsv1[12]; /* pad to offset 0x40 */ 49 /* 50 * Data structure to describe the balooning info of resources. 51 * Each VM can only have one portion of continuous area for now. 52 * (May support scattered resource in future) 53 * (starting from offset 0x40) 54 */ 55 struct { 56 /* Aperture register balooning */ 57 struct { 58 uint32_t base; 59 uint32_t size; 60 } mappable_gmadr; /* aperture */ 61 /* GMADR register balooning */ 62 struct { 63 uint32_t base; 64 uint32_t size; 65 } nonmappable_gmadr; /* non aperture */ 66 /* allowed fence registers */ 67 uint32_t fence_num; 68 uint32_t rsv2[3]; 69 } avail_rs; /* available/assigned resource */ 70 uint32_t rsv3[0x200 - 24]; /* pad to half page */ 71 /* 72 * The bottom half page is for response from Gfx driver to hypervisor. 73 * Set to reserved fields temporarily by now. 74 */ 75 uint32_t rsv4; 76 uint32_t display_ready; /* ready for display owner switch */ 77 uint32_t rsv5[0x200 - 2]; /* pad to one page */ 78 } __packed; 79 80 #define vgtif_reg(x) \ 81 (VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x) 82 83 /* vGPU display status to be used by the host side */ 84 #define VGT_DRV_DISPLAY_NOT_READY 0 85 #define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */ 86 87 extern void i915_check_vgpu(struct drm_device *dev); 88 extern int intel_vgt_balloon(struct drm_device *dev); 89 extern void intel_vgt_deballoon(void); 90 91 #endif /* _I915_VGPU_H_ */ 92