1 /*
2  *
3  * Copyright 2008 (c) Intel Corporation
4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 
27 #include <drm/i915_drm.h>
28 
29 #include "i915_reg.h"
30 #include "intel_drv.h"
31 #include "intel_fbc.h"
32 #include "intel_gmbus.h"
33 
34 static void i915_save_display(struct drm_i915_private *dev_priv)
35 {
36 	/* Display arbitration control */
37 	if (INTEL_GEN(dev_priv) <= 4)
38 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
39 
40 	/* save FBC interval */
41 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
42 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
43 }
44 
45 static void i915_restore_display(struct drm_i915_private *dev_priv)
46 {
47 	/* Display arbitration */
48 	if (INTEL_GEN(dev_priv) <= 4)
49 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
50 
51 	/* only restore FBC info on the platform that supports FBC*/
52 	intel_fbc_global_disable(dev_priv);
53 
54 	/* restore FBC interval */
55 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
56 		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
57 
58 	i915_redisable_vga(dev_priv);
59 }
60 
61 int i915_save_state(struct drm_i915_private *dev_priv)
62 {
63 	struct pci_dev *pdev = dev_priv->drm.pdev;
64 	int i;
65 
66 	mutex_lock(&dev_priv->drm.struct_mutex);
67 
68 	i915_save_display(dev_priv);
69 
70 	if (IS_GEN(dev_priv, 4))
71 		pci_read_config_word(pdev, GCDGMBUS,
72 				     &dev_priv->regfile.saveGCDGMBUS);
73 
74 	/* Cache mode state */
75 	if (INTEL_GEN(dev_priv) < 7)
76 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
77 
78 	/* Memory Arbitration state */
79 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
80 
81 	/* Scratch space */
82 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
83 		for (i = 0; i < 7; i++) {
84 			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
85 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
86 		}
87 		for (i = 0; i < 3; i++)
88 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
89 	} else if (IS_GEN(dev_priv, 2)) {
90 		for (i = 0; i < 7; i++)
91 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
92 	} else if (HAS_GMCH(dev_priv)) {
93 		for (i = 0; i < 16; i++) {
94 			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
95 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
96 		}
97 		for (i = 0; i < 3; i++)
98 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
99 	}
100 
101 	mutex_unlock(&dev_priv->drm.struct_mutex);
102 
103 	return 0;
104 }
105 
106 int i915_restore_state(struct drm_i915_private *dev_priv)
107 {
108 	struct pci_dev *pdev = dev_priv->drm.pdev;
109 	int i;
110 
111 	mutex_lock(&dev_priv->drm.struct_mutex);
112 
113 	if (IS_GEN(dev_priv, 4))
114 		pci_write_config_word(pdev, GCDGMBUS,
115 				      dev_priv->regfile.saveGCDGMBUS);
116 	i915_restore_display(dev_priv);
117 
118 	/* Cache mode state */
119 	if (INTEL_GEN(dev_priv) < 7)
120 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
121 			   0xffff0000);
122 
123 	/* Memory arbitration state */
124 	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
125 
126 	/* Scratch space */
127 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
128 		for (i = 0; i < 7; i++) {
129 			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
130 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
131 		}
132 		for (i = 0; i < 3; i++)
133 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
134 	} else if (IS_GEN(dev_priv, 2)) {
135 		for (i = 0; i < 7; i++)
136 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
137 	} else if (HAS_GMCH(dev_priv)) {
138 		for (i = 0; i < 16; i++) {
139 			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
140 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
141 		}
142 		for (i = 0; i < 3; i++)
143 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
144 	}
145 
146 	mutex_unlock(&dev_priv->drm.struct_mutex);
147 
148 	intel_gmbus_reset(dev_priv);
149 
150 	return 0;
151 }
152