1 /*
2  *
3  * Copyright 2008 (c) Intel Corporation
4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 
27 #include "display/intel_fbc.h"
28 #include "display/intel_gmbus.h"
29 #include "display/intel_vga.h"
30 
31 #include "i915_drv.h"
32 #include "i915_reg.h"
33 #include "i915_suspend.h"
34 
35 static void i915_save_display(struct drm_i915_private *dev_priv)
36 {
37 	/* Display arbitration control */
38 	if (INTEL_GEN(dev_priv) <= 4)
39 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
40 
41 	/* save FBC interval */
42 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
43 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
44 }
45 
46 static void i915_restore_display(struct drm_i915_private *dev_priv)
47 {
48 	/* Display arbitration */
49 	if (INTEL_GEN(dev_priv) <= 4)
50 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
51 
52 	/* only restore FBC info on the platform that supports FBC*/
53 	intel_fbc_global_disable(dev_priv);
54 
55 	/* restore FBC interval */
56 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
57 		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
58 
59 	intel_vga_redisable(dev_priv);
60 }
61 
62 int i915_save_state(struct drm_i915_private *dev_priv)
63 {
64 	struct pci_dev *pdev = dev_priv->drm.pdev;
65 	int i;
66 
67 	i915_save_display(dev_priv);
68 
69 	if (IS_GEN(dev_priv, 4))
70 		pci_read_config_word(pdev, GCDGMBUS,
71 				     &dev_priv->regfile.saveGCDGMBUS);
72 
73 	/* Cache mode state */
74 	if (INTEL_GEN(dev_priv) < 7)
75 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
76 
77 	/* Memory Arbitration state */
78 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
79 
80 	/* Scratch space */
81 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
82 		for (i = 0; i < 7; i++) {
83 			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
84 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
85 		}
86 		for (i = 0; i < 3; i++)
87 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
88 	} else if (IS_GEN(dev_priv, 2)) {
89 		for (i = 0; i < 7; i++)
90 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
91 	} else if (HAS_GMCH(dev_priv)) {
92 		for (i = 0; i < 16; i++) {
93 			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
94 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
95 		}
96 		for (i = 0; i < 3; i++)
97 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
98 	}
99 
100 	return 0;
101 }
102 
103 int i915_restore_state(struct drm_i915_private *dev_priv)
104 {
105 	struct pci_dev *pdev = dev_priv->drm.pdev;
106 	int i;
107 
108 	if (IS_GEN(dev_priv, 4))
109 		pci_write_config_word(pdev, GCDGMBUS,
110 				      dev_priv->regfile.saveGCDGMBUS);
111 	i915_restore_display(dev_priv);
112 
113 	/* Cache mode state */
114 	if (INTEL_GEN(dev_priv) < 7)
115 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
116 			   0xffff0000);
117 
118 	/* Memory arbitration state */
119 	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
120 
121 	/* Scratch space */
122 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
123 		for (i = 0; i < 7; i++) {
124 			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
125 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
126 		}
127 		for (i = 0; i < 3; i++)
128 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
129 	} else if (IS_GEN(dev_priv, 2)) {
130 		for (i = 0; i < 7; i++)
131 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
132 	} else if (HAS_GMCH(dev_priv)) {
133 		for (i = 0; i < 16; i++) {
134 			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
135 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
136 		}
137 		for (i = 0; i < 3; i++)
138 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
139 	}
140 
141 	intel_gmbus_reset(dev_priv);
142 
143 	return 0;
144 }
145