1 /*
2  *
3  * Copyright 2008 (c) Intel Corporation
4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 
27 #include <drm/i915_drm.h>
28 #include "intel_drv.h"
29 #include "i915_reg.h"
30 
31 static void i915_save_display(struct drm_i915_private *dev_priv)
32 {
33 	/* Display arbitration control */
34 	if (INTEL_GEN(dev_priv) <= 4)
35 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
36 
37 	/* save FBC interval */
38 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
39 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
40 }
41 
42 static void i915_restore_display(struct drm_i915_private *dev_priv)
43 {
44 	/* Display arbitration */
45 	if (INTEL_GEN(dev_priv) <= 4)
46 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
47 
48 	/* only restore FBC info on the platform that supports FBC*/
49 	intel_fbc_global_disable(dev_priv);
50 
51 	/* restore FBC interval */
52 	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
53 		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
54 
55 	i915_redisable_vga(dev_priv);
56 }
57 
58 int i915_save_state(struct drm_i915_private *dev_priv)
59 {
60 	struct pci_dev *pdev = dev_priv->drm.pdev;
61 	int i;
62 
63 	mutex_lock(&dev_priv->drm.struct_mutex);
64 
65 	i915_save_display(dev_priv);
66 
67 	if (IS_GEN(dev_priv, 4))
68 		pci_read_config_word(pdev, GCDGMBUS,
69 				     &dev_priv->regfile.saveGCDGMBUS);
70 
71 	/* Cache mode state */
72 	if (INTEL_GEN(dev_priv) < 7)
73 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
74 
75 	/* Memory Arbitration state */
76 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
77 
78 	/* Scratch space */
79 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
80 		for (i = 0; i < 7; i++) {
81 			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
82 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
83 		}
84 		for (i = 0; i < 3; i++)
85 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
86 	} else if (IS_GEN(dev_priv, 2)) {
87 		for (i = 0; i < 7; i++)
88 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
89 	} else if (HAS_GMCH(dev_priv)) {
90 		for (i = 0; i < 16; i++) {
91 			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
92 			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
93 		}
94 		for (i = 0; i < 3; i++)
95 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
96 	}
97 
98 	mutex_unlock(&dev_priv->drm.struct_mutex);
99 
100 	return 0;
101 }
102 
103 int i915_restore_state(struct drm_i915_private *dev_priv)
104 {
105 	struct pci_dev *pdev = dev_priv->drm.pdev;
106 	int i;
107 
108 	mutex_lock(&dev_priv->drm.struct_mutex);
109 
110 	if (IS_GEN(dev_priv, 4))
111 		pci_write_config_word(pdev, GCDGMBUS,
112 				      dev_priv->regfile.saveGCDGMBUS);
113 	i915_restore_display(dev_priv);
114 
115 	/* Cache mode state */
116 	if (INTEL_GEN(dev_priv) < 7)
117 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
118 			   0xffff0000);
119 
120 	/* Memory arbitration state */
121 	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
122 
123 	/* Scratch space */
124 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
125 		for (i = 0; i < 7; i++) {
126 			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
127 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
128 		}
129 		for (i = 0; i < 3; i++)
130 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
131 	} else if (IS_GEN(dev_priv, 2)) {
132 		for (i = 0; i < 7; i++)
133 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
134 	} else if (HAS_GMCH(dev_priv)) {
135 		for (i = 0; i < 16; i++) {
136 			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
137 			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
138 		}
139 		for (i = 0; i < 3; i++)
140 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
141 	}
142 
143 	mutex_unlock(&dev_priv->drm.struct_mutex);
144 
145 	intel_i2c_reset(dev_priv);
146 
147 	return 0;
148 }
149