1 /*
2  * Copyright © 2008-2018 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #ifndef I915_REQUEST_H
26 #define I915_REQUEST_H
27 
28 #include <linux/dma-fence.h>
29 #include <linux/irq_work.h>
30 #include <linux/lockdep.h>
31 
32 #include "gem/i915_gem_context_types.h"
33 #include "gt/intel_context_types.h"
34 #include "gt/intel_engine_types.h"
35 #include "gt/intel_timeline_types.h"
36 
37 #include "i915_gem.h"
38 #include "i915_scheduler.h"
39 #include "i915_selftest.h"
40 #include "i915_sw_fence.h"
41 
42 #include <uapi/drm/i915_drm.h>
43 
44 struct drm_file;
45 struct drm_i915_gem_object;
46 struct i915_request;
47 
48 struct i915_capture_list {
49 	struct i915_capture_list *next;
50 	struct i915_vma *vma;
51 };
52 
53 #define RQ_TRACE(rq, fmt, ...) do {					\
54 	const struct i915_request *rq__ = (rq);				\
55 	ENGINE_TRACE(rq__->engine, "fence %llx:%lld, current %d " fmt,	\
56 		     rq__->fence.context, rq__->fence.seqno,		\
57 		     hwsp_seqno(rq__), ##__VA_ARGS__);			\
58 } while (0)
59 
60 enum {
61 	/*
62 	 * I915_FENCE_FLAG_ACTIVE - this request is currently submitted to HW.
63 	 *
64 	 * Set by __i915_request_submit() on handing over to HW, and cleared
65 	 * by __i915_request_unsubmit() if we preempt this request.
66 	 *
67 	 * Finally cleared for consistency on retiring the request, when
68 	 * we know the HW is no longer running this request.
69 	 *
70 	 * See i915_request_is_active()
71 	 */
72 	I915_FENCE_FLAG_ACTIVE = DMA_FENCE_FLAG_USER_BITS,
73 
74 	/*
75 	 * I915_FENCE_FLAG_PQUEUE - this request is ready for execution
76 	 *
77 	 * Using the scheduler, when a request is ready for execution it is put
78 	 * into the priority queue, and removed from that queue when transferred
79 	 * to the HW runlists. We want to track its membership within the
80 	 * priority queue so that we can easily check before rescheduling.
81 	 *
82 	 * See i915_request_in_priority_queue()
83 	 */
84 	I915_FENCE_FLAG_PQUEUE,
85 
86 	/*
87 	 * I915_FENCE_FLAG_HOLD - this request is currently on hold
88 	 *
89 	 * This request has been suspended, pending an ongoing investigation.
90 	 */
91 	I915_FENCE_FLAG_HOLD,
92 
93 	/*
94 	 * I915_FENCE_FLAG_INITIAL_BREADCRUMB - this request has the initial
95 	 * breadcrumb that marks the end of semaphore waits and start of the
96 	 * user payload.
97 	 */
98 	I915_FENCE_FLAG_INITIAL_BREADCRUMB,
99 
100 	/*
101 	 * I915_FENCE_FLAG_SIGNAL - this request is currently on signal_list
102 	 *
103 	 * Internal bookkeeping used by the breadcrumb code to track when
104 	 * a request is on the various signal_list.
105 	 */
106 	I915_FENCE_FLAG_SIGNAL,
107 
108 	/*
109 	 * I915_FENCE_FLAG_NOPREEMPT - this request should not be preempted
110 	 *
111 	 * The execution of some requests should not be interrupted. This is
112 	 * a sensitive operation as it makes the request super important,
113 	 * blocking other higher priority work. Abuse of this flag will
114 	 * lead to quality of service issues.
115 	 */
116 	I915_FENCE_FLAG_NOPREEMPT,
117 
118 	/*
119 	 * I915_FENCE_FLAG_SENTINEL - this request should be last in the queue
120 	 *
121 	 * A high priority sentinel request may be submitted to clear the
122 	 * submission queue. As it will be the only request in-flight, upon
123 	 * execution all other active requests will have been preempted and
124 	 * unsubmitted. This preemptive pulse is used to re-evaluate the
125 	 * in-flight requests, particularly in cases where an active context
126 	 * is banned and those active requests need to be cancelled.
127 	 */
128 	I915_FENCE_FLAG_SENTINEL,
129 
130 	/*
131 	 * I915_FENCE_FLAG_BOOST - upclock the gpu for this request
132 	 *
133 	 * Some requests are more important than others! In particular, a
134 	 * request that the user is waiting on is typically required for
135 	 * interactive latency, for which we want to minimise by upclocking
136 	 * the GPU. Here we track such boost requests on a per-request basis.
137 	 */
138 	I915_FENCE_FLAG_BOOST,
139 };
140 
141 /**
142  * Request queue structure.
143  *
144  * The request queue allows us to note sequence numbers that have been emitted
145  * and may be associated with active buffers to be retired.
146  *
147  * By keeping this list, we can avoid having to do questionable sequence
148  * number comparisons on buffer last_read|write_seqno. It also allows an
149  * emission time to be associated with the request for tracking how far ahead
150  * of the GPU the submission is.
151  *
152  * When modifying this structure be very aware that we perform a lockless
153  * RCU lookup of it that may race against reallocation of the struct
154  * from the slab freelist. We intentionally do not zero the structure on
155  * allocation so that the lookup can use the dangling pointers (and is
156  * cogniscent that those pointers may be wrong). Instead, everything that
157  * needs to be initialised must be done so explicitly.
158  *
159  * The requests are reference counted.
160  */
161 struct i915_request {
162 	struct dma_fence fence;
163 	spinlock_t lock;
164 
165 	/**
166 	 * Context and ring buffer related to this request
167 	 * Contexts are refcounted, so when this request is associated with a
168 	 * context, we must increment the context's refcount, to guarantee that
169 	 * it persists while any request is linked to it. Requests themselves
170 	 * are also refcounted, so the request will only be freed when the last
171 	 * reference to it is dismissed, and the code in
172 	 * i915_request_free() will then decrement the refcount on the
173 	 * context.
174 	 */
175 	struct intel_engine_cs *engine;
176 	struct intel_context *context;
177 	struct intel_ring *ring;
178 	struct intel_timeline __rcu *timeline;
179 
180 	union {
181 		struct list_head signal_link;
182 		struct llist_node signal_node;
183 	};
184 
185 	/*
186 	 * The rcu epoch of when this request was allocated. Used to judiciously
187 	 * apply backpressure on future allocations to ensure that under
188 	 * mempressure there is sufficient RCU ticks for us to reclaim our
189 	 * RCU protected slabs.
190 	 */
191 	unsigned long rcustate;
192 
193 	/*
194 	 * We pin the timeline->mutex while constructing the request to
195 	 * ensure that no caller accidentally drops it during construction.
196 	 * The timeline->mutex must be held to ensure that only this caller
197 	 * can use the ring and manipulate the associated timeline during
198 	 * construction.
199 	 */
200 	struct pin_cookie cookie;
201 
202 	/*
203 	 * Fences for the various phases in the request's lifetime.
204 	 *
205 	 * The submit fence is used to await upon all of the request's
206 	 * dependencies. When it is signaled, the request is ready to run.
207 	 * It is used by the driver to then queue the request for execution.
208 	 */
209 	struct i915_sw_fence submit;
210 	union {
211 		wait_queue_entry_t submitq;
212 		struct i915_sw_dma_fence_cb dmaq;
213 		struct i915_request_duration_cb {
214 			struct dma_fence_cb cb;
215 			ktime_t emitted;
216 		} duration;
217 	};
218 	struct llist_head execute_cb;
219 	struct i915_sw_fence semaphore;
220 
221 	/*
222 	 * A list of everyone we wait upon, and everyone who waits upon us.
223 	 * Even though we will not be submitted to the hardware before the
224 	 * submit fence is signaled (it waits for all external events as well
225 	 * as our own requests), the scheduler still needs to know the
226 	 * dependency tree for the lifetime of the request (from execbuf
227 	 * to retirement), i.e. bidirectional dependency information for the
228 	 * request not tied to individual fences.
229 	 */
230 	struct i915_sched_node sched;
231 	struct i915_dependency dep;
232 	intel_engine_mask_t execution_mask;
233 
234 	/*
235 	 * A convenience pointer to the current breadcrumb value stored in
236 	 * the HW status page (or our timeline's local equivalent). The full
237 	 * path would be rq->hw_context->ring->timeline->hwsp_seqno.
238 	 */
239 	const u32 *hwsp_seqno;
240 
241 	/*
242 	 * If we need to access the timeline's seqno for this request in
243 	 * another request, we need to keep a read reference to this associated
244 	 * cacheline, so that we do not free and recycle it before the foreign
245 	 * observers have completed. Hence, we keep a pointer to the cacheline
246 	 * inside the timeline's HWSP vma, but it is only valid while this
247 	 * request has not completed and guarded by the timeline mutex.
248 	 */
249 	struct intel_timeline_cacheline __rcu *hwsp_cacheline;
250 
251 	/** Position in the ring of the start of the request */
252 	u32 head;
253 
254 	/** Position in the ring of the start of the user packets */
255 	u32 infix;
256 
257 	/**
258 	 * Position in the ring of the start of the postfix.
259 	 * This is required to calculate the maximum available ring space
260 	 * without overwriting the postfix.
261 	 */
262 	u32 postfix;
263 
264 	/** Position in the ring of the end of the whole request */
265 	u32 tail;
266 
267 	/** Position in the ring of the end of any workarounds after the tail */
268 	u32 wa_tail;
269 
270 	/** Preallocate space in the ring for the emitting the request */
271 	u32 reserved_space;
272 
273 	/** Batch buffer related to this request if any (used for
274 	 * error state dump only).
275 	 */
276 	struct i915_vma *batch;
277 	/**
278 	 * Additional buffers requested by userspace to be captured upon
279 	 * a GPU hang. The vma/obj on this list are protected by their
280 	 * active reference - all objects on this list must also be
281 	 * on the active_list (of their final request).
282 	 */
283 	struct i915_capture_list *capture_list;
284 
285 	/** Time at which this request was emitted, in jiffies. */
286 	unsigned long emitted_jiffies;
287 
288 	/** timeline->request entry for this request */
289 	struct list_head link;
290 
291 	I915_SELFTEST_DECLARE(struct {
292 		struct list_head link;
293 		unsigned long delay;
294 	} mock;)
295 };
296 
297 #define I915_FENCE_GFP (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
298 
299 extern const struct dma_fence_ops i915_fence_ops;
300 
301 static inline bool dma_fence_is_i915(const struct dma_fence *fence)
302 {
303 	return fence->ops == &i915_fence_ops;
304 }
305 
306 struct kmem_cache *i915_request_slab_cache(void);
307 
308 struct i915_request * __must_check
309 __i915_request_create(struct intel_context *ce, gfp_t gfp);
310 struct i915_request * __must_check
311 i915_request_create(struct intel_context *ce);
312 
313 void i915_request_set_error_once(struct i915_request *rq, int error);
314 void __i915_request_skip(struct i915_request *rq);
315 
316 struct i915_request *__i915_request_commit(struct i915_request *request);
317 void __i915_request_queue(struct i915_request *rq,
318 			  const struct i915_sched_attr *attr);
319 
320 bool i915_request_retire(struct i915_request *rq);
321 void i915_request_retire_upto(struct i915_request *rq);
322 
323 static inline struct i915_request *
324 to_request(struct dma_fence *fence)
325 {
326 	/* We assume that NULL fence/request are interoperable */
327 	BUILD_BUG_ON(offsetof(struct i915_request, fence) != 0);
328 	GEM_BUG_ON(fence && !dma_fence_is_i915(fence));
329 	return container_of(fence, struct i915_request, fence);
330 }
331 
332 static inline struct i915_request *
333 i915_request_get(struct i915_request *rq)
334 {
335 	return to_request(dma_fence_get(&rq->fence));
336 }
337 
338 static inline struct i915_request *
339 i915_request_get_rcu(struct i915_request *rq)
340 {
341 	return to_request(dma_fence_get_rcu(&rq->fence));
342 }
343 
344 static inline void
345 i915_request_put(struct i915_request *rq)
346 {
347 	dma_fence_put(&rq->fence);
348 }
349 
350 int i915_request_await_object(struct i915_request *to,
351 			      struct drm_i915_gem_object *obj,
352 			      bool write);
353 int i915_request_await_dma_fence(struct i915_request *rq,
354 				 struct dma_fence *fence);
355 int i915_request_await_execution(struct i915_request *rq,
356 				 struct dma_fence *fence,
357 				 void (*hook)(struct i915_request *rq,
358 					      struct dma_fence *signal));
359 
360 void i915_request_add(struct i915_request *rq);
361 
362 bool __i915_request_submit(struct i915_request *request);
363 void i915_request_submit(struct i915_request *request);
364 
365 void __i915_request_unsubmit(struct i915_request *request);
366 void i915_request_unsubmit(struct i915_request *request);
367 
368 long i915_request_wait(struct i915_request *rq,
369 		       unsigned int flags,
370 		       long timeout)
371 	__attribute__((nonnull(1)));
372 #define I915_WAIT_INTERRUPTIBLE	BIT(0)
373 #define I915_WAIT_PRIORITY	BIT(1) /* small priority bump for the request */
374 #define I915_WAIT_ALL		BIT(2) /* used by i915_gem_object_wait() */
375 
376 static inline bool i915_request_signaled(const struct i915_request *rq)
377 {
378 	/* The request may live longer than its HWSP, so check flags first! */
379 	return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags);
380 }
381 
382 static inline bool i915_request_is_active(const struct i915_request *rq)
383 {
384 	return test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
385 }
386 
387 static inline bool i915_request_in_priority_queue(const struct i915_request *rq)
388 {
389 	return test_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
390 }
391 
392 static inline bool
393 i915_request_has_initial_breadcrumb(const struct i915_request *rq)
394 {
395 	return test_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
396 }
397 
398 /**
399  * Returns true if seq1 is later than seq2.
400  */
401 static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
402 {
403 	return (s32)(seq1 - seq2) >= 0;
404 }
405 
406 static inline u32 __hwsp_seqno(const struct i915_request *rq)
407 {
408 	const u32 *hwsp = READ_ONCE(rq->hwsp_seqno);
409 
410 	return READ_ONCE(*hwsp);
411 }
412 
413 /**
414  * hwsp_seqno - the current breadcrumb value in the HW status page
415  * @rq: the request, to chase the relevant HW status page
416  *
417  * The emphasis in naming here is that hwsp_seqno() is not a property of the
418  * request, but an indication of the current HW state (associated with this
419  * request). Its value will change as the GPU executes more requests.
420  *
421  * Returns the current breadcrumb value in the associated HW status page (or
422  * the local timeline's equivalent) for this request. The request itself
423  * has the associated breadcrumb value of rq->fence.seqno, when the HW
424  * status page has that breadcrumb or later, this request is complete.
425  */
426 static inline u32 hwsp_seqno(const struct i915_request *rq)
427 {
428 	u32 seqno;
429 
430 	rcu_read_lock(); /* the HWSP may be freed at runtime */
431 	seqno = __hwsp_seqno(rq);
432 	rcu_read_unlock();
433 
434 	return seqno;
435 }
436 
437 static inline bool __i915_request_has_started(const struct i915_request *rq)
438 {
439 	return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno - 1);
440 }
441 
442 /**
443  * i915_request_started - check if the request has begun being executed
444  * @rq: the request
445  *
446  * If the timeline is not using initial breadcrumbs, a request is
447  * considered started if the previous request on its timeline (i.e.
448  * context) has been signaled.
449  *
450  * If the timeline is using semaphores, it will also be emitting an
451  * "initial breadcrumb" after the semaphores are complete and just before
452  * it began executing the user payload. A request can therefore be active
453  * on the HW and not yet started as it is still busywaiting on its
454  * dependencies (via HW semaphores).
455  *
456  * If the request has started, its dependencies will have been signaled
457  * (either by fences or by semaphores) and it will have begun processing
458  * the user payload.
459  *
460  * However, even if a request has started, it may have been preempted and
461  * so no longer active, or it may have already completed.
462  *
463  * See also i915_request_is_active().
464  *
465  * Returns true if the request has begun executing the user payload, or
466  * has completed:
467  */
468 static inline bool i915_request_started(const struct i915_request *rq)
469 {
470 	if (i915_request_signaled(rq))
471 		return true;
472 
473 	/* Remember: started but may have since been preempted! */
474 	return __i915_request_has_started(rq);
475 }
476 
477 /**
478  * i915_request_is_running - check if the request may actually be executing
479  * @rq: the request
480  *
481  * Returns true if the request is currently submitted to hardware, has passed
482  * its start point (i.e. the context is setup and not busywaiting). Note that
483  * it may no longer be running by the time the function returns!
484  */
485 static inline bool i915_request_is_running(const struct i915_request *rq)
486 {
487 	if (!i915_request_is_active(rq))
488 		return false;
489 
490 	return __i915_request_has_started(rq);
491 }
492 
493 /**
494  * i915_request_is_ready - check if the request is ready for execution
495  * @rq: the request
496  *
497  * Upon construction, the request is instructed to wait upon various
498  * signals before it is ready to be executed by the HW. That is, we do
499  * not want to start execution and read data before it is written. In practice,
500  * this is controlled with a mixture of interrupts and semaphores. Once
501  * the submit fence is completed, the backend scheduler will place the
502  * request into its queue and from there submit it for execution. So we
503  * can detect when a request is eligible for execution (and is under control
504  * of the scheduler) by querying where it is in any of the scheduler's lists.
505  *
506  * Returns true if the request is ready for execution (it may be inflight),
507  * false otherwise.
508  */
509 static inline bool i915_request_is_ready(const struct i915_request *rq)
510 {
511 	return !list_empty(&rq->sched.link);
512 }
513 
514 static inline bool i915_request_completed(const struct i915_request *rq)
515 {
516 	if (i915_request_signaled(rq))
517 		return true;
518 
519 	return i915_seqno_passed(hwsp_seqno(rq), rq->fence.seqno);
520 }
521 
522 static inline void i915_request_mark_complete(struct i915_request *rq)
523 {
524 	WRITE_ONCE(rq->hwsp_seqno, /* decouple from HWSP */
525 		   (u32 *)&rq->fence.seqno);
526 }
527 
528 static inline bool i915_request_has_waitboost(const struct i915_request *rq)
529 {
530 	return test_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags);
531 }
532 
533 static inline bool i915_request_has_nopreempt(const struct i915_request *rq)
534 {
535 	/* Preemption should only be disabled very rarely */
536 	return unlikely(test_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags));
537 }
538 
539 static inline bool i915_request_has_sentinel(const struct i915_request *rq)
540 {
541 	return unlikely(test_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags));
542 }
543 
544 static inline bool i915_request_on_hold(const struct i915_request *rq)
545 {
546 	return unlikely(test_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags));
547 }
548 
549 static inline void i915_request_set_hold(struct i915_request *rq)
550 {
551 	set_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
552 }
553 
554 static inline void i915_request_clear_hold(struct i915_request *rq)
555 {
556 	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
557 }
558 
559 static inline struct intel_timeline *
560 i915_request_timeline(const struct i915_request *rq)
561 {
562 	/* Valid only while the request is being constructed (or retired). */
563 	return rcu_dereference_protected(rq->timeline,
564 					 lockdep_is_held(&rcu_access_pointer(rq->timeline)->mutex));
565 }
566 
567 static inline struct i915_gem_context *
568 i915_request_gem_context(const struct i915_request *rq)
569 {
570 	/* Valid only while the request is being constructed (or retired). */
571 	return rcu_dereference_protected(rq->context->gem_context, true);
572 }
573 
574 static inline struct intel_timeline *
575 i915_request_active_timeline(const struct i915_request *rq)
576 {
577 	/*
578 	 * When in use during submission, we are protected by a guarantee that
579 	 * the context/timeline is pinned and must remain pinned until after
580 	 * this submission.
581 	 */
582 	return rcu_dereference_protected(rq->timeline,
583 					 lockdep_is_held(&rq->engine->active.lock));
584 }
585 
586 #endif /* I915_REQUEST_H */
587