1 /*
2  * Copyright © 2008-2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
31 
32 #include "gem/i915_gem_context.h"
33 #include "gt/intel_context.h"
34 #include "gt/intel_ring.h"
35 #include "gt/intel_rps.h"
36 
37 #include "i915_active.h"
38 #include "i915_drv.h"
39 #include "i915_globals.h"
40 #include "i915_trace.h"
41 #include "intel_pm.h"
42 
43 struct execute_cb {
44 	struct list_head link;
45 	struct irq_work work;
46 	struct i915_sw_fence *fence;
47 	void (*hook)(struct i915_request *rq, struct dma_fence *signal);
48 	struct i915_request *signal;
49 };
50 
51 static struct i915_global_request {
52 	struct i915_global base;
53 	struct kmem_cache *slab_requests;
54 	struct kmem_cache *slab_dependencies;
55 	struct kmem_cache *slab_execute_cbs;
56 } global;
57 
58 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
59 {
60 	return dev_name(to_request(fence)->i915->drm.dev);
61 }
62 
63 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
64 {
65 	const struct i915_gem_context *ctx;
66 
67 	/*
68 	 * The timeline struct (as part of the ppgtt underneath a context)
69 	 * may be freed when the request is no longer in use by the GPU.
70 	 * We could extend the life of a context to beyond that of all
71 	 * fences, possibly keeping the hw resource around indefinitely,
72 	 * or we just give them a false name. Since
73 	 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
74 	 * lie seems justifiable.
75 	 */
76 	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
77 		return "signaled";
78 
79 	ctx = i915_request_gem_context(to_request(fence));
80 	if (!ctx)
81 		return "[" DRIVER_NAME "]";
82 
83 	return ctx->name;
84 }
85 
86 static bool i915_fence_signaled(struct dma_fence *fence)
87 {
88 	return i915_request_completed(to_request(fence));
89 }
90 
91 static bool i915_fence_enable_signaling(struct dma_fence *fence)
92 {
93 	return i915_request_enable_breadcrumb(to_request(fence));
94 }
95 
96 static signed long i915_fence_wait(struct dma_fence *fence,
97 				   bool interruptible,
98 				   signed long timeout)
99 {
100 	return i915_request_wait(to_request(fence),
101 				 interruptible | I915_WAIT_PRIORITY,
102 				 timeout);
103 }
104 
105 static void i915_fence_release(struct dma_fence *fence)
106 {
107 	struct i915_request *rq = to_request(fence);
108 
109 	/*
110 	 * The request is put onto a RCU freelist (i.e. the address
111 	 * is immediately reused), mark the fences as being freed now.
112 	 * Otherwise the debugobjects for the fences are only marked as
113 	 * freed when the slab cache itself is freed, and so we would get
114 	 * caught trying to reuse dead objects.
115 	 */
116 	i915_sw_fence_fini(&rq->submit);
117 	i915_sw_fence_fini(&rq->semaphore);
118 
119 	kmem_cache_free(global.slab_requests, rq);
120 }
121 
122 const struct dma_fence_ops i915_fence_ops = {
123 	.get_driver_name = i915_fence_get_driver_name,
124 	.get_timeline_name = i915_fence_get_timeline_name,
125 	.enable_signaling = i915_fence_enable_signaling,
126 	.signaled = i915_fence_signaled,
127 	.wait = i915_fence_wait,
128 	.release = i915_fence_release,
129 };
130 
131 static void irq_execute_cb(struct irq_work *wrk)
132 {
133 	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
134 
135 	i915_sw_fence_complete(cb->fence);
136 	kmem_cache_free(global.slab_execute_cbs, cb);
137 }
138 
139 static void irq_execute_cb_hook(struct irq_work *wrk)
140 {
141 	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
142 
143 	cb->hook(container_of(cb->fence, struct i915_request, submit),
144 		 &cb->signal->fence);
145 	i915_request_put(cb->signal);
146 
147 	irq_execute_cb(wrk);
148 }
149 
150 static void __notify_execute_cb(struct i915_request *rq)
151 {
152 	struct execute_cb *cb;
153 
154 	lockdep_assert_held(&rq->lock);
155 
156 	if (list_empty(&rq->execute_cb))
157 		return;
158 
159 	list_for_each_entry(cb, &rq->execute_cb, link)
160 		irq_work_queue(&cb->work);
161 
162 	/*
163 	 * XXX Rollback on __i915_request_unsubmit()
164 	 *
165 	 * In the future, perhaps when we have an active time-slicing scheduler,
166 	 * it will be interesting to unsubmit parallel execution and remove
167 	 * busywaits from the GPU until their master is restarted. This is
168 	 * quite hairy, we have to carefully rollback the fence and do a
169 	 * preempt-to-idle cycle on the target engine, all the while the
170 	 * master execute_cb may refire.
171 	 */
172 	INIT_LIST_HEAD(&rq->execute_cb);
173 }
174 
175 static inline void
176 remove_from_client(struct i915_request *request)
177 {
178 	struct drm_i915_file_private *file_priv;
179 
180 	if (!READ_ONCE(request->file_priv))
181 		return;
182 
183 	rcu_read_lock();
184 	file_priv = xchg(&request->file_priv, NULL);
185 	if (file_priv) {
186 		spin_lock(&file_priv->mm.lock);
187 		list_del(&request->client_link);
188 		spin_unlock(&file_priv->mm.lock);
189 	}
190 	rcu_read_unlock();
191 }
192 
193 static void free_capture_list(struct i915_request *request)
194 {
195 	struct i915_capture_list *capture;
196 
197 	capture = fetch_and_zero(&request->capture_list);
198 	while (capture) {
199 		struct i915_capture_list *next = capture->next;
200 
201 		kfree(capture);
202 		capture = next;
203 	}
204 }
205 
206 static void remove_from_engine(struct i915_request *rq)
207 {
208 	struct intel_engine_cs *engine, *locked;
209 
210 	/*
211 	 * Virtual engines complicate acquiring the engine timeline lock,
212 	 * as their rq->engine pointer is not stable until under that
213 	 * engine lock. The simple ploy we use is to take the lock then
214 	 * check that the rq still belongs to the newly locked engine.
215 	 */
216 	locked = READ_ONCE(rq->engine);
217 	spin_lock_irq(&locked->active.lock);
218 	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
219 		spin_unlock(&locked->active.lock);
220 		spin_lock(&engine->active.lock);
221 		locked = engine;
222 	}
223 	list_del_init(&rq->sched.link);
224 	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
225 	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
226 	spin_unlock_irq(&locked->active.lock);
227 }
228 
229 bool i915_request_retire(struct i915_request *rq)
230 {
231 	if (!i915_request_completed(rq))
232 		return false;
233 
234 	RQ_TRACE(rq, "\n");
235 
236 	GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
237 	trace_i915_request_retire(rq);
238 
239 	/*
240 	 * We know the GPU must have read the request to have
241 	 * sent us the seqno + interrupt, so use the position
242 	 * of tail of the request to update the last known position
243 	 * of the GPU head.
244 	 *
245 	 * Note this requires that we are always called in request
246 	 * completion order.
247 	 */
248 	GEM_BUG_ON(!list_is_first(&rq->link,
249 				  &i915_request_timeline(rq)->requests));
250 	rq->ring->head = rq->postfix;
251 
252 	/*
253 	 * We only loosely track inflight requests across preemption,
254 	 * and so we may find ourselves attempting to retire a _completed_
255 	 * request that we have removed from the HW and put back on a run
256 	 * queue.
257 	 */
258 	remove_from_engine(rq);
259 
260 	spin_lock_irq(&rq->lock);
261 	i915_request_mark_complete(rq);
262 	if (!i915_request_signaled(rq))
263 		dma_fence_signal_locked(&rq->fence);
264 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
265 		i915_request_cancel_breadcrumb(rq);
266 	if (i915_request_has_waitboost(rq)) {
267 		GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
268 		atomic_dec(&rq->engine->gt->rps.num_waiters);
269 	}
270 	if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
271 		set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
272 		__notify_execute_cb(rq);
273 	}
274 	GEM_BUG_ON(!list_empty(&rq->execute_cb));
275 	spin_unlock_irq(&rq->lock);
276 
277 	remove_from_client(rq);
278 	list_del_rcu(&rq->link);
279 
280 	intel_context_exit(rq->context);
281 	intel_context_unpin(rq->context);
282 
283 	free_capture_list(rq);
284 	i915_sched_node_fini(&rq->sched);
285 	i915_request_put(rq);
286 
287 	return true;
288 }
289 
290 void i915_request_retire_upto(struct i915_request *rq)
291 {
292 	struct intel_timeline * const tl = i915_request_timeline(rq);
293 	struct i915_request *tmp;
294 
295 	RQ_TRACE(rq, "\n");
296 
297 	GEM_BUG_ON(!i915_request_completed(rq));
298 
299 	do {
300 		tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
301 	} while (i915_request_retire(tmp) && tmp != rq);
302 }
303 
304 static int
305 __await_execution(struct i915_request *rq,
306 		  struct i915_request *signal,
307 		  void (*hook)(struct i915_request *rq,
308 			       struct dma_fence *signal),
309 		  gfp_t gfp)
310 {
311 	struct execute_cb *cb;
312 
313 	if (i915_request_is_active(signal)) {
314 		if (hook)
315 			hook(rq, &signal->fence);
316 		return 0;
317 	}
318 
319 	cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
320 	if (!cb)
321 		return -ENOMEM;
322 
323 	cb->fence = &rq->submit;
324 	i915_sw_fence_await(cb->fence);
325 	init_irq_work(&cb->work, irq_execute_cb);
326 
327 	if (hook) {
328 		cb->hook = hook;
329 		cb->signal = i915_request_get(signal);
330 		cb->work.func = irq_execute_cb_hook;
331 	}
332 
333 	spin_lock_irq(&signal->lock);
334 	if (i915_request_is_active(signal)) {
335 		if (hook) {
336 			hook(rq, &signal->fence);
337 			i915_request_put(signal);
338 		}
339 		i915_sw_fence_complete(cb->fence);
340 		kmem_cache_free(global.slab_execute_cbs, cb);
341 	} else {
342 		list_add_tail(&cb->link, &signal->execute_cb);
343 	}
344 	spin_unlock_irq(&signal->lock);
345 
346 	/* Copy across semaphore status as we need the same behaviour */
347 	rq->sched.flags |= signal->sched.flags;
348 	return 0;
349 }
350 
351 bool __i915_request_submit(struct i915_request *request)
352 {
353 	struct intel_engine_cs *engine = request->engine;
354 	bool result = false;
355 
356 	RQ_TRACE(request, "\n");
357 
358 	GEM_BUG_ON(!irqs_disabled());
359 	lockdep_assert_held(&engine->active.lock);
360 
361 	/*
362 	 * With the advent of preempt-to-busy, we frequently encounter
363 	 * requests that we have unsubmitted from HW, but left running
364 	 * until the next ack and so have completed in the meantime. On
365 	 * resubmission of that completed request, we can skip
366 	 * updating the payload, and execlists can even skip submitting
367 	 * the request.
368 	 *
369 	 * We must remove the request from the caller's priority queue,
370 	 * and the caller must only call us when the request is in their
371 	 * priority queue, under the active.lock. This ensures that the
372 	 * request has *not* yet been retired and we can safely move
373 	 * the request into the engine->active.list where it will be
374 	 * dropped upon retiring. (Otherwise if resubmit a *retired*
375 	 * request, this would be a horrible use-after-free.)
376 	 */
377 	if (i915_request_completed(request))
378 		goto xfer;
379 
380 	if (intel_context_is_banned(request->context))
381 		i915_request_skip(request, -EIO);
382 
383 	/*
384 	 * Are we using semaphores when the gpu is already saturated?
385 	 *
386 	 * Using semaphores incurs a cost in having the GPU poll a
387 	 * memory location, busywaiting for it to change. The continual
388 	 * memory reads can have a noticeable impact on the rest of the
389 	 * system with the extra bus traffic, stalling the cpu as it too
390 	 * tries to access memory across the bus (perf stat -e bus-cycles).
391 	 *
392 	 * If we installed a semaphore on this request and we only submit
393 	 * the request after the signaler completed, that indicates the
394 	 * system is overloaded and using semaphores at this time only
395 	 * increases the amount of work we are doing. If so, we disable
396 	 * further use of semaphores until we are idle again, whence we
397 	 * optimistically try again.
398 	 */
399 	if (request->sched.semaphores &&
400 	    i915_sw_fence_signaled(&request->semaphore))
401 		engine->saturated |= request->sched.semaphores;
402 
403 	engine->emit_fini_breadcrumb(request,
404 				     request->ring->vaddr + request->postfix);
405 
406 	trace_i915_request_execute(request);
407 	engine->serial++;
408 	result = true;
409 
410 xfer:	/* We may be recursing from the signal callback of another i915 fence */
411 	spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
412 
413 	if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
414 		list_move_tail(&request->sched.link, &engine->active.requests);
415 		clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
416 	}
417 
418 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
419 	    !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
420 	    !i915_request_enable_breadcrumb(request))
421 		intel_engine_signal_breadcrumbs(engine);
422 
423 	__notify_execute_cb(request);
424 
425 	spin_unlock(&request->lock);
426 
427 	return result;
428 }
429 
430 void i915_request_submit(struct i915_request *request)
431 {
432 	struct intel_engine_cs *engine = request->engine;
433 	unsigned long flags;
434 
435 	/* Will be called from irq-context when using foreign fences. */
436 	spin_lock_irqsave(&engine->active.lock, flags);
437 
438 	__i915_request_submit(request);
439 
440 	spin_unlock_irqrestore(&engine->active.lock, flags);
441 }
442 
443 void __i915_request_unsubmit(struct i915_request *request)
444 {
445 	struct intel_engine_cs *engine = request->engine;
446 
447 	RQ_TRACE(request, "\n");
448 
449 	GEM_BUG_ON(!irqs_disabled());
450 	lockdep_assert_held(&engine->active.lock);
451 
452 	/*
453 	 * Only unwind in reverse order, required so that the per-context list
454 	 * is kept in seqno/ring order.
455 	 */
456 
457 	/* We may be recursing from the signal callback of another i915 fence */
458 	spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
459 
460 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
461 		i915_request_cancel_breadcrumb(request);
462 
463 	GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
464 	clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
465 
466 	spin_unlock(&request->lock);
467 
468 	/* We've already spun, don't charge on resubmitting. */
469 	if (request->sched.semaphores && i915_request_started(request)) {
470 		request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
471 		request->sched.semaphores = 0;
472 	}
473 
474 	/*
475 	 * We don't need to wake_up any waiters on request->execute, they
476 	 * will get woken by any other event or us re-adding this request
477 	 * to the engine timeline (__i915_request_submit()). The waiters
478 	 * should be quite adapt at finding that the request now has a new
479 	 * global_seqno to the one they went to sleep on.
480 	 */
481 }
482 
483 void i915_request_unsubmit(struct i915_request *request)
484 {
485 	struct intel_engine_cs *engine = request->engine;
486 	unsigned long flags;
487 
488 	/* Will be called from irq-context when using foreign fences. */
489 	spin_lock_irqsave(&engine->active.lock, flags);
490 
491 	__i915_request_unsubmit(request);
492 
493 	spin_unlock_irqrestore(&engine->active.lock, flags);
494 }
495 
496 static int __i915_sw_fence_call
497 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
498 {
499 	struct i915_request *request =
500 		container_of(fence, typeof(*request), submit);
501 
502 	switch (state) {
503 	case FENCE_COMPLETE:
504 		trace_i915_request_submit(request);
505 
506 		if (unlikely(fence->error))
507 			i915_request_skip(request, fence->error);
508 
509 		/*
510 		 * We need to serialize use of the submit_request() callback
511 		 * with its hotplugging performed during an emergency
512 		 * i915_gem_set_wedged().  We use the RCU mechanism to mark the
513 		 * critical section in order to force i915_gem_set_wedged() to
514 		 * wait until the submit_request() is completed before
515 		 * proceeding.
516 		 */
517 		rcu_read_lock();
518 		request->engine->submit_request(request);
519 		rcu_read_unlock();
520 		break;
521 
522 	case FENCE_FREE:
523 		i915_request_put(request);
524 		break;
525 	}
526 
527 	return NOTIFY_DONE;
528 }
529 
530 static int __i915_sw_fence_call
531 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
532 {
533 	struct i915_request *request =
534 		container_of(fence, typeof(*request), semaphore);
535 
536 	switch (state) {
537 	case FENCE_COMPLETE:
538 		i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
539 		break;
540 
541 	case FENCE_FREE:
542 		i915_request_put(request);
543 		break;
544 	}
545 
546 	return NOTIFY_DONE;
547 }
548 
549 static void retire_requests(struct intel_timeline *tl)
550 {
551 	struct i915_request *rq, *rn;
552 
553 	list_for_each_entry_safe(rq, rn, &tl->requests, link)
554 		if (!i915_request_retire(rq))
555 			break;
556 }
557 
558 static noinline struct i915_request *
559 request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
560 {
561 	struct i915_request *rq;
562 
563 	if (list_empty(&tl->requests))
564 		goto out;
565 
566 	if (!gfpflags_allow_blocking(gfp))
567 		goto out;
568 
569 	/* Move our oldest request to the slab-cache (if not in use!) */
570 	rq = list_first_entry(&tl->requests, typeof(*rq), link);
571 	i915_request_retire(rq);
572 
573 	rq = kmem_cache_alloc(global.slab_requests,
574 			      gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
575 	if (rq)
576 		return rq;
577 
578 	/* Ratelimit ourselves to prevent oom from malicious clients */
579 	rq = list_last_entry(&tl->requests, typeof(*rq), link);
580 	cond_synchronize_rcu(rq->rcustate);
581 
582 	/* Retire our old requests in the hope that we free some */
583 	retire_requests(tl);
584 
585 out:
586 	return kmem_cache_alloc(global.slab_requests, gfp);
587 }
588 
589 static void __i915_request_ctor(void *arg)
590 {
591 	struct i915_request *rq = arg;
592 
593 	spin_lock_init(&rq->lock);
594 	i915_sched_node_init(&rq->sched);
595 	i915_sw_fence_init(&rq->submit, submit_notify);
596 	i915_sw_fence_init(&rq->semaphore, semaphore_notify);
597 
598 	dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
599 
600 	rq->file_priv = NULL;
601 	rq->capture_list = NULL;
602 
603 	INIT_LIST_HEAD(&rq->execute_cb);
604 }
605 
606 struct i915_request *
607 __i915_request_create(struct intel_context *ce, gfp_t gfp)
608 {
609 	struct intel_timeline *tl = ce->timeline;
610 	struct i915_request *rq;
611 	u32 seqno;
612 	int ret;
613 
614 	might_sleep_if(gfpflags_allow_blocking(gfp));
615 
616 	/* Check that the caller provided an already pinned context */
617 	__intel_context_pin(ce);
618 
619 	/*
620 	 * Beware: Dragons be flying overhead.
621 	 *
622 	 * We use RCU to look up requests in flight. The lookups may
623 	 * race with the request being allocated from the slab freelist.
624 	 * That is the request we are writing to here, may be in the process
625 	 * of being read by __i915_active_request_get_rcu(). As such,
626 	 * we have to be very careful when overwriting the contents. During
627 	 * the RCU lookup, we change chase the request->engine pointer,
628 	 * read the request->global_seqno and increment the reference count.
629 	 *
630 	 * The reference count is incremented atomically. If it is zero,
631 	 * the lookup knows the request is unallocated and complete. Otherwise,
632 	 * it is either still in use, or has been reallocated and reset
633 	 * with dma_fence_init(). This increment is safe for release as we
634 	 * check that the request we have a reference to and matches the active
635 	 * request.
636 	 *
637 	 * Before we increment the refcount, we chase the request->engine
638 	 * pointer. We must not call kmem_cache_zalloc() or else we set
639 	 * that pointer to NULL and cause a crash during the lookup. If
640 	 * we see the request is completed (based on the value of the
641 	 * old engine and seqno), the lookup is complete and reports NULL.
642 	 * If we decide the request is not completed (new engine or seqno),
643 	 * then we grab a reference and double check that it is still the
644 	 * active request - which it won't be and restart the lookup.
645 	 *
646 	 * Do not use kmem_cache_zalloc() here!
647 	 */
648 	rq = kmem_cache_alloc(global.slab_requests,
649 			      gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
650 	if (unlikely(!rq)) {
651 		rq = request_alloc_slow(tl, gfp);
652 		if (!rq) {
653 			ret = -ENOMEM;
654 			goto err_unreserve;
655 		}
656 	}
657 
658 	rq->i915 = ce->engine->i915;
659 	rq->context = ce;
660 	rq->engine = ce->engine;
661 	rq->ring = ce->ring;
662 	rq->execution_mask = ce->engine->mask;
663 
664 	kref_init(&rq->fence.refcount);
665 	rq->fence.flags = 0;
666 	rq->fence.error = 0;
667 	INIT_LIST_HEAD(&rq->fence.cb_list);
668 
669 	ret = intel_timeline_get_seqno(tl, rq, &seqno);
670 	if (ret)
671 		goto err_free;
672 
673 	rq->fence.context = tl->fence_context;
674 	rq->fence.seqno = seqno;
675 
676 	RCU_INIT_POINTER(rq->timeline, tl);
677 	RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
678 	rq->hwsp_seqno = tl->hwsp_seqno;
679 
680 	rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
681 
682 	/* We bump the ref for the fence chain */
683 	i915_sw_fence_reinit(&i915_request_get(rq)->submit);
684 	i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
685 
686 	i915_sched_node_reinit(&rq->sched);
687 
688 	/* No zalloc, everything must be cleared after use */
689 	rq->batch = NULL;
690 	GEM_BUG_ON(rq->file_priv);
691 	GEM_BUG_ON(rq->capture_list);
692 	GEM_BUG_ON(!list_empty(&rq->execute_cb));
693 
694 	/*
695 	 * Reserve space in the ring buffer for all the commands required to
696 	 * eventually emit this request. This is to guarantee that the
697 	 * i915_request_add() call can't fail. Note that the reserve may need
698 	 * to be redone if the request is not actually submitted straight
699 	 * away, e.g. because a GPU scheduler has deferred it.
700 	 *
701 	 * Note that due to how we add reserved_space to intel_ring_begin()
702 	 * we need to double our request to ensure that if we need to wrap
703 	 * around inside i915_request_add() there is sufficient space at
704 	 * the beginning of the ring as well.
705 	 */
706 	rq->reserved_space =
707 		2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
708 
709 	/*
710 	 * Record the position of the start of the request so that
711 	 * should we detect the updated seqno part-way through the
712 	 * GPU processing the request, we never over-estimate the
713 	 * position of the head.
714 	 */
715 	rq->head = rq->ring->emit;
716 
717 	ret = rq->engine->request_alloc(rq);
718 	if (ret)
719 		goto err_unwind;
720 
721 	rq->infix = rq->ring->emit; /* end of header; start of user payload */
722 
723 	intel_context_mark_active(ce);
724 	list_add_tail_rcu(&rq->link, &tl->requests);
725 
726 	return rq;
727 
728 err_unwind:
729 	ce->ring->emit = rq->head;
730 
731 	/* Make sure we didn't add ourselves to external state before freeing */
732 	GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
733 	GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
734 
735 err_free:
736 	kmem_cache_free(global.slab_requests, rq);
737 err_unreserve:
738 	intel_context_unpin(ce);
739 	return ERR_PTR(ret);
740 }
741 
742 struct i915_request *
743 i915_request_create(struct intel_context *ce)
744 {
745 	struct i915_request *rq;
746 	struct intel_timeline *tl;
747 
748 	tl = intel_context_timeline_lock(ce);
749 	if (IS_ERR(tl))
750 		return ERR_CAST(tl);
751 
752 	/* Move our oldest request to the slab-cache (if not in use!) */
753 	rq = list_first_entry(&tl->requests, typeof(*rq), link);
754 	if (!list_is_last(&rq->link, &tl->requests))
755 		i915_request_retire(rq);
756 
757 	intel_context_enter(ce);
758 	rq = __i915_request_create(ce, GFP_KERNEL);
759 	intel_context_exit(ce); /* active reference transferred to request */
760 	if (IS_ERR(rq))
761 		goto err_unlock;
762 
763 	/* Check that we do not interrupt ourselves with a new request */
764 	rq->cookie = lockdep_pin_lock(&tl->mutex);
765 
766 	return rq;
767 
768 err_unlock:
769 	intel_context_timeline_unlock(tl);
770 	return rq;
771 }
772 
773 static int
774 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
775 {
776 	struct dma_fence *fence;
777 	int err;
778 
779 	GEM_BUG_ON(i915_request_timeline(rq) ==
780 		   rcu_access_pointer(signal->timeline));
781 
782 	if (i915_request_started(signal))
783 		return 0;
784 
785 	fence = NULL;
786 	rcu_read_lock();
787 	spin_lock_irq(&signal->lock);
788 	do {
789 		struct list_head *pos = READ_ONCE(signal->link.prev);
790 		struct i915_request *prev;
791 
792 		/* Confirm signal has not been retired, the link is valid */
793 		if (unlikely(i915_request_started(signal)))
794 			break;
795 
796 		/* Is signal the earliest request on its timeline? */
797 		if (pos == &rcu_dereference(signal->timeline)->requests)
798 			break;
799 
800 		/*
801 		 * Peek at the request before us in the timeline. That
802 		 * request will only be valid before it is retired, so
803 		 * after acquiring a reference to it, confirm that it is
804 		 * still part of the signaler's timeline.
805 		 */
806 		prev = list_entry(pos, typeof(*prev), link);
807 		if (!i915_request_get_rcu(prev))
808 			break;
809 
810 		/* After the strong barrier, confirm prev is still attached */
811 		if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
812 			i915_request_put(prev);
813 			break;
814 		}
815 
816 		fence = &prev->fence;
817 	} while (0);
818 	spin_unlock_irq(&signal->lock);
819 	rcu_read_unlock();
820 	if (!fence)
821 		return 0;
822 
823 	err = 0;
824 	if (intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
825 		err = i915_sw_fence_await_dma_fence(&rq->submit,
826 						    fence, 0,
827 						    I915_FENCE_GFP);
828 	dma_fence_put(fence);
829 
830 	return err;
831 }
832 
833 static intel_engine_mask_t
834 already_busywaiting(struct i915_request *rq)
835 {
836 	/*
837 	 * Polling a semaphore causes bus traffic, delaying other users of
838 	 * both the GPU and CPU. We want to limit the impact on others,
839 	 * while taking advantage of early submission to reduce GPU
840 	 * latency. Therefore we restrict ourselves to not using more
841 	 * than one semaphore from each source, and not using a semaphore
842 	 * if we have detected the engine is saturated (i.e. would not be
843 	 * submitted early and cause bus traffic reading an already passed
844 	 * semaphore).
845 	 *
846 	 * See the are-we-too-late? check in __i915_request_submit().
847 	 */
848 	return rq->sched.semaphores | rq->engine->saturated;
849 }
850 
851 static int
852 __emit_semaphore_wait(struct i915_request *to,
853 		      struct i915_request *from,
854 		      u32 seqno)
855 {
856 	const int has_token = INTEL_GEN(to->i915) >= 12;
857 	u32 hwsp_offset;
858 	int len, err;
859 	u32 *cs;
860 
861 	GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
862 
863 	/* We need to pin the signaler's HWSP until we are finished reading. */
864 	err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
865 	if (err)
866 		return err;
867 
868 	len = 4;
869 	if (has_token)
870 		len += 2;
871 
872 	cs = intel_ring_begin(to, len);
873 	if (IS_ERR(cs))
874 		return PTR_ERR(cs);
875 
876 	/*
877 	 * Using greater-than-or-equal here means we have to worry
878 	 * about seqno wraparound. To side step that issue, we swap
879 	 * the timeline HWSP upon wrapping, so that everyone listening
880 	 * for the old (pre-wrap) values do not see the much smaller
881 	 * (post-wrap) values than they were expecting (and so wait
882 	 * forever).
883 	 */
884 	*cs++ = (MI_SEMAPHORE_WAIT |
885 		 MI_SEMAPHORE_GLOBAL_GTT |
886 		 MI_SEMAPHORE_POLL |
887 		 MI_SEMAPHORE_SAD_GTE_SDD) +
888 		has_token;
889 	*cs++ = seqno;
890 	*cs++ = hwsp_offset;
891 	*cs++ = 0;
892 	if (has_token) {
893 		*cs++ = 0;
894 		*cs++ = MI_NOOP;
895 	}
896 
897 	intel_ring_advance(to, cs);
898 	return 0;
899 }
900 
901 static int
902 emit_semaphore_wait(struct i915_request *to,
903 		    struct i915_request *from,
904 		    gfp_t gfp)
905 {
906 	/* Just emit the first semaphore we see as request space is limited. */
907 	if (already_busywaiting(to) & from->engine->mask)
908 		goto await_fence;
909 
910 	if (i915_request_await_start(to, from) < 0)
911 		goto await_fence;
912 
913 	/* Only submit our spinner after the signaler is running! */
914 	if (__await_execution(to, from, NULL, gfp))
915 		goto await_fence;
916 
917 	if (__emit_semaphore_wait(to, from, from->fence.seqno))
918 		goto await_fence;
919 
920 	to->sched.semaphores |= from->engine->mask;
921 	to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
922 	return 0;
923 
924 await_fence:
925 	return i915_sw_fence_await_dma_fence(&to->submit,
926 					     &from->fence, 0,
927 					     I915_FENCE_GFP);
928 }
929 
930 static int
931 i915_request_await_request(struct i915_request *to, struct i915_request *from)
932 {
933 	int ret;
934 
935 	GEM_BUG_ON(to == from);
936 	GEM_BUG_ON(to->timeline == from->timeline);
937 
938 	if (i915_request_completed(from))
939 		return 0;
940 
941 	if (to->engine->schedule) {
942 		ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
943 		if (ret < 0)
944 			return ret;
945 	}
946 
947 	if (to->engine == from->engine)
948 		ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
949 						       &from->submit,
950 						       I915_FENCE_GFP);
951 	else if (intel_context_use_semaphores(to->context))
952 		ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
953 	else
954 		ret = i915_sw_fence_await_dma_fence(&to->submit,
955 						    &from->fence, 0,
956 						    I915_FENCE_GFP);
957 	if (ret < 0)
958 		return ret;
959 
960 	if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
961 		ret = i915_sw_fence_await_dma_fence(&to->semaphore,
962 						    &from->fence, 0,
963 						    I915_FENCE_GFP);
964 		if (ret < 0)
965 			return ret;
966 	}
967 
968 	return 0;
969 }
970 
971 int
972 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
973 {
974 	struct dma_fence **child = &fence;
975 	unsigned int nchild = 1;
976 	int ret;
977 
978 	/*
979 	 * Note that if the fence-array was created in signal-on-any mode,
980 	 * we should *not* decompose it into its individual fences. However,
981 	 * we don't currently store which mode the fence-array is operating
982 	 * in. Fortunately, the only user of signal-on-any is private to
983 	 * amdgpu and we should not see any incoming fence-array from
984 	 * sync-file being in signal-on-any mode.
985 	 */
986 	if (dma_fence_is_array(fence)) {
987 		struct dma_fence_array *array = to_dma_fence_array(fence);
988 
989 		child = array->fences;
990 		nchild = array->num_fences;
991 		GEM_BUG_ON(!nchild);
992 	}
993 
994 	do {
995 		fence = *child++;
996 		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
997 			i915_sw_fence_set_error_once(&rq->submit, fence->error);
998 			continue;
999 		}
1000 
1001 		/*
1002 		 * Requests on the same timeline are explicitly ordered, along
1003 		 * with their dependencies, by i915_request_add() which ensures
1004 		 * that requests are submitted in-order through each ring.
1005 		 */
1006 		if (fence->context == rq->fence.context)
1007 			continue;
1008 
1009 		/* Squash repeated waits to the same timelines */
1010 		if (fence->context &&
1011 		    intel_timeline_sync_is_later(i915_request_timeline(rq),
1012 						 fence))
1013 			continue;
1014 
1015 		if (dma_fence_is_i915(fence))
1016 			ret = i915_request_await_request(rq, to_request(fence));
1017 		else
1018 			ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1019 							    fence->context ? I915_FENCE_TIMEOUT : 0,
1020 							    I915_FENCE_GFP);
1021 		if (ret < 0)
1022 			return ret;
1023 
1024 		/* Record the latest fence used against each timeline */
1025 		if (fence->context)
1026 			intel_timeline_sync_set(i915_request_timeline(rq),
1027 						fence);
1028 	} while (--nchild);
1029 
1030 	return 0;
1031 }
1032 
1033 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1034 					  struct dma_fence *fence)
1035 {
1036 	return __intel_timeline_sync_is_later(tl,
1037 					      fence->context,
1038 					      fence->seqno - 1);
1039 }
1040 
1041 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1042 					 const struct dma_fence *fence)
1043 {
1044 	return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1045 }
1046 
1047 static int
1048 __i915_request_await_execution(struct i915_request *to,
1049 			       struct i915_request *from,
1050 			       void (*hook)(struct i915_request *rq,
1051 					    struct dma_fence *signal))
1052 {
1053 	int err;
1054 
1055 	/* Submit both requests at the same time */
1056 	err = __await_execution(to, from, hook, I915_FENCE_GFP);
1057 	if (err)
1058 		return err;
1059 
1060 	/* Squash repeated depenendices to the same timelines */
1061 	if (intel_timeline_sync_has_start(i915_request_timeline(to),
1062 					  &from->fence))
1063 		return 0;
1064 
1065 	/* Ensure both start together [after all semaphores in signal] */
1066 	if (intel_engine_has_semaphores(to->engine))
1067 		err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1068 	else
1069 		err = i915_request_await_start(to, from);
1070 	if (err < 0)
1071 		return err;
1072 
1073 	/* Couple the dependency tree for PI on this exposed to->fence */
1074 	if (to->engine->schedule) {
1075 		err = i915_sched_node_add_dependency(&to->sched, &from->sched);
1076 		if (err < 0)
1077 			return err;
1078 	}
1079 
1080 	return intel_timeline_sync_set_start(i915_request_timeline(to),
1081 					     &from->fence);
1082 }
1083 
1084 int
1085 i915_request_await_execution(struct i915_request *rq,
1086 			     struct dma_fence *fence,
1087 			     void (*hook)(struct i915_request *rq,
1088 					  struct dma_fence *signal))
1089 {
1090 	struct dma_fence **child = &fence;
1091 	unsigned int nchild = 1;
1092 	int ret;
1093 
1094 	if (dma_fence_is_array(fence)) {
1095 		struct dma_fence_array *array = to_dma_fence_array(fence);
1096 
1097 		/* XXX Error for signal-on-any fence arrays */
1098 
1099 		child = array->fences;
1100 		nchild = array->num_fences;
1101 		GEM_BUG_ON(!nchild);
1102 	}
1103 
1104 	do {
1105 		fence = *child++;
1106 		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1107 			i915_sw_fence_set_error_once(&rq->submit, fence->error);
1108 			continue;
1109 		}
1110 
1111 		/*
1112 		 * We don't squash repeated fence dependencies here as we
1113 		 * want to run our callback in all cases.
1114 		 */
1115 
1116 		if (dma_fence_is_i915(fence))
1117 			ret = __i915_request_await_execution(rq,
1118 							     to_request(fence),
1119 							     hook);
1120 		else
1121 			ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1122 							    I915_FENCE_TIMEOUT,
1123 							    GFP_KERNEL);
1124 		if (ret < 0)
1125 			return ret;
1126 	} while (--nchild);
1127 
1128 	return 0;
1129 }
1130 
1131 /**
1132  * i915_request_await_object - set this request to (async) wait upon a bo
1133  * @to: request we are wishing to use
1134  * @obj: object which may be in use on another ring.
1135  * @write: whether the wait is on behalf of a writer
1136  *
1137  * This code is meant to abstract object synchronization with the GPU.
1138  * Conceptually we serialise writes between engines inside the GPU.
1139  * We only allow one engine to write into a buffer at any time, but
1140  * multiple readers. To ensure each has a coherent view of memory, we must:
1141  *
1142  * - If there is an outstanding write request to the object, the new
1143  *   request must wait for it to complete (either CPU or in hw, requests
1144  *   on the same ring will be naturally ordered).
1145  *
1146  * - If we are a write request (pending_write_domain is set), the new
1147  *   request must wait for outstanding read requests to complete.
1148  *
1149  * Returns 0 if successful, else propagates up the lower layer error.
1150  */
1151 int
1152 i915_request_await_object(struct i915_request *to,
1153 			  struct drm_i915_gem_object *obj,
1154 			  bool write)
1155 {
1156 	struct dma_fence *excl;
1157 	int ret = 0;
1158 
1159 	if (write) {
1160 		struct dma_fence **shared;
1161 		unsigned int count, i;
1162 
1163 		ret = dma_resv_get_fences_rcu(obj->base.resv,
1164 							&excl, &count, &shared);
1165 		if (ret)
1166 			return ret;
1167 
1168 		for (i = 0; i < count; i++) {
1169 			ret = i915_request_await_dma_fence(to, shared[i]);
1170 			if (ret)
1171 				break;
1172 
1173 			dma_fence_put(shared[i]);
1174 		}
1175 
1176 		for (; i < count; i++)
1177 			dma_fence_put(shared[i]);
1178 		kfree(shared);
1179 	} else {
1180 		excl = dma_resv_get_excl_rcu(obj->base.resv);
1181 	}
1182 
1183 	if (excl) {
1184 		if (ret == 0)
1185 			ret = i915_request_await_dma_fence(to, excl);
1186 
1187 		dma_fence_put(excl);
1188 	}
1189 
1190 	return ret;
1191 }
1192 
1193 void i915_request_skip(struct i915_request *rq, int error)
1194 {
1195 	void *vaddr = rq->ring->vaddr;
1196 	u32 head;
1197 
1198 	GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1199 	dma_fence_set_error(&rq->fence, error);
1200 
1201 	if (rq->infix == rq->postfix)
1202 		return;
1203 
1204 	/*
1205 	 * As this request likely depends on state from the lost
1206 	 * context, clear out all the user operations leaving the
1207 	 * breadcrumb at the end (so we get the fence notifications).
1208 	 */
1209 	head = rq->infix;
1210 	if (rq->postfix < head) {
1211 		memset(vaddr + head, 0, rq->ring->size - head);
1212 		head = 0;
1213 	}
1214 	memset(vaddr + head, 0, rq->postfix - head);
1215 	rq->infix = rq->postfix;
1216 }
1217 
1218 static struct i915_request *
1219 __i915_request_add_to_timeline(struct i915_request *rq)
1220 {
1221 	struct intel_timeline *timeline = i915_request_timeline(rq);
1222 	struct i915_request *prev;
1223 
1224 	/*
1225 	 * Dependency tracking and request ordering along the timeline
1226 	 * is special cased so that we can eliminate redundant ordering
1227 	 * operations while building the request (we know that the timeline
1228 	 * itself is ordered, and here we guarantee it).
1229 	 *
1230 	 * As we know we will need to emit tracking along the timeline,
1231 	 * we embed the hooks into our request struct -- at the cost of
1232 	 * having to have specialised no-allocation interfaces (which will
1233 	 * be beneficial elsewhere).
1234 	 *
1235 	 * A second benefit to open-coding i915_request_await_request is
1236 	 * that we can apply a slight variant of the rules specialised
1237 	 * for timelines that jump between engines (such as virtual engines).
1238 	 * If we consider the case of virtual engine, we must emit a dma-fence
1239 	 * to prevent scheduling of the second request until the first is
1240 	 * complete (to maximise our greedy late load balancing) and this
1241 	 * precludes optimising to use semaphores serialisation of a single
1242 	 * timeline across engines.
1243 	 */
1244 	prev = to_request(__i915_active_fence_set(&timeline->last_request,
1245 						  &rq->fence));
1246 	if (prev && !i915_request_completed(prev)) {
1247 		if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1248 			i915_sw_fence_await_sw_fence(&rq->submit,
1249 						     &prev->submit,
1250 						     &rq->submitq);
1251 		else
1252 			__i915_sw_fence_await_dma_fence(&rq->submit,
1253 							&prev->fence,
1254 							&rq->dmaq);
1255 		if (rq->engine->schedule)
1256 			__i915_sched_node_add_dependency(&rq->sched,
1257 							 &prev->sched,
1258 							 &rq->dep,
1259 							 0);
1260 	}
1261 
1262 	/*
1263 	 * Make sure that no request gazumped us - if it was allocated after
1264 	 * our i915_request_alloc() and called __i915_request_add() before
1265 	 * us, the timeline will hold its seqno which is later than ours.
1266 	 */
1267 	GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1268 
1269 	return prev;
1270 }
1271 
1272 /*
1273  * NB: This function is not allowed to fail. Doing so would mean the the
1274  * request is not being tracked for completion but the work itself is
1275  * going to happen on the hardware. This would be a Bad Thing(tm).
1276  */
1277 struct i915_request *__i915_request_commit(struct i915_request *rq)
1278 {
1279 	struct intel_engine_cs *engine = rq->engine;
1280 	struct intel_ring *ring = rq->ring;
1281 	u32 *cs;
1282 
1283 	RQ_TRACE(rq, "\n");
1284 
1285 	/*
1286 	 * To ensure that this call will not fail, space for its emissions
1287 	 * should already have been reserved in the ring buffer. Let the ring
1288 	 * know that it is time to use that space up.
1289 	 */
1290 	GEM_BUG_ON(rq->reserved_space > ring->space);
1291 	rq->reserved_space = 0;
1292 	rq->emitted_jiffies = jiffies;
1293 
1294 	/*
1295 	 * Record the position of the start of the breadcrumb so that
1296 	 * should we detect the updated seqno part-way through the
1297 	 * GPU processing the request, we never over-estimate the
1298 	 * position of the ring's HEAD.
1299 	 */
1300 	cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1301 	GEM_BUG_ON(IS_ERR(cs));
1302 	rq->postfix = intel_ring_offset(rq, cs);
1303 
1304 	return __i915_request_add_to_timeline(rq);
1305 }
1306 
1307 void __i915_request_queue(struct i915_request *rq,
1308 			  const struct i915_sched_attr *attr)
1309 {
1310 	/*
1311 	 * Let the backend know a new request has arrived that may need
1312 	 * to adjust the existing execution schedule due to a high priority
1313 	 * request - i.e. we may want to preempt the current request in order
1314 	 * to run a high priority dependency chain *before* we can execute this
1315 	 * request.
1316 	 *
1317 	 * This is called before the request is ready to run so that we can
1318 	 * decide whether to preempt the entire chain so that it is ready to
1319 	 * run at the earliest possible convenience.
1320 	 */
1321 	i915_sw_fence_commit(&rq->semaphore);
1322 	if (attr && rq->engine->schedule)
1323 		rq->engine->schedule(rq, attr);
1324 	i915_sw_fence_commit(&rq->submit);
1325 }
1326 
1327 void i915_request_add(struct i915_request *rq)
1328 {
1329 	struct intel_timeline * const tl = i915_request_timeline(rq);
1330 	struct i915_sched_attr attr = {};
1331 	struct i915_request *prev;
1332 
1333 	lockdep_assert_held(&tl->mutex);
1334 	lockdep_unpin_lock(&tl->mutex, rq->cookie);
1335 
1336 	trace_i915_request_add(rq);
1337 
1338 	prev = __i915_request_commit(rq);
1339 
1340 	if (rcu_access_pointer(rq->context->gem_context))
1341 		attr = i915_request_gem_context(rq)->sched;
1342 
1343 	/*
1344 	 * Boost actual workloads past semaphores!
1345 	 *
1346 	 * With semaphores we spin on one engine waiting for another,
1347 	 * simply to reduce the latency of starting our work when
1348 	 * the signaler completes. However, if there is any other
1349 	 * work that we could be doing on this engine instead, that
1350 	 * is better utilisation and will reduce the overall duration
1351 	 * of the current work. To avoid PI boosting a semaphore
1352 	 * far in the distance past over useful work, we keep a history
1353 	 * of any semaphore use along our dependency chain.
1354 	 */
1355 	if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1356 		attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1357 
1358 	/*
1359 	 * Boost priorities to new clients (new request flows).
1360 	 *
1361 	 * Allow interactive/synchronous clients to jump ahead of
1362 	 * the bulk clients. (FQ_CODEL)
1363 	 */
1364 	if (list_empty(&rq->sched.signalers_list))
1365 		attr.priority |= I915_PRIORITY_WAIT;
1366 
1367 	local_bh_disable();
1368 	__i915_request_queue(rq, &attr);
1369 	local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1370 
1371 	/*
1372 	 * In typical scenarios, we do not expect the previous request on
1373 	 * the timeline to be still tracked by timeline->last_request if it
1374 	 * has been completed. If the completed request is still here, that
1375 	 * implies that request retirement is a long way behind submission,
1376 	 * suggesting that we haven't been retiring frequently enough from
1377 	 * the combination of retire-before-alloc, waiters and the background
1378 	 * retirement worker. So if the last request on this timeline was
1379 	 * already completed, do a catch up pass, flushing the retirement queue
1380 	 * up to this client. Since we have now moved the heaviest operations
1381 	 * during retirement onto secondary workers, such as freeing objects
1382 	 * or contexts, retiring a bunch of requests is mostly list management
1383 	 * (and cache misses), and so we should not be overly penalizing this
1384 	 * client by performing excess work, though we may still performing
1385 	 * work on behalf of others -- but instead we should benefit from
1386 	 * improved resource management. (Well, that's the theory at least.)
1387 	 */
1388 	if (prev &&
1389 	    i915_request_completed(prev) &&
1390 	    rcu_access_pointer(prev->timeline) == tl)
1391 		i915_request_retire_upto(prev);
1392 
1393 	mutex_unlock(&tl->mutex);
1394 }
1395 
1396 static unsigned long local_clock_us(unsigned int *cpu)
1397 {
1398 	unsigned long t;
1399 
1400 	/*
1401 	 * Cheaply and approximately convert from nanoseconds to microseconds.
1402 	 * The result and subsequent calculations are also defined in the same
1403 	 * approximate microseconds units. The principal source of timing
1404 	 * error here is from the simple truncation.
1405 	 *
1406 	 * Note that local_clock() is only defined wrt to the current CPU;
1407 	 * the comparisons are no longer valid if we switch CPUs. Instead of
1408 	 * blocking preemption for the entire busywait, we can detect the CPU
1409 	 * switch and use that as indicator of system load and a reason to
1410 	 * stop busywaiting, see busywait_stop().
1411 	 */
1412 	*cpu = get_cpu();
1413 	t = local_clock() >> 10;
1414 	put_cpu();
1415 
1416 	return t;
1417 }
1418 
1419 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1420 {
1421 	unsigned int this_cpu;
1422 
1423 	if (time_after(local_clock_us(&this_cpu), timeout))
1424 		return true;
1425 
1426 	return this_cpu != cpu;
1427 }
1428 
1429 static bool __i915_spin_request(const struct i915_request * const rq,
1430 				int state, unsigned long timeout_us)
1431 {
1432 	unsigned int cpu;
1433 
1434 	/*
1435 	 * Only wait for the request if we know it is likely to complete.
1436 	 *
1437 	 * We don't track the timestamps around requests, nor the average
1438 	 * request length, so we do not have a good indicator that this
1439 	 * request will complete within the timeout. What we do know is the
1440 	 * order in which requests are executed by the context and so we can
1441 	 * tell if the request has been started. If the request is not even
1442 	 * running yet, it is a fair assumption that it will not complete
1443 	 * within our relatively short timeout.
1444 	 */
1445 	if (!i915_request_is_running(rq))
1446 		return false;
1447 
1448 	/*
1449 	 * When waiting for high frequency requests, e.g. during synchronous
1450 	 * rendering split between the CPU and GPU, the finite amount of time
1451 	 * required to set up the irq and wait upon it limits the response
1452 	 * rate. By busywaiting on the request completion for a short while we
1453 	 * can service the high frequency waits as quick as possible. However,
1454 	 * if it is a slow request, we want to sleep as quickly as possible.
1455 	 * The tradeoff between waiting and sleeping is roughly the time it
1456 	 * takes to sleep on a request, on the order of a microsecond.
1457 	 */
1458 
1459 	timeout_us += local_clock_us(&cpu);
1460 	do {
1461 		if (i915_request_completed(rq))
1462 			return true;
1463 
1464 		if (signal_pending_state(state, current))
1465 			break;
1466 
1467 		if (busywait_stop(timeout_us, cpu))
1468 			break;
1469 
1470 		cpu_relax();
1471 	} while (!need_resched());
1472 
1473 	return false;
1474 }
1475 
1476 struct request_wait {
1477 	struct dma_fence_cb cb;
1478 	struct task_struct *tsk;
1479 };
1480 
1481 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1482 {
1483 	struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1484 
1485 	wake_up_process(wait->tsk);
1486 }
1487 
1488 /**
1489  * i915_request_wait - wait until execution of request has finished
1490  * @rq: the request to wait upon
1491  * @flags: how to wait
1492  * @timeout: how long to wait in jiffies
1493  *
1494  * i915_request_wait() waits for the request to be completed, for a
1495  * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1496  * unbounded wait).
1497  *
1498  * Returns the remaining time (in jiffies) if the request completed, which may
1499  * be zero or -ETIME if the request is unfinished after the timeout expires.
1500  * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1501  * pending before the request completes.
1502  */
1503 long i915_request_wait(struct i915_request *rq,
1504 		       unsigned int flags,
1505 		       long timeout)
1506 {
1507 	const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1508 		TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1509 	struct request_wait wait;
1510 
1511 	might_sleep();
1512 	GEM_BUG_ON(timeout < 0);
1513 
1514 	if (dma_fence_is_signaled(&rq->fence))
1515 		return timeout;
1516 
1517 	if (!timeout)
1518 		return -ETIME;
1519 
1520 	trace_i915_request_wait_begin(rq, flags);
1521 
1522 	/*
1523 	 * We must never wait on the GPU while holding a lock as we
1524 	 * may need to perform a GPU reset. So while we don't need to
1525 	 * serialise wait/reset with an explicit lock, we do want
1526 	 * lockdep to detect potential dependency cycles.
1527 	 */
1528 	mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1529 
1530 	/*
1531 	 * Optimistic spin before touching IRQs.
1532 	 *
1533 	 * We may use a rather large value here to offset the penalty of
1534 	 * switching away from the active task. Frequently, the client will
1535 	 * wait upon an old swapbuffer to throttle itself to remain within a
1536 	 * frame of the gpu. If the client is running in lockstep with the gpu,
1537 	 * then it should not be waiting long at all, and a sleep now will incur
1538 	 * extra scheduler latency in producing the next frame. To try to
1539 	 * avoid adding the cost of enabling/disabling the interrupt to the
1540 	 * short wait, we first spin to see if the request would have completed
1541 	 * in the time taken to setup the interrupt.
1542 	 *
1543 	 * We need upto 5us to enable the irq, and upto 20us to hide the
1544 	 * scheduler latency of a context switch, ignoring the secondary
1545 	 * impacts from a context switch such as cache eviction.
1546 	 *
1547 	 * The scheme used for low-latency IO is called "hybrid interrupt
1548 	 * polling". The suggestion there is to sleep until just before you
1549 	 * expect to be woken by the device interrupt and then poll for its
1550 	 * completion. That requires having a good predictor for the request
1551 	 * duration, which we currently lack.
1552 	 */
1553 	if (IS_ACTIVE(CONFIG_DRM_I915_SPIN_REQUEST) &&
1554 	    __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) {
1555 		dma_fence_signal(&rq->fence);
1556 		goto out;
1557 	}
1558 
1559 	/*
1560 	 * This client is about to stall waiting for the GPU. In many cases
1561 	 * this is undesirable and limits the throughput of the system, as
1562 	 * many clients cannot continue processing user input/output whilst
1563 	 * blocked. RPS autotuning may take tens of milliseconds to respond
1564 	 * to the GPU load and thus incurs additional latency for the client.
1565 	 * We can circumvent that by promoting the GPU frequency to maximum
1566 	 * before we sleep. This makes the GPU throttle up much more quickly
1567 	 * (good for benchmarks and user experience, e.g. window animations),
1568 	 * but at a cost of spending more power processing the workload
1569 	 * (bad for battery).
1570 	 */
1571 	if (flags & I915_WAIT_PRIORITY) {
1572 		if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1573 			intel_rps_boost(rq);
1574 		i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1575 	}
1576 
1577 	wait.tsk = current;
1578 	if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1579 		goto out;
1580 
1581 	for (;;) {
1582 		set_current_state(state);
1583 
1584 		if (i915_request_completed(rq)) {
1585 			dma_fence_signal(&rq->fence);
1586 			break;
1587 		}
1588 
1589 		if (signal_pending_state(state, current)) {
1590 			timeout = -ERESTARTSYS;
1591 			break;
1592 		}
1593 
1594 		if (!timeout) {
1595 			timeout = -ETIME;
1596 			break;
1597 		}
1598 
1599 		intel_engine_flush_submission(rq->engine);
1600 		timeout = io_schedule_timeout(timeout);
1601 	}
1602 	__set_current_state(TASK_RUNNING);
1603 
1604 	dma_fence_remove_callback(&rq->fence, &wait.cb);
1605 
1606 out:
1607 	mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1608 	trace_i915_request_wait_end(rq);
1609 	return timeout;
1610 }
1611 
1612 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1613 #include "selftests/mock_request.c"
1614 #include "selftests/i915_request.c"
1615 #endif
1616 
1617 static void i915_global_request_shrink(void)
1618 {
1619 	kmem_cache_shrink(global.slab_dependencies);
1620 	kmem_cache_shrink(global.slab_execute_cbs);
1621 	kmem_cache_shrink(global.slab_requests);
1622 }
1623 
1624 static void i915_global_request_exit(void)
1625 {
1626 	kmem_cache_destroy(global.slab_dependencies);
1627 	kmem_cache_destroy(global.slab_execute_cbs);
1628 	kmem_cache_destroy(global.slab_requests);
1629 }
1630 
1631 static struct i915_global_request global = { {
1632 	.shrink = i915_global_request_shrink,
1633 	.exit = i915_global_request_exit,
1634 } };
1635 
1636 int __init i915_global_request_init(void)
1637 {
1638 	global.slab_requests =
1639 		kmem_cache_create("i915_request",
1640 				  sizeof(struct i915_request),
1641 				  __alignof__(struct i915_request),
1642 				  SLAB_HWCACHE_ALIGN |
1643 				  SLAB_RECLAIM_ACCOUNT |
1644 				  SLAB_TYPESAFE_BY_RCU,
1645 				  __i915_request_ctor);
1646 	if (!global.slab_requests)
1647 		return -ENOMEM;
1648 
1649 	global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1650 					     SLAB_HWCACHE_ALIGN |
1651 					     SLAB_RECLAIM_ACCOUNT |
1652 					     SLAB_TYPESAFE_BY_RCU);
1653 	if (!global.slab_execute_cbs)
1654 		goto err_requests;
1655 
1656 	global.slab_dependencies = KMEM_CACHE(i915_dependency,
1657 					      SLAB_HWCACHE_ALIGN |
1658 					      SLAB_RECLAIM_ACCOUNT);
1659 	if (!global.slab_dependencies)
1660 		goto err_execute_cbs;
1661 
1662 	i915_global_register(&global.base);
1663 	return 0;
1664 
1665 err_execute_cbs:
1666 	kmem_cache_destroy(global.slab_execute_cbs);
1667 err_requests:
1668 	kmem_cache_destroy(global.slab_requests);
1669 	return -ENOMEM;
1670 }
1671