1 /*
2  * Copyright © 2008-2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/dma-fence-array.h>
26 #include <linux/dma-fence-chain.h>
27 #include <linux/irq_work.h>
28 #include <linux/prefetch.h>
29 #include <linux/sched.h>
30 #include <linux/sched/clock.h>
31 #include <linux/sched/signal.h>
32 
33 #include "gem/i915_gem_context.h"
34 #include "gt/intel_breadcrumbs.h"
35 #include "gt/intel_context.h"
36 #include "gt/intel_engine.h"
37 #include "gt/intel_engine_heartbeat.h"
38 #include "gt/intel_gpu_commands.h"
39 #include "gt/intel_reset.h"
40 #include "gt/intel_ring.h"
41 #include "gt/intel_rps.h"
42 
43 #include "i915_active.h"
44 #include "i915_drv.h"
45 #include "i915_globals.h"
46 #include "i915_trace.h"
47 #include "intel_pm.h"
48 
49 struct execute_cb {
50 	struct irq_work work;
51 	struct i915_sw_fence *fence;
52 	void (*hook)(struct i915_request *rq, struct dma_fence *signal);
53 	struct i915_request *signal;
54 };
55 
56 static struct i915_global_request {
57 	struct i915_global base;
58 	struct kmem_cache *slab_requests;
59 	struct kmem_cache *slab_execute_cbs;
60 } global;
61 
62 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
63 {
64 	return dev_name(to_request(fence)->engine->i915->drm.dev);
65 }
66 
67 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
68 {
69 	const struct i915_gem_context *ctx;
70 
71 	/*
72 	 * The timeline struct (as part of the ppgtt underneath a context)
73 	 * may be freed when the request is no longer in use by the GPU.
74 	 * We could extend the life of a context to beyond that of all
75 	 * fences, possibly keeping the hw resource around indefinitely,
76 	 * or we just give them a false name. Since
77 	 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
78 	 * lie seems justifiable.
79 	 */
80 	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
81 		return "signaled";
82 
83 	ctx = i915_request_gem_context(to_request(fence));
84 	if (!ctx)
85 		return "[" DRIVER_NAME "]";
86 
87 	return ctx->name;
88 }
89 
90 static bool i915_fence_signaled(struct dma_fence *fence)
91 {
92 	return i915_request_completed(to_request(fence));
93 }
94 
95 static bool i915_fence_enable_signaling(struct dma_fence *fence)
96 {
97 	return i915_request_enable_breadcrumb(to_request(fence));
98 }
99 
100 static signed long i915_fence_wait(struct dma_fence *fence,
101 				   bool interruptible,
102 				   signed long timeout)
103 {
104 	return i915_request_wait(to_request(fence),
105 				 interruptible | I915_WAIT_PRIORITY,
106 				 timeout);
107 }
108 
109 struct kmem_cache *i915_request_slab_cache(void)
110 {
111 	return global.slab_requests;
112 }
113 
114 static void i915_fence_release(struct dma_fence *fence)
115 {
116 	struct i915_request *rq = to_request(fence);
117 
118 	/*
119 	 * The request is put onto a RCU freelist (i.e. the address
120 	 * is immediately reused), mark the fences as being freed now.
121 	 * Otherwise the debugobjects for the fences are only marked as
122 	 * freed when the slab cache itself is freed, and so we would get
123 	 * caught trying to reuse dead objects.
124 	 */
125 	i915_sw_fence_fini(&rq->submit);
126 	i915_sw_fence_fini(&rq->semaphore);
127 
128 	/*
129 	 * Keep one request on each engine for reserved use under mempressure
130 	 *
131 	 * We do not hold a reference to the engine here and so have to be
132 	 * very careful in what rq->engine we poke. The virtual engine is
133 	 * referenced via the rq->context and we released that ref during
134 	 * i915_request_retire(), ergo we must not dereference a virtual
135 	 * engine here. Not that we would want to, as the only consumer of
136 	 * the reserved engine->request_pool is the power management parking,
137 	 * which must-not-fail, and that is only run on the physical engines.
138 	 *
139 	 * Since the request must have been executed to be have completed,
140 	 * we know that it will have been processed by the HW and will
141 	 * not be unsubmitted again, so rq->engine and rq->execution_mask
142 	 * at this point is stable. rq->execution_mask will be a single
143 	 * bit if the last and _only_ engine it could execution on was a
144 	 * physical engine, if it's multiple bits then it started on and
145 	 * could still be on a virtual engine. Thus if the mask is not a
146 	 * power-of-two we assume that rq->engine may still be a virtual
147 	 * engine and so a dangling invalid pointer that we cannot dereference
148 	 *
149 	 * For example, consider the flow of a bonded request through a virtual
150 	 * engine. The request is created with a wide engine mask (all engines
151 	 * that we might execute on). On processing the bond, the request mask
152 	 * is reduced to one or more engines. If the request is subsequently
153 	 * bound to a single engine, it will then be constrained to only
154 	 * execute on that engine and never returned to the virtual engine
155 	 * after timeslicing away, see __unwind_incomplete_requests(). Thus we
156 	 * know that if the rq->execution_mask is a single bit, rq->engine
157 	 * can be a physical engine with the exact corresponding mask.
158 	 */
159 	if (is_power_of_2(rq->execution_mask) &&
160 	    !cmpxchg(&rq->engine->request_pool, NULL, rq))
161 		return;
162 
163 	kmem_cache_free(global.slab_requests, rq);
164 }
165 
166 const struct dma_fence_ops i915_fence_ops = {
167 	.get_driver_name = i915_fence_get_driver_name,
168 	.get_timeline_name = i915_fence_get_timeline_name,
169 	.enable_signaling = i915_fence_enable_signaling,
170 	.signaled = i915_fence_signaled,
171 	.wait = i915_fence_wait,
172 	.release = i915_fence_release,
173 };
174 
175 static void irq_execute_cb(struct irq_work *wrk)
176 {
177 	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
178 
179 	i915_sw_fence_complete(cb->fence);
180 	kmem_cache_free(global.slab_execute_cbs, cb);
181 }
182 
183 static void irq_execute_cb_hook(struct irq_work *wrk)
184 {
185 	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
186 
187 	cb->hook(container_of(cb->fence, struct i915_request, submit),
188 		 &cb->signal->fence);
189 	i915_request_put(cb->signal);
190 
191 	irq_execute_cb(wrk);
192 }
193 
194 static __always_inline void
195 __notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk))
196 {
197 	struct execute_cb *cb, *cn;
198 
199 	if (llist_empty(&rq->execute_cb))
200 		return;
201 
202 	llist_for_each_entry_safe(cb, cn,
203 				  llist_del_all(&rq->execute_cb),
204 				  work.node.llist)
205 		fn(&cb->work);
206 }
207 
208 static void __notify_execute_cb_irq(struct i915_request *rq)
209 {
210 	__notify_execute_cb(rq, irq_work_queue);
211 }
212 
213 static bool irq_work_imm(struct irq_work *wrk)
214 {
215 	wrk->func(wrk);
216 	return false;
217 }
218 
219 static void __notify_execute_cb_imm(struct i915_request *rq)
220 {
221 	__notify_execute_cb(rq, irq_work_imm);
222 }
223 
224 static void free_capture_list(struct i915_request *request)
225 {
226 	struct i915_capture_list *capture;
227 
228 	capture = fetch_and_zero(&request->capture_list);
229 	while (capture) {
230 		struct i915_capture_list *next = capture->next;
231 
232 		kfree(capture);
233 		capture = next;
234 	}
235 }
236 
237 static void __i915_request_fill(struct i915_request *rq, u8 val)
238 {
239 	void *vaddr = rq->ring->vaddr;
240 	u32 head;
241 
242 	head = rq->infix;
243 	if (rq->postfix < head) {
244 		memset(vaddr + head, val, rq->ring->size - head);
245 		head = 0;
246 	}
247 	memset(vaddr + head, val, rq->postfix - head);
248 }
249 
250 /**
251  * i915_request_active_engine
252  * @rq: request to inspect
253  * @active: pointer in which to return the active engine
254  *
255  * Fills the currently active engine to the @active pointer if the request
256  * is active and still not completed.
257  *
258  * Returns true if request was active or false otherwise.
259  */
260 bool
261 i915_request_active_engine(struct i915_request *rq,
262 			   struct intel_engine_cs **active)
263 {
264 	struct intel_engine_cs *engine, *locked;
265 	bool ret = false;
266 
267 	/*
268 	 * Serialise with __i915_request_submit() so that it sees
269 	 * is-banned?, or we know the request is already inflight.
270 	 *
271 	 * Note that rq->engine is unstable, and so we double
272 	 * check that we have acquired the lock on the final engine.
273 	 */
274 	locked = READ_ONCE(rq->engine);
275 	spin_lock_irq(&locked->active.lock);
276 	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
277 		spin_unlock(&locked->active.lock);
278 		locked = engine;
279 		spin_lock(&locked->active.lock);
280 	}
281 
282 	if (i915_request_is_active(rq)) {
283 		if (!__i915_request_is_complete(rq))
284 			*active = locked;
285 		ret = true;
286 	}
287 
288 	spin_unlock_irq(&locked->active.lock);
289 
290 	return ret;
291 }
292 
293 
294 static void remove_from_engine(struct i915_request *rq)
295 {
296 	struct intel_engine_cs *engine, *locked;
297 
298 	/*
299 	 * Virtual engines complicate acquiring the engine timeline lock,
300 	 * as their rq->engine pointer is not stable until under that
301 	 * engine lock. The simple ploy we use is to take the lock then
302 	 * check that the rq still belongs to the newly locked engine.
303 	 */
304 	locked = READ_ONCE(rq->engine);
305 	spin_lock_irq(&locked->active.lock);
306 	while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
307 		spin_unlock(&locked->active.lock);
308 		spin_lock(&engine->active.lock);
309 		locked = engine;
310 	}
311 	list_del_init(&rq->sched.link);
312 
313 	clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
314 	clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
315 
316 	/* Prevent further __await_execution() registering a cb, then flush */
317 	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
318 
319 	spin_unlock_irq(&locked->active.lock);
320 
321 	__notify_execute_cb_imm(rq);
322 }
323 
324 static void __rq_init_watchdog(struct i915_request *rq)
325 {
326 	rq->watchdog.timer.function = NULL;
327 }
328 
329 static enum hrtimer_restart __rq_watchdog_expired(struct hrtimer *hrtimer)
330 {
331 	struct i915_request *rq =
332 		container_of(hrtimer, struct i915_request, watchdog.timer);
333 	struct intel_gt *gt = rq->engine->gt;
334 
335 	if (!i915_request_completed(rq)) {
336 		if (llist_add(&rq->watchdog.link, &gt->watchdog.list))
337 			schedule_work(&gt->watchdog.work);
338 	} else {
339 		i915_request_put(rq);
340 	}
341 
342 	return HRTIMER_NORESTART;
343 }
344 
345 static void __rq_arm_watchdog(struct i915_request *rq)
346 {
347 	struct i915_request_watchdog *wdg = &rq->watchdog;
348 	struct intel_context *ce = rq->context;
349 
350 	if (!ce->watchdog.timeout_us)
351 		return;
352 
353 	i915_request_get(rq);
354 
355 	hrtimer_init(&wdg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
356 	wdg->timer.function = __rq_watchdog_expired;
357 	hrtimer_start_range_ns(&wdg->timer,
358 			       ns_to_ktime(ce->watchdog.timeout_us *
359 					   NSEC_PER_USEC),
360 			       NSEC_PER_MSEC,
361 			       HRTIMER_MODE_REL);
362 }
363 
364 static void __rq_cancel_watchdog(struct i915_request *rq)
365 {
366 	struct i915_request_watchdog *wdg = &rq->watchdog;
367 
368 	if (wdg->timer.function && hrtimer_try_to_cancel(&wdg->timer) > 0)
369 		i915_request_put(rq);
370 }
371 
372 bool i915_request_retire(struct i915_request *rq)
373 {
374 	if (!__i915_request_is_complete(rq))
375 		return false;
376 
377 	RQ_TRACE(rq, "\n");
378 
379 	GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
380 	trace_i915_request_retire(rq);
381 	i915_request_mark_complete(rq);
382 
383 	__rq_cancel_watchdog(rq);
384 
385 	/*
386 	 * We know the GPU must have read the request to have
387 	 * sent us the seqno + interrupt, so use the position
388 	 * of tail of the request to update the last known position
389 	 * of the GPU head.
390 	 *
391 	 * Note this requires that we are always called in request
392 	 * completion order.
393 	 */
394 	GEM_BUG_ON(!list_is_first(&rq->link,
395 				  &i915_request_timeline(rq)->requests));
396 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
397 		/* Poison before we release our space in the ring */
398 		__i915_request_fill(rq, POISON_FREE);
399 	rq->ring->head = rq->postfix;
400 
401 	if (!i915_request_signaled(rq)) {
402 		spin_lock_irq(&rq->lock);
403 		dma_fence_signal_locked(&rq->fence);
404 		spin_unlock_irq(&rq->lock);
405 	}
406 
407 	if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags))
408 		atomic_dec(&rq->engine->gt->rps.num_waiters);
409 
410 	/*
411 	 * We only loosely track inflight requests across preemption,
412 	 * and so we may find ourselves attempting to retire a _completed_
413 	 * request that we have removed from the HW and put back on a run
414 	 * queue.
415 	 *
416 	 * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be
417 	 * after removing the breadcrumb and signaling it, so that we do not
418 	 * inadvertently attach the breadcrumb to a completed request.
419 	 */
420 	if (!list_empty(&rq->sched.link))
421 		remove_from_engine(rq);
422 	GEM_BUG_ON(!llist_empty(&rq->execute_cb));
423 
424 	__list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
425 
426 	intel_context_exit(rq->context);
427 	intel_context_unpin(rq->context);
428 
429 	free_capture_list(rq);
430 	i915_sched_node_fini(&rq->sched);
431 	i915_request_put(rq);
432 
433 	return true;
434 }
435 
436 void i915_request_retire_upto(struct i915_request *rq)
437 {
438 	struct intel_timeline * const tl = i915_request_timeline(rq);
439 	struct i915_request *tmp;
440 
441 	RQ_TRACE(rq, "\n");
442 	GEM_BUG_ON(!__i915_request_is_complete(rq));
443 
444 	do {
445 		tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
446 	} while (i915_request_retire(tmp) && tmp != rq);
447 }
448 
449 static struct i915_request * const *
450 __engine_active(struct intel_engine_cs *engine)
451 {
452 	return READ_ONCE(engine->execlists.active);
453 }
454 
455 static bool __request_in_flight(const struct i915_request *signal)
456 {
457 	struct i915_request * const *port, *rq;
458 	bool inflight = false;
459 
460 	if (!i915_request_is_ready(signal))
461 		return false;
462 
463 	/*
464 	 * Even if we have unwound the request, it may still be on
465 	 * the GPU (preempt-to-busy). If that request is inside an
466 	 * unpreemptible critical section, it will not be removed. Some
467 	 * GPU functions may even be stuck waiting for the paired request
468 	 * (__await_execution) to be submitted and cannot be preempted
469 	 * until the bond is executing.
470 	 *
471 	 * As we know that there are always preemption points between
472 	 * requests, we know that only the currently executing request
473 	 * may be still active even though we have cleared the flag.
474 	 * However, we can't rely on our tracking of ELSP[0] to know
475 	 * which request is currently active and so maybe stuck, as
476 	 * the tracking maybe an event behind. Instead assume that
477 	 * if the context is still inflight, then it is still active
478 	 * even if the active flag has been cleared.
479 	 *
480 	 * To further complicate matters, if there a pending promotion, the HW
481 	 * may either perform a context switch to the second inflight execlists,
482 	 * or it may switch to the pending set of execlists. In the case of the
483 	 * latter, it may send the ACK and we process the event copying the
484 	 * pending[] over top of inflight[], _overwriting_ our *active. Since
485 	 * this implies the HW is arbitrating and not struck in *active, we do
486 	 * not worry about complete accuracy, but we do require no read/write
487 	 * tearing of the pointer [the read of the pointer must be valid, even
488 	 * as the array is being overwritten, for which we require the writes
489 	 * to avoid tearing.]
490 	 *
491 	 * Note that the read of *execlists->active may race with the promotion
492 	 * of execlists->pending[] to execlists->inflight[], overwritting
493 	 * the value at *execlists->active. This is fine. The promotion implies
494 	 * that we received an ACK from the HW, and so the context is not
495 	 * stuck -- if we do not see ourselves in *active, the inflight status
496 	 * is valid. If instead we see ourselves being copied into *active,
497 	 * we are inflight and may signal the callback.
498 	 */
499 	if (!intel_context_inflight(signal->context))
500 		return false;
501 
502 	rcu_read_lock();
503 	for (port = __engine_active(signal->engine);
504 	     (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */
505 	     port++) {
506 		if (rq->context == signal->context) {
507 			inflight = i915_seqno_passed(rq->fence.seqno,
508 						     signal->fence.seqno);
509 			break;
510 		}
511 	}
512 	rcu_read_unlock();
513 
514 	return inflight;
515 }
516 
517 static int
518 __await_execution(struct i915_request *rq,
519 		  struct i915_request *signal,
520 		  void (*hook)(struct i915_request *rq,
521 			       struct dma_fence *signal),
522 		  gfp_t gfp)
523 {
524 	struct execute_cb *cb;
525 
526 	if (i915_request_is_active(signal)) {
527 		if (hook)
528 			hook(rq, &signal->fence);
529 		return 0;
530 	}
531 
532 	cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
533 	if (!cb)
534 		return -ENOMEM;
535 
536 	cb->fence = &rq->submit;
537 	i915_sw_fence_await(cb->fence);
538 	init_irq_work(&cb->work, irq_execute_cb);
539 
540 	if (hook) {
541 		cb->hook = hook;
542 		cb->signal = i915_request_get(signal);
543 		cb->work.func = irq_execute_cb_hook;
544 	}
545 
546 	/*
547 	 * Register the callback first, then see if the signaler is already
548 	 * active. This ensures that if we race with the
549 	 * __notify_execute_cb from i915_request_submit() and we are not
550 	 * included in that list, we get a second bite of the cherry and
551 	 * execute it ourselves. After this point, a future
552 	 * i915_request_submit() will notify us.
553 	 *
554 	 * In i915_request_retire() we set the ACTIVE bit on a completed
555 	 * request (then flush the execute_cb). So by registering the
556 	 * callback first, then checking the ACTIVE bit, we serialise with
557 	 * the completed/retired request.
558 	 */
559 	if (llist_add(&cb->work.node.llist, &signal->execute_cb)) {
560 		if (i915_request_is_active(signal) ||
561 		    __request_in_flight(signal))
562 			__notify_execute_cb_imm(signal);
563 	}
564 
565 	return 0;
566 }
567 
568 static bool fatal_error(int error)
569 {
570 	switch (error) {
571 	case 0: /* not an error! */
572 	case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
573 	case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
574 		return false;
575 	default:
576 		return true;
577 	}
578 }
579 
580 void __i915_request_skip(struct i915_request *rq)
581 {
582 	GEM_BUG_ON(!fatal_error(rq->fence.error));
583 
584 	if (rq->infix == rq->postfix)
585 		return;
586 
587 	RQ_TRACE(rq, "error: %d\n", rq->fence.error);
588 
589 	/*
590 	 * As this request likely depends on state from the lost
591 	 * context, clear out all the user operations leaving the
592 	 * breadcrumb at the end (so we get the fence notifications).
593 	 */
594 	__i915_request_fill(rq, 0);
595 	rq->infix = rq->postfix;
596 }
597 
598 bool i915_request_set_error_once(struct i915_request *rq, int error)
599 {
600 	int old;
601 
602 	GEM_BUG_ON(!IS_ERR_VALUE((long)error));
603 
604 	if (i915_request_signaled(rq))
605 		return false;
606 
607 	old = READ_ONCE(rq->fence.error);
608 	do {
609 		if (fatal_error(old))
610 			return false;
611 	} while (!try_cmpxchg(&rq->fence.error, &old, error));
612 
613 	return true;
614 }
615 
616 struct i915_request *i915_request_mark_eio(struct i915_request *rq)
617 {
618 	if (__i915_request_is_complete(rq))
619 		return NULL;
620 
621 	GEM_BUG_ON(i915_request_signaled(rq));
622 
623 	/* As soon as the request is completed, it may be retired */
624 	rq = i915_request_get(rq);
625 
626 	i915_request_set_error_once(rq, -EIO);
627 	i915_request_mark_complete(rq);
628 
629 	return rq;
630 }
631 
632 bool __i915_request_submit(struct i915_request *request)
633 {
634 	struct intel_engine_cs *engine = request->engine;
635 	bool result = false;
636 
637 	RQ_TRACE(request, "\n");
638 
639 	GEM_BUG_ON(!irqs_disabled());
640 	lockdep_assert_held(&engine->active.lock);
641 
642 	/*
643 	 * With the advent of preempt-to-busy, we frequently encounter
644 	 * requests that we have unsubmitted from HW, but left running
645 	 * until the next ack and so have completed in the meantime. On
646 	 * resubmission of that completed request, we can skip
647 	 * updating the payload, and execlists can even skip submitting
648 	 * the request.
649 	 *
650 	 * We must remove the request from the caller's priority queue,
651 	 * and the caller must only call us when the request is in their
652 	 * priority queue, under the active.lock. This ensures that the
653 	 * request has *not* yet been retired and we can safely move
654 	 * the request into the engine->active.list where it will be
655 	 * dropped upon retiring. (Otherwise if resubmit a *retired*
656 	 * request, this would be a horrible use-after-free.)
657 	 */
658 	if (__i915_request_is_complete(request)) {
659 		list_del_init(&request->sched.link);
660 		goto active;
661 	}
662 
663 	if (unlikely(intel_context_is_banned(request->context)))
664 		i915_request_set_error_once(request, -EIO);
665 
666 	if (unlikely(fatal_error(request->fence.error)))
667 		__i915_request_skip(request);
668 
669 	/*
670 	 * Are we using semaphores when the gpu is already saturated?
671 	 *
672 	 * Using semaphores incurs a cost in having the GPU poll a
673 	 * memory location, busywaiting for it to change. The continual
674 	 * memory reads can have a noticeable impact on the rest of the
675 	 * system with the extra bus traffic, stalling the cpu as it too
676 	 * tries to access memory across the bus (perf stat -e bus-cycles).
677 	 *
678 	 * If we installed a semaphore on this request and we only submit
679 	 * the request after the signaler completed, that indicates the
680 	 * system is overloaded and using semaphores at this time only
681 	 * increases the amount of work we are doing. If so, we disable
682 	 * further use of semaphores until we are idle again, whence we
683 	 * optimistically try again.
684 	 */
685 	if (request->sched.semaphores &&
686 	    i915_sw_fence_signaled(&request->semaphore))
687 		engine->saturated |= request->sched.semaphores;
688 
689 	engine->emit_fini_breadcrumb(request,
690 				     request->ring->vaddr + request->postfix);
691 
692 	trace_i915_request_execute(request);
693 	engine->serial++;
694 	result = true;
695 
696 	GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
697 	list_move_tail(&request->sched.link, &engine->active.requests);
698 active:
699 	clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
700 	set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
701 
702 	/*
703 	 * XXX Rollback bonded-execution on __i915_request_unsubmit()?
704 	 *
705 	 * In the future, perhaps when we have an active time-slicing scheduler,
706 	 * it will be interesting to unsubmit parallel execution and remove
707 	 * busywaits from the GPU until their master is restarted. This is
708 	 * quite hairy, we have to carefully rollback the fence and do a
709 	 * preempt-to-idle cycle on the target engine, all the while the
710 	 * master execute_cb may refire.
711 	 */
712 	__notify_execute_cb_irq(request);
713 
714 	/* We may be recursing from the signal callback of another i915 fence */
715 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
716 		i915_request_enable_breadcrumb(request);
717 
718 	return result;
719 }
720 
721 void i915_request_submit(struct i915_request *request)
722 {
723 	struct intel_engine_cs *engine = request->engine;
724 	unsigned long flags;
725 
726 	/* Will be called from irq-context when using foreign fences. */
727 	spin_lock_irqsave(&engine->active.lock, flags);
728 
729 	__i915_request_submit(request);
730 
731 	spin_unlock_irqrestore(&engine->active.lock, flags);
732 }
733 
734 void __i915_request_unsubmit(struct i915_request *request)
735 {
736 	struct intel_engine_cs *engine = request->engine;
737 
738 	/*
739 	 * Only unwind in reverse order, required so that the per-context list
740 	 * is kept in seqno/ring order.
741 	 */
742 	RQ_TRACE(request, "\n");
743 
744 	GEM_BUG_ON(!irqs_disabled());
745 	lockdep_assert_held(&engine->active.lock);
746 
747 	/*
748 	 * Before we remove this breadcrumb from the signal list, we have
749 	 * to ensure that a concurrent dma_fence_enable_signaling() does not
750 	 * attach itself. We first mark the request as no longer active and
751 	 * make sure that is visible to other cores, and then remove the
752 	 * breadcrumb if attached.
753 	 */
754 	GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
755 	clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
756 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
757 		i915_request_cancel_breadcrumb(request);
758 
759 	/* We've already spun, don't charge on resubmitting. */
760 	if (request->sched.semaphores && __i915_request_has_started(request))
761 		request->sched.semaphores = 0;
762 
763 	/*
764 	 * We don't need to wake_up any waiters on request->execute, they
765 	 * will get woken by any other event or us re-adding this request
766 	 * to the engine timeline (__i915_request_submit()). The waiters
767 	 * should be quite adapt at finding that the request now has a new
768 	 * global_seqno to the one they went to sleep on.
769 	 */
770 }
771 
772 void i915_request_unsubmit(struct i915_request *request)
773 {
774 	struct intel_engine_cs *engine = request->engine;
775 	unsigned long flags;
776 
777 	/* Will be called from irq-context when using foreign fences. */
778 	spin_lock_irqsave(&engine->active.lock, flags);
779 
780 	__i915_request_unsubmit(request);
781 
782 	spin_unlock_irqrestore(&engine->active.lock, flags);
783 }
784 
785 static void __cancel_request(struct i915_request *rq)
786 {
787 	struct intel_engine_cs *engine = NULL;
788 
789 	i915_request_active_engine(rq, &engine);
790 
791 	if (engine && intel_engine_pulse(engine))
792 		intel_gt_handle_error(engine->gt, engine->mask, 0,
793 				      "request cancellation by %s",
794 				      current->comm);
795 }
796 
797 void i915_request_cancel(struct i915_request *rq, int error)
798 {
799 	if (!i915_request_set_error_once(rq, error))
800 		return;
801 
802 	set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags);
803 
804 	__cancel_request(rq);
805 }
806 
807 static int __i915_sw_fence_call
808 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
809 {
810 	struct i915_request *request =
811 		container_of(fence, typeof(*request), submit);
812 
813 	switch (state) {
814 	case FENCE_COMPLETE:
815 		trace_i915_request_submit(request);
816 
817 		if (unlikely(fence->error))
818 			i915_request_set_error_once(request, fence->error);
819 		else
820 			__rq_arm_watchdog(request);
821 
822 		/*
823 		 * We need to serialize use of the submit_request() callback
824 		 * with its hotplugging performed during an emergency
825 		 * i915_gem_set_wedged().  We use the RCU mechanism to mark the
826 		 * critical section in order to force i915_gem_set_wedged() to
827 		 * wait until the submit_request() is completed before
828 		 * proceeding.
829 		 */
830 		rcu_read_lock();
831 		request->engine->submit_request(request);
832 		rcu_read_unlock();
833 		break;
834 
835 	case FENCE_FREE:
836 		i915_request_put(request);
837 		break;
838 	}
839 
840 	return NOTIFY_DONE;
841 }
842 
843 static int __i915_sw_fence_call
844 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
845 {
846 	struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
847 
848 	switch (state) {
849 	case FENCE_COMPLETE:
850 		break;
851 
852 	case FENCE_FREE:
853 		i915_request_put(rq);
854 		break;
855 	}
856 
857 	return NOTIFY_DONE;
858 }
859 
860 static void retire_requests(struct intel_timeline *tl)
861 {
862 	struct i915_request *rq, *rn;
863 
864 	list_for_each_entry_safe(rq, rn, &tl->requests, link)
865 		if (!i915_request_retire(rq))
866 			break;
867 }
868 
869 static noinline struct i915_request *
870 request_alloc_slow(struct intel_timeline *tl,
871 		   struct i915_request **rsvd,
872 		   gfp_t gfp)
873 {
874 	struct i915_request *rq;
875 
876 	/* If we cannot wait, dip into our reserves */
877 	if (!gfpflags_allow_blocking(gfp)) {
878 		rq = xchg(rsvd, NULL);
879 		if (!rq) /* Use the normal failure path for one final WARN */
880 			goto out;
881 
882 		return rq;
883 	}
884 
885 	if (list_empty(&tl->requests))
886 		goto out;
887 
888 	/* Move our oldest request to the slab-cache (if not in use!) */
889 	rq = list_first_entry(&tl->requests, typeof(*rq), link);
890 	i915_request_retire(rq);
891 
892 	rq = kmem_cache_alloc(global.slab_requests,
893 			      gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
894 	if (rq)
895 		return rq;
896 
897 	/* Ratelimit ourselves to prevent oom from malicious clients */
898 	rq = list_last_entry(&tl->requests, typeof(*rq), link);
899 	cond_synchronize_rcu(rq->rcustate);
900 
901 	/* Retire our old requests in the hope that we free some */
902 	retire_requests(tl);
903 
904 out:
905 	return kmem_cache_alloc(global.slab_requests, gfp);
906 }
907 
908 static void __i915_request_ctor(void *arg)
909 {
910 	struct i915_request *rq = arg;
911 
912 	spin_lock_init(&rq->lock);
913 	i915_sched_node_init(&rq->sched);
914 	i915_sw_fence_init(&rq->submit, submit_notify);
915 	i915_sw_fence_init(&rq->semaphore, semaphore_notify);
916 
917 	dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
918 
919 	rq->capture_list = NULL;
920 
921 	init_llist_head(&rq->execute_cb);
922 }
923 
924 struct i915_request *
925 __i915_request_create(struct intel_context *ce, gfp_t gfp)
926 {
927 	struct intel_timeline *tl = ce->timeline;
928 	struct i915_request *rq;
929 	u32 seqno;
930 	int ret;
931 
932 	might_alloc(gfp);
933 
934 	/* Check that the caller provided an already pinned context */
935 	__intel_context_pin(ce);
936 
937 	/*
938 	 * Beware: Dragons be flying overhead.
939 	 *
940 	 * We use RCU to look up requests in flight. The lookups may
941 	 * race with the request being allocated from the slab freelist.
942 	 * That is the request we are writing to here, may be in the process
943 	 * of being read by __i915_active_request_get_rcu(). As such,
944 	 * we have to be very careful when overwriting the contents. During
945 	 * the RCU lookup, we change chase the request->engine pointer,
946 	 * read the request->global_seqno and increment the reference count.
947 	 *
948 	 * The reference count is incremented atomically. If it is zero,
949 	 * the lookup knows the request is unallocated and complete. Otherwise,
950 	 * it is either still in use, or has been reallocated and reset
951 	 * with dma_fence_init(). This increment is safe for release as we
952 	 * check that the request we have a reference to and matches the active
953 	 * request.
954 	 *
955 	 * Before we increment the refcount, we chase the request->engine
956 	 * pointer. We must not call kmem_cache_zalloc() or else we set
957 	 * that pointer to NULL and cause a crash during the lookup. If
958 	 * we see the request is completed (based on the value of the
959 	 * old engine and seqno), the lookup is complete and reports NULL.
960 	 * If we decide the request is not completed (new engine or seqno),
961 	 * then we grab a reference and double check that it is still the
962 	 * active request - which it won't be and restart the lookup.
963 	 *
964 	 * Do not use kmem_cache_zalloc() here!
965 	 */
966 	rq = kmem_cache_alloc(global.slab_requests,
967 			      gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
968 	if (unlikely(!rq)) {
969 		rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);
970 		if (!rq) {
971 			ret = -ENOMEM;
972 			goto err_unreserve;
973 		}
974 	}
975 
976 	rq->context = ce;
977 	rq->engine = ce->engine;
978 	rq->ring = ce->ring;
979 	rq->execution_mask = ce->engine->mask;
980 
981 	kref_init(&rq->fence.refcount);
982 	rq->fence.flags = 0;
983 	rq->fence.error = 0;
984 	INIT_LIST_HEAD(&rq->fence.cb_list);
985 
986 	ret = intel_timeline_get_seqno(tl, rq, &seqno);
987 	if (ret)
988 		goto err_free;
989 
990 	rq->fence.context = tl->fence_context;
991 	rq->fence.seqno = seqno;
992 
993 	RCU_INIT_POINTER(rq->timeline, tl);
994 	rq->hwsp_seqno = tl->hwsp_seqno;
995 	GEM_BUG_ON(__i915_request_is_complete(rq));
996 
997 	rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
998 
999 	/* We bump the ref for the fence chain */
1000 	i915_sw_fence_reinit(&i915_request_get(rq)->submit);
1001 	i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
1002 
1003 	i915_sched_node_reinit(&rq->sched);
1004 
1005 	/* No zalloc, everything must be cleared after use */
1006 	rq->batch = NULL;
1007 	__rq_init_watchdog(rq);
1008 	GEM_BUG_ON(rq->capture_list);
1009 	GEM_BUG_ON(!llist_empty(&rq->execute_cb));
1010 
1011 	/*
1012 	 * Reserve space in the ring buffer for all the commands required to
1013 	 * eventually emit this request. This is to guarantee that the
1014 	 * i915_request_add() call can't fail. Note that the reserve may need
1015 	 * to be redone if the request is not actually submitted straight
1016 	 * away, e.g. because a GPU scheduler has deferred it.
1017 	 *
1018 	 * Note that due to how we add reserved_space to intel_ring_begin()
1019 	 * we need to double our request to ensure that if we need to wrap
1020 	 * around inside i915_request_add() there is sufficient space at
1021 	 * the beginning of the ring as well.
1022 	 */
1023 	rq->reserved_space =
1024 		2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
1025 
1026 	/*
1027 	 * Record the position of the start of the request so that
1028 	 * should we detect the updated seqno part-way through the
1029 	 * GPU processing the request, we never over-estimate the
1030 	 * position of the head.
1031 	 */
1032 	rq->head = rq->ring->emit;
1033 
1034 	ret = rq->engine->request_alloc(rq);
1035 	if (ret)
1036 		goto err_unwind;
1037 
1038 	rq->infix = rq->ring->emit; /* end of header; start of user payload */
1039 
1040 	intel_context_mark_active(ce);
1041 	list_add_tail_rcu(&rq->link, &tl->requests);
1042 
1043 	return rq;
1044 
1045 err_unwind:
1046 	ce->ring->emit = rq->head;
1047 
1048 	/* Make sure we didn't add ourselves to external state before freeing */
1049 	GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
1050 	GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
1051 
1052 err_free:
1053 	kmem_cache_free(global.slab_requests, rq);
1054 err_unreserve:
1055 	intel_context_unpin(ce);
1056 	return ERR_PTR(ret);
1057 }
1058 
1059 struct i915_request *
1060 i915_request_create(struct intel_context *ce)
1061 {
1062 	struct i915_request *rq;
1063 	struct intel_timeline *tl;
1064 
1065 	tl = intel_context_timeline_lock(ce);
1066 	if (IS_ERR(tl))
1067 		return ERR_CAST(tl);
1068 
1069 	/* Move our oldest request to the slab-cache (if not in use!) */
1070 	rq = list_first_entry(&tl->requests, typeof(*rq), link);
1071 	if (!list_is_last(&rq->link, &tl->requests))
1072 		i915_request_retire(rq);
1073 
1074 	intel_context_enter(ce);
1075 	rq = __i915_request_create(ce, GFP_KERNEL);
1076 	intel_context_exit(ce); /* active reference transferred to request */
1077 	if (IS_ERR(rq))
1078 		goto err_unlock;
1079 
1080 	/* Check that we do not interrupt ourselves with a new request */
1081 	rq->cookie = lockdep_pin_lock(&tl->mutex);
1082 
1083 	return rq;
1084 
1085 err_unlock:
1086 	intel_context_timeline_unlock(tl);
1087 	return rq;
1088 }
1089 
1090 static int
1091 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
1092 {
1093 	struct dma_fence *fence;
1094 	int err;
1095 
1096 	if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
1097 		return 0;
1098 
1099 	if (i915_request_started(signal))
1100 		return 0;
1101 
1102 	/*
1103 	 * The caller holds a reference on @signal, but we do not serialise
1104 	 * against it being retired and removed from the lists.
1105 	 *
1106 	 * We do not hold a reference to the request before @signal, and
1107 	 * so must be very careful to ensure that it is not _recycled_ as
1108 	 * we follow the link backwards.
1109 	 */
1110 	fence = NULL;
1111 	rcu_read_lock();
1112 	do {
1113 		struct list_head *pos = READ_ONCE(signal->link.prev);
1114 		struct i915_request *prev;
1115 
1116 		/* Confirm signal has not been retired, the link is valid */
1117 		if (unlikely(__i915_request_has_started(signal)))
1118 			break;
1119 
1120 		/* Is signal the earliest request on its timeline? */
1121 		if (pos == &rcu_dereference(signal->timeline)->requests)
1122 			break;
1123 
1124 		/*
1125 		 * Peek at the request before us in the timeline. That
1126 		 * request will only be valid before it is retired, so
1127 		 * after acquiring a reference to it, confirm that it is
1128 		 * still part of the signaler's timeline.
1129 		 */
1130 		prev = list_entry(pos, typeof(*prev), link);
1131 		if (!i915_request_get_rcu(prev))
1132 			break;
1133 
1134 		/* After the strong barrier, confirm prev is still attached */
1135 		if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
1136 			i915_request_put(prev);
1137 			break;
1138 		}
1139 
1140 		fence = &prev->fence;
1141 	} while (0);
1142 	rcu_read_unlock();
1143 	if (!fence)
1144 		return 0;
1145 
1146 	err = 0;
1147 	if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
1148 		err = i915_sw_fence_await_dma_fence(&rq->submit,
1149 						    fence, 0,
1150 						    I915_FENCE_GFP);
1151 	dma_fence_put(fence);
1152 
1153 	return err;
1154 }
1155 
1156 static intel_engine_mask_t
1157 already_busywaiting(struct i915_request *rq)
1158 {
1159 	/*
1160 	 * Polling a semaphore causes bus traffic, delaying other users of
1161 	 * both the GPU and CPU. We want to limit the impact on others,
1162 	 * while taking advantage of early submission to reduce GPU
1163 	 * latency. Therefore we restrict ourselves to not using more
1164 	 * than one semaphore from each source, and not using a semaphore
1165 	 * if we have detected the engine is saturated (i.e. would not be
1166 	 * submitted early and cause bus traffic reading an already passed
1167 	 * semaphore).
1168 	 *
1169 	 * See the are-we-too-late? check in __i915_request_submit().
1170 	 */
1171 	return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
1172 }
1173 
1174 static int
1175 __emit_semaphore_wait(struct i915_request *to,
1176 		      struct i915_request *from,
1177 		      u32 seqno)
1178 {
1179 	const int has_token = GRAPHICS_VER(to->engine->i915) >= 12;
1180 	u32 hwsp_offset;
1181 	int len, err;
1182 	u32 *cs;
1183 
1184 	GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8);
1185 	GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
1186 
1187 	/* We need to pin the signaler's HWSP until we are finished reading. */
1188 	err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
1189 	if (err)
1190 		return err;
1191 
1192 	len = 4;
1193 	if (has_token)
1194 		len += 2;
1195 
1196 	cs = intel_ring_begin(to, len);
1197 	if (IS_ERR(cs))
1198 		return PTR_ERR(cs);
1199 
1200 	/*
1201 	 * Using greater-than-or-equal here means we have to worry
1202 	 * about seqno wraparound. To side step that issue, we swap
1203 	 * the timeline HWSP upon wrapping, so that everyone listening
1204 	 * for the old (pre-wrap) values do not see the much smaller
1205 	 * (post-wrap) values than they were expecting (and so wait
1206 	 * forever).
1207 	 */
1208 	*cs++ = (MI_SEMAPHORE_WAIT |
1209 		 MI_SEMAPHORE_GLOBAL_GTT |
1210 		 MI_SEMAPHORE_POLL |
1211 		 MI_SEMAPHORE_SAD_GTE_SDD) +
1212 		has_token;
1213 	*cs++ = seqno;
1214 	*cs++ = hwsp_offset;
1215 	*cs++ = 0;
1216 	if (has_token) {
1217 		*cs++ = 0;
1218 		*cs++ = MI_NOOP;
1219 	}
1220 
1221 	intel_ring_advance(to, cs);
1222 	return 0;
1223 }
1224 
1225 static int
1226 emit_semaphore_wait(struct i915_request *to,
1227 		    struct i915_request *from,
1228 		    gfp_t gfp)
1229 {
1230 	const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
1231 	struct i915_sw_fence *wait = &to->submit;
1232 
1233 	if (!intel_context_use_semaphores(to->context))
1234 		goto await_fence;
1235 
1236 	if (i915_request_has_initial_breadcrumb(to))
1237 		goto await_fence;
1238 
1239 	/*
1240 	 * If this or its dependents are waiting on an external fence
1241 	 * that may fail catastrophically, then we want to avoid using
1242 	 * sempahores as they bypass the fence signaling metadata, and we
1243 	 * lose the fence->error propagation.
1244 	 */
1245 	if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1246 		goto await_fence;
1247 
1248 	/* Just emit the first semaphore we see as request space is limited. */
1249 	if (already_busywaiting(to) & mask)
1250 		goto await_fence;
1251 
1252 	if (i915_request_await_start(to, from) < 0)
1253 		goto await_fence;
1254 
1255 	/* Only submit our spinner after the signaler is running! */
1256 	if (__await_execution(to, from, NULL, gfp))
1257 		goto await_fence;
1258 
1259 	if (__emit_semaphore_wait(to, from, from->fence.seqno))
1260 		goto await_fence;
1261 
1262 	to->sched.semaphores |= mask;
1263 	wait = &to->semaphore;
1264 
1265 await_fence:
1266 	return i915_sw_fence_await_dma_fence(wait,
1267 					     &from->fence, 0,
1268 					     I915_FENCE_GFP);
1269 }
1270 
1271 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1272 					  struct dma_fence *fence)
1273 {
1274 	return __intel_timeline_sync_is_later(tl,
1275 					      fence->context,
1276 					      fence->seqno - 1);
1277 }
1278 
1279 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1280 					 const struct dma_fence *fence)
1281 {
1282 	return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1283 }
1284 
1285 static int
1286 __i915_request_await_execution(struct i915_request *to,
1287 			       struct i915_request *from,
1288 			       void (*hook)(struct i915_request *rq,
1289 					    struct dma_fence *signal))
1290 {
1291 	int err;
1292 
1293 	GEM_BUG_ON(intel_context_is_barrier(from->context));
1294 
1295 	/* Submit both requests at the same time */
1296 	err = __await_execution(to, from, hook, I915_FENCE_GFP);
1297 	if (err)
1298 		return err;
1299 
1300 	/* Squash repeated depenendices to the same timelines */
1301 	if (intel_timeline_sync_has_start(i915_request_timeline(to),
1302 					  &from->fence))
1303 		return 0;
1304 
1305 	/*
1306 	 * Wait until the start of this request.
1307 	 *
1308 	 * The execution cb fires when we submit the request to HW. But in
1309 	 * many cases this may be long before the request itself is ready to
1310 	 * run (consider that we submit 2 requests for the same context, where
1311 	 * the request of interest is behind an indefinite spinner). So we hook
1312 	 * up to both to reduce our queues and keep the execution lag minimised
1313 	 * in the worst case, though we hope that the await_start is elided.
1314 	 */
1315 	err = i915_request_await_start(to, from);
1316 	if (err < 0)
1317 		return err;
1318 
1319 	/*
1320 	 * Ensure both start together [after all semaphores in signal]
1321 	 *
1322 	 * Now that we are queued to the HW at roughly the same time (thanks
1323 	 * to the execute cb) and are ready to run at roughly the same time
1324 	 * (thanks to the await start), our signaler may still be indefinitely
1325 	 * delayed by waiting on a semaphore from a remote engine. If our
1326 	 * signaler depends on a semaphore, so indirectly do we, and we do not
1327 	 * want to start our payload until our signaler also starts theirs.
1328 	 * So we wait.
1329 	 *
1330 	 * However, there is also a second condition for which we need to wait
1331 	 * for the precise start of the signaler. Consider that the signaler
1332 	 * was submitted in a chain of requests following another context
1333 	 * (with just an ordinary intra-engine fence dependency between the
1334 	 * two). In this case the signaler is queued to HW, but not for
1335 	 * immediate execution, and so we must wait until it reaches the
1336 	 * active slot.
1337 	 */
1338 	if (intel_engine_has_semaphores(to->engine) &&
1339 	    !i915_request_has_initial_breadcrumb(to)) {
1340 		err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1341 		if (err < 0)
1342 			return err;
1343 	}
1344 
1345 	/* Couple the dependency tree for PI on this exposed to->fence */
1346 	if (to->engine->schedule) {
1347 		err = i915_sched_node_add_dependency(&to->sched,
1348 						     &from->sched,
1349 						     I915_DEPENDENCY_WEAK);
1350 		if (err < 0)
1351 			return err;
1352 	}
1353 
1354 	return intel_timeline_sync_set_start(i915_request_timeline(to),
1355 					     &from->fence);
1356 }
1357 
1358 static void mark_external(struct i915_request *rq)
1359 {
1360 	/*
1361 	 * The downside of using semaphores is that we lose metadata passing
1362 	 * along the signaling chain. This is particularly nasty when we
1363 	 * need to pass along a fatal error such as EFAULT or EDEADLK. For
1364 	 * fatal errors we want to scrub the request before it is executed,
1365 	 * which means that we cannot preload the request onto HW and have
1366 	 * it wait upon a semaphore.
1367 	 */
1368 	rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1369 }
1370 
1371 static int
1372 __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1373 {
1374 	mark_external(rq);
1375 	return i915_sw_fence_await_dma_fence(&rq->submit, fence,
1376 					     i915_fence_context_timeout(rq->engine->i915,
1377 									fence->context),
1378 					     I915_FENCE_GFP);
1379 }
1380 
1381 static int
1382 i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1383 {
1384 	struct dma_fence *iter;
1385 	int err = 0;
1386 
1387 	if (!to_dma_fence_chain(fence))
1388 		return __i915_request_await_external(rq, fence);
1389 
1390 	dma_fence_chain_for_each(iter, fence) {
1391 		struct dma_fence_chain *chain = to_dma_fence_chain(iter);
1392 
1393 		if (!dma_fence_is_i915(chain->fence)) {
1394 			err = __i915_request_await_external(rq, iter);
1395 			break;
1396 		}
1397 
1398 		err = i915_request_await_dma_fence(rq, chain->fence);
1399 		if (err < 0)
1400 			break;
1401 	}
1402 
1403 	dma_fence_put(iter);
1404 	return err;
1405 }
1406 
1407 int
1408 i915_request_await_execution(struct i915_request *rq,
1409 			     struct dma_fence *fence,
1410 			     void (*hook)(struct i915_request *rq,
1411 					  struct dma_fence *signal))
1412 {
1413 	struct dma_fence **child = &fence;
1414 	unsigned int nchild = 1;
1415 	int ret;
1416 
1417 	if (dma_fence_is_array(fence)) {
1418 		struct dma_fence_array *array = to_dma_fence_array(fence);
1419 
1420 		/* XXX Error for signal-on-any fence arrays */
1421 
1422 		child = array->fences;
1423 		nchild = array->num_fences;
1424 		GEM_BUG_ON(!nchild);
1425 	}
1426 
1427 	do {
1428 		fence = *child++;
1429 		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1430 			continue;
1431 
1432 		if (fence->context == rq->fence.context)
1433 			continue;
1434 
1435 		/*
1436 		 * We don't squash repeated fence dependencies here as we
1437 		 * want to run our callback in all cases.
1438 		 */
1439 
1440 		if (dma_fence_is_i915(fence))
1441 			ret = __i915_request_await_execution(rq,
1442 							     to_request(fence),
1443 							     hook);
1444 		else
1445 			ret = i915_request_await_external(rq, fence);
1446 		if (ret < 0)
1447 			return ret;
1448 	} while (--nchild);
1449 
1450 	return 0;
1451 }
1452 
1453 static int
1454 await_request_submit(struct i915_request *to, struct i915_request *from)
1455 {
1456 	/*
1457 	 * If we are waiting on a virtual engine, then it may be
1458 	 * constrained to execute on a single engine *prior* to submission.
1459 	 * When it is submitted, it will be first submitted to the virtual
1460 	 * engine and then passed to the physical engine. We cannot allow
1461 	 * the waiter to be submitted immediately to the physical engine
1462 	 * as it may then bypass the virtual request.
1463 	 */
1464 	if (to->engine == READ_ONCE(from->engine))
1465 		return i915_sw_fence_await_sw_fence_gfp(&to->submit,
1466 							&from->submit,
1467 							I915_FENCE_GFP);
1468 	else
1469 		return __i915_request_await_execution(to, from, NULL);
1470 }
1471 
1472 static int
1473 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1474 {
1475 	int ret;
1476 
1477 	GEM_BUG_ON(to == from);
1478 	GEM_BUG_ON(to->timeline == from->timeline);
1479 
1480 	if (i915_request_completed(from)) {
1481 		i915_sw_fence_set_error_once(&to->submit, from->fence.error);
1482 		return 0;
1483 	}
1484 
1485 	if (to->engine->schedule) {
1486 		ret = i915_sched_node_add_dependency(&to->sched,
1487 						     &from->sched,
1488 						     I915_DEPENDENCY_EXTERNAL);
1489 		if (ret < 0)
1490 			return ret;
1491 	}
1492 
1493 	if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
1494 		ret = await_request_submit(to, from);
1495 	else
1496 		ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1497 	if (ret < 0)
1498 		return ret;
1499 
1500 	return 0;
1501 }
1502 
1503 int
1504 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1505 {
1506 	struct dma_fence **child = &fence;
1507 	unsigned int nchild = 1;
1508 	int ret;
1509 
1510 	/*
1511 	 * Note that if the fence-array was created in signal-on-any mode,
1512 	 * we should *not* decompose it into its individual fences. However,
1513 	 * we don't currently store which mode the fence-array is operating
1514 	 * in. Fortunately, the only user of signal-on-any is private to
1515 	 * amdgpu and we should not see any incoming fence-array from
1516 	 * sync-file being in signal-on-any mode.
1517 	 */
1518 	if (dma_fence_is_array(fence)) {
1519 		struct dma_fence_array *array = to_dma_fence_array(fence);
1520 
1521 		child = array->fences;
1522 		nchild = array->num_fences;
1523 		GEM_BUG_ON(!nchild);
1524 	}
1525 
1526 	do {
1527 		fence = *child++;
1528 		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1529 			continue;
1530 
1531 		/*
1532 		 * Requests on the same timeline are explicitly ordered, along
1533 		 * with their dependencies, by i915_request_add() which ensures
1534 		 * that requests are submitted in-order through each ring.
1535 		 */
1536 		if (fence->context == rq->fence.context)
1537 			continue;
1538 
1539 		/* Squash repeated waits to the same timelines */
1540 		if (fence->context &&
1541 		    intel_timeline_sync_is_later(i915_request_timeline(rq),
1542 						 fence))
1543 			continue;
1544 
1545 		if (dma_fence_is_i915(fence))
1546 			ret = i915_request_await_request(rq, to_request(fence));
1547 		else
1548 			ret = i915_request_await_external(rq, fence);
1549 		if (ret < 0)
1550 			return ret;
1551 
1552 		/* Record the latest fence used against each timeline */
1553 		if (fence->context)
1554 			intel_timeline_sync_set(i915_request_timeline(rq),
1555 						fence);
1556 	} while (--nchild);
1557 
1558 	return 0;
1559 }
1560 
1561 /**
1562  * i915_request_await_object - set this request to (async) wait upon a bo
1563  * @to: request we are wishing to use
1564  * @obj: object which may be in use on another ring.
1565  * @write: whether the wait is on behalf of a writer
1566  *
1567  * This code is meant to abstract object synchronization with the GPU.
1568  * Conceptually we serialise writes between engines inside the GPU.
1569  * We only allow one engine to write into a buffer at any time, but
1570  * multiple readers. To ensure each has a coherent view of memory, we must:
1571  *
1572  * - If there is an outstanding write request to the object, the new
1573  *   request must wait for it to complete (either CPU or in hw, requests
1574  *   on the same ring will be naturally ordered).
1575  *
1576  * - If we are a write request (pending_write_domain is set), the new
1577  *   request must wait for outstanding read requests to complete.
1578  *
1579  * Returns 0 if successful, else propagates up the lower layer error.
1580  */
1581 int
1582 i915_request_await_object(struct i915_request *to,
1583 			  struct drm_i915_gem_object *obj,
1584 			  bool write)
1585 {
1586 	struct dma_fence *excl;
1587 	int ret = 0;
1588 
1589 	if (write) {
1590 		struct dma_fence **shared;
1591 		unsigned int count, i;
1592 
1593 		ret = dma_resv_get_fences(obj->base.resv, &excl, &count,
1594 					  &shared);
1595 		if (ret)
1596 			return ret;
1597 
1598 		for (i = 0; i < count; i++) {
1599 			ret = i915_request_await_dma_fence(to, shared[i]);
1600 			if (ret)
1601 				break;
1602 
1603 			dma_fence_put(shared[i]);
1604 		}
1605 
1606 		for (; i < count; i++)
1607 			dma_fence_put(shared[i]);
1608 		kfree(shared);
1609 	} else {
1610 		excl = dma_resv_get_excl_unlocked(obj->base.resv);
1611 	}
1612 
1613 	if (excl) {
1614 		if (ret == 0)
1615 			ret = i915_request_await_dma_fence(to, excl);
1616 
1617 		dma_fence_put(excl);
1618 	}
1619 
1620 	return ret;
1621 }
1622 
1623 static struct i915_request *
1624 __i915_request_add_to_timeline(struct i915_request *rq)
1625 {
1626 	struct intel_timeline *timeline = i915_request_timeline(rq);
1627 	struct i915_request *prev;
1628 
1629 	/*
1630 	 * Dependency tracking and request ordering along the timeline
1631 	 * is special cased so that we can eliminate redundant ordering
1632 	 * operations while building the request (we know that the timeline
1633 	 * itself is ordered, and here we guarantee it).
1634 	 *
1635 	 * As we know we will need to emit tracking along the timeline,
1636 	 * we embed the hooks into our request struct -- at the cost of
1637 	 * having to have specialised no-allocation interfaces (which will
1638 	 * be beneficial elsewhere).
1639 	 *
1640 	 * A second benefit to open-coding i915_request_await_request is
1641 	 * that we can apply a slight variant of the rules specialised
1642 	 * for timelines that jump between engines (such as virtual engines).
1643 	 * If we consider the case of virtual engine, we must emit a dma-fence
1644 	 * to prevent scheduling of the second request until the first is
1645 	 * complete (to maximise our greedy late load balancing) and this
1646 	 * precludes optimising to use semaphores serialisation of a single
1647 	 * timeline across engines.
1648 	 */
1649 	prev = to_request(__i915_active_fence_set(&timeline->last_request,
1650 						  &rq->fence));
1651 	if (prev && !__i915_request_is_complete(prev)) {
1652 		/*
1653 		 * The requests are supposed to be kept in order. However,
1654 		 * we need to be wary in case the timeline->last_request
1655 		 * is used as a barrier for external modification to this
1656 		 * context.
1657 		 */
1658 		GEM_BUG_ON(prev->context == rq->context &&
1659 			   i915_seqno_passed(prev->fence.seqno,
1660 					     rq->fence.seqno));
1661 
1662 		if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask))
1663 			i915_sw_fence_await_sw_fence(&rq->submit,
1664 						     &prev->submit,
1665 						     &rq->submitq);
1666 		else
1667 			__i915_sw_fence_await_dma_fence(&rq->submit,
1668 							&prev->fence,
1669 							&rq->dmaq);
1670 		if (rq->engine->schedule)
1671 			__i915_sched_node_add_dependency(&rq->sched,
1672 							 &prev->sched,
1673 							 &rq->dep,
1674 							 0);
1675 	}
1676 
1677 	/*
1678 	 * Make sure that no request gazumped us - if it was allocated after
1679 	 * our i915_request_alloc() and called __i915_request_add() before
1680 	 * us, the timeline will hold its seqno which is later than ours.
1681 	 */
1682 	GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1683 
1684 	return prev;
1685 }
1686 
1687 /*
1688  * NB: This function is not allowed to fail. Doing so would mean the the
1689  * request is not being tracked for completion but the work itself is
1690  * going to happen on the hardware. This would be a Bad Thing(tm).
1691  */
1692 struct i915_request *__i915_request_commit(struct i915_request *rq)
1693 {
1694 	struct intel_engine_cs *engine = rq->engine;
1695 	struct intel_ring *ring = rq->ring;
1696 	u32 *cs;
1697 
1698 	RQ_TRACE(rq, "\n");
1699 
1700 	/*
1701 	 * To ensure that this call will not fail, space for its emissions
1702 	 * should already have been reserved in the ring buffer. Let the ring
1703 	 * know that it is time to use that space up.
1704 	 */
1705 	GEM_BUG_ON(rq->reserved_space > ring->space);
1706 	rq->reserved_space = 0;
1707 	rq->emitted_jiffies = jiffies;
1708 
1709 	/*
1710 	 * Record the position of the start of the breadcrumb so that
1711 	 * should we detect the updated seqno part-way through the
1712 	 * GPU processing the request, we never over-estimate the
1713 	 * position of the ring's HEAD.
1714 	 */
1715 	cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1716 	GEM_BUG_ON(IS_ERR(cs));
1717 	rq->postfix = intel_ring_offset(rq, cs);
1718 
1719 	return __i915_request_add_to_timeline(rq);
1720 }
1721 
1722 void __i915_request_queue_bh(struct i915_request *rq)
1723 {
1724 	i915_sw_fence_commit(&rq->semaphore);
1725 	i915_sw_fence_commit(&rq->submit);
1726 }
1727 
1728 void __i915_request_queue(struct i915_request *rq,
1729 			  const struct i915_sched_attr *attr)
1730 {
1731 	/*
1732 	 * Let the backend know a new request has arrived that may need
1733 	 * to adjust the existing execution schedule due to a high priority
1734 	 * request - i.e. we may want to preempt the current request in order
1735 	 * to run a high priority dependency chain *before* we can execute this
1736 	 * request.
1737 	 *
1738 	 * This is called before the request is ready to run so that we can
1739 	 * decide whether to preempt the entire chain so that it is ready to
1740 	 * run at the earliest possible convenience.
1741 	 */
1742 	if (attr && rq->engine->schedule)
1743 		rq->engine->schedule(rq, attr);
1744 
1745 	local_bh_disable();
1746 	__i915_request_queue_bh(rq);
1747 	local_bh_enable(); /* kick tasklets */
1748 }
1749 
1750 void i915_request_add(struct i915_request *rq)
1751 {
1752 	struct intel_timeline * const tl = i915_request_timeline(rq);
1753 	struct i915_sched_attr attr = {};
1754 	struct i915_gem_context *ctx;
1755 
1756 	lockdep_assert_held(&tl->mutex);
1757 	lockdep_unpin_lock(&tl->mutex, rq->cookie);
1758 
1759 	trace_i915_request_add(rq);
1760 	__i915_request_commit(rq);
1761 
1762 	/* XXX placeholder for selftests */
1763 	rcu_read_lock();
1764 	ctx = rcu_dereference(rq->context->gem_context);
1765 	if (ctx)
1766 		attr = ctx->sched;
1767 	rcu_read_unlock();
1768 
1769 	__i915_request_queue(rq, &attr);
1770 
1771 	mutex_unlock(&tl->mutex);
1772 }
1773 
1774 static unsigned long local_clock_ns(unsigned int *cpu)
1775 {
1776 	unsigned long t;
1777 
1778 	/*
1779 	 * Cheaply and approximately convert from nanoseconds to microseconds.
1780 	 * The result and subsequent calculations are also defined in the same
1781 	 * approximate microseconds units. The principal source of timing
1782 	 * error here is from the simple truncation.
1783 	 *
1784 	 * Note that local_clock() is only defined wrt to the current CPU;
1785 	 * the comparisons are no longer valid if we switch CPUs. Instead of
1786 	 * blocking preemption for the entire busywait, we can detect the CPU
1787 	 * switch and use that as indicator of system load and a reason to
1788 	 * stop busywaiting, see busywait_stop().
1789 	 */
1790 	*cpu = get_cpu();
1791 	t = local_clock();
1792 	put_cpu();
1793 
1794 	return t;
1795 }
1796 
1797 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1798 {
1799 	unsigned int this_cpu;
1800 
1801 	if (time_after(local_clock_ns(&this_cpu), timeout))
1802 		return true;
1803 
1804 	return this_cpu != cpu;
1805 }
1806 
1807 static bool __i915_spin_request(struct i915_request * const rq, int state)
1808 {
1809 	unsigned long timeout_ns;
1810 	unsigned int cpu;
1811 
1812 	/*
1813 	 * Only wait for the request if we know it is likely to complete.
1814 	 *
1815 	 * We don't track the timestamps around requests, nor the average
1816 	 * request length, so we do not have a good indicator that this
1817 	 * request will complete within the timeout. What we do know is the
1818 	 * order in which requests are executed by the context and so we can
1819 	 * tell if the request has been started. If the request is not even
1820 	 * running yet, it is a fair assumption that it will not complete
1821 	 * within our relatively short timeout.
1822 	 */
1823 	if (!i915_request_is_running(rq))
1824 		return false;
1825 
1826 	/*
1827 	 * When waiting for high frequency requests, e.g. during synchronous
1828 	 * rendering split between the CPU and GPU, the finite amount of time
1829 	 * required to set up the irq and wait upon it limits the response
1830 	 * rate. By busywaiting on the request completion for a short while we
1831 	 * can service the high frequency waits as quick as possible. However,
1832 	 * if it is a slow request, we want to sleep as quickly as possible.
1833 	 * The tradeoff between waiting and sleeping is roughly the time it
1834 	 * takes to sleep on a request, on the order of a microsecond.
1835 	 */
1836 
1837 	timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1838 	timeout_ns += local_clock_ns(&cpu);
1839 	do {
1840 		if (dma_fence_is_signaled(&rq->fence))
1841 			return true;
1842 
1843 		if (signal_pending_state(state, current))
1844 			break;
1845 
1846 		if (busywait_stop(timeout_ns, cpu))
1847 			break;
1848 
1849 		cpu_relax();
1850 	} while (!need_resched());
1851 
1852 	return false;
1853 }
1854 
1855 struct request_wait {
1856 	struct dma_fence_cb cb;
1857 	struct task_struct *tsk;
1858 };
1859 
1860 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1861 {
1862 	struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1863 
1864 	wake_up_process(fetch_and_zero(&wait->tsk));
1865 }
1866 
1867 /**
1868  * i915_request_wait - wait until execution of request has finished
1869  * @rq: the request to wait upon
1870  * @flags: how to wait
1871  * @timeout: how long to wait in jiffies
1872  *
1873  * i915_request_wait() waits for the request to be completed, for a
1874  * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1875  * unbounded wait).
1876  *
1877  * Returns the remaining time (in jiffies) if the request completed, which may
1878  * be zero or -ETIME if the request is unfinished after the timeout expires.
1879  * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1880  * pending before the request completes.
1881  */
1882 long i915_request_wait(struct i915_request *rq,
1883 		       unsigned int flags,
1884 		       long timeout)
1885 {
1886 	const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1887 		TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1888 	struct request_wait wait;
1889 
1890 	might_sleep();
1891 	GEM_BUG_ON(timeout < 0);
1892 
1893 	if (dma_fence_is_signaled(&rq->fence))
1894 		return timeout;
1895 
1896 	if (!timeout)
1897 		return -ETIME;
1898 
1899 	trace_i915_request_wait_begin(rq, flags);
1900 
1901 	/*
1902 	 * We must never wait on the GPU while holding a lock as we
1903 	 * may need to perform a GPU reset. So while we don't need to
1904 	 * serialise wait/reset with an explicit lock, we do want
1905 	 * lockdep to detect potential dependency cycles.
1906 	 */
1907 	mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1908 
1909 	/*
1910 	 * Optimistic spin before touching IRQs.
1911 	 *
1912 	 * We may use a rather large value here to offset the penalty of
1913 	 * switching away from the active task. Frequently, the client will
1914 	 * wait upon an old swapbuffer to throttle itself to remain within a
1915 	 * frame of the gpu. If the client is running in lockstep with the gpu,
1916 	 * then it should not be waiting long at all, and a sleep now will incur
1917 	 * extra scheduler latency in producing the next frame. To try to
1918 	 * avoid adding the cost of enabling/disabling the interrupt to the
1919 	 * short wait, we first spin to see if the request would have completed
1920 	 * in the time taken to setup the interrupt.
1921 	 *
1922 	 * We need upto 5us to enable the irq, and upto 20us to hide the
1923 	 * scheduler latency of a context switch, ignoring the secondary
1924 	 * impacts from a context switch such as cache eviction.
1925 	 *
1926 	 * The scheme used for low-latency IO is called "hybrid interrupt
1927 	 * polling". The suggestion there is to sleep until just before you
1928 	 * expect to be woken by the device interrupt and then poll for its
1929 	 * completion. That requires having a good predictor for the request
1930 	 * duration, which we currently lack.
1931 	 */
1932 	if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) &&
1933 	    __i915_spin_request(rq, state))
1934 		goto out;
1935 
1936 	/*
1937 	 * This client is about to stall waiting for the GPU. In many cases
1938 	 * this is undesirable and limits the throughput of the system, as
1939 	 * many clients cannot continue processing user input/output whilst
1940 	 * blocked. RPS autotuning may take tens of milliseconds to respond
1941 	 * to the GPU load and thus incurs additional latency for the client.
1942 	 * We can circumvent that by promoting the GPU frequency to maximum
1943 	 * before we sleep. This makes the GPU throttle up much more quickly
1944 	 * (good for benchmarks and user experience, e.g. window animations),
1945 	 * but at a cost of spending more power processing the workload
1946 	 * (bad for battery).
1947 	 */
1948 	if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
1949 		intel_rps_boost(rq);
1950 
1951 	wait.tsk = current;
1952 	if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1953 		goto out;
1954 
1955 	/*
1956 	 * Flush the submission tasklet, but only if it may help this request.
1957 	 *
1958 	 * We sometimes experience some latency between the HW interrupts and
1959 	 * tasklet execution (mostly due to ksoftirqd latency, but it can also
1960 	 * be due to lazy CS events), so lets run the tasklet manually if there
1961 	 * is a chance it may submit this request. If the request is not ready
1962 	 * to run, as it is waiting for other fences to be signaled, flushing
1963 	 * the tasklet is busy work without any advantage for this client.
1964 	 *
1965 	 * If the HW is being lazy, this is the last chance before we go to
1966 	 * sleep to catch any pending events. We will check periodically in
1967 	 * the heartbeat to flush the submission tasklets as a last resort
1968 	 * for unhappy HW.
1969 	 */
1970 	if (i915_request_is_ready(rq))
1971 		__intel_engine_flush_submission(rq->engine, false);
1972 
1973 	for (;;) {
1974 		set_current_state(state);
1975 
1976 		if (dma_fence_is_signaled(&rq->fence))
1977 			break;
1978 
1979 		if (signal_pending_state(state, current)) {
1980 			timeout = -ERESTARTSYS;
1981 			break;
1982 		}
1983 
1984 		if (!timeout) {
1985 			timeout = -ETIME;
1986 			break;
1987 		}
1988 
1989 		timeout = io_schedule_timeout(timeout);
1990 	}
1991 	__set_current_state(TASK_RUNNING);
1992 
1993 	if (READ_ONCE(wait.tsk))
1994 		dma_fence_remove_callback(&rq->fence, &wait.cb);
1995 	GEM_BUG_ON(!list_empty(&wait.cb.node));
1996 
1997 out:
1998 	mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1999 	trace_i915_request_wait_end(rq);
2000 	return timeout;
2001 }
2002 
2003 static int print_sched_attr(const struct i915_sched_attr *attr,
2004 			    char *buf, int x, int len)
2005 {
2006 	if (attr->priority == I915_PRIORITY_INVALID)
2007 		return x;
2008 
2009 	x += snprintf(buf + x, len - x,
2010 		      " prio=%d", attr->priority);
2011 
2012 	return x;
2013 }
2014 
2015 static char queue_status(const struct i915_request *rq)
2016 {
2017 	if (i915_request_is_active(rq))
2018 		return 'E';
2019 
2020 	if (i915_request_is_ready(rq))
2021 		return intel_engine_is_virtual(rq->engine) ? 'V' : 'R';
2022 
2023 	return 'U';
2024 }
2025 
2026 static const char *run_status(const struct i915_request *rq)
2027 {
2028 	if (__i915_request_is_complete(rq))
2029 		return "!";
2030 
2031 	if (__i915_request_has_started(rq))
2032 		return "*";
2033 
2034 	if (!i915_sw_fence_signaled(&rq->semaphore))
2035 		return "&";
2036 
2037 	return "";
2038 }
2039 
2040 static const char *fence_status(const struct i915_request *rq)
2041 {
2042 	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
2043 		return "+";
2044 
2045 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
2046 		return "-";
2047 
2048 	return "";
2049 }
2050 
2051 void i915_request_show(struct drm_printer *m,
2052 		       const struct i915_request *rq,
2053 		       const char *prefix,
2054 		       int indent)
2055 {
2056 	const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence);
2057 	char buf[80] = "";
2058 	int x = 0;
2059 
2060 	/*
2061 	 * The prefix is used to show the queue status, for which we use
2062 	 * the following flags:
2063 	 *
2064 	 *  U [Unready]
2065 	 *    - initial status upon being submitted by the user
2066 	 *
2067 	 *    - the request is not ready for execution as it is waiting
2068 	 *      for external fences
2069 	 *
2070 	 *  R [Ready]
2071 	 *    - all fences the request was waiting on have been signaled,
2072 	 *      and the request is now ready for execution and will be
2073 	 *      in a backend queue
2074 	 *
2075 	 *    - a ready request may still need to wait on semaphores
2076 	 *      [internal fences]
2077 	 *
2078 	 *  V [Ready/virtual]
2079 	 *    - same as ready, but queued over multiple backends
2080 	 *
2081 	 *  E [Executing]
2082 	 *    - the request has been transferred from the backend queue and
2083 	 *      submitted for execution on HW
2084 	 *
2085 	 *    - a completed request may still be regarded as executing, its
2086 	 *      status may not be updated until it is retired and removed
2087 	 *      from the lists
2088 	 */
2089 
2090 	x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
2091 
2092 	drm_printf(m, "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n",
2093 		   prefix, indent, "                ",
2094 		   queue_status(rq),
2095 		   rq->fence.context, rq->fence.seqno,
2096 		   run_status(rq),
2097 		   fence_status(rq),
2098 		   buf,
2099 		   jiffies_to_msecs(jiffies - rq->emitted_jiffies),
2100 		   name);
2101 }
2102 
2103 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2104 #include "selftests/mock_request.c"
2105 #include "selftests/i915_request.c"
2106 #endif
2107 
2108 static void i915_global_request_shrink(void)
2109 {
2110 	kmem_cache_shrink(global.slab_execute_cbs);
2111 	kmem_cache_shrink(global.slab_requests);
2112 }
2113 
2114 static void i915_global_request_exit(void)
2115 {
2116 	kmem_cache_destroy(global.slab_execute_cbs);
2117 	kmem_cache_destroy(global.slab_requests);
2118 }
2119 
2120 static struct i915_global_request global = { {
2121 	.shrink = i915_global_request_shrink,
2122 	.exit = i915_global_request_exit,
2123 } };
2124 
2125 int __init i915_global_request_init(void)
2126 {
2127 	global.slab_requests =
2128 		kmem_cache_create("i915_request",
2129 				  sizeof(struct i915_request),
2130 				  __alignof__(struct i915_request),
2131 				  SLAB_HWCACHE_ALIGN |
2132 				  SLAB_RECLAIM_ACCOUNT |
2133 				  SLAB_TYPESAFE_BY_RCU,
2134 				  __i915_request_ctor);
2135 	if (!global.slab_requests)
2136 		return -ENOMEM;
2137 
2138 	global.slab_execute_cbs = KMEM_CACHE(execute_cb,
2139 					     SLAB_HWCACHE_ALIGN |
2140 					     SLAB_RECLAIM_ACCOUNT |
2141 					     SLAB_TYPESAFE_BY_RCU);
2142 	if (!global.slab_execute_cbs)
2143 		goto err_requests;
2144 
2145 	i915_global_register(&global.base);
2146 	return 0;
2147 
2148 err_requests:
2149 	kmem_cache_destroy(global.slab_requests);
2150 	return -ENOMEM;
2151 }
2152