1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 30 31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 32 33 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) 34 #define _MASKED_BIT_DISABLE(a) ((a) << 16) 35 36 /* PCI config space */ 37 38 #define HPLLCC 0xc0 /* 855 only */ 39 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 40 #define GC_CLOCK_133_200 (0 << 0) 41 #define GC_CLOCK_100_200 (1 << 0) 42 #define GC_CLOCK_100_133 (2 << 0) 43 #define GC_CLOCK_166_250 (3 << 0) 44 #define GCFGC2 0xda 45 #define GCFGC 0xf0 /* 915+ only */ 46 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 47 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 48 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 49 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 50 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 51 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 52 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 53 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 54 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 55 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 56 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 57 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 58 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 59 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 60 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 61 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 62 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 63 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 64 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 65 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 66 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 67 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 68 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 69 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 70 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 71 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 72 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 73 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 74 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 75 #define LBB 0xf4 76 77 /* Graphics reset regs */ 78 #define I965_GDRST 0xc0 /* PCI config register */ 79 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 80 #define GRDOM_FULL (0<<2) 81 #define GRDOM_RENDER (1<<2) 82 #define GRDOM_MEDIA (3<<2) 83 #define GRDOM_MASK (3<<2) 84 #define GRDOM_RESET_ENABLE (1<<0) 85 86 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 87 #define GEN6_MBC_SNPCR_SHIFT 21 88 #define GEN6_MBC_SNPCR_MASK (3<<21) 89 #define GEN6_MBC_SNPCR_MAX (0<<21) 90 #define GEN6_MBC_SNPCR_MED (1<<21) 91 #define GEN6_MBC_SNPCR_LOW (2<<21) 92 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 93 94 #define GEN6_MBCTL 0x0907c 95 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 96 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 97 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 98 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 99 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 100 101 #define GEN6_GDRST 0x941c 102 #define GEN6_GRDOM_FULL (1 << 0) 103 #define GEN6_GRDOM_RENDER (1 << 1) 104 #define GEN6_GRDOM_MEDIA (1 << 2) 105 #define GEN6_GRDOM_BLT (1 << 3) 106 107 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 108 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 109 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 110 #define PP_DIR_DCLV_2G 0xffffffff 111 112 #define GAM_ECOCHK 0x4090 113 #define ECOCHK_SNB_BIT (1<<10) 114 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 115 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 116 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 117 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 118 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 119 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 120 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 121 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 122 123 #define GAC_ECO_BITS 0x14090 124 #define ECOBITS_SNB_BIT (1<<13) 125 #define ECOBITS_PPGTT_CACHE64B (3<<8) 126 #define ECOBITS_PPGTT_CACHE4B (0<<8) 127 128 #define GAB_CTL 0x24000 129 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 130 131 /* VGA stuff */ 132 133 #define VGA_ST01_MDA 0x3ba 134 #define VGA_ST01_CGA 0x3da 135 136 #define VGA_MSR_WRITE 0x3c2 137 #define VGA_MSR_READ 0x3cc 138 #define VGA_MSR_MEM_EN (1<<1) 139 #define VGA_MSR_CGA_MODE (1<<0) 140 141 #define VGA_SR_INDEX 0x3c4 142 #define SR01 1 143 #define VGA_SR_DATA 0x3c5 144 145 #define VGA_AR_INDEX 0x3c0 146 #define VGA_AR_VID_EN (1<<5) 147 #define VGA_AR_DATA_WRITE 0x3c0 148 #define VGA_AR_DATA_READ 0x3c1 149 150 #define VGA_GR_INDEX 0x3ce 151 #define VGA_GR_DATA 0x3cf 152 /* GR05 */ 153 #define VGA_GR_MEM_READ_MODE_SHIFT 3 154 #define VGA_GR_MEM_READ_MODE_PLANE 1 155 /* GR06 */ 156 #define VGA_GR_MEM_MODE_MASK 0xc 157 #define VGA_GR_MEM_MODE_SHIFT 2 158 #define VGA_GR_MEM_A0000_AFFFF 0 159 #define VGA_GR_MEM_A0000_BFFFF 1 160 #define VGA_GR_MEM_B0000_B7FFF 2 161 #define VGA_GR_MEM_B0000_BFFFF 3 162 163 #define VGA_DACMASK 0x3c6 164 #define VGA_DACRX 0x3c7 165 #define VGA_DACWX 0x3c8 166 #define VGA_DACDATA 0x3c9 167 168 #define VGA_CR_INDEX_MDA 0x3b4 169 #define VGA_CR_DATA_MDA 0x3b5 170 #define VGA_CR_INDEX_CGA 0x3d4 171 #define VGA_CR_DATA_CGA 0x3d5 172 173 /* 174 * Memory interface instructions used by the kernel 175 */ 176 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 177 178 #define MI_NOOP MI_INSTR(0, 0) 179 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 180 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 181 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 182 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 183 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 184 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 185 #define MI_FLUSH MI_INSTR(0x04, 0) 186 #define MI_READ_FLUSH (1 << 0) 187 #define MI_EXE_FLUSH (1 << 1) 188 #define MI_NO_WRITE_FLUSH (1 << 2) 189 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 190 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 191 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 192 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 193 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 194 #define MI_SUSPEND_FLUSH_EN (1<<0) 195 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 196 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 197 #define MI_OVERLAY_CONTINUE (0x0<<21) 198 #define MI_OVERLAY_ON (0x1<<21) 199 #define MI_OVERLAY_OFF (0x2<<21) 200 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 201 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 202 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 203 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 204 /* IVB has funny definitions for which plane to flip. */ 205 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 206 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 207 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 208 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 209 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 210 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 211 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 212 #define MI_ARB_ENABLE (1<<0) 213 #define MI_ARB_DISABLE (0<<0) 214 215 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 216 #define MI_MM_SPACE_GTT (1<<8) 217 #define MI_MM_SPACE_PHYSICAL (0<<8) 218 #define MI_SAVE_EXT_STATE_EN (1<<3) 219 #define MI_RESTORE_EXT_STATE_EN (1<<2) 220 #define MI_FORCE_RESTORE (1<<1) 221 #define MI_RESTORE_INHIBIT (1<<0) 222 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 223 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 224 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 225 #define MI_STORE_DWORD_INDEX_SHIFT 2 226 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 227 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 228 * simply ignores the register load under certain conditions. 229 * - One can actually load arbitrary many arbitrary registers: Simply issue x 230 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 231 */ 232 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 233 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) 234 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 235 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 236 #define MI_INVALIDATE_TLB (1<<18) 237 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 238 #define MI_INVALIDATE_BSD (1<<7) 239 #define MI_FLUSH_DW_USE_GTT (1<<2) 240 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 241 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 242 #define MI_BATCH_NON_SECURE (1) 243 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 244 #define MI_BATCH_NON_SECURE_I965 (1<<8) 245 #define MI_BATCH_PPGTT_HSW (1<<8) 246 #define MI_BATCH_NON_SECURE_HSW (1<<13) 247 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 248 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 249 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 250 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 251 #define MI_SEMAPHORE_UPDATE (1<<21) 252 #define MI_SEMAPHORE_COMPARE (1<<20) 253 #define MI_SEMAPHORE_REGISTER (1<<18) 254 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 255 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 256 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 257 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 258 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 259 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 260 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 261 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 262 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 263 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 264 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 265 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 266 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 267 /* 268 * 3D instructions used by the kernel 269 */ 270 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 271 272 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 273 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 274 #define SC_UPDATE_SCISSOR (0x1<<1) 275 #define SC_ENABLE_MASK (0x1<<0) 276 #define SC_ENABLE (0x1<<0) 277 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 278 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 279 #define SCI_YMIN_MASK (0xffff<<16) 280 #define SCI_XMIN_MASK (0xffff<<0) 281 #define SCI_YMAX_MASK (0xffff<<16) 282 #define SCI_XMAX_MASK (0xffff<<0) 283 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 284 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 285 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 286 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 287 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 288 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 289 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 290 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 291 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 292 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 293 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 294 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 295 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 296 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 297 #define BLT_DEPTH_8 (0<<24) 298 #define BLT_DEPTH_16_565 (1<<24) 299 #define BLT_DEPTH_16_1555 (2<<24) 300 #define BLT_DEPTH_32 (3<<24) 301 #define BLT_ROP_GXCOPY (0xcc<<16) 302 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 303 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 304 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 305 #define ASYNC_FLIP (1<<22) 306 #define DISPLAY_PLANE_A (0<<20) 307 #define DISPLAY_PLANE_B (1<<20) 308 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 309 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 310 #define PIPE_CONTROL_CS_STALL (1<<20) 311 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 312 #define PIPE_CONTROL_QW_WRITE (1<<14) 313 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 314 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 315 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 316 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 317 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 318 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 319 #define PIPE_CONTROL_NOTIFY (1<<8) 320 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 321 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 322 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 323 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 324 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 325 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 326 327 328 /* 329 * Reset registers 330 */ 331 #define DEBUG_RESET_I830 0x6070 332 #define DEBUG_RESET_FULL (1<<7) 333 #define DEBUG_RESET_RENDER (1<<8) 334 #define DEBUG_RESET_DISPLAY (1<<9) 335 336 /* 337 * IOSF sideband 338 */ 339 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 340 #define IOSF_DEVFN_SHIFT 24 341 #define IOSF_OPCODE_SHIFT 16 342 #define IOSF_PORT_SHIFT 8 343 #define IOSF_BYTE_ENABLES_SHIFT 4 344 #define IOSF_BAR_SHIFT 1 345 #define IOSF_SB_BUSY (1<<0) 346 #define IOSF_PORT_PUNIT 0x4 347 #define IOSF_PORT_NC 0x11 348 #define IOSF_PORT_DPIO 0x12 349 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 350 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 351 352 #define PUNIT_OPCODE_REG_READ 6 353 #define PUNIT_OPCODE_REG_WRITE 7 354 355 #define PUNIT_REG_GPU_LFM 0xd3 356 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 357 #define PUNIT_REG_GPU_FREQ_STS 0xd8 358 #define GENFREQSTATUS (1<<0) 359 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 360 361 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 362 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 363 364 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 365 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 366 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 367 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 368 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 369 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 370 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 371 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 372 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 373 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 374 375 /* 376 * DPIO - a special bus for various display related registers to hide behind 377 * 378 * DPIO is VLV only. 379 * 380 * Note: digital port B is DDI0, digital pot C is DDI1 381 */ 382 #define DPIO_DEVFN 0 383 #define DPIO_OPCODE_REG_WRITE 1 384 #define DPIO_OPCODE_REG_READ 0 385 386 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) 387 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 388 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 389 #define DPIO_SFR_BYPASS (1<<1) 390 #define DPIO_RESET (1<<0) 391 392 #define _DPIO_TX3_SWING_CTL4_A 0x690 393 #define _DPIO_TX3_SWING_CTL4_B 0x2a90 394 #define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \ 395 _DPIO_TX3_SWING_CTL4_B) 396 397 /* 398 * Per pipe/PLL DPIO regs 399 */ 400 #define _DPIO_DIV_A 0x800c 401 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 402 #define DPIO_POST_DIV_DAC 0 403 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 404 #define DPIO_POST_DIV_LVDS1 2 405 #define DPIO_POST_DIV_LVDS2 3 406 #define DPIO_K_SHIFT (24) /* 4 bits */ 407 #define DPIO_P1_SHIFT (21) /* 3 bits */ 408 #define DPIO_P2_SHIFT (16) /* 5 bits */ 409 #define DPIO_N_SHIFT (12) /* 4 bits */ 410 #define DPIO_ENABLE_CALIBRATION (1<<11) 411 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 412 #define DPIO_M2DIV_MASK 0xff 413 #define _DPIO_DIV_B 0x802c 414 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) 415 416 #define _DPIO_REFSFR_A 0x8014 417 #define DPIO_REFSEL_OVERRIDE 27 418 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 419 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 420 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 421 #define DPIO_PLL_REFCLK_SEL_MASK 3 422 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 423 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 424 #define _DPIO_REFSFR_B 0x8034 425 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) 426 427 #define _DPIO_CORE_CLK_A 0x801c 428 #define _DPIO_CORE_CLK_B 0x803c 429 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) 430 431 #define _DPIO_IREF_CTL_A 0x8040 432 #define _DPIO_IREF_CTL_B 0x8060 433 #define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) 434 435 #define DPIO_IREF_BCAST 0xc044 436 #define _DPIO_IREF_A 0x8044 437 #define _DPIO_IREF_B 0x8064 438 #define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B) 439 440 #define _DPIO_PLL_CML_A 0x804c 441 #define _DPIO_PLL_CML_B 0x806c 442 #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) 443 444 #define _DPIO_LPF_COEFF_A 0x8048 445 #define _DPIO_LPF_COEFF_B 0x8068 446 #define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B) 447 448 #define DPIO_CALIBRATION 0x80ac 449 450 #define DPIO_FASTCLK_DISABLE 0x8100 451 452 /* 453 * Per DDI channel DPIO regs 454 */ 455 456 #define _DPIO_PCS_TX_0 0x8200 457 #define _DPIO_PCS_TX_1 0x8400 458 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 459 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 460 #define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1) 461 462 #define _DPIO_PCS_CLK_0 0x8204 463 #define _DPIO_PCS_CLK_1 0x8404 464 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 465 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 466 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 467 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 468 #define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1) 469 470 #define _DPIO_PCS_CTL_OVR1_A 0x8224 471 #define _DPIO_PCS_CTL_OVR1_B 0x8424 472 #define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \ 473 _DPIO_PCS_CTL_OVR1_B) 474 475 #define _DPIO_PCS_STAGGER0_A 0x822c 476 #define _DPIO_PCS_STAGGER0_B 0x842c 477 #define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \ 478 _DPIO_PCS_STAGGER0_B) 479 480 #define _DPIO_PCS_STAGGER1_A 0x8230 481 #define _DPIO_PCS_STAGGER1_B 0x8430 482 #define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \ 483 _DPIO_PCS_STAGGER1_B) 484 485 #define _DPIO_PCS_CLOCKBUF0_A 0x8238 486 #define _DPIO_PCS_CLOCKBUF0_B 0x8438 487 #define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \ 488 _DPIO_PCS_CLOCKBUF0_B) 489 490 #define _DPIO_PCS_CLOCKBUF8_A 0x825c 491 #define _DPIO_PCS_CLOCKBUF8_B 0x845c 492 #define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \ 493 _DPIO_PCS_CLOCKBUF8_B) 494 495 #define _DPIO_TX_SWING_CTL2_A 0x8288 496 #define _DPIO_TX_SWING_CTL2_B 0x8488 497 #define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \ 498 _DPIO_TX_SWING_CTL2_B) 499 500 #define _DPIO_TX_SWING_CTL3_A 0x828c 501 #define _DPIO_TX_SWING_CTL3_B 0x848c 502 #define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \ 503 _DPIO_TX_SWING_CTL3_B) 504 505 #define _DPIO_TX_SWING_CTL4_A 0x8290 506 #define _DPIO_TX_SWING_CTL4_B 0x8490 507 #define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \ 508 _DPIO_TX_SWING_CTL4_B) 509 510 #define _DPIO_TX_OCALINIT_0 0x8294 511 #define _DPIO_TX_OCALINIT_1 0x8494 512 #define DPIO_TX_OCALINIT_EN (1<<31) 513 #define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \ 514 _DPIO_TX_OCALINIT_1) 515 516 #define _DPIO_TX_CTL_0 0x82ac 517 #define _DPIO_TX_CTL_1 0x84ac 518 #define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1) 519 520 #define _DPIO_TX_LANE_0 0x82b8 521 #define _DPIO_TX_LANE_1 0x84b8 522 #define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1) 523 524 #define _DPIO_DATA_CHANNEL1 0x8220 525 #define _DPIO_DATA_CHANNEL2 0x8420 526 #define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2) 527 528 #define _DPIO_PORT0_PCS0 0x0220 529 #define _DPIO_PORT0_PCS1 0x0420 530 #define _DPIO_PORT1_PCS2 0x2620 531 #define _DPIO_PORT1_PCS3 0x2820 532 #define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2) 533 #define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3) 534 #define DPIO_DATA_CHANNEL1 0x8220 535 #define DPIO_DATA_CHANNEL2 0x8420 536 537 /* 538 * Fence registers 539 */ 540 #define FENCE_REG_830_0 0x2000 541 #define FENCE_REG_945_8 0x3000 542 #define I830_FENCE_START_MASK 0x07f80000 543 #define I830_FENCE_TILING_Y_SHIFT 12 544 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 545 #define I830_FENCE_PITCH_SHIFT 4 546 #define I830_FENCE_REG_VALID (1<<0) 547 #define I915_FENCE_MAX_PITCH_VAL 4 548 #define I830_FENCE_MAX_PITCH_VAL 6 549 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 550 551 #define I915_FENCE_START_MASK 0x0ff00000 552 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 553 554 #define FENCE_REG_965_0 0x03000 555 #define I965_FENCE_PITCH_SHIFT 2 556 #define I965_FENCE_TILING_Y_SHIFT 1 557 #define I965_FENCE_REG_VALID (1<<0) 558 #define I965_FENCE_MAX_PITCH_VAL 0x0400 559 560 #define FENCE_REG_SANDYBRIDGE_0 0x100000 561 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 562 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 563 564 /* control register for cpu gtt access */ 565 #define TILECTL 0x101000 566 #define TILECTL_SWZCTL (1 << 0) 567 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 568 #define TILECTL_BACKSNOOP_DIS (1 << 3) 569 570 /* 571 * Instruction and interrupt control regs 572 */ 573 #define PGTBL_ER 0x02024 574 #define RENDER_RING_BASE 0x02000 575 #define BSD_RING_BASE 0x04000 576 #define GEN6_BSD_RING_BASE 0x12000 577 #define VEBOX_RING_BASE 0x1a000 578 #define BLT_RING_BASE 0x22000 579 #define RING_TAIL(base) ((base)+0x30) 580 #define RING_HEAD(base) ((base)+0x34) 581 #define RING_START(base) ((base)+0x38) 582 #define RING_CTL(base) ((base)+0x3c) 583 #define RING_SYNC_0(base) ((base)+0x40) 584 #define RING_SYNC_1(base) ((base)+0x44) 585 #define RING_SYNC_2(base) ((base)+0x48) 586 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 587 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 588 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 589 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 590 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 591 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 592 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 593 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 594 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 595 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 596 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 597 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 598 #define GEN6_NOSYNC 0 599 #define RING_MAX_IDLE(base) ((base)+0x54) 600 #define RING_HWS_PGA(base) ((base)+0x80) 601 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 602 #define ARB_MODE 0x04030 603 #define ARB_MODE_SWIZZLE_SNB (1<<4) 604 #define ARB_MODE_SWIZZLE_IVB (1<<5) 605 #define RENDER_HWS_PGA_GEN7 (0x04080) 606 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 607 #define DONE_REG 0x40b0 608 #define BSD_HWS_PGA_GEN7 (0x04180) 609 #define BLT_HWS_PGA_GEN7 (0x04280) 610 #define VEBOX_HWS_PGA_GEN7 (0x04380) 611 #define RING_ACTHD(base) ((base)+0x74) 612 #define RING_NOPID(base) ((base)+0x94) 613 #define RING_IMR(base) ((base)+0xa8) 614 #define RING_TIMESTAMP(base) ((base)+0x358) 615 #define TAIL_ADDR 0x001FFFF8 616 #define HEAD_WRAP_COUNT 0xFFE00000 617 #define HEAD_WRAP_ONE 0x00200000 618 #define HEAD_ADDR 0x001FFFFC 619 #define RING_NR_PAGES 0x001FF000 620 #define RING_REPORT_MASK 0x00000006 621 #define RING_REPORT_64K 0x00000002 622 #define RING_REPORT_128K 0x00000004 623 #define RING_NO_REPORT 0x00000000 624 #define RING_VALID_MASK 0x00000001 625 #define RING_VALID 0x00000001 626 #define RING_INVALID 0x00000000 627 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 628 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 629 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 630 #if 0 631 #define PRB0_TAIL 0x02030 632 #define PRB0_HEAD 0x02034 633 #define PRB0_START 0x02038 634 #define PRB0_CTL 0x0203c 635 #define PRB1_TAIL 0x02040 /* 915+ only */ 636 #define PRB1_HEAD 0x02044 /* 915+ only */ 637 #define PRB1_START 0x02048 /* 915+ only */ 638 #define PRB1_CTL 0x0204c /* 915+ only */ 639 #endif 640 #define IPEIR_I965 0x02064 641 #define IPEHR_I965 0x02068 642 #define INSTDONE_I965 0x0206c 643 #define GEN7_INSTDONE_1 0x0206c 644 #define GEN7_SC_INSTDONE 0x07100 645 #define GEN7_SAMPLER_INSTDONE 0x0e160 646 #define GEN7_ROW_INSTDONE 0x0e164 647 #define I915_NUM_INSTDONE_REG 4 648 #define RING_IPEIR(base) ((base)+0x64) 649 #define RING_IPEHR(base) ((base)+0x68) 650 #define RING_INSTDONE(base) ((base)+0x6c) 651 #define RING_INSTPS(base) ((base)+0x70) 652 #define RING_DMA_FADD(base) ((base)+0x78) 653 #define RING_INSTPM(base) ((base)+0xc0) 654 #define INSTPS 0x02070 /* 965+ only */ 655 #define INSTDONE1 0x0207c /* 965+ only */ 656 #define ACTHD_I965 0x02074 657 #define HWS_PGA 0x02080 658 #define HWS_ADDRESS_MASK 0xfffff000 659 #define HWS_START_ADDRESS_SHIFT 4 660 #define PWRCTXA 0x2088 /* 965GM+ only */ 661 #define PWRCTX_EN (1<<0) 662 #define IPEIR 0x02088 663 #define IPEHR 0x0208c 664 #define INSTDONE 0x02090 665 #define NOPID 0x02094 666 #define HWSTAM 0x02098 667 #define DMA_FADD_I8XX 0x020d0 668 669 #define ERROR_GEN6 0x040a0 670 #define GEN7_ERR_INT 0x44040 671 #define ERR_INT_POISON (1<<31) 672 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 673 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 674 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 675 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 676 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 677 678 #define FPGA_DBG 0x42300 679 #define FPGA_DBG_RM_NOCLAIM (1<<31) 680 681 #define DERRMR 0x44050 682 #define DERRMR_PIPEA_SCANLINE (1<<0) 683 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 684 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 685 #define DERRMR_PIPEA_VBLANK (1<<3) 686 #define DERRMR_PIPEA_HBLANK (1<<5) 687 #define DERRMR_PIPEB_SCANLINE (1<<8) 688 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 689 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 690 #define DERRMR_PIPEB_VBLANK (1<<11) 691 #define DERRMR_PIPEB_HBLANK (1<<13) 692 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 693 #define DERRMR_PIPEC_SCANLINE (1<<14) 694 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 695 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 696 #define DERRMR_PIPEC_VBLANK (1<<21) 697 #define DERRMR_PIPEC_HBLANK (1<<22) 698 699 700 /* GM45+ chicken bits -- debug workaround bits that may be required 701 * for various sorts of correct behavior. The top 16 bits of each are 702 * the enables for writing to the corresponding low bit. 703 */ 704 #define _3D_CHICKEN 0x02084 705 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 706 #define _3D_CHICKEN2 0x0208c 707 /* Disables pipelining of read flushes past the SF-WIZ interface. 708 * Required on all Ironlake steppings according to the B-Spec, but the 709 * particular danger of not doing so is not specified. 710 */ 711 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 712 #define _3D_CHICKEN3 0x02090 713 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 714 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 715 716 #define MI_MODE 0x0209c 717 # define VS_TIMER_DISPATCH (1 << 6) 718 # define MI_FLUSH_ENABLE (1 << 12) 719 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 720 721 #define GEN6_GT_MODE 0x20d0 722 #define GEN6_GT_MODE_HI (1 << 9) 723 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 724 725 #define GFX_MODE 0x02520 726 #define GFX_MODE_GEN7 0x0229c 727 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 728 #define GFX_RUN_LIST_ENABLE (1<<15) 729 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 730 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 731 #define GFX_REPLAY_MODE (1<<11) 732 #define GFX_PSMI_GRANULARITY (1<<10) 733 #define GFX_PPGTT_ENABLE (1<<9) 734 735 #define VLV_DISPLAY_BASE 0x180000 736 737 #define SCPD0 0x0209c /* 915+ only */ 738 #define IER 0x020a0 739 #define IIR 0x020a4 740 #define IMR 0x020a8 741 #define ISR 0x020ac 742 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) 743 #define GCFG_DIS (1<<8) 744 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) 745 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) 746 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) 747 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) 748 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) 749 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) 750 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 751 #define EIR 0x020b0 752 #define EMR 0x020b4 753 #define ESR 0x020b8 754 #define GM45_ERROR_PAGE_TABLE (1<<5) 755 #define GM45_ERROR_MEM_PRIV (1<<4) 756 #define I915_ERROR_PAGE_TABLE (1<<4) 757 #define GM45_ERROR_CP_PRIV (1<<3) 758 #define I915_ERROR_MEMORY_REFRESH (1<<1) 759 #define I915_ERROR_INSTRUCTION (1<<0) 760 #define INSTPM 0x020c0 761 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 762 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 763 will not assert AGPBUSY# and will only 764 be delivered when out of C3. */ 765 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 766 #define INSTPM_TLB_INVALIDATE (1<<9) 767 #define INSTPM_SYNC_FLUSH (1<<5) 768 #define ACTHD 0x020c8 769 #define FW_BLC 0x020d8 770 #define FW_BLC2 0x020dc 771 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 772 #define FW_BLC_SELF_EN_MASK (1<<31) 773 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 774 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 775 #define MM_BURST_LENGTH 0x00700000 776 #define MM_FIFO_WATERMARK 0x0001F000 777 #define LM_BURST_LENGTH 0x00000700 778 #define LM_FIFO_WATERMARK 0x0000001F 779 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 780 781 /* Make render/texture TLB fetches lower priorty than associated data 782 * fetches. This is not turned on by default 783 */ 784 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 785 786 /* Isoch request wait on GTT enable (Display A/B/C streams). 787 * Make isoch requests stall on the TLB update. May cause 788 * display underruns (test mode only) 789 */ 790 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 791 792 /* Block grant count for isoch requests when block count is 793 * set to a finite value. 794 */ 795 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 796 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 797 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 798 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 799 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 800 801 /* Enable render writes to complete in C2/C3/C4 power states. 802 * If this isn't enabled, render writes are prevented in low 803 * power states. That seems bad to me. 804 */ 805 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 806 807 /* This acknowledges an async flip immediately instead 808 * of waiting for 2TLB fetches. 809 */ 810 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 811 812 /* Enables non-sequential data reads through arbiter 813 */ 814 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 815 816 /* Disable FSB snooping of cacheable write cycles from binner/render 817 * command stream 818 */ 819 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 820 821 /* Arbiter time slice for non-isoch streams */ 822 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 823 #define MI_ARB_TIME_SLICE_1 (0 << 5) 824 #define MI_ARB_TIME_SLICE_2 (1 << 5) 825 #define MI_ARB_TIME_SLICE_4 (2 << 5) 826 #define MI_ARB_TIME_SLICE_6 (3 << 5) 827 #define MI_ARB_TIME_SLICE_8 (4 << 5) 828 #define MI_ARB_TIME_SLICE_10 (5 << 5) 829 #define MI_ARB_TIME_SLICE_14 (6 << 5) 830 #define MI_ARB_TIME_SLICE_16 (7 << 5) 831 832 /* Low priority grace period page size */ 833 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 834 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 835 836 /* Disable display A/B trickle feed */ 837 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 838 839 /* Set display plane priority */ 840 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 841 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 842 843 #define CACHE_MODE_0 0x02120 /* 915+ only */ 844 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 845 #define CM0_IZ_OPT_DISABLE (1<<6) 846 #define CM0_ZR_OPT_DISABLE (1<<5) 847 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 848 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 849 #define CM0_COLOR_EVICT_DISABLE (1<<3) 850 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 851 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 852 #define BB_ADDR 0x02140 /* 8 bytes */ 853 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 854 #define GFX_FLSH_CNTL_GEN6 0x101008 855 #define GFX_FLSH_CNTL_EN (1<<0) 856 #define ECOSKPD 0x021d0 857 #define ECO_GATING_CX_ONLY (1<<3) 858 #define ECO_FLIP_DONE (1<<0) 859 860 #define CACHE_MODE_1 0x7004 /* IVB+ */ 861 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 862 863 #define GEN6_BLITTER_ECOSKPD 0x221d0 864 #define GEN6_BLITTER_LOCK_SHIFT 16 865 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 866 867 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 868 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 869 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 870 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 871 #define GEN6_BSD_GO_INDICATOR (1 << 4) 872 873 /* On modern GEN architectures interrupt control consists of two sets 874 * of registers. The first set pertains to the ring generating the 875 * interrupt. The second control is for the functional block generating the 876 * interrupt. These are PM, GT, DE, etc. 877 * 878 * Luckily *knocks on wood* all the ring interrupt bits match up with the 879 * GT interrupt bits, so we don't need to duplicate the defines. 880 * 881 * These defines should cover us well from SNB->HSW with minor exceptions 882 * it can also work on ILK. 883 */ 884 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 885 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 886 #define GT_BLT_USER_INTERRUPT (1 << 22) 887 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 888 #define GT_BSD_USER_INTERRUPT (1 << 12) 889 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 890 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 891 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 892 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 893 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 894 #define GT_RENDER_USER_INTERRUPT (1 << 0) 895 896 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 897 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 898 899 /* These are all the "old" interrupts */ 900 #define ILK_BSD_USER_INTERRUPT (1<<5) 901 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 902 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 903 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 904 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 905 #define I915_HWB_OOM_INTERRUPT (1<<13) 906 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 907 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 908 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 909 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 910 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 911 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 912 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 913 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 914 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 915 #define I915_DEBUG_INTERRUPT (1<<2) 916 #define I915_USER_INTERRUPT (1<<1) 917 #define I915_ASLE_INTERRUPT (1<<0) 918 #define I915_BSD_USER_INTERRUPT (1 << 25) 919 920 #define GEN6_BSD_RNCID 0x12198 921 922 #define GEN7_FF_THREAD_MODE 0x20a0 923 #define GEN7_FF_SCHED_MASK 0x0077070 924 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 925 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 926 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 927 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 928 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 929 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 930 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 931 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 932 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 933 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 934 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 935 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 936 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 937 938 /* 939 * Framebuffer compression (915+ only) 940 */ 941 942 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 943 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 944 #define FBC_CONTROL 0x03208 945 #define FBC_CTL_EN (1<<31) 946 #define FBC_CTL_PERIODIC (1<<30) 947 #define FBC_CTL_INTERVAL_SHIFT (16) 948 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 949 #define FBC_CTL_C3_IDLE (1<<13) 950 #define FBC_CTL_STRIDE_SHIFT (5) 951 #define FBC_CTL_FENCENO (1<<0) 952 #define FBC_COMMAND 0x0320c 953 #define FBC_CMD_COMPRESS (1<<0) 954 #define FBC_STATUS 0x03210 955 #define FBC_STAT_COMPRESSING (1<<31) 956 #define FBC_STAT_COMPRESSED (1<<30) 957 #define FBC_STAT_MODIFIED (1<<29) 958 #define FBC_STAT_CURRENT_LINE (1<<0) 959 #define FBC_CONTROL2 0x03214 960 #define FBC_CTL_FENCE_DBL (0<<4) 961 #define FBC_CTL_IDLE_IMM (0<<2) 962 #define FBC_CTL_IDLE_FULL (1<<2) 963 #define FBC_CTL_IDLE_LINE (2<<2) 964 #define FBC_CTL_IDLE_DEBUG (3<<2) 965 #define FBC_CTL_CPU_FENCE (1<<1) 966 #define FBC_CTL_PLANEA (0<<0) 967 #define FBC_CTL_PLANEB (1<<0) 968 #define FBC_FENCE_OFF 0x0321b 969 #define FBC_TAG 0x03300 970 971 #define FBC_LL_SIZE (1536) 972 973 /* Framebuffer compression for GM45+ */ 974 #define DPFC_CB_BASE 0x3200 975 #define DPFC_CONTROL 0x3208 976 #define DPFC_CTL_EN (1<<31) 977 #define DPFC_CTL_PLANEA (0<<30) 978 #define DPFC_CTL_PLANEB (1<<30) 979 #define IVB_DPFC_CTL_PLANE_SHIFT (29) 980 #define DPFC_CTL_FENCE_EN (1<<29) 981 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 982 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 983 #define DPFC_SR_EN (1<<10) 984 #define DPFC_CTL_LIMIT_1X (0<<6) 985 #define DPFC_CTL_LIMIT_2X (1<<6) 986 #define DPFC_CTL_LIMIT_4X (2<<6) 987 #define DPFC_RECOMP_CTL 0x320c 988 #define DPFC_RECOMP_STALL_EN (1<<27) 989 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 990 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 991 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 992 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 993 #define DPFC_STATUS 0x3210 994 #define DPFC_INVAL_SEG_SHIFT (16) 995 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 996 #define DPFC_COMP_SEG_SHIFT (0) 997 #define DPFC_COMP_SEG_MASK (0x000003ff) 998 #define DPFC_STATUS2 0x3214 999 #define DPFC_FENCE_YOFF 0x3218 1000 #define DPFC_CHICKEN 0x3224 1001 #define DPFC_HT_MODIFY (1<<31) 1002 1003 /* Framebuffer compression for Ironlake */ 1004 #define ILK_DPFC_CB_BASE 0x43200 1005 #define ILK_DPFC_CONTROL 0x43208 1006 /* The bit 28-8 is reserved */ 1007 #define DPFC_RESERVED (0x1FFFFF00) 1008 #define ILK_DPFC_RECOMP_CTL 0x4320c 1009 #define ILK_DPFC_STATUS 0x43210 1010 #define ILK_DPFC_FENCE_YOFF 0x43218 1011 #define ILK_DPFC_CHICKEN 0x43224 1012 #define ILK_FBC_RT_BASE 0x2128 1013 #define ILK_FBC_RT_VALID (1<<0) 1014 #define SNB_FBC_FRONT_BUFFER (1<<1) 1015 1016 #define ILK_DISPLAY_CHICKEN1 0x42000 1017 #define ILK_FBCQ_DIS (1<<22) 1018 #define ILK_PABSTRETCH_DIS (1<<21) 1019 1020 1021 /* 1022 * Framebuffer compression for Sandybridge 1023 * 1024 * The following two registers are of type GTTMMADR 1025 */ 1026 #define SNB_DPFC_CTL_SA 0x100100 1027 #define SNB_CPU_FENCE_ENABLE (1<<29) 1028 #define DPFC_CPU_FENCE_OFFSET 0x100104 1029 1030 /* Framebuffer compression for Ivybridge */ 1031 #define IVB_FBC_RT_BASE 0x7020 1032 1033 #define IPS_CTL 0x43408 1034 #define IPS_ENABLE (1 << 31) 1035 1036 #define MSG_FBC_REND_STATE 0x50380 1037 #define FBC_REND_NUKE (1<<2) 1038 #define FBC_REND_CACHE_CLEAN (1<<1) 1039 1040 #define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 1041 #define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 1042 #define HSW_BYPASS_FBC_QUEUE (1<<22) 1043 #define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \ 1044 _HSW_PIPE_SLICE_CHICKEN_1_A, + \ 1045 _HSW_PIPE_SLICE_CHICKEN_1_B) 1046 1047 #define HSW_CLKGATE_DISABLE_PART_1 0x46500 1048 #define HSW_DPFC_GATING_DISABLE (1<<23) 1049 1050 /* 1051 * GPIO regs 1052 */ 1053 #define GPIOA 0x5010 1054 #define GPIOB 0x5014 1055 #define GPIOC 0x5018 1056 #define GPIOD 0x501c 1057 #define GPIOE 0x5020 1058 #define GPIOF 0x5024 1059 #define GPIOG 0x5028 1060 #define GPIOH 0x502c 1061 # define GPIO_CLOCK_DIR_MASK (1 << 0) 1062 # define GPIO_CLOCK_DIR_IN (0 << 1) 1063 # define GPIO_CLOCK_DIR_OUT (1 << 1) 1064 # define GPIO_CLOCK_VAL_MASK (1 << 2) 1065 # define GPIO_CLOCK_VAL_OUT (1 << 3) 1066 # define GPIO_CLOCK_VAL_IN (1 << 4) 1067 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1068 # define GPIO_DATA_DIR_MASK (1 << 8) 1069 # define GPIO_DATA_DIR_IN (0 << 9) 1070 # define GPIO_DATA_DIR_OUT (1 << 9) 1071 # define GPIO_DATA_VAL_MASK (1 << 10) 1072 # define GPIO_DATA_VAL_OUT (1 << 11) 1073 # define GPIO_DATA_VAL_IN (1 << 12) 1074 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1075 1076 #define GMBUS0 0x5100 /* clock/port select */ 1077 #define GMBUS_RATE_100KHZ (0<<8) 1078 #define GMBUS_RATE_50KHZ (1<<8) 1079 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 1080 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 1081 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 1082 #define GMBUS_PORT_DISABLED 0 1083 #define GMBUS_PORT_SSC 1 1084 #define GMBUS_PORT_VGADDC 2 1085 #define GMBUS_PORT_PANEL 3 1086 #define GMBUS_PORT_DPC 4 /* HDMIC */ 1087 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 1088 #define GMBUS_PORT_DPD 6 /* HDMID */ 1089 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 1090 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 1091 #define GMBUS1 0x5104 /* command/status */ 1092 #define GMBUS_SW_CLR_INT (1<<31) 1093 #define GMBUS_SW_RDY (1<<30) 1094 #define GMBUS_ENT (1<<29) /* enable timeout */ 1095 #define GMBUS_CYCLE_NONE (0<<25) 1096 #define GMBUS_CYCLE_WAIT (1<<25) 1097 #define GMBUS_CYCLE_INDEX (2<<25) 1098 #define GMBUS_CYCLE_STOP (4<<25) 1099 #define GMBUS_BYTE_COUNT_SHIFT 16 1100 #define GMBUS_SLAVE_INDEX_SHIFT 8 1101 #define GMBUS_SLAVE_ADDR_SHIFT 1 1102 #define GMBUS_SLAVE_READ (1<<0) 1103 #define GMBUS_SLAVE_WRITE (0<<0) 1104 #define GMBUS2 0x5108 /* status */ 1105 #define GMBUS_INUSE (1<<15) 1106 #define GMBUS_HW_WAIT_PHASE (1<<14) 1107 #define GMBUS_STALL_TIMEOUT (1<<13) 1108 #define GMBUS_INT (1<<12) 1109 #define GMBUS_HW_RDY (1<<11) 1110 #define GMBUS_SATOER (1<<10) 1111 #define GMBUS_ACTIVE (1<<9) 1112 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 1113 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 1114 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 1115 #define GMBUS_NAK_EN (1<<3) 1116 #define GMBUS_IDLE_EN (1<<2) 1117 #define GMBUS_HW_WAIT_EN (1<<1) 1118 #define GMBUS_HW_RDY_EN (1<<0) 1119 #define GMBUS5 0x5120 /* byte index */ 1120 #define GMBUS_2BYTE_INDEX_EN (1<<31) 1121 1122 /* 1123 * Clock control & power management 1124 */ 1125 1126 #define VGA0 0x6000 1127 #define VGA1 0x6004 1128 #define VGA_PD 0x6010 1129 #define VGA0_PD_P2_DIV_4 (1 << 7) 1130 #define VGA0_PD_P1_DIV_2 (1 << 5) 1131 #define VGA0_PD_P1_SHIFT 0 1132 #define VGA0_PD_P1_MASK (0x1f << 0) 1133 #define VGA1_PD_P2_DIV_4 (1 << 15) 1134 #define VGA1_PD_P1_DIV_2 (1 << 13) 1135 #define VGA1_PD_P1_SHIFT 8 1136 #define VGA1_PD_P1_MASK (0x1f << 8) 1137 #define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) 1138 #define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) 1139 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) 1140 #define DPLL_VCO_ENABLE (1 << 31) 1141 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1142 #define DPLL_DVO_2X_MODE (1 << 30) 1143 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1144 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1145 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 1146 #define DPLL_VGA_MODE_DIS (1 << 28) 1147 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1148 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1149 #define DPLL_MODE_MASK (3 << 26) 1150 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1151 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1152 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1153 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1154 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1155 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1156 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1157 #define DPLL_LOCK_VLV (1<<15) 1158 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 1159 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 1160 #define DPLL_PORTC_READY_MASK (0xf << 4) 1161 #define DPLL_PORTB_READY_MASK (0xf) 1162 1163 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1164 /* 1165 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1166 * this field (only one bit may be set). 1167 */ 1168 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1169 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1170 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1171 /* i830, required in DVO non-gang */ 1172 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1173 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1174 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1175 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1176 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1177 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1178 #define PLL_REF_INPUT_MASK (3 << 13) 1179 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1180 /* Ironlake */ 1181 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1182 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1183 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 1184 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1185 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1186 1187 /* 1188 * Parallel to Serial Load Pulse phase selection. 1189 * Selects the phase for the 10X DPLL clock for the PCIe 1190 * digital display port. The range is 4 to 13; 10 or more 1191 * is just a flip delay. The default is 6 1192 */ 1193 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1194 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1195 /* 1196 * SDVO multiplier for 945G/GM. Not used on 965. 1197 */ 1198 #define SDVO_MULTIPLIER_MASK 0x000000ff 1199 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1200 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1201 #define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */ 1202 /* 1203 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1204 * 1205 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1206 */ 1207 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1208 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1209 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1210 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1211 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1212 /* 1213 * SDVO/UDI pixel multiplier. 1214 * 1215 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1216 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1217 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1218 * dummy bytes in the datastream at an increased clock rate, with both sides of 1219 * the link knowing how many bytes are fill. 1220 * 1221 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1222 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1223 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1224 * through an SDVO command. 1225 * 1226 * This register field has values of multiplication factor minus 1, with 1227 * a maximum multiplier of 5 for SDVO. 1228 */ 1229 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1230 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1231 /* 1232 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1233 * This best be set to the default value (3) or the CRT won't work. No, 1234 * I don't entirely understand what this does... 1235 */ 1236 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1237 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1238 #define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */ 1239 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) 1240 1241 #define _FPA0 0x06040 1242 #define _FPA1 0x06044 1243 #define _FPB0 0x06048 1244 #define _FPB1 0x0604c 1245 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1246 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1247 #define FP_N_DIV_MASK 0x003f0000 1248 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1249 #define FP_N_DIV_SHIFT 16 1250 #define FP_M1_DIV_MASK 0x00003f00 1251 #define FP_M1_DIV_SHIFT 8 1252 #define FP_M2_DIV_MASK 0x0000003f 1253 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1254 #define FP_M2_DIV_SHIFT 0 1255 #define DPLL_TEST 0x606c 1256 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1257 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1258 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1259 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1260 #define DPLLB_TEST_N_BYPASS (1 << 19) 1261 #define DPLLB_TEST_M_BYPASS (1 << 18) 1262 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1263 #define DPLLA_TEST_N_BYPASS (1 << 3) 1264 #define DPLLA_TEST_M_BYPASS (1 << 2) 1265 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1266 #define D_STATE 0x6104 1267 #define DSTATE_GFX_RESET_I830 (1<<6) 1268 #define DSTATE_PLL_D3_OFF (1<<3) 1269 #define DSTATE_GFX_CLOCK_GATING (1<<1) 1270 #define DSTATE_DOT_CLOCK_GATING (1<<0) 1271 #define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) 1272 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1273 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1274 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1275 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1276 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1277 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1278 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1279 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1280 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1281 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1282 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1283 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1284 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1285 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1286 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1287 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1288 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1289 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1290 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1291 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1292 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1293 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1294 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1295 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1296 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1297 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1298 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1299 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1300 /** 1301 * This bit must be set on the 830 to prevent hangs when turning off the 1302 * overlay scaler. 1303 */ 1304 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1305 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1306 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1307 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1308 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1309 1310 #define RENCLK_GATE_D1 0x6204 1311 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1312 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1313 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1314 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1315 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1316 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1317 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1318 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1319 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1320 /** This bit must be unset on 855,865 */ 1321 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1322 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1323 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1324 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1325 /** This bit must be set on 855,865. */ 1326 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1327 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1328 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1329 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1330 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1331 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1332 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1333 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1334 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1335 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1336 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1337 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1338 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1339 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1340 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1341 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1342 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1343 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1344 1345 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1346 /** This bit must always be set on 965G/965GM */ 1347 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1348 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1349 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1350 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1351 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1352 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1353 /** This bit must always be set on 965G */ 1354 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1355 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1356 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1357 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1358 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1359 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1360 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1361 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1362 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1363 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1364 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1365 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1366 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1367 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1368 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1369 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1370 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1371 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1372 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1373 1374 #define RENCLK_GATE_D2 0x6208 1375 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1376 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1377 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1378 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1379 #define DEUC 0x6214 /* CRL only */ 1380 1381 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) 1382 #define FW_CSPWRDWNEN (1<<15) 1383 1384 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) 1385 1386 /* 1387 * Palette regs 1388 */ 1389 1390 #define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) 1391 #define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) 1392 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1393 1394 /* MCH MMIO space */ 1395 1396 /* 1397 * MCHBAR mirror. 1398 * 1399 * This mirrors the MCHBAR MMIO space whose location is determined by 1400 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1401 * every way. It is not accessible from the CP register read instructions. 1402 * 1403 */ 1404 #define MCHBAR_MIRROR_BASE 0x10000 1405 1406 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1407 1408 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 1409 #define DCLK 0x5e04 1410 1411 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 1412 #define DCC 0x10200 1413 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1414 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1415 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1416 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1417 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1418 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1419 1420 /** Pineview MCH register contains DDR3 setting */ 1421 #define CSHRDDR3CTL 0x101a8 1422 #define CSHRDDR3CTL_DDR3 (1 << 2) 1423 1424 /** 965 MCH register controlling DRAM channel configuration */ 1425 #define C0DRB3 0x10206 1426 #define C1DRB3 0x10606 1427 1428 /** snb MCH registers for reading the DRAM channel configuration */ 1429 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 1430 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 1431 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 1432 #define MAD_DIMM_ECC_MASK (0x3 << 24) 1433 #define MAD_DIMM_ECC_OFF (0x0 << 24) 1434 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 1435 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 1436 #define MAD_DIMM_ECC_ON (0x3 << 24) 1437 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 1438 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 1439 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 1440 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 1441 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 1442 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 1443 #define MAD_DIMM_A_SELECT (0x1 << 16) 1444 /* DIMM sizes are in multiples of 256mb. */ 1445 #define MAD_DIMM_B_SIZE_SHIFT 8 1446 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 1447 #define MAD_DIMM_A_SIZE_SHIFT 0 1448 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 1449 1450 /** snb MCH registers for priority tuning */ 1451 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) 1452 #define MCH_SSKPD_WM0_MASK 0x3f 1453 #define MCH_SSKPD_WM0_VAL 0xc 1454 1455 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) 1456 1457 /* Clocking configuration register */ 1458 #define CLKCFG 0x10c00 1459 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1460 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1461 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1462 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1463 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1464 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1465 /* Note, below two are guess */ 1466 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1467 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1468 #define CLKCFG_FSB_MASK (7 << 0) 1469 #define CLKCFG_MEM_533 (1 << 4) 1470 #define CLKCFG_MEM_667 (2 << 4) 1471 #define CLKCFG_MEM_800 (3 << 4) 1472 #define CLKCFG_MEM_MASK (7 << 4) 1473 1474 #define TSC1 0x11001 1475 #define TSE (1<<0) 1476 #define TR1 0x11006 1477 #define TSFS 0x11020 1478 #define TSFS_SLOPE_MASK 0x0000ff00 1479 #define TSFS_SLOPE_SHIFT 8 1480 #define TSFS_INTR_MASK 0x000000ff 1481 1482 #define CRSTANDVID 0x11100 1483 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1484 #define PXVFREQ_PX_MASK 0x7f000000 1485 #define PXVFREQ_PX_SHIFT 24 1486 #define VIDFREQ_BASE 0x11110 1487 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1488 #define VIDFREQ2 0x11114 1489 #define VIDFREQ3 0x11118 1490 #define VIDFREQ4 0x1111c 1491 #define VIDFREQ_P0_MASK 0x1f000000 1492 #define VIDFREQ_P0_SHIFT 24 1493 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1494 #define VIDFREQ_P0_CSCLK_SHIFT 20 1495 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1496 #define VIDFREQ_P0_CRCLK_SHIFT 16 1497 #define VIDFREQ_P1_MASK 0x00001f00 1498 #define VIDFREQ_P1_SHIFT 8 1499 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1500 #define VIDFREQ_P1_CSCLK_SHIFT 4 1501 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1502 #define INTTOEXT_BASE_ILK 0x11300 1503 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1504 #define INTTOEXT_MAP3_SHIFT 24 1505 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1506 #define INTTOEXT_MAP2_SHIFT 16 1507 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1508 #define INTTOEXT_MAP1_SHIFT 8 1509 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1510 #define INTTOEXT_MAP0_SHIFT 0 1511 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1512 #define MEMSWCTL 0x11170 /* Ironlake only */ 1513 #define MEMCTL_CMD_MASK 0xe000 1514 #define MEMCTL_CMD_SHIFT 13 1515 #define MEMCTL_CMD_RCLK_OFF 0 1516 #define MEMCTL_CMD_RCLK_ON 1 1517 #define MEMCTL_CMD_CHFREQ 2 1518 #define MEMCTL_CMD_CHVID 3 1519 #define MEMCTL_CMD_VMMOFF 4 1520 #define MEMCTL_CMD_VMMON 5 1521 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1522 when command complete */ 1523 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1524 #define MEMCTL_FREQ_SHIFT 8 1525 #define MEMCTL_SFCAVM (1<<7) 1526 #define MEMCTL_TGT_VID_MASK 0x007f 1527 #define MEMIHYST 0x1117c 1528 #define MEMINTREN 0x11180 /* 16 bits */ 1529 #define MEMINT_RSEXIT_EN (1<<8) 1530 #define MEMINT_CX_SUPR_EN (1<<7) 1531 #define MEMINT_CONT_BUSY_EN (1<<6) 1532 #define MEMINT_AVG_BUSY_EN (1<<5) 1533 #define MEMINT_EVAL_CHG_EN (1<<4) 1534 #define MEMINT_MON_IDLE_EN (1<<3) 1535 #define MEMINT_UP_EVAL_EN (1<<2) 1536 #define MEMINT_DOWN_EVAL_EN (1<<1) 1537 #define MEMINT_SW_CMD_EN (1<<0) 1538 #define MEMINTRSTR 0x11182 /* 16 bits */ 1539 #define MEM_RSEXIT_MASK 0xc000 1540 #define MEM_RSEXIT_SHIFT 14 1541 #define MEM_CONT_BUSY_MASK 0x3000 1542 #define MEM_CONT_BUSY_SHIFT 12 1543 #define MEM_AVG_BUSY_MASK 0x0c00 1544 #define MEM_AVG_BUSY_SHIFT 10 1545 #define MEM_EVAL_CHG_MASK 0x0300 1546 #define MEM_EVAL_BUSY_SHIFT 8 1547 #define MEM_MON_IDLE_MASK 0x00c0 1548 #define MEM_MON_IDLE_SHIFT 6 1549 #define MEM_UP_EVAL_MASK 0x0030 1550 #define MEM_UP_EVAL_SHIFT 4 1551 #define MEM_DOWN_EVAL_MASK 0x000c 1552 #define MEM_DOWN_EVAL_SHIFT 2 1553 #define MEM_SW_CMD_MASK 0x0003 1554 #define MEM_INT_STEER_GFX 0 1555 #define MEM_INT_STEER_CMR 1 1556 #define MEM_INT_STEER_SMI 2 1557 #define MEM_INT_STEER_SCI 3 1558 #define MEMINTRSTS 0x11184 1559 #define MEMINT_RSEXIT (1<<7) 1560 #define MEMINT_CONT_BUSY (1<<6) 1561 #define MEMINT_AVG_BUSY (1<<5) 1562 #define MEMINT_EVAL_CHG (1<<4) 1563 #define MEMINT_MON_IDLE (1<<3) 1564 #define MEMINT_UP_EVAL (1<<2) 1565 #define MEMINT_DOWN_EVAL (1<<1) 1566 #define MEMINT_SW_CMD (1<<0) 1567 #define MEMMODECTL 0x11190 1568 #define MEMMODE_BOOST_EN (1<<31) 1569 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1570 #define MEMMODE_BOOST_FREQ_SHIFT 24 1571 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1572 #define MEMMODE_IDLE_MODE_SHIFT 16 1573 #define MEMMODE_IDLE_MODE_EVAL 0 1574 #define MEMMODE_IDLE_MODE_CONT 1 1575 #define MEMMODE_HWIDLE_EN (1<<15) 1576 #define MEMMODE_SWMODE_EN (1<<14) 1577 #define MEMMODE_RCLK_GATE (1<<13) 1578 #define MEMMODE_HW_UPDATE (1<<12) 1579 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1580 #define MEMMODE_FSTART_SHIFT 8 1581 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1582 #define MEMMODE_FMAX_SHIFT 4 1583 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1584 #define RCBMAXAVG 0x1119c 1585 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1586 #define SWMEMCMD_RENDER_OFF (0 << 13) 1587 #define SWMEMCMD_RENDER_ON (1 << 13) 1588 #define SWMEMCMD_SWFREQ (2 << 13) 1589 #define SWMEMCMD_TARVID (3 << 13) 1590 #define SWMEMCMD_VRM_OFF (4 << 13) 1591 #define SWMEMCMD_VRM_ON (5 << 13) 1592 #define CMDSTS (1<<12) 1593 #define SFCAVM (1<<11) 1594 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1595 #define SWFREQ_SHIFT 7 1596 #define TARVID_MASK 0x001f 1597 #define MEMSTAT_CTG 0x111a0 1598 #define RCBMINAVG 0x111a0 1599 #define RCUPEI 0x111b0 1600 #define RCDNEI 0x111b4 1601 #define RSTDBYCTL 0x111b8 1602 #define RS1EN (1<<31) 1603 #define RS2EN (1<<30) 1604 #define RS3EN (1<<29) 1605 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1606 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1607 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1608 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1609 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1610 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1611 #define RSX_STATUS_MASK (7<<20) 1612 #define RSX_STATUS_ON (0<<20) 1613 #define RSX_STATUS_RC1 (1<<20) 1614 #define RSX_STATUS_RC1E (2<<20) 1615 #define RSX_STATUS_RS1 (3<<20) 1616 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1617 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1618 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1619 #define RSX_STATUS_RSVD2 (7<<20) 1620 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1621 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1622 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1623 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1624 #define RS1CONTSAV_MASK (3<<14) 1625 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1626 #define RS1CONTSAV_RSVD (1<<14) 1627 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1628 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1629 #define NORMSLEXLAT_MASK (3<<12) 1630 #define SLOW_RS123 (0<<12) 1631 #define SLOW_RS23 (1<<12) 1632 #define SLOW_RS3 (2<<12) 1633 #define NORMAL_RS123 (3<<12) 1634 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1635 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1636 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1637 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1638 #define RS_CSTATE_MASK (3<<4) 1639 #define RS_CSTATE_C367_RS1 (0<<4) 1640 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1641 #define RS_CSTATE_RSVD (2<<4) 1642 #define RS_CSTATE_C367_RS2 (3<<4) 1643 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1644 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1645 #define VIDCTL 0x111c0 1646 #define VIDSTS 0x111c8 1647 #define VIDSTART 0x111cc /* 8 bits */ 1648 #define MEMSTAT_ILK 0x111f8 1649 #define MEMSTAT_VID_MASK 0x7f00 1650 #define MEMSTAT_VID_SHIFT 8 1651 #define MEMSTAT_PSTATE_MASK 0x00f8 1652 #define MEMSTAT_PSTATE_SHIFT 3 1653 #define MEMSTAT_MON_ACTV (1<<2) 1654 #define MEMSTAT_SRC_CTL_MASK 0x0003 1655 #define MEMSTAT_SRC_CTL_CORE 0 1656 #define MEMSTAT_SRC_CTL_TRB 1 1657 #define MEMSTAT_SRC_CTL_THM 2 1658 #define MEMSTAT_SRC_CTL_STDBY 3 1659 #define RCPREVBSYTUPAVG 0x113b8 1660 #define RCPREVBSYTDNAVG 0x113bc 1661 #define PMMISC 0x11214 1662 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1663 #define SDEW 0x1124c 1664 #define CSIEW0 0x11250 1665 #define CSIEW1 0x11254 1666 #define CSIEW2 0x11258 1667 #define PEW 0x1125c 1668 #define DEW 0x11270 1669 #define MCHAFE 0x112c0 1670 #define CSIEC 0x112e0 1671 #define DMIEC 0x112e4 1672 #define DDREC 0x112e8 1673 #define PEG0EC 0x112ec 1674 #define PEG1EC 0x112f0 1675 #define GFXEC 0x112f4 1676 #define RPPREVBSYTUPAVG 0x113b8 1677 #define RPPREVBSYTDNAVG 0x113bc 1678 #define ECR 0x11600 1679 #define ECR_GPFE (1<<31) 1680 #define ECR_IMONE (1<<30) 1681 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1682 #define OGW0 0x11608 1683 #define OGW1 0x1160c 1684 #define EG0 0x11610 1685 #define EG1 0x11614 1686 #define EG2 0x11618 1687 #define EG3 0x1161c 1688 #define EG4 0x11620 1689 #define EG5 0x11624 1690 #define EG6 0x11628 1691 #define EG7 0x1162c 1692 #define PXW 0x11664 1693 #define PXWL 0x11680 1694 #define LCFUSE02 0x116c0 1695 #define LCFUSE_HIV_MASK 0x000000ff 1696 #define CSIPLL0 0x12c10 1697 #define DDRMPLL1 0X12c20 1698 #define PEG_BAND_GAP_DATA 0x14d68 1699 1700 #define GEN6_GT_THREAD_STATUS_REG 0x13805c 1701 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 1702 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) 1703 1704 #define GEN6_GT_PERF_STATUS 0x145948 1705 #define GEN6_RP_STATE_LIMITS 0x145994 1706 #define GEN6_RP_STATE_CAP 0x145998 1707 1708 /* 1709 * Logical Context regs 1710 */ 1711 #define CCID 0x2180 1712 #define CCID_EN (1<<0) 1713 /* 1714 * Notes on SNB/IVB/VLV context size: 1715 * - Power context is saved elsewhere (LLC or stolen) 1716 * - Ring/execlist context is saved on SNB, not on IVB 1717 * - Extended context size already includes render context size 1718 * - We always need to follow the extended context size. 1719 * SNB BSpec has comments indicating that we should use the 1720 * render context size instead if execlists are disabled, but 1721 * based on empirical testing that's just nonsense. 1722 * - Pipelined/VF state is saved on SNB/IVB respectively 1723 * - GT1 size just indicates how much of render context 1724 * doesn't need saving on GT1 1725 */ 1726 #define CXT_SIZE 0x21a0 1727 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 1728 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 1729 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 1730 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 1731 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 1732 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 1733 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 1734 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 1735 #define GEN7_CXT_SIZE 0x21a8 1736 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 1737 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 1738 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 1739 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 1740 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 1741 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 1742 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 1743 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 1744 /* Haswell does have the CXT_SIZE register however it does not appear to be 1745 * valid. Now, docs explain in dwords what is in the context object. The full 1746 * size is 70720 bytes, however, the power context and execlist context will 1747 * never be saved (power context is stored elsewhere, and execlists don't work 1748 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. 1749 */ 1750 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 1751 1752 /* 1753 * Overlay regs 1754 */ 1755 1756 #define OVADD 0x30000 1757 #define DOVSTA 0x30008 1758 #define OC_BUF (0x3<<20) 1759 #define OGAMC5 0x30010 1760 #define OGAMC4 0x30014 1761 #define OGAMC3 0x30018 1762 #define OGAMC2 0x3001c 1763 #define OGAMC1 0x30020 1764 #define OGAMC0 0x30024 1765 1766 /* 1767 * Display engine regs 1768 */ 1769 1770 /* Pipe A timing regs */ 1771 #define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) 1772 #define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) 1773 #define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008) 1774 #define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c) 1775 #define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010) 1776 #define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014) 1777 #define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c) 1778 #define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020) 1779 #define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028) 1780 1781 /* Pipe B timing regs */ 1782 #define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000) 1783 #define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004) 1784 #define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008) 1785 #define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c) 1786 #define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010) 1787 #define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) 1788 #define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) 1789 #define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) 1790 #define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) 1791 1792 1793 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) 1794 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) 1795 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) 1796 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) 1797 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) 1798 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) 1799 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1800 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) 1801 1802 /* HSW eDP PSR registers */ 1803 #define EDP_PSR_CTL 0x64800 1804 #define EDP_PSR_ENABLE (1<<31) 1805 #define EDP_PSR_LINK_DISABLE (0<<27) 1806 #define EDP_PSR_LINK_STANDBY (1<<27) 1807 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 1808 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 1809 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 1810 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 1811 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 1812 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 1813 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 1814 #define EDP_PSR_TP1_TP2_SEL (0<<11) 1815 #define EDP_PSR_TP1_TP3_SEL (1<<11) 1816 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 1817 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 1818 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 1819 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 1820 #define EDP_PSR_TP1_TIME_500us (0<<4) 1821 #define EDP_PSR_TP1_TIME_100us (1<<4) 1822 #define EDP_PSR_TP1_TIME_2500us (2<<4) 1823 #define EDP_PSR_TP1_TIME_0us (3<<4) 1824 #define EDP_PSR_IDLE_FRAME_SHIFT 0 1825 1826 #define EDP_PSR_AUX_CTL 0x64810 1827 #define EDP_PSR_AUX_DATA1 0x64814 1828 #define EDP_PSR_DPCD_COMMAND 0x80060000 1829 #define EDP_PSR_AUX_DATA2 0x64818 1830 #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) 1831 #define EDP_PSR_AUX_DATA3 0x6481c 1832 #define EDP_PSR_AUX_DATA4 0x64820 1833 #define EDP_PSR_AUX_DATA5 0x64824 1834 1835 #define EDP_PSR_STATUS_CTL 0x64840 1836 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 1837 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 1838 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 1839 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 1840 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 1841 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 1842 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 1843 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 1844 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 1845 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 1846 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 1847 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 1848 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 1849 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 1850 #define EDP_PSR_STATUS_COUNT_SHIFT 16 1851 #define EDP_PSR_STATUS_COUNT_MASK 0xf 1852 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 1853 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 1854 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 1855 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 1856 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 1857 #define EDP_PSR_STATUS_IDLE_MASK 0xf 1858 1859 #define EDP_PSR_PERF_CNT 0x64844 1860 #define EDP_PSR_PERF_CNT_MASK 0xffffff 1861 1862 #define EDP_PSR_DEBUG_CTL 0x64860 1863 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 1864 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 1865 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 1866 1867 /* VGA port control */ 1868 #define ADPA 0x61100 1869 #define PCH_ADPA 0xe1100 1870 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) 1871 1872 #define ADPA_DAC_ENABLE (1<<31) 1873 #define ADPA_DAC_DISABLE 0 1874 #define ADPA_PIPE_SELECT_MASK (1<<30) 1875 #define ADPA_PIPE_A_SELECT 0 1876 #define ADPA_PIPE_B_SELECT (1<<30) 1877 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 1878 /* CPT uses bits 29:30 for pch transcoder select */ 1879 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1880 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 1881 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 1882 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 1883 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 1884 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 1885 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 1886 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 1887 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 1888 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 1889 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 1890 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 1891 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 1892 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 1893 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 1894 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 1895 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 1896 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 1897 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 1898 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1899 #define ADPA_SETS_HVPOLARITY 0 1900 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 1901 #define ADPA_VSYNC_CNTL_ENABLE 0 1902 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 1903 #define ADPA_HSYNC_CNTL_ENABLE 0 1904 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1905 #define ADPA_VSYNC_ACTIVE_LOW 0 1906 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1907 #define ADPA_HSYNC_ACTIVE_LOW 0 1908 #define ADPA_DPMS_MASK (~(3<<10)) 1909 #define ADPA_DPMS_ON (0<<10) 1910 #define ADPA_DPMS_SUSPEND (1<<10) 1911 #define ADPA_DPMS_STANDBY (2<<10) 1912 #define ADPA_DPMS_OFF (3<<10) 1913 1914 1915 /* Hotplug control (945+ only) */ 1916 #define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110) 1917 #define PORTB_HOTPLUG_INT_EN (1 << 29) 1918 #define PORTC_HOTPLUG_INT_EN (1 << 28) 1919 #define PORTD_HOTPLUG_INT_EN (1 << 27) 1920 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1921 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1922 #define TV_HOTPLUG_INT_EN (1 << 18) 1923 #define CRT_HOTPLUG_INT_EN (1 << 9) 1924 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 1925 PORTC_HOTPLUG_INT_EN | \ 1926 PORTD_HOTPLUG_INT_EN | \ 1927 SDVOC_HOTPLUG_INT_EN | \ 1928 SDVOB_HOTPLUG_INT_EN | \ 1929 CRT_HOTPLUG_INT_EN) 1930 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1931 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1932 /* must use period 64 on GM45 according to docs */ 1933 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1934 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1935 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1936 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1937 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1938 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1939 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1940 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1941 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1942 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1943 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1944 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1945 1946 #define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) 1947 /* 1948 * HDMI/DP bits are gen4+ 1949 * 1950 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 1951 * Please check the detailed lore in the commit message for for experimental 1952 * evidence. 1953 */ 1954 #define PORTD_HOTPLUG_LIVE_STATUS (1 << 29) 1955 #define PORTC_HOTPLUG_LIVE_STATUS (1 << 28) 1956 #define PORTB_HOTPLUG_LIVE_STATUS (1 << 27) 1957 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 1958 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 1959 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 1960 /* CRT/TV common between gen3+ */ 1961 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1962 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1963 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1964 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1965 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1966 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1967 /* SDVO is different across gen3/4 */ 1968 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 1969 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 1970 /* 1971 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 1972 * since reality corrobates that they're the same as on gen3. But keep these 1973 * bits here (and the comment!) to help any other lost wanderers back onto the 1974 * right tracks. 1975 */ 1976 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 1977 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 1978 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 1979 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 1980 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 1981 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 1982 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 1983 PORTB_HOTPLUG_INT_STATUS | \ 1984 PORTC_HOTPLUG_INT_STATUS | \ 1985 PORTD_HOTPLUG_INT_STATUS) 1986 1987 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 1988 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 1989 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 1990 PORTB_HOTPLUG_INT_STATUS | \ 1991 PORTC_HOTPLUG_INT_STATUS | \ 1992 PORTD_HOTPLUG_INT_STATUS) 1993 1994 /* SDVO and HDMI port control. 1995 * The same register may be used for SDVO or HDMI */ 1996 #define GEN3_SDVOB 0x61140 1997 #define GEN3_SDVOC 0x61160 1998 #define GEN4_HDMIB GEN3_SDVOB 1999 #define GEN4_HDMIC GEN3_SDVOC 2000 #define PCH_SDVOB 0xe1140 2001 #define PCH_HDMIB PCH_SDVOB 2002 #define PCH_HDMIC 0xe1150 2003 #define PCH_HDMID 0xe1160 2004 2005 /* Gen 3 SDVO bits: */ 2006 #define SDVO_ENABLE (1 << 31) 2007 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2008 #define SDVO_PIPE_SEL_MASK (1 << 30) 2009 #define SDVO_PIPE_B_SELECT (1 << 30) 2010 #define SDVO_STALL_SELECT (1 << 29) 2011 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2012 /** 2013 * 915G/GM SDVO pixel multiplier. 2014 * Programmed value is multiplier - 1, up to 5x. 2015 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2016 */ 2017 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2018 #define SDVO_PORT_MULTIPLY_SHIFT 23 2019 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2020 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2021 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2022 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2023 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2024 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2025 #define SDVO_DETECTED (1 << 2) 2026 /* Bits to be preserved when writing */ 2027 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2028 SDVO_INTERRUPT_ENABLE) 2029 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2030 2031 /* Gen 4 SDVO/HDMI bits: */ 2032 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2033 #define SDVO_ENCODING_SDVO (0 << 10) 2034 #define SDVO_ENCODING_HDMI (2 << 10) 2035 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2036 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2037 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2038 #define SDVO_AUDIO_ENABLE (1 << 6) 2039 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2040 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2041 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2042 2043 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2044 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2045 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2046 2047 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2048 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2049 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2050 2051 2052 /* DVO port control */ 2053 #define DVOA 0x61120 2054 #define DVOB 0x61140 2055 #define DVOC 0x61160 2056 #define DVO_ENABLE (1 << 31) 2057 #define DVO_PIPE_B_SELECT (1 << 30) 2058 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2059 #define DVO_PIPE_STALL (1 << 28) 2060 #define DVO_PIPE_STALL_TV (2 << 28) 2061 #define DVO_PIPE_STALL_MASK (3 << 28) 2062 #define DVO_USE_VGA_SYNC (1 << 15) 2063 #define DVO_DATA_ORDER_I740 (0 << 14) 2064 #define DVO_DATA_ORDER_FP (1 << 14) 2065 #define DVO_VSYNC_DISABLE (1 << 11) 2066 #define DVO_HSYNC_DISABLE (1 << 10) 2067 #define DVO_VSYNC_TRISTATE (1 << 9) 2068 #define DVO_HSYNC_TRISTATE (1 << 8) 2069 #define DVO_BORDER_ENABLE (1 << 7) 2070 #define DVO_DATA_ORDER_GBRG (1 << 6) 2071 #define DVO_DATA_ORDER_RGGB (0 << 6) 2072 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2073 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2074 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2075 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2076 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2077 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2078 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2079 #define DVO_PRESERVE_MASK (0x7<<24) 2080 #define DVOA_SRCDIM 0x61124 2081 #define DVOB_SRCDIM 0x61144 2082 #define DVOC_SRCDIM 0x61164 2083 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2084 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2085 2086 /* LVDS port control */ 2087 #define LVDS 0x61180 2088 /* 2089 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2090 * the DPLL semantics change when the LVDS is assigned to that pipe. 2091 */ 2092 #define LVDS_PORT_EN (1 << 31) 2093 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2094 #define LVDS_PIPEB_SELECT (1 << 30) 2095 #define LVDS_PIPE_MASK (1 << 30) 2096 #define LVDS_PIPE(pipe) ((pipe) << 30) 2097 /* LVDS dithering flag on 965/g4x platform */ 2098 #define LVDS_ENABLE_DITHER (1 << 25) 2099 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2100 #define LVDS_VSYNC_POLARITY (1 << 21) 2101 #define LVDS_HSYNC_POLARITY (1 << 20) 2102 2103 /* Enable border for unscaled (or aspect-scaled) display */ 2104 #define LVDS_BORDER_ENABLE (1 << 15) 2105 /* 2106 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2107 * pixel. 2108 */ 2109 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2110 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2111 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2112 /* 2113 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2114 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2115 * on. 2116 */ 2117 #define LVDS_A3_POWER_MASK (3 << 6) 2118 #define LVDS_A3_POWER_DOWN (0 << 6) 2119 #define LVDS_A3_POWER_UP (3 << 6) 2120 /* 2121 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2122 * is set. 2123 */ 2124 #define LVDS_CLKB_POWER_MASK (3 << 4) 2125 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2126 #define LVDS_CLKB_POWER_UP (3 << 4) 2127 /* 2128 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2129 * setting for whether we are in dual-channel mode. The B3 pair will 2130 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2131 */ 2132 #define LVDS_B0B3_POWER_MASK (3 << 2) 2133 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2134 #define LVDS_B0B3_POWER_UP (3 << 2) 2135 2136 /* Video Data Island Packet control */ 2137 #define VIDEO_DIP_DATA 0x61178 2138 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC 2139 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2140 * of the infoframe structure specified by CEA-861. */ 2141 #define VIDEO_DIP_DATA_SIZE 32 2142 #define VIDEO_DIP_VSC_DATA_SIZE 36 2143 #define VIDEO_DIP_CTL 0x61170 2144 /* Pre HSW: */ 2145 #define VIDEO_DIP_ENABLE (1 << 31) 2146 #define VIDEO_DIP_PORT_B (1 << 29) 2147 #define VIDEO_DIP_PORT_C (2 << 29) 2148 #define VIDEO_DIP_PORT_D (3 << 29) 2149 #define VIDEO_DIP_PORT_MASK (3 << 29) 2150 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 2151 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2152 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2153 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 2154 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2155 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2156 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2157 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2158 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2159 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2160 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2161 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2162 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2163 /* HSW and later: */ 2164 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2165 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2166 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2167 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2168 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2169 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2170 2171 /* Panel power sequencing */ 2172 #define PP_STATUS 0x61200 2173 #define PP_ON (1 << 31) 2174 /* 2175 * Indicates that all dependencies of the panel are on: 2176 * 2177 * - PLL enabled 2178 * - pipe enabled 2179 * - LVDS/DVOB/DVOC on 2180 */ 2181 #define PP_READY (1 << 30) 2182 #define PP_SEQUENCE_NONE (0 << 28) 2183 #define PP_SEQUENCE_POWER_UP (1 << 28) 2184 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 2185 #define PP_SEQUENCE_MASK (3 << 28) 2186 #define PP_SEQUENCE_SHIFT 28 2187 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 2188 #define PP_SEQUENCE_STATE_MASK 0x0000000f 2189 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 2190 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 2191 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 2192 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 2193 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 2194 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 2195 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 2196 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 2197 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 2198 #define PP_CONTROL 0x61204 2199 #define POWER_TARGET_ON (1 << 0) 2200 #define PP_ON_DELAYS 0x61208 2201 #define PP_OFF_DELAYS 0x6120c 2202 #define PP_DIVISOR 0x61210 2203 2204 /* Panel fitting */ 2205 #define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230) 2206 #define PFIT_ENABLE (1 << 31) 2207 #define PFIT_PIPE_MASK (3 << 29) 2208 #define PFIT_PIPE_SHIFT 29 2209 #define VERT_INTERP_DISABLE (0 << 10) 2210 #define VERT_INTERP_BILINEAR (1 << 10) 2211 #define VERT_INTERP_MASK (3 << 10) 2212 #define VERT_AUTO_SCALE (1 << 9) 2213 #define HORIZ_INTERP_DISABLE (0 << 6) 2214 #define HORIZ_INTERP_BILINEAR (1 << 6) 2215 #define HORIZ_INTERP_MASK (3 << 6) 2216 #define HORIZ_AUTO_SCALE (1 << 5) 2217 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2218 #define PFIT_FILTER_FUZZY (0 << 24) 2219 #define PFIT_SCALING_AUTO (0 << 26) 2220 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2221 #define PFIT_SCALING_PILLAR (2 << 26) 2222 #define PFIT_SCALING_LETTER (3 << 26) 2223 #define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234) 2224 /* Pre-965 */ 2225 #define PFIT_VERT_SCALE_SHIFT 20 2226 #define PFIT_VERT_SCALE_MASK 0xfff00000 2227 #define PFIT_HORIZ_SCALE_SHIFT 4 2228 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2229 /* 965+ */ 2230 #define PFIT_VERT_SCALE_SHIFT_965 16 2231 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2232 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2233 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2234 2235 #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) 2236 2237 /* Backlight control */ 2238 #define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */ 2239 #define BLM_PWM_ENABLE (1 << 31) 2240 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 2241 #define BLM_PIPE_SELECT (1 << 29) 2242 #define BLM_PIPE_SELECT_IVB (3 << 29) 2243 #define BLM_PIPE_A (0 << 29) 2244 #define BLM_PIPE_B (1 << 29) 2245 #define BLM_PIPE_C (2 << 29) /* ivb + */ 2246 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 2247 #define BLM_TRANSCODER_B BLM_PIPE_B 2248 #define BLM_TRANSCODER_C BLM_PIPE_C 2249 #define BLM_TRANSCODER_EDP (3 << 29) 2250 #define BLM_PIPE(pipe) ((pipe) << 29) 2251 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 2252 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 2253 #define BLM_PHASE_IN_ENABLE (1 << 25) 2254 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 2255 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 2256 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 2257 #define BLM_PHASE_IN_COUNT_SHIFT (8) 2258 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 2259 #define BLM_PHASE_IN_INCR_SHIFT (0) 2260 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 2261 #define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254) 2262 /* 2263 * This is the most significant 15 bits of the number of backlight cycles in a 2264 * complete cycle of the modulated backlight control. 2265 * 2266 * The actual value is this field multiplied by two. 2267 */ 2268 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 2269 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 2270 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 2271 /* 2272 * This is the number of cycles out of the backlight modulation cycle for which 2273 * the backlight is on. 2274 * 2275 * This field must be no greater than the number of cycles in the complete 2276 * backlight modulation cycle. 2277 */ 2278 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 2279 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 2280 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 2281 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 2282 2283 #define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260) 2284 2285 /* New registers for PCH-split platforms. Safe where new bits show up, the 2286 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 2287 #define BLC_PWM_CPU_CTL2 0x48250 2288 #define BLC_PWM_CPU_CTL 0x48254 2289 2290 #define HSW_BLC_PWM2_CTL 0x48350 2291 2292 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 2293 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 2294 #define BLC_PWM_PCH_CTL1 0xc8250 2295 #define BLM_PCH_PWM_ENABLE (1 << 31) 2296 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 2297 #define BLM_PCH_POLARITY (1 << 29) 2298 #define BLC_PWM_PCH_CTL2 0xc8254 2299 2300 #define UTIL_PIN_CTL 0x48400 2301 #define UTIL_PIN_ENABLE (1 << 31) 2302 2303 #define PCH_GTC_CTL 0xe7000 2304 #define PCH_GTC_ENABLE (1 << 31) 2305 2306 /* TV port control */ 2307 #define TV_CTL 0x68000 2308 /** Enables the TV encoder */ 2309 # define TV_ENC_ENABLE (1 << 31) 2310 /** Sources the TV encoder input from pipe B instead of A. */ 2311 # define TV_ENC_PIPEB_SELECT (1 << 30) 2312 /** Outputs composite video (DAC A only) */ 2313 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 2314 /** Outputs SVideo video (DAC B/C) */ 2315 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 2316 /** Outputs Component video (DAC A/B/C) */ 2317 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 2318 /** Outputs Composite and SVideo (DAC A/B/C) */ 2319 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 2320 # define TV_TRILEVEL_SYNC (1 << 21) 2321 /** Enables slow sync generation (945GM only) */ 2322 # define TV_SLOW_SYNC (1 << 20) 2323 /** Selects 4x oversampling for 480i and 576p */ 2324 # define TV_OVERSAMPLE_4X (0 << 18) 2325 /** Selects 2x oversampling for 720p and 1080i */ 2326 # define TV_OVERSAMPLE_2X (1 << 18) 2327 /** Selects no oversampling for 1080p */ 2328 # define TV_OVERSAMPLE_NONE (2 << 18) 2329 /** Selects 8x oversampling */ 2330 # define TV_OVERSAMPLE_8X (3 << 18) 2331 /** Selects progressive mode rather than interlaced */ 2332 # define TV_PROGRESSIVE (1 << 17) 2333 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 2334 # define TV_PAL_BURST (1 << 16) 2335 /** Field for setting delay of Y compared to C */ 2336 # define TV_YC_SKEW_MASK (7 << 12) 2337 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 2338 # define TV_ENC_SDP_FIX (1 << 11) 2339 /** 2340 * Enables a fix for the 915GM only. 2341 * 2342 * Not sure what it does. 2343 */ 2344 # define TV_ENC_C0_FIX (1 << 10) 2345 /** Bits that must be preserved by software */ 2346 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 2347 # define TV_FUSE_STATE_MASK (3 << 4) 2348 /** Read-only state that reports all features enabled */ 2349 # define TV_FUSE_STATE_ENABLED (0 << 4) 2350 /** Read-only state that reports that Macrovision is disabled in hardware*/ 2351 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 2352 /** Read-only state that reports that TV-out is disabled in hardware. */ 2353 # define TV_FUSE_STATE_DISABLED (2 << 4) 2354 /** Normal operation */ 2355 # define TV_TEST_MODE_NORMAL (0 << 0) 2356 /** Encoder test pattern 1 - combo pattern */ 2357 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 2358 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 2359 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 2360 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 2361 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 2362 /** Encoder test pattern 4 - random noise */ 2363 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 2364 /** Encoder test pattern 5 - linear color ramps */ 2365 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 2366 /** 2367 * This test mode forces the DACs to 50% of full output. 2368 * 2369 * This is used for load detection in combination with TVDAC_SENSE_MASK 2370 */ 2371 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 2372 # define TV_TEST_MODE_MASK (7 << 0) 2373 2374 #define TV_DAC 0x68004 2375 # define TV_DAC_SAVE 0x00ffff00 2376 /** 2377 * Reports that DAC state change logic has reported change (RO). 2378 * 2379 * This gets cleared when TV_DAC_STATE_EN is cleared 2380 */ 2381 # define TVDAC_STATE_CHG (1 << 31) 2382 # define TVDAC_SENSE_MASK (7 << 28) 2383 /** Reports that DAC A voltage is above the detect threshold */ 2384 # define TVDAC_A_SENSE (1 << 30) 2385 /** Reports that DAC B voltage is above the detect threshold */ 2386 # define TVDAC_B_SENSE (1 << 29) 2387 /** Reports that DAC C voltage is above the detect threshold */ 2388 # define TVDAC_C_SENSE (1 << 28) 2389 /** 2390 * Enables DAC state detection logic, for load-based TV detection. 2391 * 2392 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 2393 * to off, for load detection to work. 2394 */ 2395 # define TVDAC_STATE_CHG_EN (1 << 27) 2396 /** Sets the DAC A sense value to high */ 2397 # define TVDAC_A_SENSE_CTL (1 << 26) 2398 /** Sets the DAC B sense value to high */ 2399 # define TVDAC_B_SENSE_CTL (1 << 25) 2400 /** Sets the DAC C sense value to high */ 2401 # define TVDAC_C_SENSE_CTL (1 << 24) 2402 /** Overrides the ENC_ENABLE and DAC voltage levels */ 2403 # define DAC_CTL_OVERRIDE (1 << 7) 2404 /** Sets the slew rate. Must be preserved in software */ 2405 # define ENC_TVDAC_SLEW_FAST (1 << 6) 2406 # define DAC_A_1_3_V (0 << 4) 2407 # define DAC_A_1_1_V (1 << 4) 2408 # define DAC_A_0_7_V (2 << 4) 2409 # define DAC_A_MASK (3 << 4) 2410 # define DAC_B_1_3_V (0 << 2) 2411 # define DAC_B_1_1_V (1 << 2) 2412 # define DAC_B_0_7_V (2 << 2) 2413 # define DAC_B_MASK (3 << 2) 2414 # define DAC_C_1_3_V (0 << 0) 2415 # define DAC_C_1_1_V (1 << 0) 2416 # define DAC_C_0_7_V (2 << 0) 2417 # define DAC_C_MASK (3 << 0) 2418 2419 /** 2420 * CSC coefficients are stored in a floating point format with 9 bits of 2421 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 2422 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 2423 * -1 (0x3) being the only legal negative value. 2424 */ 2425 #define TV_CSC_Y 0x68010 2426 # define TV_RY_MASK 0x07ff0000 2427 # define TV_RY_SHIFT 16 2428 # define TV_GY_MASK 0x00000fff 2429 # define TV_GY_SHIFT 0 2430 2431 #define TV_CSC_Y2 0x68014 2432 # define TV_BY_MASK 0x07ff0000 2433 # define TV_BY_SHIFT 16 2434 /** 2435 * Y attenuation for component video. 2436 * 2437 * Stored in 1.9 fixed point. 2438 */ 2439 # define TV_AY_MASK 0x000003ff 2440 # define TV_AY_SHIFT 0 2441 2442 #define TV_CSC_U 0x68018 2443 # define TV_RU_MASK 0x07ff0000 2444 # define TV_RU_SHIFT 16 2445 # define TV_GU_MASK 0x000007ff 2446 # define TV_GU_SHIFT 0 2447 2448 #define TV_CSC_U2 0x6801c 2449 # define TV_BU_MASK 0x07ff0000 2450 # define TV_BU_SHIFT 16 2451 /** 2452 * U attenuation for component video. 2453 * 2454 * Stored in 1.9 fixed point. 2455 */ 2456 # define TV_AU_MASK 0x000003ff 2457 # define TV_AU_SHIFT 0 2458 2459 #define TV_CSC_V 0x68020 2460 # define TV_RV_MASK 0x0fff0000 2461 # define TV_RV_SHIFT 16 2462 # define TV_GV_MASK 0x000007ff 2463 # define TV_GV_SHIFT 0 2464 2465 #define TV_CSC_V2 0x68024 2466 # define TV_BV_MASK 0x07ff0000 2467 # define TV_BV_SHIFT 16 2468 /** 2469 * V attenuation for component video. 2470 * 2471 * Stored in 1.9 fixed point. 2472 */ 2473 # define TV_AV_MASK 0x000007ff 2474 # define TV_AV_SHIFT 0 2475 2476 #define TV_CLR_KNOBS 0x68028 2477 /** 2s-complement brightness adjustment */ 2478 # define TV_BRIGHTNESS_MASK 0xff000000 2479 # define TV_BRIGHTNESS_SHIFT 24 2480 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 2481 # define TV_CONTRAST_MASK 0x00ff0000 2482 # define TV_CONTRAST_SHIFT 16 2483 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 2484 # define TV_SATURATION_MASK 0x0000ff00 2485 # define TV_SATURATION_SHIFT 8 2486 /** Hue adjustment, as an integer phase angle in degrees */ 2487 # define TV_HUE_MASK 0x000000ff 2488 # define TV_HUE_SHIFT 0 2489 2490 #define TV_CLR_LEVEL 0x6802c 2491 /** Controls the DAC level for black */ 2492 # define TV_BLACK_LEVEL_MASK 0x01ff0000 2493 # define TV_BLACK_LEVEL_SHIFT 16 2494 /** Controls the DAC level for blanking */ 2495 # define TV_BLANK_LEVEL_MASK 0x000001ff 2496 # define TV_BLANK_LEVEL_SHIFT 0 2497 2498 #define TV_H_CTL_1 0x68030 2499 /** Number of pixels in the hsync. */ 2500 # define TV_HSYNC_END_MASK 0x1fff0000 2501 # define TV_HSYNC_END_SHIFT 16 2502 /** Total number of pixels minus one in the line (display and blanking). */ 2503 # define TV_HTOTAL_MASK 0x00001fff 2504 # define TV_HTOTAL_SHIFT 0 2505 2506 #define TV_H_CTL_2 0x68034 2507 /** Enables the colorburst (needed for non-component color) */ 2508 # define TV_BURST_ENA (1 << 31) 2509 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 2510 # define TV_HBURST_START_SHIFT 16 2511 # define TV_HBURST_START_MASK 0x1fff0000 2512 /** Length of the colorburst */ 2513 # define TV_HBURST_LEN_SHIFT 0 2514 # define TV_HBURST_LEN_MASK 0x0001fff 2515 2516 #define TV_H_CTL_3 0x68038 2517 /** End of hblank, measured in pixels minus one from start of hsync */ 2518 # define TV_HBLANK_END_SHIFT 16 2519 # define TV_HBLANK_END_MASK 0x1fff0000 2520 /** Start of hblank, measured in pixels minus one from start of hsync */ 2521 # define TV_HBLANK_START_SHIFT 0 2522 # define TV_HBLANK_START_MASK 0x0001fff 2523 2524 #define TV_V_CTL_1 0x6803c 2525 /** XXX */ 2526 # define TV_NBR_END_SHIFT 16 2527 # define TV_NBR_END_MASK 0x07ff0000 2528 /** XXX */ 2529 # define TV_VI_END_F1_SHIFT 8 2530 # define TV_VI_END_F1_MASK 0x00003f00 2531 /** XXX */ 2532 # define TV_VI_END_F2_SHIFT 0 2533 # define TV_VI_END_F2_MASK 0x0000003f 2534 2535 #define TV_V_CTL_2 0x68040 2536 /** Length of vsync, in half lines */ 2537 # define TV_VSYNC_LEN_MASK 0x07ff0000 2538 # define TV_VSYNC_LEN_SHIFT 16 2539 /** Offset of the start of vsync in field 1, measured in one less than the 2540 * number of half lines. 2541 */ 2542 # define TV_VSYNC_START_F1_MASK 0x00007f00 2543 # define TV_VSYNC_START_F1_SHIFT 8 2544 /** 2545 * Offset of the start of vsync in field 2, measured in one less than the 2546 * number of half lines. 2547 */ 2548 # define TV_VSYNC_START_F2_MASK 0x0000007f 2549 # define TV_VSYNC_START_F2_SHIFT 0 2550 2551 #define TV_V_CTL_3 0x68044 2552 /** Enables generation of the equalization signal */ 2553 # define TV_EQUAL_ENA (1 << 31) 2554 /** Length of vsync, in half lines */ 2555 # define TV_VEQ_LEN_MASK 0x007f0000 2556 # define TV_VEQ_LEN_SHIFT 16 2557 /** Offset of the start of equalization in field 1, measured in one less than 2558 * the number of half lines. 2559 */ 2560 # define TV_VEQ_START_F1_MASK 0x0007f00 2561 # define TV_VEQ_START_F1_SHIFT 8 2562 /** 2563 * Offset of the start of equalization in field 2, measured in one less than 2564 * the number of half lines. 2565 */ 2566 # define TV_VEQ_START_F2_MASK 0x000007f 2567 # define TV_VEQ_START_F2_SHIFT 0 2568 2569 #define TV_V_CTL_4 0x68048 2570 /** 2571 * Offset to start of vertical colorburst, measured in one less than the 2572 * number of lines from vertical start. 2573 */ 2574 # define TV_VBURST_START_F1_MASK 0x003f0000 2575 # define TV_VBURST_START_F1_SHIFT 16 2576 /** 2577 * Offset to the end of vertical colorburst, measured in one less than the 2578 * number of lines from the start of NBR. 2579 */ 2580 # define TV_VBURST_END_F1_MASK 0x000000ff 2581 # define TV_VBURST_END_F1_SHIFT 0 2582 2583 #define TV_V_CTL_5 0x6804c 2584 /** 2585 * Offset to start of vertical colorburst, measured in one less than the 2586 * number of lines from vertical start. 2587 */ 2588 # define TV_VBURST_START_F2_MASK 0x003f0000 2589 # define TV_VBURST_START_F2_SHIFT 16 2590 /** 2591 * Offset to the end of vertical colorburst, measured in one less than the 2592 * number of lines from the start of NBR. 2593 */ 2594 # define TV_VBURST_END_F2_MASK 0x000000ff 2595 # define TV_VBURST_END_F2_SHIFT 0 2596 2597 #define TV_V_CTL_6 0x68050 2598 /** 2599 * Offset to start of vertical colorburst, measured in one less than the 2600 * number of lines from vertical start. 2601 */ 2602 # define TV_VBURST_START_F3_MASK 0x003f0000 2603 # define TV_VBURST_START_F3_SHIFT 16 2604 /** 2605 * Offset to the end of vertical colorburst, measured in one less than the 2606 * number of lines from the start of NBR. 2607 */ 2608 # define TV_VBURST_END_F3_MASK 0x000000ff 2609 # define TV_VBURST_END_F3_SHIFT 0 2610 2611 #define TV_V_CTL_7 0x68054 2612 /** 2613 * Offset to start of vertical colorburst, measured in one less than the 2614 * number of lines from vertical start. 2615 */ 2616 # define TV_VBURST_START_F4_MASK 0x003f0000 2617 # define TV_VBURST_START_F4_SHIFT 16 2618 /** 2619 * Offset to the end of vertical colorburst, measured in one less than the 2620 * number of lines from the start of NBR. 2621 */ 2622 # define TV_VBURST_END_F4_MASK 0x000000ff 2623 # define TV_VBURST_END_F4_SHIFT 0 2624 2625 #define TV_SC_CTL_1 0x68060 2626 /** Turns on the first subcarrier phase generation DDA */ 2627 # define TV_SC_DDA1_EN (1 << 31) 2628 /** Turns on the first subcarrier phase generation DDA */ 2629 # define TV_SC_DDA2_EN (1 << 30) 2630 /** Turns on the first subcarrier phase generation DDA */ 2631 # define TV_SC_DDA3_EN (1 << 29) 2632 /** Sets the subcarrier DDA to reset frequency every other field */ 2633 # define TV_SC_RESET_EVERY_2 (0 << 24) 2634 /** Sets the subcarrier DDA to reset frequency every fourth field */ 2635 # define TV_SC_RESET_EVERY_4 (1 << 24) 2636 /** Sets the subcarrier DDA to reset frequency every eighth field */ 2637 # define TV_SC_RESET_EVERY_8 (2 << 24) 2638 /** Sets the subcarrier DDA to never reset the frequency */ 2639 # define TV_SC_RESET_NEVER (3 << 24) 2640 /** Sets the peak amplitude of the colorburst.*/ 2641 # define TV_BURST_LEVEL_MASK 0x00ff0000 2642 # define TV_BURST_LEVEL_SHIFT 16 2643 /** Sets the increment of the first subcarrier phase generation DDA */ 2644 # define TV_SCDDA1_INC_MASK 0x00000fff 2645 # define TV_SCDDA1_INC_SHIFT 0 2646 2647 #define TV_SC_CTL_2 0x68064 2648 /** Sets the rollover for the second subcarrier phase generation DDA */ 2649 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 2650 # define TV_SCDDA2_SIZE_SHIFT 16 2651 /** Sets the increent of the second subcarrier phase generation DDA */ 2652 # define TV_SCDDA2_INC_MASK 0x00007fff 2653 # define TV_SCDDA2_INC_SHIFT 0 2654 2655 #define TV_SC_CTL_3 0x68068 2656 /** Sets the rollover for the third subcarrier phase generation DDA */ 2657 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 2658 # define TV_SCDDA3_SIZE_SHIFT 16 2659 /** Sets the increent of the third subcarrier phase generation DDA */ 2660 # define TV_SCDDA3_INC_MASK 0x00007fff 2661 # define TV_SCDDA3_INC_SHIFT 0 2662 2663 #define TV_WIN_POS 0x68070 2664 /** X coordinate of the display from the start of horizontal active */ 2665 # define TV_XPOS_MASK 0x1fff0000 2666 # define TV_XPOS_SHIFT 16 2667 /** Y coordinate of the display from the start of vertical active (NBR) */ 2668 # define TV_YPOS_MASK 0x00000fff 2669 # define TV_YPOS_SHIFT 0 2670 2671 #define TV_WIN_SIZE 0x68074 2672 /** Horizontal size of the display window, measured in pixels*/ 2673 # define TV_XSIZE_MASK 0x1fff0000 2674 # define TV_XSIZE_SHIFT 16 2675 /** 2676 * Vertical size of the display window, measured in pixels. 2677 * 2678 * Must be even for interlaced modes. 2679 */ 2680 # define TV_YSIZE_MASK 0x00000fff 2681 # define TV_YSIZE_SHIFT 0 2682 2683 #define TV_FILTER_CTL_1 0x68080 2684 /** 2685 * Enables automatic scaling calculation. 2686 * 2687 * If set, the rest of the registers are ignored, and the calculated values can 2688 * be read back from the register. 2689 */ 2690 # define TV_AUTO_SCALE (1 << 31) 2691 /** 2692 * Disables the vertical filter. 2693 * 2694 * This is required on modes more than 1024 pixels wide */ 2695 # define TV_V_FILTER_BYPASS (1 << 29) 2696 /** Enables adaptive vertical filtering */ 2697 # define TV_VADAPT (1 << 28) 2698 # define TV_VADAPT_MODE_MASK (3 << 26) 2699 /** Selects the least adaptive vertical filtering mode */ 2700 # define TV_VADAPT_MODE_LEAST (0 << 26) 2701 /** Selects the moderately adaptive vertical filtering mode */ 2702 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2703 /** Selects the most adaptive vertical filtering mode */ 2704 # define TV_VADAPT_MODE_MOST (3 << 26) 2705 /** 2706 * Sets the horizontal scaling factor. 2707 * 2708 * This should be the fractional part of the horizontal scaling factor divided 2709 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2710 * 2711 * (src width - 1) / ((oversample * dest width) - 1) 2712 */ 2713 # define TV_HSCALE_FRAC_MASK 0x00003fff 2714 # define TV_HSCALE_FRAC_SHIFT 0 2715 2716 #define TV_FILTER_CTL_2 0x68084 2717 /** 2718 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2719 * 2720 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2721 */ 2722 # define TV_VSCALE_INT_MASK 0x00038000 2723 # define TV_VSCALE_INT_SHIFT 15 2724 /** 2725 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2726 * 2727 * \sa TV_VSCALE_INT_MASK 2728 */ 2729 # define TV_VSCALE_FRAC_MASK 0x00007fff 2730 # define TV_VSCALE_FRAC_SHIFT 0 2731 2732 #define TV_FILTER_CTL_3 0x68088 2733 /** 2734 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2735 * 2736 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2737 * 2738 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2739 */ 2740 # define TV_VSCALE_IP_INT_MASK 0x00038000 2741 # define TV_VSCALE_IP_INT_SHIFT 15 2742 /** 2743 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2744 * 2745 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2746 * 2747 * \sa TV_VSCALE_IP_INT_MASK 2748 */ 2749 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2750 # define TV_VSCALE_IP_FRAC_SHIFT 0 2751 2752 #define TV_CC_CONTROL 0x68090 2753 # define TV_CC_ENABLE (1 << 31) 2754 /** 2755 * Specifies which field to send the CC data in. 2756 * 2757 * CC data is usually sent in field 0. 2758 */ 2759 # define TV_CC_FID_MASK (1 << 27) 2760 # define TV_CC_FID_SHIFT 27 2761 /** Sets the horizontal position of the CC data. Usually 135. */ 2762 # define TV_CC_HOFF_MASK 0x03ff0000 2763 # define TV_CC_HOFF_SHIFT 16 2764 /** Sets the vertical position of the CC data. Usually 21 */ 2765 # define TV_CC_LINE_MASK 0x0000003f 2766 # define TV_CC_LINE_SHIFT 0 2767 2768 #define TV_CC_DATA 0x68094 2769 # define TV_CC_RDY (1 << 31) 2770 /** Second word of CC data to be transmitted. */ 2771 # define TV_CC_DATA_2_MASK 0x007f0000 2772 # define TV_CC_DATA_2_SHIFT 16 2773 /** First word of CC data to be transmitted. */ 2774 # define TV_CC_DATA_1_MASK 0x0000007f 2775 # define TV_CC_DATA_1_SHIFT 0 2776 2777 #define TV_H_LUMA_0 0x68100 2778 #define TV_H_LUMA_59 0x681ec 2779 #define TV_H_CHROMA_0 0x68200 2780 #define TV_H_CHROMA_59 0x682ec 2781 #define TV_V_LUMA_0 0x68300 2782 #define TV_V_LUMA_42 0x683a8 2783 #define TV_V_CHROMA_0 0x68400 2784 #define TV_V_CHROMA_42 0x684a8 2785 2786 /* Display Port */ 2787 #define DP_A 0x64000 /* eDP */ 2788 #define DP_B 0x64100 2789 #define DP_C 0x64200 2790 #define DP_D 0x64300 2791 2792 #define DP_PORT_EN (1 << 31) 2793 #define DP_PIPEB_SELECT (1 << 30) 2794 #define DP_PIPE_MASK (1 << 30) 2795 2796 /* Link training mode - select a suitable mode for each stage */ 2797 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2798 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2799 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2800 #define DP_LINK_TRAIN_OFF (3 << 28) 2801 #define DP_LINK_TRAIN_MASK (3 << 28) 2802 #define DP_LINK_TRAIN_SHIFT 28 2803 2804 /* CPT Link training mode */ 2805 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2806 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2807 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2808 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2809 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2810 #define DP_LINK_TRAIN_SHIFT_CPT 8 2811 2812 /* Signal voltages. These are mostly controlled by the other end */ 2813 #define DP_VOLTAGE_0_4 (0 << 25) 2814 #define DP_VOLTAGE_0_6 (1 << 25) 2815 #define DP_VOLTAGE_0_8 (2 << 25) 2816 #define DP_VOLTAGE_1_2 (3 << 25) 2817 #define DP_VOLTAGE_MASK (7 << 25) 2818 #define DP_VOLTAGE_SHIFT 25 2819 2820 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2821 * they want 2822 */ 2823 #define DP_PRE_EMPHASIS_0 (0 << 22) 2824 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2825 #define DP_PRE_EMPHASIS_6 (2 << 22) 2826 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2827 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2828 #define DP_PRE_EMPHASIS_SHIFT 22 2829 2830 /* How many wires to use. I guess 3 was too hard */ 2831 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 2832 #define DP_PORT_WIDTH_MASK (7 << 19) 2833 2834 /* Mystic DPCD version 1.1 special mode */ 2835 #define DP_ENHANCED_FRAMING (1 << 18) 2836 2837 /* eDP */ 2838 #define DP_PLL_FREQ_270MHZ (0 << 16) 2839 #define DP_PLL_FREQ_160MHZ (1 << 16) 2840 #define DP_PLL_FREQ_MASK (3 << 16) 2841 2842 /** locked once port is enabled */ 2843 #define DP_PORT_REVERSAL (1 << 15) 2844 2845 /* eDP */ 2846 #define DP_PLL_ENABLE (1 << 14) 2847 2848 /** sends the clock on lane 15 of the PEG for debug */ 2849 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2850 2851 #define DP_SCRAMBLING_DISABLE (1 << 12) 2852 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2853 2854 /** limit RGB values to avoid confusing TVs */ 2855 #define DP_COLOR_RANGE_16_235 (1 << 8) 2856 2857 /** Turn on the audio link */ 2858 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2859 2860 /** vs and hs sync polarity */ 2861 #define DP_SYNC_VS_HIGH (1 << 4) 2862 #define DP_SYNC_HS_HIGH (1 << 3) 2863 2864 /** A fantasy */ 2865 #define DP_DETECTED (1 << 2) 2866 2867 /** The aux channel provides a way to talk to the 2868 * signal sink for DDC etc. Max packet size supported 2869 * is 20 bytes in each direction, hence the 5 fixed 2870 * data registers 2871 */ 2872 #define DPA_AUX_CH_CTL 0x64010 2873 #define DPA_AUX_CH_DATA1 0x64014 2874 #define DPA_AUX_CH_DATA2 0x64018 2875 #define DPA_AUX_CH_DATA3 0x6401c 2876 #define DPA_AUX_CH_DATA4 0x64020 2877 #define DPA_AUX_CH_DATA5 0x64024 2878 2879 #define DPB_AUX_CH_CTL 0x64110 2880 #define DPB_AUX_CH_DATA1 0x64114 2881 #define DPB_AUX_CH_DATA2 0x64118 2882 #define DPB_AUX_CH_DATA3 0x6411c 2883 #define DPB_AUX_CH_DATA4 0x64120 2884 #define DPB_AUX_CH_DATA5 0x64124 2885 2886 #define DPC_AUX_CH_CTL 0x64210 2887 #define DPC_AUX_CH_DATA1 0x64214 2888 #define DPC_AUX_CH_DATA2 0x64218 2889 #define DPC_AUX_CH_DATA3 0x6421c 2890 #define DPC_AUX_CH_DATA4 0x64220 2891 #define DPC_AUX_CH_DATA5 0x64224 2892 2893 #define DPD_AUX_CH_CTL 0x64310 2894 #define DPD_AUX_CH_DATA1 0x64314 2895 #define DPD_AUX_CH_DATA2 0x64318 2896 #define DPD_AUX_CH_DATA3 0x6431c 2897 #define DPD_AUX_CH_DATA4 0x64320 2898 #define DPD_AUX_CH_DATA5 0x64324 2899 2900 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2901 #define DP_AUX_CH_CTL_DONE (1 << 30) 2902 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2903 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2904 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2905 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2906 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2907 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2908 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2909 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2910 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2911 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2912 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2913 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2914 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2915 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2916 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2917 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2918 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2919 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2920 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2921 2922 /* 2923 * Computing GMCH M and N values for the Display Port link 2924 * 2925 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2926 * 2927 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2928 * 2929 * The GMCH value is used internally 2930 * 2931 * bytes_per_pixel is the number of bytes coming out of the plane, 2932 * which is after the LUTs, so we want the bytes for our color format. 2933 * For our current usage, this is always 3, one byte for R, G and B. 2934 */ 2935 #define _PIPEA_DATA_M_G4X 0x70050 2936 #define _PIPEB_DATA_M_G4X 0x71050 2937 2938 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2939 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2940 #define TU_SIZE_SHIFT 25 2941 #define TU_SIZE_MASK (0x3f << 25) 2942 2943 #define DATA_LINK_M_N_MASK (0xffffff) 2944 #define DATA_LINK_N_MAX (0x800000) 2945 2946 #define _PIPEA_DATA_N_G4X 0x70054 2947 #define _PIPEB_DATA_N_G4X 0x71054 2948 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2949 2950 /* 2951 * Computing Link M and N values for the Display Port link 2952 * 2953 * Link M / N = pixel_clock / ls_clk 2954 * 2955 * (the DP spec calls pixel_clock the 'strm_clk') 2956 * 2957 * The Link value is transmitted in the Main Stream 2958 * Attributes and VB-ID. 2959 */ 2960 2961 #define _PIPEA_LINK_M_G4X 0x70060 2962 #define _PIPEB_LINK_M_G4X 0x71060 2963 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2964 2965 #define _PIPEA_LINK_N_G4X 0x70064 2966 #define _PIPEB_LINK_N_G4X 0x71064 2967 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2968 2969 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 2970 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 2971 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 2972 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 2973 2974 /* Display & cursor control */ 2975 2976 /* Pipe A */ 2977 #define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000) 2978 #define DSL_LINEMASK_GEN2 0x00000fff 2979 #define DSL_LINEMASK_GEN3 0x00001fff 2980 #define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) 2981 #define PIPECONF_ENABLE (1<<31) 2982 #define PIPECONF_DISABLE 0 2983 #define PIPECONF_DOUBLE_WIDE (1<<30) 2984 #define I965_PIPECONF_ACTIVE (1<<30) 2985 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 2986 #define PIPECONF_SINGLE_WIDE 0 2987 #define PIPECONF_PIPE_UNLOCKED 0 2988 #define PIPECONF_PIPE_LOCKED (1<<25) 2989 #define PIPECONF_PALETTE 0 2990 #define PIPECONF_GAMMA (1<<24) 2991 #define PIPECONF_FORCE_BORDER (1<<25) 2992 #define PIPECONF_INTERLACE_MASK (7 << 21) 2993 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 2994 /* Note that pre-gen3 does not support interlaced display directly. Panel 2995 * fitting must be disabled on pre-ilk for interlaced. */ 2996 #define PIPECONF_PROGRESSIVE (0 << 21) 2997 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 2998 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 2999 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 3000 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 3001 /* Ironlake and later have a complete new set of values for interlaced. PFIT 3002 * means panel fitter required, PF means progressive fetch, DBL means power 3003 * saving pixel doubling. */ 3004 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 3005 #define PIPECONF_INTERLACED_ILK (3 << 21) 3006 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 3007 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 3008 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 3009 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 3010 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 3011 #define PIPECONF_BPC_MASK (0x7 << 5) 3012 #define PIPECONF_8BPC (0<<5) 3013 #define PIPECONF_10BPC (1<<5) 3014 #define PIPECONF_6BPC (2<<5) 3015 #define PIPECONF_12BPC (3<<5) 3016 #define PIPECONF_DITHER_EN (1<<4) 3017 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 3018 #define PIPECONF_DITHER_TYPE_SP (0<<2) 3019 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 3020 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 3021 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 3022 #define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024) 3023 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 3024 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) 3025 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 3026 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 3027 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 3028 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 3029 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 3030 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 3031 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 3032 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 3033 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 3034 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 3035 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 3036 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 3037 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 3038 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 3039 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 3040 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 3041 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 3042 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) 3043 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14) 3044 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 3045 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 3046 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 3047 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) 3048 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 3049 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 3050 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 3051 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 3052 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3053 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 3054 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 3055 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 3056 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 3057 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 3058 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 3059 3060 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 3061 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) 3062 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 3063 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 3064 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 3065 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 3066 3067 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) 3068 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 3069 #define PIPEB_HLINE_INT_EN (1<<28) 3070 #define PIPEB_VBLANK_INT_EN (1<<27) 3071 #define SPRITED_FLIPDONE_INT_EN (1<<26) 3072 #define SPRITEC_FLIPDONE_INT_EN (1<<25) 3073 #define PLANEB_FLIPDONE_INT_EN (1<<24) 3074 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 3075 #define PIPEA_HLINE_INT_EN (1<<20) 3076 #define PIPEA_VBLANK_INT_EN (1<<19) 3077 #define SPRITEB_FLIPDONE_INT_EN (1<<18) 3078 #define SPRITEA_FLIPDONE_INT_EN (1<<17) 3079 #define PLANEA_FLIPDONE_INT_EN (1<<16) 3080 3081 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */ 3082 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 3083 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 3084 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 3085 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 3086 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 3087 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 3088 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 3089 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 3090 #define DPINVGTT_EN_MASK 0xff0000 3091 #define CURSORB_INVALID_GTT_STATUS (1<<7) 3092 #define CURSORA_INVALID_GTT_STATUS (1<<6) 3093 #define SPRITED_INVALID_GTT_STATUS (1<<5) 3094 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 3095 #define PLANEB_INVALID_GTT_STATUS (1<<3) 3096 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 3097 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 3098 #define PLANEA_INVALID_GTT_STATUS (1<<0) 3099 #define DPINVGTT_STATUS_MASK 0xff 3100 3101 #define DSPARB 0x70030 3102 #define DSPARB_CSTART_MASK (0x7f << 7) 3103 #define DSPARB_CSTART_SHIFT 7 3104 #define DSPARB_BSTART_MASK (0x7f) 3105 #define DSPARB_BSTART_SHIFT 0 3106 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3107 #define DSPARB_AEND_SHIFT 0 3108 3109 #define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034) 3110 #define DSPFW_SR_SHIFT 23 3111 #define DSPFW_SR_MASK (0x1ff<<23) 3112 #define DSPFW_CURSORB_SHIFT 16 3113 #define DSPFW_CURSORB_MASK (0x3f<<16) 3114 #define DSPFW_PLANEB_SHIFT 8 3115 #define DSPFW_PLANEB_MASK (0x7f<<8) 3116 #define DSPFW_PLANEA_MASK (0x7f) 3117 #define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038) 3118 #define DSPFW_CURSORA_MASK 0x00003f00 3119 #define DSPFW_CURSORA_SHIFT 8 3120 #define DSPFW_PLANEC_MASK (0x7f) 3121 #define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c) 3122 #define DSPFW_HPLL_SR_EN (1<<31) 3123 #define DSPFW_CURSOR_SR_SHIFT 24 3124 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 3125 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 3126 #define DSPFW_HPLL_CURSOR_SHIFT 16 3127 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 3128 #define DSPFW_HPLL_SR_MASK (0x1ff) 3129 #define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070) 3130 #define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c) 3131 3132 /* drain latency register values*/ 3133 #define DRAIN_LATENCY_PRECISION_32 32 3134 #define DRAIN_LATENCY_PRECISION_16 16 3135 #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) 3136 #define DDL_CURSORA_PRECISION_32 (1<<31) 3137 #define DDL_CURSORA_PRECISION_16 (0<<31) 3138 #define DDL_CURSORA_SHIFT 24 3139 #define DDL_PLANEA_PRECISION_32 (1<<7) 3140 #define DDL_PLANEA_PRECISION_16 (0<<7) 3141 #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) 3142 #define DDL_CURSORB_PRECISION_32 (1<<31) 3143 #define DDL_CURSORB_PRECISION_16 (0<<31) 3144 #define DDL_CURSORB_SHIFT 24 3145 #define DDL_PLANEB_PRECISION_32 (1<<7) 3146 #define DDL_PLANEB_PRECISION_16 (0<<7) 3147 3148 /* FIFO watermark sizes etc */ 3149 #define G4X_FIFO_LINE_SIZE 64 3150 #define I915_FIFO_LINE_SIZE 64 3151 #define I830_FIFO_LINE_SIZE 32 3152 3153 #define VALLEYVIEW_FIFO_SIZE 255 3154 #define G4X_FIFO_SIZE 127 3155 #define I965_FIFO_SIZE 512 3156 #define I945_FIFO_SIZE 127 3157 #define I915_FIFO_SIZE 95 3158 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 3159 #define I830_FIFO_SIZE 95 3160 3161 #define VALLEYVIEW_MAX_WM 0xff 3162 #define G4X_MAX_WM 0x3f 3163 #define I915_MAX_WM 0x3f 3164 3165 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 3166 #define PINEVIEW_FIFO_LINE_SIZE 64 3167 #define PINEVIEW_MAX_WM 0x1ff 3168 #define PINEVIEW_DFT_WM 0x3f 3169 #define PINEVIEW_DFT_HPLLOFF_WM 0 3170 #define PINEVIEW_GUARD_WM 10 3171 #define PINEVIEW_CURSOR_FIFO 64 3172 #define PINEVIEW_CURSOR_MAX_WM 0x3f 3173 #define PINEVIEW_CURSOR_DFT_WM 0 3174 #define PINEVIEW_CURSOR_GUARD_WM 5 3175 3176 #define VALLEYVIEW_CURSOR_MAX_WM 64 3177 #define I965_CURSOR_FIFO 64 3178 #define I965_CURSOR_MAX_WM 32 3179 #define I965_CURSOR_DFT_WM 8 3180 3181 /* define the Watermark register on Ironlake */ 3182 #define WM0_PIPEA_ILK 0x45100 3183 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 3184 #define WM0_PIPE_PLANE_SHIFT 16 3185 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 3186 #define WM0_PIPE_SPRITE_SHIFT 8 3187 #define WM0_PIPE_CURSOR_MASK (0x1f) 3188 3189 #define WM0_PIPEB_ILK 0x45104 3190 #define WM0_PIPEC_IVB 0x45200 3191 #define WM1_LP_ILK 0x45108 3192 #define WM1_LP_SR_EN (1<<31) 3193 #define WM1_LP_LATENCY_SHIFT 24 3194 #define WM1_LP_LATENCY_MASK (0x7f<<24) 3195 #define WM1_LP_FBC_MASK (0xf<<20) 3196 #define WM1_LP_FBC_SHIFT 20 3197 #define WM1_LP_SR_MASK (0x1ff<<8) 3198 #define WM1_LP_SR_SHIFT 8 3199 #define WM1_LP_CURSOR_MASK (0x3f) 3200 #define WM2_LP_ILK 0x4510c 3201 #define WM2_LP_EN (1<<31) 3202 #define WM3_LP_ILK 0x45110 3203 #define WM3_LP_EN (1<<31) 3204 #define WM1S_LP_ILK 0x45120 3205 #define WM2S_LP_IVB 0x45124 3206 #define WM3S_LP_IVB 0x45128 3207 #define WM1S_LP_EN (1<<31) 3208 3209 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 3210 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 3211 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 3212 3213 /* Memory latency timer register */ 3214 #define MLTR_ILK 0x11222 3215 #define MLTR_WM1_SHIFT 0 3216 #define MLTR_WM2_SHIFT 8 3217 /* the unit of memory self-refresh latency time is 0.5us */ 3218 #define ILK_SRLT_MASK 0x3f 3219 3220 /* define the fifo size on Ironlake */ 3221 #define ILK_DISPLAY_FIFO 128 3222 #define ILK_DISPLAY_MAXWM 64 3223 #define ILK_DISPLAY_DFTWM 8 3224 #define ILK_CURSOR_FIFO 32 3225 #define ILK_CURSOR_MAXWM 16 3226 #define ILK_CURSOR_DFTWM 8 3227 3228 #define ILK_DISPLAY_SR_FIFO 512 3229 #define ILK_DISPLAY_MAX_SRWM 0x1ff 3230 #define ILK_DISPLAY_DFT_SRWM 0x3f 3231 #define ILK_CURSOR_SR_FIFO 64 3232 #define ILK_CURSOR_MAX_SRWM 0x3f 3233 #define ILK_CURSOR_DFT_SRWM 8 3234 3235 #define ILK_FIFO_LINE_SIZE 64 3236 3237 /* define the WM info on Sandybridge */ 3238 #define SNB_DISPLAY_FIFO 128 3239 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 3240 #define SNB_DISPLAY_DFTWM 8 3241 #define SNB_CURSOR_FIFO 32 3242 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 3243 #define SNB_CURSOR_DFTWM 8 3244 3245 #define SNB_DISPLAY_SR_FIFO 512 3246 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 3247 #define SNB_DISPLAY_DFT_SRWM 0x3f 3248 #define SNB_CURSOR_SR_FIFO 64 3249 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 3250 #define SNB_CURSOR_DFT_SRWM 8 3251 3252 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 3253 3254 #define SNB_FIFO_LINE_SIZE 64 3255 3256 3257 /* the address where we get all kinds of latency value */ 3258 #define SSKPD 0x5d10 3259 #define SSKPD_WM_MASK 0x3f 3260 #define SSKPD_WM0_SHIFT 0 3261 #define SSKPD_WM1_SHIFT 8 3262 #define SSKPD_WM2_SHIFT 16 3263 #define SSKPD_WM3_SHIFT 24 3264 3265 /* 3266 * The two pipe frame counter registers are not synchronized, so 3267 * reading a stable value is somewhat tricky. The following code 3268 * should work: 3269 * 3270 * do { 3271 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 3272 * PIPE_FRAME_HIGH_SHIFT; 3273 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 3274 * PIPE_FRAME_LOW_SHIFT); 3275 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 3276 * PIPE_FRAME_HIGH_SHIFT); 3277 * } while (high1 != high2); 3278 * frame = (high1 << 8) | low1; 3279 */ 3280 #define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040) 3281 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 3282 #define PIPE_FRAME_HIGH_SHIFT 0 3283 #define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044) 3284 #define PIPE_FRAME_LOW_MASK 0xff000000 3285 #define PIPE_FRAME_LOW_SHIFT 24 3286 #define PIPE_PIXEL_MASK 0x00ffffff 3287 #define PIPE_PIXEL_SHIFT 0 3288 /* GM45+ just has to be different */ 3289 #define _PIPEA_FRMCOUNT_GM45 0x70040 3290 #define _PIPEA_FLIPCOUNT_GM45 0x70044 3291 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 3292 3293 /* Cursor A & B regs */ 3294 #define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080) 3295 /* Old style CUR*CNTR flags (desktop 8xx) */ 3296 #define CURSOR_ENABLE 0x80000000 3297 #define CURSOR_GAMMA_ENABLE 0x40000000 3298 #define CURSOR_STRIDE_MASK 0x30000000 3299 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 3300 #define CURSOR_FORMAT_SHIFT 24 3301 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 3302 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 3303 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 3304 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 3305 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 3306 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 3307 /* New style CUR*CNTR flags */ 3308 #define CURSOR_MODE 0x27 3309 #define CURSOR_MODE_DISABLE 0x00 3310 #define CURSOR_MODE_64_32B_AX 0x07 3311 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 3312 #define MCURSOR_PIPE_SELECT (1 << 28) 3313 #define MCURSOR_PIPE_A 0x00 3314 #define MCURSOR_PIPE_B (1 << 28) 3315 #define MCURSOR_GAMMA_ENABLE (1 << 26) 3316 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 3317 #define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084) 3318 #define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088) 3319 #define CURSOR_POS_MASK 0x007FF 3320 #define CURSOR_POS_SIGN 0x8000 3321 #define CURSOR_X_SHIFT 0 3322 #define CURSOR_Y_SHIFT 16 3323 #define CURSIZE 0x700a0 3324 #define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0) 3325 #define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4) 3326 #define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8) 3327 3328 #define _CURBCNTR_IVB 0x71080 3329 #define _CURBBASE_IVB 0x71084 3330 #define _CURBPOS_IVB 0x71088 3331 3332 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) 3333 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) 3334 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) 3335 3336 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) 3337 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) 3338 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 3339 3340 /* Display A control */ 3341 #define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180) 3342 #define DISPLAY_PLANE_ENABLE (1<<31) 3343 #define DISPLAY_PLANE_DISABLE 0 3344 #define DISPPLANE_GAMMA_ENABLE (1<<30) 3345 #define DISPPLANE_GAMMA_DISABLE 0 3346 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 3347 #define DISPPLANE_YUV422 (0x0<<26) 3348 #define DISPPLANE_8BPP (0x2<<26) 3349 #define DISPPLANE_BGRA555 (0x3<<26) 3350 #define DISPPLANE_BGRX555 (0x4<<26) 3351 #define DISPPLANE_BGRX565 (0x5<<26) 3352 #define DISPPLANE_BGRX888 (0x6<<26) 3353 #define DISPPLANE_BGRA888 (0x7<<26) 3354 #define DISPPLANE_RGBX101010 (0x8<<26) 3355 #define DISPPLANE_RGBA101010 (0x9<<26) 3356 #define DISPPLANE_BGRX101010 (0xa<<26) 3357 #define DISPPLANE_RGBX161616 (0xc<<26) 3358 #define DISPPLANE_RGBX888 (0xe<<26) 3359 #define DISPPLANE_RGBA888 (0xf<<26) 3360 #define DISPPLANE_STEREO_ENABLE (1<<25) 3361 #define DISPPLANE_STEREO_DISABLE 0 3362 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 3363 #define DISPPLANE_SEL_PIPE_SHIFT 24 3364 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 3365 #define DISPPLANE_SEL_PIPE_A 0 3366 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 3367 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 3368 #define DISPPLANE_SRC_KEY_DISABLE 0 3369 #define DISPPLANE_LINE_DOUBLE (1<<20) 3370 #define DISPPLANE_NO_LINE_DOUBLE 0 3371 #define DISPPLANE_STEREO_POLARITY_FIRST 0 3372 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 3373 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 3374 #define DISPPLANE_TILED (1<<10) 3375 #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) 3376 #define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) 3377 #define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ 3378 #define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) 3379 #define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ 3380 #define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ 3381 #define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */ 3382 #define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC) 3383 3384 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 3385 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 3386 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 3387 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 3388 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 3389 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 3390 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 3391 #define DSPLINOFF(plane) DSPADDR(plane) 3392 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) 3393 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) 3394 3395 /* Display/Sprite base address macros */ 3396 #define DISP_BASEADDR_MASK (0xfffff000) 3397 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 3398 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 3399 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ 3400 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) 3401 3402 /* VBIOS flags */ 3403 #define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) 3404 #define SWF01 (dev_priv->info->display_mmio_offset + 0x71414) 3405 #define SWF02 (dev_priv->info->display_mmio_offset + 0x71418) 3406 #define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c) 3407 #define SWF04 (dev_priv->info->display_mmio_offset + 0x71420) 3408 #define SWF05 (dev_priv->info->display_mmio_offset + 0x71424) 3409 #define SWF06 (dev_priv->info->display_mmio_offset + 0x71428) 3410 #define SWF10 (dev_priv->info->display_mmio_offset + 0x70410) 3411 #define SWF11 (dev_priv->info->display_mmio_offset + 0x70414) 3412 #define SWF14 (dev_priv->info->display_mmio_offset + 0x71420) 3413 #define SWF30 (dev_priv->info->display_mmio_offset + 0x72414) 3414 #define SWF31 (dev_priv->info->display_mmio_offset + 0x72418) 3415 #define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c) 3416 3417 /* Pipe B */ 3418 #define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) 3419 #define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) 3420 #define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) 3421 #define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040) 3422 #define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044) 3423 #define _PIPEB_FRMCOUNT_GM45 0x71040 3424 #define _PIPEB_FLIPCOUNT_GM45 0x71044 3425 3426 3427 /* Display B control */ 3428 #define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180) 3429 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 3430 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 3431 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 3432 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 3433 #define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184) 3434 #define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188) 3435 #define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C) 3436 #define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190) 3437 #define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C) 3438 #define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4) 3439 #define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4) 3440 #define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC) 3441 3442 /* Sprite A control */ 3443 #define _DVSACNTR 0x72180 3444 #define DVS_ENABLE (1<<31) 3445 #define DVS_GAMMA_ENABLE (1<<30) 3446 #define DVS_PIXFORMAT_MASK (3<<25) 3447 #define DVS_FORMAT_YUV422 (0<<25) 3448 #define DVS_FORMAT_RGBX101010 (1<<25) 3449 #define DVS_FORMAT_RGBX888 (2<<25) 3450 #define DVS_FORMAT_RGBX161616 (3<<25) 3451 #define DVS_PIPE_CSC_ENABLE (1<<24) 3452 #define DVS_SOURCE_KEY (1<<22) 3453 #define DVS_RGB_ORDER_XBGR (1<<20) 3454 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 3455 #define DVS_YUV_ORDER_YUYV (0<<16) 3456 #define DVS_YUV_ORDER_UYVY (1<<16) 3457 #define DVS_YUV_ORDER_YVYU (2<<16) 3458 #define DVS_YUV_ORDER_VYUY (3<<16) 3459 #define DVS_DEST_KEY (1<<2) 3460 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 3461 #define DVS_TILED (1<<10) 3462 #define _DVSALINOFF 0x72184 3463 #define _DVSASTRIDE 0x72188 3464 #define _DVSAPOS 0x7218c 3465 #define _DVSASIZE 0x72190 3466 #define _DVSAKEYVAL 0x72194 3467 #define _DVSAKEYMSK 0x72198 3468 #define _DVSASURF 0x7219c 3469 #define _DVSAKEYMAXVAL 0x721a0 3470 #define _DVSATILEOFF 0x721a4 3471 #define _DVSASURFLIVE 0x721ac 3472 #define _DVSASCALE 0x72204 3473 #define DVS_SCALE_ENABLE (1<<31) 3474 #define DVS_FILTER_MASK (3<<29) 3475 #define DVS_FILTER_MEDIUM (0<<29) 3476 #define DVS_FILTER_ENHANCING (1<<29) 3477 #define DVS_FILTER_SOFTENING (2<<29) 3478 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 3479 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 3480 #define _DVSAGAMC 0x72300 3481 3482 #define _DVSBCNTR 0x73180 3483 #define _DVSBLINOFF 0x73184 3484 #define _DVSBSTRIDE 0x73188 3485 #define _DVSBPOS 0x7318c 3486 #define _DVSBSIZE 0x73190 3487 #define _DVSBKEYVAL 0x73194 3488 #define _DVSBKEYMSK 0x73198 3489 #define _DVSBSURF 0x7319c 3490 #define _DVSBKEYMAXVAL 0x731a0 3491 #define _DVSBTILEOFF 0x731a4 3492 #define _DVSBSURFLIVE 0x731ac 3493 #define _DVSBSCALE 0x73204 3494 #define _DVSBGAMC 0x73300 3495 3496 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 3497 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 3498 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 3499 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 3500 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 3501 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 3502 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 3503 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 3504 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 3505 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 3506 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 3507 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 3508 3509 #define _SPRA_CTL 0x70280 3510 #define SPRITE_ENABLE (1<<31) 3511 #define SPRITE_GAMMA_ENABLE (1<<30) 3512 #define SPRITE_PIXFORMAT_MASK (7<<25) 3513 #define SPRITE_FORMAT_YUV422 (0<<25) 3514 #define SPRITE_FORMAT_RGBX101010 (1<<25) 3515 #define SPRITE_FORMAT_RGBX888 (2<<25) 3516 #define SPRITE_FORMAT_RGBX161616 (3<<25) 3517 #define SPRITE_FORMAT_YUV444 (4<<25) 3518 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 3519 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 3520 #define SPRITE_SOURCE_KEY (1<<22) 3521 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 3522 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 3523 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 3524 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 3525 #define SPRITE_YUV_ORDER_YUYV (0<<16) 3526 #define SPRITE_YUV_ORDER_UYVY (1<<16) 3527 #define SPRITE_YUV_ORDER_YVYU (2<<16) 3528 #define SPRITE_YUV_ORDER_VYUY (3<<16) 3529 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 3530 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 3531 #define SPRITE_TILED (1<<10) 3532 #define SPRITE_DEST_KEY (1<<2) 3533 #define _SPRA_LINOFF 0x70284 3534 #define _SPRA_STRIDE 0x70288 3535 #define _SPRA_POS 0x7028c 3536 #define _SPRA_SIZE 0x70290 3537 #define _SPRA_KEYVAL 0x70294 3538 #define _SPRA_KEYMSK 0x70298 3539 #define _SPRA_SURF 0x7029c 3540 #define _SPRA_KEYMAX 0x702a0 3541 #define _SPRA_TILEOFF 0x702a4 3542 #define _SPRA_OFFSET 0x702a4 3543 #define _SPRA_SURFLIVE 0x702ac 3544 #define _SPRA_SCALE 0x70304 3545 #define SPRITE_SCALE_ENABLE (1<<31) 3546 #define SPRITE_FILTER_MASK (3<<29) 3547 #define SPRITE_FILTER_MEDIUM (0<<29) 3548 #define SPRITE_FILTER_ENHANCING (1<<29) 3549 #define SPRITE_FILTER_SOFTENING (2<<29) 3550 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 3551 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 3552 #define _SPRA_GAMC 0x70400 3553 3554 #define _SPRB_CTL 0x71280 3555 #define _SPRB_LINOFF 0x71284 3556 #define _SPRB_STRIDE 0x71288 3557 #define _SPRB_POS 0x7128c 3558 #define _SPRB_SIZE 0x71290 3559 #define _SPRB_KEYVAL 0x71294 3560 #define _SPRB_KEYMSK 0x71298 3561 #define _SPRB_SURF 0x7129c 3562 #define _SPRB_KEYMAX 0x712a0 3563 #define _SPRB_TILEOFF 0x712a4 3564 #define _SPRB_OFFSET 0x712a4 3565 #define _SPRB_SURFLIVE 0x712ac 3566 #define _SPRB_SCALE 0x71304 3567 #define _SPRB_GAMC 0x71400 3568 3569 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 3570 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 3571 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 3572 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 3573 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 3574 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 3575 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 3576 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 3577 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 3578 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 3579 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 3580 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 3581 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 3582 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 3583 3584 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 3585 #define SP_ENABLE (1<<31) 3586 #define SP_GEAMMA_ENABLE (1<<30) 3587 #define SP_PIXFORMAT_MASK (0xf<<26) 3588 #define SP_FORMAT_YUV422 (0<<26) 3589 #define SP_FORMAT_BGR565 (5<<26) 3590 #define SP_FORMAT_BGRX8888 (6<<26) 3591 #define SP_FORMAT_BGRA8888 (7<<26) 3592 #define SP_FORMAT_RGBX1010102 (8<<26) 3593 #define SP_FORMAT_RGBA1010102 (9<<26) 3594 #define SP_FORMAT_RGBX8888 (0xe<<26) 3595 #define SP_FORMAT_RGBA8888 (0xf<<26) 3596 #define SP_SOURCE_KEY (1<<22) 3597 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 3598 #define SP_YUV_ORDER_YUYV (0<<16) 3599 #define SP_YUV_ORDER_UYVY (1<<16) 3600 #define SP_YUV_ORDER_YVYU (2<<16) 3601 #define SP_YUV_ORDER_VYUY (3<<16) 3602 #define SP_TILED (1<<10) 3603 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 3604 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 3605 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 3606 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 3607 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 3608 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 3609 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 3610 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 3611 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 3612 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 3613 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 3614 3615 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 3616 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 3617 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 3618 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 3619 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 3620 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 3621 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 3622 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 3623 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 3624 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 3625 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 3626 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 3627 3628 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) 3629 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) 3630 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) 3631 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) 3632 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) 3633 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) 3634 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) 3635 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) 3636 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) 3637 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) 3638 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) 3639 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) 3640 3641 /* VBIOS regs */ 3642 #define VGACNTRL 0x71400 3643 # define VGA_DISP_DISABLE (1 << 31) 3644 # define VGA_2X_MODE (1 << 30) 3645 # define VGA_PIPE_B_SELECT (1 << 29) 3646 3647 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) 3648 3649 /* Ironlake */ 3650 3651 #define CPU_VGACNTRL 0x41000 3652 3653 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 3654 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 3655 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 3656 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 3657 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 3658 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 3659 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 3660 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 3661 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 3662 3663 /* refresh rate hardware control */ 3664 #define RR_HW_CTL 0x45300 3665 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 3666 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 3667 3668 #define FDI_PLL_BIOS_0 0x46000 3669 #define FDI_PLL_FB_CLOCK_MASK 0xff 3670 #define FDI_PLL_BIOS_1 0x46004 3671 #define FDI_PLL_BIOS_2 0x46008 3672 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 3673 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 3674 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 3675 3676 #define PCH_3DCGDIS0 0x46020 3677 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 3678 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 3679 3680 #define PCH_3DCGDIS1 0x46024 3681 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 3682 3683 #define FDI_PLL_FREQ_CTL 0x46030 3684 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 3685 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 3686 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 3687 3688 3689 #define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030) 3690 #define PIPE_DATA_M1_OFFSET 0 3691 #define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034) 3692 #define PIPE_DATA_N1_OFFSET 0 3693 3694 #define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038) 3695 #define PIPE_DATA_M2_OFFSET 0 3696 #define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c) 3697 #define PIPE_DATA_N2_OFFSET 0 3698 3699 #define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040) 3700 #define PIPE_LINK_M1_OFFSET 0 3701 #define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044) 3702 #define PIPE_LINK_N1_OFFSET 0 3703 3704 #define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048) 3705 #define PIPE_LINK_M2_OFFSET 0 3706 #define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c) 3707 #define PIPE_LINK_N2_OFFSET 0 3708 3709 /* PIPEB timing regs are same start from 0x61000 */ 3710 3711 #define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030) 3712 #define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034) 3713 3714 #define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038) 3715 #define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c) 3716 3717 #define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040) 3718 #define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044) 3719 3720 #define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048) 3721 #define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c) 3722 3723 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 3724 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 3725 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 3726 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 3727 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 3728 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1) 3729 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2) 3730 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2) 3731 3732 /* CPU panel fitter */ 3733 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3734 #define _PFA_CTL_1 0x68080 3735 #define _PFB_CTL_1 0x68880 3736 #define PF_ENABLE (1<<31) 3737 #define PF_PIPE_SEL_MASK_IVB (3<<29) 3738 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 3739 #define PF_FILTER_MASK (3<<23) 3740 #define PF_FILTER_PROGRAMMED (0<<23) 3741 #define PF_FILTER_MED_3x3 (1<<23) 3742 #define PF_FILTER_EDGE_ENHANCE (2<<23) 3743 #define PF_FILTER_EDGE_SOFTEN (3<<23) 3744 #define _PFA_WIN_SZ 0x68074 3745 #define _PFB_WIN_SZ 0x68874 3746 #define _PFA_WIN_POS 0x68070 3747 #define _PFB_WIN_POS 0x68870 3748 #define _PFA_VSCALE 0x68084 3749 #define _PFB_VSCALE 0x68884 3750 #define _PFA_HSCALE 0x68090 3751 #define _PFB_HSCALE 0x68890 3752 3753 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 3754 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 3755 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 3756 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 3757 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 3758 3759 /* legacy palette */ 3760 #define _LGC_PALETTE_A 0x4a000 3761 #define _LGC_PALETTE_B 0x4a800 3762 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 3763 3764 #define _GAMMA_MODE_A 0x4a480 3765 #define _GAMMA_MODE_B 0x4ac80 3766 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 3767 #define GAMMA_MODE_MODE_MASK (3 << 0) 3768 #define GAMMA_MODE_MODE_8BIT (0 << 0) 3769 #define GAMMA_MODE_MODE_10BIT (1 << 0) 3770 #define GAMMA_MODE_MODE_12BIT (2 << 0) 3771 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 3772 3773 /* interrupts */ 3774 #define DE_MASTER_IRQ_CONTROL (1 << 31) 3775 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3776 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3777 #define DE_PLANEB_FLIP_DONE (1 << 27) 3778 #define DE_PLANEA_FLIP_DONE (1 << 26) 3779 #define DE_PCU_EVENT (1 << 25) 3780 #define DE_GTT_FAULT (1 << 24) 3781 #define DE_POISON (1 << 23) 3782 #define DE_PERFORM_COUNTER (1 << 22) 3783 #define DE_PCH_EVENT (1 << 21) 3784 #define DE_AUX_CHANNEL_A (1 << 20) 3785 #define DE_DP_A_HOTPLUG (1 << 19) 3786 #define DE_GSE (1 << 18) 3787 #define DE_PIPEB_VBLANK (1 << 15) 3788 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3789 #define DE_PIPEB_ODD_FIELD (1 << 13) 3790 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3791 #define DE_PIPEB_VSYNC (1 << 11) 3792 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3793 #define DE_PIPEA_VBLANK (1 << 7) 3794 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3795 #define DE_PIPEA_ODD_FIELD (1 << 5) 3796 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3797 #define DE_PIPEA_VSYNC (1 << 3) 3798 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3799 3800 /* More Ivybridge lolz */ 3801 #define DE_ERR_INT_IVB (1<<30) 3802 #define DE_GSE_IVB (1<<29) 3803 #define DE_PCH_EVENT_IVB (1<<28) 3804 #define DE_DP_A_HOTPLUG_IVB (1<<27) 3805 #define DE_AUX_CHANNEL_A_IVB (1<<26) 3806 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 3807 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 3808 #define DE_PIPEC_VBLANK_IVB (1<<10) 3809 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 3810 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 3811 #define DE_PIPEB_VBLANK_IVB (1<<5) 3812 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 3813 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 3814 #define DE_PIPEA_VBLANK_IVB (1<<0) 3815 3816 #define DE_PIPE_VBLANK_ILK(pipe) (1 << ((pipe * 8) + 7)) 3817 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) 3818 3819 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 3820 #define MASTER_INTERRUPT_ENABLE (1<<31) 3821 3822 #define DEISR 0x44000 3823 #define DEIMR 0x44004 3824 #define DEIIR 0x44008 3825 #define DEIER 0x4400c 3826 3827 #define GTISR 0x44010 3828 #define GTIMR 0x44014 3829 #define GTIIR 0x44018 3830 #define GTIER 0x4401c 3831 3832 #define ILK_DISPLAY_CHICKEN2 0x42004 3833 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3834 #define ILK_ELPIN_409_SELECT (1 << 25) 3835 #define ILK_DPARB_GATE (1<<22) 3836 #define ILK_VSDPFD_FULL (1<<21) 3837 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 3838 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 3839 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 3840 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 3841 #define ILK_HDCP_DISABLE (1<<25) 3842 #define ILK_eDP_A_DISABLE (1<<24) 3843 #define ILK_DESKTOP (1<<23) 3844 3845 #define ILK_DSPCLK_GATE_D 0x42020 3846 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 3847 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3848 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 3849 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 3850 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 3851 3852 #define IVB_CHICKEN3 0x4200c 3853 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 3854 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 3855 3856 #define CHICKEN_PAR1_1 0x42080 3857 #define FORCE_ARB_IDLE_PLANES (1 << 14) 3858 3859 #define DISP_ARB_CTL 0x45000 3860 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 3861 #define DISP_FBC_WM_DIS (1<<15) 3862 #define GEN7_MSG_CTL 0x45010 3863 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 3864 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 3865 3866 /* GEN7 chicken */ 3867 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 3868 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 3869 3870 #define GEN7_L3CNTLREG1 0xB01C 3871 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C 3872 #define GEN7_L3AGDIS (1<<19) 3873 3874 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 3875 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 3876 3877 #define GEN7_L3SQCREG4 0xb034 3878 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 3879 3880 /* WaCatErrorRejectionIssue */ 3881 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3882 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3883 3884 #define HSW_SCRATCH1 0xb038 3885 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 3886 3887 #define HSW_FUSE_STRAP 0x42014 3888 #define HSW_CDCLK_LIMIT (1 << 24) 3889 3890 /* PCH */ 3891 3892 /* south display engine interrupt: IBX */ 3893 #define SDE_AUDIO_POWER_D (1 << 27) 3894 #define SDE_AUDIO_POWER_C (1 << 26) 3895 #define SDE_AUDIO_POWER_B (1 << 25) 3896 #define SDE_AUDIO_POWER_SHIFT (25) 3897 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3898 #define SDE_GMBUS (1 << 24) 3899 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3900 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3901 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3902 #define SDE_AUDIO_TRANSB (1 << 21) 3903 #define SDE_AUDIO_TRANSA (1 << 20) 3904 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3905 #define SDE_POISON (1 << 19) 3906 /* 18 reserved */ 3907 #define SDE_FDI_RXB (1 << 17) 3908 #define SDE_FDI_RXA (1 << 16) 3909 #define SDE_FDI_MASK (3 << 16) 3910 #define SDE_AUXD (1 << 15) 3911 #define SDE_AUXC (1 << 14) 3912 #define SDE_AUXB (1 << 13) 3913 #define SDE_AUX_MASK (7 << 13) 3914 /* 12 reserved */ 3915 #define SDE_CRT_HOTPLUG (1 << 11) 3916 #define SDE_PORTD_HOTPLUG (1 << 10) 3917 #define SDE_PORTC_HOTPLUG (1 << 9) 3918 #define SDE_PORTB_HOTPLUG (1 << 8) 3919 #define SDE_SDVOB_HOTPLUG (1 << 6) 3920 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 3921 SDE_SDVOB_HOTPLUG | \ 3922 SDE_PORTB_HOTPLUG | \ 3923 SDE_PORTC_HOTPLUG | \ 3924 SDE_PORTD_HOTPLUG) 3925 #define SDE_TRANSB_CRC_DONE (1 << 5) 3926 #define SDE_TRANSB_CRC_ERR (1 << 4) 3927 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3928 #define SDE_TRANSA_CRC_DONE (1 << 2) 3929 #define SDE_TRANSA_CRC_ERR (1 << 1) 3930 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3931 #define SDE_TRANS_MASK (0x3f) 3932 3933 /* south display engine interrupt: CPT/PPT */ 3934 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 3935 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 3936 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 3937 #define SDE_AUDIO_POWER_SHIFT_CPT 29 3938 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 3939 #define SDE_AUXD_CPT (1 << 27) 3940 #define SDE_AUXC_CPT (1 << 26) 3941 #define SDE_AUXB_CPT (1 << 25) 3942 #define SDE_AUX_MASK_CPT (7 << 25) 3943 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3944 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3945 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3946 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3947 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 3948 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3949 SDE_SDVOB_HOTPLUG_CPT | \ 3950 SDE_PORTD_HOTPLUG_CPT | \ 3951 SDE_PORTC_HOTPLUG_CPT | \ 3952 SDE_PORTB_HOTPLUG_CPT) 3953 #define SDE_GMBUS_CPT (1 << 17) 3954 #define SDE_ERROR_CPT (1 << 16) 3955 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 3956 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 3957 #define SDE_FDI_RXC_CPT (1 << 8) 3958 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 3959 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 3960 #define SDE_FDI_RXB_CPT (1 << 4) 3961 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 3962 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 3963 #define SDE_FDI_RXA_CPT (1 << 0) 3964 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 3965 SDE_AUDIO_CP_REQ_B_CPT | \ 3966 SDE_AUDIO_CP_REQ_A_CPT) 3967 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 3968 SDE_AUDIO_CP_CHG_B_CPT | \ 3969 SDE_AUDIO_CP_CHG_A_CPT) 3970 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 3971 SDE_FDI_RXB_CPT | \ 3972 SDE_FDI_RXA_CPT) 3973 3974 #define SDEISR 0xc4000 3975 #define SDEIMR 0xc4004 3976 #define SDEIIR 0xc4008 3977 #define SDEIER 0xc400c 3978 3979 #define SERR_INT 0xc4040 3980 #define SERR_INT_POISON (1<<31) 3981 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 3982 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 3983 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 3984 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 3985 3986 /* digital port hotplug */ 3987 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 3988 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3989 #define PORTD_PULSE_DURATION_2ms (0) 3990 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 3991 #define PORTD_PULSE_DURATION_6ms (2 << 18) 3992 #define PORTD_PULSE_DURATION_100ms (3 << 18) 3993 #define PORTD_PULSE_DURATION_MASK (3 << 18) 3994 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) 3995 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 3996 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3997 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 3998 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3999 #define PORTC_PULSE_DURATION_2ms (0) 4000 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 4001 #define PORTC_PULSE_DURATION_6ms (2 << 10) 4002 #define PORTC_PULSE_DURATION_100ms (3 << 10) 4003 #define PORTC_PULSE_DURATION_MASK (3 << 10) 4004 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) 4005 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 4006 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 4007 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 4008 #define PORTB_HOTPLUG_ENABLE (1 << 4) 4009 #define PORTB_PULSE_DURATION_2ms (0) 4010 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 4011 #define PORTB_PULSE_DURATION_6ms (2 << 2) 4012 #define PORTB_PULSE_DURATION_100ms (3 << 2) 4013 #define PORTB_PULSE_DURATION_MASK (3 << 2) 4014 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) 4015 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 4016 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 4017 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 4018 4019 #define PCH_GPIOA 0xc5010 4020 #define PCH_GPIOB 0xc5014 4021 #define PCH_GPIOC 0xc5018 4022 #define PCH_GPIOD 0xc501c 4023 #define PCH_GPIOE 0xc5020 4024 #define PCH_GPIOF 0xc5024 4025 4026 #define PCH_GMBUS0 0xc5100 4027 #define PCH_GMBUS1 0xc5104 4028 #define PCH_GMBUS2 0xc5108 4029 #define PCH_GMBUS3 0xc510c 4030 #define PCH_GMBUS4 0xc5110 4031 #define PCH_GMBUS5 0xc5120 4032 4033 #define _PCH_DPLL_A 0xc6014 4034 #define _PCH_DPLL_B 0xc6018 4035 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 4036 4037 #define _PCH_FPA0 0xc6040 4038 #define FP_CB_TUNE (0x3<<22) 4039 #define _PCH_FPA1 0xc6044 4040 #define _PCH_FPB0 0xc6048 4041 #define _PCH_FPB1 0xc604c 4042 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 4043 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 4044 4045 #define PCH_DPLL_TEST 0xc606c 4046 4047 #define PCH_DREF_CONTROL 0xC6200 4048 #define DREF_CONTROL_MASK 0x7fc3 4049 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 4050 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 4051 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 4052 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 4053 #define DREF_SSC_SOURCE_DISABLE (0<<11) 4054 #define DREF_SSC_SOURCE_ENABLE (2<<11) 4055 #define DREF_SSC_SOURCE_MASK (3<<11) 4056 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 4057 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 4058 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 4059 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 4060 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 4061 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 4062 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 4063 #define DREF_SSC4_DOWNSPREAD (0<<6) 4064 #define DREF_SSC4_CENTERSPREAD (1<<6) 4065 #define DREF_SSC1_DISABLE (0<<1) 4066 #define DREF_SSC1_ENABLE (1<<1) 4067 #define DREF_SSC4_DISABLE (0) 4068 #define DREF_SSC4_ENABLE (1) 4069 4070 #define PCH_RAWCLK_FREQ 0xc6204 4071 #define FDL_TP1_TIMER_SHIFT 12 4072 #define FDL_TP1_TIMER_MASK (3<<12) 4073 #define FDL_TP2_TIMER_SHIFT 10 4074 #define FDL_TP2_TIMER_MASK (3<<10) 4075 #define RAWCLK_FREQ_MASK 0x3ff 4076 4077 #define PCH_DPLL_TMR_CFG 0xc6208 4078 4079 #define PCH_SSC4_PARMS 0xc6210 4080 #define PCH_SSC4_AUX_PARMS 0xc6214 4081 4082 #define PCH_DPLL_SEL 0xc7000 4083 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) 4084 #define TRANS_DPLLA_SEL(pipe) 0 4085 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) 4086 4087 /* transcoder */ 4088 4089 #define _PCH_TRANS_HTOTAL_A 0xe0000 4090 #define TRANS_HTOTAL_SHIFT 16 4091 #define TRANS_HACTIVE_SHIFT 0 4092 #define _PCH_TRANS_HBLANK_A 0xe0004 4093 #define TRANS_HBLANK_END_SHIFT 16 4094 #define TRANS_HBLANK_START_SHIFT 0 4095 #define _PCH_TRANS_HSYNC_A 0xe0008 4096 #define TRANS_HSYNC_END_SHIFT 16 4097 #define TRANS_HSYNC_START_SHIFT 0 4098 #define _PCH_TRANS_VTOTAL_A 0xe000c 4099 #define TRANS_VTOTAL_SHIFT 16 4100 #define TRANS_VACTIVE_SHIFT 0 4101 #define _PCH_TRANS_VBLANK_A 0xe0010 4102 #define TRANS_VBLANK_END_SHIFT 16 4103 #define TRANS_VBLANK_START_SHIFT 0 4104 #define _PCH_TRANS_VSYNC_A 0xe0014 4105 #define TRANS_VSYNC_END_SHIFT 16 4106 #define TRANS_VSYNC_START_SHIFT 0 4107 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 4108 4109 #define _PCH_TRANSA_DATA_M1 0xe0030 4110 #define _PCH_TRANSA_DATA_N1 0xe0034 4111 #define _PCH_TRANSA_DATA_M2 0xe0038 4112 #define _PCH_TRANSA_DATA_N2 0xe003c 4113 #define _PCH_TRANSA_LINK_M1 0xe0040 4114 #define _PCH_TRANSA_LINK_N1 0xe0044 4115 #define _PCH_TRANSA_LINK_M2 0xe0048 4116 #define _PCH_TRANSA_LINK_N2 0xe004c 4117 4118 /* Per-transcoder DIP controls */ 4119 4120 #define _VIDEO_DIP_CTL_A 0xe0200 4121 #define _VIDEO_DIP_DATA_A 0xe0208 4122 #define _VIDEO_DIP_GCP_A 0xe0210 4123 4124 #define _VIDEO_DIP_CTL_B 0xe1200 4125 #define _VIDEO_DIP_DATA_B 0xe1208 4126 #define _VIDEO_DIP_GCP_B 0xe1210 4127 4128 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 4129 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 4130 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 4131 4132 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 4133 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 4134 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 4135 4136 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 4137 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 4138 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 4139 4140 #define VLV_TVIDEO_DIP_CTL(pipe) \ 4141 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) 4142 #define VLV_TVIDEO_DIP_DATA(pipe) \ 4143 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) 4144 #define VLV_TVIDEO_DIP_GCP(pipe) \ 4145 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) 4146 4147 /* Haswell DIP controls */ 4148 #define HSW_VIDEO_DIP_CTL_A 0x60200 4149 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 4150 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 4151 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 4152 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 4153 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 4154 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 4155 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 4156 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 4157 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 4158 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 4159 #define HSW_VIDEO_DIP_GCP_A 0x60210 4160 4161 #define HSW_VIDEO_DIP_CTL_B 0x61200 4162 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 4163 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 4164 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 4165 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 4166 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 4167 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 4168 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 4169 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 4170 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 4171 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 4172 #define HSW_VIDEO_DIP_GCP_B 0x61210 4173 4174 #define HSW_TVIDEO_DIP_CTL(trans) \ 4175 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) 4176 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ 4177 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) 4178 #define HSW_TVIDEO_DIP_VS_DATA(trans) \ 4179 _TRANSCODER(trans, HSW_VIDEO_DIP_VS_DATA_A, HSW_VIDEO_DIP_VS_DATA_B) 4180 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ 4181 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) 4182 #define HSW_TVIDEO_DIP_GCP(trans) \ 4183 _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) 4184 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ 4185 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B) 4186 4187 #define HSW_STEREO_3D_CTL_A 0x70020 4188 #define S3D_ENABLE (1<<31) 4189 #define HSW_STEREO_3D_CTL_B 0x71020 4190 4191 #define HSW_STEREO_3D_CTL(trans) \ 4192 _TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A) 4193 4194 #define _PCH_TRANS_HTOTAL_B 0xe1000 4195 #define _PCH_TRANS_HBLANK_B 0xe1004 4196 #define _PCH_TRANS_HSYNC_B 0xe1008 4197 #define _PCH_TRANS_VTOTAL_B 0xe100c 4198 #define _PCH_TRANS_VBLANK_B 0xe1010 4199 #define _PCH_TRANS_VSYNC_B 0xe1014 4200 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 4201 4202 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 4203 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 4204 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 4205 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 4206 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 4207 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 4208 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ 4209 _PCH_TRANS_VSYNCSHIFT_B) 4210 4211 #define _PCH_TRANSB_DATA_M1 0xe1030 4212 #define _PCH_TRANSB_DATA_N1 0xe1034 4213 #define _PCH_TRANSB_DATA_M2 0xe1038 4214 #define _PCH_TRANSB_DATA_N2 0xe103c 4215 #define _PCH_TRANSB_LINK_M1 0xe1040 4216 #define _PCH_TRANSB_LINK_N1 0xe1044 4217 #define _PCH_TRANSB_LINK_M2 0xe1048 4218 #define _PCH_TRANSB_LINK_N2 0xe104c 4219 4220 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 4221 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 4222 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 4223 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 4224 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 4225 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 4226 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 4227 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 4228 4229 #define _PCH_TRANSACONF 0xf0008 4230 #define _PCH_TRANSBCONF 0xf1008 4231 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 4232 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ 4233 #define TRANS_DISABLE (0<<31) 4234 #define TRANS_ENABLE (1<<31) 4235 #define TRANS_STATE_MASK (1<<30) 4236 #define TRANS_STATE_DISABLE (0<<30) 4237 #define TRANS_STATE_ENABLE (1<<30) 4238 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 4239 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 4240 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 4241 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 4242 #define TRANS_INTERLACE_MASK (7<<21) 4243 #define TRANS_PROGRESSIVE (0<<21) 4244 #define TRANS_INTERLACED (3<<21) 4245 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 4246 #define TRANS_8BPC (0<<5) 4247 #define TRANS_10BPC (1<<5) 4248 #define TRANS_6BPC (2<<5) 4249 #define TRANS_12BPC (3<<5) 4250 4251 #define _TRANSA_CHICKEN1 0xf0060 4252 #define _TRANSB_CHICKEN1 0xf1060 4253 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 4254 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 4255 #define _TRANSA_CHICKEN2 0xf0064 4256 #define _TRANSB_CHICKEN2 0xf1064 4257 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 4258 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 4259 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 4260 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 4261 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 4262 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 4263 4264 #define SOUTH_CHICKEN1 0xc2000 4265 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 4266 #define FDIA_PHASE_SYNC_SHIFT_EN 18 4267 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 4268 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 4269 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 4270 #define SOUTH_CHICKEN2 0xc2004 4271 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 4272 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 4273 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 4274 4275 #define _FDI_RXA_CHICKEN 0xc200c 4276 #define _FDI_RXB_CHICKEN 0xc2010 4277 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 4278 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 4279 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 4280 4281 #define SOUTH_DSPCLK_GATE_D 0xc2020 4282 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 4283 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 4284 4285 /* CPU: FDI_TX */ 4286 #define _FDI_TXA_CTL 0x60100 4287 #define _FDI_TXB_CTL 0x61100 4288 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 4289 #define FDI_TX_DISABLE (0<<31) 4290 #define FDI_TX_ENABLE (1<<31) 4291 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 4292 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 4293 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 4294 #define FDI_LINK_TRAIN_NONE (3<<28) 4295 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 4296 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 4297 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 4298 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 4299 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 4300 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 4301 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 4302 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 4303 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 4304 SNB has different settings. */ 4305 /* SNB A-stepping */ 4306 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 4307 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 4308 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 4309 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 4310 /* SNB B-stepping */ 4311 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 4312 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 4313 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 4314 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 4315 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 4316 #define FDI_DP_PORT_WIDTH_SHIFT 19 4317 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 4318 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 4319 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 4320 /* Ironlake: hardwired to 1 */ 4321 #define FDI_TX_PLL_ENABLE (1<<14) 4322 4323 /* Ivybridge has different bits for lolz */ 4324 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 4325 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 4326 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 4327 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 4328 4329 /* both Tx and Rx */ 4330 #define FDI_COMPOSITE_SYNC (1<<11) 4331 #define FDI_LINK_TRAIN_AUTO (1<<10) 4332 #define FDI_SCRAMBLING_ENABLE (0<<7) 4333 #define FDI_SCRAMBLING_DISABLE (1<<7) 4334 4335 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 4336 #define _FDI_RXA_CTL 0xf000c 4337 #define _FDI_RXB_CTL 0xf100c 4338 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 4339 #define FDI_RX_ENABLE (1<<31) 4340 /* train, dp width same as FDI_TX */ 4341 #define FDI_FS_ERRC_ENABLE (1<<27) 4342 #define FDI_FE_ERRC_ENABLE (1<<26) 4343 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 4344 #define FDI_8BPC (0<<16) 4345 #define FDI_10BPC (1<<16) 4346 #define FDI_6BPC (2<<16) 4347 #define FDI_12BPC (3<<16) 4348 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 4349 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 4350 #define FDI_RX_PLL_ENABLE (1<<13) 4351 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 4352 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 4353 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 4354 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 4355 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 4356 #define FDI_PCDCLK (1<<4) 4357 /* CPT */ 4358 #define FDI_AUTO_TRAINING (1<<10) 4359 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 4360 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 4361 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 4362 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 4363 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 4364 4365 #define _FDI_RXA_MISC 0xf0010 4366 #define _FDI_RXB_MISC 0xf1010 4367 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 4368 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 4369 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 4370 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 4371 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 4372 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 4373 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 4374 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 4375 4376 #define _FDI_RXA_TUSIZE1 0xf0030 4377 #define _FDI_RXA_TUSIZE2 0xf0038 4378 #define _FDI_RXB_TUSIZE1 0xf1030 4379 #define _FDI_RXB_TUSIZE2 0xf1038 4380 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 4381 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 4382 4383 /* FDI_RX interrupt register format */ 4384 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 4385 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 4386 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 4387 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 4388 #define FDI_RX_FS_CODE_ERR (1<<6) 4389 #define FDI_RX_FE_CODE_ERR (1<<5) 4390 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 4391 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 4392 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 4393 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 4394 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 4395 4396 #define _FDI_RXA_IIR 0xf0014 4397 #define _FDI_RXA_IMR 0xf0018 4398 #define _FDI_RXB_IIR 0xf1014 4399 #define _FDI_RXB_IMR 0xf1018 4400 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 4401 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 4402 4403 #define FDI_PLL_CTL_1 0xfe000 4404 #define FDI_PLL_CTL_2 0xfe004 4405 4406 #define PCH_LVDS 0xe1180 4407 #define LVDS_DETECTED (1 << 1) 4408 4409 /* vlv has 2 sets of panel control regs. */ 4410 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 4411 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 4412 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 4413 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 4414 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 4415 4416 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 4417 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 4418 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 4419 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 4420 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 4421 4422 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) 4423 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) 4424 #define VLV_PIPE_PP_ON_DELAYS(pipe) \ 4425 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) 4426 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ 4427 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) 4428 #define VLV_PIPE_PP_DIVISOR(pipe) \ 4429 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) 4430 4431 #define PCH_PP_STATUS 0xc7200 4432 #define PCH_PP_CONTROL 0xc7204 4433 #define PANEL_UNLOCK_REGS (0xabcd << 16) 4434 #define PANEL_UNLOCK_MASK (0xffff << 16) 4435 #define EDP_FORCE_VDD (1 << 3) 4436 #define EDP_BLC_ENABLE (1 << 2) 4437 #define PANEL_POWER_RESET (1 << 1) 4438 #define PANEL_POWER_OFF (0 << 0) 4439 #define PANEL_POWER_ON (1 << 0) 4440 #define PCH_PP_ON_DELAYS 0xc7208 4441 #define PANEL_PORT_SELECT_MASK (3 << 30) 4442 #define PANEL_PORT_SELECT_LVDS (0 << 30) 4443 #define PANEL_PORT_SELECT_DPA (1 << 30) 4444 #define EDP_PANEL (1 << 30) 4445 #define PANEL_PORT_SELECT_DPC (2 << 30) 4446 #define PANEL_PORT_SELECT_DPD (3 << 30) 4447 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 4448 #define PANEL_POWER_UP_DELAY_SHIFT 16 4449 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 4450 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 4451 4452 #define PCH_PP_OFF_DELAYS 0xc720c 4453 #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30) 4454 #define PANEL_POWER_PORT_LVDS (0 << 30) 4455 #define PANEL_POWER_PORT_DP_A (1 << 30) 4456 #define PANEL_POWER_PORT_DP_C (2 << 30) 4457 #define PANEL_POWER_PORT_DP_D (3 << 30) 4458 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 4459 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 4460 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 4461 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 4462 4463 #define PCH_PP_DIVISOR 0xc7210 4464 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 4465 #define PP_REFERENCE_DIVIDER_SHIFT 8 4466 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 4467 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 4468 4469 #define PCH_DP_B 0xe4100 4470 #define PCH_DPB_AUX_CH_CTL 0xe4110 4471 #define PCH_DPB_AUX_CH_DATA1 0xe4114 4472 #define PCH_DPB_AUX_CH_DATA2 0xe4118 4473 #define PCH_DPB_AUX_CH_DATA3 0xe411c 4474 #define PCH_DPB_AUX_CH_DATA4 0xe4120 4475 #define PCH_DPB_AUX_CH_DATA5 0xe4124 4476 4477 #define PCH_DP_C 0xe4200 4478 #define PCH_DPC_AUX_CH_CTL 0xe4210 4479 #define PCH_DPC_AUX_CH_DATA1 0xe4214 4480 #define PCH_DPC_AUX_CH_DATA2 0xe4218 4481 #define PCH_DPC_AUX_CH_DATA3 0xe421c 4482 #define PCH_DPC_AUX_CH_DATA4 0xe4220 4483 #define PCH_DPC_AUX_CH_DATA5 0xe4224 4484 4485 #define PCH_DP_D 0xe4300 4486 #define PCH_DPD_AUX_CH_CTL 0xe4310 4487 #define PCH_DPD_AUX_CH_DATA1 0xe4314 4488 #define PCH_DPD_AUX_CH_DATA2 0xe4318 4489 #define PCH_DPD_AUX_CH_DATA3 0xe431c 4490 #define PCH_DPD_AUX_CH_DATA4 0xe4320 4491 #define PCH_DPD_AUX_CH_DATA5 0xe4324 4492 4493 /* CPT */ 4494 #define PORT_TRANS_A_SEL_CPT 0 4495 #define PORT_TRANS_B_SEL_CPT (1<<29) 4496 #define PORT_TRANS_C_SEL_CPT (2<<29) 4497 #define PORT_TRANS_SEL_MASK (3<<29) 4498 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 4499 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 4500 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 4501 4502 #define TRANS_DP_CTL_A 0xe0300 4503 #define TRANS_DP_CTL_B 0xe1300 4504 #define TRANS_DP_CTL_C 0xe2300 4505 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) 4506 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 4507 #define TRANS_DP_PORT_SEL_B (0<<29) 4508 #define TRANS_DP_PORT_SEL_C (1<<29) 4509 #define TRANS_DP_PORT_SEL_D (2<<29) 4510 #define TRANS_DP_PORT_SEL_NONE (3<<29) 4511 #define TRANS_DP_PORT_SEL_MASK (3<<29) 4512 #define TRANS_DP_AUDIO_ONLY (1<<26) 4513 #define TRANS_DP_ENH_FRAMING (1<<18) 4514 #define TRANS_DP_8BPC (0<<9) 4515 #define TRANS_DP_10BPC (1<<9) 4516 #define TRANS_DP_6BPC (2<<9) 4517 #define TRANS_DP_12BPC (3<<9) 4518 #define TRANS_DP_BPC_MASK (3<<9) 4519 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 4520 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 4521 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 4522 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 4523 #define TRANS_DP_SYNC_MASK (3<<3) 4524 4525 /* SNB eDP training params */ 4526 /* SNB A-stepping */ 4527 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 4528 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 4529 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 4530 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 4531 /* SNB B-stepping */ 4532 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 4533 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 4534 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 4535 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 4536 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 4537 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 4538 4539 /* IVB */ 4540 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 4541 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 4542 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 4543 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 4544 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 4545 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 4546 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 4547 4548 /* legacy values */ 4549 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 4550 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 4551 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 4552 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 4553 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 4554 4555 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 4556 4557 #define FORCEWAKE 0xA18C 4558 #define FORCEWAKE_VLV 0x1300b0 4559 #define FORCEWAKE_ACK_VLV 0x1300b4 4560 #define FORCEWAKE_MEDIA_VLV 0x1300b8 4561 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc 4562 #define FORCEWAKE_ACK_HSW 0x130044 4563 #define FORCEWAKE_ACK 0x130090 4564 #define VLV_GTLC_WAKE_CTRL 0x130090 4565 #define VLV_GTLC_PW_STATUS 0x130094 4566 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 4567 #define FORCEWAKE_KERNEL 0x1 4568 #define FORCEWAKE_USER 0x2 4569 #define FORCEWAKE_MT_ACK 0x130040 4570 #define ECOBUS 0xa180 4571 #define FORCEWAKE_MT_ENABLE (1<<5) 4572 4573 #define GTFIFODBG 0x120000 4574 #define GT_FIFO_CPU_ERROR_MASK 7 4575 #define GT_FIFO_OVFERR (1<<2) 4576 #define GT_FIFO_IAWRERR (1<<1) 4577 #define GT_FIFO_IARDERR (1<<0) 4578 4579 #define GT_FIFO_FREE_ENTRIES 0x120008 4580 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 4581 4582 #define HSW_IDICR 0x9008 4583 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 4584 #define HSW_EDRAM_PRESENT 0x120010 4585 4586 #define GEN6_UCGCTL1 0x9400 4587 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 4588 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 4589 4590 #define GEN6_UCGCTL2 0x9404 4591 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 4592 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 4593 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 4594 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 4595 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 4596 4597 #define GEN7_UCGCTL4 0x940c 4598 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 4599 4600 #define GEN6_RPNSWREQ 0xA008 4601 #define GEN6_TURBO_DISABLE (1<<31) 4602 #define GEN6_FREQUENCY(x) ((x)<<25) 4603 #define HSW_FREQUENCY(x) ((x)<<24) 4604 #define GEN6_OFFSET(x) ((x)<<19) 4605 #define GEN6_AGGRESSIVE_TURBO (0<<15) 4606 #define GEN6_RC_VIDEO_FREQ 0xA00C 4607 #define GEN6_RC_CONTROL 0xA090 4608 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 4609 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 4610 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 4611 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 4612 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 4613 #define GEN7_RC_CTL_TO_MODE (1<<28) 4614 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 4615 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 4616 #define GEN6_RP_DOWN_TIMEOUT 0xA010 4617 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 4618 #define GEN6_RPSTAT1 0xA01C 4619 #define GEN6_CAGF_SHIFT 8 4620 #define HSW_CAGF_SHIFT 7 4621 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 4622 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 4623 #define GEN6_RP_CONTROL 0xA024 4624 #define GEN6_RP_MEDIA_TURBO (1<<11) 4625 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 4626 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 4627 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 4628 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 4629 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 4630 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 4631 #define GEN6_RP_ENABLE (1<<7) 4632 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 4633 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 4634 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 4635 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) 4636 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 4637 #define GEN6_RP_UP_THRESHOLD 0xA02C 4638 #define GEN6_RP_DOWN_THRESHOLD 0xA030 4639 #define GEN6_RP_CUR_UP_EI 0xA050 4640 #define GEN6_CURICONT_MASK 0xffffff 4641 #define GEN6_RP_CUR_UP 0xA054 4642 #define GEN6_CURBSYTAVG_MASK 0xffffff 4643 #define GEN6_RP_PREV_UP 0xA058 4644 #define GEN6_RP_CUR_DOWN_EI 0xA05C 4645 #define GEN6_CURIAVG_MASK 0xffffff 4646 #define GEN6_RP_CUR_DOWN 0xA060 4647 #define GEN6_RP_PREV_DOWN 0xA064 4648 #define GEN6_RP_UP_EI 0xA068 4649 #define GEN6_RP_DOWN_EI 0xA06C 4650 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 4651 #define GEN6_RC_STATE 0xA094 4652 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 4653 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 4654 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 4655 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 4656 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 4657 #define GEN6_RC_SLEEP 0xA0B0 4658 #define GEN6_RC1e_THRESHOLD 0xA0B4 4659 #define GEN6_RC6_THRESHOLD 0xA0B8 4660 #define GEN6_RC6p_THRESHOLD 0xA0BC 4661 #define GEN6_RC6pp_THRESHOLD 0xA0C0 4662 #define GEN6_PMINTRMSK 0xA168 4663 4664 #define GEN6_PMISR 0x44020 4665 #define GEN6_PMIMR 0x44024 /* rps_lock */ 4666 #define GEN6_PMIIR 0x44028 4667 #define GEN6_PMIER 0x4402C 4668 #define GEN6_PM_MBOX_EVENT (1<<25) 4669 #define GEN6_PM_THERMAL_EVENT (1<<24) 4670 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 4671 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 4672 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 4673 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 4674 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 4675 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 4676 GEN6_PM_RP_DOWN_THRESHOLD | \ 4677 GEN6_PM_RP_DOWN_TIMEOUT) 4678 4679 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 4680 #define GEN6_GT_GFX_RC6 0x138108 4681 #define GEN6_GT_GFX_RC6p 0x13810C 4682 #define GEN6_GT_GFX_RC6pp 0x138110 4683 4684 #define GEN6_PCODE_MAILBOX 0x138124 4685 #define GEN6_PCODE_READY (1<<31) 4686 #define GEN6_READ_OC_PARAMS 0xc 4687 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 4688 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 4689 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 4690 #define GEN6_PCODE_READ_RC6VIDS 0x5 4691 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 4692 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 4693 #define GEN6_PCODE_DATA 0x138128 4694 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 4695 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 4696 4697 #define GEN6_GT_CORE_STATUS 0x138060 4698 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 4699 #define GEN6_RCn_MASK 7 4700 #define GEN6_RC0 0 4701 #define GEN6_RC3 2 4702 #define GEN6_RC6 3 4703 #define GEN6_RC7 4 4704 4705 #define GEN7_MISCCPCTL (0x9424) 4706 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 4707 4708 /* IVYBRIDGE DPF */ 4709 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ 4710 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 4711 #define GEN7_PARITY_ERROR_VALID (1<<13) 4712 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 4713 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 4714 #define GEN7_PARITY_ERROR_ROW(reg) \ 4715 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 4716 #define GEN7_PARITY_ERROR_BANK(reg) \ 4717 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 4718 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 4719 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 4720 #define GEN7_L3CDERRST1_ENABLE (1<<7) 4721 4722 #define GEN7_L3LOG_BASE 0xB070 4723 #define GEN7_L3LOG_SIZE 0x80 4724 4725 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ 4726 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 4727 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 4728 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 4729 4730 #define GEN7_ROW_CHICKEN2 0xe4f4 4731 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 4732 #define DOP_CLOCK_GATING_DISABLE (1<<0) 4733 4734 #define HSW_ROW_CHICKEN3 0xe49c 4735 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 4736 4737 #define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) 4738 #define INTEL_AUDIO_DEVCL 0x808629FB 4739 #define INTEL_AUDIO_DEVBLC 0x80862801 4740 #define INTEL_AUDIO_DEVCTG 0x80862802 4741 4742 #define G4X_AUD_CNTL_ST 0x620B4 4743 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 4744 #define G4X_ELDV_DEVCTG (1 << 14) 4745 #define G4X_ELD_ADDR (0xf << 5) 4746 #define G4X_ELD_ACK (1 << 4) 4747 #define G4X_HDMIW_HDMIEDID 0x6210C 4748 4749 #define IBX_HDMIW_HDMIEDID_A 0xE2050 4750 #define IBX_HDMIW_HDMIEDID_B 0xE2150 4751 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 4752 IBX_HDMIW_HDMIEDID_A, \ 4753 IBX_HDMIW_HDMIEDID_B) 4754 #define IBX_AUD_CNTL_ST_A 0xE20B4 4755 #define IBX_AUD_CNTL_ST_B 0xE21B4 4756 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 4757 IBX_AUD_CNTL_ST_A, \ 4758 IBX_AUD_CNTL_ST_B) 4759 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 4760 #define IBX_ELD_ADDRESS (0x1f << 5) 4761 #define IBX_ELD_ACK (1 << 4) 4762 #define IBX_AUD_CNTL_ST2 0xE20C0 4763 #define IBX_ELD_VALIDB (1 << 0) 4764 #define IBX_CP_READYB (1 << 1) 4765 4766 #define CPT_HDMIW_HDMIEDID_A 0xE5050 4767 #define CPT_HDMIW_HDMIEDID_B 0xE5150 4768 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 4769 CPT_HDMIW_HDMIEDID_A, \ 4770 CPT_HDMIW_HDMIEDID_B) 4771 #define CPT_AUD_CNTL_ST_A 0xE50B4 4772 #define CPT_AUD_CNTL_ST_B 0xE51B4 4773 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 4774 CPT_AUD_CNTL_ST_A, \ 4775 CPT_AUD_CNTL_ST_B) 4776 #define CPT_AUD_CNTRL_ST2 0xE50C0 4777 4778 /* These are the 4 32-bit write offset registers for each stream 4779 * output buffer. It determines the offset from the 4780 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 4781 */ 4782 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 4783 4784 #define IBX_AUD_CONFIG_A 0xe2000 4785 #define IBX_AUD_CONFIG_B 0xe2100 4786 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ 4787 IBX_AUD_CONFIG_A, \ 4788 IBX_AUD_CONFIG_B) 4789 #define CPT_AUD_CONFIG_A 0xe5000 4790 #define CPT_AUD_CONFIG_B 0xe5100 4791 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ 4792 CPT_AUD_CONFIG_A, \ 4793 CPT_AUD_CONFIG_B) 4794 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 4795 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 4796 #define AUD_CONFIG_UPPER_N_SHIFT 20 4797 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 4798 #define AUD_CONFIG_LOWER_N_SHIFT 4 4799 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 4800 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 4801 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) 4802 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 4803 4804 /* HSW Audio */ 4805 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ 4806 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ 4807 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ 4808 HSW_AUD_CONFIG_A, \ 4809 HSW_AUD_CONFIG_B) 4810 4811 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ 4812 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ 4813 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ 4814 HSW_AUD_MISC_CTRL_A, \ 4815 HSW_AUD_MISC_CTRL_B) 4816 4817 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ 4818 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ 4819 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ 4820 HSW_AUD_DIP_ELD_CTRL_ST_A, \ 4821 HSW_AUD_DIP_ELD_CTRL_ST_B) 4822 4823 /* Audio Digital Converter */ 4824 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ 4825 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ 4826 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ 4827 HSW_AUD_DIG_CNVT_1, \ 4828 HSW_AUD_DIG_CNVT_2) 4829 #define DIP_PORT_SEL_MASK 0x3 4830 4831 #define HSW_AUD_EDID_DATA_A 0x65050 4832 #define HSW_AUD_EDID_DATA_B 0x65150 4833 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ 4834 HSW_AUD_EDID_DATA_A, \ 4835 HSW_AUD_EDID_DATA_B) 4836 4837 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ 4838 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ 4839 #define AUDIO_INACTIVE_C (1<<11) 4840 #define AUDIO_INACTIVE_B (1<<7) 4841 #define AUDIO_INACTIVE_A (1<<3) 4842 #define AUDIO_OUTPUT_ENABLE_A (1<<2) 4843 #define AUDIO_OUTPUT_ENABLE_B (1<<6) 4844 #define AUDIO_OUTPUT_ENABLE_C (1<<10) 4845 #define AUDIO_ELD_VALID_A (1<<0) 4846 #define AUDIO_ELD_VALID_B (1<<4) 4847 #define AUDIO_ELD_VALID_C (1<<8) 4848 #define AUDIO_CP_READY_A (1<<1) 4849 #define AUDIO_CP_READY_B (1<<5) 4850 #define AUDIO_CP_READY_C (1<<9) 4851 4852 /* HSW Power Wells */ 4853 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ 4854 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ 4855 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ 4856 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ 4857 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 4858 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 4859 #define HSW_PWR_WELL_CTL5 0x45410 4860 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 4861 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 4862 #define HSW_PWR_WELL_FORCE_ON (1<<19) 4863 #define HSW_PWR_WELL_CTL6 0x45414 4864 4865 /* Per-pipe DDI Function Control */ 4866 #define TRANS_DDI_FUNC_CTL_A 0x60400 4867 #define TRANS_DDI_FUNC_CTL_B 0x61400 4868 #define TRANS_DDI_FUNC_CTL_C 0x62400 4869 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 4870 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ 4871 TRANS_DDI_FUNC_CTL_B) 4872 #define TRANS_DDI_FUNC_ENABLE (1<<31) 4873 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 4874 #define TRANS_DDI_PORT_MASK (7<<28) 4875 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 4876 #define TRANS_DDI_PORT_NONE (0<<28) 4877 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 4878 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 4879 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 4880 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 4881 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 4882 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 4883 #define TRANS_DDI_BPC_MASK (7<<20) 4884 #define TRANS_DDI_BPC_8 (0<<20) 4885 #define TRANS_DDI_BPC_10 (1<<20) 4886 #define TRANS_DDI_BPC_6 (2<<20) 4887 #define TRANS_DDI_BPC_12 (3<<20) 4888 #define TRANS_DDI_PVSYNC (1<<17) 4889 #define TRANS_DDI_PHSYNC (1<<16) 4890 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 4891 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 4892 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 4893 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 4894 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 4895 #define TRANS_DDI_BFI_ENABLE (1<<4) 4896 4897 /* DisplayPort Transport Control */ 4898 #define DP_TP_CTL_A 0x64040 4899 #define DP_TP_CTL_B 0x64140 4900 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) 4901 #define DP_TP_CTL_ENABLE (1<<31) 4902 #define DP_TP_CTL_MODE_SST (0<<27) 4903 #define DP_TP_CTL_MODE_MST (1<<27) 4904 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 4905 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 4906 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 4907 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 4908 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 4909 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 4910 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 4911 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 4912 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 4913 4914 /* DisplayPort Transport Status */ 4915 #define DP_TP_STATUS_A 0x64044 4916 #define DP_TP_STATUS_B 0x64144 4917 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 4918 #define DP_TP_STATUS_IDLE_DONE (1<<25) 4919 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 4920 4921 /* DDI Buffer Control */ 4922 #define DDI_BUF_CTL_A 0x64000 4923 #define DDI_BUF_CTL_B 0x64100 4924 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 4925 #define DDI_BUF_CTL_ENABLE (1<<31) 4926 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 4927 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ 4928 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ 4929 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ 4930 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ 4931 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ 4932 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ 4933 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ 4934 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ 4935 #define DDI_BUF_EMP_MASK (0xf<<24) 4936 #define DDI_BUF_PORT_REVERSAL (1<<16) 4937 #define DDI_BUF_IS_IDLE (1<<7) 4938 #define DDI_A_4_LANES (1<<4) 4939 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 4940 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 4941 4942 /* DDI Buffer Translations */ 4943 #define DDI_BUF_TRANS_A 0x64E00 4944 #define DDI_BUF_TRANS_B 0x64E60 4945 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) 4946 4947 /* Sideband Interface (SBI) is programmed indirectly, via 4948 * SBI_ADDR, which contains the register offset; and SBI_DATA, 4949 * which contains the payload */ 4950 #define SBI_ADDR 0xC6000 4951 #define SBI_DATA 0xC6004 4952 #define SBI_CTL_STAT 0xC6008 4953 #define SBI_CTL_DEST_ICLK (0x0<<16) 4954 #define SBI_CTL_DEST_MPHY (0x1<<16) 4955 #define SBI_CTL_OP_IORD (0x2<<8) 4956 #define SBI_CTL_OP_IOWR (0x3<<8) 4957 #define SBI_CTL_OP_CRRD (0x6<<8) 4958 #define SBI_CTL_OP_CRWR (0x7<<8) 4959 #define SBI_RESPONSE_FAIL (0x1<<1) 4960 #define SBI_RESPONSE_SUCCESS (0x0<<1) 4961 #define SBI_BUSY (0x1<<0) 4962 #define SBI_READY (0x0<<0) 4963 4964 /* SBI offsets */ 4965 #define SBI_SSCDIVINTPHASE6 0x0600 4966 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 4967 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 4968 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 4969 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 4970 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 4971 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 4972 #define SBI_SSCCTL 0x020c 4973 #define SBI_SSCCTL6 0x060C 4974 #define SBI_SSCCTL_PATHALT (1<<3) 4975 #define SBI_SSCCTL_DISABLE (1<<0) 4976 #define SBI_SSCAUXDIV6 0x0610 4977 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 4978 #define SBI_DBUFF0 0x2a00 4979 #define SBI_GEN0 0x1f00 4980 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 4981 4982 /* LPT PIXCLK_GATE */ 4983 #define PIXCLK_GATE 0xC6020 4984 #define PIXCLK_GATE_UNGATE (1<<0) 4985 #define PIXCLK_GATE_GATE (0<<0) 4986 4987 /* SPLL */ 4988 #define SPLL_CTL 0x46020 4989 #define SPLL_PLL_ENABLE (1<<31) 4990 #define SPLL_PLL_SSC (1<<28) 4991 #define SPLL_PLL_NON_SSC (2<<28) 4992 #define SPLL_PLL_FREQ_810MHz (0<<26) 4993 #define SPLL_PLL_FREQ_1350MHz (1<<26) 4994 4995 /* WRPLL */ 4996 #define WRPLL_CTL1 0x46040 4997 #define WRPLL_CTL2 0x46060 4998 #define WRPLL_PLL_ENABLE (1<<31) 4999 #define WRPLL_PLL_SELECT_SSC (0x01<<28) 5000 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28) 5001 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) 5002 /* WRPLL divider programming */ 5003 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 5004 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 5005 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 5006 5007 /* Port clock selection */ 5008 #define PORT_CLK_SEL_A 0x46100 5009 #define PORT_CLK_SEL_B 0x46104 5010 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) 5011 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 5012 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 5013 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 5014 #define PORT_CLK_SEL_SPLL (3<<29) 5015 #define PORT_CLK_SEL_WRPLL1 (4<<29) 5016 #define PORT_CLK_SEL_WRPLL2 (5<<29) 5017 #define PORT_CLK_SEL_NONE (7<<29) 5018 5019 /* Transcoder clock selection */ 5020 #define TRANS_CLK_SEL_A 0x46140 5021 #define TRANS_CLK_SEL_B 0x46144 5022 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) 5023 /* For each transcoder, we need to select the corresponding port clock */ 5024 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 5025 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 5026 5027 #define _TRANSA_MSA_MISC 0x60410 5028 #define _TRANSB_MSA_MISC 0x61410 5029 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ 5030 _TRANSB_MSA_MISC) 5031 #define TRANS_MSA_SYNC_CLK (1<<0) 5032 #define TRANS_MSA_6_BPC (0<<5) 5033 #define TRANS_MSA_8_BPC (1<<5) 5034 #define TRANS_MSA_10_BPC (2<<5) 5035 #define TRANS_MSA_12_BPC (3<<5) 5036 #define TRANS_MSA_16_BPC (4<<5) 5037 5038 /* LCPLL Control */ 5039 #define LCPLL_CTL 0x130040 5040 #define LCPLL_PLL_DISABLE (1<<31) 5041 #define LCPLL_PLL_LOCK (1<<30) 5042 #define LCPLL_CLK_FREQ_MASK (3<<26) 5043 #define LCPLL_CLK_FREQ_450 (0<<26) 5044 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 5045 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 5046 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 5047 #define LCPLL_CD_SOURCE_FCLK (1<<21) 5048 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 5049 5050 #define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 5051 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 5052 #define D_COMP_COMP_FORCE (1<<8) 5053 #define D_COMP_COMP_DISABLE (1<<0) 5054 5055 /* Pipe WM_LINETIME - watermark line time */ 5056 #define PIPE_WM_LINETIME_A 0x45270 5057 #define PIPE_WM_LINETIME_B 0x45274 5058 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ 5059 PIPE_WM_LINETIME_B) 5060 #define PIPE_WM_LINETIME_MASK (0x1ff) 5061 #define PIPE_WM_LINETIME_TIME(x) ((x)) 5062 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 5063 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 5064 5065 /* SFUSE_STRAP */ 5066 #define SFUSE_STRAP 0xc2014 5067 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 5068 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 5069 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 5070 5071 #define WM_MISC 0x45260 5072 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 5073 5074 #define WM_DBG 0x45280 5075 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 5076 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 5077 #define WM_DBG_DISALLOW_SPRITE (1<<2) 5078 5079 /* pipe CSC */ 5080 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 5081 #define _PIPE_A_CSC_COEFF_BY 0x49014 5082 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 5083 #define _PIPE_A_CSC_COEFF_BU 0x4901c 5084 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 5085 #define _PIPE_A_CSC_COEFF_BV 0x49024 5086 #define _PIPE_A_CSC_MODE 0x49028 5087 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 5088 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 5089 #define CSC_MODE_YUV_TO_RGB (1 << 0) 5090 #define _PIPE_A_CSC_PREOFF_HI 0x49030 5091 #define _PIPE_A_CSC_PREOFF_ME 0x49034 5092 #define _PIPE_A_CSC_PREOFF_LO 0x49038 5093 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 5094 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 5095 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 5096 5097 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 5098 #define _PIPE_B_CSC_COEFF_BY 0x49114 5099 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 5100 #define _PIPE_B_CSC_COEFF_BU 0x4911c 5101 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 5102 #define _PIPE_B_CSC_COEFF_BV 0x49124 5103 #define _PIPE_B_CSC_MODE 0x49128 5104 #define _PIPE_B_CSC_PREOFF_HI 0x49130 5105 #define _PIPE_B_CSC_PREOFF_ME 0x49134 5106 #define _PIPE_B_CSC_PREOFF_LO 0x49138 5107 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 5108 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 5109 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 5110 5111 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 5112 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 5113 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 5114 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 5115 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 5116 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 5117 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 5118 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 5119 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 5120 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 5121 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 5122 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 5123 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 5124 5125 #endif /* _I915_REG_H_ */ 5126