1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 30 /* 31 * The Bridge device's PCI config space has information about the 32 * fb aperture size and the amount of pre-reserved memory. 33 * This is all handled in the intel-gtt.ko module. i915.ko only 34 * cares about the vga bit for the vga rbiter. 35 */ 36 #define INTEL_GMCH_CTRL 0x52 37 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 38 39 /* PCI config space */ 40 41 #define HPLLCC 0xc0 /* 855 only */ 42 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 43 #define GC_CLOCK_133_200 (0 << 0) 44 #define GC_CLOCK_100_200 (1 << 0) 45 #define GC_CLOCK_100_133 (2 << 0) 46 #define GC_CLOCK_166_250 (3 << 0) 47 #define GCFGC2 0xda 48 #define GCFGC 0xf0 /* 915+ only */ 49 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 50 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 51 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 52 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 53 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 54 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 55 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 56 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 57 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 58 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 59 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 60 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 61 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 62 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 63 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 64 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 65 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 66 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 67 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 68 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 69 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 70 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 71 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 72 #define LBB 0xf4 73 74 /* Graphics reset regs */ 75 #define I965_GDRST 0xc0 /* PCI config register */ 76 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 77 #define GRDOM_FULL (0<<2) 78 #define GRDOM_RENDER (1<<2) 79 #define GRDOM_MEDIA (3<<2) 80 81 #define GEN6_GDRST 0x941c 82 #define GEN6_GRDOM_FULL (1 << 0) 83 #define GEN6_GRDOM_RENDER (1 << 1) 84 #define GEN6_GRDOM_MEDIA (1 << 2) 85 #define GEN6_GRDOM_BLT (1 << 3) 86 87 /* VGA stuff */ 88 89 #define VGA_ST01_MDA 0x3ba 90 #define VGA_ST01_CGA 0x3da 91 92 #define VGA_MSR_WRITE 0x3c2 93 #define VGA_MSR_READ 0x3cc 94 #define VGA_MSR_MEM_EN (1<<1) 95 #define VGA_MSR_CGA_MODE (1<<0) 96 97 #define VGA_SR_INDEX 0x3c4 98 #define VGA_SR_DATA 0x3c5 99 100 #define VGA_AR_INDEX 0x3c0 101 #define VGA_AR_VID_EN (1<<5) 102 #define VGA_AR_DATA_WRITE 0x3c0 103 #define VGA_AR_DATA_READ 0x3c1 104 105 #define VGA_GR_INDEX 0x3ce 106 #define VGA_GR_DATA 0x3cf 107 /* GR05 */ 108 #define VGA_GR_MEM_READ_MODE_SHIFT 3 109 #define VGA_GR_MEM_READ_MODE_PLANE 1 110 /* GR06 */ 111 #define VGA_GR_MEM_MODE_MASK 0xc 112 #define VGA_GR_MEM_MODE_SHIFT 2 113 #define VGA_GR_MEM_A0000_AFFFF 0 114 #define VGA_GR_MEM_A0000_BFFFF 1 115 #define VGA_GR_MEM_B0000_B7FFF 2 116 #define VGA_GR_MEM_B0000_BFFFF 3 117 118 #define VGA_DACMASK 0x3c6 119 #define VGA_DACRX 0x3c7 120 #define VGA_DACWX 0x3c8 121 #define VGA_DACDATA 0x3c9 122 123 #define VGA_CR_INDEX_MDA 0x3b4 124 #define VGA_CR_DATA_MDA 0x3b5 125 #define VGA_CR_INDEX_CGA 0x3d4 126 #define VGA_CR_DATA_CGA 0x3d5 127 128 /* 129 * Memory interface instructions used by the kernel 130 */ 131 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 132 133 #define MI_NOOP MI_INSTR(0, 0) 134 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 135 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 136 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 137 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 138 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 139 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 140 #define MI_FLUSH MI_INSTR(0x04, 0) 141 #define MI_READ_FLUSH (1 << 0) 142 #define MI_EXE_FLUSH (1 << 1) 143 #define MI_NO_WRITE_FLUSH (1 << 2) 144 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 145 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 146 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 147 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 148 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 149 #define MI_SUSPEND_FLUSH_EN (1<<0) 150 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 151 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 152 #define MI_OVERLAY_CONTINUE (0x0<<21) 153 #define MI_OVERLAY_ON (0x1<<21) 154 #define MI_OVERLAY_OFF (0x2<<21) 155 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 156 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 157 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 158 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 159 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 160 #define MI_MM_SPACE_GTT (1<<8) 161 #define MI_MM_SPACE_PHYSICAL (0<<8) 162 #define MI_SAVE_EXT_STATE_EN (1<<3) 163 #define MI_RESTORE_EXT_STATE_EN (1<<2) 164 #define MI_FORCE_RESTORE (1<<1) 165 #define MI_RESTORE_INHIBIT (1<<0) 166 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 167 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 168 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 169 #define MI_STORE_DWORD_INDEX_SHIFT 2 170 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 171 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 172 * simply ignores the register load under certain conditions. 173 * - One can actually load arbitrary many arbitrary registers: Simply issue x 174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 175 */ 176 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 177 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 178 #define MI_INVALIDATE_TLB (1<<18) 179 #define MI_INVALIDATE_BSD (1<<7) 180 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 181 #define MI_BATCH_NON_SECURE (1) 182 #define MI_BATCH_NON_SECURE_I965 (1<<8) 183 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 184 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 185 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 186 #define MI_SEMAPHORE_UPDATE (1<<21) 187 #define MI_SEMAPHORE_COMPARE (1<<20) 188 #define MI_SEMAPHORE_REGISTER (1<<18) 189 /* 190 * 3D instructions used by the kernel 191 */ 192 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 193 194 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 195 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 196 #define SC_UPDATE_SCISSOR (0x1<<1) 197 #define SC_ENABLE_MASK (0x1<<0) 198 #define SC_ENABLE (0x1<<0) 199 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 200 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 201 #define SCI_YMIN_MASK (0xffff<<16) 202 #define SCI_XMIN_MASK (0xffff<<0) 203 #define SCI_YMAX_MASK (0xffff<<16) 204 #define SCI_XMAX_MASK (0xffff<<0) 205 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 206 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 207 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 208 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 209 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 210 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 211 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 212 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 213 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 214 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 215 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 216 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 217 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 218 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 219 #define BLT_DEPTH_8 (0<<24) 220 #define BLT_DEPTH_16_565 (1<<24) 221 #define BLT_DEPTH_16_1555 (2<<24) 222 #define BLT_DEPTH_32 (3<<24) 223 #define BLT_ROP_GXCOPY (0xcc<<16) 224 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 225 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 226 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 227 #define ASYNC_FLIP (1<<22) 228 #define DISPLAY_PLANE_A (0<<20) 229 #define DISPLAY_PLANE_B (1<<20) 230 #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) 231 #define PIPE_CONTROL_QW_WRITE (1<<14) 232 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 233 #define PIPE_CONTROL_WC_FLUSH (1<<12) 234 #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ 235 #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ 236 #define PIPE_CONTROL_ISP_DIS (1<<9) 237 #define PIPE_CONTROL_NOTIFY (1<<8) 238 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 239 #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ 240 241 242 /* 243 * Reset registers 244 */ 245 #define DEBUG_RESET_I830 0x6070 246 #define DEBUG_RESET_FULL (1<<7) 247 #define DEBUG_RESET_RENDER (1<<8) 248 #define DEBUG_RESET_DISPLAY (1<<9) 249 250 251 /* 252 * Fence registers 253 */ 254 #define FENCE_REG_830_0 0x2000 255 #define FENCE_REG_945_8 0x3000 256 #define I830_FENCE_START_MASK 0x07f80000 257 #define I830_FENCE_TILING_Y_SHIFT 12 258 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 259 #define I830_FENCE_PITCH_SHIFT 4 260 #define I830_FENCE_REG_VALID (1<<0) 261 #define I915_FENCE_MAX_PITCH_VAL 4 262 #define I830_FENCE_MAX_PITCH_VAL 6 263 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 264 265 #define I915_FENCE_START_MASK 0x0ff00000 266 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 267 268 #define FENCE_REG_965_0 0x03000 269 #define I965_FENCE_PITCH_SHIFT 2 270 #define I965_FENCE_TILING_Y_SHIFT 1 271 #define I965_FENCE_REG_VALID (1<<0) 272 #define I965_FENCE_MAX_PITCH_VAL 0x0400 273 274 #define FENCE_REG_SANDYBRIDGE_0 0x100000 275 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 276 277 /* 278 * Instruction and interrupt control regs 279 */ 280 #define PGTBL_ER 0x02024 281 #define RENDER_RING_BASE 0x02000 282 #define BSD_RING_BASE 0x04000 283 #define GEN6_BSD_RING_BASE 0x12000 284 #define BLT_RING_BASE 0x22000 285 #define RING_TAIL(base) ((base)+0x30) 286 #define RING_HEAD(base) ((base)+0x34) 287 #define RING_START(base) ((base)+0x38) 288 #define RING_CTL(base) ((base)+0x3c) 289 #define RING_SYNC_0(base) ((base)+0x40) 290 #define RING_SYNC_1(base) ((base)+0x44) 291 #define RING_MAX_IDLE(base) ((base)+0x54) 292 #define RING_HWS_PGA(base) ((base)+0x80) 293 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 294 #define RING_ACTHD(base) ((base)+0x74) 295 #define RING_NOPID(base) ((base)+0x94) 296 #define RING_IMR(base) ((base)+0xa8) 297 #define TAIL_ADDR 0x001FFFF8 298 #define HEAD_WRAP_COUNT 0xFFE00000 299 #define HEAD_WRAP_ONE 0x00200000 300 #define HEAD_ADDR 0x001FFFFC 301 #define RING_NR_PAGES 0x001FF000 302 #define RING_REPORT_MASK 0x00000006 303 #define RING_REPORT_64K 0x00000002 304 #define RING_REPORT_128K 0x00000004 305 #define RING_NO_REPORT 0x00000000 306 #define RING_VALID_MASK 0x00000001 307 #define RING_VALID 0x00000001 308 #define RING_INVALID 0x00000000 309 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 310 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 311 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 312 #if 0 313 #define PRB0_TAIL 0x02030 314 #define PRB0_HEAD 0x02034 315 #define PRB0_START 0x02038 316 #define PRB0_CTL 0x0203c 317 #define PRB1_TAIL 0x02040 /* 915+ only */ 318 #define PRB1_HEAD 0x02044 /* 915+ only */ 319 #define PRB1_START 0x02048 /* 915+ only */ 320 #define PRB1_CTL 0x0204c /* 915+ only */ 321 #endif 322 #define IPEIR_I965 0x02064 323 #define IPEHR_I965 0x02068 324 #define INSTDONE_I965 0x0206c 325 #define INSTPS 0x02070 /* 965+ only */ 326 #define INSTDONE1 0x0207c /* 965+ only */ 327 #define ACTHD_I965 0x02074 328 #define HWS_PGA 0x02080 329 #define HWS_ADDRESS_MASK 0xfffff000 330 #define HWS_START_ADDRESS_SHIFT 4 331 #define PWRCTXA 0x2088 /* 965GM+ only */ 332 #define PWRCTX_EN (1<<0) 333 #define IPEIR 0x02088 334 #define IPEHR 0x0208c 335 #define INSTDONE 0x02090 336 #define NOPID 0x02094 337 #define HWSTAM 0x02098 338 #define VCS_INSTDONE 0x1206C 339 #define VCS_IPEIR 0x12064 340 #define VCS_IPEHR 0x12068 341 #define VCS_ACTHD 0x12074 342 #define BCS_INSTDONE 0x2206C 343 #define BCS_IPEIR 0x22064 344 #define BCS_IPEHR 0x22068 345 #define BCS_ACTHD 0x22074 346 347 #define ERROR_GEN6 0x040a0 348 349 /* GM45+ chicken bits -- debug workaround bits that may be required 350 * for various sorts of correct behavior. The top 16 bits of each are 351 * the enables for writing to the corresponding low bit. 352 */ 353 #define _3D_CHICKEN 0x02084 354 #define _3D_CHICKEN2 0x0208c 355 /* Disables pipelining of read flushes past the SF-WIZ interface. 356 * Required on all Ironlake steppings according to the B-Spec, but the 357 * particular danger of not doing so is not specified. 358 */ 359 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 360 #define _3D_CHICKEN3 0x02090 361 362 #define MI_MODE 0x0209c 363 # define VS_TIMER_DISPATCH (1 << 6) 364 # define MI_FLUSH_ENABLE (1 << 11) 365 366 #define GFX_MODE 0x02520 367 #define GFX_RUN_LIST_ENABLE (1<<15) 368 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 369 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 370 #define GFX_REPLAY_MODE (1<<11) 371 #define GFX_PSMI_GRANULARITY (1<<10) 372 #define GFX_PPGTT_ENABLE (1<<9) 373 374 #define SCPD0 0x0209c /* 915+ only */ 375 #define IER 0x020a0 376 #define IIR 0x020a4 377 #define IMR 0x020a8 378 #define ISR 0x020ac 379 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 380 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 381 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 382 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 383 #define I915_HWB_OOM_INTERRUPT (1<<13) 384 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 385 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 386 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 387 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 388 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 389 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 390 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 391 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 392 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 393 #define I915_DEBUG_INTERRUPT (1<<2) 394 #define I915_USER_INTERRUPT (1<<1) 395 #define I915_ASLE_INTERRUPT (1<<0) 396 #define I915_BSD_USER_INTERRUPT (1<<25) 397 #define EIR 0x020b0 398 #define EMR 0x020b4 399 #define ESR 0x020b8 400 #define GM45_ERROR_PAGE_TABLE (1<<5) 401 #define GM45_ERROR_MEM_PRIV (1<<4) 402 #define I915_ERROR_PAGE_TABLE (1<<4) 403 #define GM45_ERROR_CP_PRIV (1<<3) 404 #define I915_ERROR_MEMORY_REFRESH (1<<1) 405 #define I915_ERROR_INSTRUCTION (1<<0) 406 #define INSTPM 0x020c0 407 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 408 #define ACTHD 0x020c8 409 #define FW_BLC 0x020d8 410 #define FW_BLC2 0x020dc 411 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 412 #define FW_BLC_SELF_EN_MASK (1<<31) 413 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 414 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 415 #define MM_BURST_LENGTH 0x00700000 416 #define MM_FIFO_WATERMARK 0x0001F000 417 #define LM_BURST_LENGTH 0x00000700 418 #define LM_FIFO_WATERMARK 0x0000001F 419 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 420 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ 421 422 /* Make render/texture TLB fetches lower priorty than associated data 423 * fetches. This is not turned on by default 424 */ 425 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 426 427 /* Isoch request wait on GTT enable (Display A/B/C streams). 428 * Make isoch requests stall on the TLB update. May cause 429 * display underruns (test mode only) 430 */ 431 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 432 433 /* Block grant count for isoch requests when block count is 434 * set to a finite value. 435 */ 436 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 437 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 438 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 439 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 440 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 441 442 /* Enable render writes to complete in C2/C3/C4 power states. 443 * If this isn't enabled, render writes are prevented in low 444 * power states. That seems bad to me. 445 */ 446 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 447 448 /* This acknowledges an async flip immediately instead 449 * of waiting for 2TLB fetches. 450 */ 451 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 452 453 /* Enables non-sequential data reads through arbiter 454 */ 455 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 456 457 /* Disable FSB snooping of cacheable write cycles from binner/render 458 * command stream 459 */ 460 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 461 462 /* Arbiter time slice for non-isoch streams */ 463 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 464 #define MI_ARB_TIME_SLICE_1 (0 << 5) 465 #define MI_ARB_TIME_SLICE_2 (1 << 5) 466 #define MI_ARB_TIME_SLICE_4 (2 << 5) 467 #define MI_ARB_TIME_SLICE_6 (3 << 5) 468 #define MI_ARB_TIME_SLICE_8 (4 << 5) 469 #define MI_ARB_TIME_SLICE_10 (5 << 5) 470 #define MI_ARB_TIME_SLICE_14 (6 << 5) 471 #define MI_ARB_TIME_SLICE_16 (7 << 5) 472 473 /* Low priority grace period page size */ 474 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 475 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 476 477 /* Disable display A/B trickle feed */ 478 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 479 480 /* Set display plane priority */ 481 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 482 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 483 484 #define CACHE_MODE_0 0x02120 /* 915+ only */ 485 #define CM0_MASK_SHIFT 16 486 #define CM0_IZ_OPT_DISABLE (1<<6) 487 #define CM0_ZR_OPT_DISABLE (1<<5) 488 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 489 #define CM0_COLOR_EVICT_DISABLE (1<<3) 490 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 491 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 492 #define BB_ADDR 0x02140 /* 8 bytes */ 493 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 494 #define ECOSKPD 0x021d0 495 #define ECO_GATING_CX_ONLY (1<<3) 496 #define ECO_FLIP_DONE (1<<0) 497 498 /* GEN6 interrupt control */ 499 #define GEN6_RENDER_HWSTAM 0x2098 500 #define GEN6_RENDER_IMR 0x20a8 501 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 502 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 503 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 504 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 505 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 506 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 507 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 508 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 509 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 510 511 #define GEN6_BLITTER_HWSTAM 0x22098 512 #define GEN6_BLITTER_IMR 0x220a8 513 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 514 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 515 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 516 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 517 518 #define GEN6_BLITTER_ECOSKPD 0x221d0 519 #define GEN6_BLITTER_LOCK_SHIFT 16 520 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 521 522 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 523 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 524 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) 525 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 526 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 527 528 #define GEN6_BSD_IMR 0x120a8 529 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 530 531 #define GEN6_BSD_RNCID 0x12198 532 533 /* 534 * Framebuffer compression (915+ only) 535 */ 536 537 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 538 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 539 #define FBC_CONTROL 0x03208 540 #define FBC_CTL_EN (1<<31) 541 #define FBC_CTL_PERIODIC (1<<30) 542 #define FBC_CTL_INTERVAL_SHIFT (16) 543 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 544 #define FBC_CTL_C3_IDLE (1<<13) 545 #define FBC_CTL_STRIDE_SHIFT (5) 546 #define FBC_CTL_FENCENO (1<<0) 547 #define FBC_COMMAND 0x0320c 548 #define FBC_CMD_COMPRESS (1<<0) 549 #define FBC_STATUS 0x03210 550 #define FBC_STAT_COMPRESSING (1<<31) 551 #define FBC_STAT_COMPRESSED (1<<30) 552 #define FBC_STAT_MODIFIED (1<<29) 553 #define FBC_STAT_CURRENT_LINE (1<<0) 554 #define FBC_CONTROL2 0x03214 555 #define FBC_CTL_FENCE_DBL (0<<4) 556 #define FBC_CTL_IDLE_IMM (0<<2) 557 #define FBC_CTL_IDLE_FULL (1<<2) 558 #define FBC_CTL_IDLE_LINE (2<<2) 559 #define FBC_CTL_IDLE_DEBUG (3<<2) 560 #define FBC_CTL_CPU_FENCE (1<<1) 561 #define FBC_CTL_PLANEA (0<<0) 562 #define FBC_CTL_PLANEB (1<<0) 563 #define FBC_FENCE_OFF 0x0321b 564 #define FBC_TAG 0x03300 565 566 #define FBC_LL_SIZE (1536) 567 568 /* Framebuffer compression for GM45+ */ 569 #define DPFC_CB_BASE 0x3200 570 #define DPFC_CONTROL 0x3208 571 #define DPFC_CTL_EN (1<<31) 572 #define DPFC_CTL_PLANEA (0<<30) 573 #define DPFC_CTL_PLANEB (1<<30) 574 #define DPFC_CTL_FENCE_EN (1<<29) 575 #define DPFC_SR_EN (1<<10) 576 #define DPFC_CTL_LIMIT_1X (0<<6) 577 #define DPFC_CTL_LIMIT_2X (1<<6) 578 #define DPFC_CTL_LIMIT_4X (2<<6) 579 #define DPFC_RECOMP_CTL 0x320c 580 #define DPFC_RECOMP_STALL_EN (1<<27) 581 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 582 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 583 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 584 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 585 #define DPFC_STATUS 0x3210 586 #define DPFC_INVAL_SEG_SHIFT (16) 587 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 588 #define DPFC_COMP_SEG_SHIFT (0) 589 #define DPFC_COMP_SEG_MASK (0x000003ff) 590 #define DPFC_STATUS2 0x3214 591 #define DPFC_FENCE_YOFF 0x3218 592 #define DPFC_CHICKEN 0x3224 593 #define DPFC_HT_MODIFY (1<<31) 594 595 /* Framebuffer compression for Ironlake */ 596 #define ILK_DPFC_CB_BASE 0x43200 597 #define ILK_DPFC_CONTROL 0x43208 598 /* The bit 28-8 is reserved */ 599 #define DPFC_RESERVED (0x1FFFFF00) 600 #define ILK_DPFC_RECOMP_CTL 0x4320c 601 #define ILK_DPFC_STATUS 0x43210 602 #define ILK_DPFC_FENCE_YOFF 0x43218 603 #define ILK_DPFC_CHICKEN 0x43224 604 #define ILK_FBC_RT_BASE 0x2128 605 #define ILK_FBC_RT_VALID (1<<0) 606 607 #define ILK_DISPLAY_CHICKEN1 0x42000 608 #define ILK_FBCQ_DIS (1<<22) 609 #define ILK_PABSTRETCH_DIS (1<<21) 610 611 612 /* 613 * Framebuffer compression for Sandybridge 614 * 615 * The following two registers are of type GTTMMADR 616 */ 617 #define SNB_DPFC_CTL_SA 0x100100 618 #define SNB_CPU_FENCE_ENABLE (1<<29) 619 #define DPFC_CPU_FENCE_OFFSET 0x100104 620 621 622 /* 623 * GPIO regs 624 */ 625 #define GPIOA 0x5010 626 #define GPIOB 0x5014 627 #define GPIOC 0x5018 628 #define GPIOD 0x501c 629 #define GPIOE 0x5020 630 #define GPIOF 0x5024 631 #define GPIOG 0x5028 632 #define GPIOH 0x502c 633 # define GPIO_CLOCK_DIR_MASK (1 << 0) 634 # define GPIO_CLOCK_DIR_IN (0 << 1) 635 # define GPIO_CLOCK_DIR_OUT (1 << 1) 636 # define GPIO_CLOCK_VAL_MASK (1 << 2) 637 # define GPIO_CLOCK_VAL_OUT (1 << 3) 638 # define GPIO_CLOCK_VAL_IN (1 << 4) 639 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 640 # define GPIO_DATA_DIR_MASK (1 << 8) 641 # define GPIO_DATA_DIR_IN (0 << 9) 642 # define GPIO_DATA_DIR_OUT (1 << 9) 643 # define GPIO_DATA_VAL_MASK (1 << 10) 644 # define GPIO_DATA_VAL_OUT (1 << 11) 645 # define GPIO_DATA_VAL_IN (1 << 12) 646 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 647 648 #define GMBUS0 0x5100 /* clock/port select */ 649 #define GMBUS_RATE_100KHZ (0<<8) 650 #define GMBUS_RATE_50KHZ (1<<8) 651 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 652 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 653 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 654 #define GMBUS_PORT_DISABLED 0 655 #define GMBUS_PORT_SSC 1 656 #define GMBUS_PORT_VGADDC 2 657 #define GMBUS_PORT_PANEL 3 658 #define GMBUS_PORT_DPC 4 /* HDMIC */ 659 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 660 /* 6 reserved */ 661 #define GMBUS_PORT_DPD 7 /* HDMID */ 662 #define GMBUS_NUM_PORTS 8 663 #define GMBUS1 0x5104 /* command/status */ 664 #define GMBUS_SW_CLR_INT (1<<31) 665 #define GMBUS_SW_RDY (1<<30) 666 #define GMBUS_ENT (1<<29) /* enable timeout */ 667 #define GMBUS_CYCLE_NONE (0<<25) 668 #define GMBUS_CYCLE_WAIT (1<<25) 669 #define GMBUS_CYCLE_INDEX (2<<25) 670 #define GMBUS_CYCLE_STOP (4<<25) 671 #define GMBUS_BYTE_COUNT_SHIFT 16 672 #define GMBUS_SLAVE_INDEX_SHIFT 8 673 #define GMBUS_SLAVE_ADDR_SHIFT 1 674 #define GMBUS_SLAVE_READ (1<<0) 675 #define GMBUS_SLAVE_WRITE (0<<0) 676 #define GMBUS2 0x5108 /* status */ 677 #define GMBUS_INUSE (1<<15) 678 #define GMBUS_HW_WAIT_PHASE (1<<14) 679 #define GMBUS_STALL_TIMEOUT (1<<13) 680 #define GMBUS_INT (1<<12) 681 #define GMBUS_HW_RDY (1<<11) 682 #define GMBUS_SATOER (1<<10) 683 #define GMBUS_ACTIVE (1<<9) 684 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 685 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 686 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 687 #define GMBUS_NAK_EN (1<<3) 688 #define GMBUS_IDLE_EN (1<<2) 689 #define GMBUS_HW_WAIT_EN (1<<1) 690 #define GMBUS_HW_RDY_EN (1<<0) 691 #define GMBUS5 0x5120 /* byte index */ 692 #define GMBUS_2BYTE_INDEX_EN (1<<31) 693 694 /* 695 * Clock control & power management 696 */ 697 698 #define VGA0 0x6000 699 #define VGA1 0x6004 700 #define VGA_PD 0x6010 701 #define VGA0_PD_P2_DIV_4 (1 << 7) 702 #define VGA0_PD_P1_DIV_2 (1 << 5) 703 #define VGA0_PD_P1_SHIFT 0 704 #define VGA0_PD_P1_MASK (0x1f << 0) 705 #define VGA1_PD_P2_DIV_4 (1 << 15) 706 #define VGA1_PD_P1_DIV_2 (1 << 13) 707 #define VGA1_PD_P1_SHIFT 8 708 #define VGA1_PD_P1_MASK (0x1f << 8) 709 #define DPLL_A 0x06014 710 #define DPLL_B 0x06018 711 #define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B) 712 #define DPLL_VCO_ENABLE (1 << 31) 713 #define DPLL_DVO_HIGH_SPEED (1 << 30) 714 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 715 #define DPLL_VGA_MODE_DIS (1 << 28) 716 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 717 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 718 #define DPLL_MODE_MASK (3 << 26) 719 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 720 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 721 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 722 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 723 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 724 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 725 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 726 727 #define SRX_INDEX 0x3c4 728 #define SRX_DATA 0x3c5 729 #define SR01 1 730 #define SR01_SCREEN_OFF (1<<5) 731 732 #define PPCR 0x61204 733 #define PPCR_ON (1<<0) 734 735 #define DVOB 0x61140 736 #define DVOB_ON (1<<31) 737 #define DVOC 0x61160 738 #define DVOC_ON (1<<31) 739 #define LVDS 0x61180 740 #define LVDS_ON (1<<31) 741 742 /* Scratch pad debug 0 reg: 743 */ 744 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 745 /* 746 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 747 * this field (only one bit may be set). 748 */ 749 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 750 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 751 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 752 /* i830, required in DVO non-gang */ 753 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 754 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 755 #define PLL_REF_INPUT_DREFCLK (0 << 13) 756 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 757 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 758 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 759 #define PLL_REF_INPUT_MASK (3 << 13) 760 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 761 /* Ironlake */ 762 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 763 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 764 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 765 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 766 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 767 768 /* 769 * Parallel to Serial Load Pulse phase selection. 770 * Selects the phase for the 10X DPLL clock for the PCIe 771 * digital display port. The range is 4 to 13; 10 or more 772 * is just a flip delay. The default is 6 773 */ 774 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 775 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 776 /* 777 * SDVO multiplier for 945G/GM. Not used on 965. 778 */ 779 #define SDVO_MULTIPLIER_MASK 0x000000ff 780 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 781 #define SDVO_MULTIPLIER_SHIFT_VGA 0 782 #define DPLL_A_MD 0x0601c /* 965+ only */ 783 /* 784 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 785 * 786 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 787 */ 788 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 789 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 790 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 791 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 792 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 793 /* 794 * SDVO/UDI pixel multiplier. 795 * 796 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 797 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 798 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 799 * dummy bytes in the datastream at an increased clock rate, with both sides of 800 * the link knowing how many bytes are fill. 801 * 802 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 803 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 804 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 805 * through an SDVO command. 806 * 807 * This register field has values of multiplication factor minus 1, with 808 * a maximum multiplier of 5 for SDVO. 809 */ 810 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 811 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 812 /* 813 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 814 * This best be set to the default value (3) or the CRT won't work. No, 815 * I don't entirely understand what this does... 816 */ 817 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 818 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 819 #define DPLL_B_MD 0x06020 /* 965+ only */ 820 #define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD) 821 #define FPA0 0x06040 822 #define FPA1 0x06044 823 #define FPB0 0x06048 824 #define FPB1 0x0604c 825 #define FP0(pipe) _PIPE(pipe, FPA0, FPB0) 826 #define FP1(pipe) _PIPE(pipe, FPA1, FPB1) 827 #define FP_N_DIV_MASK 0x003f0000 828 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 829 #define FP_N_DIV_SHIFT 16 830 #define FP_M1_DIV_MASK 0x00003f00 831 #define FP_M1_DIV_SHIFT 8 832 #define FP_M2_DIV_MASK 0x0000003f 833 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 834 #define FP_M2_DIV_SHIFT 0 835 #define DPLL_TEST 0x606c 836 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 837 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 838 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 839 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 840 #define DPLLB_TEST_N_BYPASS (1 << 19) 841 #define DPLLB_TEST_M_BYPASS (1 << 18) 842 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 843 #define DPLLA_TEST_N_BYPASS (1 << 3) 844 #define DPLLA_TEST_M_BYPASS (1 << 2) 845 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 846 #define D_STATE 0x6104 847 #define DSTATE_GFX_RESET_I830 (1<<6) 848 #define DSTATE_PLL_D3_OFF (1<<3) 849 #define DSTATE_GFX_CLOCK_GATING (1<<1) 850 #define DSTATE_DOT_CLOCK_GATING (1<<0) 851 #define DSPCLK_GATE_D 0x6200 852 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 853 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 854 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 855 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 856 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 857 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 858 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 859 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 860 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 861 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 862 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 863 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 864 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 865 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 866 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 867 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 868 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 869 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 870 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 871 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 872 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 873 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 874 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 875 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 876 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 877 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 878 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 879 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 880 /** 881 * This bit must be set on the 830 to prevent hangs when turning off the 882 * overlay scaler. 883 */ 884 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 885 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 886 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 887 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 888 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 889 890 #define RENCLK_GATE_D1 0x6204 891 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 892 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 893 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 894 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 895 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 896 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 897 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 898 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 899 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 900 /** This bit must be unset on 855,865 */ 901 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 902 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 903 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 904 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 905 /** This bit must be set on 855,865. */ 906 # define SV_CLOCK_GATE_DISABLE (1 << 0) 907 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 908 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 909 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 910 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 911 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 912 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 913 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 914 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 915 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 916 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 917 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 918 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 919 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 920 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 921 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 922 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 923 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 924 925 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 926 /** This bit must always be set on 965G/965GM */ 927 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 928 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 929 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 930 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 931 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 932 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 933 /** This bit must always be set on 965G */ 934 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 935 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 936 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 937 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 938 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 939 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 940 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 941 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 942 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 943 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 944 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 945 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 946 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 947 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 948 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 949 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 950 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 951 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 952 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 953 954 #define RENCLK_GATE_D2 0x6208 955 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 956 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 957 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 958 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 959 #define DEUC 0x6214 /* CRL only */ 960 961 /* 962 * Palette regs 963 */ 964 965 #define PALETTE_A 0x0a000 966 #define PALETTE_B 0x0a800 967 968 /* MCH MMIO space */ 969 970 /* 971 * MCHBAR mirror. 972 * 973 * This mirrors the MCHBAR MMIO space whose location is determined by 974 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 975 * every way. It is not accessible from the CP register read instructions. 976 * 977 */ 978 #define MCHBAR_MIRROR_BASE 0x10000 979 980 #define MCHBAR_MIRROR_BASE_SNB 0x140000 981 982 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 983 #define DCC 0x10200 984 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 985 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 986 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 987 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 988 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 989 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 990 991 /** Pineview MCH register contains DDR3 setting */ 992 #define CSHRDDR3CTL 0x101a8 993 #define CSHRDDR3CTL_DDR3 (1 << 2) 994 995 /** 965 MCH register controlling DRAM channel configuration */ 996 #define C0DRB3 0x10206 997 #define C1DRB3 0x10606 998 999 /* Clocking configuration register */ 1000 #define CLKCFG 0x10c00 1001 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1002 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1003 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1004 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1005 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1006 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1007 /* Note, below two are guess */ 1008 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1009 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1010 #define CLKCFG_FSB_MASK (7 << 0) 1011 #define CLKCFG_MEM_533 (1 << 4) 1012 #define CLKCFG_MEM_667 (2 << 4) 1013 #define CLKCFG_MEM_800 (3 << 4) 1014 #define CLKCFG_MEM_MASK (7 << 4) 1015 1016 #define TSC1 0x11001 1017 #define TSE (1<<0) 1018 #define TR1 0x11006 1019 #define TSFS 0x11020 1020 #define TSFS_SLOPE_MASK 0x0000ff00 1021 #define TSFS_SLOPE_SHIFT 8 1022 #define TSFS_INTR_MASK 0x000000ff 1023 1024 #define CRSTANDVID 0x11100 1025 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1026 #define PXVFREQ_PX_MASK 0x7f000000 1027 #define PXVFREQ_PX_SHIFT 24 1028 #define VIDFREQ_BASE 0x11110 1029 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1030 #define VIDFREQ2 0x11114 1031 #define VIDFREQ3 0x11118 1032 #define VIDFREQ4 0x1111c 1033 #define VIDFREQ_P0_MASK 0x1f000000 1034 #define VIDFREQ_P0_SHIFT 24 1035 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1036 #define VIDFREQ_P0_CSCLK_SHIFT 20 1037 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1038 #define VIDFREQ_P0_CRCLK_SHIFT 16 1039 #define VIDFREQ_P1_MASK 0x00001f00 1040 #define VIDFREQ_P1_SHIFT 8 1041 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1042 #define VIDFREQ_P1_CSCLK_SHIFT 4 1043 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1044 #define INTTOEXT_BASE_ILK 0x11300 1045 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1046 #define INTTOEXT_MAP3_SHIFT 24 1047 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1048 #define INTTOEXT_MAP2_SHIFT 16 1049 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1050 #define INTTOEXT_MAP1_SHIFT 8 1051 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1052 #define INTTOEXT_MAP0_SHIFT 0 1053 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1054 #define MEMSWCTL 0x11170 /* Ironlake only */ 1055 #define MEMCTL_CMD_MASK 0xe000 1056 #define MEMCTL_CMD_SHIFT 13 1057 #define MEMCTL_CMD_RCLK_OFF 0 1058 #define MEMCTL_CMD_RCLK_ON 1 1059 #define MEMCTL_CMD_CHFREQ 2 1060 #define MEMCTL_CMD_CHVID 3 1061 #define MEMCTL_CMD_VMMOFF 4 1062 #define MEMCTL_CMD_VMMON 5 1063 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1064 when command complete */ 1065 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1066 #define MEMCTL_FREQ_SHIFT 8 1067 #define MEMCTL_SFCAVM (1<<7) 1068 #define MEMCTL_TGT_VID_MASK 0x007f 1069 #define MEMIHYST 0x1117c 1070 #define MEMINTREN 0x11180 /* 16 bits */ 1071 #define MEMINT_RSEXIT_EN (1<<8) 1072 #define MEMINT_CX_SUPR_EN (1<<7) 1073 #define MEMINT_CONT_BUSY_EN (1<<6) 1074 #define MEMINT_AVG_BUSY_EN (1<<5) 1075 #define MEMINT_EVAL_CHG_EN (1<<4) 1076 #define MEMINT_MON_IDLE_EN (1<<3) 1077 #define MEMINT_UP_EVAL_EN (1<<2) 1078 #define MEMINT_DOWN_EVAL_EN (1<<1) 1079 #define MEMINT_SW_CMD_EN (1<<0) 1080 #define MEMINTRSTR 0x11182 /* 16 bits */ 1081 #define MEM_RSEXIT_MASK 0xc000 1082 #define MEM_RSEXIT_SHIFT 14 1083 #define MEM_CONT_BUSY_MASK 0x3000 1084 #define MEM_CONT_BUSY_SHIFT 12 1085 #define MEM_AVG_BUSY_MASK 0x0c00 1086 #define MEM_AVG_BUSY_SHIFT 10 1087 #define MEM_EVAL_CHG_MASK 0x0300 1088 #define MEM_EVAL_BUSY_SHIFT 8 1089 #define MEM_MON_IDLE_MASK 0x00c0 1090 #define MEM_MON_IDLE_SHIFT 6 1091 #define MEM_UP_EVAL_MASK 0x0030 1092 #define MEM_UP_EVAL_SHIFT 4 1093 #define MEM_DOWN_EVAL_MASK 0x000c 1094 #define MEM_DOWN_EVAL_SHIFT 2 1095 #define MEM_SW_CMD_MASK 0x0003 1096 #define MEM_INT_STEER_GFX 0 1097 #define MEM_INT_STEER_CMR 1 1098 #define MEM_INT_STEER_SMI 2 1099 #define MEM_INT_STEER_SCI 3 1100 #define MEMINTRSTS 0x11184 1101 #define MEMINT_RSEXIT (1<<7) 1102 #define MEMINT_CONT_BUSY (1<<6) 1103 #define MEMINT_AVG_BUSY (1<<5) 1104 #define MEMINT_EVAL_CHG (1<<4) 1105 #define MEMINT_MON_IDLE (1<<3) 1106 #define MEMINT_UP_EVAL (1<<2) 1107 #define MEMINT_DOWN_EVAL (1<<1) 1108 #define MEMINT_SW_CMD (1<<0) 1109 #define MEMMODECTL 0x11190 1110 #define MEMMODE_BOOST_EN (1<<31) 1111 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1112 #define MEMMODE_BOOST_FREQ_SHIFT 24 1113 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1114 #define MEMMODE_IDLE_MODE_SHIFT 16 1115 #define MEMMODE_IDLE_MODE_EVAL 0 1116 #define MEMMODE_IDLE_MODE_CONT 1 1117 #define MEMMODE_HWIDLE_EN (1<<15) 1118 #define MEMMODE_SWMODE_EN (1<<14) 1119 #define MEMMODE_RCLK_GATE (1<<13) 1120 #define MEMMODE_HW_UPDATE (1<<12) 1121 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1122 #define MEMMODE_FSTART_SHIFT 8 1123 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1124 #define MEMMODE_FMAX_SHIFT 4 1125 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1126 #define RCBMAXAVG 0x1119c 1127 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1128 #define SWMEMCMD_RENDER_OFF (0 << 13) 1129 #define SWMEMCMD_RENDER_ON (1 << 13) 1130 #define SWMEMCMD_SWFREQ (2 << 13) 1131 #define SWMEMCMD_TARVID (3 << 13) 1132 #define SWMEMCMD_VRM_OFF (4 << 13) 1133 #define SWMEMCMD_VRM_ON (5 << 13) 1134 #define CMDSTS (1<<12) 1135 #define SFCAVM (1<<11) 1136 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1137 #define SWFREQ_SHIFT 7 1138 #define TARVID_MASK 0x001f 1139 #define MEMSTAT_CTG 0x111a0 1140 #define RCBMINAVG 0x111a0 1141 #define RCUPEI 0x111b0 1142 #define RCDNEI 0x111b4 1143 #define RSTDBYCTL 0x111b8 1144 #define RS1EN (1<<31) 1145 #define RS2EN (1<<30) 1146 #define RS3EN (1<<29) 1147 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1148 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1149 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1150 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1151 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1152 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1153 #define RSX_STATUS_MASK (7<<20) 1154 #define RSX_STATUS_ON (0<<20) 1155 #define RSX_STATUS_RC1 (1<<20) 1156 #define RSX_STATUS_RC1E (2<<20) 1157 #define RSX_STATUS_RS1 (3<<20) 1158 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1159 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1160 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1161 #define RSX_STATUS_RSVD2 (7<<20) 1162 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1163 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1164 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1165 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1166 #define RS1CONTSAV_MASK (3<<14) 1167 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1168 #define RS1CONTSAV_RSVD (1<<14) 1169 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1170 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1171 #define NORMSLEXLAT_MASK (3<<12) 1172 #define SLOW_RS123 (0<<12) 1173 #define SLOW_RS23 (1<<12) 1174 #define SLOW_RS3 (2<<12) 1175 #define NORMAL_RS123 (3<<12) 1176 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1177 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1178 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1179 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1180 #define RS_CSTATE_MASK (3<<4) 1181 #define RS_CSTATE_C367_RS1 (0<<4) 1182 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1183 #define RS_CSTATE_RSVD (2<<4) 1184 #define RS_CSTATE_C367_RS2 (3<<4) 1185 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1186 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1187 #define VIDCTL 0x111c0 1188 #define VIDSTS 0x111c8 1189 #define VIDSTART 0x111cc /* 8 bits */ 1190 #define MEMSTAT_ILK 0x111f8 1191 #define MEMSTAT_VID_MASK 0x7f00 1192 #define MEMSTAT_VID_SHIFT 8 1193 #define MEMSTAT_PSTATE_MASK 0x00f8 1194 #define MEMSTAT_PSTATE_SHIFT 3 1195 #define MEMSTAT_MON_ACTV (1<<2) 1196 #define MEMSTAT_SRC_CTL_MASK 0x0003 1197 #define MEMSTAT_SRC_CTL_CORE 0 1198 #define MEMSTAT_SRC_CTL_TRB 1 1199 #define MEMSTAT_SRC_CTL_THM 2 1200 #define MEMSTAT_SRC_CTL_STDBY 3 1201 #define RCPREVBSYTUPAVG 0x113b8 1202 #define RCPREVBSYTDNAVG 0x113bc 1203 #define PMMISC 0x11214 1204 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1205 #define SDEW 0x1124c 1206 #define CSIEW0 0x11250 1207 #define CSIEW1 0x11254 1208 #define CSIEW2 0x11258 1209 #define PEW 0x1125c 1210 #define DEW 0x11270 1211 #define MCHAFE 0x112c0 1212 #define CSIEC 0x112e0 1213 #define DMIEC 0x112e4 1214 #define DDREC 0x112e8 1215 #define PEG0EC 0x112ec 1216 #define PEG1EC 0x112f0 1217 #define GFXEC 0x112f4 1218 #define RPPREVBSYTUPAVG 0x113b8 1219 #define RPPREVBSYTDNAVG 0x113bc 1220 #define ECR 0x11600 1221 #define ECR_GPFE (1<<31) 1222 #define ECR_IMONE (1<<30) 1223 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1224 #define OGW0 0x11608 1225 #define OGW1 0x1160c 1226 #define EG0 0x11610 1227 #define EG1 0x11614 1228 #define EG2 0x11618 1229 #define EG3 0x1161c 1230 #define EG4 0x11620 1231 #define EG5 0x11624 1232 #define EG6 0x11628 1233 #define EG7 0x1162c 1234 #define PXW 0x11664 1235 #define PXWL 0x11680 1236 #define LCFUSE02 0x116c0 1237 #define LCFUSE_HIV_MASK 0x000000ff 1238 #define CSIPLL0 0x12c10 1239 #define DDRMPLL1 0X12c20 1240 #define PEG_BAND_GAP_DATA 0x14d68 1241 1242 #define GEN6_GT_PERF_STATUS 0x145948 1243 #define GEN6_RP_STATE_LIMITS 0x145994 1244 #define GEN6_RP_STATE_CAP 0x145998 1245 1246 /* 1247 * Logical Context regs 1248 */ 1249 #define CCID 0x2180 1250 #define CCID_EN (1<<0) 1251 /* 1252 * Overlay regs 1253 */ 1254 1255 #define OVADD 0x30000 1256 #define DOVSTA 0x30008 1257 #define OC_BUF (0x3<<20) 1258 #define OGAMC5 0x30010 1259 #define OGAMC4 0x30014 1260 #define OGAMC3 0x30018 1261 #define OGAMC2 0x3001c 1262 #define OGAMC1 0x30020 1263 #define OGAMC0 0x30024 1264 1265 /* 1266 * Display engine regs 1267 */ 1268 1269 /* Pipe A timing regs */ 1270 #define HTOTAL_A 0x60000 1271 #define HBLANK_A 0x60004 1272 #define HSYNC_A 0x60008 1273 #define VTOTAL_A 0x6000c 1274 #define VBLANK_A 0x60010 1275 #define VSYNC_A 0x60014 1276 #define PIPEASRC 0x6001c 1277 #define BCLRPAT_A 0x60020 1278 1279 /* Pipe B timing regs */ 1280 #define HTOTAL_B 0x61000 1281 #define HBLANK_B 0x61004 1282 #define HSYNC_B 0x61008 1283 #define VTOTAL_B 0x6100c 1284 #define VBLANK_B 0x61010 1285 #define VSYNC_B 0x61014 1286 #define PIPEBSRC 0x6101c 1287 #define BCLRPAT_B 0x61020 1288 1289 #define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B) 1290 #define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B) 1291 #define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B) 1292 #define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B) 1293 #define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B) 1294 #define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B) 1295 #define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B) 1296 1297 /* VGA port control */ 1298 #define ADPA 0x61100 1299 #define ADPA_DAC_ENABLE (1<<31) 1300 #define ADPA_DAC_DISABLE 0 1301 #define ADPA_PIPE_SELECT_MASK (1<<30) 1302 #define ADPA_PIPE_A_SELECT 0 1303 #define ADPA_PIPE_B_SELECT (1<<30) 1304 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1305 #define ADPA_SETS_HVPOLARITY 0 1306 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1307 #define ADPA_VSYNC_CNTL_ENABLE 0 1308 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1309 #define ADPA_HSYNC_CNTL_ENABLE 0 1310 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1311 #define ADPA_VSYNC_ACTIVE_LOW 0 1312 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1313 #define ADPA_HSYNC_ACTIVE_LOW 0 1314 #define ADPA_DPMS_MASK (~(3<<10)) 1315 #define ADPA_DPMS_ON (0<<10) 1316 #define ADPA_DPMS_SUSPEND (1<<10) 1317 #define ADPA_DPMS_STANDBY (2<<10) 1318 #define ADPA_DPMS_OFF (3<<10) 1319 1320 1321 /* Hotplug control (945+ only) */ 1322 #define PORT_HOTPLUG_EN 0x61110 1323 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1324 #define DPB_HOTPLUG_INT_EN (1 << 29) 1325 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1326 #define DPC_HOTPLUG_INT_EN (1 << 28) 1327 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1328 #define DPD_HOTPLUG_INT_EN (1 << 27) 1329 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1330 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1331 #define TV_HOTPLUG_INT_EN (1 << 18) 1332 #define CRT_HOTPLUG_INT_EN (1 << 9) 1333 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1334 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1335 /* must use period 64 on GM45 according to docs */ 1336 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1337 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1338 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1339 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1340 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1341 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1342 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1343 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1344 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1345 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1346 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1347 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1348 1349 #define PORT_HOTPLUG_STAT 0x61114 1350 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1351 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 1352 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1353 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 1354 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1355 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 1356 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1357 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1358 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1359 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1360 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1361 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1362 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1363 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1364 1365 /* SDVO port control */ 1366 #define SDVOB 0x61140 1367 #define SDVOC 0x61160 1368 #define SDVO_ENABLE (1 << 31) 1369 #define SDVO_PIPE_B_SELECT (1 << 30) 1370 #define SDVO_STALL_SELECT (1 << 29) 1371 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1372 /** 1373 * 915G/GM SDVO pixel multiplier. 1374 * 1375 * Programmed value is multiplier - 1, up to 5x. 1376 * 1377 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1378 */ 1379 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1380 #define SDVO_PORT_MULTIPLY_SHIFT 23 1381 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1382 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1383 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1384 #define SDVOC_GANG_MODE (1 << 16) 1385 #define SDVO_ENCODING_SDVO (0x0 << 10) 1386 #define SDVO_ENCODING_HDMI (0x2 << 10) 1387 /** Requird for HDMI operation */ 1388 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1389 #define SDVO_BORDER_ENABLE (1 << 7) 1390 #define SDVO_AUDIO_ENABLE (1 << 6) 1391 /** New with 965, default is to be set */ 1392 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1393 /** New with 965, default is to be set */ 1394 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1395 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1396 #define SDVO_DETECTED (1 << 2) 1397 /* Bits to be preserved when writing */ 1398 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1399 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1400 1401 /* DVO port control */ 1402 #define DVOA 0x61120 1403 #define DVOB 0x61140 1404 #define DVOC 0x61160 1405 #define DVO_ENABLE (1 << 31) 1406 #define DVO_PIPE_B_SELECT (1 << 30) 1407 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1408 #define DVO_PIPE_STALL (1 << 28) 1409 #define DVO_PIPE_STALL_TV (2 << 28) 1410 #define DVO_PIPE_STALL_MASK (3 << 28) 1411 #define DVO_USE_VGA_SYNC (1 << 15) 1412 #define DVO_DATA_ORDER_I740 (0 << 14) 1413 #define DVO_DATA_ORDER_FP (1 << 14) 1414 #define DVO_VSYNC_DISABLE (1 << 11) 1415 #define DVO_HSYNC_DISABLE (1 << 10) 1416 #define DVO_VSYNC_TRISTATE (1 << 9) 1417 #define DVO_HSYNC_TRISTATE (1 << 8) 1418 #define DVO_BORDER_ENABLE (1 << 7) 1419 #define DVO_DATA_ORDER_GBRG (1 << 6) 1420 #define DVO_DATA_ORDER_RGGB (0 << 6) 1421 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1422 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1423 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1424 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1425 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1426 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1427 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1428 #define DVO_PRESERVE_MASK (0x7<<24) 1429 #define DVOA_SRCDIM 0x61124 1430 #define DVOB_SRCDIM 0x61144 1431 #define DVOC_SRCDIM 0x61164 1432 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1433 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1434 1435 /* LVDS port control */ 1436 #define LVDS 0x61180 1437 /* 1438 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1439 * the DPLL semantics change when the LVDS is assigned to that pipe. 1440 */ 1441 #define LVDS_PORT_EN (1 << 31) 1442 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1443 #define LVDS_PIPEB_SELECT (1 << 30) 1444 /* LVDS dithering flag on 965/g4x platform */ 1445 #define LVDS_ENABLE_DITHER (1 << 25) 1446 /* Enable border for unscaled (or aspect-scaled) display */ 1447 #define LVDS_BORDER_ENABLE (1 << 15) 1448 /* 1449 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1450 * pixel. 1451 */ 1452 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1453 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1454 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1455 /* 1456 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1457 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1458 * on. 1459 */ 1460 #define LVDS_A3_POWER_MASK (3 << 6) 1461 #define LVDS_A3_POWER_DOWN (0 << 6) 1462 #define LVDS_A3_POWER_UP (3 << 6) 1463 /* 1464 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1465 * is set. 1466 */ 1467 #define LVDS_CLKB_POWER_MASK (3 << 4) 1468 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1469 #define LVDS_CLKB_POWER_UP (3 << 4) 1470 /* 1471 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1472 * setting for whether we are in dual-channel mode. The B3 pair will 1473 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1474 */ 1475 #define LVDS_B0B3_POWER_MASK (3 << 2) 1476 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1477 #define LVDS_B0B3_POWER_UP (3 << 2) 1478 1479 /* Video Data Island Packet control */ 1480 #define VIDEO_DIP_DATA 0x61178 1481 #define VIDEO_DIP_CTL 0x61170 1482 #define VIDEO_DIP_ENABLE (1 << 31) 1483 #define VIDEO_DIP_PORT_B (1 << 29) 1484 #define VIDEO_DIP_PORT_C (2 << 29) 1485 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1486 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1487 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1488 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1489 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1490 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1491 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1492 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1493 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1494 1495 /* Panel power sequencing */ 1496 #define PP_STATUS 0x61200 1497 #define PP_ON (1 << 31) 1498 /* 1499 * Indicates that all dependencies of the panel are on: 1500 * 1501 * - PLL enabled 1502 * - pipe enabled 1503 * - LVDS/DVOB/DVOC on 1504 */ 1505 #define PP_READY (1 << 30) 1506 #define PP_SEQUENCE_NONE (0 << 28) 1507 #define PP_SEQUENCE_ON (1 << 28) 1508 #define PP_SEQUENCE_OFF (2 << 28) 1509 #define PP_SEQUENCE_MASK 0x30000000 1510 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1511 #define PP_SEQUENCE_STATE_ON_IDLE (1 << 3) 1512 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1513 #define PP_CONTROL 0x61204 1514 #define POWER_TARGET_ON (1 << 0) 1515 #define PP_ON_DELAYS 0x61208 1516 #define PP_OFF_DELAYS 0x6120c 1517 #define PP_DIVISOR 0x61210 1518 1519 /* Panel fitting */ 1520 #define PFIT_CONTROL 0x61230 1521 #define PFIT_ENABLE (1 << 31) 1522 #define PFIT_PIPE_MASK (3 << 29) 1523 #define PFIT_PIPE_SHIFT 29 1524 #define VERT_INTERP_DISABLE (0 << 10) 1525 #define VERT_INTERP_BILINEAR (1 << 10) 1526 #define VERT_INTERP_MASK (3 << 10) 1527 #define VERT_AUTO_SCALE (1 << 9) 1528 #define HORIZ_INTERP_DISABLE (0 << 6) 1529 #define HORIZ_INTERP_BILINEAR (1 << 6) 1530 #define HORIZ_INTERP_MASK (3 << 6) 1531 #define HORIZ_AUTO_SCALE (1 << 5) 1532 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1533 #define PFIT_FILTER_FUZZY (0 << 24) 1534 #define PFIT_SCALING_AUTO (0 << 26) 1535 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1536 #define PFIT_SCALING_PILLAR (2 << 26) 1537 #define PFIT_SCALING_LETTER (3 << 26) 1538 #define PFIT_PGM_RATIOS 0x61234 1539 #define PFIT_VERT_SCALE_MASK 0xfff00000 1540 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1541 /* Pre-965 */ 1542 #define PFIT_VERT_SCALE_SHIFT 20 1543 #define PFIT_VERT_SCALE_MASK 0xfff00000 1544 #define PFIT_HORIZ_SCALE_SHIFT 4 1545 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1546 /* 965+ */ 1547 #define PFIT_VERT_SCALE_SHIFT_965 16 1548 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1549 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1550 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1551 1552 #define PFIT_AUTO_RATIOS 0x61238 1553 1554 /* Backlight control */ 1555 #define BLC_PWM_CTL 0x61254 1556 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1557 /* 1558 * This is the number of cycles out of the backlight modulation cycle for which 1559 * the backlight is on. 1560 * 1561 * This field must be no greater than the number of cycles in the complete 1562 * backlight modulation cycle. 1563 */ 1564 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1565 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1566 1567 #define BLC_HIST_CTL 0x61260 1568 1569 /* TV port control */ 1570 #define TV_CTL 0x68000 1571 /** Enables the TV encoder */ 1572 # define TV_ENC_ENABLE (1 << 31) 1573 /** Sources the TV encoder input from pipe B instead of A. */ 1574 # define TV_ENC_PIPEB_SELECT (1 << 30) 1575 /** Outputs composite video (DAC A only) */ 1576 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1577 /** Outputs SVideo video (DAC B/C) */ 1578 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1579 /** Outputs Component video (DAC A/B/C) */ 1580 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1581 /** Outputs Composite and SVideo (DAC A/B/C) */ 1582 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1583 # define TV_TRILEVEL_SYNC (1 << 21) 1584 /** Enables slow sync generation (945GM only) */ 1585 # define TV_SLOW_SYNC (1 << 20) 1586 /** Selects 4x oversampling for 480i and 576p */ 1587 # define TV_OVERSAMPLE_4X (0 << 18) 1588 /** Selects 2x oversampling for 720p and 1080i */ 1589 # define TV_OVERSAMPLE_2X (1 << 18) 1590 /** Selects no oversampling for 1080p */ 1591 # define TV_OVERSAMPLE_NONE (2 << 18) 1592 /** Selects 8x oversampling */ 1593 # define TV_OVERSAMPLE_8X (3 << 18) 1594 /** Selects progressive mode rather than interlaced */ 1595 # define TV_PROGRESSIVE (1 << 17) 1596 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1597 # define TV_PAL_BURST (1 << 16) 1598 /** Field for setting delay of Y compared to C */ 1599 # define TV_YC_SKEW_MASK (7 << 12) 1600 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1601 # define TV_ENC_SDP_FIX (1 << 11) 1602 /** 1603 * Enables a fix for the 915GM only. 1604 * 1605 * Not sure what it does. 1606 */ 1607 # define TV_ENC_C0_FIX (1 << 10) 1608 /** Bits that must be preserved by software */ 1609 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1610 # define TV_FUSE_STATE_MASK (3 << 4) 1611 /** Read-only state that reports all features enabled */ 1612 # define TV_FUSE_STATE_ENABLED (0 << 4) 1613 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1614 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1615 /** Read-only state that reports that TV-out is disabled in hardware. */ 1616 # define TV_FUSE_STATE_DISABLED (2 << 4) 1617 /** Normal operation */ 1618 # define TV_TEST_MODE_NORMAL (0 << 0) 1619 /** Encoder test pattern 1 - combo pattern */ 1620 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1621 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1622 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1623 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1624 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1625 /** Encoder test pattern 4 - random noise */ 1626 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1627 /** Encoder test pattern 5 - linear color ramps */ 1628 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1629 /** 1630 * This test mode forces the DACs to 50% of full output. 1631 * 1632 * This is used for load detection in combination with TVDAC_SENSE_MASK 1633 */ 1634 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1635 # define TV_TEST_MODE_MASK (7 << 0) 1636 1637 #define TV_DAC 0x68004 1638 # define TV_DAC_SAVE 0x00ffff00 1639 /** 1640 * Reports that DAC state change logic has reported change (RO). 1641 * 1642 * This gets cleared when TV_DAC_STATE_EN is cleared 1643 */ 1644 # define TVDAC_STATE_CHG (1 << 31) 1645 # define TVDAC_SENSE_MASK (7 << 28) 1646 /** Reports that DAC A voltage is above the detect threshold */ 1647 # define TVDAC_A_SENSE (1 << 30) 1648 /** Reports that DAC B voltage is above the detect threshold */ 1649 # define TVDAC_B_SENSE (1 << 29) 1650 /** Reports that DAC C voltage is above the detect threshold */ 1651 # define TVDAC_C_SENSE (1 << 28) 1652 /** 1653 * Enables DAC state detection logic, for load-based TV detection. 1654 * 1655 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1656 * to off, for load detection to work. 1657 */ 1658 # define TVDAC_STATE_CHG_EN (1 << 27) 1659 /** Sets the DAC A sense value to high */ 1660 # define TVDAC_A_SENSE_CTL (1 << 26) 1661 /** Sets the DAC B sense value to high */ 1662 # define TVDAC_B_SENSE_CTL (1 << 25) 1663 /** Sets the DAC C sense value to high */ 1664 # define TVDAC_C_SENSE_CTL (1 << 24) 1665 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1666 # define DAC_CTL_OVERRIDE (1 << 7) 1667 /** Sets the slew rate. Must be preserved in software */ 1668 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1669 # define DAC_A_1_3_V (0 << 4) 1670 # define DAC_A_1_1_V (1 << 4) 1671 # define DAC_A_0_7_V (2 << 4) 1672 # define DAC_A_MASK (3 << 4) 1673 # define DAC_B_1_3_V (0 << 2) 1674 # define DAC_B_1_1_V (1 << 2) 1675 # define DAC_B_0_7_V (2 << 2) 1676 # define DAC_B_MASK (3 << 2) 1677 # define DAC_C_1_3_V (0 << 0) 1678 # define DAC_C_1_1_V (1 << 0) 1679 # define DAC_C_0_7_V (2 << 0) 1680 # define DAC_C_MASK (3 << 0) 1681 1682 /** 1683 * CSC coefficients are stored in a floating point format with 9 bits of 1684 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1685 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1686 * -1 (0x3) being the only legal negative value. 1687 */ 1688 #define TV_CSC_Y 0x68010 1689 # define TV_RY_MASK 0x07ff0000 1690 # define TV_RY_SHIFT 16 1691 # define TV_GY_MASK 0x00000fff 1692 # define TV_GY_SHIFT 0 1693 1694 #define TV_CSC_Y2 0x68014 1695 # define TV_BY_MASK 0x07ff0000 1696 # define TV_BY_SHIFT 16 1697 /** 1698 * Y attenuation for component video. 1699 * 1700 * Stored in 1.9 fixed point. 1701 */ 1702 # define TV_AY_MASK 0x000003ff 1703 # define TV_AY_SHIFT 0 1704 1705 #define TV_CSC_U 0x68018 1706 # define TV_RU_MASK 0x07ff0000 1707 # define TV_RU_SHIFT 16 1708 # define TV_GU_MASK 0x000007ff 1709 # define TV_GU_SHIFT 0 1710 1711 #define TV_CSC_U2 0x6801c 1712 # define TV_BU_MASK 0x07ff0000 1713 # define TV_BU_SHIFT 16 1714 /** 1715 * U attenuation for component video. 1716 * 1717 * Stored in 1.9 fixed point. 1718 */ 1719 # define TV_AU_MASK 0x000003ff 1720 # define TV_AU_SHIFT 0 1721 1722 #define TV_CSC_V 0x68020 1723 # define TV_RV_MASK 0x0fff0000 1724 # define TV_RV_SHIFT 16 1725 # define TV_GV_MASK 0x000007ff 1726 # define TV_GV_SHIFT 0 1727 1728 #define TV_CSC_V2 0x68024 1729 # define TV_BV_MASK 0x07ff0000 1730 # define TV_BV_SHIFT 16 1731 /** 1732 * V attenuation for component video. 1733 * 1734 * Stored in 1.9 fixed point. 1735 */ 1736 # define TV_AV_MASK 0x000007ff 1737 # define TV_AV_SHIFT 0 1738 1739 #define TV_CLR_KNOBS 0x68028 1740 /** 2s-complement brightness adjustment */ 1741 # define TV_BRIGHTNESS_MASK 0xff000000 1742 # define TV_BRIGHTNESS_SHIFT 24 1743 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1744 # define TV_CONTRAST_MASK 0x00ff0000 1745 # define TV_CONTRAST_SHIFT 16 1746 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1747 # define TV_SATURATION_MASK 0x0000ff00 1748 # define TV_SATURATION_SHIFT 8 1749 /** Hue adjustment, as an integer phase angle in degrees */ 1750 # define TV_HUE_MASK 0x000000ff 1751 # define TV_HUE_SHIFT 0 1752 1753 #define TV_CLR_LEVEL 0x6802c 1754 /** Controls the DAC level for black */ 1755 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1756 # define TV_BLACK_LEVEL_SHIFT 16 1757 /** Controls the DAC level for blanking */ 1758 # define TV_BLANK_LEVEL_MASK 0x000001ff 1759 # define TV_BLANK_LEVEL_SHIFT 0 1760 1761 #define TV_H_CTL_1 0x68030 1762 /** Number of pixels in the hsync. */ 1763 # define TV_HSYNC_END_MASK 0x1fff0000 1764 # define TV_HSYNC_END_SHIFT 16 1765 /** Total number of pixels minus one in the line (display and blanking). */ 1766 # define TV_HTOTAL_MASK 0x00001fff 1767 # define TV_HTOTAL_SHIFT 0 1768 1769 #define TV_H_CTL_2 0x68034 1770 /** Enables the colorburst (needed for non-component color) */ 1771 # define TV_BURST_ENA (1 << 31) 1772 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1773 # define TV_HBURST_START_SHIFT 16 1774 # define TV_HBURST_START_MASK 0x1fff0000 1775 /** Length of the colorburst */ 1776 # define TV_HBURST_LEN_SHIFT 0 1777 # define TV_HBURST_LEN_MASK 0x0001fff 1778 1779 #define TV_H_CTL_3 0x68038 1780 /** End of hblank, measured in pixels minus one from start of hsync */ 1781 # define TV_HBLANK_END_SHIFT 16 1782 # define TV_HBLANK_END_MASK 0x1fff0000 1783 /** Start of hblank, measured in pixels minus one from start of hsync */ 1784 # define TV_HBLANK_START_SHIFT 0 1785 # define TV_HBLANK_START_MASK 0x0001fff 1786 1787 #define TV_V_CTL_1 0x6803c 1788 /** XXX */ 1789 # define TV_NBR_END_SHIFT 16 1790 # define TV_NBR_END_MASK 0x07ff0000 1791 /** XXX */ 1792 # define TV_VI_END_F1_SHIFT 8 1793 # define TV_VI_END_F1_MASK 0x00003f00 1794 /** XXX */ 1795 # define TV_VI_END_F2_SHIFT 0 1796 # define TV_VI_END_F2_MASK 0x0000003f 1797 1798 #define TV_V_CTL_2 0x68040 1799 /** Length of vsync, in half lines */ 1800 # define TV_VSYNC_LEN_MASK 0x07ff0000 1801 # define TV_VSYNC_LEN_SHIFT 16 1802 /** Offset of the start of vsync in field 1, measured in one less than the 1803 * number of half lines. 1804 */ 1805 # define TV_VSYNC_START_F1_MASK 0x00007f00 1806 # define TV_VSYNC_START_F1_SHIFT 8 1807 /** 1808 * Offset of the start of vsync in field 2, measured in one less than the 1809 * number of half lines. 1810 */ 1811 # define TV_VSYNC_START_F2_MASK 0x0000007f 1812 # define TV_VSYNC_START_F2_SHIFT 0 1813 1814 #define TV_V_CTL_3 0x68044 1815 /** Enables generation of the equalization signal */ 1816 # define TV_EQUAL_ENA (1 << 31) 1817 /** Length of vsync, in half lines */ 1818 # define TV_VEQ_LEN_MASK 0x007f0000 1819 # define TV_VEQ_LEN_SHIFT 16 1820 /** Offset of the start of equalization in field 1, measured in one less than 1821 * the number of half lines. 1822 */ 1823 # define TV_VEQ_START_F1_MASK 0x0007f00 1824 # define TV_VEQ_START_F1_SHIFT 8 1825 /** 1826 * Offset of the start of equalization in field 2, measured in one less than 1827 * the number of half lines. 1828 */ 1829 # define TV_VEQ_START_F2_MASK 0x000007f 1830 # define TV_VEQ_START_F2_SHIFT 0 1831 1832 #define TV_V_CTL_4 0x68048 1833 /** 1834 * Offset to start of vertical colorburst, measured in one less than the 1835 * number of lines from vertical start. 1836 */ 1837 # define TV_VBURST_START_F1_MASK 0x003f0000 1838 # define TV_VBURST_START_F1_SHIFT 16 1839 /** 1840 * Offset to the end of vertical colorburst, measured in one less than the 1841 * number of lines from the start of NBR. 1842 */ 1843 # define TV_VBURST_END_F1_MASK 0x000000ff 1844 # define TV_VBURST_END_F1_SHIFT 0 1845 1846 #define TV_V_CTL_5 0x6804c 1847 /** 1848 * Offset to start of vertical colorburst, measured in one less than the 1849 * number of lines from vertical start. 1850 */ 1851 # define TV_VBURST_START_F2_MASK 0x003f0000 1852 # define TV_VBURST_START_F2_SHIFT 16 1853 /** 1854 * Offset to the end of vertical colorburst, measured in one less than the 1855 * number of lines from the start of NBR. 1856 */ 1857 # define TV_VBURST_END_F2_MASK 0x000000ff 1858 # define TV_VBURST_END_F2_SHIFT 0 1859 1860 #define TV_V_CTL_6 0x68050 1861 /** 1862 * Offset to start of vertical colorburst, measured in one less than the 1863 * number of lines from vertical start. 1864 */ 1865 # define TV_VBURST_START_F3_MASK 0x003f0000 1866 # define TV_VBURST_START_F3_SHIFT 16 1867 /** 1868 * Offset to the end of vertical colorburst, measured in one less than the 1869 * number of lines from the start of NBR. 1870 */ 1871 # define TV_VBURST_END_F3_MASK 0x000000ff 1872 # define TV_VBURST_END_F3_SHIFT 0 1873 1874 #define TV_V_CTL_7 0x68054 1875 /** 1876 * Offset to start of vertical colorburst, measured in one less than the 1877 * number of lines from vertical start. 1878 */ 1879 # define TV_VBURST_START_F4_MASK 0x003f0000 1880 # define TV_VBURST_START_F4_SHIFT 16 1881 /** 1882 * Offset to the end of vertical colorburst, measured in one less than the 1883 * number of lines from the start of NBR. 1884 */ 1885 # define TV_VBURST_END_F4_MASK 0x000000ff 1886 # define TV_VBURST_END_F4_SHIFT 0 1887 1888 #define TV_SC_CTL_1 0x68060 1889 /** Turns on the first subcarrier phase generation DDA */ 1890 # define TV_SC_DDA1_EN (1 << 31) 1891 /** Turns on the first subcarrier phase generation DDA */ 1892 # define TV_SC_DDA2_EN (1 << 30) 1893 /** Turns on the first subcarrier phase generation DDA */ 1894 # define TV_SC_DDA3_EN (1 << 29) 1895 /** Sets the subcarrier DDA to reset frequency every other field */ 1896 # define TV_SC_RESET_EVERY_2 (0 << 24) 1897 /** Sets the subcarrier DDA to reset frequency every fourth field */ 1898 # define TV_SC_RESET_EVERY_4 (1 << 24) 1899 /** Sets the subcarrier DDA to reset frequency every eighth field */ 1900 # define TV_SC_RESET_EVERY_8 (2 << 24) 1901 /** Sets the subcarrier DDA to never reset the frequency */ 1902 # define TV_SC_RESET_NEVER (3 << 24) 1903 /** Sets the peak amplitude of the colorburst.*/ 1904 # define TV_BURST_LEVEL_MASK 0x00ff0000 1905 # define TV_BURST_LEVEL_SHIFT 16 1906 /** Sets the increment of the first subcarrier phase generation DDA */ 1907 # define TV_SCDDA1_INC_MASK 0x00000fff 1908 # define TV_SCDDA1_INC_SHIFT 0 1909 1910 #define TV_SC_CTL_2 0x68064 1911 /** Sets the rollover for the second subcarrier phase generation DDA */ 1912 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 1913 # define TV_SCDDA2_SIZE_SHIFT 16 1914 /** Sets the increent of the second subcarrier phase generation DDA */ 1915 # define TV_SCDDA2_INC_MASK 0x00007fff 1916 # define TV_SCDDA2_INC_SHIFT 0 1917 1918 #define TV_SC_CTL_3 0x68068 1919 /** Sets the rollover for the third subcarrier phase generation DDA */ 1920 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 1921 # define TV_SCDDA3_SIZE_SHIFT 16 1922 /** Sets the increent of the third subcarrier phase generation DDA */ 1923 # define TV_SCDDA3_INC_MASK 0x00007fff 1924 # define TV_SCDDA3_INC_SHIFT 0 1925 1926 #define TV_WIN_POS 0x68070 1927 /** X coordinate of the display from the start of horizontal active */ 1928 # define TV_XPOS_MASK 0x1fff0000 1929 # define TV_XPOS_SHIFT 16 1930 /** Y coordinate of the display from the start of vertical active (NBR) */ 1931 # define TV_YPOS_MASK 0x00000fff 1932 # define TV_YPOS_SHIFT 0 1933 1934 #define TV_WIN_SIZE 0x68074 1935 /** Horizontal size of the display window, measured in pixels*/ 1936 # define TV_XSIZE_MASK 0x1fff0000 1937 # define TV_XSIZE_SHIFT 16 1938 /** 1939 * Vertical size of the display window, measured in pixels. 1940 * 1941 * Must be even for interlaced modes. 1942 */ 1943 # define TV_YSIZE_MASK 0x00000fff 1944 # define TV_YSIZE_SHIFT 0 1945 1946 #define TV_FILTER_CTL_1 0x68080 1947 /** 1948 * Enables automatic scaling calculation. 1949 * 1950 * If set, the rest of the registers are ignored, and the calculated values can 1951 * be read back from the register. 1952 */ 1953 # define TV_AUTO_SCALE (1 << 31) 1954 /** 1955 * Disables the vertical filter. 1956 * 1957 * This is required on modes more than 1024 pixels wide */ 1958 # define TV_V_FILTER_BYPASS (1 << 29) 1959 /** Enables adaptive vertical filtering */ 1960 # define TV_VADAPT (1 << 28) 1961 # define TV_VADAPT_MODE_MASK (3 << 26) 1962 /** Selects the least adaptive vertical filtering mode */ 1963 # define TV_VADAPT_MODE_LEAST (0 << 26) 1964 /** Selects the moderately adaptive vertical filtering mode */ 1965 # define TV_VADAPT_MODE_MODERATE (1 << 26) 1966 /** Selects the most adaptive vertical filtering mode */ 1967 # define TV_VADAPT_MODE_MOST (3 << 26) 1968 /** 1969 * Sets the horizontal scaling factor. 1970 * 1971 * This should be the fractional part of the horizontal scaling factor divided 1972 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1973 * 1974 * (src width - 1) / ((oversample * dest width) - 1) 1975 */ 1976 # define TV_HSCALE_FRAC_MASK 0x00003fff 1977 # define TV_HSCALE_FRAC_SHIFT 0 1978 1979 #define TV_FILTER_CTL_2 0x68084 1980 /** 1981 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1982 * 1983 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1984 */ 1985 # define TV_VSCALE_INT_MASK 0x00038000 1986 # define TV_VSCALE_INT_SHIFT 15 1987 /** 1988 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1989 * 1990 * \sa TV_VSCALE_INT_MASK 1991 */ 1992 # define TV_VSCALE_FRAC_MASK 0x00007fff 1993 # define TV_VSCALE_FRAC_SHIFT 0 1994 1995 #define TV_FILTER_CTL_3 0x68088 1996 /** 1997 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1998 * 1999 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2000 * 2001 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2002 */ 2003 # define TV_VSCALE_IP_INT_MASK 0x00038000 2004 # define TV_VSCALE_IP_INT_SHIFT 15 2005 /** 2006 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2007 * 2008 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2009 * 2010 * \sa TV_VSCALE_IP_INT_MASK 2011 */ 2012 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2013 # define TV_VSCALE_IP_FRAC_SHIFT 0 2014 2015 #define TV_CC_CONTROL 0x68090 2016 # define TV_CC_ENABLE (1 << 31) 2017 /** 2018 * Specifies which field to send the CC data in. 2019 * 2020 * CC data is usually sent in field 0. 2021 */ 2022 # define TV_CC_FID_MASK (1 << 27) 2023 # define TV_CC_FID_SHIFT 27 2024 /** Sets the horizontal position of the CC data. Usually 135. */ 2025 # define TV_CC_HOFF_MASK 0x03ff0000 2026 # define TV_CC_HOFF_SHIFT 16 2027 /** Sets the vertical position of the CC data. Usually 21 */ 2028 # define TV_CC_LINE_MASK 0x0000003f 2029 # define TV_CC_LINE_SHIFT 0 2030 2031 #define TV_CC_DATA 0x68094 2032 # define TV_CC_RDY (1 << 31) 2033 /** Second word of CC data to be transmitted. */ 2034 # define TV_CC_DATA_2_MASK 0x007f0000 2035 # define TV_CC_DATA_2_SHIFT 16 2036 /** First word of CC data to be transmitted. */ 2037 # define TV_CC_DATA_1_MASK 0x0000007f 2038 # define TV_CC_DATA_1_SHIFT 0 2039 2040 #define TV_H_LUMA_0 0x68100 2041 #define TV_H_LUMA_59 0x681ec 2042 #define TV_H_CHROMA_0 0x68200 2043 #define TV_H_CHROMA_59 0x682ec 2044 #define TV_V_LUMA_0 0x68300 2045 #define TV_V_LUMA_42 0x683a8 2046 #define TV_V_CHROMA_0 0x68400 2047 #define TV_V_CHROMA_42 0x684a8 2048 2049 /* Display Port */ 2050 #define DP_A 0x64000 /* eDP */ 2051 #define DP_B 0x64100 2052 #define DP_C 0x64200 2053 #define DP_D 0x64300 2054 2055 #define DP_PORT_EN (1 << 31) 2056 #define DP_PIPEB_SELECT (1 << 30) 2057 2058 /* Link training mode - select a suitable mode for each stage */ 2059 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2060 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2061 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2062 #define DP_LINK_TRAIN_OFF (3 << 28) 2063 #define DP_LINK_TRAIN_MASK (3 << 28) 2064 #define DP_LINK_TRAIN_SHIFT 28 2065 2066 /* CPT Link training mode */ 2067 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2068 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2069 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2070 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2071 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2072 #define DP_LINK_TRAIN_SHIFT_CPT 8 2073 2074 /* Signal voltages. These are mostly controlled by the other end */ 2075 #define DP_VOLTAGE_0_4 (0 << 25) 2076 #define DP_VOLTAGE_0_6 (1 << 25) 2077 #define DP_VOLTAGE_0_8 (2 << 25) 2078 #define DP_VOLTAGE_1_2 (3 << 25) 2079 #define DP_VOLTAGE_MASK (7 << 25) 2080 #define DP_VOLTAGE_SHIFT 25 2081 2082 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2083 * they want 2084 */ 2085 #define DP_PRE_EMPHASIS_0 (0 << 22) 2086 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2087 #define DP_PRE_EMPHASIS_6 (2 << 22) 2088 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2089 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2090 #define DP_PRE_EMPHASIS_SHIFT 22 2091 2092 /* How many wires to use. I guess 3 was too hard */ 2093 #define DP_PORT_WIDTH_1 (0 << 19) 2094 #define DP_PORT_WIDTH_2 (1 << 19) 2095 #define DP_PORT_WIDTH_4 (3 << 19) 2096 #define DP_PORT_WIDTH_MASK (7 << 19) 2097 2098 /* Mystic DPCD version 1.1 special mode */ 2099 #define DP_ENHANCED_FRAMING (1 << 18) 2100 2101 /* eDP */ 2102 #define DP_PLL_FREQ_270MHZ (0 << 16) 2103 #define DP_PLL_FREQ_160MHZ (1 << 16) 2104 #define DP_PLL_FREQ_MASK (3 << 16) 2105 2106 /** locked once port is enabled */ 2107 #define DP_PORT_REVERSAL (1 << 15) 2108 2109 /* eDP */ 2110 #define DP_PLL_ENABLE (1 << 14) 2111 2112 /** sends the clock on lane 15 of the PEG for debug */ 2113 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2114 2115 #define DP_SCRAMBLING_DISABLE (1 << 12) 2116 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2117 2118 /** limit RGB values to avoid confusing TVs */ 2119 #define DP_COLOR_RANGE_16_235 (1 << 8) 2120 2121 /** Turn on the audio link */ 2122 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2123 2124 /** vs and hs sync polarity */ 2125 #define DP_SYNC_VS_HIGH (1 << 4) 2126 #define DP_SYNC_HS_HIGH (1 << 3) 2127 2128 /** A fantasy */ 2129 #define DP_DETECTED (1 << 2) 2130 2131 /** The aux channel provides a way to talk to the 2132 * signal sink for DDC etc. Max packet size supported 2133 * is 20 bytes in each direction, hence the 5 fixed 2134 * data registers 2135 */ 2136 #define DPA_AUX_CH_CTL 0x64010 2137 #define DPA_AUX_CH_DATA1 0x64014 2138 #define DPA_AUX_CH_DATA2 0x64018 2139 #define DPA_AUX_CH_DATA3 0x6401c 2140 #define DPA_AUX_CH_DATA4 0x64020 2141 #define DPA_AUX_CH_DATA5 0x64024 2142 2143 #define DPB_AUX_CH_CTL 0x64110 2144 #define DPB_AUX_CH_DATA1 0x64114 2145 #define DPB_AUX_CH_DATA2 0x64118 2146 #define DPB_AUX_CH_DATA3 0x6411c 2147 #define DPB_AUX_CH_DATA4 0x64120 2148 #define DPB_AUX_CH_DATA5 0x64124 2149 2150 #define DPC_AUX_CH_CTL 0x64210 2151 #define DPC_AUX_CH_DATA1 0x64214 2152 #define DPC_AUX_CH_DATA2 0x64218 2153 #define DPC_AUX_CH_DATA3 0x6421c 2154 #define DPC_AUX_CH_DATA4 0x64220 2155 #define DPC_AUX_CH_DATA5 0x64224 2156 2157 #define DPD_AUX_CH_CTL 0x64310 2158 #define DPD_AUX_CH_DATA1 0x64314 2159 #define DPD_AUX_CH_DATA2 0x64318 2160 #define DPD_AUX_CH_DATA3 0x6431c 2161 #define DPD_AUX_CH_DATA4 0x64320 2162 #define DPD_AUX_CH_DATA5 0x64324 2163 2164 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2165 #define DP_AUX_CH_CTL_DONE (1 << 30) 2166 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2167 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2168 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2169 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2170 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2171 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2172 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2173 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2174 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2175 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2176 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2177 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2178 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2179 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2180 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2181 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2182 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2183 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2184 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2185 2186 /* 2187 * Computing GMCH M and N values for the Display Port link 2188 * 2189 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2190 * 2191 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2192 * 2193 * The GMCH value is used internally 2194 * 2195 * bytes_per_pixel is the number of bytes coming out of the plane, 2196 * which is after the LUTs, so we want the bytes for our color format. 2197 * For our current usage, this is always 3, one byte for R, G and B. 2198 */ 2199 #define PIPEA_GMCH_DATA_M 0x70050 2200 #define PIPEB_GMCH_DATA_M 0x71050 2201 2202 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2203 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2204 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2205 2206 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2207 2208 #define PIPEA_GMCH_DATA_N 0x70054 2209 #define PIPEB_GMCH_DATA_N 0x71054 2210 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2211 2212 /* 2213 * Computing Link M and N values for the Display Port link 2214 * 2215 * Link M / N = pixel_clock / ls_clk 2216 * 2217 * (the DP spec calls pixel_clock the 'strm_clk') 2218 * 2219 * The Link value is transmitted in the Main Stream 2220 * Attributes and VB-ID. 2221 */ 2222 2223 #define PIPEA_DP_LINK_M 0x70060 2224 #define PIPEB_DP_LINK_M 0x71060 2225 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2226 2227 #define PIPEA_DP_LINK_N 0x70064 2228 #define PIPEB_DP_LINK_N 0x71064 2229 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2230 2231 /* Display & cursor control */ 2232 2233 /* Pipe A */ 2234 #define PIPEADSL 0x70000 2235 #define DSL_LINEMASK 0x00000fff 2236 #define PIPEACONF 0x70008 2237 #define PIPECONF_ENABLE (1<<31) 2238 #define PIPECONF_DISABLE 0 2239 #define PIPECONF_DOUBLE_WIDE (1<<30) 2240 #define I965_PIPECONF_ACTIVE (1<<30) 2241 #define PIPECONF_SINGLE_WIDE 0 2242 #define PIPECONF_PIPE_UNLOCKED 0 2243 #define PIPECONF_PIPE_LOCKED (1<<25) 2244 #define PIPECONF_PALETTE 0 2245 #define PIPECONF_GAMMA (1<<24) 2246 #define PIPECONF_FORCE_BORDER (1<<25) 2247 #define PIPECONF_PROGRESSIVE (0 << 21) 2248 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2249 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2250 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2251 #define PIPECONF_BPP_MASK (0x000000e0) 2252 #define PIPECONF_BPP_8 (0<<5) 2253 #define PIPECONF_BPP_10 (1<<5) 2254 #define PIPECONF_BPP_6 (2<<5) 2255 #define PIPECONF_BPP_12 (3<<5) 2256 #define PIPECONF_DITHER_EN (1<<4) 2257 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2258 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2259 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2260 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2261 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2262 #define PIPEASTAT 0x70024 2263 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2264 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2265 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2266 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2267 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2268 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2269 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2270 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2271 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2272 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2273 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2274 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2275 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2276 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2277 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2278 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2279 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2280 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2281 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2282 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2283 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2284 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2285 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2286 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2287 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2288 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2289 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2290 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2291 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2292 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2293 #define PIPE_8BPC (0 << 5) 2294 #define PIPE_10BPC (1 << 5) 2295 #define PIPE_6BPC (2 << 5) 2296 #define PIPE_12BPC (3 << 5) 2297 2298 #define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC) 2299 #define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF) 2300 #define PIPEDSL(pipe) _PIPE(pipe, PIPEADSL, PIPEBDSL) 2301 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, PIPEAFRAMEPIXEL, PIPEBFRAMEPIXEL) 2302 2303 #define DSPARB 0x70030 2304 #define DSPARB_CSTART_MASK (0x7f << 7) 2305 #define DSPARB_CSTART_SHIFT 7 2306 #define DSPARB_BSTART_MASK (0x7f) 2307 #define DSPARB_BSTART_SHIFT 0 2308 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2309 #define DSPARB_AEND_SHIFT 0 2310 2311 #define DSPFW1 0x70034 2312 #define DSPFW_SR_SHIFT 23 2313 #define DSPFW_SR_MASK (0x1ff<<23) 2314 #define DSPFW_CURSORB_SHIFT 16 2315 #define DSPFW_CURSORB_MASK (0x3f<<16) 2316 #define DSPFW_PLANEB_SHIFT 8 2317 #define DSPFW_PLANEB_MASK (0x7f<<8) 2318 #define DSPFW_PLANEA_MASK (0x7f) 2319 #define DSPFW2 0x70038 2320 #define DSPFW_CURSORA_MASK 0x00003f00 2321 #define DSPFW_CURSORA_SHIFT 8 2322 #define DSPFW_PLANEC_MASK (0x7f) 2323 #define DSPFW3 0x7003c 2324 #define DSPFW_HPLL_SR_EN (1<<31) 2325 #define DSPFW_CURSOR_SR_SHIFT 24 2326 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2327 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2328 #define DSPFW_HPLL_CURSOR_SHIFT 16 2329 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2330 #define DSPFW_HPLL_SR_MASK (0x1ff) 2331 2332 /* FIFO watermark sizes etc */ 2333 #define G4X_FIFO_LINE_SIZE 64 2334 #define I915_FIFO_LINE_SIZE 64 2335 #define I830_FIFO_LINE_SIZE 32 2336 2337 #define G4X_FIFO_SIZE 127 2338 #define I965_FIFO_SIZE 512 2339 #define I945_FIFO_SIZE 127 2340 #define I915_FIFO_SIZE 95 2341 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2342 #define I830_FIFO_SIZE 95 2343 2344 #define G4X_MAX_WM 0x3f 2345 #define I915_MAX_WM 0x3f 2346 2347 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2348 #define PINEVIEW_FIFO_LINE_SIZE 64 2349 #define PINEVIEW_MAX_WM 0x1ff 2350 #define PINEVIEW_DFT_WM 0x3f 2351 #define PINEVIEW_DFT_HPLLOFF_WM 0 2352 #define PINEVIEW_GUARD_WM 10 2353 #define PINEVIEW_CURSOR_FIFO 64 2354 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2355 #define PINEVIEW_CURSOR_DFT_WM 0 2356 #define PINEVIEW_CURSOR_GUARD_WM 5 2357 2358 #define I965_CURSOR_FIFO 64 2359 #define I965_CURSOR_MAX_WM 32 2360 #define I965_CURSOR_DFT_WM 8 2361 2362 /* define the Watermark register on Ironlake */ 2363 #define WM0_PIPEA_ILK 0x45100 2364 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2365 #define WM0_PIPE_PLANE_SHIFT 16 2366 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2367 #define WM0_PIPE_SPRITE_SHIFT 8 2368 #define WM0_PIPE_CURSOR_MASK (0x1f) 2369 2370 #define WM0_PIPEB_ILK 0x45104 2371 #define WM1_LP_ILK 0x45108 2372 #define WM1_LP_SR_EN (1<<31) 2373 #define WM1_LP_LATENCY_SHIFT 24 2374 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2375 #define WM1_LP_FBC_MASK (0xf<<20) 2376 #define WM1_LP_FBC_SHIFT 20 2377 #define WM1_LP_SR_MASK (0x1ff<<8) 2378 #define WM1_LP_SR_SHIFT 8 2379 #define WM1_LP_CURSOR_MASK (0x3f) 2380 #define WM2_LP_ILK 0x4510c 2381 #define WM2_LP_EN (1<<31) 2382 #define WM3_LP_ILK 0x45110 2383 #define WM3_LP_EN (1<<31) 2384 #define WM1S_LP_ILK 0x45120 2385 #define WM1S_LP_EN (1<<31) 2386 2387 /* Memory latency timer register */ 2388 #define MLTR_ILK 0x11222 2389 #define MLTR_WM1_SHIFT 0 2390 #define MLTR_WM2_SHIFT 8 2391 /* the unit of memory self-refresh latency time is 0.5us */ 2392 #define ILK_SRLT_MASK 0x3f 2393 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2394 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2395 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2396 2397 /* define the fifo size on Ironlake */ 2398 #define ILK_DISPLAY_FIFO 128 2399 #define ILK_DISPLAY_MAXWM 64 2400 #define ILK_DISPLAY_DFTWM 8 2401 #define ILK_CURSOR_FIFO 32 2402 #define ILK_CURSOR_MAXWM 16 2403 #define ILK_CURSOR_DFTWM 8 2404 2405 #define ILK_DISPLAY_SR_FIFO 512 2406 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2407 #define ILK_DISPLAY_DFT_SRWM 0x3f 2408 #define ILK_CURSOR_SR_FIFO 64 2409 #define ILK_CURSOR_MAX_SRWM 0x3f 2410 #define ILK_CURSOR_DFT_SRWM 8 2411 2412 #define ILK_FIFO_LINE_SIZE 64 2413 2414 /* define the WM info on Sandybridge */ 2415 #define SNB_DISPLAY_FIFO 128 2416 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2417 #define SNB_DISPLAY_DFTWM 8 2418 #define SNB_CURSOR_FIFO 32 2419 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2420 #define SNB_CURSOR_DFTWM 8 2421 2422 #define SNB_DISPLAY_SR_FIFO 512 2423 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2424 #define SNB_DISPLAY_DFT_SRWM 0x3f 2425 #define SNB_CURSOR_SR_FIFO 64 2426 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2427 #define SNB_CURSOR_DFT_SRWM 8 2428 2429 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2430 2431 #define SNB_FIFO_LINE_SIZE 64 2432 2433 2434 /* the address where we get all kinds of latency value */ 2435 #define SSKPD 0x5d10 2436 #define SSKPD_WM_MASK 0x3f 2437 #define SSKPD_WM0_SHIFT 0 2438 #define SSKPD_WM1_SHIFT 8 2439 #define SSKPD_WM2_SHIFT 16 2440 #define SSKPD_WM3_SHIFT 24 2441 2442 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) 2443 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) 2444 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) 2445 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) 2446 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) 2447 2448 /* 2449 * The two pipe frame counter registers are not synchronized, so 2450 * reading a stable value is somewhat tricky. The following code 2451 * should work: 2452 * 2453 * do { 2454 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2455 * PIPE_FRAME_HIGH_SHIFT; 2456 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2457 * PIPE_FRAME_LOW_SHIFT); 2458 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2459 * PIPE_FRAME_HIGH_SHIFT); 2460 * } while (high1 != high2); 2461 * frame = (high1 << 8) | low1; 2462 */ 2463 #define PIPEAFRAMEHIGH 0x70040 2464 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2465 #define PIPE_FRAME_HIGH_SHIFT 0 2466 #define PIPEAFRAMEPIXEL 0x70044 2467 #define PIPE_FRAME_LOW_MASK 0xff000000 2468 #define PIPE_FRAME_LOW_SHIFT 24 2469 #define PIPE_PIXEL_MASK 0x00ffffff 2470 #define PIPE_PIXEL_SHIFT 0 2471 /* GM45+ just has to be different */ 2472 #define PIPEA_FRMCOUNT_GM45 0x70040 2473 #define PIPEA_FLIPCOUNT_GM45 0x70044 2474 2475 /* Cursor A & B regs */ 2476 #define CURACNTR 0x70080 2477 /* Old style CUR*CNTR flags (desktop 8xx) */ 2478 #define CURSOR_ENABLE 0x80000000 2479 #define CURSOR_GAMMA_ENABLE 0x40000000 2480 #define CURSOR_STRIDE_MASK 0x30000000 2481 #define CURSOR_FORMAT_SHIFT 24 2482 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2483 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2484 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2485 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2486 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2487 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2488 /* New style CUR*CNTR flags */ 2489 #define CURSOR_MODE 0x27 2490 #define CURSOR_MODE_DISABLE 0x00 2491 #define CURSOR_MODE_64_32B_AX 0x07 2492 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2493 #define MCURSOR_PIPE_SELECT (1 << 28) 2494 #define MCURSOR_PIPE_A 0x00 2495 #define MCURSOR_PIPE_B (1 << 28) 2496 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2497 #define CURABASE 0x70084 2498 #define CURAPOS 0x70088 2499 #define CURSOR_POS_MASK 0x007FF 2500 #define CURSOR_POS_SIGN 0x8000 2501 #define CURSOR_X_SHIFT 0 2502 #define CURSOR_Y_SHIFT 16 2503 #define CURSIZE 0x700a0 2504 #define CURBCNTR 0x700c0 2505 #define CURBBASE 0x700c4 2506 #define CURBPOS 0x700c8 2507 2508 #define CURCNTR(pipe) _PIPE(pipe, CURACNTR, CURBCNTR) 2509 #define CURBASE(pipe) _PIPE(pipe, CURABASE, CURBBASE) 2510 #define CURPOS(pipe) _PIPE(pipe, CURAPOS, CURBPOS) 2511 2512 /* Display A control */ 2513 #define DSPACNTR 0x70180 2514 #define DISPLAY_PLANE_ENABLE (1<<31) 2515 #define DISPLAY_PLANE_DISABLE 0 2516 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2517 #define DISPPLANE_GAMMA_DISABLE 0 2518 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2519 #define DISPPLANE_8BPP (0x2<<26) 2520 #define DISPPLANE_15_16BPP (0x4<<26) 2521 #define DISPPLANE_16BPP (0x5<<26) 2522 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2523 #define DISPPLANE_32BPP (0x7<<26) 2524 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2525 #define DISPPLANE_STEREO_ENABLE (1<<25) 2526 #define DISPPLANE_STEREO_DISABLE 0 2527 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 2528 #define DISPPLANE_SEL_PIPE_A 0 2529 #define DISPPLANE_SEL_PIPE_B (1<<24) 2530 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2531 #define DISPPLANE_SRC_KEY_DISABLE 0 2532 #define DISPPLANE_LINE_DOUBLE (1<<20) 2533 #define DISPPLANE_NO_LINE_DOUBLE 0 2534 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2535 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2536 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2537 #define DISPPLANE_TILED (1<<10) 2538 #define DSPAADDR 0x70184 2539 #define DSPASTRIDE 0x70188 2540 #define DSPAPOS 0x7018C /* reserved */ 2541 #define DSPASIZE 0x70190 2542 #define DSPASURF 0x7019C /* 965+ only */ 2543 #define DSPATILEOFF 0x701A4 /* 965+ only */ 2544 2545 #define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR) 2546 #define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR) 2547 #define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE) 2548 #define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS) 2549 #define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE) 2550 #define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF) 2551 #define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF) 2552 2553 /* VBIOS flags */ 2554 #define SWF00 0x71410 2555 #define SWF01 0x71414 2556 #define SWF02 0x71418 2557 #define SWF03 0x7141c 2558 #define SWF04 0x71420 2559 #define SWF05 0x71424 2560 #define SWF06 0x71428 2561 #define SWF10 0x70410 2562 #define SWF11 0x70414 2563 #define SWF14 0x71420 2564 #define SWF30 0x72414 2565 #define SWF31 0x72418 2566 #define SWF32 0x7241c 2567 2568 /* Pipe B */ 2569 #define PIPEBDSL 0x71000 2570 #define PIPEBCONF 0x71008 2571 #define PIPEBSTAT 0x71024 2572 #define PIPEBFRAMEHIGH 0x71040 2573 #define PIPEBFRAMEPIXEL 0x71044 2574 #define PIPEB_FRMCOUNT_GM45 0x71040 2575 #define PIPEB_FLIPCOUNT_GM45 0x71044 2576 2577 2578 /* Display B control */ 2579 #define DSPBCNTR 0x71180 2580 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2581 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2582 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2583 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2584 #define DSPBADDR 0x71184 2585 #define DSPBSTRIDE 0x71188 2586 #define DSPBPOS 0x7118C 2587 #define DSPBSIZE 0x71190 2588 #define DSPBSURF 0x7119C 2589 #define DSPBTILEOFF 0x711A4 2590 2591 /* VBIOS regs */ 2592 #define VGACNTRL 0x71400 2593 # define VGA_DISP_DISABLE (1 << 31) 2594 # define VGA_2X_MODE (1 << 30) 2595 # define VGA_PIPE_B_SELECT (1 << 29) 2596 2597 /* Ironlake */ 2598 2599 #define CPU_VGACNTRL 0x41000 2600 2601 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2602 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2603 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2604 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2605 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2606 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2607 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 2608 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2609 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2610 2611 /* refresh rate hardware control */ 2612 #define RR_HW_CTL 0x45300 2613 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2614 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2615 2616 #define FDI_PLL_BIOS_0 0x46000 2617 #define FDI_PLL_FB_CLOCK_MASK 0xff 2618 #define FDI_PLL_BIOS_1 0x46004 2619 #define FDI_PLL_BIOS_2 0x46008 2620 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2621 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2622 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2623 2624 #define PCH_DSPCLK_GATE_D 0x42020 2625 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 2626 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 2627 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 2628 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 2629 2630 #define PCH_3DCGDIS0 0x46020 2631 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2632 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2633 2634 #define PCH_3DCGDIS1 0x46024 2635 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2636 2637 #define FDI_PLL_FREQ_CTL 0x46030 2638 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2639 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2640 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2641 2642 2643 #define PIPEA_DATA_M1 0x60030 2644 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2645 #define TU_SIZE_MASK 0x7e000000 2646 #define PIPE_DATA_M1_OFFSET 0 2647 #define PIPEA_DATA_N1 0x60034 2648 #define PIPE_DATA_N1_OFFSET 0 2649 2650 #define PIPEA_DATA_M2 0x60038 2651 #define PIPE_DATA_M2_OFFSET 0 2652 #define PIPEA_DATA_N2 0x6003c 2653 #define PIPE_DATA_N2_OFFSET 0 2654 2655 #define PIPEA_LINK_M1 0x60040 2656 #define PIPE_LINK_M1_OFFSET 0 2657 #define PIPEA_LINK_N1 0x60044 2658 #define PIPE_LINK_N1_OFFSET 0 2659 2660 #define PIPEA_LINK_M2 0x60048 2661 #define PIPE_LINK_M2_OFFSET 0 2662 #define PIPEA_LINK_N2 0x6004c 2663 #define PIPE_LINK_N2_OFFSET 0 2664 2665 /* PIPEB timing regs are same start from 0x61000 */ 2666 2667 #define PIPEB_DATA_M1 0x61030 2668 #define PIPEB_DATA_N1 0x61034 2669 2670 #define PIPEB_DATA_M2 0x61038 2671 #define PIPEB_DATA_N2 0x6103c 2672 2673 #define PIPEB_LINK_M1 0x61040 2674 #define PIPEB_LINK_N1 0x61044 2675 2676 #define PIPEB_LINK_M2 0x61048 2677 #define PIPEB_LINK_N2 0x6104c 2678 2679 #define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1) 2680 #define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1) 2681 #define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2) 2682 #define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2) 2683 #define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1) 2684 #define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1) 2685 #define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2) 2686 #define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2) 2687 2688 /* CPU panel fitter */ 2689 #define PFA_CTL_1 0x68080 2690 #define PFB_CTL_1 0x68880 2691 #define PF_ENABLE (1<<31) 2692 #define PF_FILTER_MASK (3<<23) 2693 #define PF_FILTER_PROGRAMMED (0<<23) 2694 #define PF_FILTER_MED_3x3 (1<<23) 2695 #define PF_FILTER_EDGE_ENHANCE (2<<23) 2696 #define PF_FILTER_EDGE_SOFTEN (3<<23) 2697 #define PFA_WIN_SZ 0x68074 2698 #define PFB_WIN_SZ 0x68874 2699 #define PFA_WIN_POS 0x68070 2700 #define PFB_WIN_POS 0x68870 2701 2702 /* legacy palette */ 2703 #define LGC_PALETTE_A 0x4a000 2704 #define LGC_PALETTE_B 0x4a800 2705 2706 /* interrupts */ 2707 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2708 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2709 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2710 #define DE_PLANEB_FLIP_DONE (1 << 27) 2711 #define DE_PLANEA_FLIP_DONE (1 << 26) 2712 #define DE_PCU_EVENT (1 << 25) 2713 #define DE_GTT_FAULT (1 << 24) 2714 #define DE_POISON (1 << 23) 2715 #define DE_PERFORM_COUNTER (1 << 22) 2716 #define DE_PCH_EVENT (1 << 21) 2717 #define DE_AUX_CHANNEL_A (1 << 20) 2718 #define DE_DP_A_HOTPLUG (1 << 19) 2719 #define DE_GSE (1 << 18) 2720 #define DE_PIPEB_VBLANK (1 << 15) 2721 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2722 #define DE_PIPEB_ODD_FIELD (1 << 13) 2723 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2724 #define DE_PIPEB_VSYNC (1 << 11) 2725 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2726 #define DE_PIPEA_VBLANK (1 << 7) 2727 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2728 #define DE_PIPEA_ODD_FIELD (1 << 5) 2729 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2730 #define DE_PIPEA_VSYNC (1 << 3) 2731 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2732 2733 #define DEISR 0x44000 2734 #define DEIMR 0x44004 2735 #define DEIIR 0x44008 2736 #define DEIER 0x4400c 2737 2738 /* GT interrupt */ 2739 #define GT_PIPE_NOTIFY (1 << 4) 2740 #define GT_SYNC_STATUS (1 << 2) 2741 #define GT_USER_INTERRUPT (1 << 0) 2742 #define GT_BSD_USER_INTERRUPT (1 << 5) 2743 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 2744 #define GT_BLT_USER_INTERRUPT (1 << 22) 2745 2746 #define GTISR 0x44010 2747 #define GTIMR 0x44014 2748 #define GTIIR 0x44018 2749 #define GTIER 0x4401c 2750 2751 #define ILK_DISPLAY_CHICKEN2 0x42004 2752 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 2753 #define ILK_ELPIN_409_SELECT (1 << 25) 2754 #define ILK_DPARB_GATE (1<<22) 2755 #define ILK_VSDPFD_FULL (1<<21) 2756 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 2757 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 2758 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 2759 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 2760 #define ILK_HDCP_DISABLE (1<<25) 2761 #define ILK_eDP_A_DISABLE (1<<24) 2762 #define ILK_DESKTOP (1<<23) 2763 #define ILK_DSPCLK_GATE 0x42020 2764 #define ILK_DPARB_CLK_GATE (1<<5) 2765 #define ILK_DPFD_CLK_GATE (1<<7) 2766 2767 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 2768 #define ILK_CLK_FBC (1<<7) 2769 #define ILK_DPFC_DIS1 (1<<8) 2770 #define ILK_DPFC_DIS2 (1<<9) 2771 2772 #define DISP_ARB_CTL 0x45000 2773 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 2774 #define DISP_FBC_WM_DIS (1<<15) 2775 2776 /* PCH */ 2777 2778 /* south display engine interrupt */ 2779 #define SDE_AUDIO_POWER_D (1 << 27) 2780 #define SDE_AUDIO_POWER_C (1 << 26) 2781 #define SDE_AUDIO_POWER_B (1 << 25) 2782 #define SDE_AUDIO_POWER_SHIFT (25) 2783 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 2784 #define SDE_GMBUS (1 << 24) 2785 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 2786 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 2787 #define SDE_AUDIO_HDCP_MASK (3 << 22) 2788 #define SDE_AUDIO_TRANSB (1 << 21) 2789 #define SDE_AUDIO_TRANSA (1 << 20) 2790 #define SDE_AUDIO_TRANS_MASK (3 << 20) 2791 #define SDE_POISON (1 << 19) 2792 /* 18 reserved */ 2793 #define SDE_FDI_RXB (1 << 17) 2794 #define SDE_FDI_RXA (1 << 16) 2795 #define SDE_FDI_MASK (3 << 16) 2796 #define SDE_AUXD (1 << 15) 2797 #define SDE_AUXC (1 << 14) 2798 #define SDE_AUXB (1 << 13) 2799 #define SDE_AUX_MASK (7 << 13) 2800 /* 12 reserved */ 2801 #define SDE_CRT_HOTPLUG (1 << 11) 2802 #define SDE_PORTD_HOTPLUG (1 << 10) 2803 #define SDE_PORTC_HOTPLUG (1 << 9) 2804 #define SDE_PORTB_HOTPLUG (1 << 8) 2805 #define SDE_SDVOB_HOTPLUG (1 << 6) 2806 #define SDE_HOTPLUG_MASK (0xf << 8) 2807 #define SDE_TRANSB_CRC_DONE (1 << 5) 2808 #define SDE_TRANSB_CRC_ERR (1 << 4) 2809 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 2810 #define SDE_TRANSA_CRC_DONE (1 << 2) 2811 #define SDE_TRANSA_CRC_ERR (1 << 1) 2812 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 2813 #define SDE_TRANS_MASK (0x3f) 2814 /* CPT */ 2815 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 2816 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 2817 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 2818 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 2819 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 2820 SDE_PORTD_HOTPLUG_CPT | \ 2821 SDE_PORTC_HOTPLUG_CPT | \ 2822 SDE_PORTB_HOTPLUG_CPT) 2823 2824 #define SDEISR 0xc4000 2825 #define SDEIMR 0xc4004 2826 #define SDEIIR 0xc4008 2827 #define SDEIER 0xc400c 2828 2829 /* digital port hotplug */ 2830 #define PCH_PORT_HOTPLUG 0xc4030 2831 #define PORTD_HOTPLUG_ENABLE (1 << 20) 2832 #define PORTD_PULSE_DURATION_2ms (0) 2833 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 2834 #define PORTD_PULSE_DURATION_6ms (2 << 18) 2835 #define PORTD_PULSE_DURATION_100ms (3 << 18) 2836 #define PORTD_HOTPLUG_NO_DETECT (0) 2837 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 2838 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 2839 #define PORTC_HOTPLUG_ENABLE (1 << 12) 2840 #define PORTC_PULSE_DURATION_2ms (0) 2841 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 2842 #define PORTC_PULSE_DURATION_6ms (2 << 10) 2843 #define PORTC_PULSE_DURATION_100ms (3 << 10) 2844 #define PORTC_HOTPLUG_NO_DETECT (0) 2845 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 2846 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 2847 #define PORTB_HOTPLUG_ENABLE (1 << 4) 2848 #define PORTB_PULSE_DURATION_2ms (0) 2849 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 2850 #define PORTB_PULSE_DURATION_6ms (2 << 2) 2851 #define PORTB_PULSE_DURATION_100ms (3 << 2) 2852 #define PORTB_HOTPLUG_NO_DETECT (0) 2853 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 2854 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 2855 2856 #define PCH_GPIOA 0xc5010 2857 #define PCH_GPIOB 0xc5014 2858 #define PCH_GPIOC 0xc5018 2859 #define PCH_GPIOD 0xc501c 2860 #define PCH_GPIOE 0xc5020 2861 #define PCH_GPIOF 0xc5024 2862 2863 #define PCH_GMBUS0 0xc5100 2864 #define PCH_GMBUS1 0xc5104 2865 #define PCH_GMBUS2 0xc5108 2866 #define PCH_GMBUS3 0xc510c 2867 #define PCH_GMBUS4 0xc5110 2868 #define PCH_GMBUS5 0xc5120 2869 2870 #define PCH_DPLL_A 0xc6014 2871 #define PCH_DPLL_B 0xc6018 2872 #define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B) 2873 2874 #define PCH_FPA0 0xc6040 2875 #define FP_CB_TUNE (0x3<<22) 2876 #define PCH_FPA1 0xc6044 2877 #define PCH_FPB0 0xc6048 2878 #define PCH_FPB1 0xc604c 2879 #define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0) 2880 #define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1) 2881 2882 #define PCH_DPLL_TEST 0xc606c 2883 2884 #define PCH_DREF_CONTROL 0xC6200 2885 #define DREF_CONTROL_MASK 0x7fc3 2886 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 2887 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 2888 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 2889 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 2890 #define DREF_SSC_SOURCE_DISABLE (0<<11) 2891 #define DREF_SSC_SOURCE_ENABLE (2<<11) 2892 #define DREF_SSC_SOURCE_MASK (3<<11) 2893 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 2894 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 2895 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 2896 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 2897 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2898 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2899 #define DREF_SSC4_DOWNSPREAD (0<<6) 2900 #define DREF_SSC4_CENTERSPREAD (1<<6) 2901 #define DREF_SSC1_DISABLE (0<<1) 2902 #define DREF_SSC1_ENABLE (1<<1) 2903 #define DREF_SSC4_DISABLE (0) 2904 #define DREF_SSC4_ENABLE (1) 2905 2906 #define PCH_RAWCLK_FREQ 0xc6204 2907 #define FDL_TP1_TIMER_SHIFT 12 2908 #define FDL_TP1_TIMER_MASK (3<<12) 2909 #define FDL_TP2_TIMER_SHIFT 10 2910 #define FDL_TP2_TIMER_MASK (3<<10) 2911 #define RAWCLK_FREQ_MASK 0x3ff 2912 2913 #define PCH_DPLL_TMR_CFG 0xc6208 2914 2915 #define PCH_SSC4_PARMS 0xc6210 2916 #define PCH_SSC4_AUX_PARMS 0xc6214 2917 2918 #define PCH_DPLL_SEL 0xc7000 2919 #define TRANSA_DPLL_ENABLE (1<<3) 2920 #define TRANSA_DPLLB_SEL (1<<0) 2921 #define TRANSA_DPLLA_SEL 0 2922 #define TRANSB_DPLL_ENABLE (1<<7) 2923 #define TRANSB_DPLLB_SEL (1<<4) 2924 #define TRANSB_DPLLA_SEL (0) 2925 #define TRANSC_DPLL_ENABLE (1<<11) 2926 #define TRANSC_DPLLB_SEL (1<<8) 2927 #define TRANSC_DPLLA_SEL (0) 2928 2929 /* transcoder */ 2930 2931 #define TRANS_HTOTAL_A 0xe0000 2932 #define TRANS_HTOTAL_SHIFT 16 2933 #define TRANS_HACTIVE_SHIFT 0 2934 #define TRANS_HBLANK_A 0xe0004 2935 #define TRANS_HBLANK_END_SHIFT 16 2936 #define TRANS_HBLANK_START_SHIFT 0 2937 #define TRANS_HSYNC_A 0xe0008 2938 #define TRANS_HSYNC_END_SHIFT 16 2939 #define TRANS_HSYNC_START_SHIFT 0 2940 #define TRANS_VTOTAL_A 0xe000c 2941 #define TRANS_VTOTAL_SHIFT 16 2942 #define TRANS_VACTIVE_SHIFT 0 2943 #define TRANS_VBLANK_A 0xe0010 2944 #define TRANS_VBLANK_END_SHIFT 16 2945 #define TRANS_VBLANK_START_SHIFT 0 2946 #define TRANS_VSYNC_A 0xe0014 2947 #define TRANS_VSYNC_END_SHIFT 16 2948 #define TRANS_VSYNC_START_SHIFT 0 2949 2950 #define TRANSA_DATA_M1 0xe0030 2951 #define TRANSA_DATA_N1 0xe0034 2952 #define TRANSA_DATA_M2 0xe0038 2953 #define TRANSA_DATA_N2 0xe003c 2954 #define TRANSA_DP_LINK_M1 0xe0040 2955 #define TRANSA_DP_LINK_N1 0xe0044 2956 #define TRANSA_DP_LINK_M2 0xe0048 2957 #define TRANSA_DP_LINK_N2 0xe004c 2958 2959 #define TRANS_HTOTAL_B 0xe1000 2960 #define TRANS_HBLANK_B 0xe1004 2961 #define TRANS_HSYNC_B 0xe1008 2962 #define TRANS_VTOTAL_B 0xe100c 2963 #define TRANS_VBLANK_B 0xe1010 2964 #define TRANS_VSYNC_B 0xe1014 2965 2966 #define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B) 2967 #define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B) 2968 #define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B) 2969 #define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B) 2970 #define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B) 2971 #define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B) 2972 2973 #define TRANSB_DATA_M1 0xe1030 2974 #define TRANSB_DATA_N1 0xe1034 2975 #define TRANSB_DATA_M2 0xe1038 2976 #define TRANSB_DATA_N2 0xe103c 2977 #define TRANSB_DP_LINK_M1 0xe1040 2978 #define TRANSB_DP_LINK_N1 0xe1044 2979 #define TRANSB_DP_LINK_M2 0xe1048 2980 #define TRANSB_DP_LINK_N2 0xe104c 2981 2982 #define TRANSACONF 0xf0008 2983 #define TRANSBCONF 0xf1008 2984 #define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF) 2985 #define TRANS_DISABLE (0<<31) 2986 #define TRANS_ENABLE (1<<31) 2987 #define TRANS_STATE_MASK (1<<30) 2988 #define TRANS_STATE_DISABLE (0<<30) 2989 #define TRANS_STATE_ENABLE (1<<30) 2990 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 2991 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 2992 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 2993 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 2994 #define TRANS_DP_AUDIO_ONLY (1<<26) 2995 #define TRANS_DP_VIDEO_AUDIO (0<<26) 2996 #define TRANS_PROGRESSIVE (0<<21) 2997 #define TRANS_8BPC (0<<5) 2998 #define TRANS_10BPC (1<<5) 2999 #define TRANS_6BPC (2<<5) 3000 #define TRANS_12BPC (3<<5) 3001 3002 #define FDI_RXA_CHICKEN 0xc200c 3003 #define FDI_RXB_CHICKEN 0xc2010 3004 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 3005 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN) 3006 3007 #define SOUTH_DSPCLK_GATE_D 0xc2020 3008 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3009 3010 /* CPU: FDI_TX */ 3011 #define FDI_TXA_CTL 0x60100 3012 #define FDI_TXB_CTL 0x61100 3013 #define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL) 3014 #define FDI_TX_DISABLE (0<<31) 3015 #define FDI_TX_ENABLE (1<<31) 3016 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3017 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3018 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3019 #define FDI_LINK_TRAIN_NONE (3<<28) 3020 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3021 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3022 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3023 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3024 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3025 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3026 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3027 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3028 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3029 SNB has different settings. */ 3030 /* SNB A-stepping */ 3031 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3032 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3033 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3034 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3035 /* SNB B-stepping */ 3036 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3037 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3038 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3039 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3040 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3041 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3042 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3043 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3044 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3045 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3046 /* Ironlake: hardwired to 1 */ 3047 #define FDI_TX_PLL_ENABLE (1<<14) 3048 /* both Tx and Rx */ 3049 #define FDI_SCRAMBLING_ENABLE (0<<7) 3050 #define FDI_SCRAMBLING_DISABLE (1<<7) 3051 3052 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3053 #define FDI_RXA_CTL 0xf000c 3054 #define FDI_RXB_CTL 0xf100c 3055 #define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL) 3056 #define FDI_RX_ENABLE (1<<31) 3057 /* train, dp width same as FDI_TX */ 3058 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3059 #define FDI_8BPC (0<<16) 3060 #define FDI_10BPC (1<<16) 3061 #define FDI_6BPC (2<<16) 3062 #define FDI_12BPC (3<<16) 3063 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3064 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3065 #define FDI_RX_PLL_ENABLE (1<<13) 3066 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3067 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3068 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3069 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3070 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3071 #define FDI_PCDCLK (1<<4) 3072 /* CPT */ 3073 #define FDI_AUTO_TRAINING (1<<10) 3074 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3075 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3076 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3077 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3078 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3079 3080 #define FDI_RXA_MISC 0xf0010 3081 #define FDI_RXB_MISC 0xf1010 3082 #define FDI_RXA_TUSIZE1 0xf0030 3083 #define FDI_RXA_TUSIZE2 0xf0038 3084 #define FDI_RXB_TUSIZE1 0xf1030 3085 #define FDI_RXB_TUSIZE2 0xf1038 3086 #define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC) 3087 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1) 3088 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2) 3089 3090 /* FDI_RX interrupt register format */ 3091 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3092 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3093 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3094 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3095 #define FDI_RX_FS_CODE_ERR (1<<6) 3096 #define FDI_RX_FE_CODE_ERR (1<<5) 3097 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3098 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3099 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3100 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3101 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3102 3103 #define FDI_RXA_IIR 0xf0014 3104 #define FDI_RXA_IMR 0xf0018 3105 #define FDI_RXB_IIR 0xf1014 3106 #define FDI_RXB_IMR 0xf1018 3107 #define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR) 3108 #define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR) 3109 3110 #define FDI_PLL_CTL_1 0xfe000 3111 #define FDI_PLL_CTL_2 0xfe004 3112 3113 /* CRT */ 3114 #define PCH_ADPA 0xe1100 3115 #define ADPA_TRANS_SELECT_MASK (1<<30) 3116 #define ADPA_TRANS_A_SELECT 0 3117 #define ADPA_TRANS_B_SELECT (1<<30) 3118 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3119 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3120 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3121 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3122 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3123 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3124 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3125 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3126 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3127 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3128 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3129 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3130 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3131 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3132 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3133 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3134 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3135 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3136 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3137 3138 /* or SDVOB */ 3139 #define HDMIB 0xe1140 3140 #define PORT_ENABLE (1 << 31) 3141 #define TRANSCODER_A (0) 3142 #define TRANSCODER_B (1 << 30) 3143 #define COLOR_FORMAT_8bpc (0) 3144 #define COLOR_FORMAT_12bpc (3 << 26) 3145 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3146 #define SDVO_ENCODING (0) 3147 #define TMDS_ENCODING (2 << 10) 3148 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3149 /* CPT */ 3150 #define HDMI_MODE_SELECT (1 << 9) 3151 #define DVI_MODE_SELECT (0) 3152 #define SDVOB_BORDER_ENABLE (1 << 7) 3153 #define AUDIO_ENABLE (1 << 6) 3154 #define VSYNC_ACTIVE_HIGH (1 << 4) 3155 #define HSYNC_ACTIVE_HIGH (1 << 3) 3156 #define PORT_DETECTED (1 << 2) 3157 3158 /* PCH SDVOB multiplex with HDMIB */ 3159 #define PCH_SDVOB HDMIB 3160 3161 #define HDMIC 0xe1150 3162 #define HDMID 0xe1160 3163 3164 #define PCH_LVDS 0xe1180 3165 #define LVDS_DETECTED (1 << 1) 3166 3167 #define BLC_PWM_CPU_CTL2 0x48250 3168 #define PWM_ENABLE (1 << 31) 3169 #define PWM_PIPE_A (0 << 29) 3170 #define PWM_PIPE_B (1 << 29) 3171 #define BLC_PWM_CPU_CTL 0x48254 3172 3173 #define BLC_PWM_PCH_CTL1 0xc8250 3174 #define PWM_PCH_ENABLE (1 << 31) 3175 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3176 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3177 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3178 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3179 3180 #define BLC_PWM_PCH_CTL2 0xc8254 3181 3182 #define PCH_PP_STATUS 0xc7200 3183 #define PCH_PP_CONTROL 0xc7204 3184 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3185 #define EDP_FORCE_VDD (1 << 3) 3186 #define EDP_BLC_ENABLE (1 << 2) 3187 #define PANEL_POWER_RESET (1 << 1) 3188 #define PANEL_POWER_OFF (0 << 0) 3189 #define PANEL_POWER_ON (1 << 0) 3190 #define PCH_PP_ON_DELAYS 0xc7208 3191 #define EDP_PANEL (1 << 30) 3192 #define PCH_PP_OFF_DELAYS 0xc720c 3193 #define PCH_PP_DIVISOR 0xc7210 3194 3195 #define PCH_DP_B 0xe4100 3196 #define PCH_DPB_AUX_CH_CTL 0xe4110 3197 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3198 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3199 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3200 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3201 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3202 3203 #define PCH_DP_C 0xe4200 3204 #define PCH_DPC_AUX_CH_CTL 0xe4210 3205 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3206 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3207 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3208 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3209 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3210 3211 #define PCH_DP_D 0xe4300 3212 #define PCH_DPD_AUX_CH_CTL 0xe4310 3213 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3214 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3215 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3216 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3217 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3218 3219 /* CPT */ 3220 #define PORT_TRANS_A_SEL_CPT 0 3221 #define PORT_TRANS_B_SEL_CPT (1<<29) 3222 #define PORT_TRANS_C_SEL_CPT (2<<29) 3223 #define PORT_TRANS_SEL_MASK (3<<29) 3224 3225 #define TRANS_DP_CTL_A 0xe0300 3226 #define TRANS_DP_CTL_B 0xe1300 3227 #define TRANS_DP_CTL_C 0xe2300 3228 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) 3229 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3230 #define TRANS_DP_PORT_SEL_B (0<<29) 3231 #define TRANS_DP_PORT_SEL_C (1<<29) 3232 #define TRANS_DP_PORT_SEL_D (2<<29) 3233 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3234 #define TRANS_DP_AUDIO_ONLY (1<<26) 3235 #define TRANS_DP_ENH_FRAMING (1<<18) 3236 #define TRANS_DP_8BPC (0<<9) 3237 #define TRANS_DP_10BPC (1<<9) 3238 #define TRANS_DP_6BPC (2<<9) 3239 #define TRANS_DP_12BPC (3<<9) 3240 #define TRANS_DP_BPC_MASK (3<<9) 3241 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3242 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3243 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3244 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3245 #define TRANS_DP_SYNC_MASK (3<<3) 3246 3247 /* SNB eDP training params */ 3248 /* SNB A-stepping */ 3249 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3250 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3251 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3252 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3253 /* SNB B-stepping */ 3254 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3255 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3256 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3257 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3258 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3259 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3260 3261 #define FORCEWAKE 0xA18C 3262 #define FORCEWAKE_ACK 0x130090 3263 3264 #define GEN6_RPNSWREQ 0xA008 3265 #define GEN6_TURBO_DISABLE (1<<31) 3266 #define GEN6_FREQUENCY(x) ((x)<<25) 3267 #define GEN6_OFFSET(x) ((x)<<19) 3268 #define GEN6_AGGRESSIVE_TURBO (0<<15) 3269 #define GEN6_RC_VIDEO_FREQ 0xA00C 3270 #define GEN6_RC_CONTROL 0xA090 3271 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 3272 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 3273 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 3274 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 3275 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 3276 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 3277 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 3278 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3279 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3280 #define GEN6_RPSTAT1 0xA01C 3281 #define GEN6_RP_CONTROL 0xA024 3282 #define GEN6_RP_MEDIA_TURBO (1<<11) 3283 #define GEN6_RP_USE_NORMAL_FREQ (1<<9) 3284 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 3285 #define GEN6_RP_ENABLE (1<<7) 3286 #define GEN6_RP_UP_BUSY_MAX (0x2<<3) 3287 #define GEN6_RP_DOWN_BUSY_MIN (0x2<<0) 3288 #define GEN6_RP_UP_THRESHOLD 0xA02C 3289 #define GEN6_RP_DOWN_THRESHOLD 0xA030 3290 #define GEN6_RP_UP_EI 0xA068 3291 #define GEN6_RP_DOWN_EI 0xA06C 3292 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 3293 #define GEN6_RC_STATE 0xA094 3294 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 3295 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 3296 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 3297 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3298 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3299 #define GEN6_RC_SLEEP 0xA0B0 3300 #define GEN6_RC1e_THRESHOLD 0xA0B4 3301 #define GEN6_RC6_THRESHOLD 0xA0B8 3302 #define GEN6_RC6p_THRESHOLD 0xA0BC 3303 #define GEN6_RC6pp_THRESHOLD 0xA0C0 3304 #define GEN6_PMINTRMSK 0xA168 3305 3306 #define GEN6_PMISR 0x44020 3307 #define GEN6_PMIMR 0x44024 3308 #define GEN6_PMIIR 0x44028 3309 #define GEN6_PMIER 0x4402C 3310 #define GEN6_PM_MBOX_EVENT (1<<25) 3311 #define GEN6_PM_THERMAL_EVENT (1<<24) 3312 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 3313 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 3314 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 3315 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 3316 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 3317 3318 #define GEN6_PCODE_MAILBOX 0x138124 3319 #define GEN6_PCODE_READY (1<<31) 3320 #define GEN6_READ_OC_PARAMS 0xc 3321 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x9 3322 #define GEN6_PCODE_DATA 0x138128 3323 3324 #endif /* _I915_REG_H_ */ 3325