1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 #define _PLANE(plane, a, b) _PIPE(plane, a, b) 30 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ 33 (pipe) == PIPE_B ? (b) : (c)) 34 35 #define _MASKED_FIELD(mask, value) ({ \ 36 if (__builtin_constant_p(mask)) \ 37 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 38 if (__builtin_constant_p(value)) \ 39 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 40 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 41 BUILD_BUG_ON_MSG((value) & ~(mask), \ 42 "Incorrect value for mask"); \ 43 (mask) << 16 | (value); }) 44 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 45 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 46 47 48 49 /* PCI config space */ 50 51 #define HPLLCC 0xc0 /* 855 only */ 52 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 53 #define GC_CLOCK_133_200 (0 << 0) 54 #define GC_CLOCK_100_200 (1 << 0) 55 #define GC_CLOCK_100_133 (2 << 0) 56 #define GC_CLOCK_166_250 (3 << 0) 57 #define GCFGC2 0xda 58 #define GCFGC 0xf0 /* 915+ only */ 59 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 60 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 61 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 62 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 63 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 64 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 65 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 66 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 67 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 68 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 69 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 70 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 71 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 72 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 73 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 74 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 75 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 76 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 77 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 78 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 79 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 80 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 81 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 82 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 83 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 84 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 85 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 86 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 87 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 88 #define GCDGMBUS 0xcc 89 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 90 91 92 /* Graphics reset regs */ 93 #define I915_GDRST 0xc0 /* PCI config register */ 94 #define GRDOM_FULL (0<<2) 95 #define GRDOM_RENDER (1<<2) 96 #define GRDOM_MEDIA (3<<2) 97 #define GRDOM_MASK (3<<2) 98 #define GRDOM_RESET_STATUS (1<<1) 99 #define GRDOM_RESET_ENABLE (1<<0) 100 101 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 102 #define ILK_GRDOM_FULL (0<<1) 103 #define ILK_GRDOM_RENDER (1<<1) 104 #define ILK_GRDOM_MEDIA (3<<1) 105 #define ILK_GRDOM_MASK (3<<1) 106 #define ILK_GRDOM_RESET_ENABLE (1<<0) 107 108 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 109 #define GEN6_MBC_SNPCR_SHIFT 21 110 #define GEN6_MBC_SNPCR_MASK (3<<21) 111 #define GEN6_MBC_SNPCR_MAX (0<<21) 112 #define GEN6_MBC_SNPCR_MED (1<<21) 113 #define GEN6_MBC_SNPCR_LOW (2<<21) 114 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 115 116 #define VLV_G3DCTL 0x9024 117 #define VLV_GSCKGCTL 0x9028 118 119 #define GEN6_MBCTL 0x0907c 120 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 121 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 122 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 123 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 124 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 125 126 #define GEN6_GDRST 0x941c 127 #define GEN6_GRDOM_FULL (1 << 0) 128 #define GEN6_GRDOM_RENDER (1 << 1) 129 #define GEN6_GRDOM_MEDIA (1 << 2) 130 #define GEN6_GRDOM_BLT (1 << 3) 131 132 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 133 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 134 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 135 #define PP_DIR_DCLV_2G 0xffffffff 136 137 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) 138 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) 139 140 #define GAM_ECOCHK 0x4090 141 #define ECOCHK_SNB_BIT (1<<10) 142 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 143 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 144 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 145 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 146 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 147 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 148 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 149 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 150 151 #define GAC_ECO_BITS 0x14090 152 #define ECOBITS_SNB_BIT (1<<13) 153 #define ECOBITS_PPGTT_CACHE64B (3<<8) 154 #define ECOBITS_PPGTT_CACHE4B (0<<8) 155 156 #define GAB_CTL 0x24000 157 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 158 159 #define GEN7_BIOS_RESERVED 0x1082C0 160 #define GEN7_BIOS_RESERVED_1M (0 << 5) 161 #define GEN7_BIOS_RESERVED_256K (1 << 5) 162 #define GEN8_BIOS_RESERVED_SHIFT 7 163 #define GEN7_BIOS_RESERVED_MASK 0x1 164 #define GEN8_BIOS_RESERVED_MASK 0x3 165 166 167 /* VGA stuff */ 168 169 #define VGA_ST01_MDA 0x3ba 170 #define VGA_ST01_CGA 0x3da 171 172 #define VGA_MSR_WRITE 0x3c2 173 #define VGA_MSR_READ 0x3cc 174 #define VGA_MSR_MEM_EN (1<<1) 175 #define VGA_MSR_CGA_MODE (1<<0) 176 177 #define VGA_SR_INDEX 0x3c4 178 #define SR01 1 179 #define VGA_SR_DATA 0x3c5 180 181 #define VGA_AR_INDEX 0x3c0 182 #define VGA_AR_VID_EN (1<<5) 183 #define VGA_AR_DATA_WRITE 0x3c0 184 #define VGA_AR_DATA_READ 0x3c1 185 186 #define VGA_GR_INDEX 0x3ce 187 #define VGA_GR_DATA 0x3cf 188 /* GR05 */ 189 #define VGA_GR_MEM_READ_MODE_SHIFT 3 190 #define VGA_GR_MEM_READ_MODE_PLANE 1 191 /* GR06 */ 192 #define VGA_GR_MEM_MODE_MASK 0xc 193 #define VGA_GR_MEM_MODE_SHIFT 2 194 #define VGA_GR_MEM_A0000_AFFFF 0 195 #define VGA_GR_MEM_A0000_BFFFF 1 196 #define VGA_GR_MEM_B0000_B7FFF 2 197 #define VGA_GR_MEM_B0000_BFFFF 3 198 199 #define VGA_DACMASK 0x3c6 200 #define VGA_DACRX 0x3c7 201 #define VGA_DACWX 0x3c8 202 #define VGA_DACDATA 0x3c9 203 204 #define VGA_CR_INDEX_MDA 0x3b4 205 #define VGA_CR_DATA_MDA 0x3b5 206 #define VGA_CR_INDEX_CGA 0x3d4 207 #define VGA_CR_DATA_CGA 0x3d5 208 209 /* 210 * Instruction field definitions used by the command parser 211 */ 212 #define INSTR_CLIENT_SHIFT 29 213 #define INSTR_CLIENT_MASK 0xE0000000 214 #define INSTR_MI_CLIENT 0x0 215 #define INSTR_BC_CLIENT 0x2 216 #define INSTR_RC_CLIENT 0x3 217 #define INSTR_SUBCLIENT_SHIFT 27 218 #define INSTR_SUBCLIENT_MASK 0x18000000 219 #define INSTR_MEDIA_SUBCLIENT 0x2 220 221 /* 222 * Memory interface instructions used by the kernel 223 */ 224 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 225 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 226 #define MI_GLOBAL_GTT (1<<22) 227 228 #define MI_NOOP MI_INSTR(0, 0) 229 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 230 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 231 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 232 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 233 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 234 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 235 #define MI_FLUSH MI_INSTR(0x04, 0) 236 #define MI_READ_FLUSH (1 << 0) 237 #define MI_EXE_FLUSH (1 << 1) 238 #define MI_NO_WRITE_FLUSH (1 << 2) 239 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 240 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 241 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 242 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 243 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 244 #define MI_ARB_ENABLE (1<<0) 245 #define MI_ARB_DISABLE (0<<0) 246 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 247 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 248 #define MI_SUSPEND_FLUSH_EN (1<<0) 249 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 250 #define MI_OVERLAY_CONTINUE (0x0<<21) 251 #define MI_OVERLAY_ON (0x1<<21) 252 #define MI_OVERLAY_OFF (0x2<<21) 253 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 254 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 255 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 256 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 257 /* IVB has funny definitions for which plane to flip. */ 258 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 259 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 260 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 261 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 262 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 263 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 264 /* SKL ones */ 265 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 266 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 267 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 268 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 269 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 270 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 271 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 272 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 273 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 274 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 275 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 276 #define MI_SEMAPHORE_UPDATE (1<<21) 277 #define MI_SEMAPHORE_COMPARE (1<<20) 278 #define MI_SEMAPHORE_REGISTER (1<<18) 279 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 280 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 281 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 282 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 283 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 284 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 285 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 286 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 287 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 288 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 289 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 290 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 291 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 292 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 293 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 294 #define MI_MM_SPACE_GTT (1<<8) 295 #define MI_MM_SPACE_PHYSICAL (0<<8) 296 #define MI_SAVE_EXT_STATE_EN (1<<3) 297 #define MI_RESTORE_EXT_STATE_EN (1<<2) 298 #define MI_FORCE_RESTORE (1<<1) 299 #define MI_RESTORE_INHIBIT (1<<0) 300 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 301 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 302 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 303 #define MI_SEMAPHORE_POLL (1<<15) 304 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 305 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 306 #define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) 307 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 308 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 309 #define MI_STORE_DWORD_INDEX_SHIFT 2 310 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 311 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 312 * simply ignores the register load under certain conditions. 313 * - One can actually load arbitrary many arbitrary registers: Simply issue x 314 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 315 */ 316 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 317 #define MI_LRI_FORCE_POSTED (1<<12) 318 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) 319 #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) 320 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 321 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 322 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 323 #define MI_INVALIDATE_TLB (1<<18) 324 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 325 #define MI_FLUSH_DW_OP_MASK (3<<14) 326 #define MI_FLUSH_DW_NOTIFY (1<<8) 327 #define MI_INVALIDATE_BSD (1<<7) 328 #define MI_FLUSH_DW_USE_GTT (1<<2) 329 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 330 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 331 #define MI_BATCH_NON_SECURE (1) 332 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 333 #define MI_BATCH_NON_SECURE_I965 (1<<8) 334 #define MI_BATCH_PPGTT_HSW (1<<8) 335 #define MI_BATCH_NON_SECURE_HSW (1<<13) 336 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 337 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 338 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 339 340 #define MI_PREDICATE_SRC0 (0x2400) 341 #define MI_PREDICATE_SRC1 (0x2408) 342 343 #define MI_PREDICATE_RESULT_2 (0x2214) 344 #define LOWER_SLICE_ENABLED (1<<0) 345 #define LOWER_SLICE_DISABLED (0<<0) 346 347 /* 348 * 3D instructions used by the kernel 349 */ 350 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 351 352 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 353 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 354 #define SC_UPDATE_SCISSOR (0x1<<1) 355 #define SC_ENABLE_MASK (0x1<<0) 356 #define SC_ENABLE (0x1<<0) 357 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 358 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 359 #define SCI_YMIN_MASK (0xffff<<16) 360 #define SCI_XMIN_MASK (0xffff<<0) 361 #define SCI_YMAX_MASK (0xffff<<16) 362 #define SCI_XMAX_MASK (0xffff<<0) 363 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 364 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 365 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 366 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 367 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 368 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 369 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 370 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 371 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 372 373 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 374 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 375 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 376 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 377 #define BLT_WRITE_A (2<<20) 378 #define BLT_WRITE_RGB (1<<20) 379 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 380 #define BLT_DEPTH_8 (0<<24) 381 #define BLT_DEPTH_16_565 (1<<24) 382 #define BLT_DEPTH_16_1555 (2<<24) 383 #define BLT_DEPTH_32 (3<<24) 384 #define BLT_ROP_SRC_COPY (0xcc<<16) 385 #define BLT_ROP_COLOR_COPY (0xf0<<16) 386 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 387 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 388 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 389 #define ASYNC_FLIP (1<<22) 390 #define DISPLAY_PLANE_A (0<<20) 391 #define DISPLAY_PLANE_B (1<<20) 392 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 393 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 394 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 395 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 396 #define PIPE_CONTROL_CS_STALL (1<<20) 397 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 398 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 399 #define PIPE_CONTROL_QW_WRITE (1<<14) 400 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 401 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 402 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 403 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 404 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 405 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 406 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 407 #define PIPE_CONTROL_NOTIFY (1<<8) 408 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 409 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 410 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 411 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 412 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 413 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 414 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 415 416 /* 417 * Commands used only by the command parser 418 */ 419 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 420 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 421 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 422 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 423 #define MI_PREDICATE MI_INSTR(0x0C, 0) 424 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 425 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 426 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 427 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 428 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 429 #define MI_CLFLUSH MI_INSTR(0x27, 0) 430 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 431 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 432 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) 433 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 434 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 435 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 436 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 437 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 438 439 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 440 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 441 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 442 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 443 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 444 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 445 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 446 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 447 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 448 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 449 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 450 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 451 452 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 453 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 454 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 455 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 456 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 457 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 458 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 459 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 460 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 461 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 462 463 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 464 465 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 466 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 467 468 /* 469 * Registers used only by the command parser 470 */ 471 #define BCS_SWCTRL 0x22200 472 473 #define HS_INVOCATION_COUNT 0x2300 474 #define DS_INVOCATION_COUNT 0x2308 475 #define IA_VERTICES_COUNT 0x2310 476 #define IA_PRIMITIVES_COUNT 0x2318 477 #define VS_INVOCATION_COUNT 0x2320 478 #define GS_INVOCATION_COUNT 0x2328 479 #define GS_PRIMITIVES_COUNT 0x2330 480 #define CL_INVOCATION_COUNT 0x2338 481 #define CL_PRIMITIVES_COUNT 0x2340 482 #define PS_INVOCATION_COUNT 0x2348 483 #define PS_DEPTH_COUNT 0x2350 484 485 /* There are the 4 64-bit counter registers, one for each stream output */ 486 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) 487 488 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) 489 490 #define GEN7_3DPRIM_END_OFFSET 0x2420 491 #define GEN7_3DPRIM_START_VERTEX 0x2430 492 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 493 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 494 #define GEN7_3DPRIM_START_INSTANCE 0x243C 495 #define GEN7_3DPRIM_BASE_VERTEX 0x2440 496 497 #define OACONTROL 0x2360 498 499 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 500 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 501 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ 502 _GEN7_PIPEA_DE_LOAD_SL, \ 503 _GEN7_PIPEB_DE_LOAD_SL) 504 505 /* 506 * Reset registers 507 */ 508 #define DEBUG_RESET_I830 0x6070 509 #define DEBUG_RESET_FULL (1<<7) 510 #define DEBUG_RESET_RENDER (1<<8) 511 #define DEBUG_RESET_DISPLAY (1<<9) 512 513 /* 514 * IOSF sideband 515 */ 516 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 517 #define IOSF_DEVFN_SHIFT 24 518 #define IOSF_OPCODE_SHIFT 16 519 #define IOSF_PORT_SHIFT 8 520 #define IOSF_BYTE_ENABLES_SHIFT 4 521 #define IOSF_BAR_SHIFT 1 522 #define IOSF_SB_BUSY (1<<0) 523 #define IOSF_PORT_BUNIT 0x3 524 #define IOSF_PORT_PUNIT 0x4 525 #define IOSF_PORT_NC 0x11 526 #define IOSF_PORT_DPIO 0x12 527 #define IOSF_PORT_DPIO_2 0x1a 528 #define IOSF_PORT_GPIO_NC 0x13 529 #define IOSF_PORT_CCK 0x14 530 #define IOSF_PORT_CCU 0xA9 531 #define IOSF_PORT_GPS_CORE 0x48 532 #define IOSF_PORT_FLISDSI 0x1B 533 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 534 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 535 536 /* See configdb bunit SB addr map */ 537 #define BUNIT_REG_BISOC 0x11 538 539 #define PUNIT_REG_DSPFREQ 0x36 540 #define DSPFREQSTAT_SHIFT_CHV 24 541 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 542 #define DSPFREQGUAR_SHIFT_CHV 8 543 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 544 #define DSPFREQSTAT_SHIFT 30 545 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 546 #define DSPFREQGUAR_SHIFT 14 547 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 548 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 549 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 550 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 551 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 552 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 553 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 554 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 555 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 556 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 557 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 558 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 559 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 560 561 /* See the PUNIT HAS v0.8 for the below bits */ 562 enum punit_power_well { 563 PUNIT_POWER_WELL_RENDER = 0, 564 PUNIT_POWER_WELL_MEDIA = 1, 565 PUNIT_POWER_WELL_DISP2D = 3, 566 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 567 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 568 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 569 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 570 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 571 PUNIT_POWER_WELL_DPIO_RX0 = 10, 572 PUNIT_POWER_WELL_DPIO_RX1 = 11, 573 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 574 /* FIXME: guesswork below */ 575 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, 576 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, 577 PUNIT_POWER_WELL_DPIO_RX2 = 15, 578 579 PUNIT_POWER_WELL_NUM, 580 }; 581 582 #define PUNIT_REG_PWRGT_CTRL 0x60 583 #define PUNIT_REG_PWRGT_STATUS 0x61 584 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 585 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 586 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 587 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 588 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 589 590 #define PUNIT_REG_GPU_LFM 0xd3 591 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 592 #define PUNIT_REG_GPU_FREQ_STS 0xd8 593 #define GPLLENABLE (1<<4) 594 #define GENFREQSTATUS (1<<0) 595 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 596 #define PUNIT_REG_CZ_TIMESTAMP 0xce 597 598 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 599 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 600 601 #define PUNIT_GPU_STATUS_REG 0xdb 602 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 603 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 604 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 605 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 606 607 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 608 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 609 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 610 611 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 612 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 613 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 614 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 615 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 616 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 617 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 618 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 619 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 620 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 621 622 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 623 #define VLV_RP_UP_EI_THRESHOLD 90 624 #define VLV_RP_DOWN_EI_THRESHOLD 70 625 #define VLV_INT_COUNT_FOR_DOWN_EI 5 626 627 /* vlv2 north clock has */ 628 #define CCK_FUSE_REG 0x8 629 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 630 #define CCK_REG_DSI_PLL_FUSE 0x44 631 #define CCK_REG_DSI_PLL_CONTROL 0x48 632 #define DSI_PLL_VCO_EN (1 << 31) 633 #define DSI_PLL_LDO_GATE (1 << 30) 634 #define DSI_PLL_P1_POST_DIV_SHIFT 17 635 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 636 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 637 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 638 #define DSI_PLL_MUX_MASK (3 << 9) 639 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 640 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 641 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 642 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 643 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 644 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 645 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 646 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 647 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 648 #define DSI_PLL_LOCK (1 << 0) 649 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 650 #define DSI_PLL_LFSR (1 << 31) 651 #define DSI_PLL_FRACTION_EN (1 << 30) 652 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 653 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 654 #define DSI_PLL_USYNC_CNT_SHIFT 18 655 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 656 #define DSI_PLL_N1_DIV_SHIFT 16 657 #define DSI_PLL_N1_DIV_MASK (3 << 16) 658 #define DSI_PLL_M1_DIV_SHIFT 0 659 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 660 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 661 #define DISPLAY_TRUNK_FORCE_ON (1 << 17) 662 #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) 663 #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) 664 #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 665 #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) 666 667 /** 668 * DOC: DPIO 669 * 670 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI 671 * ports. DPIO is the name given to such a display PHY. These PHYs 672 * don't follow the standard programming model using direct MMIO 673 * registers, and instead their registers must be accessed trough IOSF 674 * sideband. VLV has one such PHY for driving ports B and C, and CHV 675 * adds another PHY for driving port D. Each PHY responds to specific 676 * IOSF-SB port. 677 * 678 * Each display PHY is made up of one or two channels. Each channel 679 * houses a common lane part which contains the PLL and other common 680 * logic. CH0 common lane also contains the IOSF-SB logic for the 681 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 682 * must be running when any DPIO registers are accessed. 683 * 684 * In addition to having their own registers, the PHYs are also 685 * controlled through some dedicated signals from the display 686 * controller. These include PLL reference clock enable, PLL enable, 687 * and CRI clock selection, for example. 688 * 689 * Eeach channel also has two splines (also called data lanes), and 690 * each spline is made up of one Physical Access Coding Sub-Layer 691 * (PCS) block and two TX lanes. So each channel has two PCS blocks 692 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 693 * data/clock pairs depending on the output type. 694 * 695 * Additionally the PHY also contains an AUX lane with AUX blocks 696 * for each channel. This is used for DP AUX communication, but 697 * this fact isn't really relevant for the driver since AUX is 698 * controlled from the display controller side. No DPIO registers 699 * need to be accessed during AUX communication, 700 * 701 * Generally the common lane corresponds to the pipe and 702 * the spline (PCS/TX) corresponds to the port. 703 * 704 * For dual channel PHY (VLV/CHV): 705 * 706 * pipe A == CMN/PLL/REF CH0 707 * 708 * pipe B == CMN/PLL/REF CH1 709 * 710 * port B == PCS/TX CH0 711 * 712 * port C == PCS/TX CH1 713 * 714 * This is especially important when we cross the streams 715 * ie. drive port B with pipe B, or port C with pipe A. 716 * 717 * For single channel PHY (CHV): 718 * 719 * pipe C == CMN/PLL/REF CH0 720 * 721 * port D == PCS/TX CH0 722 * 723 * Note: digital port B is DDI0, digital port C is DDI1, 724 * digital port D is DDI2 725 */ 726 /* 727 * Dual channel PHY (VLV/CHV) 728 * --------------------------------- 729 * | CH0 | CH1 | 730 * | CMN/PLL/REF | CMN/PLL/REF | 731 * |---------------|---------------| Display PHY 732 * | PCS01 | PCS23 | PCS01 | PCS23 | 733 * |-------|-------|-------|-------| 734 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 735 * --------------------------------- 736 * | DDI0 | DDI1 | DP/HDMI ports 737 * --------------------------------- 738 * 739 * Single channel PHY (CHV) 740 * ----------------- 741 * | CH0 | 742 * | CMN/PLL/REF | 743 * |---------------| Display PHY 744 * | PCS01 | PCS23 | 745 * |-------|-------| 746 * |TX0|TX1|TX2|TX3| 747 * ----------------- 748 * | DDI2 | DP/HDMI port 749 * ----------------- 750 */ 751 #define DPIO_DEVFN 0 752 753 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) 754 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 755 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 756 #define DPIO_SFR_BYPASS (1<<1) 757 #define DPIO_CMNRST (1<<0) 758 759 #define DPIO_PHY(pipe) ((pipe) >> 1) 760 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 761 762 /* 763 * Per pipe/PLL DPIO regs 764 */ 765 #define _VLV_PLL_DW3_CH0 0x800c 766 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 767 #define DPIO_POST_DIV_DAC 0 768 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 769 #define DPIO_POST_DIV_LVDS1 2 770 #define DPIO_POST_DIV_LVDS2 3 771 #define DPIO_K_SHIFT (24) /* 4 bits */ 772 #define DPIO_P1_SHIFT (21) /* 3 bits */ 773 #define DPIO_P2_SHIFT (16) /* 5 bits */ 774 #define DPIO_N_SHIFT (12) /* 4 bits */ 775 #define DPIO_ENABLE_CALIBRATION (1<<11) 776 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 777 #define DPIO_M2DIV_MASK 0xff 778 #define _VLV_PLL_DW3_CH1 0x802c 779 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 780 781 #define _VLV_PLL_DW5_CH0 0x8014 782 #define DPIO_REFSEL_OVERRIDE 27 783 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 784 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 785 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 786 #define DPIO_PLL_REFCLK_SEL_MASK 3 787 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 788 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 789 #define _VLV_PLL_DW5_CH1 0x8034 790 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 791 792 #define _VLV_PLL_DW7_CH0 0x801c 793 #define _VLV_PLL_DW7_CH1 0x803c 794 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 795 796 #define _VLV_PLL_DW8_CH0 0x8040 797 #define _VLV_PLL_DW8_CH1 0x8060 798 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 799 800 #define VLV_PLL_DW9_BCAST 0xc044 801 #define _VLV_PLL_DW9_CH0 0x8044 802 #define _VLV_PLL_DW9_CH1 0x8064 803 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 804 805 #define _VLV_PLL_DW10_CH0 0x8048 806 #define _VLV_PLL_DW10_CH1 0x8068 807 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 808 809 #define _VLV_PLL_DW11_CH0 0x804c 810 #define _VLV_PLL_DW11_CH1 0x806c 811 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 812 813 /* Spec for ref block start counts at DW10 */ 814 #define VLV_REF_DW13 0x80ac 815 816 #define VLV_CMN_DW0 0x8100 817 818 /* 819 * Per DDI channel DPIO regs 820 */ 821 822 #define _VLV_PCS_DW0_CH0 0x8200 823 #define _VLV_PCS_DW0_CH1 0x8400 824 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 825 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 826 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) 827 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) 828 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 829 830 #define _VLV_PCS01_DW0_CH0 0x200 831 #define _VLV_PCS23_DW0_CH0 0x400 832 #define _VLV_PCS01_DW0_CH1 0x2600 833 #define _VLV_PCS23_DW0_CH1 0x2800 834 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 835 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 836 837 #define _VLV_PCS_DW1_CH0 0x8204 838 #define _VLV_PCS_DW1_CH1 0x8404 839 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 840 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 841 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 842 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 843 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 844 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 845 846 #define _VLV_PCS01_DW1_CH0 0x204 847 #define _VLV_PCS23_DW1_CH0 0x404 848 #define _VLV_PCS01_DW1_CH1 0x2604 849 #define _VLV_PCS23_DW1_CH1 0x2804 850 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 851 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 852 853 #define _VLV_PCS_DW8_CH0 0x8220 854 #define _VLV_PCS_DW8_CH1 0x8420 855 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 856 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 857 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 858 859 #define _VLV_PCS01_DW8_CH0 0x0220 860 #define _VLV_PCS23_DW8_CH0 0x0420 861 #define _VLV_PCS01_DW8_CH1 0x2620 862 #define _VLV_PCS23_DW8_CH1 0x2820 863 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 864 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 865 866 #define _VLV_PCS_DW9_CH0 0x8224 867 #define _VLV_PCS_DW9_CH1 0x8424 868 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) 869 #define DPIO_PCS_TX2MARGIN_000 (0<<13) 870 #define DPIO_PCS_TX2MARGIN_101 (1<<13) 871 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) 872 #define DPIO_PCS_TX1MARGIN_000 (0<<10) 873 #define DPIO_PCS_TX1MARGIN_101 (1<<10) 874 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 875 876 #define _VLV_PCS01_DW9_CH0 0x224 877 #define _VLV_PCS23_DW9_CH0 0x424 878 #define _VLV_PCS01_DW9_CH1 0x2624 879 #define _VLV_PCS23_DW9_CH1 0x2824 880 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 881 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 882 883 #define _CHV_PCS_DW10_CH0 0x8228 884 #define _CHV_PCS_DW10_CH1 0x8428 885 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 886 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 887 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) 888 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) 889 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) 890 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) 891 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) 892 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) 893 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 894 895 #define _VLV_PCS01_DW10_CH0 0x0228 896 #define _VLV_PCS23_DW10_CH0 0x0428 897 #define _VLV_PCS01_DW10_CH1 0x2628 898 #define _VLV_PCS23_DW10_CH1 0x2828 899 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 900 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 901 902 #define _VLV_PCS_DW11_CH0 0x822c 903 #define _VLV_PCS_DW11_CH1 0x842c 904 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) 905 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) 906 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) 907 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 908 909 #define _VLV_PCS01_DW11_CH0 0x022c 910 #define _VLV_PCS23_DW11_CH0 0x042c 911 #define _VLV_PCS01_DW11_CH1 0x262c 912 #define _VLV_PCS23_DW11_CH1 0x282c 913 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 914 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 915 916 #define _VLV_PCS_DW12_CH0 0x8230 917 #define _VLV_PCS_DW12_CH1 0x8430 918 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 919 920 #define _VLV_PCS_DW14_CH0 0x8238 921 #define _VLV_PCS_DW14_CH1 0x8438 922 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 923 924 #define _VLV_PCS_DW23_CH0 0x825c 925 #define _VLV_PCS_DW23_CH1 0x845c 926 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 927 928 #define _VLV_TX_DW2_CH0 0x8288 929 #define _VLV_TX_DW2_CH1 0x8488 930 #define DPIO_SWING_MARGIN000_SHIFT 16 931 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 932 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 933 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 934 935 #define _VLV_TX_DW3_CH0 0x828c 936 #define _VLV_TX_DW3_CH1 0x848c 937 /* The following bit for CHV phy */ 938 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 939 #define DPIO_SWING_MARGIN101_SHIFT 16 940 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 941 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 942 943 #define _VLV_TX_DW4_CH0 0x8290 944 #define _VLV_TX_DW4_CH1 0x8490 945 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 946 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 947 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 948 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 949 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 950 951 #define _VLV_TX3_DW4_CH0 0x690 952 #define _VLV_TX3_DW4_CH1 0x2a90 953 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 954 955 #define _VLV_TX_DW5_CH0 0x8294 956 #define _VLV_TX_DW5_CH1 0x8494 957 #define DPIO_TX_OCALINIT_EN (1<<31) 958 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 959 960 #define _VLV_TX_DW11_CH0 0x82ac 961 #define _VLV_TX_DW11_CH1 0x84ac 962 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 963 964 #define _VLV_TX_DW14_CH0 0x82b8 965 #define _VLV_TX_DW14_CH1 0x84b8 966 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 967 968 /* CHV dpPhy registers */ 969 #define _CHV_PLL_DW0_CH0 0x8000 970 #define _CHV_PLL_DW0_CH1 0x8180 971 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 972 973 #define _CHV_PLL_DW1_CH0 0x8004 974 #define _CHV_PLL_DW1_CH1 0x8184 975 #define DPIO_CHV_N_DIV_SHIFT 8 976 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 977 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 978 979 #define _CHV_PLL_DW2_CH0 0x8008 980 #define _CHV_PLL_DW2_CH1 0x8188 981 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 982 983 #define _CHV_PLL_DW3_CH0 0x800c 984 #define _CHV_PLL_DW3_CH1 0x818c 985 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 986 #define DPIO_CHV_FIRST_MOD (0 << 8) 987 #define DPIO_CHV_SECOND_MOD (1 << 8) 988 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 989 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 990 991 #define _CHV_PLL_DW6_CH0 0x8018 992 #define _CHV_PLL_DW6_CH1 0x8198 993 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 994 #define DPIO_CHV_INT_COEFF_SHIFT 8 995 #define DPIO_CHV_PROP_COEFF_SHIFT 0 996 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 997 998 #define _CHV_CMN_DW5_CH0 0x8114 999 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1000 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1001 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1002 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1003 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1004 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1005 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1006 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1007 1008 #define _CHV_CMN_DW13_CH0 0x8134 1009 #define _CHV_CMN_DW0_CH1 0x8080 1010 #define DPIO_CHV_S1_DIV_SHIFT 21 1011 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1012 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1013 #define DPIO_CHV_K_DIV_SHIFT 4 1014 #define DPIO_PLL_FREQLOCK (1 << 1) 1015 #define DPIO_PLL_LOCK (1 << 0) 1016 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1017 1018 #define _CHV_CMN_DW14_CH0 0x8138 1019 #define _CHV_CMN_DW1_CH1 0x8084 1020 #define DPIO_AFC_RECAL (1 << 14) 1021 #define DPIO_DCLKP_EN (1 << 13) 1022 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1023 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1024 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1025 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1026 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1027 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1028 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1029 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1030 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1031 1032 #define _CHV_CMN_DW19_CH0 0x814c 1033 #define _CHV_CMN_DW6_CH1 0x8098 1034 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1035 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1036 1037 #define CHV_CMN_DW30 0x8178 1038 #define DPIO_LRC_BYPASS (1 << 3) 1039 1040 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1041 (lane) * 0x200 + (offset)) 1042 1043 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1044 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1045 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1046 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1047 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1048 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1049 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1050 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1051 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1052 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1053 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1054 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1055 #define DPIO_FRC_LATENCY_SHFIT 8 1056 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1057 #define DPIO_UPAR_SHIFT 30 1058 /* 1059 * Fence registers 1060 */ 1061 #define FENCE_REG_830_0 0x2000 1062 #define FENCE_REG_945_8 0x3000 1063 #define I830_FENCE_START_MASK 0x07f80000 1064 #define I830_FENCE_TILING_Y_SHIFT 12 1065 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 1066 #define I830_FENCE_PITCH_SHIFT 4 1067 #define I830_FENCE_REG_VALID (1<<0) 1068 #define I915_FENCE_MAX_PITCH_VAL 4 1069 #define I830_FENCE_MAX_PITCH_VAL 6 1070 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 1071 1072 #define I915_FENCE_START_MASK 0x0ff00000 1073 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 1074 1075 #define FENCE_REG_965_0 0x03000 1076 #define I965_FENCE_PITCH_SHIFT 2 1077 #define I965_FENCE_TILING_Y_SHIFT 1 1078 #define I965_FENCE_REG_VALID (1<<0) 1079 #define I965_FENCE_MAX_PITCH_VAL 0x0400 1080 1081 #define FENCE_REG_SANDYBRIDGE_0 0x100000 1082 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 1083 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 1084 1085 1086 /* control register for cpu gtt access */ 1087 #define TILECTL 0x101000 1088 #define TILECTL_SWZCTL (1 << 0) 1089 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 1090 #define TILECTL_BACKSNOOP_DIS (1 << 3) 1091 1092 /* 1093 * Instruction and interrupt control regs 1094 */ 1095 #define PGTBL_CTL 0x02020 1096 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 1097 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 1098 #define PGTBL_ER 0x02024 1099 #define PRB0_BASE (0x2030-0x30) 1100 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 1101 #define PRB2_BASE (0x2050-0x30) /* gen3 */ 1102 #define SRB0_BASE (0x2100-0x30) /* gen2 */ 1103 #define SRB1_BASE (0x2110-0x30) /* gen2 */ 1104 #define SRB2_BASE (0x2120-0x30) /* 830 */ 1105 #define SRB3_BASE (0x2130-0x30) /* 830 */ 1106 #define RENDER_RING_BASE 0x02000 1107 #define BSD_RING_BASE 0x04000 1108 #define GEN6_BSD_RING_BASE 0x12000 1109 #define GEN8_BSD2_RING_BASE 0x1c000 1110 #define VEBOX_RING_BASE 0x1a000 1111 #define BLT_RING_BASE 0x22000 1112 #define RING_TAIL(base) ((base)+0x30) 1113 #define RING_HEAD(base) ((base)+0x34) 1114 #define RING_START(base) ((base)+0x38) 1115 #define RING_CTL(base) ((base)+0x3c) 1116 #define RING_SYNC_0(base) ((base)+0x40) 1117 #define RING_SYNC_1(base) ((base)+0x44) 1118 #define RING_SYNC_2(base) ((base)+0x48) 1119 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 1120 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 1121 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 1122 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 1123 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 1124 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 1125 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 1126 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 1127 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 1128 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 1129 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 1130 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 1131 #define GEN6_NOSYNC 0 1132 #define RING_PSMI_CTL(base) ((base)+0x50) 1133 #define RING_MAX_IDLE(base) ((base)+0x54) 1134 #define RING_HWS_PGA(base) ((base)+0x80) 1135 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 1136 1137 #define GEN7_WR_WATERMARK 0x4028 1138 #define GEN7_GFX_PRIO_CTRL 0x402C 1139 #define ARB_MODE 0x4030 1140 #define ARB_MODE_SWIZZLE_SNB (1<<4) 1141 #define ARB_MODE_SWIZZLE_IVB (1<<5) 1142 #define GEN7_GFX_PEND_TLB0 0x4034 1143 #define GEN7_GFX_PEND_TLB1 0x4038 1144 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1145 #define GEN7_LRA_LIMITS_BASE 0x403C 1146 #define GEN7_LRA_LIMITS_REG_NUM 13 1147 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 1148 #define GEN7_GFX_MAX_REQ_COUNT 0x4074 1149 1150 #define GAMTARBMODE 0x04a08 1151 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 1152 #define ARB_MODE_SWIZZLE_BDW (1<<1) 1153 #define RENDER_HWS_PGA_GEN7 (0x04080) 1154 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 1155 #define RING_FAULT_GTTSEL_MASK (1<<11) 1156 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) 1157 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) 1158 #define RING_FAULT_VALID (1<<0) 1159 #define DONE_REG 0x40b0 1160 #define GEN8_PRIVATE_PAT 0x40e0 1161 #define BSD_HWS_PGA_GEN7 (0x04180) 1162 #define BLT_HWS_PGA_GEN7 (0x04280) 1163 #define VEBOX_HWS_PGA_GEN7 (0x04380) 1164 #define RING_ACTHD(base) ((base)+0x74) 1165 #define RING_ACTHD_UDW(base) ((base)+0x5c) 1166 #define RING_NOPID(base) ((base)+0x94) 1167 #define RING_IMR(base) ((base)+0xa8) 1168 #define RING_HWSTAM(base) ((base)+0x98) 1169 #define RING_TIMESTAMP(base) ((base)+0x358) 1170 #define TAIL_ADDR 0x001FFFF8 1171 #define HEAD_WRAP_COUNT 0xFFE00000 1172 #define HEAD_WRAP_ONE 0x00200000 1173 #define HEAD_ADDR 0x001FFFFC 1174 #define RING_NR_PAGES 0x001FF000 1175 #define RING_REPORT_MASK 0x00000006 1176 #define RING_REPORT_64K 0x00000002 1177 #define RING_REPORT_128K 0x00000004 1178 #define RING_NO_REPORT 0x00000000 1179 #define RING_VALID_MASK 0x00000001 1180 #define RING_VALID 0x00000001 1181 #define RING_INVALID 0x00000000 1182 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 1183 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 1184 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 1185 1186 #define GEN7_TLB_RD_ADDR 0x4700 1187 1188 #if 0 1189 #define PRB0_TAIL 0x02030 1190 #define PRB0_HEAD 0x02034 1191 #define PRB0_START 0x02038 1192 #define PRB0_CTL 0x0203c 1193 #define PRB1_TAIL 0x02040 /* 915+ only */ 1194 #define PRB1_HEAD 0x02044 /* 915+ only */ 1195 #define PRB1_START 0x02048 /* 915+ only */ 1196 #define PRB1_CTL 0x0204c /* 915+ only */ 1197 #endif 1198 #define IPEIR_I965 0x02064 1199 #define IPEHR_I965 0x02068 1200 #define INSTDONE_I965 0x0206c 1201 #define GEN7_INSTDONE_1 0x0206c 1202 #define GEN7_SC_INSTDONE 0x07100 1203 #define GEN7_SAMPLER_INSTDONE 0x0e160 1204 #define GEN7_ROW_INSTDONE 0x0e164 1205 #define I915_NUM_INSTDONE_REG 4 1206 #define RING_IPEIR(base) ((base)+0x64) 1207 #define RING_IPEHR(base) ((base)+0x68) 1208 #define RING_INSTDONE(base) ((base)+0x6c) 1209 #define RING_INSTPS(base) ((base)+0x70) 1210 #define RING_DMA_FADD(base) ((base)+0x78) 1211 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ 1212 #define RING_INSTPM(base) ((base)+0xc0) 1213 #define RING_MI_MODE(base) ((base)+0x9c) 1214 #define INSTPS 0x02070 /* 965+ only */ 1215 #define INSTDONE1 0x0207c /* 965+ only */ 1216 #define ACTHD_I965 0x02074 1217 #define HWS_PGA 0x02080 1218 #define HWS_ADDRESS_MASK 0xfffff000 1219 #define HWS_START_ADDRESS_SHIFT 4 1220 #define PWRCTXA 0x2088 /* 965GM+ only */ 1221 #define PWRCTX_EN (1<<0) 1222 #define IPEIR 0x02088 1223 #define IPEHR 0x0208c 1224 #define INSTDONE 0x02090 1225 #define NOPID 0x02094 1226 #define HWSTAM 0x02098 1227 #define DMA_FADD_I8XX 0x020d0 1228 #define RING_BBSTATE(base) ((base)+0x110) 1229 #define RING_BBADDR(base) ((base)+0x140) 1230 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ 1231 1232 #define ERROR_GEN6 0x040a0 1233 #define GEN7_ERR_INT 0x44040 1234 #define ERR_INT_POISON (1<<31) 1235 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 1236 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 1237 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 1238 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 1239 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 1240 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 1241 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) 1242 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 1243 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 1244 1245 #define FPGA_DBG 0x42300 1246 #define FPGA_DBG_RM_NOCLAIM (1<<31) 1247 1248 #define DERRMR 0x44050 1249 /* Note that HBLANK events are reserved on bdw+ */ 1250 #define DERRMR_PIPEA_SCANLINE (1<<0) 1251 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 1252 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 1253 #define DERRMR_PIPEA_VBLANK (1<<3) 1254 #define DERRMR_PIPEA_HBLANK (1<<5) 1255 #define DERRMR_PIPEB_SCANLINE (1<<8) 1256 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 1257 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 1258 #define DERRMR_PIPEB_VBLANK (1<<11) 1259 #define DERRMR_PIPEB_HBLANK (1<<13) 1260 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1261 #define DERRMR_PIPEC_SCANLINE (1<<14) 1262 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 1263 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 1264 #define DERRMR_PIPEC_VBLANK (1<<21) 1265 #define DERRMR_PIPEC_HBLANK (1<<22) 1266 1267 1268 /* GM45+ chicken bits -- debug workaround bits that may be required 1269 * for various sorts of correct behavior. The top 16 bits of each are 1270 * the enables for writing to the corresponding low bit. 1271 */ 1272 #define _3D_CHICKEN 0x02084 1273 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 1274 #define _3D_CHICKEN2 0x0208c 1275 /* Disables pipelining of read flushes past the SF-WIZ interface. 1276 * Required on all Ironlake steppings according to the B-Spec, but the 1277 * particular danger of not doing so is not specified. 1278 */ 1279 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 1280 #define _3D_CHICKEN3 0x02090 1281 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 1282 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 1283 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 1284 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 1285 1286 #define MI_MODE 0x0209c 1287 # define VS_TIMER_DISPATCH (1 << 6) 1288 # define MI_FLUSH_ENABLE (1 << 12) 1289 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 1290 # define MODE_IDLE (1 << 9) 1291 # define STOP_RING (1 << 8) 1292 1293 #define GEN6_GT_MODE 0x20d0 1294 #define GEN7_GT_MODE 0x7008 1295 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 1296 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 1297 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 1298 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 1299 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 1300 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 1301 1302 #define GFX_MODE 0x02520 1303 #define GFX_MODE_GEN7 0x0229c 1304 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 1305 #define GFX_RUN_LIST_ENABLE (1<<15) 1306 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 1307 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 1308 #define GFX_REPLAY_MODE (1<<11) 1309 #define GFX_PSMI_GRANULARITY (1<<10) 1310 #define GFX_PPGTT_ENABLE (1<<9) 1311 1312 #define VLV_DISPLAY_BASE 0x180000 1313 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 1314 1315 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) 1316 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) 1317 #define SCPD0 0x0209c /* 915+ only */ 1318 #define IER 0x020a0 1319 #define IIR 0x020a4 1320 #define IMR 0x020a8 1321 #define ISR 0x020ac 1322 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) 1323 #define GINT_DIS (1<<22) 1324 #define GCFG_DIS (1<<8) 1325 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) 1326 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) 1327 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) 1328 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) 1329 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) 1330 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) 1331 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) 1332 #define VLV_PCBR_ADDR_SHIFT 12 1333 1334 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 1335 #define EIR 0x020b0 1336 #define EMR 0x020b4 1337 #define ESR 0x020b8 1338 #define GM45_ERROR_PAGE_TABLE (1<<5) 1339 #define GM45_ERROR_MEM_PRIV (1<<4) 1340 #define I915_ERROR_PAGE_TABLE (1<<4) 1341 #define GM45_ERROR_CP_PRIV (1<<3) 1342 #define I915_ERROR_MEMORY_REFRESH (1<<1) 1343 #define I915_ERROR_INSTRUCTION (1<<0) 1344 #define INSTPM 0x020c0 1345 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1346 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 1347 will not assert AGPBUSY# and will only 1348 be delivered when out of C3. */ 1349 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1350 #define INSTPM_TLB_INVALIDATE (1<<9) 1351 #define INSTPM_SYNC_FLUSH (1<<5) 1352 #define ACTHD 0x020c8 1353 #define MEM_MODE 0x020cc 1354 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 1355 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 1356 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 1357 #define FW_BLC 0x020d8 1358 #define FW_BLC2 0x020dc 1359 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 1360 #define FW_BLC_SELF_EN_MASK (1<<31) 1361 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 1362 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 1363 #define MM_BURST_LENGTH 0x00700000 1364 #define MM_FIFO_WATERMARK 0x0001F000 1365 #define LM_BURST_LENGTH 0x00000700 1366 #define LM_FIFO_WATERMARK 0x0000001F 1367 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 1368 1369 /* Make render/texture TLB fetches lower priorty than associated data 1370 * fetches. This is not turned on by default 1371 */ 1372 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1373 1374 /* Isoch request wait on GTT enable (Display A/B/C streams). 1375 * Make isoch requests stall on the TLB update. May cause 1376 * display underruns (test mode only) 1377 */ 1378 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1379 1380 /* Block grant count for isoch requests when block count is 1381 * set to a finite value. 1382 */ 1383 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1384 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1385 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1386 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1387 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1388 1389 /* Enable render writes to complete in C2/C3/C4 power states. 1390 * If this isn't enabled, render writes are prevented in low 1391 * power states. That seems bad to me. 1392 */ 1393 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1394 1395 /* This acknowledges an async flip immediately instead 1396 * of waiting for 2TLB fetches. 1397 */ 1398 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1399 1400 /* Enables non-sequential data reads through arbiter 1401 */ 1402 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1403 1404 /* Disable FSB snooping of cacheable write cycles from binner/render 1405 * command stream 1406 */ 1407 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1408 1409 /* Arbiter time slice for non-isoch streams */ 1410 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1411 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1412 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1413 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1414 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1415 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1416 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1417 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1418 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1419 1420 /* Low priority grace period page size */ 1421 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1422 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1423 1424 /* Disable display A/B trickle feed */ 1425 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1426 1427 /* Set display plane priority */ 1428 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1429 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1430 1431 #define MI_STATE 0x020e4 /* gen2 only */ 1432 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1433 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1434 1435 #define CACHE_MODE_0 0x02120 /* 915+ only */ 1436 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1437 #define CM0_IZ_OPT_DISABLE (1<<6) 1438 #define CM0_ZR_OPT_DISABLE (1<<5) 1439 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 1440 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 1441 #define CM0_COLOR_EVICT_DISABLE (1<<3) 1442 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 1443 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 1444 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 1445 #define GFX_FLSH_CNTL_GEN6 0x101008 1446 #define GFX_FLSH_CNTL_EN (1<<0) 1447 #define ECOSKPD 0x021d0 1448 #define ECO_GATING_CX_ONLY (1<<3) 1449 #define ECO_FLIP_DONE (1<<0) 1450 1451 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ 1452 #define RC_OP_FLUSH_ENABLE (1<<0) 1453 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 1454 #define CACHE_MODE_1 0x7004 /* IVB+ */ 1455 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 1456 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 1457 1458 #define GEN6_BLITTER_ECOSKPD 0x221d0 1459 #define GEN6_BLITTER_LOCK_SHIFT 16 1460 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 1461 1462 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 1463 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 1464 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 1465 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 1466 1467 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 1468 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 1469 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 1470 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 1471 #define GEN6_BSD_GO_INDICATOR (1 << 4) 1472 1473 /* On modern GEN architectures interrupt control consists of two sets 1474 * of registers. The first set pertains to the ring generating the 1475 * interrupt. The second control is for the functional block generating the 1476 * interrupt. These are PM, GT, DE, etc. 1477 * 1478 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1479 * GT interrupt bits, so we don't need to duplicate the defines. 1480 * 1481 * These defines should cover us well from SNB->HSW with minor exceptions 1482 * it can also work on ILK. 1483 */ 1484 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1485 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1486 #define GT_BLT_USER_INTERRUPT (1 << 22) 1487 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1488 #define GT_BSD_USER_INTERRUPT (1 << 12) 1489 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1490 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1491 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1492 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1493 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 1494 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1495 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1496 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1497 1498 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1499 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1500 1501 #define GT_PARITY_ERROR(dev) \ 1502 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1503 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1504 1505 /* These are all the "old" interrupts */ 1506 #define ILK_BSD_USER_INTERRUPT (1<<5) 1507 1508 #define I915_PM_INTERRUPT (1<<31) 1509 #define I915_ISP_INTERRUPT (1<<22) 1510 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 1511 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 1512 #define I915_MIPIB_INTERRUPT (1<<19) 1513 #define I915_MIPIA_INTERRUPT (1<<18) 1514 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 1515 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 1516 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 1517 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 1518 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 1519 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 1520 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 1521 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 1522 #define I915_HWB_OOM_INTERRUPT (1<<13) 1523 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 1524 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 1525 #define I915_MISC_INTERRUPT (1<<11) 1526 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 1527 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 1528 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 1529 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 1530 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 1531 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 1532 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 1533 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 1534 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 1535 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 1536 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 1537 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 1538 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 1539 #define I915_DEBUG_INTERRUPT (1<<2) 1540 #define I915_WINVALID_INTERRUPT (1<<1) 1541 #define I915_USER_INTERRUPT (1<<1) 1542 #define I915_ASLE_INTERRUPT (1<<0) 1543 #define I915_BSD_USER_INTERRUPT (1<<25) 1544 1545 #define GEN6_BSD_RNCID 0x12198 1546 1547 #define GEN7_FF_THREAD_MODE 0x20a0 1548 #define GEN7_FF_SCHED_MASK 0x0077070 1549 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1550 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 1551 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 1552 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 1553 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 1554 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1555 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 1556 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 1557 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 1558 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 1559 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 1560 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 1561 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 1562 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 1563 1564 /* 1565 * Framebuffer compression (915+ only) 1566 */ 1567 1568 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1569 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1570 #define FBC_CONTROL 0x03208 1571 #define FBC_CTL_EN (1<<31) 1572 #define FBC_CTL_PERIODIC (1<<30) 1573 #define FBC_CTL_INTERVAL_SHIFT (16) 1574 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 1575 #define FBC_CTL_C3_IDLE (1<<13) 1576 #define FBC_CTL_STRIDE_SHIFT (5) 1577 #define FBC_CTL_FENCENO_SHIFT (0) 1578 #define FBC_COMMAND 0x0320c 1579 #define FBC_CMD_COMPRESS (1<<0) 1580 #define FBC_STATUS 0x03210 1581 #define FBC_STAT_COMPRESSING (1<<31) 1582 #define FBC_STAT_COMPRESSED (1<<30) 1583 #define FBC_STAT_MODIFIED (1<<29) 1584 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 1585 #define FBC_CONTROL2 0x03214 1586 #define FBC_CTL_FENCE_DBL (0<<4) 1587 #define FBC_CTL_IDLE_IMM (0<<2) 1588 #define FBC_CTL_IDLE_FULL (1<<2) 1589 #define FBC_CTL_IDLE_LINE (2<<2) 1590 #define FBC_CTL_IDLE_DEBUG (3<<2) 1591 #define FBC_CTL_CPU_FENCE (1<<1) 1592 #define FBC_CTL_PLANE(plane) ((plane)<<0) 1593 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ 1594 #define FBC_TAG 0x03300 1595 1596 #define FBC_LL_SIZE (1536) 1597 1598 /* Framebuffer compression for GM45+ */ 1599 #define DPFC_CB_BASE 0x3200 1600 #define DPFC_CONTROL 0x3208 1601 #define DPFC_CTL_EN (1<<31) 1602 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 1603 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 1604 #define DPFC_CTL_FENCE_EN (1<<29) 1605 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 1606 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 1607 #define DPFC_SR_EN (1<<10) 1608 #define DPFC_CTL_LIMIT_1X (0<<6) 1609 #define DPFC_CTL_LIMIT_2X (1<<6) 1610 #define DPFC_CTL_LIMIT_4X (2<<6) 1611 #define DPFC_RECOMP_CTL 0x320c 1612 #define DPFC_RECOMP_STALL_EN (1<<27) 1613 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 1614 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 1615 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 1616 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 1617 #define DPFC_STATUS 0x3210 1618 #define DPFC_INVAL_SEG_SHIFT (16) 1619 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 1620 #define DPFC_COMP_SEG_SHIFT (0) 1621 #define DPFC_COMP_SEG_MASK (0x000003ff) 1622 #define DPFC_STATUS2 0x3214 1623 #define DPFC_FENCE_YOFF 0x3218 1624 #define DPFC_CHICKEN 0x3224 1625 #define DPFC_HT_MODIFY (1<<31) 1626 1627 /* Framebuffer compression for Ironlake */ 1628 #define ILK_DPFC_CB_BASE 0x43200 1629 #define ILK_DPFC_CONTROL 0x43208 1630 #define FBC_CTL_FALSE_COLOR (1<<10) 1631 /* The bit 28-8 is reserved */ 1632 #define DPFC_RESERVED (0x1FFFFF00) 1633 #define ILK_DPFC_RECOMP_CTL 0x4320c 1634 #define ILK_DPFC_STATUS 0x43210 1635 #define ILK_DPFC_FENCE_YOFF 0x43218 1636 #define ILK_DPFC_CHICKEN 0x43224 1637 #define ILK_FBC_RT_BASE 0x2128 1638 #define ILK_FBC_RT_VALID (1<<0) 1639 #define SNB_FBC_FRONT_BUFFER (1<<1) 1640 1641 #define ILK_DISPLAY_CHICKEN1 0x42000 1642 #define ILK_FBCQ_DIS (1<<22) 1643 #define ILK_PABSTRETCH_DIS (1<<21) 1644 1645 1646 /* 1647 * Framebuffer compression for Sandybridge 1648 * 1649 * The following two registers are of type GTTMMADR 1650 */ 1651 #define SNB_DPFC_CTL_SA 0x100100 1652 #define SNB_CPU_FENCE_ENABLE (1<<29) 1653 #define DPFC_CPU_FENCE_OFFSET 0x100104 1654 1655 /* Framebuffer compression for Ivybridge */ 1656 #define IVB_FBC_RT_BASE 0x7020 1657 1658 #define IPS_CTL 0x43408 1659 #define IPS_ENABLE (1 << 31) 1660 1661 #define MSG_FBC_REND_STATE 0x50380 1662 #define FBC_REND_NUKE (1<<2) 1663 #define FBC_REND_CACHE_CLEAN (1<<1) 1664 1665 /* 1666 * GPIO regs 1667 */ 1668 #define GPIOA 0x5010 1669 #define GPIOB 0x5014 1670 #define GPIOC 0x5018 1671 #define GPIOD 0x501c 1672 #define GPIOE 0x5020 1673 #define GPIOF 0x5024 1674 #define GPIOG 0x5028 1675 #define GPIOH 0x502c 1676 # define GPIO_CLOCK_DIR_MASK (1 << 0) 1677 # define GPIO_CLOCK_DIR_IN (0 << 1) 1678 # define GPIO_CLOCK_DIR_OUT (1 << 1) 1679 # define GPIO_CLOCK_VAL_MASK (1 << 2) 1680 # define GPIO_CLOCK_VAL_OUT (1 << 3) 1681 # define GPIO_CLOCK_VAL_IN (1 << 4) 1682 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1683 # define GPIO_DATA_DIR_MASK (1 << 8) 1684 # define GPIO_DATA_DIR_IN (0 << 9) 1685 # define GPIO_DATA_DIR_OUT (1 << 9) 1686 # define GPIO_DATA_VAL_MASK (1 << 10) 1687 # define GPIO_DATA_VAL_OUT (1 << 11) 1688 # define GPIO_DATA_VAL_IN (1 << 12) 1689 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1690 1691 #define GMBUS0 0x5100 /* clock/port select */ 1692 #define GMBUS_RATE_100KHZ (0<<8) 1693 #define GMBUS_RATE_50KHZ (1<<8) 1694 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 1695 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 1696 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 1697 #define GMBUS_PORT_DISABLED 0 1698 #define GMBUS_PORT_SSC 1 1699 #define GMBUS_PORT_VGADDC 2 1700 #define GMBUS_PORT_PANEL 3 1701 #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ 1702 #define GMBUS_PORT_DPC 4 /* HDMIC */ 1703 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 1704 #define GMBUS_PORT_DPD 6 /* HDMID */ 1705 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 1706 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 1707 #define GMBUS1 0x5104 /* command/status */ 1708 #define GMBUS_SW_CLR_INT (1<<31) 1709 #define GMBUS_SW_RDY (1<<30) 1710 #define GMBUS_ENT (1<<29) /* enable timeout */ 1711 #define GMBUS_CYCLE_NONE (0<<25) 1712 #define GMBUS_CYCLE_WAIT (1<<25) 1713 #define GMBUS_CYCLE_INDEX (2<<25) 1714 #define GMBUS_CYCLE_STOP (4<<25) 1715 #define GMBUS_BYTE_COUNT_SHIFT 16 1716 #define GMBUS_SLAVE_INDEX_SHIFT 8 1717 #define GMBUS_SLAVE_ADDR_SHIFT 1 1718 #define GMBUS_SLAVE_READ (1<<0) 1719 #define GMBUS_SLAVE_WRITE (0<<0) 1720 #define GMBUS2 0x5108 /* status */ 1721 #define GMBUS_INUSE (1<<15) 1722 #define GMBUS_HW_WAIT_PHASE (1<<14) 1723 #define GMBUS_STALL_TIMEOUT (1<<13) 1724 #define GMBUS_INT (1<<12) 1725 #define GMBUS_HW_RDY (1<<11) 1726 #define GMBUS_SATOER (1<<10) 1727 #define GMBUS_ACTIVE (1<<9) 1728 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 1729 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 1730 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 1731 #define GMBUS_NAK_EN (1<<3) 1732 #define GMBUS_IDLE_EN (1<<2) 1733 #define GMBUS_HW_WAIT_EN (1<<1) 1734 #define GMBUS_HW_RDY_EN (1<<0) 1735 #define GMBUS5 0x5120 /* byte index */ 1736 #define GMBUS_2BYTE_INDEX_EN (1<<31) 1737 1738 /* 1739 * Clock control & power management 1740 */ 1741 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 1742 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 1743 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 1744 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1745 1746 #define VGA0 0x6000 1747 #define VGA1 0x6004 1748 #define VGA_PD 0x6010 1749 #define VGA0_PD_P2_DIV_4 (1 << 7) 1750 #define VGA0_PD_P1_DIV_2 (1 << 5) 1751 #define VGA0_PD_P1_SHIFT 0 1752 #define VGA0_PD_P1_MASK (0x1f << 0) 1753 #define VGA1_PD_P2_DIV_4 (1 << 15) 1754 #define VGA1_PD_P1_DIV_2 (1 << 13) 1755 #define VGA1_PD_P1_SHIFT 8 1756 #define VGA1_PD_P1_MASK (0x1f << 8) 1757 #define DPLL_VCO_ENABLE (1 << 31) 1758 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1759 #define DPLL_DVO_2X_MODE (1 << 30) 1760 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1761 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1762 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 1763 #define DPLL_VGA_MODE_DIS (1 << 28) 1764 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1765 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1766 #define DPLL_MODE_MASK (3 << 26) 1767 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1768 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1769 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1770 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1771 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1772 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1773 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1774 #define DPLL_LOCK_VLV (1<<15) 1775 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 1776 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 1777 #define DPLL_SSC_REF_CLOCK_CHV (1<<13) 1778 #define DPLL_PORTC_READY_MASK (0xf << 4) 1779 #define DPLL_PORTB_READY_MASK (0xf) 1780 1781 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1782 1783 /* Additional CHV pll/phy registers */ 1784 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) 1785 #define DPLL_PORTD_READY_MASK (0xf) 1786 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) 1787 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1788 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) 1789 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 1790 1791 /* 1792 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1793 * this field (only one bit may be set). 1794 */ 1795 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1796 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1797 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1798 /* i830, required in DVO non-gang */ 1799 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1800 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1801 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1802 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1803 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1804 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1805 #define PLL_REF_INPUT_MASK (3 << 13) 1806 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1807 /* Ironlake */ 1808 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1809 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1810 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 1811 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1812 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1813 1814 /* 1815 * Parallel to Serial Load Pulse phase selection. 1816 * Selects the phase for the 10X DPLL clock for the PCIe 1817 * digital display port. The range is 4 to 13; 10 or more 1818 * is just a flip delay. The default is 6 1819 */ 1820 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1821 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1822 /* 1823 * SDVO multiplier for 945G/GM. Not used on 965. 1824 */ 1825 #define SDVO_MULTIPLIER_MASK 0x000000ff 1826 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1827 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1828 1829 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 1830 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 1831 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 1832 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1833 1834 /* 1835 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1836 * 1837 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1838 */ 1839 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1840 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1841 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1842 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1843 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1844 /* 1845 * SDVO/UDI pixel multiplier. 1846 * 1847 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1848 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1849 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1850 * dummy bytes in the datastream at an increased clock rate, with both sides of 1851 * the link knowing how many bytes are fill. 1852 * 1853 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1854 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1855 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1856 * through an SDVO command. 1857 * 1858 * This register field has values of multiplication factor minus 1, with 1859 * a maximum multiplier of 5 for SDVO. 1860 */ 1861 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1862 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1863 /* 1864 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1865 * This best be set to the default value (3) or the CRT won't work. No, 1866 * I don't entirely understand what this does... 1867 */ 1868 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1869 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1870 1871 #define _FPA0 0x06040 1872 #define _FPA1 0x06044 1873 #define _FPB0 0x06048 1874 #define _FPB1 0x0604c 1875 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1876 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1877 #define FP_N_DIV_MASK 0x003f0000 1878 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1879 #define FP_N_DIV_SHIFT 16 1880 #define FP_M1_DIV_MASK 0x00003f00 1881 #define FP_M1_DIV_SHIFT 8 1882 #define FP_M2_DIV_MASK 0x0000003f 1883 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1884 #define FP_M2_DIV_SHIFT 0 1885 #define DPLL_TEST 0x606c 1886 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1887 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1888 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1889 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1890 #define DPLLB_TEST_N_BYPASS (1 << 19) 1891 #define DPLLB_TEST_M_BYPASS (1 << 18) 1892 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1893 #define DPLLA_TEST_N_BYPASS (1 << 3) 1894 #define DPLLA_TEST_M_BYPASS (1 << 2) 1895 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1896 #define D_STATE 0x6104 1897 #define DSTATE_GFX_RESET_I830 (1<<6) 1898 #define DSTATE_PLL_D3_OFF (1<<3) 1899 #define DSTATE_GFX_CLOCK_GATING (1<<1) 1900 #define DSTATE_DOT_CLOCK_GATING (1<<0) 1901 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) 1902 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1903 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1904 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1905 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1906 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1907 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1908 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1909 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1910 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1911 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1912 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1913 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1914 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1915 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1916 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1917 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1918 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1919 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1920 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1921 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1922 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1923 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1924 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1925 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1926 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1927 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1928 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1929 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1930 /* 1931 * This bit must be set on the 830 to prevent hangs when turning off the 1932 * overlay scaler. 1933 */ 1934 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1935 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1936 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1937 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1938 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1939 1940 #define RENCLK_GATE_D1 0x6204 1941 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1942 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1943 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1944 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1945 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1946 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1947 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1948 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1949 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1950 /* This bit must be unset on 855,865 */ 1951 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1952 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1953 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1954 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1955 /* This bit must be set on 855,865. */ 1956 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1957 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1958 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1959 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1960 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1961 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1962 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1963 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1964 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1965 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1966 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1967 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1968 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1969 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1970 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1971 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1972 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1973 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1974 1975 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1976 /* This bit must always be set on 965G/965GM */ 1977 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1978 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1979 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1980 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1981 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1982 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1983 /* This bit must always be set on 965G */ 1984 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1985 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1986 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1987 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1988 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1989 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1990 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1991 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1992 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1993 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1994 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1995 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1996 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1997 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1998 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1999 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 2000 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 2001 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 2002 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 2003 2004 #define RENCLK_GATE_D2 0x6208 2005 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 2006 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 2007 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 2008 2009 #define VDECCLK_GATE_D 0x620C /* g4x only */ 2010 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 2011 2012 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 2013 #define DEUC 0x6214 /* CRL only */ 2014 2015 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) 2016 #define FW_CSPWRDWNEN (1<<15) 2017 2018 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) 2019 2020 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) 2021 #define CDCLK_FREQ_SHIFT 4 2022 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 2023 #define CZCLK_FREQ_MASK 0xf 2024 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) 2025 2026 /* 2027 * Palette regs 2028 */ 2029 #define PALETTE_A_OFFSET 0xa000 2030 #define PALETTE_B_OFFSET 0xa800 2031 #define CHV_PALETTE_C_OFFSET 0xc000 2032 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ 2033 dev_priv->info.display_mmio_offset) 2034 2035 /* MCH MMIO space */ 2036 2037 /* 2038 * MCHBAR mirror. 2039 * 2040 * This mirrors the MCHBAR MMIO space whose location is determined by 2041 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 2042 * every way. It is not accessible from the CP register read instructions. 2043 * 2044 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 2045 * just read. 2046 */ 2047 #define MCHBAR_MIRROR_BASE 0x10000 2048 2049 #define MCHBAR_MIRROR_BASE_SNB 0x140000 2050 2051 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 2052 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) 2053 2054 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 2055 #define DCC 0x10200 2056 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 2057 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 2058 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 2059 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 2060 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 2061 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 2062 #define DCC2 0x10204 2063 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 2064 2065 /* Pineview MCH register contains DDR3 setting */ 2066 #define CSHRDDR3CTL 0x101a8 2067 #define CSHRDDR3CTL_DDR3 (1 << 2) 2068 2069 /* 965 MCH register controlling DRAM channel configuration */ 2070 #define C0DRB3 0x10206 2071 #define C1DRB3 0x10606 2072 2073 /* snb MCH registers for reading the DRAM channel configuration */ 2074 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 2075 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 2076 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 2077 #define MAD_DIMM_ECC_MASK (0x3 << 24) 2078 #define MAD_DIMM_ECC_OFF (0x0 << 24) 2079 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 2080 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 2081 #define MAD_DIMM_ECC_ON (0x3 << 24) 2082 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 2083 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 2084 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 2085 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 2086 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 2087 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 2088 #define MAD_DIMM_A_SELECT (0x1 << 16) 2089 /* DIMM sizes are in multiples of 256mb. */ 2090 #define MAD_DIMM_B_SIZE_SHIFT 8 2091 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 2092 #define MAD_DIMM_A_SIZE_SHIFT 0 2093 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 2094 2095 /* snb MCH registers for priority tuning */ 2096 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) 2097 #define MCH_SSKPD_WM0_MASK 0x3f 2098 #define MCH_SSKPD_WM0_VAL 0xc 2099 2100 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) 2101 2102 /* Clocking configuration register */ 2103 #define CLKCFG 0x10c00 2104 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 2105 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 2106 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 2107 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 2108 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 2109 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 2110 /* Note, below two are guess */ 2111 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 2112 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 2113 #define CLKCFG_FSB_MASK (7 << 0) 2114 #define CLKCFG_MEM_533 (1 << 4) 2115 #define CLKCFG_MEM_667 (2 << 4) 2116 #define CLKCFG_MEM_800 (3 << 4) 2117 #define CLKCFG_MEM_MASK (7 << 4) 2118 2119 #define TSC1 0x11001 2120 #define TSE (1<<0) 2121 #define TR1 0x11006 2122 #define TSFS 0x11020 2123 #define TSFS_SLOPE_MASK 0x0000ff00 2124 #define TSFS_SLOPE_SHIFT 8 2125 #define TSFS_INTR_MASK 0x000000ff 2126 2127 #define CRSTANDVID 0x11100 2128 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 2129 #define PXVFREQ_PX_MASK 0x7f000000 2130 #define PXVFREQ_PX_SHIFT 24 2131 #define VIDFREQ_BASE 0x11110 2132 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 2133 #define VIDFREQ2 0x11114 2134 #define VIDFREQ3 0x11118 2135 #define VIDFREQ4 0x1111c 2136 #define VIDFREQ_P0_MASK 0x1f000000 2137 #define VIDFREQ_P0_SHIFT 24 2138 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 2139 #define VIDFREQ_P0_CSCLK_SHIFT 20 2140 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 2141 #define VIDFREQ_P0_CRCLK_SHIFT 16 2142 #define VIDFREQ_P1_MASK 0x00001f00 2143 #define VIDFREQ_P1_SHIFT 8 2144 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 2145 #define VIDFREQ_P1_CSCLK_SHIFT 4 2146 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 2147 #define INTTOEXT_BASE_ILK 0x11300 2148 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 2149 #define INTTOEXT_MAP3_SHIFT 24 2150 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 2151 #define INTTOEXT_MAP2_SHIFT 16 2152 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 2153 #define INTTOEXT_MAP1_SHIFT 8 2154 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 2155 #define INTTOEXT_MAP0_SHIFT 0 2156 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 2157 #define MEMSWCTL 0x11170 /* Ironlake only */ 2158 #define MEMCTL_CMD_MASK 0xe000 2159 #define MEMCTL_CMD_SHIFT 13 2160 #define MEMCTL_CMD_RCLK_OFF 0 2161 #define MEMCTL_CMD_RCLK_ON 1 2162 #define MEMCTL_CMD_CHFREQ 2 2163 #define MEMCTL_CMD_CHVID 3 2164 #define MEMCTL_CMD_VMMOFF 4 2165 #define MEMCTL_CMD_VMMON 5 2166 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 2167 when command complete */ 2168 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 2169 #define MEMCTL_FREQ_SHIFT 8 2170 #define MEMCTL_SFCAVM (1<<7) 2171 #define MEMCTL_TGT_VID_MASK 0x007f 2172 #define MEMIHYST 0x1117c 2173 #define MEMINTREN 0x11180 /* 16 bits */ 2174 #define MEMINT_RSEXIT_EN (1<<8) 2175 #define MEMINT_CX_SUPR_EN (1<<7) 2176 #define MEMINT_CONT_BUSY_EN (1<<6) 2177 #define MEMINT_AVG_BUSY_EN (1<<5) 2178 #define MEMINT_EVAL_CHG_EN (1<<4) 2179 #define MEMINT_MON_IDLE_EN (1<<3) 2180 #define MEMINT_UP_EVAL_EN (1<<2) 2181 #define MEMINT_DOWN_EVAL_EN (1<<1) 2182 #define MEMINT_SW_CMD_EN (1<<0) 2183 #define MEMINTRSTR 0x11182 /* 16 bits */ 2184 #define MEM_RSEXIT_MASK 0xc000 2185 #define MEM_RSEXIT_SHIFT 14 2186 #define MEM_CONT_BUSY_MASK 0x3000 2187 #define MEM_CONT_BUSY_SHIFT 12 2188 #define MEM_AVG_BUSY_MASK 0x0c00 2189 #define MEM_AVG_BUSY_SHIFT 10 2190 #define MEM_EVAL_CHG_MASK 0x0300 2191 #define MEM_EVAL_BUSY_SHIFT 8 2192 #define MEM_MON_IDLE_MASK 0x00c0 2193 #define MEM_MON_IDLE_SHIFT 6 2194 #define MEM_UP_EVAL_MASK 0x0030 2195 #define MEM_UP_EVAL_SHIFT 4 2196 #define MEM_DOWN_EVAL_MASK 0x000c 2197 #define MEM_DOWN_EVAL_SHIFT 2 2198 #define MEM_SW_CMD_MASK 0x0003 2199 #define MEM_INT_STEER_GFX 0 2200 #define MEM_INT_STEER_CMR 1 2201 #define MEM_INT_STEER_SMI 2 2202 #define MEM_INT_STEER_SCI 3 2203 #define MEMINTRSTS 0x11184 2204 #define MEMINT_RSEXIT (1<<7) 2205 #define MEMINT_CONT_BUSY (1<<6) 2206 #define MEMINT_AVG_BUSY (1<<5) 2207 #define MEMINT_EVAL_CHG (1<<4) 2208 #define MEMINT_MON_IDLE (1<<3) 2209 #define MEMINT_UP_EVAL (1<<2) 2210 #define MEMINT_DOWN_EVAL (1<<1) 2211 #define MEMINT_SW_CMD (1<<0) 2212 #define MEMMODECTL 0x11190 2213 #define MEMMODE_BOOST_EN (1<<31) 2214 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 2215 #define MEMMODE_BOOST_FREQ_SHIFT 24 2216 #define MEMMODE_IDLE_MODE_MASK 0x00030000 2217 #define MEMMODE_IDLE_MODE_SHIFT 16 2218 #define MEMMODE_IDLE_MODE_EVAL 0 2219 #define MEMMODE_IDLE_MODE_CONT 1 2220 #define MEMMODE_HWIDLE_EN (1<<15) 2221 #define MEMMODE_SWMODE_EN (1<<14) 2222 #define MEMMODE_RCLK_GATE (1<<13) 2223 #define MEMMODE_HW_UPDATE (1<<12) 2224 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 2225 #define MEMMODE_FSTART_SHIFT 8 2226 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 2227 #define MEMMODE_FMAX_SHIFT 4 2228 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 2229 #define RCBMAXAVG 0x1119c 2230 #define MEMSWCTL2 0x1119e /* Cantiga only */ 2231 #define SWMEMCMD_RENDER_OFF (0 << 13) 2232 #define SWMEMCMD_RENDER_ON (1 << 13) 2233 #define SWMEMCMD_SWFREQ (2 << 13) 2234 #define SWMEMCMD_TARVID (3 << 13) 2235 #define SWMEMCMD_VRM_OFF (4 << 13) 2236 #define SWMEMCMD_VRM_ON (5 << 13) 2237 #define CMDSTS (1<<12) 2238 #define SFCAVM (1<<11) 2239 #define SWFREQ_MASK 0x0380 /* P0-7 */ 2240 #define SWFREQ_SHIFT 7 2241 #define TARVID_MASK 0x001f 2242 #define MEMSTAT_CTG 0x111a0 2243 #define RCBMINAVG 0x111a0 2244 #define RCUPEI 0x111b0 2245 #define RCDNEI 0x111b4 2246 #define RSTDBYCTL 0x111b8 2247 #define RS1EN (1<<31) 2248 #define RS2EN (1<<30) 2249 #define RS3EN (1<<29) 2250 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 2251 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 2252 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 2253 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 2254 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 2255 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 2256 #define RSX_STATUS_MASK (7<<20) 2257 #define RSX_STATUS_ON (0<<20) 2258 #define RSX_STATUS_RC1 (1<<20) 2259 #define RSX_STATUS_RC1E (2<<20) 2260 #define RSX_STATUS_RS1 (3<<20) 2261 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 2262 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 2263 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 2264 #define RSX_STATUS_RSVD2 (7<<20) 2265 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 2266 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 2267 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 2268 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 2269 #define RS1CONTSAV_MASK (3<<14) 2270 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 2271 #define RS1CONTSAV_RSVD (1<<14) 2272 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 2273 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 2274 #define NORMSLEXLAT_MASK (3<<12) 2275 #define SLOW_RS123 (0<<12) 2276 #define SLOW_RS23 (1<<12) 2277 #define SLOW_RS3 (2<<12) 2278 #define NORMAL_RS123 (3<<12) 2279 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 2280 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 2281 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 2282 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 2283 #define RS_CSTATE_MASK (3<<4) 2284 #define RS_CSTATE_C367_RS1 (0<<4) 2285 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 2286 #define RS_CSTATE_RSVD (2<<4) 2287 #define RS_CSTATE_C367_RS2 (3<<4) 2288 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 2289 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 2290 #define VIDCTL 0x111c0 2291 #define VIDSTS 0x111c8 2292 #define VIDSTART 0x111cc /* 8 bits */ 2293 #define MEMSTAT_ILK 0x111f8 2294 #define MEMSTAT_VID_MASK 0x7f00 2295 #define MEMSTAT_VID_SHIFT 8 2296 #define MEMSTAT_PSTATE_MASK 0x00f8 2297 #define MEMSTAT_PSTATE_SHIFT 3 2298 #define MEMSTAT_MON_ACTV (1<<2) 2299 #define MEMSTAT_SRC_CTL_MASK 0x0003 2300 #define MEMSTAT_SRC_CTL_CORE 0 2301 #define MEMSTAT_SRC_CTL_TRB 1 2302 #define MEMSTAT_SRC_CTL_THM 2 2303 #define MEMSTAT_SRC_CTL_STDBY 3 2304 #define RCPREVBSYTUPAVG 0x113b8 2305 #define RCPREVBSYTDNAVG 0x113bc 2306 #define PMMISC 0x11214 2307 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 2308 #define SDEW 0x1124c 2309 #define CSIEW0 0x11250 2310 #define CSIEW1 0x11254 2311 #define CSIEW2 0x11258 2312 #define PEW 0x1125c 2313 #define DEW 0x11270 2314 #define MCHAFE 0x112c0 2315 #define CSIEC 0x112e0 2316 #define DMIEC 0x112e4 2317 #define DDREC 0x112e8 2318 #define PEG0EC 0x112ec 2319 #define PEG1EC 0x112f0 2320 #define GFXEC 0x112f4 2321 #define RPPREVBSYTUPAVG 0x113b8 2322 #define RPPREVBSYTDNAVG 0x113bc 2323 #define ECR 0x11600 2324 #define ECR_GPFE (1<<31) 2325 #define ECR_IMONE (1<<30) 2326 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 2327 #define OGW0 0x11608 2328 #define OGW1 0x1160c 2329 #define EG0 0x11610 2330 #define EG1 0x11614 2331 #define EG2 0x11618 2332 #define EG3 0x1161c 2333 #define EG4 0x11620 2334 #define EG5 0x11624 2335 #define EG6 0x11628 2336 #define EG7 0x1162c 2337 #define PXW 0x11664 2338 #define PXWL 0x11680 2339 #define LCFUSE02 0x116c0 2340 #define LCFUSE_HIV_MASK 0x000000ff 2341 #define CSIPLL0 0x12c10 2342 #define DDRMPLL1 0X12c20 2343 #define PEG_BAND_GAP_DATA 0x14d68 2344 2345 #define GEN6_GT_THREAD_STATUS_REG 0x13805c 2346 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 2347 2348 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) 2349 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) 2350 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) 2351 2352 /* 2353 * Logical Context regs 2354 */ 2355 #define CCID 0x2180 2356 #define CCID_EN (1<<0) 2357 /* 2358 * Notes on SNB/IVB/VLV context size: 2359 * - Power context is saved elsewhere (LLC or stolen) 2360 * - Ring/execlist context is saved on SNB, not on IVB 2361 * - Extended context size already includes render context size 2362 * - We always need to follow the extended context size. 2363 * SNB BSpec has comments indicating that we should use the 2364 * render context size instead if execlists are disabled, but 2365 * based on empirical testing that's just nonsense. 2366 * - Pipelined/VF state is saved on SNB/IVB respectively 2367 * - GT1 size just indicates how much of render context 2368 * doesn't need saving on GT1 2369 */ 2370 #define CXT_SIZE 0x21a0 2371 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 2372 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 2373 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 2374 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 2375 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 2376 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 2377 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 2378 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 2379 #define GEN7_CXT_SIZE 0x21a8 2380 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 2381 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 2382 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 2383 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 2384 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 2385 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 2386 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 2387 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 2388 /* Haswell does have the CXT_SIZE register however it does not appear to be 2389 * valid. Now, docs explain in dwords what is in the context object. The full 2390 * size is 70720 bytes, however, the power context and execlist context will 2391 * never be saved (power context is stored elsewhere, and execlists don't work 2392 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. 2393 */ 2394 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 2395 /* Same as Haswell, but 72064 bytes now. */ 2396 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 2397 2398 #define CHV_CLK_CTL1 0x101100 2399 #define VLV_CLK_CTL2 0x101104 2400 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 2401 2402 /* 2403 * Overlay regs 2404 */ 2405 2406 #define OVADD 0x30000 2407 #define DOVSTA 0x30008 2408 #define OC_BUF (0x3<<20) 2409 #define OGAMC5 0x30010 2410 #define OGAMC4 0x30014 2411 #define OGAMC3 0x30018 2412 #define OGAMC2 0x3001c 2413 #define OGAMC1 0x30020 2414 #define OGAMC0 0x30024 2415 2416 /* 2417 * Display engine regs 2418 */ 2419 2420 /* Pipe A CRC regs */ 2421 #define _PIPE_CRC_CTL_A 0x60050 2422 #define PIPE_CRC_ENABLE (1 << 31) 2423 /* ivb+ source selection */ 2424 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 2425 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 2426 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 2427 /* ilk+ source selection */ 2428 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 2429 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 2430 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 2431 /* embedded DP port on the north display block, reserved on ivb */ 2432 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 2433 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 2434 /* vlv source selection */ 2435 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 2436 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 2437 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 2438 /* with DP port the pipe source is invalid */ 2439 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 2440 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 2441 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 2442 /* gen3+ source selection */ 2443 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 2444 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 2445 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 2446 /* with DP/TV port the pipe source is invalid */ 2447 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 2448 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 2449 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 2450 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 2451 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 2452 /* gen2 doesn't have source selection bits */ 2453 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 2454 2455 #define _PIPE_CRC_RES_1_A_IVB 0x60064 2456 #define _PIPE_CRC_RES_2_A_IVB 0x60068 2457 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 2458 #define _PIPE_CRC_RES_4_A_IVB 0x60070 2459 #define _PIPE_CRC_RES_5_A_IVB 0x60074 2460 2461 #define _PIPE_CRC_RES_RED_A 0x60060 2462 #define _PIPE_CRC_RES_GREEN_A 0x60064 2463 #define _PIPE_CRC_RES_BLUE_A 0x60068 2464 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 2465 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 2466 2467 /* Pipe B CRC regs */ 2468 #define _PIPE_CRC_RES_1_B_IVB 0x61064 2469 #define _PIPE_CRC_RES_2_B_IVB 0x61068 2470 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 2471 #define _PIPE_CRC_RES_4_B_IVB 0x61070 2472 #define _PIPE_CRC_RES_5_B_IVB 0x61074 2473 2474 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) 2475 #define PIPE_CRC_RES_1_IVB(pipe) \ 2476 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) 2477 #define PIPE_CRC_RES_2_IVB(pipe) \ 2478 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) 2479 #define PIPE_CRC_RES_3_IVB(pipe) \ 2480 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) 2481 #define PIPE_CRC_RES_4_IVB(pipe) \ 2482 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) 2483 #define PIPE_CRC_RES_5_IVB(pipe) \ 2484 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) 2485 2486 #define PIPE_CRC_RES_RED(pipe) \ 2487 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) 2488 #define PIPE_CRC_RES_GREEN(pipe) \ 2489 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) 2490 #define PIPE_CRC_RES_BLUE(pipe) \ 2491 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) 2492 #define PIPE_CRC_RES_RES1_I915(pipe) \ 2493 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) 2494 #define PIPE_CRC_RES_RES2_G4X(pipe) \ 2495 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 2496 2497 /* Pipe A timing regs */ 2498 #define _HTOTAL_A 0x60000 2499 #define _HBLANK_A 0x60004 2500 #define _HSYNC_A 0x60008 2501 #define _VTOTAL_A 0x6000c 2502 #define _VBLANK_A 0x60010 2503 #define _VSYNC_A 0x60014 2504 #define _PIPEASRC 0x6001c 2505 #define _BCLRPAT_A 0x60020 2506 #define _VSYNCSHIFT_A 0x60028 2507 #define _PIPE_MULT_A 0x6002c 2508 2509 /* Pipe B timing regs */ 2510 #define _HTOTAL_B 0x61000 2511 #define _HBLANK_B 0x61004 2512 #define _HSYNC_B 0x61008 2513 #define _VTOTAL_B 0x6100c 2514 #define _VBLANK_B 0x61010 2515 #define _VSYNC_B 0x61014 2516 #define _PIPEBSRC 0x6101c 2517 #define _BCLRPAT_B 0x61020 2518 #define _VSYNCSHIFT_B 0x61028 2519 #define _PIPE_MULT_B 0x6102c 2520 2521 #define TRANSCODER_A_OFFSET 0x60000 2522 #define TRANSCODER_B_OFFSET 0x61000 2523 #define TRANSCODER_C_OFFSET 0x62000 2524 #define CHV_TRANSCODER_C_OFFSET 0x63000 2525 #define TRANSCODER_EDP_OFFSET 0x6f000 2526 2527 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ 2528 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 2529 dev_priv->info.display_mmio_offset) 2530 2531 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) 2532 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) 2533 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) 2534 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) 2535 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) 2536 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) 2537 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) 2538 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) 2539 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) 2540 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) 2541 2542 /* HSW+ eDP PSR registers */ 2543 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) 2544 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) 2545 #define EDP_PSR_ENABLE (1<<31) 2546 #define BDW_PSR_SINGLE_FRAME (1<<30) 2547 #define EDP_PSR_LINK_DISABLE (0<<27) 2548 #define EDP_PSR_LINK_STANDBY (1<<27) 2549 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 2550 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 2551 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 2552 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 2553 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 2554 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2555 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 2556 #define EDP_PSR_TP1_TP2_SEL (0<<11) 2557 #define EDP_PSR_TP1_TP3_SEL (1<<11) 2558 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 2559 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 2560 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 2561 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 2562 #define EDP_PSR_TP1_TIME_500us (0<<4) 2563 #define EDP_PSR_TP1_TIME_100us (1<<4) 2564 #define EDP_PSR_TP1_TIME_2500us (2<<4) 2565 #define EDP_PSR_TP1_TIME_0us (3<<4) 2566 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2567 2568 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) 2569 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) 2570 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) 2571 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) 2572 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) 2573 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) 2574 2575 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) 2576 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 2577 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 2578 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 2579 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 2580 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 2581 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 2582 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 2583 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 2584 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 2585 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 2586 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 2587 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 2588 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2589 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2590 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2591 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2592 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 2593 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 2594 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 2595 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 2596 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 2597 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2598 2599 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) 2600 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2601 2602 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) 2603 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 2604 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 2605 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 2606 2607 /* VGA port control */ 2608 #define ADPA 0x61100 2609 #define PCH_ADPA 0xe1100 2610 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) 2611 2612 #define ADPA_DAC_ENABLE (1<<31) 2613 #define ADPA_DAC_DISABLE 0 2614 #define ADPA_PIPE_SELECT_MASK (1<<30) 2615 #define ADPA_PIPE_A_SELECT 0 2616 #define ADPA_PIPE_B_SELECT (1<<30) 2617 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 2618 /* CPT uses bits 29:30 for pch transcoder select */ 2619 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2620 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 2621 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 2622 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 2623 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 2624 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 2625 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 2626 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 2627 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 2628 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 2629 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 2630 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 2631 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 2632 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 2633 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 2634 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 2635 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 2636 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 2637 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 2638 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 2639 #define ADPA_SETS_HVPOLARITY 0 2640 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 2641 #define ADPA_VSYNC_CNTL_ENABLE 0 2642 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 2643 #define ADPA_HSYNC_CNTL_ENABLE 0 2644 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 2645 #define ADPA_VSYNC_ACTIVE_LOW 0 2646 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 2647 #define ADPA_HSYNC_ACTIVE_LOW 0 2648 #define ADPA_DPMS_MASK (~(3<<10)) 2649 #define ADPA_DPMS_ON (0<<10) 2650 #define ADPA_DPMS_SUSPEND (1<<10) 2651 #define ADPA_DPMS_STANDBY (2<<10) 2652 #define ADPA_DPMS_OFF (3<<10) 2653 2654 2655 /* Hotplug control (945+ only) */ 2656 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) 2657 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2658 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2659 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2660 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2661 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2662 #define TV_HOTPLUG_INT_EN (1 << 18) 2663 #define CRT_HOTPLUG_INT_EN (1 << 9) 2664 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2665 PORTC_HOTPLUG_INT_EN | \ 2666 PORTD_HOTPLUG_INT_EN | \ 2667 SDVOC_HOTPLUG_INT_EN | \ 2668 SDVOB_HOTPLUG_INT_EN | \ 2669 CRT_HOTPLUG_INT_EN) 2670 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2671 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2672 /* must use period 64 on GM45 according to docs */ 2673 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2674 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2675 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2676 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2677 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2678 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2679 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2680 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2681 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2682 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2683 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2684 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2685 2686 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) 2687 /* 2688 * HDMI/DP bits are gen4+ 2689 * 2690 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2691 * Please check the detailed lore in the commit message for for experimental 2692 * evidence. 2693 */ 2694 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2695 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2696 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2697 /* VLV DP/HDMI bits again match Bspec */ 2698 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) 2699 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) 2700 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) 2701 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2702 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2703 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2704 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2705 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2706 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2707 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2708 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2709 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2710 /* CRT/TV common between gen3+ */ 2711 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2712 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2713 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2714 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2715 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2716 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2717 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2718 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2719 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2720 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2721 2722 /* SDVO is different across gen3/4 */ 2723 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2724 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2725 /* 2726 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2727 * since reality corrobates that they're the same as on gen3. But keep these 2728 * bits here (and the comment!) to help any other lost wanderers back onto the 2729 * right tracks. 2730 */ 2731 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2732 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2733 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2734 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2735 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2736 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2737 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2738 PORTB_HOTPLUG_INT_STATUS | \ 2739 PORTC_HOTPLUG_INT_STATUS | \ 2740 PORTD_HOTPLUG_INT_STATUS) 2741 2742 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2743 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2744 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2745 PORTB_HOTPLUG_INT_STATUS | \ 2746 PORTC_HOTPLUG_INT_STATUS | \ 2747 PORTD_HOTPLUG_INT_STATUS) 2748 2749 /* SDVO and HDMI port control. 2750 * The same register may be used for SDVO or HDMI */ 2751 #define GEN3_SDVOB 0x61140 2752 #define GEN3_SDVOC 0x61160 2753 #define GEN4_HDMIB GEN3_SDVOB 2754 #define GEN4_HDMIC GEN3_SDVOC 2755 #define CHV_HDMID 0x6116C 2756 #define PCH_SDVOB 0xe1140 2757 #define PCH_HDMIB PCH_SDVOB 2758 #define PCH_HDMIC 0xe1150 2759 #define PCH_HDMID 0xe1160 2760 2761 #define PORT_DFT_I9XX 0x61150 2762 #define DC_BALANCE_RESET (1 << 25) 2763 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) 2764 #define DC_BALANCE_RESET_VLV (1 << 31) 2765 #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) 2766 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 2767 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 2768 2769 /* Gen 3 SDVO bits: */ 2770 #define SDVO_ENABLE (1 << 31) 2771 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2772 #define SDVO_PIPE_SEL_MASK (1 << 30) 2773 #define SDVO_PIPE_B_SELECT (1 << 30) 2774 #define SDVO_STALL_SELECT (1 << 29) 2775 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2776 /* 2777 * 915G/GM SDVO pixel multiplier. 2778 * Programmed value is multiplier - 1, up to 5x. 2779 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2780 */ 2781 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2782 #define SDVO_PORT_MULTIPLY_SHIFT 23 2783 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2784 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2785 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2786 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2787 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2788 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2789 #define SDVO_DETECTED (1 << 2) 2790 /* Bits to be preserved when writing */ 2791 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2792 SDVO_INTERRUPT_ENABLE) 2793 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2794 2795 /* Gen 4 SDVO/HDMI bits: */ 2796 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2797 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2798 #define SDVO_ENCODING_SDVO (0 << 10) 2799 #define SDVO_ENCODING_HDMI (2 << 10) 2800 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2801 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2802 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2803 #define SDVO_AUDIO_ENABLE (1 << 6) 2804 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2805 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2806 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2807 2808 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2809 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2810 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2811 2812 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2813 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2814 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2815 2816 /* CHV SDVO/HDMI bits: */ 2817 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2818 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2819 2820 2821 /* DVO port control */ 2822 #define DVOA 0x61120 2823 #define DVOB 0x61140 2824 #define DVOC 0x61160 2825 #define DVO_ENABLE (1 << 31) 2826 #define DVO_PIPE_B_SELECT (1 << 30) 2827 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2828 #define DVO_PIPE_STALL (1 << 28) 2829 #define DVO_PIPE_STALL_TV (2 << 28) 2830 #define DVO_PIPE_STALL_MASK (3 << 28) 2831 #define DVO_USE_VGA_SYNC (1 << 15) 2832 #define DVO_DATA_ORDER_I740 (0 << 14) 2833 #define DVO_DATA_ORDER_FP (1 << 14) 2834 #define DVO_VSYNC_DISABLE (1 << 11) 2835 #define DVO_HSYNC_DISABLE (1 << 10) 2836 #define DVO_VSYNC_TRISTATE (1 << 9) 2837 #define DVO_HSYNC_TRISTATE (1 << 8) 2838 #define DVO_BORDER_ENABLE (1 << 7) 2839 #define DVO_DATA_ORDER_GBRG (1 << 6) 2840 #define DVO_DATA_ORDER_RGGB (0 << 6) 2841 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2842 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2843 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2844 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2845 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2846 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2847 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2848 #define DVO_PRESERVE_MASK (0x7<<24) 2849 #define DVOA_SRCDIM 0x61124 2850 #define DVOB_SRCDIM 0x61144 2851 #define DVOC_SRCDIM 0x61164 2852 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2853 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2854 2855 /* LVDS port control */ 2856 #define LVDS 0x61180 2857 /* 2858 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2859 * the DPLL semantics change when the LVDS is assigned to that pipe. 2860 */ 2861 #define LVDS_PORT_EN (1 << 31) 2862 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2863 #define LVDS_PIPEB_SELECT (1 << 30) 2864 #define LVDS_PIPE_MASK (1 << 30) 2865 #define LVDS_PIPE(pipe) ((pipe) << 30) 2866 /* LVDS dithering flag on 965/g4x platform */ 2867 #define LVDS_ENABLE_DITHER (1 << 25) 2868 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2869 #define LVDS_VSYNC_POLARITY (1 << 21) 2870 #define LVDS_HSYNC_POLARITY (1 << 20) 2871 2872 /* Enable border for unscaled (or aspect-scaled) display */ 2873 #define LVDS_BORDER_ENABLE (1 << 15) 2874 /* 2875 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2876 * pixel. 2877 */ 2878 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2879 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2880 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2881 /* 2882 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2883 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2884 * on. 2885 */ 2886 #define LVDS_A3_POWER_MASK (3 << 6) 2887 #define LVDS_A3_POWER_DOWN (0 << 6) 2888 #define LVDS_A3_POWER_UP (3 << 6) 2889 /* 2890 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2891 * is set. 2892 */ 2893 #define LVDS_CLKB_POWER_MASK (3 << 4) 2894 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2895 #define LVDS_CLKB_POWER_UP (3 << 4) 2896 /* 2897 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2898 * setting for whether we are in dual-channel mode. The B3 pair will 2899 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2900 */ 2901 #define LVDS_B0B3_POWER_MASK (3 << 2) 2902 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2903 #define LVDS_B0B3_POWER_UP (3 << 2) 2904 2905 /* Video Data Island Packet control */ 2906 #define VIDEO_DIP_DATA 0x61178 2907 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC 2908 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2909 * of the infoframe structure specified by CEA-861. */ 2910 #define VIDEO_DIP_DATA_SIZE 32 2911 #define VIDEO_DIP_VSC_DATA_SIZE 36 2912 #define VIDEO_DIP_CTL 0x61170 2913 /* Pre HSW: */ 2914 #define VIDEO_DIP_ENABLE (1 << 31) 2915 #define VIDEO_DIP_PORT(port) ((port) << 29) 2916 #define VIDEO_DIP_PORT_MASK (3 << 29) 2917 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 2918 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2919 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2920 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 2921 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2922 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2923 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2924 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2925 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2926 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2927 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2928 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2929 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2930 /* HSW and later: */ 2931 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2932 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2933 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2934 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2935 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2936 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2937 2938 /* Panel power sequencing */ 2939 #define PP_STATUS 0x61200 2940 #define PP_ON (1 << 31) 2941 /* 2942 * Indicates that all dependencies of the panel are on: 2943 * 2944 * - PLL enabled 2945 * - pipe enabled 2946 * - LVDS/DVOB/DVOC on 2947 */ 2948 #define PP_READY (1 << 30) 2949 #define PP_SEQUENCE_NONE (0 << 28) 2950 #define PP_SEQUENCE_POWER_UP (1 << 28) 2951 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 2952 #define PP_SEQUENCE_MASK (3 << 28) 2953 #define PP_SEQUENCE_SHIFT 28 2954 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 2955 #define PP_SEQUENCE_STATE_MASK 0x0000000f 2956 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 2957 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 2958 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 2959 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 2960 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 2961 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 2962 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 2963 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 2964 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 2965 #define PP_CONTROL 0x61204 2966 #define POWER_TARGET_ON (1 << 0) 2967 #define PP_ON_DELAYS 0x61208 2968 #define PP_OFF_DELAYS 0x6120c 2969 #define PP_DIVISOR 0x61210 2970 2971 /* Panel fitting */ 2972 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) 2973 #define PFIT_ENABLE (1 << 31) 2974 #define PFIT_PIPE_MASK (3 << 29) 2975 #define PFIT_PIPE_SHIFT 29 2976 #define VERT_INTERP_DISABLE (0 << 10) 2977 #define VERT_INTERP_BILINEAR (1 << 10) 2978 #define VERT_INTERP_MASK (3 << 10) 2979 #define VERT_AUTO_SCALE (1 << 9) 2980 #define HORIZ_INTERP_DISABLE (0 << 6) 2981 #define HORIZ_INTERP_BILINEAR (1 << 6) 2982 #define HORIZ_INTERP_MASK (3 << 6) 2983 #define HORIZ_AUTO_SCALE (1 << 5) 2984 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2985 #define PFIT_FILTER_FUZZY (0 << 24) 2986 #define PFIT_SCALING_AUTO (0 << 26) 2987 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2988 #define PFIT_SCALING_PILLAR (2 << 26) 2989 #define PFIT_SCALING_LETTER (3 << 26) 2990 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) 2991 /* Pre-965 */ 2992 #define PFIT_VERT_SCALE_SHIFT 20 2993 #define PFIT_VERT_SCALE_MASK 0xfff00000 2994 #define PFIT_HORIZ_SCALE_SHIFT 4 2995 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2996 /* 965+ */ 2997 #define PFIT_VERT_SCALE_SHIFT_965 16 2998 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2999 #define PFIT_HORIZ_SCALE_SHIFT_965 0 3000 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 3001 3002 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) 3003 3004 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 3005 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 3006 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 3007 _VLV_BLC_PWM_CTL2_B) 3008 3009 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 3010 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 3011 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 3012 _VLV_BLC_PWM_CTL_B) 3013 3014 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 3015 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 3016 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 3017 _VLV_BLC_HIST_CTL_B) 3018 3019 /* Backlight control */ 3020 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 3021 #define BLM_PWM_ENABLE (1 << 31) 3022 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 3023 #define BLM_PIPE_SELECT (1 << 29) 3024 #define BLM_PIPE_SELECT_IVB (3 << 29) 3025 #define BLM_PIPE_A (0 << 29) 3026 #define BLM_PIPE_B (1 << 29) 3027 #define BLM_PIPE_C (2 << 29) /* ivb + */ 3028 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 3029 #define BLM_TRANSCODER_B BLM_PIPE_B 3030 #define BLM_TRANSCODER_C BLM_PIPE_C 3031 #define BLM_TRANSCODER_EDP (3 << 29) 3032 #define BLM_PIPE(pipe) ((pipe) << 29) 3033 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 3034 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 3035 #define BLM_PHASE_IN_ENABLE (1 << 25) 3036 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 3037 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 3038 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 3039 #define BLM_PHASE_IN_COUNT_SHIFT (8) 3040 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 3041 #define BLM_PHASE_IN_INCR_SHIFT (0) 3042 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 3043 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) 3044 /* 3045 * This is the most significant 15 bits of the number of backlight cycles in a 3046 * complete cycle of the modulated backlight control. 3047 * 3048 * The actual value is this field multiplied by two. 3049 */ 3050 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 3051 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 3052 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 3053 /* 3054 * This is the number of cycles out of the backlight modulation cycle for which 3055 * the backlight is on. 3056 * 3057 * This field must be no greater than the number of cycles in the complete 3058 * backlight modulation cycle. 3059 */ 3060 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 3061 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 3062 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 3063 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 3064 3065 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) 3066 3067 /* New registers for PCH-split platforms. Safe where new bits show up, the 3068 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 3069 #define BLC_PWM_CPU_CTL2 0x48250 3070 #define BLC_PWM_CPU_CTL 0x48254 3071 3072 #define HSW_BLC_PWM2_CTL 0x48350 3073 3074 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 3075 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 3076 #define BLC_PWM_PCH_CTL1 0xc8250 3077 #define BLM_PCH_PWM_ENABLE (1 << 31) 3078 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 3079 #define BLM_PCH_POLARITY (1 << 29) 3080 #define BLC_PWM_PCH_CTL2 0xc8254 3081 3082 #define UTIL_PIN_CTL 0x48400 3083 #define UTIL_PIN_ENABLE (1 << 31) 3084 3085 #define PCH_GTC_CTL 0xe7000 3086 #define PCH_GTC_ENABLE (1 << 31) 3087 3088 /* TV port control */ 3089 #define TV_CTL 0x68000 3090 /* Enables the TV encoder */ 3091 # define TV_ENC_ENABLE (1 << 31) 3092 /* Sources the TV encoder input from pipe B instead of A. */ 3093 # define TV_ENC_PIPEB_SELECT (1 << 30) 3094 /* Outputs composite video (DAC A only) */ 3095 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3096 /* Outputs SVideo video (DAC B/C) */ 3097 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3098 /* Outputs Component video (DAC A/B/C) */ 3099 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3100 /* Outputs Composite and SVideo (DAC A/B/C) */ 3101 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3102 # define TV_TRILEVEL_SYNC (1 << 21) 3103 /* Enables slow sync generation (945GM only) */ 3104 # define TV_SLOW_SYNC (1 << 20) 3105 /* Selects 4x oversampling for 480i and 576p */ 3106 # define TV_OVERSAMPLE_4X (0 << 18) 3107 /* Selects 2x oversampling for 720p and 1080i */ 3108 # define TV_OVERSAMPLE_2X (1 << 18) 3109 /* Selects no oversampling for 1080p */ 3110 # define TV_OVERSAMPLE_NONE (2 << 18) 3111 /* Selects 8x oversampling */ 3112 # define TV_OVERSAMPLE_8X (3 << 18) 3113 /* Selects progressive mode rather than interlaced */ 3114 # define TV_PROGRESSIVE (1 << 17) 3115 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3116 # define TV_PAL_BURST (1 << 16) 3117 /* Field for setting delay of Y compared to C */ 3118 # define TV_YC_SKEW_MASK (7 << 12) 3119 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3120 # define TV_ENC_SDP_FIX (1 << 11) 3121 /* 3122 * Enables a fix for the 915GM only. 3123 * 3124 * Not sure what it does. 3125 */ 3126 # define TV_ENC_C0_FIX (1 << 10) 3127 /* Bits that must be preserved by software */ 3128 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3129 # define TV_FUSE_STATE_MASK (3 << 4) 3130 /* Read-only state that reports all features enabled */ 3131 # define TV_FUSE_STATE_ENABLED (0 << 4) 3132 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3133 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3134 /* Read-only state that reports that TV-out is disabled in hardware. */ 3135 # define TV_FUSE_STATE_DISABLED (2 << 4) 3136 /* Normal operation */ 3137 # define TV_TEST_MODE_NORMAL (0 << 0) 3138 /* Encoder test pattern 1 - combo pattern */ 3139 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3140 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3141 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3142 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3143 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3144 /* Encoder test pattern 4 - random noise */ 3145 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3146 /* Encoder test pattern 5 - linear color ramps */ 3147 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3148 /* 3149 * This test mode forces the DACs to 50% of full output. 3150 * 3151 * This is used for load detection in combination with TVDAC_SENSE_MASK 3152 */ 3153 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3154 # define TV_TEST_MODE_MASK (7 << 0) 3155 3156 #define TV_DAC 0x68004 3157 # define TV_DAC_SAVE 0x00ffff00 3158 /* 3159 * Reports that DAC state change logic has reported change (RO). 3160 * 3161 * This gets cleared when TV_DAC_STATE_EN is cleared 3162 */ 3163 # define TVDAC_STATE_CHG (1 << 31) 3164 # define TVDAC_SENSE_MASK (7 << 28) 3165 /* Reports that DAC A voltage is above the detect threshold */ 3166 # define TVDAC_A_SENSE (1 << 30) 3167 /* Reports that DAC B voltage is above the detect threshold */ 3168 # define TVDAC_B_SENSE (1 << 29) 3169 /* Reports that DAC C voltage is above the detect threshold */ 3170 # define TVDAC_C_SENSE (1 << 28) 3171 /* 3172 * Enables DAC state detection logic, for load-based TV detection. 3173 * 3174 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3175 * to off, for load detection to work. 3176 */ 3177 # define TVDAC_STATE_CHG_EN (1 << 27) 3178 /* Sets the DAC A sense value to high */ 3179 # define TVDAC_A_SENSE_CTL (1 << 26) 3180 /* Sets the DAC B sense value to high */ 3181 # define TVDAC_B_SENSE_CTL (1 << 25) 3182 /* Sets the DAC C sense value to high */ 3183 # define TVDAC_C_SENSE_CTL (1 << 24) 3184 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3185 # define DAC_CTL_OVERRIDE (1 << 7) 3186 /* Sets the slew rate. Must be preserved in software */ 3187 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3188 # define DAC_A_1_3_V (0 << 4) 3189 # define DAC_A_1_1_V (1 << 4) 3190 # define DAC_A_0_7_V (2 << 4) 3191 # define DAC_A_MASK (3 << 4) 3192 # define DAC_B_1_3_V (0 << 2) 3193 # define DAC_B_1_1_V (1 << 2) 3194 # define DAC_B_0_7_V (2 << 2) 3195 # define DAC_B_MASK (3 << 2) 3196 # define DAC_C_1_3_V (0 << 0) 3197 # define DAC_C_1_1_V (1 << 0) 3198 # define DAC_C_0_7_V (2 << 0) 3199 # define DAC_C_MASK (3 << 0) 3200 3201 /* 3202 * CSC coefficients are stored in a floating point format with 9 bits of 3203 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3204 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3205 * -1 (0x3) being the only legal negative value. 3206 */ 3207 #define TV_CSC_Y 0x68010 3208 # define TV_RY_MASK 0x07ff0000 3209 # define TV_RY_SHIFT 16 3210 # define TV_GY_MASK 0x00000fff 3211 # define TV_GY_SHIFT 0 3212 3213 #define TV_CSC_Y2 0x68014 3214 # define TV_BY_MASK 0x07ff0000 3215 # define TV_BY_SHIFT 16 3216 /* 3217 * Y attenuation for component video. 3218 * 3219 * Stored in 1.9 fixed point. 3220 */ 3221 # define TV_AY_MASK 0x000003ff 3222 # define TV_AY_SHIFT 0 3223 3224 #define TV_CSC_U 0x68018 3225 # define TV_RU_MASK 0x07ff0000 3226 # define TV_RU_SHIFT 16 3227 # define TV_GU_MASK 0x000007ff 3228 # define TV_GU_SHIFT 0 3229 3230 #define TV_CSC_U2 0x6801c 3231 # define TV_BU_MASK 0x07ff0000 3232 # define TV_BU_SHIFT 16 3233 /* 3234 * U attenuation for component video. 3235 * 3236 * Stored in 1.9 fixed point. 3237 */ 3238 # define TV_AU_MASK 0x000003ff 3239 # define TV_AU_SHIFT 0 3240 3241 #define TV_CSC_V 0x68020 3242 # define TV_RV_MASK 0x0fff0000 3243 # define TV_RV_SHIFT 16 3244 # define TV_GV_MASK 0x000007ff 3245 # define TV_GV_SHIFT 0 3246 3247 #define TV_CSC_V2 0x68024 3248 # define TV_BV_MASK 0x07ff0000 3249 # define TV_BV_SHIFT 16 3250 /* 3251 * V attenuation for component video. 3252 * 3253 * Stored in 1.9 fixed point. 3254 */ 3255 # define TV_AV_MASK 0x000007ff 3256 # define TV_AV_SHIFT 0 3257 3258 #define TV_CLR_KNOBS 0x68028 3259 /* 2s-complement brightness adjustment */ 3260 # define TV_BRIGHTNESS_MASK 0xff000000 3261 # define TV_BRIGHTNESS_SHIFT 24 3262 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3263 # define TV_CONTRAST_MASK 0x00ff0000 3264 # define TV_CONTRAST_SHIFT 16 3265 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3266 # define TV_SATURATION_MASK 0x0000ff00 3267 # define TV_SATURATION_SHIFT 8 3268 /* Hue adjustment, as an integer phase angle in degrees */ 3269 # define TV_HUE_MASK 0x000000ff 3270 # define TV_HUE_SHIFT 0 3271 3272 #define TV_CLR_LEVEL 0x6802c 3273 /* Controls the DAC level for black */ 3274 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3275 # define TV_BLACK_LEVEL_SHIFT 16 3276 /* Controls the DAC level for blanking */ 3277 # define TV_BLANK_LEVEL_MASK 0x000001ff 3278 # define TV_BLANK_LEVEL_SHIFT 0 3279 3280 #define TV_H_CTL_1 0x68030 3281 /* Number of pixels in the hsync. */ 3282 # define TV_HSYNC_END_MASK 0x1fff0000 3283 # define TV_HSYNC_END_SHIFT 16 3284 /* Total number of pixels minus one in the line (display and blanking). */ 3285 # define TV_HTOTAL_MASK 0x00001fff 3286 # define TV_HTOTAL_SHIFT 0 3287 3288 #define TV_H_CTL_2 0x68034 3289 /* Enables the colorburst (needed for non-component color) */ 3290 # define TV_BURST_ENA (1 << 31) 3291 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3292 # define TV_HBURST_START_SHIFT 16 3293 # define TV_HBURST_START_MASK 0x1fff0000 3294 /* Length of the colorburst */ 3295 # define TV_HBURST_LEN_SHIFT 0 3296 # define TV_HBURST_LEN_MASK 0x0001fff 3297 3298 #define TV_H_CTL_3 0x68038 3299 /* End of hblank, measured in pixels minus one from start of hsync */ 3300 # define TV_HBLANK_END_SHIFT 16 3301 # define TV_HBLANK_END_MASK 0x1fff0000 3302 /* Start of hblank, measured in pixels minus one from start of hsync */ 3303 # define TV_HBLANK_START_SHIFT 0 3304 # define TV_HBLANK_START_MASK 0x0001fff 3305 3306 #define TV_V_CTL_1 0x6803c 3307 /* XXX */ 3308 # define TV_NBR_END_SHIFT 16 3309 # define TV_NBR_END_MASK 0x07ff0000 3310 /* XXX */ 3311 # define TV_VI_END_F1_SHIFT 8 3312 # define TV_VI_END_F1_MASK 0x00003f00 3313 /* XXX */ 3314 # define TV_VI_END_F2_SHIFT 0 3315 # define TV_VI_END_F2_MASK 0x0000003f 3316 3317 #define TV_V_CTL_2 0x68040 3318 /* Length of vsync, in half lines */ 3319 # define TV_VSYNC_LEN_MASK 0x07ff0000 3320 # define TV_VSYNC_LEN_SHIFT 16 3321 /* Offset of the start of vsync in field 1, measured in one less than the 3322 * number of half lines. 3323 */ 3324 # define TV_VSYNC_START_F1_MASK 0x00007f00 3325 # define TV_VSYNC_START_F1_SHIFT 8 3326 /* 3327 * Offset of the start of vsync in field 2, measured in one less than the 3328 * number of half lines. 3329 */ 3330 # define TV_VSYNC_START_F2_MASK 0x0000007f 3331 # define TV_VSYNC_START_F2_SHIFT 0 3332 3333 #define TV_V_CTL_3 0x68044 3334 /* Enables generation of the equalization signal */ 3335 # define TV_EQUAL_ENA (1 << 31) 3336 /* Length of vsync, in half lines */ 3337 # define TV_VEQ_LEN_MASK 0x007f0000 3338 # define TV_VEQ_LEN_SHIFT 16 3339 /* Offset of the start of equalization in field 1, measured in one less than 3340 * the number of half lines. 3341 */ 3342 # define TV_VEQ_START_F1_MASK 0x0007f00 3343 # define TV_VEQ_START_F1_SHIFT 8 3344 /* 3345 * Offset of the start of equalization in field 2, measured in one less than 3346 * the number of half lines. 3347 */ 3348 # define TV_VEQ_START_F2_MASK 0x000007f 3349 # define TV_VEQ_START_F2_SHIFT 0 3350 3351 #define TV_V_CTL_4 0x68048 3352 /* 3353 * Offset to start of vertical colorburst, measured in one less than the 3354 * number of lines from vertical start. 3355 */ 3356 # define TV_VBURST_START_F1_MASK 0x003f0000 3357 # define TV_VBURST_START_F1_SHIFT 16 3358 /* 3359 * Offset to the end of vertical colorburst, measured in one less than the 3360 * number of lines from the start of NBR. 3361 */ 3362 # define TV_VBURST_END_F1_MASK 0x000000ff 3363 # define TV_VBURST_END_F1_SHIFT 0 3364 3365 #define TV_V_CTL_5 0x6804c 3366 /* 3367 * Offset to start of vertical colorburst, measured in one less than the 3368 * number of lines from vertical start. 3369 */ 3370 # define TV_VBURST_START_F2_MASK 0x003f0000 3371 # define TV_VBURST_START_F2_SHIFT 16 3372 /* 3373 * Offset to the end of vertical colorburst, measured in one less than the 3374 * number of lines from the start of NBR. 3375 */ 3376 # define TV_VBURST_END_F2_MASK 0x000000ff 3377 # define TV_VBURST_END_F2_SHIFT 0 3378 3379 #define TV_V_CTL_6 0x68050 3380 /* 3381 * Offset to start of vertical colorburst, measured in one less than the 3382 * number of lines from vertical start. 3383 */ 3384 # define TV_VBURST_START_F3_MASK 0x003f0000 3385 # define TV_VBURST_START_F3_SHIFT 16 3386 /* 3387 * Offset to the end of vertical colorburst, measured in one less than the 3388 * number of lines from the start of NBR. 3389 */ 3390 # define TV_VBURST_END_F3_MASK 0x000000ff 3391 # define TV_VBURST_END_F3_SHIFT 0 3392 3393 #define TV_V_CTL_7 0x68054 3394 /* 3395 * Offset to start of vertical colorburst, measured in one less than the 3396 * number of lines from vertical start. 3397 */ 3398 # define TV_VBURST_START_F4_MASK 0x003f0000 3399 # define TV_VBURST_START_F4_SHIFT 16 3400 /* 3401 * Offset to the end of vertical colorburst, measured in one less than the 3402 * number of lines from the start of NBR. 3403 */ 3404 # define TV_VBURST_END_F4_MASK 0x000000ff 3405 # define TV_VBURST_END_F4_SHIFT 0 3406 3407 #define TV_SC_CTL_1 0x68060 3408 /* Turns on the first subcarrier phase generation DDA */ 3409 # define TV_SC_DDA1_EN (1 << 31) 3410 /* Turns on the first subcarrier phase generation DDA */ 3411 # define TV_SC_DDA2_EN (1 << 30) 3412 /* Turns on the first subcarrier phase generation DDA */ 3413 # define TV_SC_DDA3_EN (1 << 29) 3414 /* Sets the subcarrier DDA to reset frequency every other field */ 3415 # define TV_SC_RESET_EVERY_2 (0 << 24) 3416 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3417 # define TV_SC_RESET_EVERY_4 (1 << 24) 3418 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3419 # define TV_SC_RESET_EVERY_8 (2 << 24) 3420 /* Sets the subcarrier DDA to never reset the frequency */ 3421 # define TV_SC_RESET_NEVER (3 << 24) 3422 /* Sets the peak amplitude of the colorburst.*/ 3423 # define TV_BURST_LEVEL_MASK 0x00ff0000 3424 # define TV_BURST_LEVEL_SHIFT 16 3425 /* Sets the increment of the first subcarrier phase generation DDA */ 3426 # define TV_SCDDA1_INC_MASK 0x00000fff 3427 # define TV_SCDDA1_INC_SHIFT 0 3428 3429 #define TV_SC_CTL_2 0x68064 3430 /* Sets the rollover for the second subcarrier phase generation DDA */ 3431 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3432 # define TV_SCDDA2_SIZE_SHIFT 16 3433 /* Sets the increent of the second subcarrier phase generation DDA */ 3434 # define TV_SCDDA2_INC_MASK 0x00007fff 3435 # define TV_SCDDA2_INC_SHIFT 0 3436 3437 #define TV_SC_CTL_3 0x68068 3438 /* Sets the rollover for the third subcarrier phase generation DDA */ 3439 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3440 # define TV_SCDDA3_SIZE_SHIFT 16 3441 /* Sets the increent of the third subcarrier phase generation DDA */ 3442 # define TV_SCDDA3_INC_MASK 0x00007fff 3443 # define TV_SCDDA3_INC_SHIFT 0 3444 3445 #define TV_WIN_POS 0x68070 3446 /* X coordinate of the display from the start of horizontal active */ 3447 # define TV_XPOS_MASK 0x1fff0000 3448 # define TV_XPOS_SHIFT 16 3449 /* Y coordinate of the display from the start of vertical active (NBR) */ 3450 # define TV_YPOS_MASK 0x00000fff 3451 # define TV_YPOS_SHIFT 0 3452 3453 #define TV_WIN_SIZE 0x68074 3454 /* Horizontal size of the display window, measured in pixels*/ 3455 # define TV_XSIZE_MASK 0x1fff0000 3456 # define TV_XSIZE_SHIFT 16 3457 /* 3458 * Vertical size of the display window, measured in pixels. 3459 * 3460 * Must be even for interlaced modes. 3461 */ 3462 # define TV_YSIZE_MASK 0x00000fff 3463 # define TV_YSIZE_SHIFT 0 3464 3465 #define TV_FILTER_CTL_1 0x68080 3466 /* 3467 * Enables automatic scaling calculation. 3468 * 3469 * If set, the rest of the registers are ignored, and the calculated values can 3470 * be read back from the register. 3471 */ 3472 # define TV_AUTO_SCALE (1 << 31) 3473 /* 3474 * Disables the vertical filter. 3475 * 3476 * This is required on modes more than 1024 pixels wide */ 3477 # define TV_V_FILTER_BYPASS (1 << 29) 3478 /* Enables adaptive vertical filtering */ 3479 # define TV_VADAPT (1 << 28) 3480 # define TV_VADAPT_MODE_MASK (3 << 26) 3481 /* Selects the least adaptive vertical filtering mode */ 3482 # define TV_VADAPT_MODE_LEAST (0 << 26) 3483 /* Selects the moderately adaptive vertical filtering mode */ 3484 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3485 /* Selects the most adaptive vertical filtering mode */ 3486 # define TV_VADAPT_MODE_MOST (3 << 26) 3487 /* 3488 * Sets the horizontal scaling factor. 3489 * 3490 * This should be the fractional part of the horizontal scaling factor divided 3491 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3492 * 3493 * (src width - 1) / ((oversample * dest width) - 1) 3494 */ 3495 # define TV_HSCALE_FRAC_MASK 0x00003fff 3496 # define TV_HSCALE_FRAC_SHIFT 0 3497 3498 #define TV_FILTER_CTL_2 0x68084 3499 /* 3500 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3501 * 3502 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3503 */ 3504 # define TV_VSCALE_INT_MASK 0x00038000 3505 # define TV_VSCALE_INT_SHIFT 15 3506 /* 3507 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3508 * 3509 * \sa TV_VSCALE_INT_MASK 3510 */ 3511 # define TV_VSCALE_FRAC_MASK 0x00007fff 3512 # define TV_VSCALE_FRAC_SHIFT 0 3513 3514 #define TV_FILTER_CTL_3 0x68088 3515 /* 3516 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3517 * 3518 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3519 * 3520 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3521 */ 3522 # define TV_VSCALE_IP_INT_MASK 0x00038000 3523 # define TV_VSCALE_IP_INT_SHIFT 15 3524 /* 3525 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3526 * 3527 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3528 * 3529 * \sa TV_VSCALE_IP_INT_MASK 3530 */ 3531 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3532 # define TV_VSCALE_IP_FRAC_SHIFT 0 3533 3534 #define TV_CC_CONTROL 0x68090 3535 # define TV_CC_ENABLE (1 << 31) 3536 /* 3537 * Specifies which field to send the CC data in. 3538 * 3539 * CC data is usually sent in field 0. 3540 */ 3541 # define TV_CC_FID_MASK (1 << 27) 3542 # define TV_CC_FID_SHIFT 27 3543 /* Sets the horizontal position of the CC data. Usually 135. */ 3544 # define TV_CC_HOFF_MASK 0x03ff0000 3545 # define TV_CC_HOFF_SHIFT 16 3546 /* Sets the vertical position of the CC data. Usually 21 */ 3547 # define TV_CC_LINE_MASK 0x0000003f 3548 # define TV_CC_LINE_SHIFT 0 3549 3550 #define TV_CC_DATA 0x68094 3551 # define TV_CC_RDY (1 << 31) 3552 /* Second word of CC data to be transmitted. */ 3553 # define TV_CC_DATA_2_MASK 0x007f0000 3554 # define TV_CC_DATA_2_SHIFT 16 3555 /* First word of CC data to be transmitted. */ 3556 # define TV_CC_DATA_1_MASK 0x0000007f 3557 # define TV_CC_DATA_1_SHIFT 0 3558 3559 #define TV_H_LUMA_0 0x68100 3560 #define TV_H_LUMA_59 0x681ec 3561 #define TV_H_CHROMA_0 0x68200 3562 #define TV_H_CHROMA_59 0x682ec 3563 #define TV_V_LUMA_0 0x68300 3564 #define TV_V_LUMA_42 0x683a8 3565 #define TV_V_CHROMA_0 0x68400 3566 #define TV_V_CHROMA_42 0x684a8 3567 3568 /* Display Port */ 3569 #define DP_A 0x64000 /* eDP */ 3570 #define DP_B 0x64100 3571 #define DP_C 0x64200 3572 #define DP_D 0x64300 3573 3574 #define DP_PORT_EN (1 << 31) 3575 #define DP_PIPEB_SELECT (1 << 30) 3576 #define DP_PIPE_MASK (1 << 30) 3577 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 3578 #define DP_PIPE_MASK_CHV (3 << 16) 3579 3580 /* Link training mode - select a suitable mode for each stage */ 3581 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3582 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3583 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3584 #define DP_LINK_TRAIN_OFF (3 << 28) 3585 #define DP_LINK_TRAIN_MASK (3 << 28) 3586 #define DP_LINK_TRAIN_SHIFT 28 3587 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 3588 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 3589 3590 /* CPT Link training mode */ 3591 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3592 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3593 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3594 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3595 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3596 #define DP_LINK_TRAIN_SHIFT_CPT 8 3597 3598 /* Signal voltages. These are mostly controlled by the other end */ 3599 #define DP_VOLTAGE_0_4 (0 << 25) 3600 #define DP_VOLTAGE_0_6 (1 << 25) 3601 #define DP_VOLTAGE_0_8 (2 << 25) 3602 #define DP_VOLTAGE_1_2 (3 << 25) 3603 #define DP_VOLTAGE_MASK (7 << 25) 3604 #define DP_VOLTAGE_SHIFT 25 3605 3606 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3607 * they want 3608 */ 3609 #define DP_PRE_EMPHASIS_0 (0 << 22) 3610 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3611 #define DP_PRE_EMPHASIS_6 (2 << 22) 3612 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3613 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3614 #define DP_PRE_EMPHASIS_SHIFT 22 3615 3616 /* How many wires to use. I guess 3 was too hard */ 3617 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3618 #define DP_PORT_WIDTH_MASK (7 << 19) 3619 3620 /* Mystic DPCD version 1.1 special mode */ 3621 #define DP_ENHANCED_FRAMING (1 << 18) 3622 3623 /* eDP */ 3624 #define DP_PLL_FREQ_270MHZ (0 << 16) 3625 #define DP_PLL_FREQ_160MHZ (1 << 16) 3626 #define DP_PLL_FREQ_MASK (3 << 16) 3627 3628 /* locked once port is enabled */ 3629 #define DP_PORT_REVERSAL (1 << 15) 3630 3631 /* eDP */ 3632 #define DP_PLL_ENABLE (1 << 14) 3633 3634 /* sends the clock on lane 15 of the PEG for debug */ 3635 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3636 3637 #define DP_SCRAMBLING_DISABLE (1 << 12) 3638 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3639 3640 /* limit RGB values to avoid confusing TVs */ 3641 #define DP_COLOR_RANGE_16_235 (1 << 8) 3642 3643 /* Turn on the audio link */ 3644 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3645 3646 /* vs and hs sync polarity */ 3647 #define DP_SYNC_VS_HIGH (1 << 4) 3648 #define DP_SYNC_HS_HIGH (1 << 3) 3649 3650 /* A fantasy */ 3651 #define DP_DETECTED (1 << 2) 3652 3653 /* The aux channel provides a way to talk to the 3654 * signal sink for DDC etc. Max packet size supported 3655 * is 20 bytes in each direction, hence the 5 fixed 3656 * data registers 3657 */ 3658 #define DPA_AUX_CH_CTL 0x64010 3659 #define DPA_AUX_CH_DATA1 0x64014 3660 #define DPA_AUX_CH_DATA2 0x64018 3661 #define DPA_AUX_CH_DATA3 0x6401c 3662 #define DPA_AUX_CH_DATA4 0x64020 3663 #define DPA_AUX_CH_DATA5 0x64024 3664 3665 #define DPB_AUX_CH_CTL 0x64110 3666 #define DPB_AUX_CH_DATA1 0x64114 3667 #define DPB_AUX_CH_DATA2 0x64118 3668 #define DPB_AUX_CH_DATA3 0x6411c 3669 #define DPB_AUX_CH_DATA4 0x64120 3670 #define DPB_AUX_CH_DATA5 0x64124 3671 3672 #define DPC_AUX_CH_CTL 0x64210 3673 #define DPC_AUX_CH_DATA1 0x64214 3674 #define DPC_AUX_CH_DATA2 0x64218 3675 #define DPC_AUX_CH_DATA3 0x6421c 3676 #define DPC_AUX_CH_DATA4 0x64220 3677 #define DPC_AUX_CH_DATA5 0x64224 3678 3679 #define DPD_AUX_CH_CTL 0x64310 3680 #define DPD_AUX_CH_DATA1 0x64314 3681 #define DPD_AUX_CH_DATA2 0x64318 3682 #define DPD_AUX_CH_DATA3 0x6431c 3683 #define DPD_AUX_CH_DATA4 0x64320 3684 #define DPD_AUX_CH_DATA5 0x64324 3685 3686 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3687 #define DP_AUX_CH_CTL_DONE (1 << 30) 3688 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3689 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3690 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3691 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3692 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3693 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 3694 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3695 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3696 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3697 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3698 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3699 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3700 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3701 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3702 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3703 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3704 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3705 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3706 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3707 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3708 3709 /* 3710 * Computing GMCH M and N values for the Display Port link 3711 * 3712 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3713 * 3714 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3715 * 3716 * The GMCH value is used internally 3717 * 3718 * bytes_per_pixel is the number of bytes coming out of the plane, 3719 * which is after the LUTs, so we want the bytes for our color format. 3720 * For our current usage, this is always 3, one byte for R, G and B. 3721 */ 3722 #define _PIPEA_DATA_M_G4X 0x70050 3723 #define _PIPEB_DATA_M_G4X 0x71050 3724 3725 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3726 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 3727 #define TU_SIZE_SHIFT 25 3728 #define TU_SIZE_MASK (0x3f << 25) 3729 3730 #define DATA_LINK_M_N_MASK (0xffffff) 3731 #define DATA_LINK_N_MAX (0x800000) 3732 3733 #define _PIPEA_DATA_N_G4X 0x70054 3734 #define _PIPEB_DATA_N_G4X 0x71054 3735 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 3736 3737 /* 3738 * Computing Link M and N values for the Display Port link 3739 * 3740 * Link M / N = pixel_clock / ls_clk 3741 * 3742 * (the DP spec calls pixel_clock the 'strm_clk') 3743 * 3744 * The Link value is transmitted in the Main Stream 3745 * Attributes and VB-ID. 3746 */ 3747 3748 #define _PIPEA_LINK_M_G4X 0x70060 3749 #define _PIPEB_LINK_M_G4X 0x71060 3750 #define PIPEA_DP_LINK_M_MASK (0xffffff) 3751 3752 #define _PIPEA_LINK_N_G4X 0x70064 3753 #define _PIPEB_LINK_N_G4X 0x71064 3754 #define PIPEA_DP_LINK_N_MASK (0xffffff) 3755 3756 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3757 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3758 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3759 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3760 3761 /* Display & cursor control */ 3762 3763 /* Pipe A */ 3764 #define _PIPEADSL 0x70000 3765 #define DSL_LINEMASK_GEN2 0x00000fff 3766 #define DSL_LINEMASK_GEN3 0x00001fff 3767 #define _PIPEACONF 0x70008 3768 #define PIPECONF_ENABLE (1<<31) 3769 #define PIPECONF_DISABLE 0 3770 #define PIPECONF_DOUBLE_WIDE (1<<30) 3771 #define I965_PIPECONF_ACTIVE (1<<30) 3772 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 3773 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 3774 #define PIPECONF_SINGLE_WIDE 0 3775 #define PIPECONF_PIPE_UNLOCKED 0 3776 #define PIPECONF_PIPE_LOCKED (1<<25) 3777 #define PIPECONF_PALETTE 0 3778 #define PIPECONF_GAMMA (1<<24) 3779 #define PIPECONF_FORCE_BORDER (1<<25) 3780 #define PIPECONF_INTERLACE_MASK (7 << 21) 3781 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 3782 /* Note that pre-gen3 does not support interlaced display directly. Panel 3783 * fitting must be disabled on pre-ilk for interlaced. */ 3784 #define PIPECONF_PROGRESSIVE (0 << 21) 3785 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 3786 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 3787 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 3788 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 3789 /* Ironlake and later have a complete new set of values for interlaced. PFIT 3790 * means panel fitter required, PF means progressive fetch, DBL means power 3791 * saving pixel doubling. */ 3792 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 3793 #define PIPECONF_INTERLACED_ILK (3 << 21) 3794 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 3795 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 3796 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 3797 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 3798 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 3799 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 3800 #define PIPECONF_BPC_MASK (0x7 << 5) 3801 #define PIPECONF_8BPC (0<<5) 3802 #define PIPECONF_10BPC (1<<5) 3803 #define PIPECONF_6BPC (2<<5) 3804 #define PIPECONF_12BPC (3<<5) 3805 #define PIPECONF_DITHER_EN (1<<4) 3806 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 3807 #define PIPECONF_DITHER_TYPE_SP (0<<2) 3808 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 3809 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 3810 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 3811 #define _PIPEASTAT 0x70024 3812 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 3813 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 3814 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 3815 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 3816 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 3817 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 3818 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 3819 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 3820 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 3821 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 3822 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 3823 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 3824 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 3825 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 3826 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 3827 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 3828 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 3829 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 3830 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 3831 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 3832 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 3833 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 3834 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 3835 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 3836 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 3837 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 3838 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 3839 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 3840 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 3841 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 3842 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 3843 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 3844 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 3845 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 3846 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 3847 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3848 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 3849 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 3850 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 3851 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 3852 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 3853 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 3854 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 3855 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 3856 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 3857 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 3858 3859 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3860 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3861 3862 #define PIPE_A_OFFSET 0x70000 3863 #define PIPE_B_OFFSET 0x71000 3864 #define PIPE_C_OFFSET 0x72000 3865 #define CHV_PIPE_C_OFFSET 0x74000 3866 /* 3867 * There's actually no pipe EDP. Some pipe registers have 3868 * simply shifted from the pipe to the transcoder, while 3869 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3870 * to access such registers in transcoder EDP. 3871 */ 3872 #define PIPE_EDP_OFFSET 0x7f000 3873 3874 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ 3875 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 3876 dev_priv->info.display_mmio_offset) 3877 3878 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) 3879 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) 3880 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) 3881 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) 3882 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) 3883 3884 #define _PIPE_MISC_A 0x70030 3885 #define _PIPE_MISC_B 0x71030 3886 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 3887 #define PIPEMISC_DITHER_8_BPC (0<<5) 3888 #define PIPEMISC_DITHER_10_BPC (1<<5) 3889 #define PIPEMISC_DITHER_6_BPC (2<<5) 3890 #define PIPEMISC_DITHER_12_BPC (3<<5) 3891 #define PIPEMISC_DITHER_ENABLE (1<<4) 3892 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 3893 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 3894 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) 3895 3896 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) 3897 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 3898 #define PIPEB_HLINE_INT_EN (1<<28) 3899 #define PIPEB_VBLANK_INT_EN (1<<27) 3900 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 3901 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 3902 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 3903 #define PIPE_PSR_INT_EN (1<<22) 3904 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 3905 #define PIPEA_HLINE_INT_EN (1<<20) 3906 #define PIPEA_VBLANK_INT_EN (1<<19) 3907 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 3908 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 3909 #define PLANEA_FLIPDONE_INT_EN (1<<16) 3910 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 3911 #define PIPEC_HLINE_INT_EN (1<<12) 3912 #define PIPEC_VBLANK_INT_EN (1<<11) 3913 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 3914 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 3915 #define PLANEC_FLIPDONE_INT_EN (1<<8) 3916 3917 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3918 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 3919 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 3920 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 3921 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 3922 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 3923 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 3924 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 3925 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 3926 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 3927 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 3928 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 3929 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 3930 #define DPINVGTT_EN_MASK 0xff0000 3931 #define DPINVGTT_EN_MASK_CHV 0xfff0000 3932 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 3933 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 3934 #define PLANEC_INVALID_GTT_STATUS (1<<9) 3935 #define CURSORC_INVALID_GTT_STATUS (1<<8) 3936 #define CURSORB_INVALID_GTT_STATUS (1<<7) 3937 #define CURSORA_INVALID_GTT_STATUS (1<<6) 3938 #define SPRITED_INVALID_GTT_STATUS (1<<5) 3939 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 3940 #define PLANEB_INVALID_GTT_STATUS (1<<3) 3941 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 3942 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 3943 #define PLANEA_INVALID_GTT_STATUS (1<<0) 3944 #define DPINVGTT_STATUS_MASK 0xff 3945 #define DPINVGTT_STATUS_MASK_CHV 0xfff 3946 3947 #define DSPARB 0x70030 3948 #define DSPARB_CSTART_MASK (0x7f << 7) 3949 #define DSPARB_CSTART_SHIFT 7 3950 #define DSPARB_BSTART_MASK (0x7f) 3951 #define DSPARB_BSTART_SHIFT 0 3952 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3953 #define DSPARB_AEND_SHIFT 0 3954 3955 /* pnv/gen4/g4x/vlv/chv */ 3956 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) 3957 #define DSPFW_SR_SHIFT 23 3958 #define DSPFW_SR_MASK (0x1ff<<23) 3959 #define DSPFW_CURSORB_SHIFT 16 3960 #define DSPFW_CURSORB_MASK (0x3f<<16) 3961 #define DSPFW_PLANEB_SHIFT 8 3962 #define DSPFW_PLANEB_MASK (0x7f<<8) 3963 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 3964 #define DSPFW_PLANEA_SHIFT 0 3965 #define DSPFW_PLANEA_MASK (0x7f<<0) 3966 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 3967 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) 3968 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 3969 #define DSPFW_FBC_SR_SHIFT 28 3970 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 3971 #define DSPFW_FBC_HPLL_SR_SHIFT 24 3972 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 3973 #define DSPFW_SPRITEB_SHIFT (16) 3974 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 3975 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 3976 #define DSPFW_CURSORA_SHIFT 8 3977 #define DSPFW_CURSORA_MASK (0x3f<<8) 3978 #define DSPFW_PLANEC_SHIFT_OLD 0 3979 #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ 3980 #define DSPFW_SPRITEA_SHIFT 0 3981 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 3982 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 3983 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) 3984 #define DSPFW_HPLL_SR_EN (1<<31) 3985 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 3986 #define DSPFW_CURSOR_SR_SHIFT 24 3987 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 3988 #define DSPFW_HPLL_CURSOR_SHIFT 16 3989 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 3990 #define DSPFW_HPLL_SR_SHIFT 0 3991 #define DSPFW_HPLL_SR_MASK (0x1ff<<0) 3992 3993 /* vlv/chv */ 3994 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) 3995 #define DSPFW_SPRITEB_WM1_SHIFT 16 3996 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 3997 #define DSPFW_CURSORA_WM1_SHIFT 8 3998 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 3999 #define DSPFW_SPRITEA_WM1_SHIFT 0 4000 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 4001 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) 4002 #define DSPFW_PLANEB_WM1_SHIFT 24 4003 #define DSPFW_PLANEB_WM1_MASK (0xff<<24) 4004 #define DSPFW_PLANEA_WM1_SHIFT 16 4005 #define DSPFW_PLANEA_WM1_MASK (0xff<<16) 4006 #define DSPFW_CURSORB_WM1_SHIFT 8 4007 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 4008 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4009 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 4010 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) 4011 #define DSPFW_SR_WM1_SHIFT 0 4012 #define DSPFW_SR_WM1_MASK (0x1ff<<0) 4013 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) 4014 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4015 #define DSPFW_SPRITED_WM1_SHIFT 24 4016 #define DSPFW_SPRITED_WM1_MASK (0xff<<24) 4017 #define DSPFW_SPRITED_SHIFT 16 4018 #define DSPFW_SPRITED_MASK (0xff<<16) 4019 #define DSPFW_SPRITEC_WM1_SHIFT 8 4020 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 4021 #define DSPFW_SPRITEC_SHIFT 0 4022 #define DSPFW_SPRITEC_MASK (0xff<<0) 4023 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) 4024 #define DSPFW_SPRITEF_WM1_SHIFT 24 4025 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 4026 #define DSPFW_SPRITEF_SHIFT 16 4027 #define DSPFW_SPRITEF_MASK (0xff<<16) 4028 #define DSPFW_SPRITEE_WM1_SHIFT 8 4029 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 4030 #define DSPFW_SPRITEE_SHIFT 0 4031 #define DSPFW_SPRITEE_MASK (0xff<<0) 4032 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4033 #define DSPFW_PLANEC_WM1_SHIFT 24 4034 #define DSPFW_PLANEC_WM1_MASK (0xff<<24) 4035 #define DSPFW_PLANEC_SHIFT 16 4036 #define DSPFW_PLANEC_MASK (0xff<<16) 4037 #define DSPFW_CURSORC_WM1_SHIFT 8 4038 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 4039 #define DSPFW_CURSORC_SHIFT 0 4040 #define DSPFW_CURSORC_MASK (0x3f<<0) 4041 4042 /* vlv/chv high order bits */ 4043 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) 4044 #define DSPFW_SR_HI_SHIFT 24 4045 #define DSPFW_SR_HI_MASK (1<<24) 4046 #define DSPFW_SPRITEF_HI_SHIFT 23 4047 #define DSPFW_SPRITEF_HI_MASK (1<<23) 4048 #define DSPFW_SPRITEE_HI_SHIFT 22 4049 #define DSPFW_SPRITEE_HI_MASK (1<<22) 4050 #define DSPFW_PLANEC_HI_SHIFT 21 4051 #define DSPFW_PLANEC_HI_MASK (1<<21) 4052 #define DSPFW_SPRITED_HI_SHIFT 20 4053 #define DSPFW_SPRITED_HI_MASK (1<<20) 4054 #define DSPFW_SPRITEC_HI_SHIFT 16 4055 #define DSPFW_SPRITEC_HI_MASK (1<<16) 4056 #define DSPFW_PLANEB_HI_SHIFT 12 4057 #define DSPFW_PLANEB_HI_MASK (1<<12) 4058 #define DSPFW_SPRITEB_HI_SHIFT 8 4059 #define DSPFW_SPRITEB_HI_MASK (1<<8) 4060 #define DSPFW_SPRITEA_HI_SHIFT 4 4061 #define DSPFW_SPRITEA_HI_MASK (1<<4) 4062 #define DSPFW_PLANEA_HI_SHIFT 0 4063 #define DSPFW_PLANEA_HI_MASK (1<<0) 4064 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) 4065 #define DSPFW_SR_WM1_HI_SHIFT 24 4066 #define DSPFW_SR_WM1_HI_MASK (1<<24) 4067 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4068 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 4069 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4070 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 4071 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4072 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 4073 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4074 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 4075 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4076 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 4077 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4078 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 4079 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4080 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 4081 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4082 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 4083 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4084 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 4085 4086 /* drain latency register values*/ 4087 #define DRAIN_LATENCY_PRECISION_16 16 4088 #define DRAIN_LATENCY_PRECISION_32 32 4089 #define DRAIN_LATENCY_PRECISION_64 64 4090 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4091 #define DDL_CURSOR_PRECISION_HIGH (1<<31) 4092 #define DDL_CURSOR_PRECISION_LOW (0<<31) 4093 #define DDL_CURSOR_SHIFT 24 4094 #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite))) 4095 #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite))) 4096 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 4097 #define DDL_PLANE_PRECISION_HIGH (1<<7) 4098 #define DDL_PLANE_PRECISION_LOW (0<<7) 4099 #define DDL_PLANE_SHIFT 0 4100 #define DRAIN_LATENCY_MASK 0x7f 4101 4102 /* FIFO watermark sizes etc */ 4103 #define G4X_FIFO_LINE_SIZE 64 4104 #define I915_FIFO_LINE_SIZE 64 4105 #define I830_FIFO_LINE_SIZE 32 4106 4107 #define VALLEYVIEW_FIFO_SIZE 255 4108 #define G4X_FIFO_SIZE 127 4109 #define I965_FIFO_SIZE 512 4110 #define I945_FIFO_SIZE 127 4111 #define I915_FIFO_SIZE 95 4112 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4113 #define I830_FIFO_SIZE 95 4114 4115 #define VALLEYVIEW_MAX_WM 0xff 4116 #define G4X_MAX_WM 0x3f 4117 #define I915_MAX_WM 0x3f 4118 4119 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4120 #define PINEVIEW_FIFO_LINE_SIZE 64 4121 #define PINEVIEW_MAX_WM 0x1ff 4122 #define PINEVIEW_DFT_WM 0x3f 4123 #define PINEVIEW_DFT_HPLLOFF_WM 0 4124 #define PINEVIEW_GUARD_WM 10 4125 #define PINEVIEW_CURSOR_FIFO 64 4126 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4127 #define PINEVIEW_CURSOR_DFT_WM 0 4128 #define PINEVIEW_CURSOR_GUARD_WM 5 4129 4130 #define VALLEYVIEW_CURSOR_MAX_WM 64 4131 #define I965_CURSOR_FIFO 64 4132 #define I965_CURSOR_MAX_WM 32 4133 #define I965_CURSOR_DFT_WM 8 4134 4135 /* Watermark register definitions for SKL */ 4136 #define CUR_WM_A_0 0x70140 4137 #define CUR_WM_B_0 0x71140 4138 #define PLANE_WM_1_A_0 0x70240 4139 #define PLANE_WM_1_B_0 0x71240 4140 #define PLANE_WM_2_A_0 0x70340 4141 #define PLANE_WM_2_B_0 0x71340 4142 #define PLANE_WM_TRANS_1_A_0 0x70268 4143 #define PLANE_WM_TRANS_1_B_0 0x71268 4144 #define PLANE_WM_TRANS_2_A_0 0x70368 4145 #define PLANE_WM_TRANS_2_B_0 0x71368 4146 #define CUR_WM_TRANS_A_0 0x70168 4147 #define CUR_WM_TRANS_B_0 0x71168 4148 #define PLANE_WM_EN (1 << 31) 4149 #define PLANE_WM_LINES_SHIFT 14 4150 #define PLANE_WM_LINES_MASK 0x1f 4151 #define PLANE_WM_BLOCKS_MASK 0x3ff 4152 4153 #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0) 4154 #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level))) 4155 #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0) 4156 4157 #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0) 4158 #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0) 4159 #define _PLANE_WM_BASE(pipe, plane) \ 4160 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4161 #define PLANE_WM(pipe, plane, level) \ 4162 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4163 #define _PLANE_WM_TRANS_1(pipe) \ 4164 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0) 4165 #define _PLANE_WM_TRANS_2(pipe) \ 4166 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0) 4167 #define PLANE_WM_TRANS(pipe, plane) \ 4168 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)) 4169 4170 /* define the Watermark register on Ironlake */ 4171 #define WM0_PIPEA_ILK 0x45100 4172 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 4173 #define WM0_PIPE_PLANE_SHIFT 16 4174 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 4175 #define WM0_PIPE_SPRITE_SHIFT 8 4176 #define WM0_PIPE_CURSOR_MASK (0xff) 4177 4178 #define WM0_PIPEB_ILK 0x45104 4179 #define WM0_PIPEC_IVB 0x45200 4180 #define WM1_LP_ILK 0x45108 4181 #define WM1_LP_SR_EN (1<<31) 4182 #define WM1_LP_LATENCY_SHIFT 24 4183 #define WM1_LP_LATENCY_MASK (0x7f<<24) 4184 #define WM1_LP_FBC_MASK (0xf<<20) 4185 #define WM1_LP_FBC_SHIFT 20 4186 #define WM1_LP_FBC_SHIFT_BDW 19 4187 #define WM1_LP_SR_MASK (0x7ff<<8) 4188 #define WM1_LP_SR_SHIFT 8 4189 #define WM1_LP_CURSOR_MASK (0xff) 4190 #define WM2_LP_ILK 0x4510c 4191 #define WM2_LP_EN (1<<31) 4192 #define WM3_LP_ILK 0x45110 4193 #define WM3_LP_EN (1<<31) 4194 #define WM1S_LP_ILK 0x45120 4195 #define WM2S_LP_IVB 0x45124 4196 #define WM3S_LP_IVB 0x45128 4197 #define WM1S_LP_EN (1<<31) 4198 4199 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4200 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 4201 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 4202 4203 /* Memory latency timer register */ 4204 #define MLTR_ILK 0x11222 4205 #define MLTR_WM1_SHIFT 0 4206 #define MLTR_WM2_SHIFT 8 4207 /* the unit of memory self-refresh latency time is 0.5us */ 4208 #define ILK_SRLT_MASK 0x3f 4209 4210 4211 /* the address where we get all kinds of latency value */ 4212 #define SSKPD 0x5d10 4213 #define SSKPD_WM_MASK 0x3f 4214 #define SSKPD_WM0_SHIFT 0 4215 #define SSKPD_WM1_SHIFT 8 4216 #define SSKPD_WM2_SHIFT 16 4217 #define SSKPD_WM3_SHIFT 24 4218 4219 /* 4220 * The two pipe frame counter registers are not synchronized, so 4221 * reading a stable value is somewhat tricky. The following code 4222 * should work: 4223 * 4224 * do { 4225 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4226 * PIPE_FRAME_HIGH_SHIFT; 4227 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4228 * PIPE_FRAME_LOW_SHIFT); 4229 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4230 * PIPE_FRAME_HIGH_SHIFT); 4231 * } while (high1 != high2); 4232 * frame = (high1 << 8) | low1; 4233 */ 4234 #define _PIPEAFRAMEHIGH 0x70040 4235 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4236 #define PIPE_FRAME_HIGH_SHIFT 0 4237 #define _PIPEAFRAMEPIXEL 0x70044 4238 #define PIPE_FRAME_LOW_MASK 0xff000000 4239 #define PIPE_FRAME_LOW_SHIFT 24 4240 #define PIPE_PIXEL_MASK 0x00ffffff 4241 #define PIPE_PIXEL_SHIFT 0 4242 /* GM45+ just has to be different */ 4243 #define _PIPEA_FRMCOUNT_GM45 0x70040 4244 #define _PIPEA_FLIPCOUNT_GM45 0x70044 4245 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) 4246 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) 4247 4248 /* Cursor A & B regs */ 4249 #define _CURACNTR 0x70080 4250 /* Old style CUR*CNTR flags (desktop 8xx) */ 4251 #define CURSOR_ENABLE 0x80000000 4252 #define CURSOR_GAMMA_ENABLE 0x40000000 4253 #define CURSOR_STRIDE_SHIFT 28 4254 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 4255 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 4256 #define CURSOR_FORMAT_SHIFT 24 4257 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 4258 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 4259 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 4260 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 4261 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 4262 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 4263 /* New style CUR*CNTR flags */ 4264 #define CURSOR_MODE 0x27 4265 #define CURSOR_MODE_DISABLE 0x00 4266 #define CURSOR_MODE_128_32B_AX 0x02 4267 #define CURSOR_MODE_256_32B_AX 0x03 4268 #define CURSOR_MODE_64_32B_AX 0x07 4269 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 4270 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 4271 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 4272 #define MCURSOR_PIPE_SELECT (1 << 28) 4273 #define MCURSOR_PIPE_A 0x00 4274 #define MCURSOR_PIPE_B (1 << 28) 4275 #define MCURSOR_GAMMA_ENABLE (1 << 26) 4276 #define CURSOR_ROTATE_180 (1<<15) 4277 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 4278 #define _CURABASE 0x70084 4279 #define _CURAPOS 0x70088 4280 #define CURSOR_POS_MASK 0x007FF 4281 #define CURSOR_POS_SIGN 0x8000 4282 #define CURSOR_X_SHIFT 0 4283 #define CURSOR_Y_SHIFT 16 4284 #define CURSIZE 0x700a0 4285 #define _CURBCNTR 0x700c0 4286 #define _CURBBASE 0x700c4 4287 #define _CURBPOS 0x700c8 4288 4289 #define _CURBCNTR_IVB 0x71080 4290 #define _CURBBASE_IVB 0x71084 4291 #define _CURBPOS_IVB 0x71088 4292 4293 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ 4294 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 4295 dev_priv->info.display_mmio_offset) 4296 4297 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 4298 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 4299 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 4300 4301 #define CURSOR_A_OFFSET 0x70080 4302 #define CURSOR_B_OFFSET 0x700c0 4303 #define CHV_CURSOR_C_OFFSET 0x700e0 4304 #define IVB_CURSOR_B_OFFSET 0x71080 4305 #define IVB_CURSOR_C_OFFSET 0x72080 4306 4307 /* Display A control */ 4308 #define _DSPACNTR 0x70180 4309 #define DISPLAY_PLANE_ENABLE (1<<31) 4310 #define DISPLAY_PLANE_DISABLE 0 4311 #define DISPPLANE_GAMMA_ENABLE (1<<30) 4312 #define DISPPLANE_GAMMA_DISABLE 0 4313 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 4314 #define DISPPLANE_YUV422 (0x0<<26) 4315 #define DISPPLANE_8BPP (0x2<<26) 4316 #define DISPPLANE_BGRA555 (0x3<<26) 4317 #define DISPPLANE_BGRX555 (0x4<<26) 4318 #define DISPPLANE_BGRX565 (0x5<<26) 4319 #define DISPPLANE_BGRX888 (0x6<<26) 4320 #define DISPPLANE_BGRA888 (0x7<<26) 4321 #define DISPPLANE_RGBX101010 (0x8<<26) 4322 #define DISPPLANE_RGBA101010 (0x9<<26) 4323 #define DISPPLANE_BGRX101010 (0xa<<26) 4324 #define DISPPLANE_RGBX161616 (0xc<<26) 4325 #define DISPPLANE_RGBX888 (0xe<<26) 4326 #define DISPPLANE_RGBA888 (0xf<<26) 4327 #define DISPPLANE_STEREO_ENABLE (1<<25) 4328 #define DISPPLANE_STEREO_DISABLE 0 4329 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 4330 #define DISPPLANE_SEL_PIPE_SHIFT 24 4331 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 4332 #define DISPPLANE_SEL_PIPE_A 0 4333 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 4334 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 4335 #define DISPPLANE_SRC_KEY_DISABLE 0 4336 #define DISPPLANE_LINE_DOUBLE (1<<20) 4337 #define DISPPLANE_NO_LINE_DOUBLE 0 4338 #define DISPPLANE_STEREO_POLARITY_FIRST 0 4339 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 4340 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ 4341 #define DISPPLANE_ROTATE_180 (1<<15) 4342 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 4343 #define DISPPLANE_TILED (1<<10) 4344 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ 4345 #define _DSPAADDR 0x70184 4346 #define _DSPASTRIDE 0x70188 4347 #define _DSPAPOS 0x7018C /* reserved */ 4348 #define _DSPASIZE 0x70190 4349 #define _DSPASURF 0x7019C /* 965+ only */ 4350 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4351 #define _DSPAOFFSET 0x701A4 /* HSW */ 4352 #define _DSPASURFLIVE 0x701AC 4353 4354 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) 4355 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) 4356 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) 4357 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) 4358 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) 4359 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) 4360 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) 4361 #define DSPLINOFF(plane) DSPADDR(plane) 4362 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) 4363 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) 4364 4365 /* CHV pipe B blender and primary plane */ 4366 #define _CHV_BLEND_A 0x60a00 4367 #define CHV_BLEND_LEGACY (0<<30) 4368 #define CHV_BLEND_ANDROID (1<<30) 4369 #define CHV_BLEND_MPO (2<<30) 4370 #define CHV_BLEND_MASK (3<<30) 4371 #define _CHV_CANVAS_A 0x60a04 4372 #define _PRIMPOS_A 0x60a08 4373 #define _PRIMSIZE_A 0x60a0c 4374 #define _PRIMCNSTALPHA_A 0x60a10 4375 #define PRIM_CONST_ALPHA_ENABLE (1<<31) 4376 4377 #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A) 4378 #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A) 4379 #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A) 4380 #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A) 4381 #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A) 4382 4383 /* Display/Sprite base address macros */ 4384 #define DISP_BASEADDR_MASK (0xfffff000) 4385 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 4386 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 4387 4388 /* VBIOS flags */ 4389 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) 4390 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) 4391 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) 4392 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) 4393 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) 4394 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) 4395 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) 4396 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) 4397 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) 4398 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) 4399 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) 4400 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) 4401 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) 4402 4403 /* Pipe B */ 4404 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 4405 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 4406 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 4407 #define _PIPEBFRAMEHIGH 0x71040 4408 #define _PIPEBFRAMEPIXEL 0x71044 4409 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) 4410 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) 4411 4412 4413 /* Display B control */ 4414 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 4415 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 4416 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 4417 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 4418 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 4419 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 4420 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 4421 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 4422 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 4423 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 4424 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 4425 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 4426 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 4427 4428 /* Sprite A control */ 4429 #define _DVSACNTR 0x72180 4430 #define DVS_ENABLE (1<<31) 4431 #define DVS_GAMMA_ENABLE (1<<30) 4432 #define DVS_PIXFORMAT_MASK (3<<25) 4433 #define DVS_FORMAT_YUV422 (0<<25) 4434 #define DVS_FORMAT_RGBX101010 (1<<25) 4435 #define DVS_FORMAT_RGBX888 (2<<25) 4436 #define DVS_FORMAT_RGBX161616 (3<<25) 4437 #define DVS_PIPE_CSC_ENABLE (1<<24) 4438 #define DVS_SOURCE_KEY (1<<22) 4439 #define DVS_RGB_ORDER_XBGR (1<<20) 4440 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 4441 #define DVS_YUV_ORDER_YUYV (0<<16) 4442 #define DVS_YUV_ORDER_UYVY (1<<16) 4443 #define DVS_YUV_ORDER_YVYU (2<<16) 4444 #define DVS_YUV_ORDER_VYUY (3<<16) 4445 #define DVS_ROTATE_180 (1<<15) 4446 #define DVS_DEST_KEY (1<<2) 4447 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 4448 #define DVS_TILED (1<<10) 4449 #define _DVSALINOFF 0x72184 4450 #define _DVSASTRIDE 0x72188 4451 #define _DVSAPOS 0x7218c 4452 #define _DVSASIZE 0x72190 4453 #define _DVSAKEYVAL 0x72194 4454 #define _DVSAKEYMSK 0x72198 4455 #define _DVSASURF 0x7219c 4456 #define _DVSAKEYMAXVAL 0x721a0 4457 #define _DVSATILEOFF 0x721a4 4458 #define _DVSASURFLIVE 0x721ac 4459 #define _DVSASCALE 0x72204 4460 #define DVS_SCALE_ENABLE (1<<31) 4461 #define DVS_FILTER_MASK (3<<29) 4462 #define DVS_FILTER_MEDIUM (0<<29) 4463 #define DVS_FILTER_ENHANCING (1<<29) 4464 #define DVS_FILTER_SOFTENING (2<<29) 4465 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4466 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 4467 #define _DVSAGAMC 0x72300 4468 4469 #define _DVSBCNTR 0x73180 4470 #define _DVSBLINOFF 0x73184 4471 #define _DVSBSTRIDE 0x73188 4472 #define _DVSBPOS 0x7318c 4473 #define _DVSBSIZE 0x73190 4474 #define _DVSBKEYVAL 0x73194 4475 #define _DVSBKEYMSK 0x73198 4476 #define _DVSBSURF 0x7319c 4477 #define _DVSBKEYMAXVAL 0x731a0 4478 #define _DVSBTILEOFF 0x731a4 4479 #define _DVSBSURFLIVE 0x731ac 4480 #define _DVSBSCALE 0x73204 4481 #define _DVSBGAMC 0x73300 4482 4483 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4484 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4485 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4486 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 4487 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 4488 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4489 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4490 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4491 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4492 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4493 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4494 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4495 4496 #define _SPRA_CTL 0x70280 4497 #define SPRITE_ENABLE (1<<31) 4498 #define SPRITE_GAMMA_ENABLE (1<<30) 4499 #define SPRITE_PIXFORMAT_MASK (7<<25) 4500 #define SPRITE_FORMAT_YUV422 (0<<25) 4501 #define SPRITE_FORMAT_RGBX101010 (1<<25) 4502 #define SPRITE_FORMAT_RGBX888 (2<<25) 4503 #define SPRITE_FORMAT_RGBX161616 (3<<25) 4504 #define SPRITE_FORMAT_YUV444 (4<<25) 4505 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 4506 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 4507 #define SPRITE_SOURCE_KEY (1<<22) 4508 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 4509 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 4510 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 4511 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 4512 #define SPRITE_YUV_ORDER_YUYV (0<<16) 4513 #define SPRITE_YUV_ORDER_UYVY (1<<16) 4514 #define SPRITE_YUV_ORDER_YVYU (2<<16) 4515 #define SPRITE_YUV_ORDER_VYUY (3<<16) 4516 #define SPRITE_ROTATE_180 (1<<15) 4517 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 4518 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 4519 #define SPRITE_TILED (1<<10) 4520 #define SPRITE_DEST_KEY (1<<2) 4521 #define _SPRA_LINOFF 0x70284 4522 #define _SPRA_STRIDE 0x70288 4523 #define _SPRA_POS 0x7028c 4524 #define _SPRA_SIZE 0x70290 4525 #define _SPRA_KEYVAL 0x70294 4526 #define _SPRA_KEYMSK 0x70298 4527 #define _SPRA_SURF 0x7029c 4528 #define _SPRA_KEYMAX 0x702a0 4529 #define _SPRA_TILEOFF 0x702a4 4530 #define _SPRA_OFFSET 0x702a4 4531 #define _SPRA_SURFLIVE 0x702ac 4532 #define _SPRA_SCALE 0x70304 4533 #define SPRITE_SCALE_ENABLE (1<<31) 4534 #define SPRITE_FILTER_MASK (3<<29) 4535 #define SPRITE_FILTER_MEDIUM (0<<29) 4536 #define SPRITE_FILTER_ENHANCING (1<<29) 4537 #define SPRITE_FILTER_SOFTENING (2<<29) 4538 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4539 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 4540 #define _SPRA_GAMC 0x70400 4541 4542 #define _SPRB_CTL 0x71280 4543 #define _SPRB_LINOFF 0x71284 4544 #define _SPRB_STRIDE 0x71288 4545 #define _SPRB_POS 0x7128c 4546 #define _SPRB_SIZE 0x71290 4547 #define _SPRB_KEYVAL 0x71294 4548 #define _SPRB_KEYMSK 0x71298 4549 #define _SPRB_SURF 0x7129c 4550 #define _SPRB_KEYMAX 0x712a0 4551 #define _SPRB_TILEOFF 0x712a4 4552 #define _SPRB_OFFSET 0x712a4 4553 #define _SPRB_SURFLIVE 0x712ac 4554 #define _SPRB_SCALE 0x71304 4555 #define _SPRB_GAMC 0x71400 4556 4557 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4558 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4559 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4560 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 4561 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4562 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4563 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4564 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4565 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4566 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4567 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4568 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4569 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 4570 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4571 4572 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4573 #define SP_ENABLE (1<<31) 4574 #define SP_GAMMA_ENABLE (1<<30) 4575 #define SP_PIXFORMAT_MASK (0xf<<26) 4576 #define SP_FORMAT_YUV422 (0<<26) 4577 #define SP_FORMAT_BGR565 (5<<26) 4578 #define SP_FORMAT_BGRX8888 (6<<26) 4579 #define SP_FORMAT_BGRA8888 (7<<26) 4580 #define SP_FORMAT_RGBX1010102 (8<<26) 4581 #define SP_FORMAT_RGBA1010102 (9<<26) 4582 #define SP_FORMAT_RGBX8888 (0xe<<26) 4583 #define SP_FORMAT_RGBA8888 (0xf<<26) 4584 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ 4585 #define SP_SOURCE_KEY (1<<22) 4586 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 4587 #define SP_YUV_ORDER_YUYV (0<<16) 4588 #define SP_YUV_ORDER_UYVY (1<<16) 4589 #define SP_YUV_ORDER_YVYU (2<<16) 4590 #define SP_YUV_ORDER_VYUY (3<<16) 4591 #define SP_ROTATE_180 (1<<15) 4592 #define SP_TILED (1<<10) 4593 #define SP_MIRROR (1<<8) /* CHV pipe B */ 4594 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4595 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4596 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4597 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4598 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4599 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4600 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4601 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4602 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4603 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4604 #define SP_CONST_ALPHA_ENABLE (1<<31) 4605 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 4606 4607 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4608 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4609 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4610 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4611 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4612 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4613 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4614 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4615 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4616 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4617 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4618 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 4619 4620 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) 4621 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) 4622 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) 4623 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) 4624 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) 4625 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) 4626 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) 4627 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) 4628 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4629 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) 4630 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) 4631 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) 4632 4633 /* 4634 * CHV pipe B sprite CSC 4635 * 4636 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4637 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4638 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4639 */ 4640 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) 4641 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) 4642 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) 4643 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 4644 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 4645 4646 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) 4647 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) 4648 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) 4649 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) 4650 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) 4651 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 4652 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 4653 4654 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) 4655 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) 4656 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) 4657 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 4658 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 4659 4660 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) 4661 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) 4662 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) 4663 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 4664 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 4665 4666 /* Skylake plane registers */ 4667 4668 #define _PLANE_CTL_1_A 0x70180 4669 #define _PLANE_CTL_2_A 0x70280 4670 #define _PLANE_CTL_3_A 0x70380 4671 #define PLANE_CTL_ENABLE (1 << 31) 4672 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) 4673 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 4674 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) 4675 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) 4676 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) 4677 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) 4678 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) 4679 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) 4680 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) 4681 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) 4682 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) 4683 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 4684 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) 4685 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) 4686 #define PLANE_CTL_ORDER_BGRX (0 << 20) 4687 #define PLANE_CTL_ORDER_RGBX (1 << 20) 4688 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 4689 #define PLANE_CTL_YUV422_YUYV ( 0 << 16) 4690 #define PLANE_CTL_YUV422_UYVY ( 1 << 16) 4691 #define PLANE_CTL_YUV422_YVYU ( 2 << 16) 4692 #define PLANE_CTL_YUV422_VYUY ( 3 << 16) 4693 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) 4694 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 4695 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) 4696 #define PLANE_CTL_TILED_MASK (0x7 << 10) 4697 #define PLANE_CTL_TILED_LINEAR ( 0 << 10) 4698 #define PLANE_CTL_TILED_X ( 1 << 10) 4699 #define PLANE_CTL_TILED_Y ( 4 << 10) 4700 #define PLANE_CTL_TILED_YF ( 5 << 10) 4701 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) 4702 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) 4703 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) 4704 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) 4705 #define PLANE_CTL_ROTATE_MASK 0x3 4706 #define PLANE_CTL_ROTATE_0 0x0 4707 #define PLANE_CTL_ROTATE_180 0x2 4708 #define _PLANE_STRIDE_1_A 0x70188 4709 #define _PLANE_STRIDE_2_A 0x70288 4710 #define _PLANE_STRIDE_3_A 0x70388 4711 #define _PLANE_POS_1_A 0x7018c 4712 #define _PLANE_POS_2_A 0x7028c 4713 #define _PLANE_POS_3_A 0x7038c 4714 #define _PLANE_SIZE_1_A 0x70190 4715 #define _PLANE_SIZE_2_A 0x70290 4716 #define _PLANE_SIZE_3_A 0x70390 4717 #define _PLANE_SURF_1_A 0x7019c 4718 #define _PLANE_SURF_2_A 0x7029c 4719 #define _PLANE_SURF_3_A 0x7039c 4720 #define _PLANE_OFFSET_1_A 0x701a4 4721 #define _PLANE_OFFSET_2_A 0x702a4 4722 #define _PLANE_OFFSET_3_A 0x703a4 4723 #define _PLANE_KEYVAL_1_A 0x70194 4724 #define _PLANE_KEYVAL_2_A 0x70294 4725 #define _PLANE_KEYMSK_1_A 0x70198 4726 #define _PLANE_KEYMSK_2_A 0x70298 4727 #define _PLANE_KEYMAX_1_A 0x701a0 4728 #define _PLANE_KEYMAX_2_A 0x702a0 4729 #define _PLANE_BUF_CFG_1_A 0x7027c 4730 #define _PLANE_BUF_CFG_2_A 0x7037c 4731 4732 #define _PLANE_CTL_1_B 0x71180 4733 #define _PLANE_CTL_2_B 0x71280 4734 #define _PLANE_CTL_3_B 0x71380 4735 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 4736 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 4737 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 4738 #define PLANE_CTL(pipe, plane) \ 4739 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 4740 4741 #define _PLANE_STRIDE_1_B 0x71188 4742 #define _PLANE_STRIDE_2_B 0x71288 4743 #define _PLANE_STRIDE_3_B 0x71388 4744 #define _PLANE_STRIDE_1(pipe) \ 4745 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 4746 #define _PLANE_STRIDE_2(pipe) \ 4747 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 4748 #define _PLANE_STRIDE_3(pipe) \ 4749 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 4750 #define PLANE_STRIDE(pipe, plane) \ 4751 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 4752 4753 #define _PLANE_POS_1_B 0x7118c 4754 #define _PLANE_POS_2_B 0x7128c 4755 #define _PLANE_POS_3_B 0x7138c 4756 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 4757 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 4758 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 4759 #define PLANE_POS(pipe, plane) \ 4760 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 4761 4762 #define _PLANE_SIZE_1_B 0x71190 4763 #define _PLANE_SIZE_2_B 0x71290 4764 #define _PLANE_SIZE_3_B 0x71390 4765 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 4766 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 4767 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 4768 #define PLANE_SIZE(pipe, plane) \ 4769 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 4770 4771 #define _PLANE_SURF_1_B 0x7119c 4772 #define _PLANE_SURF_2_B 0x7129c 4773 #define _PLANE_SURF_3_B 0x7139c 4774 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 4775 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 4776 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 4777 #define PLANE_SURF(pipe, plane) \ 4778 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 4779 4780 #define _PLANE_OFFSET_1_B 0x711a4 4781 #define _PLANE_OFFSET_2_B 0x712a4 4782 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 4783 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 4784 #define PLANE_OFFSET(pipe, plane) \ 4785 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 4786 4787 #define _PLANE_KEYVAL_1_B 0x71194 4788 #define _PLANE_KEYVAL_2_B 0x71294 4789 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 4790 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 4791 #define PLANE_KEYVAL(pipe, plane) \ 4792 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 4793 4794 #define _PLANE_KEYMSK_1_B 0x71198 4795 #define _PLANE_KEYMSK_2_B 0x71298 4796 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 4797 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 4798 #define PLANE_KEYMSK(pipe, plane) \ 4799 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 4800 4801 #define _PLANE_KEYMAX_1_B 0x711a0 4802 #define _PLANE_KEYMAX_2_B 0x712a0 4803 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 4804 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 4805 #define PLANE_KEYMAX(pipe, plane) \ 4806 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 4807 4808 #define _PLANE_BUF_CFG_1_B 0x7127c 4809 #define _PLANE_BUF_CFG_2_B 0x7137c 4810 #define _PLANE_BUF_CFG_1(pipe) \ 4811 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 4812 #define _PLANE_BUF_CFG_2(pipe) \ 4813 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 4814 #define PLANE_BUF_CFG(pipe, plane) \ 4815 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 4816 4817 /* SKL new cursor registers */ 4818 #define _CUR_BUF_CFG_A 0x7017c 4819 #define _CUR_BUF_CFG_B 0x7117c 4820 #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 4821 4822 /* VBIOS regs */ 4823 #define VGACNTRL 0x71400 4824 # define VGA_DISP_DISABLE (1 << 31) 4825 # define VGA_2X_MODE (1 << 30) 4826 # define VGA_PIPE_B_SELECT (1 << 29) 4827 4828 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) 4829 4830 /* Ironlake */ 4831 4832 #define CPU_VGACNTRL 0x41000 4833 4834 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 4835 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 4836 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 4837 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 4838 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 4839 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 4840 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 4841 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 4842 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 4843 4844 /* refresh rate hardware control */ 4845 #define RR_HW_CTL 0x45300 4846 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 4847 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 4848 4849 #define FDI_PLL_BIOS_0 0x46000 4850 #define FDI_PLL_FB_CLOCK_MASK 0xff 4851 #define FDI_PLL_BIOS_1 0x46004 4852 #define FDI_PLL_BIOS_2 0x46008 4853 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 4854 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 4855 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 4856 4857 #define PCH_3DCGDIS0 0x46020 4858 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 4859 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 4860 4861 #define PCH_3DCGDIS1 0x46024 4862 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 4863 4864 #define FDI_PLL_FREQ_CTL 0x46030 4865 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 4866 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 4867 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 4868 4869 4870 #define _PIPEA_DATA_M1 0x60030 4871 #define PIPE_DATA_M1_OFFSET 0 4872 #define _PIPEA_DATA_N1 0x60034 4873 #define PIPE_DATA_N1_OFFSET 0 4874 4875 #define _PIPEA_DATA_M2 0x60038 4876 #define PIPE_DATA_M2_OFFSET 0 4877 #define _PIPEA_DATA_N2 0x6003c 4878 #define PIPE_DATA_N2_OFFSET 0 4879 4880 #define _PIPEA_LINK_M1 0x60040 4881 #define PIPE_LINK_M1_OFFSET 0 4882 #define _PIPEA_LINK_N1 0x60044 4883 #define PIPE_LINK_N1_OFFSET 0 4884 4885 #define _PIPEA_LINK_M2 0x60048 4886 #define PIPE_LINK_M2_OFFSET 0 4887 #define _PIPEA_LINK_N2 0x6004c 4888 #define PIPE_LINK_N2_OFFSET 0 4889 4890 /* PIPEB timing regs are same start from 0x61000 */ 4891 4892 #define _PIPEB_DATA_M1 0x61030 4893 #define _PIPEB_DATA_N1 0x61034 4894 #define _PIPEB_DATA_M2 0x61038 4895 #define _PIPEB_DATA_N2 0x6103c 4896 #define _PIPEB_LINK_M1 0x61040 4897 #define _PIPEB_LINK_N1 0x61044 4898 #define _PIPEB_LINK_M2 0x61048 4899 #define _PIPEB_LINK_N2 0x6104c 4900 4901 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) 4902 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) 4903 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) 4904 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) 4905 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) 4906 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) 4907 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) 4908 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) 4909 4910 /* CPU panel fitter */ 4911 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 4912 #define _PFA_CTL_1 0x68080 4913 #define _PFB_CTL_1 0x68880 4914 #define PF_ENABLE (1<<31) 4915 #define PF_PIPE_SEL_MASK_IVB (3<<29) 4916 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 4917 #define PF_FILTER_MASK (3<<23) 4918 #define PF_FILTER_PROGRAMMED (0<<23) 4919 #define PF_FILTER_MED_3x3 (1<<23) 4920 #define PF_FILTER_EDGE_ENHANCE (2<<23) 4921 #define PF_FILTER_EDGE_SOFTEN (3<<23) 4922 #define _PFA_WIN_SZ 0x68074 4923 #define _PFB_WIN_SZ 0x68874 4924 #define _PFA_WIN_POS 0x68070 4925 #define _PFB_WIN_POS 0x68870 4926 #define _PFA_VSCALE 0x68084 4927 #define _PFB_VSCALE 0x68884 4928 #define _PFA_HSCALE 0x68090 4929 #define _PFB_HSCALE 0x68890 4930 4931 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 4932 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 4933 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 4934 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 4935 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 4936 4937 #define _PSA_CTL 0x68180 4938 #define _PSB_CTL 0x68980 4939 #define PS_ENABLE (1<<31) 4940 #define _PSA_WIN_SZ 0x68174 4941 #define _PSB_WIN_SZ 0x68974 4942 #define _PSA_WIN_POS 0x68170 4943 #define _PSB_WIN_POS 0x68970 4944 4945 #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) 4946 #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 4947 #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 4948 4949 /* legacy palette */ 4950 #define _LGC_PALETTE_A 0x4a000 4951 #define _LGC_PALETTE_B 0x4a800 4952 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 4953 4954 #define _GAMMA_MODE_A 0x4a480 4955 #define _GAMMA_MODE_B 0x4ac80 4956 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 4957 #define GAMMA_MODE_MODE_MASK (3 << 0) 4958 #define GAMMA_MODE_MODE_8BIT (0 << 0) 4959 #define GAMMA_MODE_MODE_10BIT (1 << 0) 4960 #define GAMMA_MODE_MODE_12BIT (2 << 0) 4961 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 4962 4963 /* interrupts */ 4964 #define DE_MASTER_IRQ_CONTROL (1 << 31) 4965 #define DE_SPRITEB_FLIP_DONE (1 << 29) 4966 #define DE_SPRITEA_FLIP_DONE (1 << 28) 4967 #define DE_PLANEB_FLIP_DONE (1 << 27) 4968 #define DE_PLANEA_FLIP_DONE (1 << 26) 4969 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 4970 #define DE_PCU_EVENT (1 << 25) 4971 #define DE_GTT_FAULT (1 << 24) 4972 #define DE_POISON (1 << 23) 4973 #define DE_PERFORM_COUNTER (1 << 22) 4974 #define DE_PCH_EVENT (1 << 21) 4975 #define DE_AUX_CHANNEL_A (1 << 20) 4976 #define DE_DP_A_HOTPLUG (1 << 19) 4977 #define DE_GSE (1 << 18) 4978 #define DE_PIPEB_VBLANK (1 << 15) 4979 #define DE_PIPEB_EVEN_FIELD (1 << 14) 4980 #define DE_PIPEB_ODD_FIELD (1 << 13) 4981 #define DE_PIPEB_LINE_COMPARE (1 << 12) 4982 #define DE_PIPEB_VSYNC (1 << 11) 4983 #define DE_PIPEB_CRC_DONE (1 << 10) 4984 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 4985 #define DE_PIPEA_VBLANK (1 << 7) 4986 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 4987 #define DE_PIPEA_EVEN_FIELD (1 << 6) 4988 #define DE_PIPEA_ODD_FIELD (1 << 5) 4989 #define DE_PIPEA_LINE_COMPARE (1 << 4) 4990 #define DE_PIPEA_VSYNC (1 << 3) 4991 #define DE_PIPEA_CRC_DONE (1 << 2) 4992 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 4993 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 4994 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 4995 4996 /* More Ivybridge lolz */ 4997 #define DE_ERR_INT_IVB (1<<30) 4998 #define DE_GSE_IVB (1<<29) 4999 #define DE_PCH_EVENT_IVB (1<<28) 5000 #define DE_DP_A_HOTPLUG_IVB (1<<27) 5001 #define DE_AUX_CHANNEL_A_IVB (1<<26) 5002 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 5003 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 5004 #define DE_PIPEC_VBLANK_IVB (1<<10) 5005 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 5006 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 5007 #define DE_PIPEB_VBLANK_IVB (1<<5) 5008 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 5009 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 5010 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 5011 #define DE_PIPEA_VBLANK_IVB (1<<0) 5012 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) 5013 5014 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 5015 #define MASTER_INTERRUPT_ENABLE (1<<31) 5016 5017 #define DEISR 0x44000 5018 #define DEIMR 0x44004 5019 #define DEIIR 0x44008 5020 #define DEIER 0x4400c 5021 5022 #define GTISR 0x44010 5023 #define GTIMR 0x44014 5024 #define GTIIR 0x44018 5025 #define GTIER 0x4401c 5026 5027 #define GEN8_MASTER_IRQ 0x44200 5028 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 5029 #define GEN8_PCU_IRQ (1<<30) 5030 #define GEN8_DE_PCH_IRQ (1<<23) 5031 #define GEN8_DE_MISC_IRQ (1<<22) 5032 #define GEN8_DE_PORT_IRQ (1<<20) 5033 #define GEN8_DE_PIPE_C_IRQ (1<<18) 5034 #define GEN8_DE_PIPE_B_IRQ (1<<17) 5035 #define GEN8_DE_PIPE_A_IRQ (1<<16) 5036 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) 5037 #define GEN8_GT_VECS_IRQ (1<<6) 5038 #define GEN8_GT_PM_IRQ (1<<4) 5039 #define GEN8_GT_VCS2_IRQ (1<<3) 5040 #define GEN8_GT_VCS1_IRQ (1<<2) 5041 #define GEN8_GT_BCS_IRQ (1<<1) 5042 #define GEN8_GT_RCS_IRQ (1<<0) 5043 5044 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) 5045 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) 5046 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) 5047 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) 5048 5049 #define GEN8_BCS_IRQ_SHIFT 16 5050 #define GEN8_RCS_IRQ_SHIFT 0 5051 #define GEN8_VCS2_IRQ_SHIFT 16 5052 #define GEN8_VCS1_IRQ_SHIFT 0 5053 #define GEN8_VECS_IRQ_SHIFT 0 5054 5055 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) 5056 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) 5057 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) 5058 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) 5059 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5060 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5061 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5062 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5063 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5064 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5065 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5066 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5067 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5068 #define GEN8_PIPE_VSYNC (1 << 1) 5069 #define GEN8_PIPE_VBLANK (1 << 0) 5070 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5071 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5072 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5073 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5074 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5075 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5076 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5077 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) 5078 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5079 (GEN8_PIPE_CURSOR_FAULT | \ 5080 GEN8_PIPE_SPRITE_FAULT | \ 5081 GEN8_PIPE_PRIMARY_FAULT) 5082 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5083 (GEN9_PIPE_CURSOR_FAULT | \ 5084 GEN9_PIPE_PLANE3_FAULT | \ 5085 GEN9_PIPE_PLANE2_FAULT | \ 5086 GEN9_PIPE_PLANE1_FAULT) 5087 5088 #define GEN8_DE_PORT_ISR 0x44440 5089 #define GEN8_DE_PORT_IMR 0x44444 5090 #define GEN8_DE_PORT_IIR 0x44448 5091 #define GEN8_DE_PORT_IER 0x4444c 5092 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 5093 #define GEN9_AUX_CHANNEL_D (1 << 27) 5094 #define GEN9_AUX_CHANNEL_C (1 << 26) 5095 #define GEN9_AUX_CHANNEL_B (1 << 25) 5096 #define GEN8_AUX_CHANNEL_A (1 << 0) 5097 5098 #define GEN8_DE_MISC_ISR 0x44460 5099 #define GEN8_DE_MISC_IMR 0x44464 5100 #define GEN8_DE_MISC_IIR 0x44468 5101 #define GEN8_DE_MISC_IER 0x4446c 5102 #define GEN8_DE_MISC_GSE (1 << 27) 5103 5104 #define GEN8_PCU_ISR 0x444e0 5105 #define GEN8_PCU_IMR 0x444e4 5106 #define GEN8_PCU_IIR 0x444e8 5107 #define GEN8_PCU_IER 0x444ec 5108 5109 #define ILK_DISPLAY_CHICKEN2 0x42004 5110 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5111 #define ILK_ELPIN_409_SELECT (1 << 25) 5112 #define ILK_DPARB_GATE (1<<22) 5113 #define ILK_VSDPFD_FULL (1<<21) 5114 #define FUSE_STRAP 0x42014 5115 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5116 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5117 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5118 #define ILK_HDCP_DISABLE (1 << 25) 5119 #define ILK_eDP_A_DISABLE (1 << 24) 5120 #define HSW_CDCLK_LIMIT (1 << 24) 5121 #define ILK_DESKTOP (1 << 23) 5122 5123 #define ILK_DSPCLK_GATE_D 0x42020 5124 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5125 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5126 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5127 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5128 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5129 5130 #define IVB_CHICKEN3 0x4200c 5131 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5132 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5133 5134 #define CHICKEN_PAR1_1 0x42080 5135 #define DPA_MASK_VBLANK_SRD (1 << 15) 5136 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5137 5138 #define _CHICKEN_PIPESL_1_A 0x420b0 5139 #define _CHICKEN_PIPESL_1_B 0x420b4 5140 #define HSW_FBCQ_DIS (1 << 22) 5141 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5142 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5143 5144 #define DISP_ARB_CTL 0x45000 5145 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 5146 #define DISP_FBC_WM_DIS (1<<15) 5147 #define DISP_ARB_CTL2 0x45004 5148 #define DISP_DATA_PARTITION_5_6 (1<<6) 5149 #define GEN7_MSG_CTL 0x45010 5150 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 5151 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 5152 #define HSW_NDE_RSTWRN_OPT 0x46408 5153 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 5154 5155 /* GEN7 chicken */ 5156 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 5157 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 5158 #define COMMON_SLICE_CHICKEN2 0x7014 5159 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 5160 5161 #define GEN7_L3SQCREG1 0xB010 5162 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 5163 5164 #define GEN7_L3CNTLREG1 0xB01C 5165 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 5166 #define GEN7_L3AGDIS (1<<19) 5167 #define GEN7_L3CNTLREG2 0xB020 5168 #define GEN7_L3CNTLREG3 0xB024 5169 5170 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 5171 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 5172 5173 #define GEN7_L3SQCREG4 0xb034 5174 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 5175 5176 /* GEN8 chicken */ 5177 #define HDC_CHICKEN0 0x7300 5178 #define HDC_FORCE_NON_COHERENT (1<<4) 5179 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 5180 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 5181 5182 /* WaCatErrorRejectionIssue */ 5183 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 5184 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 5185 5186 #define HSW_SCRATCH1 0xb038 5187 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 5188 5189 /* PCH */ 5190 5191 /* south display engine interrupt: IBX */ 5192 #define SDE_AUDIO_POWER_D (1 << 27) 5193 #define SDE_AUDIO_POWER_C (1 << 26) 5194 #define SDE_AUDIO_POWER_B (1 << 25) 5195 #define SDE_AUDIO_POWER_SHIFT (25) 5196 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5197 #define SDE_GMBUS (1 << 24) 5198 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5199 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5200 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5201 #define SDE_AUDIO_TRANSB (1 << 21) 5202 #define SDE_AUDIO_TRANSA (1 << 20) 5203 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5204 #define SDE_POISON (1 << 19) 5205 /* 18 reserved */ 5206 #define SDE_FDI_RXB (1 << 17) 5207 #define SDE_FDI_RXA (1 << 16) 5208 #define SDE_FDI_MASK (3 << 16) 5209 #define SDE_AUXD (1 << 15) 5210 #define SDE_AUXC (1 << 14) 5211 #define SDE_AUXB (1 << 13) 5212 #define SDE_AUX_MASK (7 << 13) 5213 /* 12 reserved */ 5214 #define SDE_CRT_HOTPLUG (1 << 11) 5215 #define SDE_PORTD_HOTPLUG (1 << 10) 5216 #define SDE_PORTC_HOTPLUG (1 << 9) 5217 #define SDE_PORTB_HOTPLUG (1 << 8) 5218 #define SDE_SDVOB_HOTPLUG (1 << 6) 5219 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 5220 SDE_SDVOB_HOTPLUG | \ 5221 SDE_PORTB_HOTPLUG | \ 5222 SDE_PORTC_HOTPLUG | \ 5223 SDE_PORTD_HOTPLUG) 5224 #define SDE_TRANSB_CRC_DONE (1 << 5) 5225 #define SDE_TRANSB_CRC_ERR (1 << 4) 5226 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 5227 #define SDE_TRANSA_CRC_DONE (1 << 2) 5228 #define SDE_TRANSA_CRC_ERR (1 << 1) 5229 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 5230 #define SDE_TRANS_MASK (0x3f) 5231 5232 /* south display engine interrupt: CPT/PPT */ 5233 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 5234 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 5235 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 5236 #define SDE_AUDIO_POWER_SHIFT_CPT 29 5237 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 5238 #define SDE_AUXD_CPT (1 << 27) 5239 #define SDE_AUXC_CPT (1 << 26) 5240 #define SDE_AUXB_CPT (1 << 25) 5241 #define SDE_AUX_MASK_CPT (7 << 25) 5242 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 5243 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 5244 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 5245 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 5246 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 5247 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 5248 SDE_SDVOB_HOTPLUG_CPT | \ 5249 SDE_PORTD_HOTPLUG_CPT | \ 5250 SDE_PORTC_HOTPLUG_CPT | \ 5251 SDE_PORTB_HOTPLUG_CPT) 5252 #define SDE_GMBUS_CPT (1 << 17) 5253 #define SDE_ERROR_CPT (1 << 16) 5254 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 5255 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 5256 #define SDE_FDI_RXC_CPT (1 << 8) 5257 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 5258 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 5259 #define SDE_FDI_RXB_CPT (1 << 4) 5260 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 5261 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 5262 #define SDE_FDI_RXA_CPT (1 << 0) 5263 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 5264 SDE_AUDIO_CP_REQ_B_CPT | \ 5265 SDE_AUDIO_CP_REQ_A_CPT) 5266 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 5267 SDE_AUDIO_CP_CHG_B_CPT | \ 5268 SDE_AUDIO_CP_CHG_A_CPT) 5269 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 5270 SDE_FDI_RXB_CPT | \ 5271 SDE_FDI_RXA_CPT) 5272 5273 #define SDEISR 0xc4000 5274 #define SDEIMR 0xc4004 5275 #define SDEIIR 0xc4008 5276 #define SDEIER 0xc400c 5277 5278 #define SERR_INT 0xc4040 5279 #define SERR_INT_POISON (1<<31) 5280 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 5281 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 5282 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 5283 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 5284 5285 /* digital port hotplug */ 5286 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 5287 #define PORTD_HOTPLUG_ENABLE (1 << 20) 5288 #define PORTD_PULSE_DURATION_2ms (0) 5289 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 5290 #define PORTD_PULSE_DURATION_6ms (2 << 18) 5291 #define PORTD_PULSE_DURATION_100ms (3 << 18) 5292 #define PORTD_PULSE_DURATION_MASK (3 << 18) 5293 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) 5294 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 5295 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 5296 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 5297 #define PORTC_HOTPLUG_ENABLE (1 << 12) 5298 #define PORTC_PULSE_DURATION_2ms (0) 5299 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 5300 #define PORTC_PULSE_DURATION_6ms (2 << 10) 5301 #define PORTC_PULSE_DURATION_100ms (3 << 10) 5302 #define PORTC_PULSE_DURATION_MASK (3 << 10) 5303 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) 5304 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 5305 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 5306 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 5307 #define PORTB_HOTPLUG_ENABLE (1 << 4) 5308 #define PORTB_PULSE_DURATION_2ms (0) 5309 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 5310 #define PORTB_PULSE_DURATION_6ms (2 << 2) 5311 #define PORTB_PULSE_DURATION_100ms (3 << 2) 5312 #define PORTB_PULSE_DURATION_MASK (3 << 2) 5313 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) 5314 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 5315 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 5316 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 5317 5318 #define PCH_GPIOA 0xc5010 5319 #define PCH_GPIOB 0xc5014 5320 #define PCH_GPIOC 0xc5018 5321 #define PCH_GPIOD 0xc501c 5322 #define PCH_GPIOE 0xc5020 5323 #define PCH_GPIOF 0xc5024 5324 5325 #define PCH_GMBUS0 0xc5100 5326 #define PCH_GMBUS1 0xc5104 5327 #define PCH_GMBUS2 0xc5108 5328 #define PCH_GMBUS3 0xc510c 5329 #define PCH_GMBUS4 0xc5110 5330 #define PCH_GMBUS5 0xc5120 5331 5332 #define _PCH_DPLL_A 0xc6014 5333 #define _PCH_DPLL_B 0xc6018 5334 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 5335 5336 #define _PCH_FPA0 0xc6040 5337 #define FP_CB_TUNE (0x3<<22) 5338 #define _PCH_FPA1 0xc6044 5339 #define _PCH_FPB0 0xc6048 5340 #define _PCH_FPB1 0xc604c 5341 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 5342 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 5343 5344 #define PCH_DPLL_TEST 0xc606c 5345 5346 #define PCH_DREF_CONTROL 0xC6200 5347 #define DREF_CONTROL_MASK 0x7fc3 5348 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 5349 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 5350 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 5351 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 5352 #define DREF_SSC_SOURCE_DISABLE (0<<11) 5353 #define DREF_SSC_SOURCE_ENABLE (2<<11) 5354 #define DREF_SSC_SOURCE_MASK (3<<11) 5355 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 5356 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 5357 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 5358 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 5359 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 5360 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 5361 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 5362 #define DREF_SSC4_DOWNSPREAD (0<<6) 5363 #define DREF_SSC4_CENTERSPREAD (1<<6) 5364 #define DREF_SSC1_DISABLE (0<<1) 5365 #define DREF_SSC1_ENABLE (1<<1) 5366 #define DREF_SSC4_DISABLE (0) 5367 #define DREF_SSC4_ENABLE (1) 5368 5369 #define PCH_RAWCLK_FREQ 0xc6204 5370 #define FDL_TP1_TIMER_SHIFT 12 5371 #define FDL_TP1_TIMER_MASK (3<<12) 5372 #define FDL_TP2_TIMER_SHIFT 10 5373 #define FDL_TP2_TIMER_MASK (3<<10) 5374 #define RAWCLK_FREQ_MASK 0x3ff 5375 5376 #define PCH_DPLL_TMR_CFG 0xc6208 5377 5378 #define PCH_SSC4_PARMS 0xc6210 5379 #define PCH_SSC4_AUX_PARMS 0xc6214 5380 5381 #define PCH_DPLL_SEL 0xc7000 5382 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) 5383 #define TRANS_DPLLA_SEL(pipe) 0 5384 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) 5385 5386 /* transcoder */ 5387 5388 #define _PCH_TRANS_HTOTAL_A 0xe0000 5389 #define TRANS_HTOTAL_SHIFT 16 5390 #define TRANS_HACTIVE_SHIFT 0 5391 #define _PCH_TRANS_HBLANK_A 0xe0004 5392 #define TRANS_HBLANK_END_SHIFT 16 5393 #define TRANS_HBLANK_START_SHIFT 0 5394 #define _PCH_TRANS_HSYNC_A 0xe0008 5395 #define TRANS_HSYNC_END_SHIFT 16 5396 #define TRANS_HSYNC_START_SHIFT 0 5397 #define _PCH_TRANS_VTOTAL_A 0xe000c 5398 #define TRANS_VTOTAL_SHIFT 16 5399 #define TRANS_VACTIVE_SHIFT 0 5400 #define _PCH_TRANS_VBLANK_A 0xe0010 5401 #define TRANS_VBLANK_END_SHIFT 16 5402 #define TRANS_VBLANK_START_SHIFT 0 5403 #define _PCH_TRANS_VSYNC_A 0xe0014 5404 #define TRANS_VSYNC_END_SHIFT 16 5405 #define TRANS_VSYNC_START_SHIFT 0 5406 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 5407 5408 #define _PCH_TRANSA_DATA_M1 0xe0030 5409 #define _PCH_TRANSA_DATA_N1 0xe0034 5410 #define _PCH_TRANSA_DATA_M2 0xe0038 5411 #define _PCH_TRANSA_DATA_N2 0xe003c 5412 #define _PCH_TRANSA_LINK_M1 0xe0040 5413 #define _PCH_TRANSA_LINK_N1 0xe0044 5414 #define _PCH_TRANSA_LINK_M2 0xe0048 5415 #define _PCH_TRANSA_LINK_N2 0xe004c 5416 5417 /* Per-transcoder DIP controls (PCH) */ 5418 #define _VIDEO_DIP_CTL_A 0xe0200 5419 #define _VIDEO_DIP_DATA_A 0xe0208 5420 #define _VIDEO_DIP_GCP_A 0xe0210 5421 5422 #define _VIDEO_DIP_CTL_B 0xe1200 5423 #define _VIDEO_DIP_DATA_B 0xe1208 5424 #define _VIDEO_DIP_GCP_B 0xe1210 5425 5426 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 5427 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 5428 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 5429 5430 /* Per-transcoder DIP controls (VLV) */ 5431 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 5432 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 5433 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 5434 5435 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 5436 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 5437 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 5438 5439 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 5440 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 5441 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 5442 5443 #define VLV_TVIDEO_DIP_CTL(pipe) \ 5444 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ 5445 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) 5446 #define VLV_TVIDEO_DIP_DATA(pipe) \ 5447 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ 5448 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) 5449 #define VLV_TVIDEO_DIP_GCP(pipe) \ 5450 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 5451 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 5452 5453 /* Haswell DIP controls */ 5454 #define HSW_VIDEO_DIP_CTL_A 0x60200 5455 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 5456 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 5457 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 5458 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 5459 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 5460 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 5461 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 5462 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 5463 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 5464 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 5465 #define HSW_VIDEO_DIP_GCP_A 0x60210 5466 5467 #define HSW_VIDEO_DIP_CTL_B 0x61200 5468 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 5469 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 5470 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 5471 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 5472 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 5473 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 5474 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 5475 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 5476 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 5477 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 5478 #define HSW_VIDEO_DIP_GCP_B 0x61210 5479 5480 #define HSW_TVIDEO_DIP_CTL(trans) \ 5481 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) 5482 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ 5483 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) 5484 #define HSW_TVIDEO_DIP_VS_DATA(trans) \ 5485 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) 5486 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ 5487 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) 5488 #define HSW_TVIDEO_DIP_GCP(trans) \ 5489 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) 5490 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ 5491 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) 5492 5493 #define HSW_STEREO_3D_CTL_A 0x70020 5494 #define S3D_ENABLE (1<<31) 5495 #define HSW_STEREO_3D_CTL_B 0x71020 5496 5497 #define HSW_STEREO_3D_CTL(trans) \ 5498 _PIPE2(trans, HSW_STEREO_3D_CTL_A) 5499 5500 #define _PCH_TRANS_HTOTAL_B 0xe1000 5501 #define _PCH_TRANS_HBLANK_B 0xe1004 5502 #define _PCH_TRANS_HSYNC_B 0xe1008 5503 #define _PCH_TRANS_VTOTAL_B 0xe100c 5504 #define _PCH_TRANS_VBLANK_B 0xe1010 5505 #define _PCH_TRANS_VSYNC_B 0xe1014 5506 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 5507 5508 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 5509 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 5510 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 5511 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 5512 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 5513 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 5514 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ 5515 _PCH_TRANS_VSYNCSHIFT_B) 5516 5517 #define _PCH_TRANSB_DATA_M1 0xe1030 5518 #define _PCH_TRANSB_DATA_N1 0xe1034 5519 #define _PCH_TRANSB_DATA_M2 0xe1038 5520 #define _PCH_TRANSB_DATA_N2 0xe103c 5521 #define _PCH_TRANSB_LINK_M1 0xe1040 5522 #define _PCH_TRANSB_LINK_N1 0xe1044 5523 #define _PCH_TRANSB_LINK_M2 0xe1048 5524 #define _PCH_TRANSB_LINK_N2 0xe104c 5525 5526 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 5527 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 5528 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 5529 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 5530 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 5531 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 5532 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 5533 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 5534 5535 #define _PCH_TRANSACONF 0xf0008 5536 #define _PCH_TRANSBCONF 0xf1008 5537 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 5538 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ 5539 #define TRANS_DISABLE (0<<31) 5540 #define TRANS_ENABLE (1<<31) 5541 #define TRANS_STATE_MASK (1<<30) 5542 #define TRANS_STATE_DISABLE (0<<30) 5543 #define TRANS_STATE_ENABLE (1<<30) 5544 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 5545 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 5546 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 5547 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 5548 #define TRANS_INTERLACE_MASK (7<<21) 5549 #define TRANS_PROGRESSIVE (0<<21) 5550 #define TRANS_INTERLACED (3<<21) 5551 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 5552 #define TRANS_8BPC (0<<5) 5553 #define TRANS_10BPC (1<<5) 5554 #define TRANS_6BPC (2<<5) 5555 #define TRANS_12BPC (3<<5) 5556 5557 #define _TRANSA_CHICKEN1 0xf0060 5558 #define _TRANSB_CHICKEN1 0xf1060 5559 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 5560 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 5561 #define _TRANSA_CHICKEN2 0xf0064 5562 #define _TRANSB_CHICKEN2 0xf1064 5563 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 5564 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 5565 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 5566 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 5567 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 5568 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 5569 5570 #define SOUTH_CHICKEN1 0xc2000 5571 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 5572 #define FDIA_PHASE_SYNC_SHIFT_EN 18 5573 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 5574 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 5575 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 5576 #define SOUTH_CHICKEN2 0xc2004 5577 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 5578 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 5579 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 5580 5581 #define _FDI_RXA_CHICKEN 0xc200c 5582 #define _FDI_RXB_CHICKEN 0xc2010 5583 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 5584 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 5585 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 5586 5587 #define SOUTH_DSPCLK_GATE_D 0xc2020 5588 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 5589 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 5590 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 5591 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 5592 5593 /* CPU: FDI_TX */ 5594 #define _FDI_TXA_CTL 0x60100 5595 #define _FDI_TXB_CTL 0x61100 5596 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 5597 #define FDI_TX_DISABLE (0<<31) 5598 #define FDI_TX_ENABLE (1<<31) 5599 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 5600 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 5601 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 5602 #define FDI_LINK_TRAIN_NONE (3<<28) 5603 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 5604 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 5605 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 5606 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 5607 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 5608 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 5609 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 5610 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 5611 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 5612 SNB has different settings. */ 5613 /* SNB A-stepping */ 5614 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 5615 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 5616 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 5617 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 5618 /* SNB B-stepping */ 5619 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 5620 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 5621 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 5622 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 5623 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 5624 #define FDI_DP_PORT_WIDTH_SHIFT 19 5625 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 5626 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 5627 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 5628 /* Ironlake: hardwired to 1 */ 5629 #define FDI_TX_PLL_ENABLE (1<<14) 5630 5631 /* Ivybridge has different bits for lolz */ 5632 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 5633 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 5634 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 5635 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 5636 5637 /* both Tx and Rx */ 5638 #define FDI_COMPOSITE_SYNC (1<<11) 5639 #define FDI_LINK_TRAIN_AUTO (1<<10) 5640 #define FDI_SCRAMBLING_ENABLE (0<<7) 5641 #define FDI_SCRAMBLING_DISABLE (1<<7) 5642 5643 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 5644 #define _FDI_RXA_CTL 0xf000c 5645 #define _FDI_RXB_CTL 0xf100c 5646 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 5647 #define FDI_RX_ENABLE (1<<31) 5648 /* train, dp width same as FDI_TX */ 5649 #define FDI_FS_ERRC_ENABLE (1<<27) 5650 #define FDI_FE_ERRC_ENABLE (1<<26) 5651 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 5652 #define FDI_8BPC (0<<16) 5653 #define FDI_10BPC (1<<16) 5654 #define FDI_6BPC (2<<16) 5655 #define FDI_12BPC (3<<16) 5656 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 5657 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 5658 #define FDI_RX_PLL_ENABLE (1<<13) 5659 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 5660 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 5661 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 5662 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 5663 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 5664 #define FDI_PCDCLK (1<<4) 5665 /* CPT */ 5666 #define FDI_AUTO_TRAINING (1<<10) 5667 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 5668 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 5669 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 5670 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 5671 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 5672 5673 #define _FDI_RXA_MISC 0xf0010 5674 #define _FDI_RXB_MISC 0xf1010 5675 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 5676 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 5677 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 5678 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 5679 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 5680 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 5681 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 5682 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 5683 5684 #define _FDI_RXA_TUSIZE1 0xf0030 5685 #define _FDI_RXA_TUSIZE2 0xf0038 5686 #define _FDI_RXB_TUSIZE1 0xf1030 5687 #define _FDI_RXB_TUSIZE2 0xf1038 5688 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 5689 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 5690 5691 /* FDI_RX interrupt register format */ 5692 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 5693 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 5694 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 5695 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 5696 #define FDI_RX_FS_CODE_ERR (1<<6) 5697 #define FDI_RX_FE_CODE_ERR (1<<5) 5698 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 5699 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 5700 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 5701 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 5702 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 5703 5704 #define _FDI_RXA_IIR 0xf0014 5705 #define _FDI_RXA_IMR 0xf0018 5706 #define _FDI_RXB_IIR 0xf1014 5707 #define _FDI_RXB_IMR 0xf1018 5708 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 5709 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 5710 5711 #define FDI_PLL_CTL_1 0xfe000 5712 #define FDI_PLL_CTL_2 0xfe004 5713 5714 #define PCH_LVDS 0xe1180 5715 #define LVDS_DETECTED (1 << 1) 5716 5717 /* vlv has 2 sets of panel control regs. */ 5718 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 5719 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 5720 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 5721 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 5722 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 5723 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 5724 5725 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 5726 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 5727 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 5728 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 5729 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 5730 5731 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) 5732 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) 5733 #define VLV_PIPE_PP_ON_DELAYS(pipe) \ 5734 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) 5735 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ 5736 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) 5737 #define VLV_PIPE_PP_DIVISOR(pipe) \ 5738 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) 5739 5740 #define PCH_PP_STATUS 0xc7200 5741 #define PCH_PP_CONTROL 0xc7204 5742 #define PANEL_UNLOCK_REGS (0xabcd << 16) 5743 #define PANEL_UNLOCK_MASK (0xffff << 16) 5744 #define EDP_FORCE_VDD (1 << 3) 5745 #define EDP_BLC_ENABLE (1 << 2) 5746 #define PANEL_POWER_RESET (1 << 1) 5747 #define PANEL_POWER_OFF (0 << 0) 5748 #define PANEL_POWER_ON (1 << 0) 5749 #define PCH_PP_ON_DELAYS 0xc7208 5750 #define PANEL_PORT_SELECT_MASK (3 << 30) 5751 #define PANEL_PORT_SELECT_LVDS (0 << 30) 5752 #define PANEL_PORT_SELECT_DPA (1 << 30) 5753 #define PANEL_PORT_SELECT_DPC (2 << 30) 5754 #define PANEL_PORT_SELECT_DPD (3 << 30) 5755 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 5756 #define PANEL_POWER_UP_DELAY_SHIFT 16 5757 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 5758 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 5759 5760 #define PCH_PP_OFF_DELAYS 0xc720c 5761 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 5762 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 5763 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 5764 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 5765 5766 #define PCH_PP_DIVISOR 0xc7210 5767 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 5768 #define PP_REFERENCE_DIVIDER_SHIFT 8 5769 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 5770 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 5771 5772 #define PCH_DP_B 0xe4100 5773 #define PCH_DPB_AUX_CH_CTL 0xe4110 5774 #define PCH_DPB_AUX_CH_DATA1 0xe4114 5775 #define PCH_DPB_AUX_CH_DATA2 0xe4118 5776 #define PCH_DPB_AUX_CH_DATA3 0xe411c 5777 #define PCH_DPB_AUX_CH_DATA4 0xe4120 5778 #define PCH_DPB_AUX_CH_DATA5 0xe4124 5779 5780 #define PCH_DP_C 0xe4200 5781 #define PCH_DPC_AUX_CH_CTL 0xe4210 5782 #define PCH_DPC_AUX_CH_DATA1 0xe4214 5783 #define PCH_DPC_AUX_CH_DATA2 0xe4218 5784 #define PCH_DPC_AUX_CH_DATA3 0xe421c 5785 #define PCH_DPC_AUX_CH_DATA4 0xe4220 5786 #define PCH_DPC_AUX_CH_DATA5 0xe4224 5787 5788 #define PCH_DP_D 0xe4300 5789 #define PCH_DPD_AUX_CH_CTL 0xe4310 5790 #define PCH_DPD_AUX_CH_DATA1 0xe4314 5791 #define PCH_DPD_AUX_CH_DATA2 0xe4318 5792 #define PCH_DPD_AUX_CH_DATA3 0xe431c 5793 #define PCH_DPD_AUX_CH_DATA4 0xe4320 5794 #define PCH_DPD_AUX_CH_DATA5 0xe4324 5795 5796 /* CPT */ 5797 #define PORT_TRANS_A_SEL_CPT 0 5798 #define PORT_TRANS_B_SEL_CPT (1<<29) 5799 #define PORT_TRANS_C_SEL_CPT (2<<29) 5800 #define PORT_TRANS_SEL_MASK (3<<29) 5801 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 5802 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 5803 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 5804 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 5805 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 5806 5807 #define TRANS_DP_CTL_A 0xe0300 5808 #define TRANS_DP_CTL_B 0xe1300 5809 #define TRANS_DP_CTL_C 0xe2300 5810 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) 5811 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 5812 #define TRANS_DP_PORT_SEL_B (0<<29) 5813 #define TRANS_DP_PORT_SEL_C (1<<29) 5814 #define TRANS_DP_PORT_SEL_D (2<<29) 5815 #define TRANS_DP_PORT_SEL_NONE (3<<29) 5816 #define TRANS_DP_PORT_SEL_MASK (3<<29) 5817 #define TRANS_DP_AUDIO_ONLY (1<<26) 5818 #define TRANS_DP_ENH_FRAMING (1<<18) 5819 #define TRANS_DP_8BPC (0<<9) 5820 #define TRANS_DP_10BPC (1<<9) 5821 #define TRANS_DP_6BPC (2<<9) 5822 #define TRANS_DP_12BPC (3<<9) 5823 #define TRANS_DP_BPC_MASK (3<<9) 5824 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 5825 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 5826 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 5827 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 5828 #define TRANS_DP_SYNC_MASK (3<<3) 5829 5830 /* SNB eDP training params */ 5831 /* SNB A-stepping */ 5832 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 5833 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 5834 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 5835 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 5836 /* SNB B-stepping */ 5837 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 5838 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 5839 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 5840 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 5841 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 5842 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 5843 5844 /* IVB */ 5845 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 5846 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 5847 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 5848 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 5849 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 5850 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 5851 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 5852 5853 /* legacy values */ 5854 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 5855 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 5856 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 5857 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 5858 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 5859 5860 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 5861 5862 #define VLV_PMWGICZ 0x1300a4 5863 5864 #define FORCEWAKE 0xA18C 5865 #define FORCEWAKE_VLV 0x1300b0 5866 #define FORCEWAKE_ACK_VLV 0x1300b4 5867 #define FORCEWAKE_MEDIA_VLV 0x1300b8 5868 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc 5869 #define FORCEWAKE_ACK_HSW 0x130044 5870 #define FORCEWAKE_ACK 0x130090 5871 #define VLV_GTLC_WAKE_CTRL 0x130090 5872 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 5873 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 5874 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 5875 5876 #define VLV_GTLC_PW_STATUS 0x130094 5877 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 5878 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 5879 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 5880 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 5881 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 5882 #define FORCEWAKE_MEDIA_GEN9 0xa270 5883 #define FORCEWAKE_RENDER_GEN9 0xa278 5884 #define FORCEWAKE_BLITTER_GEN9 0xa188 5885 #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88 5886 #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84 5887 #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044 5888 #define FORCEWAKE_KERNEL 0x1 5889 #define FORCEWAKE_USER 0x2 5890 #define FORCEWAKE_MT_ACK 0x130040 5891 #define ECOBUS 0xa180 5892 #define FORCEWAKE_MT_ENABLE (1<<5) 5893 #define VLV_SPAREG2H 0xA194 5894 5895 #define GTFIFODBG 0x120000 5896 #define GT_FIFO_SBDROPERR (1<<6) 5897 #define GT_FIFO_BLOBDROPERR (1<<5) 5898 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 5899 #define GT_FIFO_DROPERR (1<<3) 5900 #define GT_FIFO_OVFERR (1<<2) 5901 #define GT_FIFO_IAWRERR (1<<1) 5902 #define GT_FIFO_IARDERR (1<<0) 5903 5904 #define GTFIFOCTL 0x120008 5905 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 5906 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 5907 5908 #define HSW_IDICR 0x9008 5909 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 5910 #define HSW_EDRAM_PRESENT 0x120010 5911 5912 #define GEN6_UCGCTL1 0x9400 5913 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 5914 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 5915 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 5916 5917 #define GEN6_UCGCTL2 0x9404 5918 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 5919 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 5920 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 5921 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 5922 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 5923 5924 #define GEN6_UCGCTL3 0x9408 5925 5926 #define GEN7_UCGCTL4 0x940c 5927 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 5928 5929 #define GEN6_RCGCTL1 0x9410 5930 #define GEN6_RCGCTL2 0x9414 5931 #define GEN6_RSTCTL 0x9420 5932 5933 #define GEN8_UCGCTL6 0x9430 5934 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 5935 5936 #define GEN6_GFXPAUSE 0xA000 5937 #define GEN6_RPNSWREQ 0xA008 5938 #define GEN6_TURBO_DISABLE (1<<31) 5939 #define GEN6_FREQUENCY(x) ((x)<<25) 5940 #define HSW_FREQUENCY(x) ((x)<<24) 5941 #define GEN6_OFFSET(x) ((x)<<19) 5942 #define GEN6_AGGRESSIVE_TURBO (0<<15) 5943 #define GEN6_RC_VIDEO_FREQ 0xA00C 5944 #define GEN6_RC_CONTROL 0xA090 5945 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 5946 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 5947 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 5948 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 5949 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 5950 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 5951 #define GEN7_RC_CTL_TO_MODE (1<<28) 5952 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 5953 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 5954 #define GEN6_RP_DOWN_TIMEOUT 0xA010 5955 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 5956 #define GEN6_RPSTAT1 0xA01C 5957 #define GEN6_CAGF_SHIFT 8 5958 #define HSW_CAGF_SHIFT 7 5959 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 5960 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 5961 #define GEN6_RP_CONTROL 0xA024 5962 #define GEN6_RP_MEDIA_TURBO (1<<11) 5963 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 5964 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 5965 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 5966 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 5967 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 5968 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 5969 #define GEN6_RP_ENABLE (1<<7) 5970 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 5971 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 5972 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 5973 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 5974 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 5975 #define GEN6_RP_UP_THRESHOLD 0xA02C 5976 #define GEN6_RP_DOWN_THRESHOLD 0xA030 5977 #define GEN6_RP_CUR_UP_EI 0xA050 5978 #define GEN6_CURICONT_MASK 0xffffff 5979 #define GEN6_RP_CUR_UP 0xA054 5980 #define GEN6_CURBSYTAVG_MASK 0xffffff 5981 #define GEN6_RP_PREV_UP 0xA058 5982 #define GEN6_RP_CUR_DOWN_EI 0xA05C 5983 #define GEN6_CURIAVG_MASK 0xffffff 5984 #define GEN6_RP_CUR_DOWN 0xA060 5985 #define GEN6_RP_PREV_DOWN 0xA064 5986 #define GEN6_RP_UP_EI 0xA068 5987 #define GEN6_RP_DOWN_EI 0xA06C 5988 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 5989 #define GEN6_RPDEUHWTC 0xA080 5990 #define GEN6_RPDEUC 0xA084 5991 #define GEN6_RPDEUCSW 0xA088 5992 #define GEN6_RC_STATE 0xA094 5993 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 5994 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 5995 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 5996 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 5997 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 5998 #define GEN6_RC_SLEEP 0xA0B0 5999 #define GEN6_RCUBMABDTMR 0xA0B0 6000 #define GEN6_RC1e_THRESHOLD 0xA0B4 6001 #define GEN6_RC6_THRESHOLD 0xA0B8 6002 #define GEN6_RC6p_THRESHOLD 0xA0BC 6003 #define VLV_RCEDATA 0xA0BC 6004 #define GEN6_RC6pp_THRESHOLD 0xA0C0 6005 #define GEN6_PMINTRMSK 0xA168 6006 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 6007 #define VLV_PWRDWNUPCTL 0xA294 6008 6009 #define GEN6_PMISR 0x44020 6010 #define GEN6_PMIMR 0x44024 /* rps_lock */ 6011 #define GEN6_PMIIR 0x44028 6012 #define GEN6_PMIER 0x4402C 6013 #define GEN6_PM_MBOX_EVENT (1<<25) 6014 #define GEN6_PM_THERMAL_EVENT (1<<24) 6015 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 6016 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 6017 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 6018 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 6019 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 6020 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 6021 GEN6_PM_RP_DOWN_THRESHOLD | \ 6022 GEN6_PM_RP_DOWN_TIMEOUT) 6023 6024 #define GEN7_GT_SCRATCH_BASE 0x4F100 6025 #define GEN7_GT_SCRATCH_REG_NUM 8 6026 6027 #define VLV_GTLC_SURVIVABILITY_REG 0x130098 6028 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 6029 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 6030 6031 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 6032 #define VLV_COUNTER_CONTROL 0x138104 6033 #define VLV_COUNT_RANGE_HIGH (1<<15) 6034 #define VLV_MEDIA_RC0_COUNT_EN (1<<5) 6035 #define VLV_RENDER_RC0_COUNT_EN (1<<4) 6036 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 6037 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 6038 #define GEN6_GT_GFX_RC6 0x138108 6039 #define VLV_GT_RENDER_RC6 0x138108 6040 #define VLV_GT_MEDIA_RC6 0x13810C 6041 6042 #define GEN6_GT_GFX_RC6p 0x13810C 6043 #define GEN6_GT_GFX_RC6pp 0x138110 6044 #define VLV_RENDER_C0_COUNT_REG 0x138118 6045 #define VLV_MEDIA_C0_COUNT_REG 0x13811C 6046 6047 #define GEN6_PCODE_MAILBOX 0x138124 6048 #define GEN6_PCODE_READY (1<<31) 6049 #define GEN6_READ_OC_PARAMS 0xc 6050 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6051 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6052 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6053 #define GEN6_PCODE_READ_RC6VIDS 0x5 6054 #define GEN6_PCODE_READ_D_COMP 0x10 6055 #define GEN6_PCODE_WRITE_D_COMP 0x11 6056 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6057 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6058 #define DISPLAY_IPS_CONTROL 0x19 6059 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6060 #define GEN6_PCODE_DATA 0x138128 6061 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6062 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6063 #define GEN6_PCODE_DATA1 0x13812C 6064 6065 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6066 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 6067 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 6068 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 6069 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 6070 6071 #define GEN6_GT_CORE_STATUS 0x138060 6072 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 6073 #define GEN6_RCn_MASK 7 6074 #define GEN6_RC0 0 6075 #define GEN6_RC3 2 6076 #define GEN6_RC6 3 6077 #define GEN6_RC7 4 6078 6079 #define GEN7_MISCCPCTL (0x9424) 6080 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 6081 6082 /* IVYBRIDGE DPF */ 6083 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ 6084 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ 6085 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 6086 #define GEN7_PARITY_ERROR_VALID (1<<13) 6087 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 6088 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 6089 #define GEN7_PARITY_ERROR_ROW(reg) \ 6090 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6091 #define GEN7_PARITY_ERROR_BANK(reg) \ 6092 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6093 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6094 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6095 #define GEN7_L3CDERRST1_ENABLE (1<<7) 6096 6097 #define GEN7_L3LOG_BASE 0xB070 6098 #define HSW_L3LOG_BASE_SLICE1 0xB270 6099 #define GEN7_L3LOG_SIZE 0x80 6100 6101 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ 6102 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 6103 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 6104 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 6105 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 6106 6107 #define GEN9_HALF_SLICE_CHICKEN5 0xe188 6108 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) 6109 6110 #define GEN8_ROW_CHICKEN 0xe4f0 6111 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 6112 #define STALL_DOP_GATING_DISABLE (1<<5) 6113 6114 #define GEN7_ROW_CHICKEN2 0xe4f4 6115 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 6116 #define DOP_CLOCK_GATING_DISABLE (1<<0) 6117 6118 #define HSW_ROW_CHICKEN3 0xe49c 6119 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 6120 6121 #define HALF_SLICE_CHICKEN3 0xe184 6122 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 6123 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 6124 6125 /* Audio */ 6126 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) 6127 #define INTEL_AUDIO_DEVCL 0x808629FB 6128 #define INTEL_AUDIO_DEVBLC 0x80862801 6129 #define INTEL_AUDIO_DEVCTG 0x80862802 6130 6131 #define G4X_AUD_CNTL_ST 0x620B4 6132 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 6133 #define G4X_ELDV_DEVCTG (1 << 14) 6134 #define G4X_ELD_ADDR_MASK (0xf << 5) 6135 #define G4X_ELD_ACK (1 << 4) 6136 #define G4X_HDMIW_HDMIEDID 0x6210C 6137 6138 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 6139 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 6140 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 6141 _IBX_HDMIW_HDMIEDID_A, \ 6142 _IBX_HDMIW_HDMIEDID_B) 6143 #define _IBX_AUD_CNTL_ST_A 0xE20B4 6144 #define _IBX_AUD_CNTL_ST_B 0xE21B4 6145 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 6146 _IBX_AUD_CNTL_ST_A, \ 6147 _IBX_AUD_CNTL_ST_B) 6148 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 6149 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 6150 #define IBX_ELD_ACK (1 << 4) 6151 #define IBX_AUD_CNTL_ST2 0xE20C0 6152 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 6153 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 6154 6155 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 6156 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 6157 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 6158 _CPT_HDMIW_HDMIEDID_A, \ 6159 _CPT_HDMIW_HDMIEDID_B) 6160 #define _CPT_AUD_CNTL_ST_A 0xE50B4 6161 #define _CPT_AUD_CNTL_ST_B 0xE51B4 6162 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 6163 _CPT_AUD_CNTL_ST_A, \ 6164 _CPT_AUD_CNTL_ST_B) 6165 #define CPT_AUD_CNTRL_ST2 0xE50C0 6166 6167 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 6168 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 6169 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 6170 _VLV_HDMIW_HDMIEDID_A, \ 6171 _VLV_HDMIW_HDMIEDID_B) 6172 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 6173 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 6174 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 6175 _VLV_AUD_CNTL_ST_A, \ 6176 _VLV_AUD_CNTL_ST_B) 6177 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) 6178 6179 /* These are the 4 32-bit write offset registers for each stream 6180 * output buffer. It determines the offset from the 6181 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6182 */ 6183 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 6184 6185 #define _IBX_AUD_CONFIG_A 0xe2000 6186 #define _IBX_AUD_CONFIG_B 0xe2100 6187 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ 6188 _IBX_AUD_CONFIG_A, \ 6189 _IBX_AUD_CONFIG_B) 6190 #define _CPT_AUD_CONFIG_A 0xe5000 6191 #define _CPT_AUD_CONFIG_B 0xe5100 6192 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ 6193 _CPT_AUD_CONFIG_A, \ 6194 _CPT_AUD_CONFIG_B) 6195 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 6196 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 6197 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ 6198 _VLV_AUD_CONFIG_A, \ 6199 _VLV_AUD_CONFIG_B) 6200 6201 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 6202 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 6203 #define AUD_CONFIG_UPPER_N_SHIFT 20 6204 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 6205 #define AUD_CONFIG_LOWER_N_SHIFT 4 6206 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 6207 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 6208 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 6209 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 6210 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 6211 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 6212 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 6213 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 6214 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 6215 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 6216 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 6217 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 6218 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 6219 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 6220 6221 /* HSW Audio */ 6222 #define _HSW_AUD_CONFIG_A 0x65000 6223 #define _HSW_AUD_CONFIG_B 0x65100 6224 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ 6225 _HSW_AUD_CONFIG_A, \ 6226 _HSW_AUD_CONFIG_B) 6227 6228 #define _HSW_AUD_MISC_CTRL_A 0x65010 6229 #define _HSW_AUD_MISC_CTRL_B 0x65110 6230 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ 6231 _HSW_AUD_MISC_CTRL_A, \ 6232 _HSW_AUD_MISC_CTRL_B) 6233 6234 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 6235 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 6236 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ 6237 _HSW_AUD_DIP_ELD_CTRL_ST_A, \ 6238 _HSW_AUD_DIP_ELD_CTRL_ST_B) 6239 6240 /* Audio Digital Converter */ 6241 #define _HSW_AUD_DIG_CNVT_1 0x65080 6242 #define _HSW_AUD_DIG_CNVT_2 0x65180 6243 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ 6244 _HSW_AUD_DIG_CNVT_1, \ 6245 _HSW_AUD_DIG_CNVT_2) 6246 #define DIP_PORT_SEL_MASK 0x3 6247 6248 #define _HSW_AUD_EDID_DATA_A 0x65050 6249 #define _HSW_AUD_EDID_DATA_B 0x65150 6250 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ 6251 _HSW_AUD_EDID_DATA_A, \ 6252 _HSW_AUD_EDID_DATA_B) 6253 6254 #define HSW_AUD_PIPE_CONV_CFG 0x6507c 6255 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 6256 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 6257 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 6258 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 6259 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 6260 6261 /* HSW Power Wells */ 6262 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ 6263 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ 6264 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ 6265 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ 6266 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 6267 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 6268 #define HSW_PWR_WELL_CTL5 0x45410 6269 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 6270 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 6271 #define HSW_PWR_WELL_FORCE_ON (1<<19) 6272 #define HSW_PWR_WELL_CTL6 0x45414 6273 6274 /* Per-pipe DDI Function Control */ 6275 #define TRANS_DDI_FUNC_CTL_A 0x60400 6276 #define TRANS_DDI_FUNC_CTL_B 0x61400 6277 #define TRANS_DDI_FUNC_CTL_C 0x62400 6278 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 6279 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) 6280 6281 #define TRANS_DDI_FUNC_ENABLE (1<<31) 6282 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 6283 #define TRANS_DDI_PORT_MASK (7<<28) 6284 #define TRANS_DDI_PORT_SHIFT 28 6285 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 6286 #define TRANS_DDI_PORT_NONE (0<<28) 6287 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 6288 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 6289 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 6290 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 6291 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 6292 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 6293 #define TRANS_DDI_BPC_MASK (7<<20) 6294 #define TRANS_DDI_BPC_8 (0<<20) 6295 #define TRANS_DDI_BPC_10 (1<<20) 6296 #define TRANS_DDI_BPC_6 (2<<20) 6297 #define TRANS_DDI_BPC_12 (3<<20) 6298 #define TRANS_DDI_PVSYNC (1<<17) 6299 #define TRANS_DDI_PHSYNC (1<<16) 6300 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 6301 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 6302 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 6303 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 6304 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 6305 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 6306 #define TRANS_DDI_BFI_ENABLE (1<<4) 6307 6308 /* DisplayPort Transport Control */ 6309 #define DP_TP_CTL_A 0x64040 6310 #define DP_TP_CTL_B 0x64140 6311 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) 6312 #define DP_TP_CTL_ENABLE (1<<31) 6313 #define DP_TP_CTL_MODE_SST (0<<27) 6314 #define DP_TP_CTL_MODE_MST (1<<27) 6315 #define DP_TP_CTL_FORCE_ACT (1<<25) 6316 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 6317 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 6318 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 6319 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 6320 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 6321 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 6322 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 6323 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 6324 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 6325 6326 /* DisplayPort Transport Status */ 6327 #define DP_TP_STATUS_A 0x64044 6328 #define DP_TP_STATUS_B 0x64144 6329 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 6330 #define DP_TP_STATUS_IDLE_DONE (1<<25) 6331 #define DP_TP_STATUS_ACT_SENT (1<<24) 6332 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 6333 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 6334 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 6335 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 6336 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 6337 6338 /* DDI Buffer Control */ 6339 #define DDI_BUF_CTL_A 0x64000 6340 #define DDI_BUF_CTL_B 0x64100 6341 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 6342 #define DDI_BUF_CTL_ENABLE (1<<31) 6343 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 6344 #define DDI_BUF_EMP_MASK (0xf<<24) 6345 #define DDI_BUF_PORT_REVERSAL (1<<16) 6346 #define DDI_BUF_IS_IDLE (1<<7) 6347 #define DDI_A_4_LANES (1<<4) 6348 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 6349 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 6350 6351 /* DDI Buffer Translations */ 6352 #define DDI_BUF_TRANS_A 0x64E00 6353 #define DDI_BUF_TRANS_B 0x64E60 6354 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) 6355 6356 /* Sideband Interface (SBI) is programmed indirectly, via 6357 * SBI_ADDR, which contains the register offset; and SBI_DATA, 6358 * which contains the payload */ 6359 #define SBI_ADDR 0xC6000 6360 #define SBI_DATA 0xC6004 6361 #define SBI_CTL_STAT 0xC6008 6362 #define SBI_CTL_DEST_ICLK (0x0<<16) 6363 #define SBI_CTL_DEST_MPHY (0x1<<16) 6364 #define SBI_CTL_OP_IORD (0x2<<8) 6365 #define SBI_CTL_OP_IOWR (0x3<<8) 6366 #define SBI_CTL_OP_CRRD (0x6<<8) 6367 #define SBI_CTL_OP_CRWR (0x7<<8) 6368 #define SBI_RESPONSE_FAIL (0x1<<1) 6369 #define SBI_RESPONSE_SUCCESS (0x0<<1) 6370 #define SBI_BUSY (0x1<<0) 6371 #define SBI_READY (0x0<<0) 6372 6373 /* SBI offsets */ 6374 #define SBI_SSCDIVINTPHASE6 0x0600 6375 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 6376 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 6377 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 6378 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 6379 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 6380 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 6381 #define SBI_SSCCTL 0x020c 6382 #define SBI_SSCCTL6 0x060C 6383 #define SBI_SSCCTL_PATHALT (1<<3) 6384 #define SBI_SSCCTL_DISABLE (1<<0) 6385 #define SBI_SSCAUXDIV6 0x0610 6386 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 6387 #define SBI_DBUFF0 0x2a00 6388 #define SBI_GEN0 0x1f00 6389 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 6390 6391 /* LPT PIXCLK_GATE */ 6392 #define PIXCLK_GATE 0xC6020 6393 #define PIXCLK_GATE_UNGATE (1<<0) 6394 #define PIXCLK_GATE_GATE (0<<0) 6395 6396 /* SPLL */ 6397 #define SPLL_CTL 0x46020 6398 #define SPLL_PLL_ENABLE (1<<31) 6399 #define SPLL_PLL_SSC (1<<28) 6400 #define SPLL_PLL_NON_SSC (2<<28) 6401 #define SPLL_PLL_LCPLL (3<<28) 6402 #define SPLL_PLL_REF_MASK (3<<28) 6403 #define SPLL_PLL_FREQ_810MHz (0<<26) 6404 #define SPLL_PLL_FREQ_1350MHz (1<<26) 6405 #define SPLL_PLL_FREQ_2700MHz (2<<26) 6406 #define SPLL_PLL_FREQ_MASK (3<<26) 6407 6408 /* WRPLL */ 6409 #define WRPLL_CTL1 0x46040 6410 #define WRPLL_CTL2 0x46060 6411 #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) 6412 #define WRPLL_PLL_ENABLE (1<<31) 6413 #define WRPLL_PLL_SSC (1<<28) 6414 #define WRPLL_PLL_NON_SSC (2<<28) 6415 #define WRPLL_PLL_LCPLL (3<<28) 6416 #define WRPLL_PLL_REF_MASK (3<<28) 6417 /* WRPLL divider programming */ 6418 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 6419 #define WRPLL_DIVIDER_REF_MASK (0xff) 6420 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 6421 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 6422 #define WRPLL_DIVIDER_POST_SHIFT 8 6423 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 6424 #define WRPLL_DIVIDER_FB_SHIFT 16 6425 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 6426 6427 /* Port clock selection */ 6428 #define PORT_CLK_SEL_A 0x46100 6429 #define PORT_CLK_SEL_B 0x46104 6430 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) 6431 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 6432 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 6433 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 6434 #define PORT_CLK_SEL_SPLL (3<<29) 6435 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 6436 #define PORT_CLK_SEL_WRPLL1 (4<<29) 6437 #define PORT_CLK_SEL_WRPLL2 (5<<29) 6438 #define PORT_CLK_SEL_NONE (7<<29) 6439 #define PORT_CLK_SEL_MASK (7<<29) 6440 6441 /* Transcoder clock selection */ 6442 #define TRANS_CLK_SEL_A 0x46140 6443 #define TRANS_CLK_SEL_B 0x46144 6444 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) 6445 /* For each transcoder, we need to select the corresponding port clock */ 6446 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 6447 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 6448 6449 #define TRANSA_MSA_MISC 0x60410 6450 #define TRANSB_MSA_MISC 0x61410 6451 #define TRANSC_MSA_MISC 0x62410 6452 #define TRANS_EDP_MSA_MISC 0x6f410 6453 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) 6454 6455 #define TRANS_MSA_SYNC_CLK (1<<0) 6456 #define TRANS_MSA_6_BPC (0<<5) 6457 #define TRANS_MSA_8_BPC (1<<5) 6458 #define TRANS_MSA_10_BPC (2<<5) 6459 #define TRANS_MSA_12_BPC (3<<5) 6460 #define TRANS_MSA_16_BPC (4<<5) 6461 6462 /* LCPLL Control */ 6463 #define LCPLL_CTL 0x130040 6464 #define LCPLL_PLL_DISABLE (1<<31) 6465 #define LCPLL_PLL_LOCK (1<<30) 6466 #define LCPLL_CLK_FREQ_MASK (3<<26) 6467 #define LCPLL_CLK_FREQ_450 (0<<26) 6468 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 6469 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 6470 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 6471 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 6472 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 6473 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 6474 #define LCPLL_CD_SOURCE_FCLK (1<<21) 6475 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 6476 6477 /* 6478 * SKL Clocks 6479 */ 6480 6481 /* CDCLK_CTL */ 6482 #define CDCLK_CTL 0x46000 6483 #define CDCLK_FREQ_SEL_MASK (3<<26) 6484 #define CDCLK_FREQ_450_432 (0<<26) 6485 #define CDCLK_FREQ_540 (1<<26) 6486 #define CDCLK_FREQ_337_308 (2<<26) 6487 #define CDCLK_FREQ_675_617 (3<<26) 6488 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 6489 6490 /* LCPLL_CTL */ 6491 #define LCPLL1_CTL 0x46010 6492 #define LCPLL2_CTL 0x46014 6493 #define LCPLL_PLL_ENABLE (1<<31) 6494 6495 /* DPLL control1 */ 6496 #define DPLL_CTRL1 0x6C058 6497 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) 6498 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) 6499 #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) 6500 #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) 6501 #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) 6502 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) 6503 #define DPLL_CRTL1_LINK_RATE_2700 0 6504 #define DPLL_CRTL1_LINK_RATE_1350 1 6505 #define DPLL_CRTL1_LINK_RATE_810 2 6506 #define DPLL_CRTL1_LINK_RATE_1620 3 6507 #define DPLL_CRTL1_LINK_RATE_1080 4 6508 #define DPLL_CRTL1_LINK_RATE_2160 5 6509 6510 /* DPLL control2 */ 6511 #define DPLL_CTRL2 0x6C05C 6512 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) 6513 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) 6514 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) 6515 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) 6516 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) 6517 6518 /* DPLL Status */ 6519 #define DPLL_STATUS 0x6C060 6520 #define DPLL_LOCK(id) (1<<((id)*8)) 6521 6522 /* DPLL cfg */ 6523 #define DPLL1_CFGCR1 0x6C040 6524 #define DPLL2_CFGCR1 0x6C048 6525 #define DPLL3_CFGCR1 0x6C050 6526 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) 6527 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) 6528 #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) 6529 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 6530 6531 #define DPLL1_CFGCR2 0x6C044 6532 #define DPLL2_CFGCR2 0x6C04C 6533 #define DPLL3_CFGCR2 0x6C054 6534 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) 6535 #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) 6536 #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) 6537 #define DPLL_CFGCR2_KDIV_MASK (3<<5) 6538 #define DPLL_CFGCR2_KDIV(x) (x<<5) 6539 #define DPLL_CFGCR2_KDIV_5 (0<<5) 6540 #define DPLL_CFGCR2_KDIV_2 (1<<5) 6541 #define DPLL_CFGCR2_KDIV_3 (2<<5) 6542 #define DPLL_CFGCR2_KDIV_1 (3<<5) 6543 #define DPLL_CFGCR2_PDIV_MASK (7<<2) 6544 #define DPLL_CFGCR2_PDIV(x) (x<<2) 6545 #define DPLL_CFGCR2_PDIV_1 (0<<2) 6546 #define DPLL_CFGCR2_PDIV_2 (1<<2) 6547 #define DPLL_CFGCR2_PDIV_3 (2<<2) 6548 #define DPLL_CFGCR2_PDIV_7 (4<<2) 6549 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 6550 6551 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) 6552 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) 6553 6554 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 6555 * since on HSW we can't write to it using I915_WRITE. */ 6556 #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 6557 #define D_COMP_BDW 0x138144 6558 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 6559 #define D_COMP_COMP_FORCE (1<<8) 6560 #define D_COMP_COMP_DISABLE (1<<0) 6561 6562 /* Pipe WM_LINETIME - watermark line time */ 6563 #define PIPE_WM_LINETIME_A 0x45270 6564 #define PIPE_WM_LINETIME_B 0x45274 6565 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ 6566 PIPE_WM_LINETIME_B) 6567 #define PIPE_WM_LINETIME_MASK (0x1ff) 6568 #define PIPE_WM_LINETIME_TIME(x) ((x)) 6569 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 6570 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 6571 6572 /* SFUSE_STRAP */ 6573 #define SFUSE_STRAP 0xc2014 6574 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 6575 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 6576 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 6577 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 6578 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 6579 6580 #define WM_MISC 0x45260 6581 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 6582 6583 #define WM_DBG 0x45280 6584 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 6585 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 6586 #define WM_DBG_DISALLOW_SPRITE (1<<2) 6587 6588 /* pipe CSC */ 6589 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 6590 #define _PIPE_A_CSC_COEFF_BY 0x49014 6591 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 6592 #define _PIPE_A_CSC_COEFF_BU 0x4901c 6593 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 6594 #define _PIPE_A_CSC_COEFF_BV 0x49024 6595 #define _PIPE_A_CSC_MODE 0x49028 6596 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 6597 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 6598 #define CSC_MODE_YUV_TO_RGB (1 << 0) 6599 #define _PIPE_A_CSC_PREOFF_HI 0x49030 6600 #define _PIPE_A_CSC_PREOFF_ME 0x49034 6601 #define _PIPE_A_CSC_PREOFF_LO 0x49038 6602 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 6603 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 6604 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 6605 6606 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 6607 #define _PIPE_B_CSC_COEFF_BY 0x49114 6608 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 6609 #define _PIPE_B_CSC_COEFF_BU 0x4911c 6610 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 6611 #define _PIPE_B_CSC_COEFF_BV 0x49124 6612 #define _PIPE_B_CSC_MODE 0x49128 6613 #define _PIPE_B_CSC_PREOFF_HI 0x49130 6614 #define _PIPE_B_CSC_PREOFF_ME 0x49134 6615 #define _PIPE_B_CSC_PREOFF_LO 0x49138 6616 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 6617 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 6618 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 6619 6620 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 6621 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 6622 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 6623 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 6624 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 6625 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 6626 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 6627 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 6628 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 6629 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 6630 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 6631 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 6632 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 6633 6634 /* VLV MIPI registers */ 6635 6636 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 6637 #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 6638 #define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ 6639 _MIPIB_PORT_CTRL) 6640 #define DPI_ENABLE (1 << 31) /* A + B */ 6641 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 6642 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 6643 #define DUAL_LINK_MODE_MASK (1 << 26) 6644 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 6645 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 6646 #define DITHERING_ENABLE (1 << 25) /* A + B */ 6647 #define FLOPPED_HSTX (1 << 23) 6648 #define DE_INVERT (1 << 19) /* XXX */ 6649 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 6650 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 6651 #define AFE_LATCHOUT (1 << 17) 6652 #define LP_OUTPUT_HOLD (1 << 16) 6653 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 6654 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 6655 #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 6656 #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 6657 #define CSB_SHIFT 9 6658 #define CSB_MASK (3 << 9) 6659 #define CSB_20MHZ (0 << 9) 6660 #define CSB_10MHZ (1 << 9) 6661 #define CSB_40MHZ (2 << 9) 6662 #define BANDGAP_MASK (1 << 8) 6663 #define BANDGAP_PNW_CIRCUIT (0 << 8) 6664 #define BANDGAP_LNC_CIRCUIT (1 << 8) 6665 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 6666 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 6667 #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ 6668 #define TEARING_EFFECT_SHIFT 2 /* A + B */ 6669 #define TEARING_EFFECT_MASK (3 << 2) 6670 #define TEARING_EFFECT_OFF (0 << 2) 6671 #define TEARING_EFFECT_DSI (1 << 2) 6672 #define TEARING_EFFECT_GPIO (2 << 2) 6673 #define LANE_CONFIGURATION_SHIFT 0 6674 #define LANE_CONFIGURATION_MASK (3 << 0) 6675 #define LANE_CONFIGURATION_4LANE (0 << 0) 6676 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 6677 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 6678 6679 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 6680 #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 6681 #define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ 6682 _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) 6683 #define TEARING_EFFECT_DELAY_SHIFT 0 6684 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 6685 6686 /* XXX: all bits reserved */ 6687 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 6688 6689 /* MIPI DSI Controller and D-PHY registers */ 6690 6691 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 6692 #define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 6693 #define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ 6694 _MIPIB_DEVICE_READY) 6695 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 6696 #define ULPS_STATE_MASK (3 << 1) 6697 #define ULPS_STATE_ENTER (2 << 1) 6698 #define ULPS_STATE_EXIT (1 << 1) 6699 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 6700 #define DEVICE_READY (1 << 0) 6701 6702 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 6703 #define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 6704 #define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ 6705 _MIPIB_INTR_STAT) 6706 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 6707 #define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 6708 #define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ 6709 _MIPIB_INTR_EN) 6710 #define TEARING_EFFECT (1 << 31) 6711 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 6712 #define GEN_READ_DATA_AVAIL (1 << 29) 6713 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 6714 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 6715 #define RX_PROT_VIOLATION (1 << 26) 6716 #define RX_INVALID_TX_LENGTH (1 << 25) 6717 #define ACK_WITH_NO_ERROR (1 << 24) 6718 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 6719 #define LP_RX_TIMEOUT (1 << 22) 6720 #define HS_TX_TIMEOUT (1 << 21) 6721 #define DPI_FIFO_UNDERRUN (1 << 20) 6722 #define LOW_CONTENTION (1 << 19) 6723 #define HIGH_CONTENTION (1 << 18) 6724 #define TXDSI_VC_ID_INVALID (1 << 17) 6725 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 6726 #define TXCHECKSUM_ERROR (1 << 15) 6727 #define TXECC_MULTIBIT_ERROR (1 << 14) 6728 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 6729 #define TXFALSE_CONTROL_ERROR (1 << 12) 6730 #define RXDSI_VC_ID_INVALID (1 << 11) 6731 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 6732 #define RXCHECKSUM_ERROR (1 << 9) 6733 #define RXECC_MULTIBIT_ERROR (1 << 8) 6734 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 6735 #define RXFALSE_CONTROL_ERROR (1 << 6) 6736 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 6737 #define RX_LP_TX_SYNC_ERROR (1 << 4) 6738 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 6739 #define RXEOT_SYNC_ERROR (1 << 2) 6740 #define RXSOT_SYNC_ERROR (1 << 1) 6741 #define RXSOT_ERROR (1 << 0) 6742 6743 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 6744 #define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 6745 #define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ 6746 _MIPIB_DSI_FUNC_PRG) 6747 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 6748 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 6749 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 6750 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 6751 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 6752 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 6753 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 6754 #define VID_MODE_FORMAT_MASK (0xf << 7) 6755 #define VID_MODE_NOT_SUPPORTED (0 << 7) 6756 #define VID_MODE_FORMAT_RGB565 (1 << 7) 6757 #define VID_MODE_FORMAT_RGB666 (2 << 7) 6758 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) 6759 #define VID_MODE_FORMAT_RGB888 (4 << 7) 6760 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 6761 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 6762 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 6763 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 6764 #define DATA_LANES_PRG_REG_SHIFT 0 6765 #define DATA_LANES_PRG_REG_MASK (7 << 0) 6766 6767 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 6768 #define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 6769 #define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ 6770 _MIPIB_HS_TX_TIMEOUT) 6771 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 6772 6773 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 6774 #define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 6775 #define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ 6776 _MIPIB_LP_RX_TIMEOUT) 6777 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 6778 6779 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 6780 #define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 6781 #define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ 6782 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) 6783 #define TURN_AROUND_TIMEOUT_MASK 0x3f 6784 6785 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 6786 #define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 6787 #define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ 6788 _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) 6789 #define DEVICE_RESET_TIMER_MASK 0xffff 6790 6791 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 6792 #define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 6793 #define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ 6794 _MIPIB_DPI_RESOLUTION) 6795 #define VERTICAL_ADDRESS_SHIFT 16 6796 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 6797 #define HORIZONTAL_ADDRESS_SHIFT 0 6798 #define HORIZONTAL_ADDRESS_MASK 0xffff 6799 6800 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 6801 #define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 6802 #define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ 6803 _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) 6804 #define DBI_FIFO_EMPTY_HALF (0 << 0) 6805 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 6806 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 6807 6808 /* regs below are bits 15:0 */ 6809 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 6810 #define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 6811 #define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ 6812 _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) 6813 6814 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 6815 #define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 6816 #define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ 6817 _MIPIB_HBP_COUNT) 6818 6819 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 6820 #define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 6821 #define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ 6822 _MIPIB_HFP_COUNT) 6823 6824 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 6825 #define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 6826 #define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ 6827 _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) 6828 6829 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 6830 #define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 6831 #define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ 6832 _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) 6833 6834 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 6835 #define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 6836 #define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ 6837 _MIPIB_VBP_COUNT) 6838 6839 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 6840 #define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 6841 #define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ 6842 _MIPIB_VFP_COUNT) 6843 6844 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 6845 #define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 6846 #define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ 6847 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) 6848 6849 /* regs above are bits 15:0 */ 6850 6851 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 6852 #define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 6853 #define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ 6854 _MIPIB_DPI_CONTROL) 6855 #define DPI_LP_MODE (1 << 6) 6856 #define BACKLIGHT_OFF (1 << 5) 6857 #define BACKLIGHT_ON (1 << 4) 6858 #define COLOR_MODE_OFF (1 << 3) 6859 #define COLOR_MODE_ON (1 << 2) 6860 #define TURN_ON (1 << 1) 6861 #define SHUTDOWN (1 << 0) 6862 6863 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 6864 #define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 6865 #define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ 6866 _MIPIB_DPI_DATA) 6867 #define COMMAND_BYTE_SHIFT 0 6868 #define COMMAND_BYTE_MASK (0x3f << 0) 6869 6870 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 6871 #define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 6872 #define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ 6873 _MIPIB_INIT_COUNT) 6874 #define MASTER_INIT_TIMER_SHIFT 0 6875 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 6876 6877 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 6878 #define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 6879 #define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ 6880 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) 6881 #define MAX_RETURN_PKT_SIZE_SHIFT 0 6882 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 6883 6884 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 6885 #define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 6886 #define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ 6887 _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) 6888 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 6889 #define DISABLE_VIDEO_BTA (1 << 3) 6890 #define IP_TG_CONFIG (1 << 2) 6891 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 6892 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 6893 #define VIDEO_MODE_BURST (3 << 0) 6894 6895 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 6896 #define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 6897 #define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ 6898 _MIPIB_EOT_DISABLE) 6899 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 6900 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 6901 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 6902 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 6903 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 6904 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 6905 #define CLOCKSTOP (1 << 1) 6906 #define EOT_DISABLE (1 << 0) 6907 6908 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 6909 #define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 6910 #define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ 6911 _MIPIB_LP_BYTECLK) 6912 #define LP_BYTECLK_SHIFT 0 6913 #define LP_BYTECLK_MASK (0xffff << 0) 6914 6915 /* bits 31:0 */ 6916 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 6917 #define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 6918 #define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ 6919 _MIPIB_LP_GEN_DATA) 6920 6921 /* bits 31:0 */ 6922 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 6923 #define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 6924 #define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ 6925 _MIPIB_HS_GEN_DATA) 6926 6927 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 6928 #define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 6929 #define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ 6930 _MIPIB_LP_GEN_CTRL) 6931 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 6932 #define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 6933 #define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ 6934 _MIPIB_HS_GEN_CTRL) 6935 #define LONG_PACKET_WORD_COUNT_SHIFT 8 6936 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 6937 #define SHORT_PACKET_PARAM_SHIFT 8 6938 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 6939 #define VIRTUAL_CHANNEL_SHIFT 6 6940 #define VIRTUAL_CHANNEL_MASK (3 << 6) 6941 #define DATA_TYPE_SHIFT 0 6942 #define DATA_TYPE_MASK (3f << 0) 6943 /* data type values, see include/video/mipi_display.h */ 6944 6945 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 6946 #define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 6947 #define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ 6948 _MIPIB_GEN_FIFO_STAT) 6949 #define DPI_FIFO_EMPTY (1 << 28) 6950 #define DBI_FIFO_EMPTY (1 << 27) 6951 #define LP_CTRL_FIFO_EMPTY (1 << 26) 6952 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 6953 #define LP_CTRL_FIFO_FULL (1 << 24) 6954 #define HS_CTRL_FIFO_EMPTY (1 << 18) 6955 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 6956 #define HS_CTRL_FIFO_FULL (1 << 16) 6957 #define LP_DATA_FIFO_EMPTY (1 << 10) 6958 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 6959 #define LP_DATA_FIFO_FULL (1 << 8) 6960 #define HS_DATA_FIFO_EMPTY (1 << 2) 6961 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 6962 #define HS_DATA_FIFO_FULL (1 << 0) 6963 6964 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 6965 #define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 6966 #define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ 6967 _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) 6968 #define DBI_HS_LP_MODE_MASK (1 << 0) 6969 #define DBI_LP_MODE (1 << 0) 6970 #define DBI_HS_MODE (0 << 0) 6971 6972 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 6973 #define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 6974 #define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ 6975 _MIPIB_DPHY_PARAM) 6976 #define EXIT_ZERO_COUNT_SHIFT 24 6977 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 6978 #define TRAIL_COUNT_SHIFT 16 6979 #define TRAIL_COUNT_MASK (0x1f << 16) 6980 #define CLK_ZERO_COUNT_SHIFT 8 6981 #define CLK_ZERO_COUNT_MASK (0xff << 8) 6982 #define PREPARE_COUNT_SHIFT 0 6983 #define PREPARE_COUNT_MASK (0x3f << 0) 6984 6985 /* bits 31:0 */ 6986 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 6987 #define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 6988 #define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ 6989 _MIPIB_DBI_BW_CTRL) 6990 6991 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ 6992 + 0xb088) 6993 #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ 6994 + 0xb888) 6995 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ 6996 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) 6997 #define LP_HS_SSW_CNT_SHIFT 16 6998 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 6999 #define HS_LP_PWR_SW_CNT_SHIFT 0 7000 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 7001 7002 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 7003 #define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 7004 #define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ 7005 _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) 7006 #define STOP_STATE_STALL_COUNTER_SHIFT 0 7007 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 7008 7009 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 7010 #define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 7011 #define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ 7012 _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) 7013 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 7014 #define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 7015 #define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ 7016 _MIPIB_INTR_EN_REG_1) 7017 #define RX_CONTENTION_DETECTED (1 << 0) 7018 7019 /* XXX: only pipe A ?!? */ 7020 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 7021 #define DBI_TYPEC_ENABLE (1 << 31) 7022 #define DBI_TYPEC_WIP (1 << 30) 7023 #define DBI_TYPEC_OPTION_SHIFT 28 7024 #define DBI_TYPEC_OPTION_MASK (3 << 28) 7025 #define DBI_TYPEC_FREQ_SHIFT 24 7026 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 7027 #define DBI_TYPEC_OVERRIDE (1 << 8) 7028 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 7029 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 7030 7031 7032 /* MIPI adapter registers */ 7033 7034 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 7035 #define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) 7036 #define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ 7037 _MIPIB_CTRL) 7038 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 7039 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 7040 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 7041 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 7042 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 7043 #define READ_REQUEST_PRIORITY_SHIFT 3 7044 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 7045 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 7046 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 7047 #define RGB_FLIP_TO_BGR (1 << 2) 7048 7049 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 7050 #define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 7051 #define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ 7052 _MIPIB_DATA_ADDRESS) 7053 #define DATA_MEM_ADDRESS_SHIFT 5 7054 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 7055 #define DATA_VALID (1 << 0) 7056 7057 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 7058 #define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 7059 #define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ 7060 _MIPIB_DATA_LENGTH) 7061 #define DATA_LENGTH_SHIFT 0 7062 #define DATA_LENGTH_MASK (0xfffff << 0) 7063 7064 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 7065 #define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 7066 #define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ 7067 _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) 7068 #define COMMAND_MEM_ADDRESS_SHIFT 5 7069 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 7070 #define AUTO_PWG_ENABLE (1 << 2) 7071 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 7072 #define COMMAND_VALID (1 << 0) 7073 7074 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 7075 #define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 7076 #define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ 7077 _MIPIB_COMMAND_LENGTH) 7078 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 7079 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 7080 7081 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 7082 #define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 7083 #define MIPI_READ_DATA_RETURN(tc, n) \ 7084 (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ 7085 + 4 * (n)) /* n: 0...7 */ 7086 7087 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 7088 #define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 7089 #define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ 7090 _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) 7091 #define READ_DATA_VALID(n) (1 << (n)) 7092 7093 /* For UMS only (deprecated): */ 7094 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 7095 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 7096 7097 #endif /* _I915_REG_H_ */ 7098