xref: /openbmc/linux/drivers/gpu/drm/i915/i915_reg.h (revision b9221f71)
1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2  * All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27 
28 #include <linux/bitfield.h>
29 #include <linux/bits.h>
30 
31 /**
32  * DOC: The i915 register macro definition style guide
33  *
34  * Follow the style described here for new macros, and while changing existing
35  * macros. Do **not** mass change existing definitions just to update the style.
36  *
37  * File Layout
38  * ~~~~~~~~~~~
39  *
40  * Keep helper macros near the top. For example, _PIPE() and friends.
41  *
42  * Prefix macros that generally should not be used outside of this file with
43  * underscore '_'. For example, _PIPE() and friends, single instances of
44  * registers that are defined solely for the use by function-like macros.
45  *
46  * Avoid using the underscore prefixed macros outside of this file. There are
47  * exceptions, but keep them to a minimum.
48  *
49  * There are two basic types of register definitions: Single registers and
50  * register groups. Register groups are registers which have two or more
51  * instances, for example one per pipe, port, transcoder, etc. Register groups
52  * should be defined using function-like macros.
53  *
54  * For single registers, define the register offset first, followed by register
55  * contents.
56  *
57  * For register groups, define the register instance offsets first, prefixed
58  * with underscore, followed by a function-like macro choosing the right
59  * instance based on the parameter, followed by register contents.
60  *
61  * Define the register contents (i.e. bit and bit field macros) from most
62  * significant to least significant bit. Indent the register content macros
63  * using two extra spaces between ``#define`` and the macro name.
64  *
65  * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66  * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67  * shifted in place, so they can be directly OR'd together. For convenience,
68  * function-like macros may be used to define bit fields, but do note that the
69  * macros may be needed to read as well as write the register contents.
70  *
71  * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72  *
73  * Group the register and its contents together without blank lines, separate
74  * from other registers and their contents with one blank line.
75  *
76  * Indent macro values from macro names using TABs. Align values vertically. Use
77  * braces in macro values as needed to avoid unintended precedence after macro
78  * substitution. Use spaces in macro values according to kernel coding
79  * style. Use lower case in hexadecimal values.
80  *
81  * Naming
82  * ~~~~~~
83  *
84  * Try to name registers according to the specs. If the register name changes in
85  * the specs from platform to another, stick to the original name.
86  *
87  * Try to re-use existing register macro definitions. Only add new macros for
88  * new register offsets, or when the register contents have changed enough to
89  * warrant a full redefinition.
90  *
91  * When a register macro changes for a new platform, prefix the new macro using
92  * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93  * prefix signifies the start platform/generation using the register.
94  *
95  * When a bit (field) macro changes or gets added for a new platform, while
96  * retaining the existing register macro, add a platform acronym or generation
97  * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98  *
99  * Examples
100  * ~~~~~~~~
101  *
102  * (Note that the values in the example are indented using spaces instead of
103  * TABs to avoid misalignment in generated documentation. Use TABs in the
104  * definitions.)::
105  *
106  *  #define _FOO_A                      0xf000
107  *  #define _FOO_B                      0xf001
108  *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109  *  #define   FOO_ENABLE                REG_BIT(31)
110  *  #define   FOO_MODE_MASK             REG_GENMASK(19, 16)
111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
112  *  #define   FOO_MODE_BAZ              REG_FIELD_PREP(FOO_MODE_MASK, 1)
113  *  #define   FOO_MODE_QUX_SNB          REG_FIELD_PREP(FOO_MODE_MASK, 2)
114  *
115  *  #define BAR                         _MMIO(0xb000)
116  *  #define GEN8_BAR                    _MMIO(0xb888)
117  */
118 
119 /**
120  * REG_BIT() - Prepare a u32 bit value
121  * @__n: 0-based bit number
122  *
123  * Local wrapper for BIT() to force u32, with compile time checks.
124  *
125  * @return: Value with bit @__n set.
126  */
127 #define REG_BIT(__n)							\
128 	((u32)(BIT(__n) +						\
129 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&		\
130 				 ((__n) < 0 || (__n) > 31))))
131 
132 /**
133  * REG_GENMASK() - Prepare a continuous u32 bitmask
134  * @__high: 0-based high bit
135  * @__low: 0-based low bit
136  *
137  * Local wrapper for GENMASK() to force u32, with compile time checks.
138  *
139  * @return: Continuous bitmask from @__high to @__low, inclusive.
140  */
141 #define REG_GENMASK(__high, __low)					\
142 	((u32)(GENMASK(__high, __low) +					\
143 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&	\
144 				 __is_constexpr(__low) &&		\
145 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146 
147 /*
148  * Local integer constant expression version of is_power_of_2().
149  */
150 #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
151 
152 /**
153  * REG_FIELD_PREP() - Prepare a u32 bitfield value
154  * @__mask: shifted mask defining the field's length and position
155  * @__val: value to put in the field
156  *
157  * Local copy of FIELD_PREP() to generate an integer constant expression, force
158  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
159  *
160  * @return: @__val masked and shifted into the field defined by @__mask.
161  */
162 #define REG_FIELD_PREP(__mask, __val)						\
163 	((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +	\
164 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +		\
165 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
166 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
168 
169 /**
170  * REG_FIELD_GET() - Extract a u32 bitfield value
171  * @__mask: shifted mask defining the field's length and position
172  * @__val: value to extract the bitfield value from
173  *
174  * Local wrapper for FIELD_GET() to force u32 and for consistency with
175  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176  *
177  * @return: Masked and shifted value of the field defined by @__mask in @__val.
178  */
179 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
180 
181 typedef struct {
182 	u32 reg;
183 } i915_reg_t;
184 
185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186 
187 #define INVALID_MMIO_REG _MMIO(0)
188 
189 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
190 {
191 	return reg.reg;
192 }
193 
194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195 {
196 	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197 }
198 
199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200 {
201 	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202 }
203 
204 #define VLV_DISPLAY_BASE		0x180000
205 #define VLV_MIPI_BASE			VLV_DISPLAY_BASE
206 #define BXT_MIPI_BASE			0x60000
207 
208 #define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display_mmio_offset)
209 
210 /*
211  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212  * numbers, pick the 0-based __index'th value.
213  *
214  * Always prefer this over _PICK() if the numbers are evenly spaced.
215  */
216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
217 
218 /*
219  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
220  *
221  * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
222  */
223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
224 
225 /*
226  * Named helper wrappers around _PICK_EVEN() and _PICK().
227  */
228 #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
229 #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
230 #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
231 #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
232 #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
233 #define _PHY(phy, a, b)			_PICK_EVEN(phy, a, b)
234 
235 #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
236 #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
237 #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
238 #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
239 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
240 #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
241 
242 #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
243 
244 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
245 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
246 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
247 #define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
248 
249 
250 /*
251  * Device info offset array based helpers for groups of registers with unevenly
252  * spaced base offsets.
253  */
254 #define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
255 					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
256 					      DISPLAY_MMIO_BASE(dev_priv))
257 #define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
258 					 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
259 					 DISPLAY_MMIO_BASE(dev_priv))
260 #define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))
261 #define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
262 					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
263 					      DISPLAY_MMIO_BASE(dev_priv))
264 
265 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
266 #define _MASKED_FIELD(mask, value) ({					   \
267 	if (__builtin_constant_p(mask))					   \
268 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
269 	if (__builtin_constant_p(value))				   \
270 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
271 	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
272 		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
273 				 "Incorrect value for mask");		   \
274 	__MASKED_FIELD(mask, value); })
275 #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
276 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
277 
278 /* PCI config space */
279 
280 #define MCHBAR_I915 0x44
281 #define MCHBAR_I965 0x48
282 #define MCHBAR_SIZE (4 * 4096)
283 
284 #define DEVEN 0x54
285 #define   DEVEN_MCHBAR_EN (1 << 28)
286 
287 /* BSM in include/drm/i915_drm.h */
288 
289 #define HPLLCC	0xc0 /* 85x only */
290 #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
291 #define   GC_CLOCK_133_200		(0 << 0)
292 #define   GC_CLOCK_100_200		(1 << 0)
293 #define   GC_CLOCK_100_133		(2 << 0)
294 #define   GC_CLOCK_133_266		(3 << 0)
295 #define   GC_CLOCK_133_200_2		(4 << 0)
296 #define   GC_CLOCK_133_266_2		(5 << 0)
297 #define   GC_CLOCK_166_266		(6 << 0)
298 #define   GC_CLOCK_166_250		(7 << 0)
299 
300 #define I915_GDRST 0xc0 /* PCI config register */
301 #define   GRDOM_FULL		(0 << 2)
302 #define   GRDOM_RENDER		(1 << 2)
303 #define   GRDOM_MEDIA		(3 << 2)
304 #define   GRDOM_MASK		(3 << 2)
305 #define   GRDOM_RESET_STATUS	(1 << 1)
306 #define   GRDOM_RESET_ENABLE	(1 << 0)
307 
308 /* BSpec only has register offset, PCI device and bit found empirically */
309 #define I830_CLOCK_GATE	0xc8 /* device 0 */
310 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
311 
312 #define GCDGMBUS 0xcc
313 
314 #define GCFGC2	0xda
315 #define GCFGC	0xf0 /* 915+ only */
316 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
317 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
318 #define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
319 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
320 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
321 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
322 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
323 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
324 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
325 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
326 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
327 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
328 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
329 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
330 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
331 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
332 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
333 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
334 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
335 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
336 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
337 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
338 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
339 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
340 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
341 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
342 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
343 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
344 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
345 
346 #define ASLE	0xe4
347 #define ASLS	0xfc
348 
349 #define SWSCI	0xe8
350 #define   SWSCI_SCISEL	(1 << 15)
351 #define   SWSCI_GSSCIE	(1 << 0)
352 
353 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
354 
355 
356 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
357 #define  ILK_GRDOM_FULL		(0 << 1)
358 #define  ILK_GRDOM_RENDER	(1 << 1)
359 #define  ILK_GRDOM_MEDIA	(3 << 1)
360 #define  ILK_GRDOM_MASK		(3 << 1)
361 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
362 
363 #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
364 #define   GEN6_MBC_SNPCR_SHIFT	21
365 #define   GEN6_MBC_SNPCR_MASK	(3 << 21)
366 #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
367 #define   GEN6_MBC_SNPCR_MED	(1 << 21)
368 #define   GEN6_MBC_SNPCR_LOW	(2 << 21)
369 #define   GEN6_MBC_SNPCR_MIN	(3 << 21) /* only 1/16th of the cache is shared */
370 
371 #define VLV_G3DCTL		_MMIO(0x9024)
372 #define VLV_GSCKGCTL		_MMIO(0x9028)
373 
374 #define GEN6_MBCTL		_MMIO(0x0907c)
375 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
376 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
377 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
378 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
379 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
380 
381 #define GEN6_GDRST	_MMIO(0x941c)
382 #define  GEN6_GRDOM_FULL		(1 << 0)
383 #define  GEN6_GRDOM_RENDER		(1 << 1)
384 #define  GEN6_GRDOM_MEDIA		(1 << 2)
385 #define  GEN6_GRDOM_BLT			(1 << 3)
386 #define  GEN6_GRDOM_VECS		(1 << 4)
387 #define  GEN9_GRDOM_GUC			(1 << 5)
388 #define  GEN8_GRDOM_MEDIA2		(1 << 7)
389 /* GEN11 changed all bit defs except for FULL & RENDER */
390 #define  GEN11_GRDOM_FULL		GEN6_GRDOM_FULL
391 #define  GEN11_GRDOM_RENDER		GEN6_GRDOM_RENDER
392 #define  GEN11_GRDOM_BLT		(1 << 2)
393 #define  GEN11_GRDOM_GUC		(1 << 3)
394 #define  GEN11_GRDOM_MEDIA		(1 << 5)
395 #define  GEN11_GRDOM_MEDIA2		(1 << 6)
396 #define  GEN11_GRDOM_MEDIA3		(1 << 7)
397 #define  GEN11_GRDOM_MEDIA4		(1 << 8)
398 #define  GEN11_GRDOM_MEDIA5		(1 << 9)
399 #define  GEN11_GRDOM_MEDIA6		(1 << 10)
400 #define  GEN11_GRDOM_MEDIA7		(1 << 11)
401 #define  GEN11_GRDOM_MEDIA8		(1 << 12)
402 #define  GEN11_GRDOM_VECS		(1 << 13)
403 #define  GEN11_GRDOM_VECS2		(1 << 14)
404 #define  GEN11_GRDOM_VECS3		(1 << 15)
405 #define  GEN11_GRDOM_VECS4		(1 << 16)
406 #define  GEN11_GRDOM_SFC0		(1 << 17)
407 #define  GEN11_GRDOM_SFC1		(1 << 18)
408 #define  GEN11_GRDOM_SFC2		(1 << 19)
409 #define  GEN11_GRDOM_SFC3		(1 << 20)
410 
411 #define  GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
412 #define  GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))
413 
414 #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
415 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT		(1 << 0)
416 #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
417 #define   GEN11_VCS_SFC_USAGE_BIT		(1 << 0)
418 #define   GEN11_VCS_SFC_LOCK_ACK_BIT		(1 << 1)
419 
420 #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
421 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT	(1 << 0)
422 #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
423 #define   GEN11_VECS_SFC_LOCK_ACK_BIT		(1 << 0)
424 #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
425 #define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)
426 
427 #define GEN12_HCP_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x2910)
428 #define   GEN12_HCP_SFC_FORCED_LOCK_BIT		REG_BIT(0)
429 #define GEN12_HCP_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x2914)
430 #define   GEN12_HCP_SFC_LOCK_ACK_BIT		REG_BIT(1)
431 #define   GEN12_HCP_SFC_USAGE_BIT			REG_BIT(0)
432 
433 #define GEN12_SFC_DONE(n)		_MMIO(0x1cc000 + (n) * 0x1000)
434 #define GEN12_SFC_DONE_MAX		4
435 
436 #define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)
437 #define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)
438 #define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)
439 #define   PP_DIR_DCLV_2G		0xffffffff
440 
441 #define GEN8_RING_PDP_UDW(base, n)	_MMIO((base) + 0x270 + (n) * 8 + 4)
442 #define GEN8_RING_PDP_LDW(base, n)	_MMIO((base) + 0x270 + (n) * 8)
443 
444 #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
445 #define   GEN8_RPCS_ENABLE		(1 << 31)
446 #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
447 #define   GEN8_RPCS_S_CNT_SHIFT		15
448 #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
449 #define   GEN11_RPCS_S_CNT_SHIFT	12
450 #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
451 #define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
452 #define   GEN8_RPCS_SS_CNT_SHIFT	8
453 #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
454 #define   GEN8_RPCS_EU_MAX_SHIFT	4
455 #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
456 #define   GEN8_RPCS_EU_MIN_SHIFT	0
457 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
458 
459 #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
460 /* HSW only */
461 #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2
462 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
463 #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT		4
464 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
465 /* HSW+ */
466 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
467 #define   HSW_RCS_CONTEXT_ENABLE			(1 << 7)
468 #define   HSW_RCS_INHIBIT				(1 << 8)
469 /* Gen8 */
470 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
471 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
472 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
473 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
474 #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE	(1 << 6)
475 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT	9
476 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
477 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT	11
478 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
479 #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
480 
481 #define GAM_ECOCHK			_MMIO(0x4090)
482 #define   BDW_DISABLE_HDC_INVALIDATION	(1 << 25)
483 #define   ECOCHK_SNB_BIT		(1 << 10)
484 #define   ECOCHK_DIS_TLB		(1 << 8)
485 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1 << 6)
486 #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
487 #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
488 #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
489 #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
490 #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
491 #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
492 #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
493 
494 #define GEN8_RC6_CTX_INFO		_MMIO(0x8504)
495 
496 #define GAC_ECO_BITS			_MMIO(0x14090)
497 #define   ECOBITS_SNB_BIT		(1 << 13)
498 #define   ECOBITS_PPGTT_CACHE64B	(3 << 8)
499 #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
500 
501 #define GAB_CTL				_MMIO(0x24000)
502 #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1 << 8)
503 
504 #define GU_CNTL				_MMIO(0x101010)
505 #define   LMEM_INIT			REG_BIT(7)
506 
507 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
508 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
509 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
510 #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
511 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
512 #define GEN6_STOLEN_RESERVED_512K	(1 << 4)
513 #define GEN6_STOLEN_RESERVED_256K	(2 << 4)
514 #define GEN6_STOLEN_RESERVED_128K	(3 << 4)
515 #define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
516 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
517 #define GEN7_STOLEN_RESERVED_256K	(1 << 5)
518 #define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
519 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
520 #define GEN8_STOLEN_RESERVED_2M		(1 << 7)
521 #define GEN8_STOLEN_RESERVED_4M		(2 << 7)
522 #define GEN8_STOLEN_RESERVED_8M		(3 << 7)
523 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
524 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
525 
526 /* VGA stuff */
527 
528 #define VGA_ST01_MDA 0x3ba
529 #define VGA_ST01_CGA 0x3da
530 
531 #define _VGA_MSR_WRITE _MMIO(0x3c2)
532 #define VGA_MSR_WRITE 0x3c2
533 #define VGA_MSR_READ 0x3cc
534 #define   VGA_MSR_MEM_EN (1 << 1)
535 #define   VGA_MSR_CGA_MODE (1 << 0)
536 
537 #define VGA_SR_INDEX 0x3c4
538 #define SR01			1
539 #define VGA_SR_DATA 0x3c5
540 
541 #define VGA_AR_INDEX 0x3c0
542 #define   VGA_AR_VID_EN (1 << 5)
543 #define VGA_AR_DATA_WRITE 0x3c0
544 #define VGA_AR_DATA_READ 0x3c1
545 
546 #define VGA_GR_INDEX 0x3ce
547 #define VGA_GR_DATA 0x3cf
548 /* GR05 */
549 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
550 #define     VGA_GR_MEM_READ_MODE_PLANE 1
551 /* GR06 */
552 #define   VGA_GR_MEM_MODE_MASK 0xc
553 #define   VGA_GR_MEM_MODE_SHIFT 2
554 #define   VGA_GR_MEM_A0000_AFFFF 0
555 #define   VGA_GR_MEM_A0000_BFFFF 1
556 #define   VGA_GR_MEM_B0000_B7FFF 2
557 #define   VGA_GR_MEM_B0000_BFFFF 3
558 
559 #define VGA_DACMASK 0x3c6
560 #define VGA_DACRX 0x3c7
561 #define VGA_DACWX 0x3c8
562 #define VGA_DACDATA 0x3c9
563 
564 #define VGA_CR_INDEX_MDA 0x3b4
565 #define VGA_CR_DATA_MDA 0x3b5
566 #define VGA_CR_INDEX_CGA 0x3d4
567 #define VGA_CR_DATA_CGA 0x3d5
568 
569 #define MI_PREDICATE_SRC0	_MMIO(0x2400)
570 #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
571 #define MI_PREDICATE_SRC1	_MMIO(0x2408)
572 #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
573 #define MI_PREDICATE_DATA       _MMIO(0x2410)
574 #define MI_PREDICATE_RESULT     _MMIO(0x2418)
575 #define MI_PREDICATE_RESULT_1   _MMIO(0x241c)
576 #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
577 #define  LOWER_SLICE_ENABLED	(1 << 0)
578 #define  LOWER_SLICE_DISABLED	(0 << 0)
579 
580 /*
581  * Registers used only by the command parser
582  */
583 #define BCS_SWCTRL _MMIO(0x22200)
584 #define   BCS_SRC_Y REG_BIT(0)
585 #define   BCS_DST_Y REG_BIT(1)
586 
587 /* There are 16 GPR registers */
588 #define BCS_GPR(n)	_MMIO(0x22600 + (n) * 8)
589 #define BCS_GPR_UDW(n)	_MMIO(0x22600 + (n) * 8 + 4)
590 
591 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
592 #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
593 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
594 #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
595 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
596 #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
597 #define IA_VERTICES_COUNT               _MMIO(0x2310)
598 #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
599 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
600 #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
601 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
602 #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
603 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
604 #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
605 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
606 #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
607 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
608 #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
609 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
610 #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
611 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
612 #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
613 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
614 #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
615 
616 /* There are the 4 64-bit counter registers, one for each stream output */
617 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
618 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
619 
620 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
621 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
622 
623 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
624 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
625 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
626 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
627 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
628 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
629 
630 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
631 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
632 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
633 
634 /* There are the 16 64-bit CS General Purpose Registers */
635 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
636 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
637 
638 #define GEN7_OACONTROL _MMIO(0x2360)
639 #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
640 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
641 #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
642 #define  GEN7_OACONTROL_TIMER_ENABLE	    (1 << 5)
643 #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
644 #define  GEN7_OACONTROL_FORMAT_A29	    (1 << 2)
645 #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
646 #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
647 #define  GEN7_OACONTROL_FORMAT_B4_C8	    (4 << 2)
648 #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
649 #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
650 #define  GEN7_OACONTROL_FORMAT_C4_B8	    (7 << 2)
651 #define  GEN7_OACONTROL_FORMAT_SHIFT	    2
652 #define  GEN7_OACONTROL_PER_CTX_ENABLE	    (1 << 1)
653 #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
654 
655 #define GEN8_OACTXID _MMIO(0x2364)
656 
657 #define GEN8_OA_DEBUG _MMIO(0x2B04)
658 #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
659 #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO	    (1 << 6)
660 #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS	    (1 << 2)
661 #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
662 
663 #define GEN8_OACONTROL _MMIO(0x2B00)
664 #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
665 #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
666 #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
667 #define  GEN8_OA_REPORT_FORMAT_C4_B8	    (7 << 2)
668 #define  GEN8_OA_REPORT_FORMAT_SHIFT	    2
669 #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
670 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
671 
672 #define GEN8_OACTXCONTROL _MMIO(0x2360)
673 #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
674 #define  GEN8_OA_TIMER_PERIOD_SHIFT	    2
675 #define  GEN8_OA_TIMER_ENABLE		    (1 << 1)
676 #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
677 
678 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
679 #define  GEN7_OABUFFER_OVERRUN_DISABLE	    (1 << 3)
680 #define  GEN7_OABUFFER_EDGE_TRIGGER	    (1 << 2)
681 #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
682 #define  GEN7_OABUFFER_RESUME		    (1 << 0)
683 
684 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
685 #define GEN8_OABUFFER _MMIO(0x2b14)
686 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
687 
688 #define GEN7_OASTATUS1 _MMIO(0x2364)
689 #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
690 #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
691 #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
692 #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
693 
694 #define GEN7_OASTATUS2 _MMIO(0x2368)
695 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
696 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
697 
698 #define GEN8_OASTATUS _MMIO(0x2b08)
699 #define  GEN8_OASTATUS_TAIL_POINTER_WRAP    (1 << 17)
700 #define  GEN8_OASTATUS_HEAD_POINTER_WRAP    (1 << 16)
701 #define  GEN8_OASTATUS_OVERRUN_STATUS	    (1 << 3)
702 #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
703 #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
704 #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
705 
706 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
707 #define GEN8_OAHEADPTR_MASK    0xffffffc0
708 #define GEN8_OATAILPTR _MMIO(0x2B10)
709 #define GEN8_OATAILPTR_MASK    0xffffffc0
710 
711 #define OABUFFER_SIZE_128K  (0 << 3)
712 #define OABUFFER_SIZE_256K  (1 << 3)
713 #define OABUFFER_SIZE_512K  (2 << 3)
714 #define OABUFFER_SIZE_1M    (3 << 3)
715 #define OABUFFER_SIZE_2M    (4 << 3)
716 #define OABUFFER_SIZE_4M    (5 << 3)
717 #define OABUFFER_SIZE_8M    (6 << 3)
718 #define OABUFFER_SIZE_16M   (7 << 3)
719 
720 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
721 
722 /* Gen12 OAR unit */
723 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
724 #define  GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
725 #define  GEN12_OAR_OACONTROL_COUNTER_ENABLE       (1 << 0)
726 
727 #define GEN12_OACTXCONTROL _MMIO(0x2360)
728 #define GEN12_OAR_OASTATUS _MMIO(0x2968)
729 
730 /* Gen12 OAG unit */
731 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
732 #define  GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
733 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
734 #define  GEN12_OAG_OATAILPTR_MASK 0xffffffc0
735 
736 #define GEN12_OAG_OABUFFER  _MMIO(0xdb08)
737 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK  (0x7)
738 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
739 #define  GEN12_OAG_OABUFFER_MEMORY_SELECT     (1 << 0) /* 0: PPGTT, 1: GGTT */
740 
741 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
742 #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
743 #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE       (1 << 1)
744 #define  GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME     (1 << 0)
745 
746 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
747 #define  GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
748 #define  GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE       (1 << 0)
749 
750 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
751 #define  GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO          (1 << 6)
752 #define  GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS  (1 << 5)
753 #define  GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS     (1 << 2)
754 #define  GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
755 
756 #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
757 #define  GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
758 #define  GEN12_OAG_OASTATUS_BUFFER_OVERFLOW  (1 << 1)
759 #define  GEN12_OAG_OASTATUS_REPORT_LOST      (1 << 0)
760 
761 /*
762  * Flexible, Aggregate EU Counter Registers.
763  * Note: these aren't contiguous
764  */
765 #define EU_PERF_CNTL0	    _MMIO(0xe458)
766 #define EU_PERF_CNTL1	    _MMIO(0xe558)
767 #define EU_PERF_CNTL2	    _MMIO(0xe658)
768 #define EU_PERF_CNTL3	    _MMIO(0xe758)
769 #define EU_PERF_CNTL4	    _MMIO(0xe45c)
770 #define EU_PERF_CNTL5	    _MMIO(0xe55c)
771 #define EU_PERF_CNTL6	    _MMIO(0xe65c)
772 
773 /*
774  * OA Boolean state
775  */
776 
777 #define OASTARTTRIG1 _MMIO(0x2710)
778 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
779 #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
780 
781 #define OASTARTTRIG2 _MMIO(0x2714)
782 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
783 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
784 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
785 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
786 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
787 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
788 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
789 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
790 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
791 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
792 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
793 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
794 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
795 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
796 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
797 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
798 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
799 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
800 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
801 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
802 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
803 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
804 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
805 #define OASTARTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
806 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
807 #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
808 #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
809 #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
810 #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
811 
812 #define OASTARTTRIG3 _MMIO(0x2718)
813 #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
814 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
815 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
816 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
817 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
818 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
819 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
820 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
821 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
822 
823 #define OASTARTTRIG4 _MMIO(0x271c)
824 #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
825 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
826 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
827 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
828 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
829 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
830 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
831 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
832 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
833 
834 #define OASTARTTRIG5 _MMIO(0x2720)
835 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
836 #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
837 
838 #define OASTARTTRIG6 _MMIO(0x2724)
839 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
840 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
841 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
842 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
843 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
844 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
845 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
846 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
847 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
848 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
849 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
850 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
851 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
852 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
853 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
854 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
855 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
856 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
857 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
858 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
859 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
860 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
861 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
862 #define OASTARTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
863 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
864 #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
865 #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
866 #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
867 #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
868 
869 #define OASTARTTRIG7 _MMIO(0x2728)
870 #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
871 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
872 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
873 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
874 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
875 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
876 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
877 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
878 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
879 
880 #define OASTARTTRIG8 _MMIO(0x272c)
881 #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
882 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
883 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
884 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
885 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
886 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
887 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
888 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
889 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
890 
891 #define OAREPORTTRIG1 _MMIO(0x2740)
892 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
893 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
894 
895 #define OAREPORTTRIG2 _MMIO(0x2744)
896 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
897 #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
898 #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
899 #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
900 #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
901 #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
902 #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
903 #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
904 #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
905 #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
906 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
907 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
908 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
909 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
910 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
911 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
912 #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
913 #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
914 #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
915 #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
916 #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
917 #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
918 #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
919 #define OAREPORTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
920 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
921 
922 #define OAREPORTTRIG3 _MMIO(0x2748)
923 #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
924 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
925 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
926 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
927 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
928 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
929 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
930 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
931 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
932 
933 #define OAREPORTTRIG4 _MMIO(0x274c)
934 #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
935 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
936 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
937 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
938 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
939 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
940 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
941 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
942 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
943 
944 #define OAREPORTTRIG5 _MMIO(0x2750)
945 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
946 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
947 
948 #define OAREPORTTRIG6 _MMIO(0x2754)
949 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
950 #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
951 #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
952 #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
953 #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
954 #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
955 #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
956 #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
957 #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
958 #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
959 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
960 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
961 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
962 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
963 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
964 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
965 #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
966 #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
967 #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
968 #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
969 #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
970 #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
971 #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
972 #define OAREPORTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
973 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
974 
975 #define OAREPORTTRIG7 _MMIO(0x2758)
976 #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
977 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
978 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
979 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
980 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
981 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
982 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
983 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
984 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
985 
986 #define OAREPORTTRIG8 _MMIO(0x275c)
987 #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
988 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
989 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
990 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
991 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
992 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
993 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
994 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
995 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
996 
997 /* Same layout as OASTARTTRIGX */
998 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
999 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
1000 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
1001 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
1002 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
1003 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
1004 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
1005 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
1006 
1007 /* Same layout as OAREPORTTRIGX */
1008 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
1009 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
1010 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
1011 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
1012 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
1013 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
1014 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
1015 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
1016 
1017 /* CECX_0 */
1018 #define OACEC_COMPARE_LESS_OR_EQUAL	6
1019 #define OACEC_COMPARE_NOT_EQUAL		5
1020 #define OACEC_COMPARE_LESS_THAN		4
1021 #define OACEC_COMPARE_GREATER_OR_EQUAL	3
1022 #define OACEC_COMPARE_EQUAL		2
1023 #define OACEC_COMPARE_GREATER_THAN	1
1024 #define OACEC_COMPARE_ANY_EQUAL		0
1025 
1026 #define OACEC_COMPARE_VALUE_MASK    0xffff
1027 #define OACEC_COMPARE_VALUE_SHIFT   3
1028 
1029 #define OACEC_SELECT_NOA	(0 << 19)
1030 #define OACEC_SELECT_PREV	(1 << 19)
1031 #define OACEC_SELECT_BOOLEAN	(2 << 19)
1032 
1033 /* 11-bit array 0: pass-through, 1: negated */
1034 #define GEN12_OASCEC_NEGATE_MASK  0x7ff
1035 #define GEN12_OASCEC_NEGATE_SHIFT 21
1036 
1037 /* CECX_1 */
1038 #define OACEC_MASK_MASK		    0xffff
1039 #define OACEC_CONSIDERATIONS_MASK   0xffff
1040 #define OACEC_CONSIDERATIONS_SHIFT  16
1041 
1042 #define OACEC0_0 _MMIO(0x2770)
1043 #define OACEC0_1 _MMIO(0x2774)
1044 #define OACEC1_0 _MMIO(0x2778)
1045 #define OACEC1_1 _MMIO(0x277c)
1046 #define OACEC2_0 _MMIO(0x2780)
1047 #define OACEC2_1 _MMIO(0x2784)
1048 #define OACEC3_0 _MMIO(0x2788)
1049 #define OACEC3_1 _MMIO(0x278c)
1050 #define OACEC4_0 _MMIO(0x2790)
1051 #define OACEC4_1 _MMIO(0x2794)
1052 #define OACEC5_0 _MMIO(0x2798)
1053 #define OACEC5_1 _MMIO(0x279c)
1054 #define OACEC6_0 _MMIO(0x27a0)
1055 #define OACEC6_1 _MMIO(0x27a4)
1056 #define OACEC7_0 _MMIO(0x27a8)
1057 #define OACEC7_1 _MMIO(0x27ac)
1058 
1059 /* Same layout as CECX_Y */
1060 #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1061 #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1062 #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1063 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1064 #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1065 #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1066 #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1067 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1068 #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1069 #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1070 #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1071 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1072 #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1073 #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1074 #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1075 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1076 
1077 /* Same layout as CECX_Y + negate 11-bit array */
1078 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1079 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1080 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1081 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1082 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1083 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1084 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1085 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1086 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1087 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1088 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1089 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1090 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1091 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1092 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1093 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1094 
1095 /* OA perf counters */
1096 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
1097 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
1098 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
1099 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
1100 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
1101 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
1102 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
1103 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
1104 
1105 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
1106 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
1107 
1108 /* RPM unit config (Gen8+) */
1109 #define RPM_CONFIG0	    _MMIO(0x0D00)
1110 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
1111 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1112 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
1113 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	1
1114 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
1115 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1116 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
1117 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
1118 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
1119 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	3
1120 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT	1
1121 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1122 
1123 #define RPM_CONFIG1	    _MMIO(0x0D04)
1124 #define  GEN10_GT_NOA_ENABLE  (1 << 9)
1125 
1126 /* GPM unit config (Gen9+) */
1127 #define CTC_MODE			_MMIO(0xA26C)
1128 #define  CTC_SOURCE_PARAMETER_MASK 1
1129 #define  CTC_SOURCE_CRYSTAL_CLOCK	0
1130 #define  CTC_SOURCE_DIVIDE_LOGIC	1
1131 #define  CTC_SHIFT_PARAMETER_SHIFT	1
1132 #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1133 
1134 /* RCP unit config (Gen8+) */
1135 #define RCP_CONFIG	    _MMIO(0x0D08)
1136 
1137 /* NOA (HSW) */
1138 #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
1139 #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
1140 #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
1141 #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
1142 #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
1143 #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
1144 #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
1145 #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
1146 #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
1147 #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
1148 
1149 #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
1150 
1151 /* NOA (Gen8+) */
1152 #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
1153 
1154 #define MICRO_BP0_0	    _MMIO(0x9800)
1155 #define MICRO_BP0_2	    _MMIO(0x9804)
1156 #define MICRO_BP0_1	    _MMIO(0x9808)
1157 
1158 #define MICRO_BP1_0	    _MMIO(0x980C)
1159 #define MICRO_BP1_2	    _MMIO(0x9810)
1160 #define MICRO_BP1_1	    _MMIO(0x9814)
1161 
1162 #define MICRO_BP2_0	    _MMIO(0x9818)
1163 #define MICRO_BP2_2	    _MMIO(0x981C)
1164 #define MICRO_BP2_1	    _MMIO(0x9820)
1165 
1166 #define MICRO_BP3_0	    _MMIO(0x9824)
1167 #define MICRO_BP3_2	    _MMIO(0x9828)
1168 #define MICRO_BP3_1	    _MMIO(0x982C)
1169 
1170 #define MICRO_BP_TRIGGER		_MMIO(0x9830)
1171 #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
1172 #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
1173 #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
1174 
1175 #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1176 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1177 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1178 
1179 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
1180 #define   GT_NOA_ENABLE	    0x00000080
1181 
1182 #define NOA_DATA	    _MMIO(0x986C)
1183 #define NOA_WRITE	    _MMIO(0x9888)
1184 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1185 
1186 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
1187 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
1188 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1189 
1190 /*
1191  * Reset registers
1192  */
1193 #define DEBUG_RESET_I830		_MMIO(0x6070)
1194 #define  DEBUG_RESET_FULL		(1 << 7)
1195 #define  DEBUG_RESET_RENDER		(1 << 8)
1196 #define  DEBUG_RESET_DISPLAY		(1 << 9)
1197 
1198 /*
1199  * IOSF sideband
1200  */
1201 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
1202 #define   IOSF_DEVFN_SHIFT			24
1203 #define   IOSF_OPCODE_SHIFT			16
1204 #define   IOSF_PORT_SHIFT			8
1205 #define   IOSF_BYTE_ENABLES_SHIFT		4
1206 #define   IOSF_BAR_SHIFT			1
1207 #define   IOSF_SB_BUSY				(1 << 0)
1208 #define   IOSF_PORT_BUNIT			0x03
1209 #define   IOSF_PORT_PUNIT			0x04
1210 #define   IOSF_PORT_NC				0x11
1211 #define   IOSF_PORT_DPIO			0x12
1212 #define   IOSF_PORT_GPIO_NC			0x13
1213 #define   IOSF_PORT_CCK				0x14
1214 #define   IOSF_PORT_DPIO_2			0x1a
1215 #define   IOSF_PORT_FLISDSI			0x1b
1216 #define   IOSF_PORT_GPIO_SC			0x48
1217 #define   IOSF_PORT_GPIO_SUS			0xa8
1218 #define   IOSF_PORT_CCU				0xa9
1219 #define   CHV_IOSF_PORT_GPIO_N			0x13
1220 #define   CHV_IOSF_PORT_GPIO_SE			0x48
1221 #define   CHV_IOSF_PORT_GPIO_E			0xa8
1222 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
1223 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
1224 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
1225 
1226 /* See configdb bunit SB addr map */
1227 #define BUNIT_REG_BISOC				0x11
1228 
1229 /* PUNIT_REG_*SSPM0 */
1230 #define   _SSPM0_SSC(val)			((val) << 0)
1231 #define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
1232 #define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
1233 #define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
1234 #define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
1235 #define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
1236 #define   _SSPM0_SSS(val)			((val) << 24)
1237 #define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
1238 #define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
1239 #define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
1240 #define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
1241 #define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
1242 
1243 /* PUNIT_REG_*SSPM1 */
1244 #define   SSPM1_FREQSTAT_SHIFT			24
1245 #define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
1246 #define   SSPM1_FREQGUAR_SHIFT			8
1247 #define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
1248 #define   SSPM1_FREQ_SHIFT			0
1249 #define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
1250 
1251 #define PUNIT_REG_VEDSSPM0			0x32
1252 #define PUNIT_REG_VEDSSPM1			0x33
1253 
1254 #define PUNIT_REG_DSPSSPM			0x36
1255 #define   DSPFREQSTAT_SHIFT_CHV			24
1256 #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
1257 #define   DSPFREQGUAR_SHIFT_CHV			8
1258 #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
1259 #define   DSPFREQSTAT_SHIFT			30
1260 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
1261 #define   DSPFREQGUAR_SHIFT			14
1262 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
1263 #define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
1264 #define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
1265 #define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
1266 #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
1267 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
1268 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
1269 #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
1270 #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
1271 #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
1272 #define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
1273 #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
1274 #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
1275 #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
1276 #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
1277 #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
1278 
1279 #define PUNIT_REG_ISPSSPM0			0x39
1280 #define PUNIT_REG_ISPSSPM1			0x3a
1281 
1282 #define PUNIT_REG_PWRGT_CTRL			0x60
1283 #define PUNIT_REG_PWRGT_STATUS			0x61
1284 #define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
1285 #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
1286 #define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
1287 #define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
1288 #define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
1289 
1290 #define PUNIT_PWGT_IDX_RENDER			0
1291 #define PUNIT_PWGT_IDX_MEDIA			1
1292 #define PUNIT_PWGT_IDX_DISP2D			3
1293 #define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
1294 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
1295 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
1296 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
1297 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
1298 #define PUNIT_PWGT_IDX_DPIO_RX0			10
1299 #define PUNIT_PWGT_IDX_DPIO_RX1			11
1300 #define PUNIT_PWGT_IDX_DPIO_CMN_D		12
1301 
1302 #define PUNIT_REG_GPU_LFM			0xd3
1303 #define PUNIT_REG_GPU_FREQ_REQ			0xd4
1304 #define PUNIT_REG_GPU_FREQ_STS			0xd8
1305 #define   GPLLENABLE				(1 << 4)
1306 #define   GENFREQSTATUS				(1 << 0)
1307 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
1308 #define PUNIT_REG_CZ_TIMESTAMP			0xce
1309 
1310 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
1311 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
1312 
1313 #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
1314 #define FB_GFX_FREQ_FUSE_MASK			0xff
1315 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
1316 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
1317 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
1318 
1319 #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
1320 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
1321 
1322 #define PUNIT_REG_DDR_SETUP2			0x139
1323 #define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
1324 #define   FORCE_DDR_LOW_FREQ			(1 << 1)
1325 #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
1326 
1327 #define PUNIT_GPU_STATUS_REG			0xdb
1328 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
1329 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
1330 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
1331 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
1332 
1333 #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
1334 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
1335 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
1336 
1337 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
1338 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
1339 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
1340 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
1341 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
1342 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
1343 #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
1344 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
1345 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
1346 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
1347 
1348 #define VLV_TURBO_SOC_OVERRIDE		0x04
1349 #define   VLV_OVERRIDE_EN		1
1350 #define   VLV_SOC_TDP_EN		(1 << 1)
1351 #define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
1352 #define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
1353 
1354 /* vlv2 north clock has */
1355 #define CCK_FUSE_REG				0x8
1356 #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
1357 #define CCK_REG_DSI_PLL_FUSE			0x44
1358 #define CCK_REG_DSI_PLL_CONTROL			0x48
1359 #define  DSI_PLL_VCO_EN				(1 << 31)
1360 #define  DSI_PLL_LDO_GATE			(1 << 30)
1361 #define  DSI_PLL_P1_POST_DIV_SHIFT		17
1362 #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
1363 #define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
1364 #define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
1365 #define  DSI_PLL_MUX_MASK			(3 << 9)
1366 #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
1367 #define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
1368 #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
1369 #define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
1370 #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
1371 #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
1372 #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
1373 #define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
1374 #define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
1375 #define  DSI_PLL_LOCK				(1 << 0)
1376 #define CCK_REG_DSI_PLL_DIVIDER			0x4c
1377 #define  DSI_PLL_LFSR				(1 << 31)
1378 #define  DSI_PLL_FRACTION_EN			(1 << 30)
1379 #define  DSI_PLL_FRAC_COUNTER_SHIFT		27
1380 #define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
1381 #define  DSI_PLL_USYNC_CNT_SHIFT		18
1382 #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
1383 #define  DSI_PLL_N1_DIV_SHIFT			16
1384 #define  DSI_PLL_N1_DIV_MASK			(3 << 16)
1385 #define  DSI_PLL_M1_DIV_SHIFT			0
1386 #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
1387 #define CCK_CZ_CLOCK_CONTROL			0x62
1388 #define CCK_GPLL_CLOCK_CONTROL			0x67
1389 #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
1390 #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
1391 #define  CCK_TRUNK_FORCE_ON			(1 << 17)
1392 #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
1393 #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
1394 #define  CCK_FREQUENCY_STATUS_SHIFT		8
1395 #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
1396 
1397 /* DPIO registers */
1398 #define DPIO_DEVFN			0
1399 
1400 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
1401 #define  DPIO_MODSEL1			(1 << 3) /* if ref clk b == 27 */
1402 #define  DPIO_MODSEL0			(1 << 2) /* if ref clk a == 27 */
1403 #define  DPIO_SFR_BYPASS		(1 << 1)
1404 #define  DPIO_CMNRST			(1 << 0)
1405 
1406 #define DPIO_PHY(pipe)			((pipe) >> 1)
1407 
1408 /*
1409  * Per pipe/PLL DPIO regs
1410  */
1411 #define _VLV_PLL_DW3_CH0		0x800c
1412 #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
1413 #define   DPIO_POST_DIV_DAC		0
1414 #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
1415 #define   DPIO_POST_DIV_LVDS1		2
1416 #define   DPIO_POST_DIV_LVDS2		3
1417 #define   DPIO_K_SHIFT			(24) /* 4 bits */
1418 #define   DPIO_P1_SHIFT			(21) /* 3 bits */
1419 #define   DPIO_P2_SHIFT			(16) /* 5 bits */
1420 #define   DPIO_N_SHIFT			(12) /* 4 bits */
1421 #define   DPIO_ENABLE_CALIBRATION	(1 << 11)
1422 #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
1423 #define   DPIO_M2DIV_MASK		0xff
1424 #define _VLV_PLL_DW3_CH1		0x802c
1425 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1426 
1427 #define _VLV_PLL_DW5_CH0		0x8014
1428 #define   DPIO_REFSEL_OVERRIDE		27
1429 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
1430 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
1431 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
1432 #define   DPIO_PLL_REFCLK_SEL_MASK	3
1433 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
1434 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
1435 #define _VLV_PLL_DW5_CH1		0x8034
1436 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1437 
1438 #define _VLV_PLL_DW7_CH0		0x801c
1439 #define _VLV_PLL_DW7_CH1		0x803c
1440 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1441 
1442 #define _VLV_PLL_DW8_CH0		0x8040
1443 #define _VLV_PLL_DW8_CH1		0x8060
1444 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1445 
1446 #define VLV_PLL_DW9_BCAST		0xc044
1447 #define _VLV_PLL_DW9_CH0		0x8044
1448 #define _VLV_PLL_DW9_CH1		0x8064
1449 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1450 
1451 #define _VLV_PLL_DW10_CH0		0x8048
1452 #define _VLV_PLL_DW10_CH1		0x8068
1453 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1454 
1455 #define _VLV_PLL_DW11_CH0		0x804c
1456 #define _VLV_PLL_DW11_CH1		0x806c
1457 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1458 
1459 /* Spec for ref block start counts at DW10 */
1460 #define VLV_REF_DW13			0x80ac
1461 
1462 #define VLV_CMN_DW0			0x8100
1463 
1464 /*
1465  * Per DDI channel DPIO regs
1466  */
1467 
1468 #define _VLV_PCS_DW0_CH0		0x8200
1469 #define _VLV_PCS_DW0_CH1		0x8400
1470 #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
1471 #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
1472 #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
1473 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
1474 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1475 
1476 #define _VLV_PCS01_DW0_CH0		0x200
1477 #define _VLV_PCS23_DW0_CH0		0x400
1478 #define _VLV_PCS01_DW0_CH1		0x2600
1479 #define _VLV_PCS23_DW0_CH1		0x2800
1480 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1481 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1482 
1483 #define _VLV_PCS_DW1_CH0		0x8204
1484 #define _VLV_PCS_DW1_CH1		0x8404
1485 #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
1486 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
1487 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1488 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
1489 #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
1490 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1491 
1492 #define _VLV_PCS01_DW1_CH0		0x204
1493 #define _VLV_PCS23_DW1_CH0		0x404
1494 #define _VLV_PCS01_DW1_CH1		0x2604
1495 #define _VLV_PCS23_DW1_CH1		0x2804
1496 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1497 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1498 
1499 #define _VLV_PCS_DW8_CH0		0x8220
1500 #define _VLV_PCS_DW8_CH1		0x8420
1501 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
1502 #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
1503 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1504 
1505 #define _VLV_PCS01_DW8_CH0		0x0220
1506 #define _VLV_PCS23_DW8_CH0		0x0420
1507 #define _VLV_PCS01_DW8_CH1		0x2620
1508 #define _VLV_PCS23_DW8_CH1		0x2820
1509 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1510 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1511 
1512 #define _VLV_PCS_DW9_CH0		0x8224
1513 #define _VLV_PCS_DW9_CH1		0x8424
1514 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
1515 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
1516 #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
1517 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
1518 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
1519 #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
1520 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1521 
1522 #define _VLV_PCS01_DW9_CH0		0x224
1523 #define _VLV_PCS23_DW9_CH0		0x424
1524 #define _VLV_PCS01_DW9_CH1		0x2624
1525 #define _VLV_PCS23_DW9_CH1		0x2824
1526 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1527 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1528 
1529 #define _CHV_PCS_DW10_CH0		0x8228
1530 #define _CHV_PCS_DW10_CH1		0x8428
1531 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
1532 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
1533 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
1534 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
1535 #define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
1536 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
1537 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
1538 #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
1539 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1540 
1541 #define _VLV_PCS01_DW10_CH0		0x0228
1542 #define _VLV_PCS23_DW10_CH0		0x0428
1543 #define _VLV_PCS01_DW10_CH1		0x2628
1544 #define _VLV_PCS23_DW10_CH1		0x2828
1545 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1546 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1547 
1548 #define _VLV_PCS_DW11_CH0		0x822c
1549 #define _VLV_PCS_DW11_CH1		0x842c
1550 #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
1551 #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
1552 #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
1553 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
1554 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1555 
1556 #define _VLV_PCS01_DW11_CH0		0x022c
1557 #define _VLV_PCS23_DW11_CH0		0x042c
1558 #define _VLV_PCS01_DW11_CH1		0x262c
1559 #define _VLV_PCS23_DW11_CH1		0x282c
1560 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1561 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1562 
1563 #define _VLV_PCS01_DW12_CH0		0x0230
1564 #define _VLV_PCS23_DW12_CH0		0x0430
1565 #define _VLV_PCS01_DW12_CH1		0x2630
1566 #define _VLV_PCS23_DW12_CH1		0x2830
1567 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1568 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1569 
1570 #define _VLV_PCS_DW12_CH0		0x8230
1571 #define _VLV_PCS_DW12_CH1		0x8430
1572 #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
1573 #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
1574 #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
1575 #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
1576 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
1577 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1578 
1579 #define _VLV_PCS_DW14_CH0		0x8238
1580 #define _VLV_PCS_DW14_CH1		0x8438
1581 #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1582 
1583 #define _VLV_PCS_DW23_CH0		0x825c
1584 #define _VLV_PCS_DW23_CH1		0x845c
1585 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1586 
1587 #define _VLV_TX_DW2_CH0			0x8288
1588 #define _VLV_TX_DW2_CH1			0x8488
1589 #define   DPIO_SWING_MARGIN000_SHIFT	16
1590 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
1591 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
1592 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1593 
1594 #define _VLV_TX_DW3_CH0			0x828c
1595 #define _VLV_TX_DW3_CH1			0x848c
1596 /* The following bit for CHV phy */
1597 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
1598 #define   DPIO_SWING_MARGIN101_SHIFT	16
1599 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
1600 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1601 
1602 #define _VLV_TX_DW4_CH0			0x8290
1603 #define _VLV_TX_DW4_CH1			0x8490
1604 #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
1605 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1606 #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
1607 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1608 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1609 
1610 #define _VLV_TX3_DW4_CH0		0x690
1611 #define _VLV_TX3_DW4_CH1		0x2a90
1612 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1613 
1614 #define _VLV_TX_DW5_CH0			0x8294
1615 #define _VLV_TX_DW5_CH1			0x8494
1616 #define   DPIO_TX_OCALINIT_EN		(1 << 31)
1617 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1618 
1619 #define _VLV_TX_DW11_CH0		0x82ac
1620 #define _VLV_TX_DW11_CH1		0x84ac
1621 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1622 
1623 #define _VLV_TX_DW14_CH0		0x82b8
1624 #define _VLV_TX_DW14_CH1		0x84b8
1625 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1626 
1627 /* CHV dpPhy registers */
1628 #define _CHV_PLL_DW0_CH0		0x8000
1629 #define _CHV_PLL_DW0_CH1		0x8180
1630 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1631 
1632 #define _CHV_PLL_DW1_CH0		0x8004
1633 #define _CHV_PLL_DW1_CH1		0x8184
1634 #define   DPIO_CHV_N_DIV_SHIFT		8
1635 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1636 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1637 
1638 #define _CHV_PLL_DW2_CH0		0x8008
1639 #define _CHV_PLL_DW2_CH1		0x8188
1640 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1641 
1642 #define _CHV_PLL_DW3_CH0		0x800c
1643 #define _CHV_PLL_DW3_CH1		0x818c
1644 #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
1645 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
1646 #define  DPIO_CHV_SECOND_MOD		(1 << 8)
1647 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
1648 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
1649 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1650 
1651 #define _CHV_PLL_DW6_CH0		0x8018
1652 #define _CHV_PLL_DW6_CH1		0x8198
1653 #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
1654 #define	  DPIO_CHV_INT_COEFF_SHIFT	8
1655 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
1656 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1657 
1658 #define _CHV_PLL_DW8_CH0		0x8020
1659 #define _CHV_PLL_DW8_CH1		0x81A0
1660 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1661 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1662 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1663 
1664 #define _CHV_PLL_DW9_CH0		0x8024
1665 #define _CHV_PLL_DW9_CH1		0x81A4
1666 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
1667 #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
1668 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1669 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1670 
1671 #define _CHV_CMN_DW0_CH0               0x8100
1672 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
1673 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
1674 #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
1675 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1676 
1677 #define _CHV_CMN_DW5_CH0               0x8114
1678 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1679 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
1680 #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
1681 #define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
1682 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1683 #define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
1684 #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
1685 #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
1686 
1687 #define _CHV_CMN_DW13_CH0		0x8134
1688 #define _CHV_CMN_DW0_CH1		0x8080
1689 #define   DPIO_CHV_S1_DIV_SHIFT		21
1690 #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
1691 #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
1692 #define   DPIO_CHV_K_DIV_SHIFT		4
1693 #define   DPIO_PLL_FREQLOCK		(1 << 1)
1694 #define   DPIO_PLL_LOCK			(1 << 0)
1695 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1696 
1697 #define _CHV_CMN_DW14_CH0		0x8138
1698 #define _CHV_CMN_DW1_CH1		0x8084
1699 #define   DPIO_AFC_RECAL		(1 << 14)
1700 #define   DPIO_DCLKP_EN			(1 << 13)
1701 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1702 #define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
1703 #define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
1704 #define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
1705 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1706 #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
1707 #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
1708 #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
1709 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1710 
1711 #define _CHV_CMN_DW19_CH0		0x814c
1712 #define _CHV_CMN_DW6_CH1		0x8098
1713 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
1714 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
1715 #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
1716 #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
1717 
1718 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1719 
1720 #define CHV_CMN_DW28			0x8170
1721 #define   DPIO_CL1POWERDOWNEN		(1 << 23)
1722 #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
1723 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1724 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1725 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1726 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1727 
1728 #define CHV_CMN_DW30			0x8178
1729 #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
1730 #define   DPIO_LRC_BYPASS		(1 << 3)
1731 
1732 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1733 					(lane) * 0x200 + (offset))
1734 
1735 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1736 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1737 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1738 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1739 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1740 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1741 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1742 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1743 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1744 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1745 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1746 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1747 #define   DPIO_FRC_LATENCY_SHFIT	8
1748 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1749 #define   DPIO_UPAR_SHIFT		30
1750 
1751 /* BXT PHY registers */
1752 #define _BXT_PHY0_BASE			0x6C000
1753 #define _BXT_PHY1_BASE			0x162000
1754 #define _BXT_PHY2_BASE			0x163000
1755 #define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
1756 						     _BXT_PHY1_BASE, \
1757 						     _BXT_PHY2_BASE)
1758 
1759 #define _BXT_PHY(phy, reg)						\
1760 	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1761 
1762 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
1763 	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,	\
1764 					 (reg_ch1) - _BXT_PHY0_BASE))
1765 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
1766 	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1767 
1768 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
1769 #define  MIPIO_RST_CTRL				(1 << 2)
1770 
1771 #define _BXT_PHY_CTL_DDI_A		0x64C00
1772 #define _BXT_PHY_CTL_DDI_B		0x64C10
1773 #define _BXT_PHY_CTL_DDI_C		0x64C20
1774 #define   BXT_PHY_CMNLANE_POWERDOWN_ACK	(1 << 10)
1775 #define   BXT_PHY_LANE_POWERDOWN_ACK	(1 << 9)
1776 #define   BXT_PHY_LANE_ENABLED		(1 << 8)
1777 #define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1778 							 _BXT_PHY_CTL_DDI_B)
1779 
1780 #define _PHY_CTL_FAMILY_EDP		0x64C80
1781 #define _PHY_CTL_FAMILY_DDI		0x64C90
1782 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
1783 #define   COMMON_RESET_DIS		(1 << 31)
1784 #define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1785 							  _PHY_CTL_FAMILY_EDP, \
1786 							  _PHY_CTL_FAMILY_DDI_C)
1787 
1788 /* BXT PHY PLL registers */
1789 #define _PORT_PLL_A			0x46074
1790 #define _PORT_PLL_B			0x46078
1791 #define _PORT_PLL_C			0x4607c
1792 #define   PORT_PLL_ENABLE		(1 << 31)
1793 #define   PORT_PLL_LOCK			(1 << 30)
1794 #define   PORT_PLL_REF_SEL		(1 << 27)
1795 #define   PORT_PLL_POWER_ENABLE		(1 << 26)
1796 #define   PORT_PLL_POWER_STATE		(1 << 25)
1797 #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1798 
1799 #define _PORT_PLL_EBB_0_A		0x162034
1800 #define _PORT_PLL_EBB_0_B		0x6C034
1801 #define _PORT_PLL_EBB_0_C		0x6C340
1802 #define   PORT_PLL_P1_SHIFT		13
1803 #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1804 #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
1805 #define   PORT_PLL_P2_SHIFT		8
1806 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1807 #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
1808 #define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
1809 							 _PORT_PLL_EBB_0_B, \
1810 							 _PORT_PLL_EBB_0_C)
1811 
1812 #define _PORT_PLL_EBB_4_A		0x162038
1813 #define _PORT_PLL_EBB_4_B		0x6C038
1814 #define _PORT_PLL_EBB_4_C		0x6C344
1815 #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
1816 #define   PORT_PLL_RECALIBRATE		(1 << 14)
1817 #define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
1818 							 _PORT_PLL_EBB_4_B, \
1819 							 _PORT_PLL_EBB_4_C)
1820 
1821 #define _PORT_PLL_0_A			0x162100
1822 #define _PORT_PLL_0_B			0x6C100
1823 #define _PORT_PLL_0_C			0x6C380
1824 /* PORT_PLL_0_A */
1825 #define   PORT_PLL_M2_MASK		0xFF
1826 /* PORT_PLL_1_A */
1827 #define   PORT_PLL_N_SHIFT		8
1828 #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1829 #define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
1830 /* PORT_PLL_2_A */
1831 #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1832 /* PORT_PLL_3_A */
1833 #define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
1834 /* PORT_PLL_6_A */
1835 #define   PORT_PLL_PROP_COEFF_MASK	0xF
1836 #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1837 #define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
1838 #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1839 #define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
1840 /* PORT_PLL_8_A */
1841 #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1842 /* PORT_PLL_9_A */
1843 #define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
1844 #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1845 /* PORT_PLL_10_A */
1846 #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1 << 27)
1847 #define  PORT_PLL_DCO_AMP_DEFAULT	15
1848 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
1849 #define  PORT_PLL_DCO_AMP(x)		((x) << 10)
1850 #define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \
1851 						    _PORT_PLL_0_B, \
1852 						    _PORT_PLL_0_C)
1853 #define BXT_PORT_PLL(phy, ch, idx)	_MMIO(_PORT_PLL_BASE(phy, ch) + \
1854 					      (idx) * 4)
1855 
1856 /* BXT PHY common lane registers */
1857 #define _PORT_CL1CM_DW0_A		0x162000
1858 #define _PORT_CL1CM_DW0_BC		0x6C000
1859 #define   PHY_POWER_GOOD		(1 << 16)
1860 #define   PHY_RESERVED			(1 << 7)
1861 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1862 
1863 #define _PORT_CL1CM_DW9_A		0x162024
1864 #define _PORT_CL1CM_DW9_BC		0x6C024
1865 #define   IREF0RC_OFFSET_SHIFT		8
1866 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1867 #define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1868 
1869 #define _PORT_CL1CM_DW10_A		0x162028
1870 #define _PORT_CL1CM_DW10_BC		0x6C028
1871 #define   IREF1RC_OFFSET_SHIFT		8
1872 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1873 #define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1874 
1875 #define _PORT_CL1CM_DW28_A		0x162070
1876 #define _PORT_CL1CM_DW28_BC		0x6C070
1877 #define   OCL1_POWER_DOWN_EN		(1 << 23)
1878 #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
1879 #define   SUS_CLK_CONFIG		0x3
1880 #define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1881 
1882 #define _PORT_CL1CM_DW30_A		0x162078
1883 #define _PORT_CL1CM_DW30_BC		0x6C078
1884 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
1885 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1886 
1887 /*
1888  * ICL Port/COMBO-PHY Registers
1889  */
1890 #define _ICL_COMBOPHY_A			0x162000
1891 #define _ICL_COMBOPHY_B			0x6C000
1892 #define _EHL_COMBOPHY_C			0x160000
1893 #define _RKL_COMBOPHY_D			0x161000
1894 #define _ADL_COMBOPHY_E			0x16B000
1895 
1896 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
1897 					      _ICL_COMBOPHY_B, \
1898 					      _EHL_COMBOPHY_C, \
1899 					      _RKL_COMBOPHY_D, \
1900 					      _ADL_COMBOPHY_E)
1901 
1902 /* ICL Port CL_DW registers */
1903 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
1904 					 4 * (dw))
1905 
1906 #define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
1907 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
1908 #define   SUS_CLOCK_CONFIG		(3 << 0)
1909 
1910 #define ICL_PORT_CL_DW10(phy)		_MMIO(_ICL_PORT_CL_DW(10, phy))
1911 #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
1912 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
1913 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
1914 #define  PWR_UP_ALL_LANES		(0x0 << 4)
1915 #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
1916 #define  PWR_DOWN_LN_3_2		(0xc << 4)
1917 #define  PWR_DOWN_LN_3			(0x8 << 4)
1918 #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
1919 #define  PWR_DOWN_LN_1_0		(0x3 << 4)
1920 #define  PWR_DOWN_LN_3_1		(0xa << 4)
1921 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
1922 #define  PWR_DOWN_LN_MASK		(0xf << 4)
1923 #define  PWR_DOWN_LN_SHIFT		4
1924 #define  EDP4K2K_MODE_OVRD_EN		(1 << 3)
1925 #define  EDP4K2K_MODE_OVRD_OPTIMIZED	(1 << 2)
1926 
1927 #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
1928 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
1929 
1930 /* ICL Port COMP_DW registers */
1931 #define _ICL_PORT_COMP			0x100
1932 #define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
1933 					 _ICL_PORT_COMP + 4 * (dw))
1934 
1935 #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
1936 #define   COMP_INIT			(1 << 31)
1937 
1938 #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
1939 
1940 #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
1941 #define   PROCESS_INFO_DOT_0		(0 << 26)
1942 #define   PROCESS_INFO_DOT_1		(1 << 26)
1943 #define   PROCESS_INFO_DOT_4		(2 << 26)
1944 #define   PROCESS_INFO_MASK		(7 << 26)
1945 #define   PROCESS_INFO_SHIFT		26
1946 #define   VOLTAGE_INFO_0_85V		(0 << 24)
1947 #define   VOLTAGE_INFO_0_95V		(1 << 24)
1948 #define   VOLTAGE_INFO_1_05V		(2 << 24)
1949 #define   VOLTAGE_INFO_MASK		(3 << 24)
1950 #define   VOLTAGE_INFO_SHIFT		24
1951 
1952 #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
1953 #define   IREFGEN			(1 << 24)
1954 
1955 #define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
1956 
1957 #define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
1958 
1959 /* ICL Port PCS registers */
1960 #define _ICL_PORT_PCS_AUX		0x300
1961 #define _ICL_PORT_PCS_GRP		0x600
1962 #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
1963 #define _ICL_PORT_PCS_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
1964 					 _ICL_PORT_PCS_AUX + 4 * (dw))
1965 #define _ICL_PORT_PCS_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
1966 					 _ICL_PORT_PCS_GRP + 4 * (dw))
1967 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1968 					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1969 #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1970 #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1971 #define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1972 #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
1973 #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
1974 #define   COMMON_KEEPER_EN		(1 << 26)
1975 #define   LATENCY_OPTIM_MASK		(0x3 << 2)
1976 #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
1977 
1978 /* ICL Port TX registers */
1979 #define _ICL_PORT_TX_AUX		0x380
1980 #define _ICL_PORT_TX_GRP		0x680
1981 #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
1982 
1983 #define _ICL_PORT_TX_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
1984 					 _ICL_PORT_TX_AUX + 4 * (dw))
1985 #define _ICL_PORT_TX_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
1986 					 _ICL_PORT_TX_GRP + 4 * (dw))
1987 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1988 					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
1989 
1990 #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
1991 #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
1992 #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
1993 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
1994 #define   SWING_SEL_UPPER_MASK		(1 << 15)
1995 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
1996 #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
1997 #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
1998 #define   FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
1999 #define   RCOMP_SCALAR(x)		((x) << 0)
2000 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
2001 
2002 #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2003 #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
2004 #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
2005 #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
2006 #define   LOADGEN_SELECT		(1 << 31)
2007 #define   POST_CURSOR_1(x)		((x) << 12)
2008 #define   POST_CURSOR_1_MASK		(0x3F << 12)
2009 #define   POST_CURSOR_2(x)		((x) << 6)
2010 #define   POST_CURSOR_2_MASK		(0x3F << 6)
2011 #define   CURSOR_COEFF(x)		((x) << 0)
2012 #define   CURSOR_COEFF_MASK		(0x3F << 0)
2013 
2014 #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2015 #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
2016 #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
2017 #define   TX_TRAINING_EN		(1 << 31)
2018 #define   TAP2_DISABLE			(1 << 30)
2019 #define   TAP3_DISABLE			(1 << 29)
2020 #define   SCALING_MODE_SEL(x)		((x) << 18)
2021 #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
2022 #define   RTERM_SELECT(x)		((x) << 3)
2023 #define   RTERM_SELECT_MASK		(0x7 << 3)
2024 
2025 #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2026 #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
2027 #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
2028 #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
2029 #define   N_SCALAR(x)			((x) << 24)
2030 #define   N_SCALAR_MASK			(0x7F << 24)
2031 
2032 #define ICL_PORT_TX_DW8_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
2033 #define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
2034 #define ICL_PORT_TX_DW8_LN0(phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
2035 #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
2036 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
2037 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2038 
2039 #define _ICL_DPHY_CHKN_REG			0x194
2040 #define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2041 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
2042 
2043 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2044 	_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2045 
2046 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
2047 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
2048 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
2049 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
2050 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
2051 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
2052 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
2053 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
2054 #define MG_TX1_LINK_PARAMS(ln, tc_port) \
2055 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2056 				    MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2057 				    MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2058 
2059 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
2060 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
2061 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
2062 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
2063 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
2064 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
2065 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
2066 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
2067 #define MG_TX2_LINK_PARAMS(ln, tc_port) \
2068 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2069 				    MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2070 				    MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2071 #define   CRI_USE_FS32			(1 << 5)
2072 
2073 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
2074 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
2075 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
2076 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
2077 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
2078 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
2079 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
2080 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
2081 #define MG_TX1_PISO_READLOAD(ln, tc_port) \
2082 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2083 				    MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2084 				    MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2085 
2086 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
2087 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
2088 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
2089 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
2090 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
2091 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
2092 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
2093 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
2094 #define MG_TX2_PISO_READLOAD(ln, tc_port) \
2095 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2096 				    MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2097 				    MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2098 #define   CRI_CALCINIT					(1 << 1)
2099 
2100 #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
2101 #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
2102 #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
2103 #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
2104 #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
2105 #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
2106 #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
2107 #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
2108 #define MG_TX1_SWINGCTRL(ln, tc_port) \
2109 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2110 				    MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2111 				    MG_TX_SWINGCTRL_TX1LN1_PORT1)
2112 
2113 #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
2114 #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
2115 #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
2116 #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
2117 #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
2118 #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
2119 #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
2120 #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
2121 #define MG_TX2_SWINGCTRL(ln, tc_port) \
2122 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2123 				    MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2124 				    MG_TX_SWINGCTRL_TX2LN1_PORT1)
2125 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
2126 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
2127 
2128 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
2129 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
2130 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
2131 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
2132 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
2133 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
2134 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
2135 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
2136 #define MG_TX1_DRVCTRL(ln, tc_port) \
2137 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2138 				    MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2139 				    MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2140 
2141 #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
2142 #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
2143 #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
2144 #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
2145 #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
2146 #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
2147 #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
2148 #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
2149 #define MG_TX2_DRVCTRL(ln, tc_port) \
2150 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2151 				    MG_TX_DRVCTRL_TX2LN0_PORT2, \
2152 				    MG_TX_DRVCTRL_TX2LN1_PORT1)
2153 #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
2154 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
2155 #define   CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)
2156 #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
2157 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
2158 #define   CRI_LOADGEN_SEL(x)				((x) << 12)
2159 #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
2160 
2161 #define MG_CLKHUB_LN0_PORT1			0x16839C
2162 #define MG_CLKHUB_LN1_PORT1			0x16879C
2163 #define MG_CLKHUB_LN0_PORT2			0x16939C
2164 #define MG_CLKHUB_LN1_PORT2			0x16979C
2165 #define MG_CLKHUB_LN0_PORT3			0x16A39C
2166 #define MG_CLKHUB_LN1_PORT3			0x16A79C
2167 #define MG_CLKHUB_LN0_PORT4			0x16B39C
2168 #define MG_CLKHUB_LN1_PORT4			0x16B79C
2169 #define MG_CLKHUB(ln, tc_port) \
2170 	MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2171 				    MG_CLKHUB_LN0_PORT2, \
2172 				    MG_CLKHUB_LN1_PORT1)
2173 #define   CFG_LOW_RATE_LKREN_EN				(1 << 11)
2174 
2175 #define MG_TX_DCC_TX1LN0_PORT1			0x168110
2176 #define MG_TX_DCC_TX1LN1_PORT1			0x168510
2177 #define MG_TX_DCC_TX1LN0_PORT2			0x169110
2178 #define MG_TX_DCC_TX1LN1_PORT2			0x169510
2179 #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
2180 #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
2181 #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
2182 #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
2183 #define MG_TX1_DCC(ln, tc_port) \
2184 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2185 				    MG_TX_DCC_TX1LN0_PORT2, \
2186 				    MG_TX_DCC_TX1LN1_PORT1)
2187 #define MG_TX_DCC_TX2LN0_PORT1			0x168090
2188 #define MG_TX_DCC_TX2LN1_PORT1			0x168490
2189 #define MG_TX_DCC_TX2LN0_PORT2			0x169090
2190 #define MG_TX_DCC_TX2LN1_PORT2			0x169490
2191 #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
2192 #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
2193 #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
2194 #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
2195 #define MG_TX2_DCC(ln, tc_port) \
2196 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2197 				    MG_TX_DCC_TX2LN0_PORT2, \
2198 				    MG_TX_DCC_TX2LN1_PORT1)
2199 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)	((x) << 25)
2200 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
2201 #define   CFG_AMI_CK_DIV_OVERRIDE_EN		(1 << 24)
2202 
2203 #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
2204 #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
2205 #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
2206 #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
2207 #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
2208 #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
2209 #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
2210 #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
2211 #define MG_DP_MODE(ln, tc_port)	\
2212 	MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2213 				    MG_DP_MODE_LN0_ACU_PORT2, \
2214 				    MG_DP_MODE_LN1_ACU_PORT1)
2215 #define   MG_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
2216 #define   MG_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
2217 
2218 /*
2219  * DG2 SNPS PHY registers (TC1 = PHY_E)
2220  */
2221 #define _SNPS_PHY_A_BASE			0x168000
2222 #define _SNPS_PHY_B_BASE			0x169000
2223 #define _SNPS_PHY(phy)				_PHY(phy, \
2224 						     _SNPS_PHY_A_BASE, \
2225 						     _SNPS_PHY_B_BASE)
2226 #define _SNPS2(phy, reg)			(_SNPS_PHY(phy) - \
2227 						 _SNPS_PHY_A_BASE + (reg))
2228 #define _MMIO_SNPS(phy, reg)			_MMIO(_SNPS2(phy, reg))
2229 #define _MMIO_SNPS_LN(ln, phy, reg)		_MMIO(_SNPS2(phy, \
2230 							     (reg) + (ln) * 0x10))
2231 
2232 #define SNPS_PHY_MPLLB_CP(phy)			_MMIO_SNPS(phy, 0x168000)
2233 #define   SNPS_PHY_MPLLB_CP_INT			REG_GENMASK(31, 25)
2234 #define   SNPS_PHY_MPLLB_CP_INT_GS		REG_GENMASK(23, 17)
2235 #define   SNPS_PHY_MPLLB_CP_PROP		REG_GENMASK(15, 9)
2236 #define   SNPS_PHY_MPLLB_CP_PROP_GS		REG_GENMASK(7, 1)
2237 
2238 #define SNPS_PHY_MPLLB_DIV(phy)			_MMIO_SNPS(phy, 0x168004)
2239 #define   SNPS_PHY_MPLLB_FORCE_EN		REG_BIT(31)
2240 #define   SNPS_PHY_MPLLB_DIV5_CLK_EN		REG_BIT(29)
2241 #define   SNPS_PHY_MPLLB_V2I			REG_GENMASK(27, 26)
2242 #define   SNPS_PHY_MPLLB_FREQ_VCO		REG_GENMASK(25, 24)
2243 #define   SNPS_PHY_MPLLB_PMIX_EN		REG_BIT(10)
2244 #define   SNPS_PHY_MPLLB_TX_CLK_DIV		REG_GENMASK(7, 5)
2245 
2246 #define SNPS_PHY_MPLLB_FRACN1(phy)		_MMIO_SNPS(phy, 0x168008)
2247 #define   SNPS_PHY_MPLLB_FRACN_EN		REG_BIT(31)
2248 #define   SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN	REG_BIT(30)
2249 #define   SNPS_PHY_MPLLB_FRACN_DEN		REG_GENMASK(15, 0)
2250 
2251 #define SNPS_PHY_MPLLB_FRACN2(phy)		_MMIO_SNPS(phy, 0x16800C)
2252 #define   SNPS_PHY_MPLLB_FRACN_REM		REG_GENMASK(31, 16)
2253 #define   SNPS_PHY_MPLLB_FRACN_QUOT		REG_GENMASK(15, 0)
2254 
2255 #define SNPS_PHY_MPLLB_SSCEN(phy)		_MMIO_SNPS(phy, 0x168014)
2256 #define   SNPS_PHY_MPLLB_SSC_EN			REG_BIT(31)
2257 #define   SNPS_PHY_MPLLB_SSC_UP_SPREAD		REG_BIT(30)
2258 #define   SNPS_PHY_MPLLB_SSC_PEAK		REG_GENMASK(29, 10)
2259 
2260 #define SNPS_PHY_MPLLB_SSCSTEP(phy)		_MMIO_SNPS(phy, 0x168018)
2261 #define   SNPS_PHY_MPLLB_SSC_STEPSIZE		REG_GENMASK(31, 11)
2262 
2263 #define SNPS_PHY_MPLLB_DIV2(phy)		_MMIO_SNPS(phy, 0x16801C)
2264 #define   SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV	REG_GENMASK(19, 18)
2265 #define   SNPS_PHY_MPLLB_HDMI_DIV		REG_GENMASK(17, 15)
2266 #define   SNPS_PHY_MPLLB_REF_CLK_DIV		REG_GENMASK(14, 12)
2267 #define   SNPS_PHY_MPLLB_MULTIPLIER		REG_GENMASK(11, 0)
2268 
2269 #define SNPS_PHY_REF_CONTROL(phy)		_MMIO_SNPS(phy, 0x168188)
2270 #define   SNPS_PHY_REF_CONTROL_REF_RANGE	REG_GENMASK(31, 27)
2271 
2272 #define SNPS_PHY_TX_REQ(phy)			_MMIO_SNPS(phy, 0x168200)
2273 #define   SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR	REG_GENMASK(31, 30)
2274 
2275 #define SNPS_PHY_TX_EQ(ln, phy)			_MMIO_SNPS_LN(ln, phy, 0x168300)
2276 #define   SNPS_PHY_TX_EQ_MAIN			REG_GENMASK(23, 18)
2277 #define   SNPS_PHY_TX_EQ_POST			REG_GENMASK(15, 10)
2278 #define   SNPS_PHY_TX_EQ_PRE			REG_GENMASK(7, 2)
2279 
2280 /* The spec defines this only for BXT PHY0, but lets assume that this
2281  * would exist for PHY1 too if it had a second channel.
2282  */
2283 #define _PORT_CL2CM_DW6_A		0x162358
2284 #define _PORT_CL2CM_DW6_BC		0x6C358
2285 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2286 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
2287 
2288 #define FIA1_BASE			0x163000
2289 #define FIA2_BASE			0x16E000
2290 #define FIA3_BASE			0x16F000
2291 #define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2292 #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
2293 
2294 /* ICL PHY DFLEX registers */
2295 #define PORT_TX_DFLEXDPMLE1(fia)		_MMIO_FIA((fia),  0x008C0)
2296 #define   DFLEXDPMLE1_DPMLETC_MASK(idx)		(0xf << (4 * (idx)))
2297 #define   DFLEXDPMLE1_DPMLETC_ML0(idx)		(1 << (4 * (idx)))
2298 #define   DFLEXDPMLE1_DPMLETC_ML1_0(idx)	(3 << (4 * (idx)))
2299 #define   DFLEXDPMLE1_DPMLETC_ML3(idx)		(8 << (4 * (idx)))
2300 #define   DFLEXDPMLE1_DPMLETC_ML3_2(idx)	(12 << (4 * (idx)))
2301 #define   DFLEXDPMLE1_DPMLETC_ML3_0(idx)	(15 << (4 * (idx)))
2302 
2303 /* BXT PHY Ref registers */
2304 #define _PORT_REF_DW3_A			0x16218C
2305 #define _PORT_REF_DW3_BC		0x6C18C
2306 #define   GRC_DONE			(1 << 22)
2307 #define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC)
2308 
2309 #define _PORT_REF_DW6_A			0x162198
2310 #define _PORT_REF_DW6_BC		0x6C198
2311 #define   GRC_CODE_SHIFT		24
2312 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
2313 #define   GRC_CODE_FAST_SHIFT		16
2314 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
2315 #define   GRC_CODE_SLOW_SHIFT		8
2316 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
2317 #define   GRC_CODE_NOM_MASK		0xFF
2318 #define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC)
2319 
2320 #define _PORT_REF_DW8_A			0x1621A0
2321 #define _PORT_REF_DW8_BC		0x6C1A0
2322 #define   GRC_DIS			(1 << 15)
2323 #define   GRC_RDY_OVRD			(1 << 1)
2324 #define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC)
2325 
2326 /* BXT PHY PCS registers */
2327 #define _PORT_PCS_DW10_LN01_A		0x162428
2328 #define _PORT_PCS_DW10_LN01_B		0x6C428
2329 #define _PORT_PCS_DW10_LN01_C		0x6C828
2330 #define _PORT_PCS_DW10_GRP_A		0x162C28
2331 #define _PORT_PCS_DW10_GRP_B		0x6CC28
2332 #define _PORT_PCS_DW10_GRP_C		0x6CE28
2333 #define BXT_PORT_PCS_DW10_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2334 							 _PORT_PCS_DW10_LN01_B, \
2335 							 _PORT_PCS_DW10_LN01_C)
2336 #define BXT_PORT_PCS_DW10_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2337 							 _PORT_PCS_DW10_GRP_B, \
2338 							 _PORT_PCS_DW10_GRP_C)
2339 
2340 #define   TX2_SWING_CALC_INIT		(1 << 31)
2341 #define   TX1_SWING_CALC_INIT		(1 << 30)
2342 
2343 #define _PORT_PCS_DW12_LN01_A		0x162430
2344 #define _PORT_PCS_DW12_LN01_B		0x6C430
2345 #define _PORT_PCS_DW12_LN01_C		0x6C830
2346 #define _PORT_PCS_DW12_LN23_A		0x162630
2347 #define _PORT_PCS_DW12_LN23_B		0x6C630
2348 #define _PORT_PCS_DW12_LN23_C		0x6CA30
2349 #define _PORT_PCS_DW12_GRP_A		0x162c30
2350 #define _PORT_PCS_DW12_GRP_B		0x6CC30
2351 #define _PORT_PCS_DW12_GRP_C		0x6CE30
2352 #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
2353 #define   LANE_STAGGER_MASK		0x1F
2354 #define BXT_PORT_PCS_DW12_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2355 							 _PORT_PCS_DW12_LN01_B, \
2356 							 _PORT_PCS_DW12_LN01_C)
2357 #define BXT_PORT_PCS_DW12_LN23(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2358 							 _PORT_PCS_DW12_LN23_B, \
2359 							 _PORT_PCS_DW12_LN23_C)
2360 #define BXT_PORT_PCS_DW12_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2361 							 _PORT_PCS_DW12_GRP_B, \
2362 							 _PORT_PCS_DW12_GRP_C)
2363 
2364 /* BXT PHY TX registers */
2365 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
2366 					  ((lane) & 1) * 0x80)
2367 
2368 #define _PORT_TX_DW2_LN0_A		0x162508
2369 #define _PORT_TX_DW2_LN0_B		0x6C508
2370 #define _PORT_TX_DW2_LN0_C		0x6C908
2371 #define _PORT_TX_DW2_GRP_A		0x162D08
2372 #define _PORT_TX_DW2_GRP_B		0x6CD08
2373 #define _PORT_TX_DW2_GRP_C		0x6CF08
2374 #define BXT_PORT_TX_DW2_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2375 							 _PORT_TX_DW2_LN0_B, \
2376 							 _PORT_TX_DW2_LN0_C)
2377 #define BXT_PORT_TX_DW2_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2378 							 _PORT_TX_DW2_GRP_B, \
2379 							 _PORT_TX_DW2_GRP_C)
2380 #define   MARGIN_000_SHIFT		16
2381 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
2382 #define   UNIQ_TRANS_SCALE_SHIFT	8
2383 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
2384 
2385 #define _PORT_TX_DW3_LN0_A		0x16250C
2386 #define _PORT_TX_DW3_LN0_B		0x6C50C
2387 #define _PORT_TX_DW3_LN0_C		0x6C90C
2388 #define _PORT_TX_DW3_GRP_A		0x162D0C
2389 #define _PORT_TX_DW3_GRP_B		0x6CD0C
2390 #define _PORT_TX_DW3_GRP_C		0x6CF0C
2391 #define BXT_PORT_TX_DW3_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2392 							 _PORT_TX_DW3_LN0_B, \
2393 							 _PORT_TX_DW3_LN0_C)
2394 #define BXT_PORT_TX_DW3_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2395 							 _PORT_TX_DW3_GRP_B, \
2396 							 _PORT_TX_DW3_GRP_C)
2397 #define   SCALE_DCOMP_METHOD		(1 << 26)
2398 #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
2399 
2400 #define _PORT_TX_DW4_LN0_A		0x162510
2401 #define _PORT_TX_DW4_LN0_B		0x6C510
2402 #define _PORT_TX_DW4_LN0_C		0x6C910
2403 #define _PORT_TX_DW4_GRP_A		0x162D10
2404 #define _PORT_TX_DW4_GRP_B		0x6CD10
2405 #define _PORT_TX_DW4_GRP_C		0x6CF10
2406 #define BXT_PORT_TX_DW4_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2407 							 _PORT_TX_DW4_LN0_B, \
2408 							 _PORT_TX_DW4_LN0_C)
2409 #define BXT_PORT_TX_DW4_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2410 							 _PORT_TX_DW4_GRP_B, \
2411 							 _PORT_TX_DW4_GRP_C)
2412 #define   DEEMPH_SHIFT			24
2413 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
2414 
2415 #define _PORT_TX_DW5_LN0_A		0x162514
2416 #define _PORT_TX_DW5_LN0_B		0x6C514
2417 #define _PORT_TX_DW5_LN0_C		0x6C914
2418 #define _PORT_TX_DW5_GRP_A		0x162D14
2419 #define _PORT_TX_DW5_GRP_B		0x6CD14
2420 #define _PORT_TX_DW5_GRP_C		0x6CF14
2421 #define BXT_PORT_TX_DW5_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2422 							 _PORT_TX_DW5_LN0_B, \
2423 							 _PORT_TX_DW5_LN0_C)
2424 #define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2425 							 _PORT_TX_DW5_GRP_B, \
2426 							 _PORT_TX_DW5_GRP_C)
2427 #define   DCC_DELAY_RANGE_1		(1 << 9)
2428 #define   DCC_DELAY_RANGE_2		(1 << 8)
2429 
2430 #define _PORT_TX_DW14_LN0_A		0x162538
2431 #define _PORT_TX_DW14_LN0_B		0x6C538
2432 #define _PORT_TX_DW14_LN0_C		0x6C938
2433 #define   LATENCY_OPTIM_SHIFT		30
2434 #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
2435 #define BXT_PORT_TX_DW14_LN(phy, ch, lane)				\
2436 	_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,			\
2437 				   _PORT_TX_DW14_LN0_C) +		\
2438 	      _BXT_LANE_OFFSET(lane))
2439 
2440 /* UAIMI scratch pad register 1 */
2441 #define UAIMI_SPR1			_MMIO(0x4F074)
2442 /* SKL VccIO mask */
2443 #define SKL_VCCIO_MASK			0x1
2444 /* SKL balance leg register */
2445 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
2446 /* I_boost values */
2447 #define BALANCE_LEG_SHIFT(port)		(8 + 3 * (port))
2448 #define BALANCE_LEG_MASK(port)		(7 << (8 + 3 * (port)))
2449 /* Balance leg disable bits */
2450 #define BALANCE_LEG_DISABLE_SHIFT	23
2451 #define BALANCE_LEG_DISABLE(port)	(1 << (23 + (port)))
2452 
2453 /*
2454  * Fence registers
2455  * [0-7]  @ 0x2000 gen2,gen3
2456  * [8-15] @ 0x3000 945,g33,pnv
2457  *
2458  * [0-15] @ 0x3000 gen4,gen5
2459  *
2460  * [0-15] @ 0x100000 gen6,vlv,chv
2461  * [0-31] @ 0x100000 gen7+
2462  */
2463 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2464 #define   I830_FENCE_START_MASK		0x07f80000
2465 #define   I830_FENCE_TILING_Y_SHIFT	12
2466 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
2467 #define   I830_FENCE_PITCH_SHIFT	4
2468 #define   I830_FENCE_REG_VALID		(1 << 0)
2469 #define   I915_FENCE_MAX_PITCH_VAL	4
2470 #define   I830_FENCE_MAX_PITCH_VAL	6
2471 #define   I830_FENCE_MAX_SIZE_VAL	(1 << 8)
2472 
2473 #define   I915_FENCE_START_MASK		0x0ff00000
2474 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
2475 
2476 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
2477 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
2478 #define   I965_FENCE_PITCH_SHIFT	2
2479 #define   I965_FENCE_TILING_Y_SHIFT	1
2480 #define   I965_FENCE_REG_VALID		(1 << 0)
2481 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
2482 
2483 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
2484 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
2485 #define   GEN6_FENCE_PITCH_SHIFT	32
2486 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2487 
2488 
2489 /* control register for cpu gtt access */
2490 #define TILECTL				_MMIO(0x101000)
2491 #define   TILECTL_SWZCTL			(1 << 0)
2492 #define   TILECTL_TLBPF			(1 << 1)
2493 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
2494 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
2495 
2496 /*
2497  * Instruction and interrupt control regs
2498  */
2499 #define PGTBL_CTL	_MMIO(0x02020)
2500 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
2501 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
2502 #define PGTBL_ER	_MMIO(0x02024)
2503 #define PRB0_BASE	(0x2030 - 0x30)
2504 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
2505 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
2506 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
2507 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
2508 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
2509 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
2510 #define RENDER_RING_BASE	0x02000
2511 #define BSD_RING_BASE		0x04000
2512 #define GEN6_BSD_RING_BASE	0x12000
2513 #define GEN8_BSD2_RING_BASE	0x1c000
2514 #define GEN11_BSD_RING_BASE	0x1c0000
2515 #define GEN11_BSD2_RING_BASE	0x1c4000
2516 #define GEN11_BSD3_RING_BASE	0x1d0000
2517 #define GEN11_BSD4_RING_BASE	0x1d4000
2518 #define XEHP_BSD5_RING_BASE	0x1e0000
2519 #define XEHP_BSD6_RING_BASE	0x1e4000
2520 #define XEHP_BSD7_RING_BASE	0x1f0000
2521 #define XEHP_BSD8_RING_BASE	0x1f4000
2522 #define VEBOX_RING_BASE		0x1a000
2523 #define GEN11_VEBOX_RING_BASE		0x1c8000
2524 #define GEN11_VEBOX2_RING_BASE		0x1d8000
2525 #define XEHP_VEBOX3_RING_BASE		0x1e8000
2526 #define XEHP_VEBOX4_RING_BASE		0x1f8000
2527 #define BLT_RING_BASE		0x22000
2528 #define RING_TAIL(base)		_MMIO((base) + 0x30)
2529 #define RING_HEAD(base)		_MMIO((base) + 0x34)
2530 #define RING_START(base)	_MMIO((base) + 0x38)
2531 #define RING_CTL(base)		_MMIO((base) + 0x3c)
2532 #define   RING_CTL_SIZE(size)	((size) - PAGE_SIZE) /* in bytes -> pages */
2533 #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
2534 #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
2535 #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
2536 #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
2537 #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
2538 #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
2539 #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
2540 #define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
2541 #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
2542 #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
2543 #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
2544 #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
2545 #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
2546 #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
2547 #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
2548 #define GEN6_NOSYNC	INVALID_MMIO_REG
2549 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
2550 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
2551 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
2552 #define RING_ID(base)		_MMIO((base) + 0x8c)
2553 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
2554 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
2555 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
2556 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
2557 #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
2558 
2559 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2560 
2561 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
2562 #define   GTT_CACHE_EN_ALL	0xF0007FFF
2563 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
2564 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
2565 #define ARB_MODE		_MMIO(0x4030)
2566 #define   ARB_MODE_SWIZZLE_SNB	(1 << 4)
2567 #define   ARB_MODE_SWIZZLE_IVB	(1 << 5)
2568 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
2569 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
2570 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2571 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
2572 #define GEN7_LRA_LIMITS_REG_NUM	13
2573 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
2574 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
2575 
2576 #define GAMTARBMODE		_MMIO(0x04a08)
2577 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
2578 #define   ARB_MODE_SWIZZLE_BDW	(1 << 1)
2579 #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
2580 
2581 #define _RING_FAULT_REG_RCS        0x4094
2582 #define _RING_FAULT_REG_VCS        0x4194
2583 #define _RING_FAULT_REG_BCS        0x4294
2584 #define _RING_FAULT_REG_VECS       0x4394
2585 #define RING_FAULT_REG(engine)     _MMIO(_PICK((engine)->class, \
2586 					       _RING_FAULT_REG_RCS, \
2587 					       _RING_FAULT_REG_VCS, \
2588 					       _RING_FAULT_REG_VECS, \
2589 					       _RING_FAULT_REG_BCS))
2590 #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
2591 #define GEN12_RING_FAULT_REG	_MMIO(0xcec4)
2592 #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
2593 #define   RING_FAULT_GTTSEL_MASK (1 << 11)
2594 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
2595 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2596 #define   RING_FAULT_VALID	(1 << 0)
2597 #define DONE_REG		_MMIO(0x40b0)
2598 #define GEN12_GAM_DONE		_MMIO(0xcf68)
2599 #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
2600 #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
2601 #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
2602 #define GEN12_PAT_INDEX(index)	_MMIO(0x4800 + (index) * 4)
2603 #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
2604 #define GEN12_GFX_CCS_AUX_NV	_MMIO(0x4208)
2605 #define GEN12_VD0_AUX_NV	_MMIO(0x4218)
2606 #define GEN12_VD1_AUX_NV	_MMIO(0x4228)
2607 #define GEN12_VD2_AUX_NV	_MMIO(0x4298)
2608 #define GEN12_VD3_AUX_NV	_MMIO(0x42A8)
2609 #define GEN12_VE0_AUX_NV	_MMIO(0x4238)
2610 #define GEN12_VE1_AUX_NV	_MMIO(0x42B8)
2611 #define   AUX_INV		REG_BIT(0)
2612 #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
2613 #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
2614 #define RING_ACTHD(base)	_MMIO((base) + 0x74)
2615 #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
2616 #define RING_NOPID(base)	_MMIO((base) + 0x94)
2617 #define RING_IMR(base)		_MMIO((base) + 0xa8)
2618 #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
2619 #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
2620 #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
2621 #define   TAIL_ADDR		0x001FFFF8
2622 #define   HEAD_WRAP_COUNT	0xFFE00000
2623 #define   HEAD_WRAP_ONE		0x00200000
2624 #define   HEAD_ADDR		0x001FFFFC
2625 #define   RING_NR_PAGES		0x001FF000
2626 #define   RING_REPORT_MASK	0x00000006
2627 #define   RING_REPORT_64K	0x00000002
2628 #define   RING_REPORT_128K	0x00000004
2629 #define   RING_NO_REPORT	0x00000000
2630 #define   RING_VALID_MASK	0x00000001
2631 #define   RING_VALID		0x00000001
2632 #define   RING_INVALID		0x00000000
2633 #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
2634 #define   RING_WAIT		(1 << 11) /* gen3+, PRBx_CTL */
2635 #define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */
2636 
2637 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2638 #define GEN8_RING_CS_GPR(base, n)	_MMIO((base) + 0x600 + (n) * 8)
2639 #define GEN8_RING_CS_GPR_UDW(base, n)	_MMIO((base) + 0x600 + (n) * 8 + 4)
2640 
2641 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2642 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)
2643 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
2644 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)
2645 #define   RING_FORCE_TO_NONPRIV_ACCESS_WR	(2 << 28)
2646 #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID	(3 << 28)
2647 #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	(3 << 28)
2648 #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
2649 #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
2650 #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
2651 #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
2652 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
2653 #define   RING_FORCE_TO_NONPRIV_MASK_VALID	\
2654 					(RING_FORCE_TO_NONPRIV_RANGE_MASK \
2655 					| RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2656 #define   RING_MAX_NONPRIV_SLOTS  12
2657 
2658 #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
2659 
2660 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2661 #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1 << 18)
2662 
2663 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2664 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2665 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
2666 
2667 #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
2668 #define   GAMT_CHKN_DISABLE_L3_COH_PIPE			(1 << 31)
2669 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1 << 28)
2670 #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1 << 24)
2671 
2672 #if 0
2673 #define PRB0_TAIL	_MMIO(0x2030)
2674 #define PRB0_HEAD	_MMIO(0x2034)
2675 #define PRB0_START	_MMIO(0x2038)
2676 #define PRB0_CTL	_MMIO(0x203c)
2677 #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
2678 #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
2679 #define PRB1_START	_MMIO(0x2048) /* 915+ only */
2680 #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
2681 #endif
2682 #define IPEIR_I965	_MMIO(0x2064)
2683 #define IPEHR_I965	_MMIO(0x2068)
2684 #define GEN7_SC_INSTDONE	_MMIO(0x7100)
2685 #define GEN12_SC_INSTDONE_EXTRA		_MMIO(0x7104)
2686 #define GEN12_SC_INSTDONE_EXTRA2	_MMIO(0x7108)
2687 #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
2688 #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
2689 #define MCFG_MCR_SELECTOR		_MMIO(0xfd0)
2690 #define SF_MCR_SELECTOR			_MMIO(0xfd8)
2691 #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
2692 #define   GEN8_MCR_SLICE(slice)		(((slice) & 3) << 26)
2693 #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
2694 #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
2695 #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
2696 #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
2697 #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
2698 #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
2699 #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
2700 #define RING_IPEIR(base)	_MMIO((base) + 0x64)
2701 #define RING_IPEHR(base)	_MMIO((base) + 0x68)
2702 #define RING_EIR(base)		_MMIO((base) + 0xb0)
2703 #define RING_EMR(base)		_MMIO((base) + 0xb4)
2704 #define RING_ESR(base)		_MMIO((base) + 0xb8)
2705 /*
2706  * On GEN4, only the render ring INSTDONE exists and has a different
2707  * layout than the GEN7+ version.
2708  * The GEN2 counterpart of this register is GEN2_INSTDONE.
2709  */
2710 #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
2711 #define RING_INSTPS(base)	_MMIO((base) + 0x70)
2712 #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
2713 #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
2714 #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
2715 #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
2716 #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2717 #define INSTPS		_MMIO(0x2070) /* 965+ only */
2718 #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2719 #define ACTHD_I965	_MMIO(0x2074)
2720 #define HWS_PGA		_MMIO(0x2080)
2721 #define HWS_ADDRESS_MASK	0xfffff000
2722 #define HWS_START_ADDRESS_SHIFT	4
2723 #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
2724 #define   PWRCTX_EN	(1 << 0)
2725 #define IPEIR(base)	_MMIO((base) + 0x88)
2726 #define IPEHR(base)	_MMIO((base) + 0x8c)
2727 #define GEN2_INSTDONE	_MMIO(0x2090)
2728 #define NOPID		_MMIO(0x2094)
2729 #define HWSTAM		_MMIO(0x2098)
2730 #define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)
2731 #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
2732 #define   RING_BB_PPGTT		(1 << 5)
2733 #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
2734 #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
2735 #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
2736 #define RING_BBADDR(base)	_MMIO((base) + 0x140)
2737 #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
2738 #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
2739 #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
2740 #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
2741 #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
2742 
2743 #define VDBOX_CGCTL3F10(base)		_MMIO((base) + 0x3f10)
2744 #define   IECPUNIT_CLKGATE_DIS		REG_BIT(22)
2745 
2746 #define ERROR_GEN6	_MMIO(0x40a0)
2747 #define GEN7_ERR_INT	_MMIO(0x44040)
2748 #define   ERR_INT_POISON		(1 << 31)
2749 #define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
2750 #define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
2751 #define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
2752 #define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
2753 #define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
2754 #define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
2755 #define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
2756 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
2757 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
2758 
2759 #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
2760 #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
2761 #define GEN12_FAULT_TLB_DATA0		_MMIO(0xceb8)
2762 #define GEN12_FAULT_TLB_DATA1		_MMIO(0xcebc)
2763 #define   FAULT_VA_HIGH_BITS		(0xf << 0)
2764 #define   FAULT_GTT_SEL			(1 << 4)
2765 
2766 #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
2767 
2768 #define FPGA_DBG		_MMIO(0x42300)
2769 #define   FPGA_DBG_RM_NOCLAIM	(1 << 31)
2770 
2771 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
2772 #define   CLAIM_ER_CLR		(1 << 31)
2773 #define   CLAIM_ER_OVERFLOW	(1 << 16)
2774 #define   CLAIM_ER_CTR_MASK	0xffff
2775 
2776 #define DERRMR		_MMIO(0x44050)
2777 /* Note that HBLANK events are reserved on bdw+ */
2778 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
2779 #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1 << 1)
2780 #define   DERRMR_PIPEA_SPR_FLIP_DONE	(1 << 2)
2781 #define   DERRMR_PIPEA_VBLANK		(1 << 3)
2782 #define   DERRMR_PIPEA_HBLANK		(1 << 5)
2783 #define   DERRMR_PIPEB_SCANLINE		(1 << 8)
2784 #define   DERRMR_PIPEB_PRI_FLIP_DONE	(1 << 9)
2785 #define   DERRMR_PIPEB_SPR_FLIP_DONE	(1 << 10)
2786 #define   DERRMR_PIPEB_VBLANK		(1 << 11)
2787 #define   DERRMR_PIPEB_HBLANK		(1 << 13)
2788 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2789 #define   DERRMR_PIPEC_SCANLINE		(1 << 14)
2790 #define   DERRMR_PIPEC_PRI_FLIP_DONE	(1 << 15)
2791 #define   DERRMR_PIPEC_SPR_FLIP_DONE	(1 << 20)
2792 #define   DERRMR_PIPEC_VBLANK		(1 << 21)
2793 #define   DERRMR_PIPEC_HBLANK		(1 << 22)
2794 
2795 
2796 /* GM45+ chicken bits -- debug workaround bits that may be required
2797  * for various sorts of correct behavior.  The top 16 bits of each are
2798  * the enables for writing to the corresponding low bit.
2799  */
2800 #define _3D_CHICKEN	_MMIO(0x2084)
2801 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
2802 #define _3D_CHICKEN2	_MMIO(0x208c)
2803 
2804 #define FF_SLICE_CHICKEN	_MMIO(0x2088)
2805 #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX	(1 << 1)
2806 
2807 /* Disables pipelining of read flushes past the SF-WIZ interface.
2808  * Required on all Ironlake steppings according to the B-Spec, but the
2809  * particular danger of not doing so is not specified.
2810  */
2811 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
2812 #define _3D_CHICKEN3	_MMIO(0x2090)
2813 #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX		(1 << 12)
2814 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
2815 #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
2816 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
2817 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x) << 1) /* gen8+ */
2818 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
2819 
2820 #define MI_MODE		_MMIO(0x209c)
2821 # define VS_TIMER_DISPATCH				(1 << 6)
2822 # define MI_FLUSH_ENABLE				(1 << 12)
2823 # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
2824 # define MODE_IDLE					(1 << 9)
2825 # define STOP_RING					(1 << 8)
2826 
2827 #define GEN6_GT_MODE	_MMIO(0x20d0)
2828 #define GEN7_GT_MODE	_MMIO(0x7008)
2829 #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
2830 #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
2831 #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
2832 #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
2833 #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
2834 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
2835 #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
2836 #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
2837 
2838 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2839 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2840 #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2841 #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2842 
2843 /* WaClearTdlStateAckDirtyBits */
2844 #define GEN8_STATE_ACK		_MMIO(0x20F0)
2845 #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
2846 #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
2847 #define   GEN9_STATE_ACK_TDL0 (1 << 12)
2848 #define   GEN9_STATE_ACK_TDL1 (1 << 13)
2849 #define   GEN9_STATE_ACK_TDL2 (1 << 14)
2850 #define   GEN9_STATE_ACK_TDL3 (1 << 15)
2851 #define   GEN9_SUBSLICE_TDL_ACK_BITS \
2852 	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2853 	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2854 
2855 #define GFX_MODE	_MMIO(0x2520)
2856 #define GFX_MODE_GEN7	_MMIO(0x229c)
2857 #define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
2858 #define   GFX_RUN_LIST_ENABLE		(1 << 15)
2859 #define   GFX_INTERRUPT_STEERING	(1 << 14)
2860 #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
2861 #define   GFX_SURFACE_FAULT_ENABLE	(1 << 12)
2862 #define   GFX_REPLAY_MODE		(1 << 11)
2863 #define   GFX_PSMI_GRANULARITY		(1 << 10)
2864 #define   GFX_PPGTT_ENABLE		(1 << 9)
2865 #define   GEN8_GFX_PPGTT_48B		(1 << 7)
2866 
2867 #define   GFX_FORWARD_VBLANK_MASK	(3 << 5)
2868 #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
2869 #define   GFX_FORWARD_VBLANK_ALWAYS	(1 << 5)
2870 #define   GFX_FORWARD_VBLANK_COND	(2 << 5)
2871 
2872 #define   GEN11_GFX_DISABLE_LEGACY_MODE	(1 << 3)
2873 
2874 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
2875 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
2876 #define SCPD0		_MMIO(0x209c) /* 915+ only */
2877 #define  SCPD_FBC_IGNORE_3D			(1 << 6)
2878 #define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
2879 #define GEN2_IER	_MMIO(0x20a0)
2880 #define GEN2_IIR	_MMIO(0x20a4)
2881 #define GEN2_IMR	_MMIO(0x20a8)
2882 #define GEN2_ISR	_MMIO(0x20ac)
2883 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
2884 #define   GINT_DIS		(1 << 22)
2885 #define   GCFG_DIS		(1 << 8)
2886 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
2887 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
2888 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
2889 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
2890 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
2891 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
2892 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
2893 #define VLV_PCBR_ADDR_SHIFT	12
2894 
2895 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2896 #define EIR		_MMIO(0x20b0)
2897 #define EMR		_MMIO(0x20b4)
2898 #define ESR		_MMIO(0x20b8)
2899 #define   GM45_ERROR_PAGE_TABLE				(1 << 5)
2900 #define   GM45_ERROR_MEM_PRIV				(1 << 4)
2901 #define   I915_ERROR_PAGE_TABLE				(1 << 4)
2902 #define   GM45_ERROR_CP_PRIV				(1 << 3)
2903 #define   I915_ERROR_MEMORY_REFRESH			(1 << 1)
2904 #define   I915_ERROR_INSTRUCTION			(1 << 0)
2905 #define INSTPM	        _MMIO(0x20c0)
2906 #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
2907 #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2908 					will not assert AGPBUSY# and will only
2909 					be delivered when out of C3. */
2910 #define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
2911 #define   INSTPM_TLB_INVALIDATE	(1 << 9)
2912 #define   INSTPM_SYNC_FLUSH	(1 << 5)
2913 #define ACTHD(base)	_MMIO((base) + 0xc8)
2914 #define MEM_MODE	_MMIO(0x20cc)
2915 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2916 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2917 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2918 #define FW_BLC		_MMIO(0x20d8)
2919 #define FW_BLC2		_MMIO(0x20dc)
2920 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
2921 #define   FW_BLC_SELF_EN_MASK      (1 << 31)
2922 #define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
2923 #define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
2924 #define MM_BURST_LENGTH     0x00700000
2925 #define MM_FIFO_WATERMARK   0x0001F000
2926 #define LM_BURST_LENGTH     0x00000700
2927 #define LM_FIFO_WATERMARK   0x0000001F
2928 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
2929 
2930 #define _MBUS_ABOX0_CTL			0x45038
2931 #define _MBUS_ABOX1_CTL			0x45048
2932 #define _MBUS_ABOX2_CTL			0x4504C
2933 #define MBUS_ABOX_CTL(x)		_MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
2934 						    _MBUS_ABOX1_CTL, \
2935 						    _MBUS_ABOX2_CTL))
2936 #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
2937 #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
2938 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
2939 #define MBUS_ABOX_B_CREDIT(x)		((x) << 16)
2940 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
2941 #define MBUS_ABOX_BT_CREDIT_POOL2(x)	((x) << 8)
2942 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
2943 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
2944 
2945 #define _PIPEA_MBUS_DBOX_CTL		0x7003C
2946 #define _PIPEB_MBUS_DBOX_CTL		0x7103C
2947 #define PIPE_MBUS_DBOX_CTL(pipe)	_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2948 						   _PIPEB_MBUS_DBOX_CTL)
2949 #define MBUS_DBOX_BW_CREDIT_MASK	(3 << 14)
2950 #define MBUS_DBOX_BW_CREDIT(x)		((x) << 14)
2951 #define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
2952 #define MBUS_DBOX_B_CREDIT(x)		((x) << 8)
2953 #define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
2954 #define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
2955 
2956 #define MBUS_UBOX_CTL			_MMIO(0x4503C)
2957 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
2958 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
2959 
2960 #define MBUS_CTL			_MMIO(0x4438C)
2961 #define MBUS_JOIN			REG_BIT(31)
2962 #define MBUS_HASHING_MODE_MASK		REG_BIT(30)
2963 #define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
2964 #define MBUS_HASHING_MODE_1x4		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
2965 #define MBUS_JOIN_PIPE_SELECT_MASK	REG_GENMASK(28, 26)
2966 #define MBUS_JOIN_PIPE_SELECT(pipe)	REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
2967 #define MBUS_JOIN_PIPE_SELECT_NONE	MBUS_JOIN_PIPE_SELECT(7)
2968 
2969 #define HDPORT_STATE			_MMIO(0x45050)
2970 #define   HDPORT_DPLL_USED_MASK		REG_GENMASK(15, 12)
2971 #define   HDPORT_DDI_USED(phy)		REG_BIT(2 * (phy) + 1)
2972 #define   HDPORT_ENABLED		REG_BIT(0)
2973 
2974 /* Make render/texture TLB fetches lower priorty than associated data
2975  *   fetches. This is not turned on by default
2976  */
2977 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
2978 
2979 /* Isoch request wait on GTT enable (Display A/B/C streams).
2980  * Make isoch requests stall on the TLB update. May cause
2981  * display underruns (test mode only)
2982  */
2983 #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
2984 
2985 /* Block grant count for isoch requests when block count is
2986  * set to a finite value.
2987  */
2988 #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
2989 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
2990 #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
2991 #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
2992 #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
2993 
2994 /* Enable render writes to complete in C2/C3/C4 power states.
2995  * If this isn't enabled, render writes are prevented in low
2996  * power states. That seems bad to me.
2997  */
2998 #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
2999 
3000 /* This acknowledges an async flip immediately instead
3001  * of waiting for 2TLB fetches.
3002  */
3003 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
3004 
3005 /* Enables non-sequential data reads through arbiter
3006  */
3007 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
3008 
3009 /* Disable FSB snooping of cacheable write cycles from binner/render
3010  * command stream
3011  */
3012 #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
3013 
3014 /* Arbiter time slice for non-isoch streams */
3015 #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
3016 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
3017 #define   MI_ARB_TIME_SLICE_2			(1 << 5)
3018 #define   MI_ARB_TIME_SLICE_4			(2 << 5)
3019 #define   MI_ARB_TIME_SLICE_6			(3 << 5)
3020 #define   MI_ARB_TIME_SLICE_8			(4 << 5)
3021 #define   MI_ARB_TIME_SLICE_10			(5 << 5)
3022 #define   MI_ARB_TIME_SLICE_14			(6 << 5)
3023 #define   MI_ARB_TIME_SLICE_16			(7 << 5)
3024 
3025 /* Low priority grace period page size */
3026 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
3027 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
3028 
3029 /* Disable display A/B trickle feed */
3030 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
3031 
3032 /* Set display plane priority */
3033 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
3034 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
3035 
3036 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
3037 #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
3038 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
3039 
3040 #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
3041 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
3042 #define   CM0_IZ_OPT_DISABLE      (1 << 6)
3043 #define   CM0_ZR_OPT_DISABLE      (1 << 5)
3044 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1 << 5)
3045 #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
3046 #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
3047 #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
3048 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
3049 #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
3050 #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
3051 #define   GFX_FLSH_CNTL_EN	(1 << 0)
3052 #define ECOSKPD		_MMIO(0x21d0)
3053 #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
3054 #define   ECO_GATING_CX_ONLY	(1 << 3)
3055 #define   ECO_FLIP_DONE		(1 << 0)
3056 
3057 #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
3058 #define RC_OP_FLUSH_ENABLE (1 << 0)
3059 #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
3060 #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
3061 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)
3062 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)
3063 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)
3064 
3065 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
3066 #define   GEN6_BLITTER_LOCK_SHIFT			16
3067 #define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)
3068 
3069 #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
3070 #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
3071 #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
3072 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
3073 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1 << 10)
3074 
3075 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3076 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3077 
3078 #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
3079 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
3080 
3081 /* Fuse readout registers for GT */
3082 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
3083 #define   HSW_F1_EU_DIS_SHIFT		16
3084 #define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
3085 #define   HSW_F1_EU_DIS_10EUS		0
3086 #define   HSW_F1_EU_DIS_8EUS		1
3087 #define   HSW_F1_EU_DIS_6EUS		2
3088 
3089 #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
3090 #define   CHV_FGT_DISABLE_SS0		(1 << 10)
3091 #define   CHV_FGT_DISABLE_SS1		(1 << 11)
3092 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
3093 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3094 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
3095 #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3096 #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
3097 #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3098 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
3099 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3100 
3101 #define GEN8_FUSE2			_MMIO(0x9120)
3102 #define   GEN8_F2_SS_DIS_SHIFT		21
3103 #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
3104 #define   GEN8_F2_S_ENA_SHIFT		25
3105 #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
3106 
3107 #define   GEN9_F2_SS_DIS_SHIFT		20
3108 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
3109 
3110 #define   GEN10_F2_S_ENA_SHIFT		22
3111 #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
3112 #define   GEN10_F2_SS_DIS_SHIFT		18
3113 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
3114 
3115 #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
3116 #define GEN10_L3BANK_PAIR_COUNT     4
3117 #define GEN10_L3BANK_MASK   0x0F
3118 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */
3119 #define GEN12_MAX_MSLICES 4
3120 #define GEN12_MEML3_EN_MASK 0x0F
3121 
3122 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
3123 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
3124 #define   GEN8_EU_DIS0_S1_SHIFT		24
3125 #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
3126 
3127 #define GEN8_EU_DISABLE1		_MMIO(0x9138)
3128 #define   GEN8_EU_DIS1_S1_MASK		0xffff
3129 #define   GEN8_EU_DIS1_S2_SHIFT		16
3130 #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
3131 
3132 #define GEN8_EU_DISABLE2		_MMIO(0x913c)
3133 #define   GEN8_EU_DIS2_S2_MASK		0xff
3134 
3135 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
3136 
3137 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
3138 #define   GEN10_EU_DIS_SS_MASK		0xff
3139 
3140 #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
3141 #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
3142 #define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
3143 #define   GEN11_GT_VEBOX_DISABLE_MASK	(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3144 
3145 #define GEN11_EU_DISABLE _MMIO(0x9134)
3146 #define GEN11_EU_DIS_MASK 0xFF
3147 
3148 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3149 #define GEN11_GT_S_ENA_MASK 0xFF
3150 
3151 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3152 
3153 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
3154 
3155 #define XEHP_EU_ENABLE			_MMIO(0x9134)
3156 #define XEHP_EU_ENA_MASK		0xFF
3157 
3158 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
3159 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
3160 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
3161 #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
3162 #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
3163 
3164 /* On modern GEN architectures interrupt control consists of two sets
3165  * of registers. The first set pertains to the ring generating the
3166  * interrupt. The second control is for the functional block generating the
3167  * interrupt. These are PM, GT, DE, etc.
3168  *
3169  * Luckily *knocks on wood* all the ring interrupt bits match up with the
3170  * GT interrupt bits, so we don't need to duplicate the defines.
3171  *
3172  * These defines should cover us well from SNB->HSW with minor exceptions
3173  * it can also work on ILK.
3174  */
3175 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
3176 #define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
3177 #define GT_BLT_USER_INTERRUPT			(1 << 22)
3178 #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
3179 #define GT_BSD_USER_INTERRUPT			(1 << 12)
3180 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
3181 #define GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11) /* bdw+ */
3182 #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
3183 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
3184 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
3185 #define GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
3186 #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
3187 #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
3188 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
3189 
3190 #define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
3191 #define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
3192 
3193 #define GT_PARITY_ERROR(dev_priv) \
3194 	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3195 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3196 
3197 /* These are all the "old" interrupts */
3198 #define ILK_BSD_USER_INTERRUPT				(1 << 5)
3199 
3200 #define I915_PM_INTERRUPT				(1 << 31)
3201 #define I915_ISP_INTERRUPT				(1 << 22)
3202 #define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
3203 #define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
3204 #define I915_MIPIC_INTERRUPT				(1 << 19)
3205 #define I915_MIPIA_INTERRUPT				(1 << 18)
3206 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
3207 #define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
3208 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
3209 #define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
3210 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
3211 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
3212 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
3213 #define I915_HWB_OOM_INTERRUPT				(1 << 13)
3214 #define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
3215 #define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
3216 #define I915_MISC_INTERRUPT				(1 << 11)
3217 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
3218 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
3219 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
3220 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
3221 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
3222 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
3223 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
3224 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
3225 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
3226 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
3227 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
3228 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
3229 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
3230 #define I915_DEBUG_INTERRUPT				(1 << 2)
3231 #define I915_WINVALID_INTERRUPT				(1 << 1)
3232 #define I915_USER_INTERRUPT				(1 << 1)
3233 #define I915_ASLE_INTERRUPT				(1 << 0)
3234 #define I915_BSD_USER_INTERRUPT				(1 << 25)
3235 
3236 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
3237 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
3238 
3239 /* DisplayPort Audio w/ LPE */
3240 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
3241 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
3242 
3243 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
3244 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
3245 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
3246 #define VLV_AUD_PORT_EN_DBG(port)	_MMIO_PORT3((port) - PORT_B,	   \
3247 						    _VLV_AUD_PORT_EN_B_DBG, \
3248 						    _VLV_AUD_PORT_EN_C_DBG, \
3249 						    _VLV_AUD_PORT_EN_D_DBG)
3250 #define VLV_AMP_MUTE		        (1 << 1)
3251 
3252 #define GEN6_BSD_RNCID			_MMIO(0x12198)
3253 
3254 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
3255 #define   GEN7_FF_SCHED_MASK		0x0077070
3256 #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
3257 #define   GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
3258 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
3259 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
3260 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
3261 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
3262 #define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
3263 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
3264 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
3265 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
3266 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
3267 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
3268 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
3269 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
3270 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
3271 
3272 /*
3273  * Framebuffer compression (915+ only)
3274  */
3275 
3276 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
3277 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
3278 #define FBC_CONTROL		_MMIO(0x3208)
3279 #define   FBC_CTL_EN		REG_BIT(31)
3280 #define   FBC_CTL_PERIODIC	REG_BIT(30)
3281 #define   FBC_CTL_INTERVAL_MASK	REG_GENMASK(29, 16)
3282 #define   FBC_CTL_INTERVAL(x)	REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
3283 #define   FBC_CTL_STOP_ON_MOD	REG_BIT(15)
3284 #define   FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
3285 #define   FBC_CTL_C3_IDLE	REG_BIT(13) /* i945gm */
3286 #define   FBC_CTL_STRIDE_MASK	REG_GENMASK(12, 5)
3287 #define   FBC_CTL_STRIDE(x)	REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
3288 #define   FBC_CTL_FENCENO_MASK	REG_GENMASK(3, 0)
3289 #define   FBC_CTL_FENCENO(x)	REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
3290 #define FBC_COMMAND		_MMIO(0x320c)
3291 #define   FBC_CMD_COMPRESS	(1 << 0)
3292 #define FBC_STATUS		_MMIO(0x3210)
3293 #define   FBC_STAT_COMPRESSING	(1 << 31)
3294 #define   FBC_STAT_COMPRESSED	(1 << 30)
3295 #define   FBC_STAT_MODIFIED	(1 << 29)
3296 #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
3297 #define FBC_CONTROL2		_MMIO(0x3214)
3298 #define   FBC_CTL_FENCE_DBL	(0 << 4)
3299 #define   FBC_CTL_IDLE_IMM	(0 << 2)
3300 #define   FBC_CTL_IDLE_FULL	(1 << 2)
3301 #define   FBC_CTL_IDLE_LINE	(2 << 2)
3302 #define   FBC_CTL_IDLE_DEBUG	(3 << 2)
3303 #define   FBC_CTL_CPU_FENCE	(1 << 1)
3304 #define   FBC_CTL_PLANE(plane)	((plane) << 0)
3305 #define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
3306 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
3307 
3308 #define FBC_LL_SIZE		(1536)
3309 
3310 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
3311 #define   FBC_LLC_FULLY_OPEN	(1 << 30)
3312 
3313 /* Framebuffer compression for GM45+ */
3314 #define DPFC_CB_BASE		_MMIO(0x3200)
3315 #define DPFC_CONTROL		_MMIO(0x3208)
3316 #define   DPFC_CTL_EN		(1 << 31)
3317 #define   DPFC_CTL_PLANE(plane)	((plane) << 30)
3318 #define   IVB_DPFC_CTL_PLANE(plane)	((plane) << 29)
3319 #define   DPFC_CTL_FENCE_EN	(1 << 29)
3320 #define   IVB_DPFC_CTL_FENCE_EN	(1 << 28)
3321 #define   DPFC_CTL_PERSISTENT_MODE	(1 << 25)
3322 #define   DPFC_SR_EN		(1 << 10)
3323 #define   DPFC_CTL_LIMIT_1X	(0 << 6)
3324 #define   DPFC_CTL_LIMIT_2X	(1 << 6)
3325 #define   DPFC_CTL_LIMIT_4X	(2 << 6)
3326 #define DPFC_RECOMP_CTL		_MMIO(0x320c)
3327 #define   DPFC_RECOMP_STALL_EN	(1 << 27)
3328 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
3329 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3330 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3331 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3332 #define DPFC_STATUS		_MMIO(0x3210)
3333 #define   DPFC_INVAL_SEG_SHIFT  (16)
3334 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
3335 #define   DPFC_COMP_SEG_SHIFT	(0)
3336 #define   DPFC_COMP_SEG_MASK	(0x000007ff)
3337 #define DPFC_STATUS2		_MMIO(0x3214)
3338 #define DPFC_FENCE_YOFF		_MMIO(0x3218)
3339 #define DPFC_CHICKEN		_MMIO(0x3224)
3340 #define   DPFC_HT_MODIFY	(1 << 31)
3341 
3342 /* Framebuffer compression for Ironlake */
3343 #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
3344 #define ILK_DPFC_CONTROL	_MMIO(0x43208)
3345 #define   FBC_CTL_FALSE_COLOR	(1 << 10)
3346 /* The bit 28-8 is reserved */
3347 #define   DPFC_RESERVED		(0x1FFFFF00)
3348 #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
3349 #define ILK_DPFC_STATUS		_MMIO(0x43210)
3350 #define  ILK_DPFC_COMP_SEG_MASK	0x7ff
3351 #define IVB_FBC_STATUS2		_MMIO(0x43214)
3352 #define  IVB_FBC_COMP_SEG_MASK	0x7ff
3353 #define  BDW_FBC_COMP_SEG_MASK	0xfff
3354 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
3355 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
3356 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3357 #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL	(1 << 14)
3358 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1 << 23)
3359 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
3360 #define   ILK_FBC_RT_VALID	(1 << 0)
3361 #define   SNB_FBC_FRONT_BUFFER	(1 << 1)
3362 
3363 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
3364 #define   ILK_FBCQ_DIS		(1 << 22)
3365 #define   ILK_PABSTRETCH_DIS	REG_BIT(21)
3366 #define   ILK_SABSTRETCH_DIS	REG_BIT(20)
3367 #define   IVB_PRI_STRETCH_MAX_MASK	REG_GENMASK(21, 20)
3368 #define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
3369 #define   IVB_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
3370 #define   IVB_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
3371 #define   IVB_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
3372 #define   IVB_SPR_STRETCH_MAX_MASK	REG_GENMASK(19, 18)
3373 #define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
3374 #define   IVB_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
3375 #define   IVB_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
3376 #define   IVB_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
3377 
3378 
3379 /*
3380  * Framebuffer compression for Sandybridge
3381  *
3382  * The following two registers are of type GTTMMADR
3383  */
3384 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
3385 #define   SNB_CPU_FENCE_ENABLE	(1 << 29)
3386 #define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
3387 
3388 /* Framebuffer compression for Ivybridge */
3389 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
3390 #define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
3391 
3392 #define IPS_CTL		_MMIO(0x43408)
3393 #define   IPS_ENABLE	(1 << 31)
3394 
3395 #define MSG_FBC_REND_STATE	_MMIO(0x50380)
3396 #define   FBC_REND_NUKE		(1 << 2)
3397 #define   FBC_REND_CACHE_CLEAN	(1 << 1)
3398 
3399 /*
3400  * GPIO regs
3401  */
3402 #define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3403 				      4 * (gpio))
3404 
3405 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
3406 # define GPIO_CLOCK_DIR_IN		(0 << 1)
3407 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
3408 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
3409 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
3410 # define GPIO_CLOCK_VAL_IN		(1 << 4)
3411 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
3412 # define GPIO_DATA_DIR_MASK		(1 << 8)
3413 # define GPIO_DATA_DIR_IN		(0 << 9)
3414 # define GPIO_DATA_DIR_OUT		(1 << 9)
3415 # define GPIO_DATA_VAL_MASK		(1 << 10)
3416 # define GPIO_DATA_VAL_OUT		(1 << 11)
3417 # define GPIO_DATA_VAL_IN		(1 << 12)
3418 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
3419 
3420 #define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3421 #define   GMBUS_AKSV_SELECT	(1 << 11)
3422 #define   GMBUS_RATE_100KHZ	(0 << 8)
3423 #define   GMBUS_RATE_50KHZ	(1 << 8)
3424 #define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */
3425 #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
3426 #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
3427 #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3428 
3429 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3430 #define   GMBUS_SW_CLR_INT	(1 << 31)
3431 #define   GMBUS_SW_RDY		(1 << 30)
3432 #define   GMBUS_ENT		(1 << 29) /* enable timeout */
3433 #define   GMBUS_CYCLE_NONE	(0 << 25)
3434 #define   GMBUS_CYCLE_WAIT	(1 << 25)
3435 #define   GMBUS_CYCLE_INDEX	(2 << 25)
3436 #define   GMBUS_CYCLE_STOP	(4 << 25)
3437 #define   GMBUS_BYTE_COUNT_SHIFT 16
3438 #define   GMBUS_BYTE_COUNT_MAX   256U
3439 #define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
3440 #define   GMBUS_SLAVE_INDEX_SHIFT 8
3441 #define   GMBUS_SLAVE_ADDR_SHIFT 1
3442 #define   GMBUS_SLAVE_READ	(1 << 0)
3443 #define   GMBUS_SLAVE_WRITE	(0 << 0)
3444 #define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3445 #define   GMBUS_INUSE		(1 << 15)
3446 #define   GMBUS_HW_WAIT_PHASE	(1 << 14)
3447 #define   GMBUS_STALL_TIMEOUT	(1 << 13)
3448 #define   GMBUS_INT		(1 << 12)
3449 #define   GMBUS_HW_RDY		(1 << 11)
3450 #define   GMBUS_SATOER		(1 << 10)
3451 #define   GMBUS_ACTIVE		(1 << 9)
3452 #define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3453 #define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3454 #define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3455 #define   GMBUS_NAK_EN		(1 << 3)
3456 #define   GMBUS_IDLE_EN		(1 << 2)
3457 #define   GMBUS_HW_WAIT_EN	(1 << 1)
3458 #define   GMBUS_HW_RDY_EN	(1 << 0)
3459 #define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3460 #define   GMBUS_2BYTE_INDEX_EN	(1 << 31)
3461 
3462 /*
3463  * Clock control & power management
3464  */
3465 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3466 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3467 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3468 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3469 
3470 #define VGA0	_MMIO(0x6000)
3471 #define VGA1	_MMIO(0x6004)
3472 #define VGA_PD	_MMIO(0x6010)
3473 #define   VGA0_PD_P2_DIV_4	(1 << 7)
3474 #define   VGA0_PD_P1_DIV_2	(1 << 5)
3475 #define   VGA0_PD_P1_SHIFT	0
3476 #define   VGA0_PD_P1_MASK	(0x1f << 0)
3477 #define   VGA1_PD_P2_DIV_4	(1 << 15)
3478 #define   VGA1_PD_P1_DIV_2	(1 << 13)
3479 #define   VGA1_PD_P1_SHIFT	8
3480 #define   VGA1_PD_P1_MASK	(0x1f << 8)
3481 #define   DPLL_VCO_ENABLE		(1 << 31)
3482 #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
3483 #define   DPLL_DVO_2X_MODE		(1 << 30)
3484 #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
3485 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
3486 #define   DPLL_REF_CLK_ENABLE_VLV	(1 << 29)
3487 #define   DPLL_VGA_MODE_DIS		(1 << 28)
3488 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
3489 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
3490 #define   DPLL_MODE_MASK		(3 << 26)
3491 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3492 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3493 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
3494 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
3495 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
3496 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
3497 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3498 #define   DPLL_LOCK_VLV			(1 << 15)
3499 #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1 << 14)
3500 #define   DPLL_INTEGRATED_REF_CLK_VLV	(1 << 13)
3501 #define   DPLL_SSC_REF_CLK_CHV		(1 << 13)
3502 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
3503 #define   DPLL_PORTB_READY_MASK		(0xf)
3504 
3505 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
3506 
3507 /* Additional CHV pll/phy registers */
3508 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
3509 #define   DPLL_PORTD_READY_MASK		(0xf)
3510 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3511 #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2 * (phy) + (ch) + 27))
3512 #define   PHY_LDO_DELAY_0NS			0x0
3513 #define   PHY_LDO_DELAY_200NS			0x1
3514 #define   PHY_LDO_DELAY_600NS			0x2
3515 #define   PHY_LDO_SEQ_DELAY(delay, phy)		((delay) << (2 * (phy) + 23))
3516 #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)	((mask) << (8 * (phy) + 4 * (ch) + 11))
3517 #define   PHY_CH_SU_PSR				0x1
3518 #define   PHY_CH_DEEP_PSR			0x7
3519 #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6 * (phy) + 3 * (ch) + 2))
3520 #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
3521 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3522 #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3523 #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
3524 #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3525 
3526 /*
3527  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3528  * this field (only one bit may be set).
3529  */
3530 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
3531 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
3532 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3533 /* i830, required in DVO non-gang */
3534 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
3535 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
3536 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
3537 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
3538 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
3539 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3540 #define   PLL_REF_INPUT_MASK		(3 << 13)
3541 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
3542 /* Ironlake */
3543 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
3544 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
3545 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x) - 1) << 9)
3546 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3547 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3548 
3549 /*
3550  * Parallel to Serial Load Pulse phase selection.
3551  * Selects the phase for the 10X DPLL clock for the PCIe
3552  * digital display port. The range is 4 to 13; 10 or more
3553  * is just a flip delay. The default is 6
3554  */
3555 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3556 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
3557 /*
3558  * SDVO multiplier for 945G/GM. Not used on 965.
3559  */
3560 #define   SDVO_MULTIPLIER_MASK			0x000000ff
3561 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
3562 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
3563 
3564 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3565 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3566 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3567 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3568 
3569 /*
3570  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3571  *
3572  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
3573  */
3574 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
3575 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
3576 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3577 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
3578 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
3579 /*
3580  * SDVO/UDI pixel multiplier.
3581  *
3582  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3583  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
3584  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3585  * dummy bytes in the datastream at an increased clock rate, with both sides of
3586  * the link knowing how many bytes are fill.
3587  *
3588  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3589  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
3590  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3591  * through an SDVO command.
3592  *
3593  * This register field has values of multiplication factor minus 1, with
3594  * a maximum multiplier of 5 for SDVO.
3595  */
3596 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
3597 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
3598 /*
3599  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3600  * This best be set to the default value (3) or the CRT won't work. No,
3601  * I don't entirely understand what this does...
3602  */
3603 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
3604 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3605 
3606 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
3607 
3608 #define _FPA0	0x6040
3609 #define _FPA1	0x6044
3610 #define _FPB0	0x6048
3611 #define _FPB1	0x604c
3612 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3613 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3614 #define   FP_N_DIV_MASK		0x003f0000
3615 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
3616 #define   FP_N_DIV_SHIFT		16
3617 #define   FP_M1_DIV_MASK	0x00003f00
3618 #define   FP_M1_DIV_SHIFT		 8
3619 #define   FP_M2_DIV_MASK	0x0000003f
3620 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
3621 #define   FP_M2_DIV_SHIFT		 0
3622 #define DPLL_TEST	_MMIO(0x606c)
3623 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
3624 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
3625 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
3626 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
3627 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
3628 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
3629 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
3630 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
3631 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
3632 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
3633 #define D_STATE		_MMIO(0x6104)
3634 #define  DSTATE_GFX_RESET_I830			(1 << 6)
3635 #define  DSTATE_PLL_D3_OFF			(1 << 3)
3636 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
3637 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
3638 #define DSPCLK_GATE_D	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3639 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
3640 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
3641 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
3642 # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
3643 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
3644 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
3645 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
3646 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
3647 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
3648 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
3649 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
3650 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
3651 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
3652 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
3653 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
3654 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
3655 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
3656 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
3657 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
3658 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
3659 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3660 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
3661 # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
3662 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
3663 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
3664 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
3665 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
3666 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
3667 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
3668 /*
3669  * This bit must be set on the 830 to prevent hangs when turning off the
3670  * overlay scaler.
3671  */
3672 # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
3673 # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
3674 # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3675 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
3676 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
3677 
3678 #define RENCLK_GATE_D1		_MMIO(0x6204)
3679 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
3680 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
3681 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
3682 # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
3683 # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
3684 # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
3685 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
3686 # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
3687 # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
3688 /* This bit must be unset on 855,865 */
3689 # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
3690 # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
3691 # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
3692 # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
3693 /* This bit must be set on 855,865. */
3694 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
3695 # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
3696 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
3697 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
3698 # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
3699 # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
3700 # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
3701 # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
3702 # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
3703 # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
3704 # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
3705 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
3706 # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
3707 # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
3708 # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
3709 # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
3710 # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
3711 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
3712 
3713 # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
3714 /* This bit must always be set on 965G/965GM */
3715 # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
3716 # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
3717 # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
3718 # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
3719 # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
3720 # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
3721 /* This bit must always be set on 965G */
3722 # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
3723 # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
3724 # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
3725 # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
3726 # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
3727 # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
3728 # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
3729 # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
3730 # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
3731 # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
3732 # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
3733 # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
3734 # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
3735 # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
3736 # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
3737 # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
3738 # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
3739 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
3740 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
3741 
3742 #define RENCLK_GATE_D2		_MMIO(0x6208)
3743 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
3744 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
3745 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
3746 
3747 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
3748 #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
3749 
3750 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
3751 #define DEUC			_MMIO(0x6214)          /* CRL only */
3752 
3753 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
3754 #define  FW_CSPWRDWNEN		(1 << 15)
3755 
3756 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
3757 
3758 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
3759 #define   CDCLK_FREQ_SHIFT	4
3760 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
3761 #define   CZCLK_FREQ_MASK	0xf
3762 
3763 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
3764 #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
3765 #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
3766 #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
3767 #define   PFI_CREDIT_RESEND	(1 << 27)
3768 #define   VGA_FAST_MODE_DISABLE	(1 << 14)
3769 
3770 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
3771 
3772 /*
3773  * Palette regs
3774  */
3775 #define _PALETTE_A		0xa000
3776 #define _PALETTE_B		0xa800
3777 #define _CHV_PALETTE_C		0xc000
3778 #define PALETTE_RED_MASK        REG_GENMASK(23, 16)
3779 #define PALETTE_GREEN_MASK      REG_GENMASK(15, 8)
3780 #define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
3781 #define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3782 				      _PICK((pipe), _PALETTE_A,		\
3783 					    _PALETTE_B, _CHV_PALETTE_C) + \
3784 				      (i) * 4)
3785 
3786 /* MCH MMIO space */
3787 
3788 /*
3789  * MCHBAR mirror.
3790  *
3791  * This mirrors the MCHBAR MMIO space whose location is determined by
3792  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3793  * every way.  It is not accessible from the CP register read instructions.
3794  *
3795  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3796  * just read.
3797  */
3798 #define MCHBAR_MIRROR_BASE	0x10000
3799 
3800 #define MCHBAR_MIRROR_BASE_SNB	0x140000
3801 
3802 #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
3803 #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
3804 #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
3805 #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
3806 #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
3807 
3808 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3809 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3810 
3811 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3812 #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
3813 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
3814 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
3815 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
3816 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
3817 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
3818 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
3819 #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
3820 #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
3821 
3822 /* Pineview MCH register contains DDR3 setting */
3823 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3824 #define CSHRDDR3CTL_DDR3       (1 << 2)
3825 
3826 /* 965 MCH register controlling DRAM channel configuration */
3827 #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
3828 #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
3829 
3830 /* snb MCH registers for reading the DRAM channel configuration */
3831 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3832 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3833 #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3834 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
3835 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
3836 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
3837 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
3838 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
3839 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
3840 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
3841 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
3842 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
3843 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
3844 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
3845 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
3846 /* DIMM sizes are in multiples of 256mb. */
3847 #define   MAD_DIMM_B_SIZE_SHIFT		8
3848 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
3849 #define   MAD_DIMM_A_SIZE_SHIFT		0
3850 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
3851 
3852 /* snb MCH registers for priority tuning */
3853 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3854 #define   MCH_SSKPD_WM0_MASK		0x3f
3855 #define   MCH_SSKPD_WM0_VAL		0xc
3856 
3857 /* Clocking configuration register */
3858 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3859 #define CLKCFG_FSB_400					(0 << 0)	/* hrawclk 100 */
3860 #define CLKCFG_FSB_400_ALT				(5 << 0)	/* hrawclk 100 */
3861 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
3862 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
3863 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
3864 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
3865 #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
3866 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
3867 #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
3868 #define CLKCFG_FSB_1600_ALT				(6 << 0)	/* hrawclk 400 */
3869 #define CLKCFG_FSB_MASK					(7 << 0)
3870 #define CLKCFG_MEM_533					(1 << 4)
3871 #define CLKCFG_MEM_667					(2 << 4)
3872 #define CLKCFG_MEM_800					(3 << 4)
3873 #define CLKCFG_MEM_MASK					(7 << 4)
3874 
3875 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3876 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3877 
3878 #define TSC1			_MMIO(0x11001)
3879 #define   TSE			(1 << 0)
3880 #define TR1			_MMIO(0x11006)
3881 #define TSFS			_MMIO(0x11020)
3882 #define   TSFS_SLOPE_MASK	0x0000ff00
3883 #define   TSFS_SLOPE_SHIFT	8
3884 #define   TSFS_INTR_MASK	0x000000ff
3885 
3886 #define CRSTANDVID		_MMIO(0x11100)
3887 #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3888 #define   PXVFREQ_PX_MASK	0x7f000000
3889 #define   PXVFREQ_PX_SHIFT	24
3890 #define VIDFREQ_BASE		_MMIO(0x11110)
3891 #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3892 #define VIDFREQ2		_MMIO(0x11114)
3893 #define VIDFREQ3		_MMIO(0x11118)
3894 #define VIDFREQ4		_MMIO(0x1111c)
3895 #define   VIDFREQ_P0_MASK	0x1f000000
3896 #define   VIDFREQ_P0_SHIFT	24
3897 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
3898 #define   VIDFREQ_P0_CSCLK_SHIFT 20
3899 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
3900 #define   VIDFREQ_P0_CRCLK_SHIFT 16
3901 #define   VIDFREQ_P1_MASK	0x00001f00
3902 #define   VIDFREQ_P1_SHIFT	8
3903 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
3904 #define   VIDFREQ_P1_CSCLK_SHIFT 4
3905 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
3906 #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
3907 #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3908 #define   INTTOEXT_MAP3_SHIFT	24
3909 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
3910 #define   INTTOEXT_MAP2_SHIFT	16
3911 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
3912 #define   INTTOEXT_MAP1_SHIFT	8
3913 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
3914 #define   INTTOEXT_MAP0_SHIFT	0
3915 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
3916 #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
3917 #define   MEMCTL_CMD_MASK	0xe000
3918 #define   MEMCTL_CMD_SHIFT	13
3919 #define   MEMCTL_CMD_RCLK_OFF	0
3920 #define   MEMCTL_CMD_RCLK_ON	1
3921 #define   MEMCTL_CMD_CHFREQ	2
3922 #define   MEMCTL_CMD_CHVID	3
3923 #define   MEMCTL_CMD_VMMOFF	4
3924 #define   MEMCTL_CMD_VMMON	5
3925 #define   MEMCTL_CMD_STS	(1 << 12) /* write 1 triggers command, clears
3926 					   when command complete */
3927 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
3928 #define   MEMCTL_FREQ_SHIFT	8
3929 #define   MEMCTL_SFCAVM		(1 << 7)
3930 #define   MEMCTL_TGT_VID_MASK	0x007f
3931 #define MEMIHYST		_MMIO(0x1117c)
3932 #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
3933 #define   MEMINT_RSEXIT_EN	(1 << 8)
3934 #define   MEMINT_CX_SUPR_EN	(1 << 7)
3935 #define   MEMINT_CONT_BUSY_EN	(1 << 6)
3936 #define   MEMINT_AVG_BUSY_EN	(1 << 5)
3937 #define   MEMINT_EVAL_CHG_EN	(1 << 4)
3938 #define   MEMINT_MON_IDLE_EN	(1 << 3)
3939 #define   MEMINT_UP_EVAL_EN	(1 << 2)
3940 #define   MEMINT_DOWN_EVAL_EN	(1 << 1)
3941 #define   MEMINT_SW_CMD_EN	(1 << 0)
3942 #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
3943 #define   MEM_RSEXIT_MASK	0xc000
3944 #define   MEM_RSEXIT_SHIFT	14
3945 #define   MEM_CONT_BUSY_MASK	0x3000
3946 #define   MEM_CONT_BUSY_SHIFT	12
3947 #define   MEM_AVG_BUSY_MASK	0x0c00
3948 #define   MEM_AVG_BUSY_SHIFT	10
3949 #define   MEM_EVAL_CHG_MASK	0x0300
3950 #define   MEM_EVAL_BUSY_SHIFT	8
3951 #define   MEM_MON_IDLE_MASK	0x00c0
3952 #define   MEM_MON_IDLE_SHIFT	6
3953 #define   MEM_UP_EVAL_MASK	0x0030
3954 #define   MEM_UP_EVAL_SHIFT	4
3955 #define   MEM_DOWN_EVAL_MASK	0x000c
3956 #define   MEM_DOWN_EVAL_SHIFT	2
3957 #define   MEM_SW_CMD_MASK	0x0003
3958 #define   MEM_INT_STEER_GFX	0
3959 #define   MEM_INT_STEER_CMR	1
3960 #define   MEM_INT_STEER_SMI	2
3961 #define   MEM_INT_STEER_SCI	3
3962 #define MEMINTRSTS		_MMIO(0x11184)
3963 #define   MEMINT_RSEXIT		(1 << 7)
3964 #define   MEMINT_CONT_BUSY	(1 << 6)
3965 #define   MEMINT_AVG_BUSY	(1 << 5)
3966 #define   MEMINT_EVAL_CHG	(1 << 4)
3967 #define   MEMINT_MON_IDLE	(1 << 3)
3968 #define   MEMINT_UP_EVAL	(1 << 2)
3969 #define   MEMINT_DOWN_EVAL	(1 << 1)
3970 #define   MEMINT_SW_CMD		(1 << 0)
3971 #define MEMMODECTL		_MMIO(0x11190)
3972 #define   MEMMODE_BOOST_EN	(1 << 31)
3973 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3974 #define   MEMMODE_BOOST_FREQ_SHIFT 24
3975 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3976 #define   MEMMODE_IDLE_MODE_SHIFT 16
3977 #define   MEMMODE_IDLE_MODE_EVAL 0
3978 #define   MEMMODE_IDLE_MODE_CONT 1
3979 #define   MEMMODE_HWIDLE_EN	(1 << 15)
3980 #define   MEMMODE_SWMODE_EN	(1 << 14)
3981 #define   MEMMODE_RCLK_GATE	(1 << 13)
3982 #define   MEMMODE_HW_UPDATE	(1 << 12)
3983 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
3984 #define   MEMMODE_FSTART_SHIFT	8
3985 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
3986 #define   MEMMODE_FMAX_SHIFT	4
3987 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
3988 #define RCBMAXAVG		_MMIO(0x1119c)
3989 #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
3990 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
3991 #define   SWMEMCMD_RENDER_ON	(1 << 13)
3992 #define   SWMEMCMD_SWFREQ	(2 << 13)
3993 #define   SWMEMCMD_TARVID	(3 << 13)
3994 #define   SWMEMCMD_VRM_OFF	(4 << 13)
3995 #define   SWMEMCMD_VRM_ON	(5 << 13)
3996 #define   CMDSTS		(1 << 12)
3997 #define   SFCAVM		(1 << 11)
3998 #define   SWFREQ_MASK		0x0380 /* P0-7 */
3999 #define   SWFREQ_SHIFT		7
4000 #define   TARVID_MASK		0x001f
4001 #define MEMSTAT_CTG		_MMIO(0x111a0)
4002 #define RCBMINAVG		_MMIO(0x111a0)
4003 #define RCUPEI			_MMIO(0x111b0)
4004 #define RCDNEI			_MMIO(0x111b4)
4005 #define RSTDBYCTL		_MMIO(0x111b8)
4006 #define   RS1EN			(1 << 31)
4007 #define   RS2EN			(1 << 30)
4008 #define   RS3EN			(1 << 29)
4009 #define   D3RS3EN		(1 << 28) /* Display D3 imlies RS3 */
4010 #define   SWPROMORSX		(1 << 27) /* RSx promotion timers ignored */
4011 #define   RCWAKERW		(1 << 26) /* Resetwarn from PCH causes wakeup */
4012 #define   DPRSLPVREN		(1 << 25) /* Fast voltage ramp enable */
4013 #define   GFXTGHYST		(1 << 24) /* Hysteresis to allow trunk gating */
4014 #define   RCX_SW_EXIT		(1 << 23) /* Leave RSx and prevent re-entry */
4015 #define   RSX_STATUS_MASK	(7 << 20)
4016 #define   RSX_STATUS_ON		(0 << 20)
4017 #define   RSX_STATUS_RC1	(1 << 20)
4018 #define   RSX_STATUS_RC1E	(2 << 20)
4019 #define   RSX_STATUS_RS1	(3 << 20)
4020 #define   RSX_STATUS_RS2	(4 << 20) /* aka rc6 */
4021 #define   RSX_STATUS_RSVD	(5 << 20) /* deep rc6 unsupported on ilk */
4022 #define   RSX_STATUS_RS3	(6 << 20) /* rs3 unsupported on ilk */
4023 #define   RSX_STATUS_RSVD2	(7 << 20)
4024 #define   UWRCRSXE		(1 << 19) /* wake counter limit prevents rsx */
4025 #define   RSCRP			(1 << 18) /* rs requests control on rs1/2 reqs */
4026 #define   JRSC			(1 << 17) /* rsx coupled to cpu c-state */
4027 #define   RS2INC0		(1 << 16) /* allow rs2 in cpu c0 */
4028 #define   RS1CONTSAV_MASK	(3 << 14)
4029 #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
4030 #define   RS1CONTSAV_RSVD	(1 << 14)
4031 #define   RS1CONTSAV_SAVE_RS1	(2 << 14) /* rs1 saves context */
4032 #define   RS1CONTSAV_FULL_RS1	(3 << 14) /* rs1 saves and restores context */
4033 #define   NORMSLEXLAT_MASK	(3 << 12)
4034 #define   SLOW_RS123		(0 << 12)
4035 #define   SLOW_RS23		(1 << 12)
4036 #define   SLOW_RS3		(2 << 12)
4037 #define   NORMAL_RS123		(3 << 12)
4038 #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
4039 #define   IMPROMOEN		(1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
4040 #define   RCENTSYNC		(1 << 9) /* rs coupled to cpu c-state (3/6/7) */
4041 #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
4042 #define   RS_CSTATE_MASK	(3 << 4)
4043 #define   RS_CSTATE_C367_RS1	(0 << 4)
4044 #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
4045 #define   RS_CSTATE_RSVD	(2 << 4)
4046 #define   RS_CSTATE_C367_RS2	(3 << 4)
4047 #define   REDSAVES		(1 << 3) /* no context save if was idle during rs0 */
4048 #define   REDRESTORES		(1 << 2) /* no restore if was idle during rs0 */
4049 #define VIDCTL			_MMIO(0x111c0)
4050 #define VIDSTS			_MMIO(0x111c8)
4051 #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
4052 #define MEMSTAT_ILK		_MMIO(0x111f8)
4053 #define   MEMSTAT_VID_MASK	0x7f00
4054 #define   MEMSTAT_VID_SHIFT	8
4055 #define   MEMSTAT_PSTATE_MASK	0x00f8
4056 #define   MEMSTAT_PSTATE_SHIFT  3
4057 #define   MEMSTAT_MON_ACTV	(1 << 2)
4058 #define   MEMSTAT_SRC_CTL_MASK	0x0003
4059 #define   MEMSTAT_SRC_CTL_CORE	0
4060 #define   MEMSTAT_SRC_CTL_TRB	1
4061 #define   MEMSTAT_SRC_CTL_THM	2
4062 #define   MEMSTAT_SRC_CTL_STDBY 3
4063 #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
4064 #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
4065 #define PMMISC			_MMIO(0x11214)
4066 #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
4067 #define SDEW			_MMIO(0x1124c)
4068 #define CSIEW0			_MMIO(0x11250)
4069 #define CSIEW1			_MMIO(0x11254)
4070 #define CSIEW2			_MMIO(0x11258)
4071 #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
4072 #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
4073 #define MCHAFE			_MMIO(0x112c0)
4074 #define CSIEC			_MMIO(0x112e0)
4075 #define DMIEC			_MMIO(0x112e4)
4076 #define DDREC			_MMIO(0x112e8)
4077 #define PEG0EC			_MMIO(0x112ec)
4078 #define PEG1EC			_MMIO(0x112f0)
4079 #define GFXEC			_MMIO(0x112f4)
4080 #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
4081 #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
4082 #define ECR			_MMIO(0x11600)
4083 #define   ECR_GPFE		(1 << 31)
4084 #define   ECR_IMONE		(1 << 30)
4085 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
4086 #define OGW0			_MMIO(0x11608)
4087 #define OGW1			_MMIO(0x1160c)
4088 #define EG0			_MMIO(0x11610)
4089 #define EG1			_MMIO(0x11614)
4090 #define EG2			_MMIO(0x11618)
4091 #define EG3			_MMIO(0x1161c)
4092 #define EG4			_MMIO(0x11620)
4093 #define EG5			_MMIO(0x11624)
4094 #define EG6			_MMIO(0x11628)
4095 #define EG7			_MMIO(0x1162c)
4096 #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
4097 #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
4098 #define LCFUSE02		_MMIO(0x116c0)
4099 #define   LCFUSE_HIV_MASK	0x000000ff
4100 #define CSIPLL0			_MMIO(0x12c10)
4101 #define DDRMPLL1		_MMIO(0X12c20)
4102 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
4103 
4104 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4105 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4106 
4107 #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4108 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4109 #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4110 #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4111 #define   RP0_CAP_MASK		REG_GENMASK(7, 0)
4112 #define   RP1_CAP_MASK		REG_GENMASK(15, 8)
4113 #define   RPN_CAP_MASK		REG_GENMASK(23, 16)
4114 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
4115 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
4116 
4117 /*
4118  * Logical Context regs
4119  */
4120 #define CCID(base)			_MMIO((base) + 0x180)
4121 #define   CCID_EN			BIT(0)
4122 #define   CCID_EXTENDED_STATE_RESTORE	BIT(2)
4123 #define   CCID_EXTENDED_STATE_SAVE	BIT(3)
4124 /*
4125  * Notes on SNB/IVB/VLV context size:
4126  * - Power context is saved elsewhere (LLC or stolen)
4127  * - Ring/execlist context is saved on SNB, not on IVB
4128  * - Extended context size already includes render context size
4129  * - We always need to follow the extended context size.
4130  *   SNB BSpec has comments indicating that we should use the
4131  *   render context size instead if execlists are disabled, but
4132  *   based on empirical testing that's just nonsense.
4133  * - Pipelined/VF state is saved on SNB/IVB respectively
4134  * - GT1 size just indicates how much of render context
4135  *   doesn't need saving on GT1
4136  */
4137 #define CXT_SIZE		_MMIO(0x21a0)
4138 #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
4139 #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
4140 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
4141 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
4142 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
4143 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
4144 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4145 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4146 #define GEN7_CXT_SIZE		_MMIO(0x21a8)
4147 #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
4148 #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
4149 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
4150 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
4151 #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
4152 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
4153 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4154 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4155 
4156 enum {
4157 	INTEL_ADVANCED_CONTEXT = 0,
4158 	INTEL_LEGACY_32B_CONTEXT,
4159 	INTEL_ADVANCED_AD_CONTEXT,
4160 	INTEL_LEGACY_64B_CONTEXT
4161 };
4162 
4163 enum {
4164 	FAULT_AND_HANG = 0,
4165 	FAULT_AND_HALT, /* Debug only */
4166 	FAULT_AND_STREAM,
4167 	FAULT_AND_CONTINUE /* Unsupported */
4168 };
4169 
4170 #define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
4171 #define GEN8_CTX_VALID (1 << 0)
4172 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4173 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
4174 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4175 #define GEN8_CTX_PRIVILEGE (1 << 8)
4176 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4177 
4178 #define GEN8_CTX_ID_SHIFT 32
4179 #define GEN8_CTX_ID_WIDTH 21
4180 #define GEN11_SW_CTX_ID_SHIFT 37
4181 #define GEN11_SW_CTX_ID_WIDTH 11
4182 #define GEN11_ENGINE_CLASS_SHIFT 61
4183 #define GEN11_ENGINE_CLASS_WIDTH 3
4184 #define GEN11_ENGINE_INSTANCE_SHIFT 48
4185 #define GEN11_ENGINE_INSTANCE_WIDTH 6
4186 
4187 #define XEHP_SW_CTX_ID_SHIFT 39
4188 #define XEHP_SW_CTX_ID_WIDTH 16
4189 #define XEHP_SW_COUNTER_SHIFT 58
4190 #define XEHP_SW_COUNTER_WIDTH 6
4191 
4192 #define CHV_CLK_CTL1			_MMIO(0x101100)
4193 #define VLV_CLK_CTL2			_MMIO(0x101104)
4194 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
4195 
4196 /*
4197  * Overlay regs
4198  */
4199 
4200 #define OVADD			_MMIO(0x30000)
4201 #define DOVSTA			_MMIO(0x30008)
4202 #define OC_BUF			(0x3 << 20)
4203 #define OGAMC5			_MMIO(0x30010)
4204 #define OGAMC4			_MMIO(0x30014)
4205 #define OGAMC3			_MMIO(0x30018)
4206 #define OGAMC2			_MMIO(0x3001c)
4207 #define OGAMC1			_MMIO(0x30020)
4208 #define OGAMC0			_MMIO(0x30024)
4209 
4210 /*
4211  * GEN9 clock gating regs
4212  */
4213 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
4214 #define   DARBF_GATING_DIS		(1 << 27)
4215 #define   PWM2_GATING_DIS		(1 << 14)
4216 #define   PWM1_GATING_DIS		(1 << 13)
4217 
4218 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
4219 #define   TGL_VRH_GATING_DIS		REG_BIT(31)
4220 #define   DPT_GATING_DIS		REG_BIT(22)
4221 
4222 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
4223 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
4224 
4225 #define GEN9_CLKGATE_DIS_5		_MMIO(0x46540)
4226 #define   DPCE_GATING_DIS		REG_BIT(17)
4227 
4228 #define _CLKGATE_DIS_PSL_A		0x46520
4229 #define _CLKGATE_DIS_PSL_B		0x46524
4230 #define _CLKGATE_DIS_PSL_C		0x46528
4231 #define   DUPS1_GATING_DIS		(1 << 15)
4232 #define   DUPS2_GATING_DIS		(1 << 19)
4233 #define   DUPS3_GATING_DIS		(1 << 23)
4234 #define   DPF_GATING_DIS		(1 << 10)
4235 #define   DPF_RAM_GATING_DIS		(1 << 9)
4236 #define   DPFR_GATING_DIS		(1 << 8)
4237 
4238 #define CLKGATE_DIS_PSL(pipe) \
4239 	_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4240 
4241 /*
4242  * GEN10 clock gating regs
4243  */
4244 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
4245 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
4246 #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
4247 #define  MSCUNIT_CLKGATE_DIS		(1 << 10)
4248 #define  L3_CLKGATE_DIS			REG_BIT(16)
4249 #define  L3_CR2X_CLKGATE_DIS		REG_BIT(17)
4250 
4251 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
4252 #define  GWUNIT_CLKGATE_DIS		(1 << 16)
4253 
4254 #define SUBSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x9528)
4255 #define  CPSSUNIT_CLKGATE_DIS		REG_BIT(9)
4256 
4257 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
4258 #define   VFUNIT_CLKGATE_DIS		REG_BIT(20)
4259 #define   HSUNIT_CLKGATE_DIS		REG_BIT(8)
4260 #define   VSUNIT_CLKGATE_DIS		REG_BIT(3)
4261 
4262 #define UNSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x94e4)
4263 #define   VSUNIT_CLKGATE_DIS_TGL	REG_BIT(19)
4264 #define   PSDUNIT_CLKGATE_DIS		REG_BIT(5)
4265 
4266 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
4267 #define   CGPSF_CLKGATE_DIS		(1 << 3)
4268 
4269 /*
4270  * Display engine regs
4271  */
4272 
4273 /* Pipe A CRC regs */
4274 #define _PIPE_CRC_CTL_A			0x60050
4275 #define   PIPE_CRC_ENABLE		(1 << 31)
4276 /* skl+ source selection */
4277 #define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
4278 #define   PIPE_CRC_SOURCE_PLANE_2_SKL	(2 << 28)
4279 #define   PIPE_CRC_SOURCE_DMUX_SKL	(4 << 28)
4280 #define   PIPE_CRC_SOURCE_PLANE_3_SKL	(6 << 28)
4281 #define   PIPE_CRC_SOURCE_PLANE_4_SKL	(7 << 28)
4282 #define   PIPE_CRC_SOURCE_PLANE_5_SKL	(5 << 28)
4283 #define   PIPE_CRC_SOURCE_PLANE_6_SKL	(3 << 28)
4284 #define   PIPE_CRC_SOURCE_PLANE_7_SKL	(1 << 28)
4285 /* ivb+ source selection */
4286 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
4287 #define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
4288 #define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
4289 /* ilk+ source selection */
4290 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
4291 #define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
4292 #define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
4293 /* embedded DP port on the north display block, reserved on ivb */
4294 #define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
4295 #define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
4296 /* vlv source selection */
4297 #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
4298 #define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
4299 #define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
4300 /* with DP port the pipe source is invalid */
4301 #define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
4302 #define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
4303 #define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
4304 /* gen3+ source selection */
4305 #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
4306 #define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
4307 #define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
4308 /* with DP/TV port the pipe source is invalid */
4309 #define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
4310 #define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
4311 #define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
4312 #define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
4313 #define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
4314 /* gen2 doesn't have source selection bits */
4315 #define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
4316 
4317 #define _PIPE_CRC_RES_1_A_IVB		0x60064
4318 #define _PIPE_CRC_RES_2_A_IVB		0x60068
4319 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
4320 #define _PIPE_CRC_RES_4_A_IVB		0x60070
4321 #define _PIPE_CRC_RES_5_A_IVB		0x60074
4322 
4323 #define _PIPE_CRC_RES_RED_A		0x60060
4324 #define _PIPE_CRC_RES_GREEN_A		0x60064
4325 #define _PIPE_CRC_RES_BLUE_A		0x60068
4326 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
4327 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
4328 
4329 /* Pipe B CRC regs */
4330 #define _PIPE_CRC_RES_1_B_IVB		0x61064
4331 #define _PIPE_CRC_RES_2_B_IVB		0x61068
4332 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
4333 #define _PIPE_CRC_RES_4_B_IVB		0x61070
4334 #define _PIPE_CRC_RES_5_B_IVB		0x61074
4335 
4336 #define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4337 #define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4338 #define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4339 #define PIPE_CRC_RES_3_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4340 #define PIPE_CRC_RES_4_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4341 #define PIPE_CRC_RES_5_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4342 
4343 #define PIPE_CRC_RES_RED(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4344 #define PIPE_CRC_RES_GREEN(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4345 #define PIPE_CRC_RES_BLUE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4346 #define PIPE_CRC_RES_RES1_I915(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4347 #define PIPE_CRC_RES_RES2_G4X(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4348 
4349 /* Pipe A timing regs */
4350 #define _HTOTAL_A	0x60000
4351 #define _HBLANK_A	0x60004
4352 #define _HSYNC_A	0x60008
4353 #define _VTOTAL_A	0x6000c
4354 #define _VBLANK_A	0x60010
4355 #define _VSYNC_A	0x60014
4356 #define _EXITLINE_A	0x60018
4357 #define _PIPEASRC	0x6001c
4358 #define _BCLRPAT_A	0x60020
4359 #define _VSYNCSHIFT_A	0x60028
4360 #define _PIPE_MULT_A	0x6002c
4361 
4362 /* Pipe B timing regs */
4363 #define _HTOTAL_B	0x61000
4364 #define _HBLANK_B	0x61004
4365 #define _HSYNC_B	0x61008
4366 #define _VTOTAL_B	0x6100c
4367 #define _VBLANK_B	0x61010
4368 #define _VSYNC_B	0x61014
4369 #define _PIPEBSRC	0x6101c
4370 #define _BCLRPAT_B	0x61020
4371 #define _VSYNCSHIFT_B	0x61028
4372 #define _PIPE_MULT_B	0x6102c
4373 
4374 /* DSI 0 timing regs */
4375 #define _HTOTAL_DSI0		0x6b000
4376 #define _HSYNC_DSI0		0x6b008
4377 #define _VTOTAL_DSI0		0x6b00c
4378 #define _VSYNC_DSI0		0x6b014
4379 #define _VSYNCSHIFT_DSI0	0x6b028
4380 
4381 /* DSI 1 timing regs */
4382 #define _HTOTAL_DSI1		0x6b800
4383 #define _HSYNC_DSI1		0x6b808
4384 #define _VTOTAL_DSI1		0x6b80c
4385 #define _VSYNC_DSI1		0x6b814
4386 #define _VSYNCSHIFT_DSI1	0x6b828
4387 
4388 #define TRANSCODER_A_OFFSET 0x60000
4389 #define TRANSCODER_B_OFFSET 0x61000
4390 #define TRANSCODER_C_OFFSET 0x62000
4391 #define CHV_TRANSCODER_C_OFFSET 0x63000
4392 #define TRANSCODER_D_OFFSET 0x63000
4393 #define TRANSCODER_EDP_OFFSET 0x6f000
4394 #define TRANSCODER_DSI0_OFFSET	0x6b000
4395 #define TRANSCODER_DSI1_OFFSET	0x6b800
4396 
4397 #define HTOTAL(trans)		_MMIO_TRANS2(trans, _HTOTAL_A)
4398 #define HBLANK(trans)		_MMIO_TRANS2(trans, _HBLANK_A)
4399 #define HSYNC(trans)		_MMIO_TRANS2(trans, _HSYNC_A)
4400 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
4401 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
4402 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
4403 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
4404 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4405 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
4406 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
4407 
4408 #define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
4409 #define   EXITLINE_ENABLE	REG_BIT(31)
4410 #define   EXITLINE_MASK		REG_GENMASK(12, 0)
4411 #define   EXITLINE_SHIFT	0
4412 
4413 /* VRR registers */
4414 #define _TRANS_VRR_CTL_A		0x60420
4415 #define _TRANS_VRR_CTL_B		0x61420
4416 #define _TRANS_VRR_CTL_C		0x62420
4417 #define _TRANS_VRR_CTL_D		0x63420
4418 #define TRANS_VRR_CTL(trans)			_MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
4419 #define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
4420 #define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
4421 #define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
4422 #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
4423 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
4424 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
4425 #define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
4426 #define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
4427 
4428 #define _TRANS_VRR_VMAX_A		0x60424
4429 #define _TRANS_VRR_VMAX_B		0x61424
4430 #define _TRANS_VRR_VMAX_C		0x62424
4431 #define _TRANS_VRR_VMAX_D		0x63424
4432 #define TRANS_VRR_VMAX(trans)		_MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
4433 #define   VRR_VMAX_MASK			REG_GENMASK(19, 0)
4434 
4435 #define _TRANS_VRR_VMIN_A		0x60434
4436 #define _TRANS_VRR_VMIN_B		0x61434
4437 #define _TRANS_VRR_VMIN_C		0x62434
4438 #define _TRANS_VRR_VMIN_D		0x63434
4439 #define TRANS_VRR_VMIN(trans)		_MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
4440 #define   VRR_VMIN_MASK			REG_GENMASK(15, 0)
4441 
4442 #define _TRANS_VRR_VMAXSHIFT_A		0x60428
4443 #define _TRANS_VRR_VMAXSHIFT_B		0x61428
4444 #define _TRANS_VRR_VMAXSHIFT_C		0x62428
4445 #define _TRANS_VRR_VMAXSHIFT_D		0x63428
4446 #define TRANS_VRR_VMAXSHIFT(trans)	_MMIO_TRANS2(trans, \
4447 					_TRANS_VRR_VMAXSHIFT_A)
4448 #define   VRR_VMAXSHIFT_DEC_MASK	REG_GENMASK(29, 16)
4449 #define   VRR_VMAXSHIFT_DEC		REG_BIT(16)
4450 #define   VRR_VMAXSHIFT_INC_MASK	REG_GENMASK(12, 0)
4451 
4452 #define _TRANS_VRR_STATUS_A		0x6042C
4453 #define _TRANS_VRR_STATUS_B		0x6142C
4454 #define _TRANS_VRR_STATUS_C		0x6242C
4455 #define _TRANS_VRR_STATUS_D		0x6342C
4456 #define TRANS_VRR_STATUS(trans)		_MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
4457 #define   VRR_STATUS_VMAX_REACHED	REG_BIT(31)
4458 #define   VRR_STATUS_NOFLIP_TILL_BNDR	REG_BIT(30)
4459 #define   VRR_STATUS_FLIP_BEF_BNDR	REG_BIT(29)
4460 #define   VRR_STATUS_NO_FLIP_FRAME	REG_BIT(28)
4461 #define   VRR_STATUS_VRR_EN_LIVE	REG_BIT(27)
4462 #define   VRR_STATUS_FLIPS_SERVICED	REG_BIT(26)
4463 #define   VRR_STATUS_VBLANK_MASK	REG_GENMASK(22, 20)
4464 #define   STATUS_FSM_IDLE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4465 #define   STATUS_FSM_WAIT_TILL_FDB	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
4466 #define   STATUS_FSM_WAIT_TILL_FS	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
4467 #define   STATUS_FSM_WAIT_TILL_FLIP	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
4468 #define   STATUS_FSM_PIPELINE_FILL	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
4469 #define   STATUS_FSM_ACTIVE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
4470 #define   STATUS_FSM_LEGACY_VBLANK	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
4471 
4472 #define _TRANS_VRR_VTOTAL_PREV_A	0x60480
4473 #define _TRANS_VRR_VTOTAL_PREV_B	0x61480
4474 #define _TRANS_VRR_VTOTAL_PREV_C	0x62480
4475 #define _TRANS_VRR_VTOTAL_PREV_D	0x63480
4476 #define TRANS_VRR_VTOTAL_PREV(trans)	_MMIO_TRANS2(trans, \
4477 					_TRANS_VRR_VTOTAL_PREV_A)
4478 #define   VRR_VTOTAL_FLIP_BEFR_BNDR	REG_BIT(31)
4479 #define   VRR_VTOTAL_FLIP_AFTER_BNDR	REG_BIT(30)
4480 #define   VRR_VTOTAL_FLIP_AFTER_DBLBUF	REG_BIT(29)
4481 #define   VRR_VTOTAL_PREV_FRAME_MASK	REG_GENMASK(19, 0)
4482 
4483 #define _TRANS_VRR_FLIPLINE_A		0x60438
4484 #define _TRANS_VRR_FLIPLINE_B		0x61438
4485 #define _TRANS_VRR_FLIPLINE_C		0x62438
4486 #define _TRANS_VRR_FLIPLINE_D		0x63438
4487 #define TRANS_VRR_FLIPLINE(trans)	_MMIO_TRANS2(trans, \
4488 					_TRANS_VRR_FLIPLINE_A)
4489 #define   VRR_FLIPLINE_MASK		REG_GENMASK(19, 0)
4490 
4491 #define _TRANS_VRR_STATUS2_A		0x6043C
4492 #define _TRANS_VRR_STATUS2_B		0x6143C
4493 #define _TRANS_VRR_STATUS2_C		0x6243C
4494 #define _TRANS_VRR_STATUS2_D		0x6343C
4495 #define TRANS_VRR_STATUS2(trans)	_MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
4496 #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
4497 
4498 #define _TRANS_PUSH_A			0x60A70
4499 #define _TRANS_PUSH_B			0x61A70
4500 #define _TRANS_PUSH_C			0x62A70
4501 #define _TRANS_PUSH_D			0x63A70
4502 #define TRANS_PUSH(trans)		_MMIO_TRANS2(trans, _TRANS_PUSH_A)
4503 #define   TRANS_PUSH_EN			REG_BIT(31)
4504 #define   TRANS_PUSH_SEND		REG_BIT(30)
4505 
4506 /*
4507  * HSW+ eDP PSR registers
4508  *
4509  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4510  * instance of it
4511  */
4512 #define _HSW_EDP_PSR_BASE			0x64800
4513 #define _SRD_CTL_A				0x60800
4514 #define _SRD_CTL_EDP				0x6f800
4515 #define _PSR_ADJ(tran, reg)			(_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4516 #define EDP_PSR_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
4517 #define   EDP_PSR_ENABLE			(1 << 31)
4518 #define   BDW_PSR_SINGLE_FRAME			(1 << 30)
4519 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1 << 29) /* SW can't modify */
4520 #define   EDP_PSR_LINK_STANDBY			(1 << 27)
4521 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3 << 25)
4522 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
4523 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1 << 25)
4524 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2 << 25)
4525 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3 << 25)
4526 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
4527 #define   EDP_PSR_SKIP_AUX_EXIT			(1 << 12)
4528 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
4529 #define   EDP_PSR_TP1_TP3_SEL			(1 << 11)
4530 #define   EDP_PSR_CRC_ENABLE			(1 << 10) /* BDW+ */
4531 #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
4532 #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
4533 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
4534 #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
4535 #define   EDP_PSR_TP4_TIME_0US			(3 << 6) /* ICL+ */
4536 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
4537 #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
4538 #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
4539 #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
4540 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
4541 
4542 /*
4543  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4544  * to transcoder and bits defined for each one as if using no shift (i.e. as if
4545  * it was for TRANSCODER_EDP)
4546  */
4547 #define EDP_PSR_IMR				_MMIO(0x64834)
4548 #define EDP_PSR_IIR				_MMIO(0x64838)
4549 #define _PSR_IMR_A				0x60814
4550 #define _PSR_IIR_A				0x60818
4551 #define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(tran, _PSR_IMR_A)
4552 #define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(tran, _PSR_IIR_A)
4553 #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
4554 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
4555 #define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4556 #define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4557 #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4558 #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4559 
4560 #define _SRD_AUX_CTL_A				0x60810
4561 #define _SRD_AUX_CTL_EDP			0x6f810
4562 #define EDP_PSR_AUX_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
4563 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
4564 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
4565 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
4566 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
4567 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
4568 
4569 #define _SRD_AUX_DATA_A				0x60814
4570 #define _SRD_AUX_DATA_EDP			0x6f814
4571 #define EDP_PSR_AUX_DATA(tran, i)		_MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
4572 
4573 #define _SRD_STATUS_A				0x60840
4574 #define _SRD_STATUS_EDP				0x6f840
4575 #define EDP_PSR_STATUS(tran)			_MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
4576 #define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)
4577 #define   EDP_PSR_STATUS_STATE_SHIFT		29
4578 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
4579 #define   EDP_PSR_STATUS_STATE_SRDONACK		(1 << 29)
4580 #define   EDP_PSR_STATUS_STATE_SRDENT		(2 << 29)
4581 #define   EDP_PSR_STATUS_STATE_BUFOFF		(3 << 29)
4582 #define   EDP_PSR_STATUS_STATE_BUFON		(4 << 29)
4583 #define   EDP_PSR_STATUS_STATE_AUXACK		(5 << 29)
4584 #define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6 << 29)
4585 #define   EDP_PSR_STATUS_LINK_MASK		(3 << 26)
4586 #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
4587 #define   EDP_PSR_STATUS_LINK_FULL_ON		(1 << 26)
4588 #define   EDP_PSR_STATUS_LINK_STANDBY		(2 << 26)
4589 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
4590 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
4591 #define   EDP_PSR_STATUS_COUNT_SHIFT		16
4592 #define   EDP_PSR_STATUS_COUNT_MASK		0xf
4593 #define   EDP_PSR_STATUS_AUX_ERROR		(1 << 15)
4594 #define   EDP_PSR_STATUS_AUX_SENDING		(1 << 12)
4595 #define   EDP_PSR_STATUS_SENDING_IDLE		(1 << 9)
4596 #define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1 << 8)
4597 #define   EDP_PSR_STATUS_SENDING_TP1		(1 << 4)
4598 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
4599 
4600 #define _SRD_PERF_CNT_A			0x60844
4601 #define _SRD_PERF_CNT_EDP		0x6f844
4602 #define EDP_PSR_PERF_CNT(tran)		_MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
4603 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
4604 
4605 /* PSR_MASK on SKL+ */
4606 #define _SRD_DEBUG_A				0x60860
4607 #define _SRD_DEBUG_EDP				0x6f860
4608 #define EDP_PSR_DEBUG(tran)			_MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
4609 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
4610 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
4611 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
4612 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
4613 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
4614 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4615 
4616 #define _PSR2_CTL_A				0x60900
4617 #define _PSR2_CTL_EDP				0x6f900
4618 #define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(tran, _PSR2_CTL_A)
4619 #define   EDP_PSR2_ENABLE			(1 << 31)
4620 #define   EDP_SU_TRACK_ENABLE			(1 << 30) /* up to adl-p */
4621 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
4622 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)
4623 #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
4624 #define   EDP_PSR2_SU_SDP_SCANLINE		REG_BIT(25) /* display 13+ */
4625 #define   EDP_MAX_SU_DISABLE_TIME(t)		((t) << 20)
4626 #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
4627 #define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES	8
4628 #define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
4629 #define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)
4630 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
4631 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT	13
4632 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
4633 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)
4634 #define   EDP_PSR2_FAST_WAKE_MAX_LINES		8
4635 #define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
4636 #define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)
4637 #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5
4638 #define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT	10
4639 #define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
4640 #define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)
4641 #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
4642 #define   EDP_PSR2_TP2_TIME_100us		(1 << 8)
4643 #define   EDP_PSR2_TP2_TIME_2500us		(2 << 8)
4644 #define   EDP_PSR2_TP2_TIME_50us		(3 << 8)
4645 #define   EDP_PSR2_TP2_TIME_MASK		(3 << 8)
4646 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT	4
4647 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK		(0xf << 4)
4648 #define   EDP_PSR2_FRAME_BEFORE_SU(a)		((a) << 4)
4649 #define   EDP_PSR2_IDLE_FRAME_MASK		0xf
4650 #define   EDP_PSR2_IDLE_FRAME_SHIFT		0
4651 
4652 #define _PSR_EVENT_TRANS_A			0x60848
4653 #define _PSR_EVENT_TRANS_B			0x61848
4654 #define _PSR_EVENT_TRANS_C			0x62848
4655 #define _PSR_EVENT_TRANS_D			0x63848
4656 #define _PSR_EVENT_TRANS_EDP			0x6f848
4657 #define PSR_EVENT(tran)				_MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
4658 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE		(1 << 17)
4659 #define  PSR_EVENT_PSR2_DISABLED		(1 << 16)
4660 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN	(1 << 15)
4661 #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN		(1 << 14)
4662 #define  PSR_EVENT_GRAPHICS_RESET		(1 << 12)
4663 #define  PSR_EVENT_PCH_INTERRUPT		(1 << 11)
4664 #define  PSR_EVENT_MEMORY_UP			(1 << 10)
4665 #define  PSR_EVENT_FRONT_BUFFER_MODIFY		(1 << 9)
4666 #define  PSR_EVENT_WD_TIMER_EXPIRE		(1 << 8)
4667 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE	(1 << 6)
4668 #define  PSR_EVENT_REGISTER_UPDATE		(1 << 5) /* Reserved in ICL+ */
4669 #define  PSR_EVENT_HDCP_ENABLE			(1 << 4)
4670 #define  PSR_EVENT_KVMR_SESSION_ENABLE		(1 << 3)
4671 #define  PSR_EVENT_VBI_ENABLE			(1 << 2)
4672 #define  PSR_EVENT_LPSP_MODE_EXIT		(1 << 1)
4673 #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
4674 
4675 #define _PSR2_STATUS_A			0x60940
4676 #define _PSR2_STATUS_EDP		0x6f940
4677 #define EDP_PSR2_STATUS(tran)		_MMIO_TRANS2(tran, _PSR2_STATUS_A)
4678 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4679 #define EDP_PSR2_STATUS_STATE_SHIFT    28
4680 
4681 #define _PSR2_SU_STATUS_A		0x60914
4682 #define _PSR2_SU_STATUS_EDP		0x6f914
4683 #define _PSR2_SU_STATUS(tran, index)	_MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
4684 #define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
4685 #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
4686 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4687 #define PSR2_SU_STATUS_FRAMES		8
4688 
4689 #define _PSR2_MAN_TRK_CTL_A					0x60910
4690 #define _PSR2_MAN_TRK_CTL_EDP					0x6f910
4691 #define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
4692 #define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
4693 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
4694 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
4695 #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(20, 11)
4696 #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
4697 #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
4698 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
4699 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
4700 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
4701 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
4702 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
4703 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
4704 #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
4705 #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
4706 
4707 /* Icelake DSC Rate Control Range Parameter Registers */
4708 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
4709 #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
4710 #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
4711 #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
4712 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
4713 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
4714 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
4715 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
4716 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
4717 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
4718 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
4719 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
4720 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4721 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
4722 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
4723 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4724 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
4725 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
4726 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4727 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
4728 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
4729 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4730 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
4731 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
4732 #define RC_BPG_OFFSET_SHIFT			10
4733 #define RC_MAX_QP_SHIFT				5
4734 #define RC_MIN_QP_SHIFT				0
4735 
4736 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
4737 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
4738 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
4739 #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
4740 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
4741 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
4742 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
4743 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
4744 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
4745 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
4746 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
4747 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
4748 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4749 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
4750 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
4751 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4752 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
4753 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
4754 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4755 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
4756 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
4757 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4758 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
4759 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
4760 
4761 #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
4762 #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
4763 #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
4764 #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
4765 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
4766 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
4767 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
4768 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
4769 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
4770 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
4771 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
4772 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
4773 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4774 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
4775 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
4776 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4777 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
4778 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
4779 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4780 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
4781 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
4782 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4783 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
4784 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
4785 
4786 #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
4787 #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
4788 #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
4789 #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
4790 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
4791 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
4792 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
4793 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
4794 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
4795 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
4796 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
4797 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
4798 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4799 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
4800 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
4801 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4802 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
4803 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
4804 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
4805 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
4806 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
4807 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
4808 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
4809 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
4810 
4811 /* VGA port control */
4812 #define ADPA			_MMIO(0x61100)
4813 #define PCH_ADPA                _MMIO(0xe1100)
4814 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
4815 
4816 #define   ADPA_DAC_ENABLE	(1 << 31)
4817 #define   ADPA_DAC_DISABLE	0
4818 #define   ADPA_PIPE_SEL_SHIFT		30
4819 #define   ADPA_PIPE_SEL_MASK		(1 << 30)
4820 #define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
4821 #define   ADPA_PIPE_SEL_SHIFT_CPT	29
4822 #define   ADPA_PIPE_SEL_MASK_CPT	(3 << 29)
4823 #define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
4824 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4825 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4826 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
4827 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4828 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
4829 #define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
4830 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4831 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
4832 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4833 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
4834 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4835 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
4836 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4837 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
4838 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
4839 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
4840 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4841 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
4842 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4843 #define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
4844 #define   ADPA_SETS_HVPOLARITY	0
4845 #define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4846 #define   ADPA_VSYNC_CNTL_ENABLE 0
4847 #define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4848 #define   ADPA_HSYNC_CNTL_ENABLE 0
4849 #define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4850 #define   ADPA_VSYNC_ACTIVE_LOW	0
4851 #define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4852 #define   ADPA_HSYNC_ACTIVE_LOW	0
4853 #define   ADPA_DPMS_MASK	(~(3 << 10))
4854 #define   ADPA_DPMS_ON		(0 << 10)
4855 #define   ADPA_DPMS_SUSPEND	(1 << 10)
4856 #define   ADPA_DPMS_STANDBY	(2 << 10)
4857 #define   ADPA_DPMS_OFF		(3 << 10)
4858 
4859 
4860 /* Hotplug control (945+ only) */
4861 #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4862 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
4863 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
4864 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
4865 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
4866 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
4867 #define   TV_HOTPLUG_INT_EN			(1 << 18)
4868 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
4869 #define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
4870 						 PORTC_HOTPLUG_INT_EN | \
4871 						 PORTD_HOTPLUG_INT_EN | \
4872 						 SDVOC_HOTPLUG_INT_EN | \
4873 						 SDVOB_HOTPLUG_INT_EN | \
4874 						 CRT_HOTPLUG_INT_EN)
4875 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
4876 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
4877 /* must use period 64 on GM45 according to docs */
4878 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
4879 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
4880 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
4881 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
4882 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
4883 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
4884 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
4885 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
4886 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
4887 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
4888 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
4889 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
4890 
4891 #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4892 /*
4893  * HDMI/DP bits are g4x+
4894  *
4895  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4896  * Please check the detailed lore in the commit message for for experimental
4897  * evidence.
4898  */
4899 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4900 #define   PORTD_HOTPLUG_LIVE_STATUS_GM45	(1 << 29)
4901 #define   PORTC_HOTPLUG_LIVE_STATUS_GM45	(1 << 28)
4902 #define   PORTB_HOTPLUG_LIVE_STATUS_GM45	(1 << 27)
4903 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4904 #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
4905 #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
4906 #define   PORTB_HOTPLUG_LIVE_STATUS_G4X		(1 << 29)
4907 #define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
4908 #define   PORTD_HOTPLUG_INT_LONG_PULSE		(2 << 21)
4909 #define   PORTD_HOTPLUG_INT_SHORT_PULSE		(1 << 21)
4910 #define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
4911 #define   PORTC_HOTPLUG_INT_LONG_PULSE		(2 << 19)
4912 #define   PORTC_HOTPLUG_INT_SHORT_PULSE		(1 << 19)
4913 #define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
4914 #define   PORTB_HOTPLUG_INT_LONG_PULSE		(2 << 17)
4915 #define   PORTB_HOTPLUG_INT_SHORT_PLUSE		(1 << 17)
4916 /* CRT/TV common between gen3+ */
4917 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
4918 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
4919 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
4920 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
4921 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
4922 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4923 #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
4924 #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
4925 #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
4926 #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(7 << 4)
4927 
4928 /* SDVO is different across gen3/4 */
4929 #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
4930 #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
4931 /*
4932  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4933  * since reality corrobates that they're the same as on gen3. But keep these
4934  * bits here (and the comment!) to help any other lost wanderers back onto the
4935  * right tracks.
4936  */
4937 #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
4938 #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
4939 #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
4940 #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
4941 #define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
4942 						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4943 						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4944 						 PORTB_HOTPLUG_INT_STATUS | \
4945 						 PORTC_HOTPLUG_INT_STATUS | \
4946 						 PORTD_HOTPLUG_INT_STATUS)
4947 
4948 #define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
4949 						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4950 						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4951 						 PORTB_HOTPLUG_INT_STATUS | \
4952 						 PORTC_HOTPLUG_INT_STATUS | \
4953 						 PORTD_HOTPLUG_INT_STATUS)
4954 
4955 /* SDVO and HDMI port control.
4956  * The same register may be used for SDVO or HDMI */
4957 #define _GEN3_SDVOB	0x61140
4958 #define _GEN3_SDVOC	0x61160
4959 #define GEN3_SDVOB	_MMIO(_GEN3_SDVOB)
4960 #define GEN3_SDVOC	_MMIO(_GEN3_SDVOC)
4961 #define GEN4_HDMIB	GEN3_SDVOB
4962 #define GEN4_HDMIC	GEN3_SDVOC
4963 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
4964 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
4965 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
4966 #define PCH_SDVOB	_MMIO(0xe1140)
4967 #define PCH_HDMIB	PCH_SDVOB
4968 #define PCH_HDMIC	_MMIO(0xe1150)
4969 #define PCH_HDMID	_MMIO(0xe1160)
4970 
4971 #define PORT_DFT_I9XX				_MMIO(0x61150)
4972 #define   DC_BALANCE_RESET			(1 << 25)
4973 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4974 #define   DC_BALANCE_RESET_VLV			(1 << 31)
4975 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
4976 #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
4977 #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
4978 #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
4979 
4980 /* Gen 3 SDVO bits: */
4981 #define   SDVO_ENABLE				(1 << 31)
4982 #define   SDVO_PIPE_SEL_SHIFT			30
4983 #define   SDVO_PIPE_SEL_MASK			(1 << 30)
4984 #define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
4985 #define   SDVO_STALL_SELECT			(1 << 29)
4986 #define   SDVO_INTERRUPT_ENABLE			(1 << 26)
4987 /*
4988  * 915G/GM SDVO pixel multiplier.
4989  * Programmed value is multiplier - 1, up to 5x.
4990  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4991  */
4992 #define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
4993 #define   SDVO_PORT_MULTIPLY_SHIFT		23
4994 #define   SDVO_PHASE_SELECT_MASK		(15 << 19)
4995 #define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
4996 #define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
4997 #define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
4998 #define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
4999 #define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
5000 #define   SDVO_DETECTED				(1 << 2)
5001 /* Bits to be preserved when writing */
5002 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
5003 			       SDVO_INTERRUPT_ENABLE)
5004 #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
5005 
5006 /* Gen 4 SDVO/HDMI bits: */
5007 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
5008 #define   SDVO_COLOR_FORMAT_MASK		(7 << 26)
5009 #define   SDVO_ENCODING_SDVO			(0 << 10)
5010 #define   SDVO_ENCODING_HDMI			(2 << 10)
5011 #define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
5012 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
5013 #define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
5014 #define   HDMI_AUDIO_ENABLE			(1 << 6) /* HDMI only */
5015 /* VSYNC/HSYNC bits new with 965, default is to be set */
5016 #define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
5017 #define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
5018 
5019 /* Gen 5 (IBX) SDVO/HDMI bits: */
5020 #define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
5021 #define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
5022 
5023 /* Gen 6 (CPT) SDVO/HDMI bits: */
5024 #define   SDVO_PIPE_SEL_SHIFT_CPT		29
5025 #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
5026 #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
5027 
5028 /* CHV SDVO/HDMI bits: */
5029 #define   SDVO_PIPE_SEL_SHIFT_CHV		24
5030 #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
5031 #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
5032 
5033 
5034 /* DVO port control */
5035 #define _DVOA			0x61120
5036 #define DVOA			_MMIO(_DVOA)
5037 #define _DVOB			0x61140
5038 #define DVOB			_MMIO(_DVOB)
5039 #define _DVOC			0x61160
5040 #define DVOC			_MMIO(_DVOC)
5041 #define   DVO_ENABLE			(1 << 31)
5042 #define   DVO_PIPE_SEL_SHIFT		30
5043 #define   DVO_PIPE_SEL_MASK		(1 << 30)
5044 #define   DVO_PIPE_SEL(pipe)		((pipe) << 30)
5045 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
5046 #define   DVO_PIPE_STALL		(1 << 28)
5047 #define   DVO_PIPE_STALL_TV		(2 << 28)
5048 #define   DVO_PIPE_STALL_MASK		(3 << 28)
5049 #define   DVO_USE_VGA_SYNC		(1 << 15)
5050 #define   DVO_DATA_ORDER_I740		(0 << 14)
5051 #define   DVO_DATA_ORDER_FP		(1 << 14)
5052 #define   DVO_VSYNC_DISABLE		(1 << 11)
5053 #define   DVO_HSYNC_DISABLE		(1 << 10)
5054 #define   DVO_VSYNC_TRISTATE		(1 << 9)
5055 #define   DVO_HSYNC_TRISTATE		(1 << 8)
5056 #define   DVO_BORDER_ENABLE		(1 << 7)
5057 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
5058 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
5059 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
5060 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
5061 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
5062 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
5063 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
5064 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
5065 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
5066 #define   DVO_PRESERVE_MASK		(0x7 << 24)
5067 #define DVOA_SRCDIM		_MMIO(0x61124)
5068 #define DVOB_SRCDIM		_MMIO(0x61144)
5069 #define DVOC_SRCDIM		_MMIO(0x61164)
5070 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
5071 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
5072 
5073 /* LVDS port control */
5074 #define LVDS			_MMIO(0x61180)
5075 /*
5076  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
5077  * the DPLL semantics change when the LVDS is assigned to that pipe.
5078  */
5079 #define   LVDS_PORT_EN			(1 << 31)
5080 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
5081 #define   LVDS_PIPE_SEL_SHIFT		30
5082 #define   LVDS_PIPE_SEL_MASK		(1 << 30)
5083 #define   LVDS_PIPE_SEL(pipe)		((pipe) << 30)
5084 #define   LVDS_PIPE_SEL_SHIFT_CPT	29
5085 #define   LVDS_PIPE_SEL_MASK_CPT	(3 << 29)
5086 #define   LVDS_PIPE_SEL_CPT(pipe)	((pipe) << 29)
5087 /* LVDS dithering flag on 965/g4x platform */
5088 #define   LVDS_ENABLE_DITHER		(1 << 25)
5089 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
5090 #define   LVDS_VSYNC_POLARITY		(1 << 21)
5091 #define   LVDS_HSYNC_POLARITY		(1 << 20)
5092 
5093 /* Enable border for unscaled (or aspect-scaled) display */
5094 #define   LVDS_BORDER_ENABLE		(1 << 15)
5095 /*
5096  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
5097  * pixel.
5098  */
5099 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
5100 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
5101 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
5102 /*
5103  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
5104  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
5105  * on.
5106  */
5107 #define   LVDS_A3_POWER_MASK		(3 << 6)
5108 #define   LVDS_A3_POWER_DOWN		(0 << 6)
5109 #define   LVDS_A3_POWER_UP		(3 << 6)
5110 /*
5111  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
5112  * is set.
5113  */
5114 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
5115 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
5116 #define   LVDS_CLKB_POWER_UP		(3 << 4)
5117 /*
5118  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
5119  * setting for whether we are in dual-channel mode.  The B3 pair will
5120  * additionally only be powered up when LVDS_A3_POWER_UP is set.
5121  */
5122 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
5123 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
5124 #define   LVDS_B0B3_POWER_UP		(3 << 2)
5125 
5126 /* Video Data Island Packet control */
5127 #define VIDEO_DIP_DATA		_MMIO(0x61178)
5128 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
5129  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
5130  * of the infoframe structure specified by CEA-861. */
5131 #define   VIDEO_DIP_DATA_SIZE	32
5132 #define   VIDEO_DIP_GMP_DATA_SIZE	36
5133 #define   VIDEO_DIP_VSC_DATA_SIZE	36
5134 #define   VIDEO_DIP_PPS_DATA_SIZE	132
5135 #define VIDEO_DIP_CTL		_MMIO(0x61170)
5136 /* Pre HSW: */
5137 #define   VIDEO_DIP_ENABLE		(1 << 31)
5138 #define   VIDEO_DIP_PORT(port)		((port) << 29)
5139 #define   VIDEO_DIP_PORT_MASK		(3 << 29)
5140 #define   VIDEO_DIP_ENABLE_GCP		(1 << 25) /* ilk+ */
5141 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
5142 #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
5143 #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21) /* ilk+ */
5144 #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
5145 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
5146 #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
5147 #define   VIDEO_DIP_SELECT_GAMUT	(2 << 19)
5148 #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
5149 #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
5150 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
5151 #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
5152 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
5153 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
5154 /* HSW and later: */
5155 #define   VIDEO_DIP_ENABLE_DRM_GLK	(1 << 28)
5156 #define   PSR_VSC_BIT_7_SET		(1 << 27)
5157 #define   VSC_SELECT_MASK		(0x3 << 25)
5158 #define   VSC_SELECT_SHIFT		25
5159 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
5160 #define   VSC_DIP_HW_HEA_SW_DATA	(1 << 25)
5161 #define   VSC_DIP_HW_DATA_SW_HEA	(2 << 25)
5162 #define   VSC_DIP_SW_HEA_DATA		(3 << 25)
5163 #define   VDIP_ENABLE_PPS		(1 << 24)
5164 #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
5165 #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
5166 #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
5167 #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
5168 #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
5169 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
5170 
5171 /* Panel power sequencing */
5172 #define PPS_BASE			0x61200
5173 #define VLV_PPS_BASE			(VLV_DISPLAY_BASE + PPS_BASE)
5174 #define PCH_PPS_BASE			0xC7200
5175 
5176 #define _MMIO_PPS(pps_idx, reg)		_MMIO(dev_priv->pps_mmio_base -	\
5177 					      PPS_BASE + (reg) +	\
5178 					      (pps_idx) * 0x100)
5179 
5180 #define _PP_STATUS			0x61200
5181 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
5182 #define   PP_ON				REG_BIT(31)
5183 /*
5184  * Indicates that all dependencies of the panel are on:
5185  *
5186  * - PLL enabled
5187  * - pipe enabled
5188  * - LVDS/DVOB/DVOC on
5189  */
5190 #define   PP_READY			REG_BIT(30)
5191 #define   PP_SEQUENCE_MASK		REG_GENMASK(29, 28)
5192 #define   PP_SEQUENCE_NONE		REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
5193 #define   PP_SEQUENCE_POWER_UP		REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
5194 #define   PP_SEQUENCE_POWER_DOWN	REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
5195 #define   PP_CYCLE_DELAY_ACTIVE		REG_BIT(27)
5196 #define   PP_SEQUENCE_STATE_MASK	REG_GENMASK(3, 0)
5197 #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
5198 #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
5199 #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
5200 #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
5201 #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
5202 #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
5203 #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
5204 #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
5205 #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
5206 
5207 #define _PP_CONTROL			0x61204
5208 #define PP_CONTROL(pps_idx)		_MMIO_PPS(pps_idx, _PP_CONTROL)
5209 #define  PANEL_UNLOCK_MASK		REG_GENMASK(31, 16)
5210 #define  PANEL_UNLOCK_REGS		REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
5211 #define  BXT_POWER_CYCLE_DELAY_MASK	REG_GENMASK(8, 4)
5212 #define  EDP_FORCE_VDD			REG_BIT(3)
5213 #define  EDP_BLC_ENABLE			REG_BIT(2)
5214 #define  PANEL_POWER_RESET		REG_BIT(1)
5215 #define  PANEL_POWER_ON			REG_BIT(0)
5216 
5217 #define _PP_ON_DELAYS			0x61208
5218 #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
5219 #define  PANEL_PORT_SELECT_MASK		REG_GENMASK(31, 30)
5220 #define  PANEL_PORT_SELECT_LVDS		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
5221 #define  PANEL_PORT_SELECT_DPA		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
5222 #define  PANEL_PORT_SELECT_DPC		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
5223 #define  PANEL_PORT_SELECT_DPD		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
5224 #define  PANEL_PORT_SELECT_VLV(port)	REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
5225 #define  PANEL_POWER_UP_DELAY_MASK	REG_GENMASK(28, 16)
5226 #define  PANEL_LIGHT_ON_DELAY_MASK	REG_GENMASK(12, 0)
5227 
5228 #define _PP_OFF_DELAYS			0x6120C
5229 #define PP_OFF_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
5230 #define  PANEL_POWER_DOWN_DELAY_MASK	REG_GENMASK(28, 16)
5231 #define  PANEL_LIGHT_OFF_DELAY_MASK	REG_GENMASK(12, 0)
5232 
5233 #define _PP_DIVISOR			0x61210
5234 #define PP_DIVISOR(pps_idx)		_MMIO_PPS(pps_idx, _PP_DIVISOR)
5235 #define  PP_REFERENCE_DIVIDER_MASK	REG_GENMASK(31, 8)
5236 #define  PANEL_POWER_CYCLE_DELAY_MASK	REG_GENMASK(4, 0)
5237 
5238 /* Panel fitting */
5239 #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
5240 #define   PFIT_ENABLE		(1 << 31)
5241 #define   PFIT_PIPE_MASK	(3 << 29)
5242 #define   PFIT_PIPE_SHIFT	29
5243 #define   PFIT_PIPE(pipe)	((pipe) << 29)
5244 #define   VERT_INTERP_DISABLE	(0 << 10)
5245 #define   VERT_INTERP_BILINEAR	(1 << 10)
5246 #define   VERT_INTERP_MASK	(3 << 10)
5247 #define   VERT_AUTO_SCALE	(1 << 9)
5248 #define   HORIZ_INTERP_DISABLE	(0 << 6)
5249 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
5250 #define   HORIZ_INTERP_MASK	(3 << 6)
5251 #define   HORIZ_AUTO_SCALE	(1 << 5)
5252 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
5253 #define   PFIT_FILTER_FUZZY	(0 << 24)
5254 #define   PFIT_SCALING_AUTO	(0 << 26)
5255 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
5256 #define   PFIT_SCALING_PILLAR	(2 << 26)
5257 #define   PFIT_SCALING_LETTER	(3 << 26)
5258 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
5259 /* Pre-965 */
5260 #define		PFIT_VERT_SCALE_SHIFT		20
5261 #define		PFIT_VERT_SCALE_MASK		0xfff00000
5262 #define		PFIT_HORIZ_SCALE_SHIFT		4
5263 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
5264 /* 965+ */
5265 #define		PFIT_VERT_SCALE_SHIFT_965	16
5266 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
5267 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
5268 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
5269 
5270 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
5271 
5272 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5273 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
5274 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
5275 					 _VLV_BLC_PWM_CTL2_B)
5276 
5277 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5278 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
5279 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
5280 					_VLV_BLC_PWM_CTL_B)
5281 
5282 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5283 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
5284 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
5285 					 _VLV_BLC_HIST_CTL_B)
5286 
5287 /* Backlight control */
5288 #define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
5289 #define   BLM_PWM_ENABLE		(1 << 31)
5290 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
5291 #define   BLM_PIPE_SELECT		(1 << 29)
5292 #define   BLM_PIPE_SELECT_IVB		(3 << 29)
5293 #define   BLM_PIPE_A			(0 << 29)
5294 #define   BLM_PIPE_B			(1 << 29)
5295 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
5296 #define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
5297 #define   BLM_TRANSCODER_B		BLM_PIPE_B
5298 #define   BLM_TRANSCODER_C		BLM_PIPE_C
5299 #define   BLM_TRANSCODER_EDP		(3 << 29)
5300 #define   BLM_PIPE(pipe)		((pipe) << 29)
5301 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
5302 #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
5303 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
5304 #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
5305 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
5306 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
5307 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
5308 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
5309 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
5310 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
5311 #define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5312 /*
5313  * This is the most significant 15 bits of the number of backlight cycles in a
5314  * complete cycle of the modulated backlight control.
5315  *
5316  * The actual value is this field multiplied by two.
5317  */
5318 #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
5319 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
5320 #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
5321 /*
5322  * This is the number of cycles out of the backlight modulation cycle for which
5323  * the backlight is on.
5324  *
5325  * This field must be no greater than the number of cycles in the complete
5326  * backlight modulation cycle.
5327  */
5328 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
5329 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
5330 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
5331 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
5332 
5333 #define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5334 #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
5335 
5336 /* New registers for PCH-split platforms. Safe where new bits show up, the
5337  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
5338 #define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
5339 #define BLC_PWM_CPU_CTL		_MMIO(0x48254)
5340 
5341 #define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
5342 
5343 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
5344  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
5345 #define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
5346 #define   BLM_PCH_PWM_ENABLE			(1 << 31)
5347 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
5348 #define   BLM_PCH_POLARITY			(1 << 29)
5349 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
5350 
5351 #define UTIL_PIN_CTL			_MMIO(0x48400)
5352 #define   UTIL_PIN_ENABLE		(1 << 31)
5353 #define   UTIL_PIN_PIPE_MASK		(3 << 29)
5354 #define   UTIL_PIN_PIPE(x)		((x) << 29)
5355 #define   UTIL_PIN_MODE_MASK		(0xf << 24)
5356 #define   UTIL_PIN_MODE_DATA		(0 << 24)
5357 #define   UTIL_PIN_MODE_PWM		(1 << 24)
5358 #define   UTIL_PIN_MODE_VBLANK		(4 << 24)
5359 #define   UTIL_PIN_MODE_VSYNC		(5 << 24)
5360 #define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
5361 #define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
5362 #define   UTIL_PIN_POLARITY		(1 << 22)
5363 #define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
5364 #define   UTIL_PIN_INPUT_DATA		(1 << 16)
5365 
5366 /* BXT backlight register definition. */
5367 #define _BXT_BLC_PWM_CTL1			0xC8250
5368 #define   BXT_BLC_PWM_ENABLE			(1 << 31)
5369 #define   BXT_BLC_PWM_POLARITY			(1 << 29)
5370 #define _BXT_BLC_PWM_FREQ1			0xC8254
5371 #define _BXT_BLC_PWM_DUTY1			0xC8258
5372 
5373 #define _BXT_BLC_PWM_CTL2			0xC8350
5374 #define _BXT_BLC_PWM_FREQ2			0xC8354
5375 #define _BXT_BLC_PWM_DUTY2			0xC8358
5376 
5377 #define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
5378 					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
5379 #define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
5380 					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
5381 #define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
5382 					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
5383 
5384 #define PCH_GTC_CTL		_MMIO(0xe7000)
5385 #define   PCH_GTC_ENABLE	(1 << 31)
5386 
5387 /* TV port control */
5388 #define TV_CTL			_MMIO(0x68000)
5389 /* Enables the TV encoder */
5390 # define TV_ENC_ENABLE			(1 << 31)
5391 /* Sources the TV encoder input from pipe B instead of A. */
5392 # define TV_ENC_PIPE_SEL_SHIFT		30
5393 # define TV_ENC_PIPE_SEL_MASK		(1 << 30)
5394 # define TV_ENC_PIPE_SEL(pipe)		((pipe) << 30)
5395 /* Outputs composite video (DAC A only) */
5396 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
5397 /* Outputs SVideo video (DAC B/C) */
5398 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
5399 /* Outputs Component video (DAC A/B/C) */
5400 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
5401 /* Outputs Composite and SVideo (DAC A/B/C) */
5402 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
5403 # define TV_TRILEVEL_SYNC		(1 << 21)
5404 /* Enables slow sync generation (945GM only) */
5405 # define TV_SLOW_SYNC			(1 << 20)
5406 /* Selects 4x oversampling for 480i and 576p */
5407 # define TV_OVERSAMPLE_4X		(0 << 18)
5408 /* Selects 2x oversampling for 720p and 1080i */
5409 # define TV_OVERSAMPLE_2X		(1 << 18)
5410 /* Selects no oversampling for 1080p */
5411 # define TV_OVERSAMPLE_NONE		(2 << 18)
5412 /* Selects 8x oversampling */
5413 # define TV_OVERSAMPLE_8X		(3 << 18)
5414 # define TV_OVERSAMPLE_MASK		(3 << 18)
5415 /* Selects progressive mode rather than interlaced */
5416 # define TV_PROGRESSIVE			(1 << 17)
5417 /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
5418 # define TV_PAL_BURST			(1 << 16)
5419 /* Field for setting delay of Y compared to C */
5420 # define TV_YC_SKEW_MASK		(7 << 12)
5421 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
5422 # define TV_ENC_SDP_FIX			(1 << 11)
5423 /*
5424  * Enables a fix for the 915GM only.
5425  *
5426  * Not sure what it does.
5427  */
5428 # define TV_ENC_C0_FIX			(1 << 10)
5429 /* Bits that must be preserved by software */
5430 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5431 # define TV_FUSE_STATE_MASK		(3 << 4)
5432 /* Read-only state that reports all features enabled */
5433 # define TV_FUSE_STATE_ENABLED		(0 << 4)
5434 /* Read-only state that reports that Macrovision is disabled in hardware*/
5435 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
5436 /* Read-only state that reports that TV-out is disabled in hardware. */
5437 # define TV_FUSE_STATE_DISABLED		(2 << 4)
5438 /* Normal operation */
5439 # define TV_TEST_MODE_NORMAL		(0 << 0)
5440 /* Encoder test pattern 1 - combo pattern */
5441 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
5442 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5443 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
5444 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5445 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
5446 /* Encoder test pattern 4 - random noise */
5447 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
5448 /* Encoder test pattern 5 - linear color ramps */
5449 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
5450 /*
5451  * This test mode forces the DACs to 50% of full output.
5452  *
5453  * This is used for load detection in combination with TVDAC_SENSE_MASK
5454  */
5455 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
5456 # define TV_TEST_MODE_MASK		(7 << 0)
5457 
5458 #define TV_DAC			_MMIO(0x68004)
5459 # define TV_DAC_SAVE		0x00ffff00
5460 /*
5461  * Reports that DAC state change logic has reported change (RO).
5462  *
5463  * This gets cleared when TV_DAC_STATE_EN is cleared
5464 */
5465 # define TVDAC_STATE_CHG		(1 << 31)
5466 # define TVDAC_SENSE_MASK		(7 << 28)
5467 /* Reports that DAC A voltage is above the detect threshold */
5468 # define TVDAC_A_SENSE			(1 << 30)
5469 /* Reports that DAC B voltage is above the detect threshold */
5470 # define TVDAC_B_SENSE			(1 << 29)
5471 /* Reports that DAC C voltage is above the detect threshold */
5472 # define TVDAC_C_SENSE			(1 << 28)
5473 /*
5474  * Enables DAC state detection logic, for load-based TV detection.
5475  *
5476  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5477  * to off, for load detection to work.
5478  */
5479 # define TVDAC_STATE_CHG_EN		(1 << 27)
5480 /* Sets the DAC A sense value to high */
5481 # define TVDAC_A_SENSE_CTL		(1 << 26)
5482 /* Sets the DAC B sense value to high */
5483 # define TVDAC_B_SENSE_CTL		(1 << 25)
5484 /* Sets the DAC C sense value to high */
5485 # define TVDAC_C_SENSE_CTL		(1 << 24)
5486 /* Overrides the ENC_ENABLE and DAC voltage levels */
5487 # define DAC_CTL_OVERRIDE		(1 << 7)
5488 /* Sets the slew rate.  Must be preserved in software */
5489 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
5490 # define DAC_A_1_3_V			(0 << 4)
5491 # define DAC_A_1_1_V			(1 << 4)
5492 # define DAC_A_0_7_V			(2 << 4)
5493 # define DAC_A_MASK			(3 << 4)
5494 # define DAC_B_1_3_V			(0 << 2)
5495 # define DAC_B_1_1_V			(1 << 2)
5496 # define DAC_B_0_7_V			(2 << 2)
5497 # define DAC_B_MASK			(3 << 2)
5498 # define DAC_C_1_3_V			(0 << 0)
5499 # define DAC_C_1_1_V			(1 << 0)
5500 # define DAC_C_0_7_V			(2 << 0)
5501 # define DAC_C_MASK			(3 << 0)
5502 
5503 /*
5504  * CSC coefficients are stored in a floating point format with 9 bits of
5505  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
5506  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5507  * -1 (0x3) being the only legal negative value.
5508  */
5509 #define TV_CSC_Y		_MMIO(0x68010)
5510 # define TV_RY_MASK			0x07ff0000
5511 # define TV_RY_SHIFT			16
5512 # define TV_GY_MASK			0x00000fff
5513 # define TV_GY_SHIFT			0
5514 
5515 #define TV_CSC_Y2		_MMIO(0x68014)
5516 # define TV_BY_MASK			0x07ff0000
5517 # define TV_BY_SHIFT			16
5518 /*
5519  * Y attenuation for component video.
5520  *
5521  * Stored in 1.9 fixed point.
5522  */
5523 # define TV_AY_MASK			0x000003ff
5524 # define TV_AY_SHIFT			0
5525 
5526 #define TV_CSC_U		_MMIO(0x68018)
5527 # define TV_RU_MASK			0x07ff0000
5528 # define TV_RU_SHIFT			16
5529 # define TV_GU_MASK			0x000007ff
5530 # define TV_GU_SHIFT			0
5531 
5532 #define TV_CSC_U2		_MMIO(0x6801c)
5533 # define TV_BU_MASK			0x07ff0000
5534 # define TV_BU_SHIFT			16
5535 /*
5536  * U attenuation for component video.
5537  *
5538  * Stored in 1.9 fixed point.
5539  */
5540 # define TV_AU_MASK			0x000003ff
5541 # define TV_AU_SHIFT			0
5542 
5543 #define TV_CSC_V		_MMIO(0x68020)
5544 # define TV_RV_MASK			0x0fff0000
5545 # define TV_RV_SHIFT			16
5546 # define TV_GV_MASK			0x000007ff
5547 # define TV_GV_SHIFT			0
5548 
5549 #define TV_CSC_V2		_MMIO(0x68024)
5550 # define TV_BV_MASK			0x07ff0000
5551 # define TV_BV_SHIFT			16
5552 /*
5553  * V attenuation for component video.
5554  *
5555  * Stored in 1.9 fixed point.
5556  */
5557 # define TV_AV_MASK			0x000007ff
5558 # define TV_AV_SHIFT			0
5559 
5560 #define TV_CLR_KNOBS		_MMIO(0x68028)
5561 /* 2s-complement brightness adjustment */
5562 # define TV_BRIGHTNESS_MASK		0xff000000
5563 # define TV_BRIGHTNESS_SHIFT		24
5564 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5565 # define TV_CONTRAST_MASK		0x00ff0000
5566 # define TV_CONTRAST_SHIFT		16
5567 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5568 # define TV_SATURATION_MASK		0x0000ff00
5569 # define TV_SATURATION_SHIFT		8
5570 /* Hue adjustment, as an integer phase angle in degrees */
5571 # define TV_HUE_MASK			0x000000ff
5572 # define TV_HUE_SHIFT			0
5573 
5574 #define TV_CLR_LEVEL		_MMIO(0x6802c)
5575 /* Controls the DAC level for black */
5576 # define TV_BLACK_LEVEL_MASK		0x01ff0000
5577 # define TV_BLACK_LEVEL_SHIFT		16
5578 /* Controls the DAC level for blanking */
5579 # define TV_BLANK_LEVEL_MASK		0x000001ff
5580 # define TV_BLANK_LEVEL_SHIFT		0
5581 
5582 #define TV_H_CTL_1		_MMIO(0x68030)
5583 /* Number of pixels in the hsync. */
5584 # define TV_HSYNC_END_MASK		0x1fff0000
5585 # define TV_HSYNC_END_SHIFT		16
5586 /* Total number of pixels minus one in the line (display and blanking). */
5587 # define TV_HTOTAL_MASK			0x00001fff
5588 # define TV_HTOTAL_SHIFT		0
5589 
5590 #define TV_H_CTL_2		_MMIO(0x68034)
5591 /* Enables the colorburst (needed for non-component color) */
5592 # define TV_BURST_ENA			(1 << 31)
5593 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5594 # define TV_HBURST_START_SHIFT		16
5595 # define TV_HBURST_START_MASK		0x1fff0000
5596 /* Length of the colorburst */
5597 # define TV_HBURST_LEN_SHIFT		0
5598 # define TV_HBURST_LEN_MASK		0x0001fff
5599 
5600 #define TV_H_CTL_3		_MMIO(0x68038)
5601 /* End of hblank, measured in pixels minus one from start of hsync */
5602 # define TV_HBLANK_END_SHIFT		16
5603 # define TV_HBLANK_END_MASK		0x1fff0000
5604 /* Start of hblank, measured in pixels minus one from start of hsync */
5605 # define TV_HBLANK_START_SHIFT		0
5606 # define TV_HBLANK_START_MASK		0x0001fff
5607 
5608 #define TV_V_CTL_1		_MMIO(0x6803c)
5609 /* XXX */
5610 # define TV_NBR_END_SHIFT		16
5611 # define TV_NBR_END_MASK		0x07ff0000
5612 /* XXX */
5613 # define TV_VI_END_F1_SHIFT		8
5614 # define TV_VI_END_F1_MASK		0x00003f00
5615 /* XXX */
5616 # define TV_VI_END_F2_SHIFT		0
5617 # define TV_VI_END_F2_MASK		0x0000003f
5618 
5619 #define TV_V_CTL_2		_MMIO(0x68040)
5620 /* Length of vsync, in half lines */
5621 # define TV_VSYNC_LEN_MASK		0x07ff0000
5622 # define TV_VSYNC_LEN_SHIFT		16
5623 /* Offset of the start of vsync in field 1, measured in one less than the
5624  * number of half lines.
5625  */
5626 # define TV_VSYNC_START_F1_MASK		0x00007f00
5627 # define TV_VSYNC_START_F1_SHIFT	8
5628 /*
5629  * Offset of the start of vsync in field 2, measured in one less than the
5630  * number of half lines.
5631  */
5632 # define TV_VSYNC_START_F2_MASK		0x0000007f
5633 # define TV_VSYNC_START_F2_SHIFT	0
5634 
5635 #define TV_V_CTL_3		_MMIO(0x68044)
5636 /* Enables generation of the equalization signal */
5637 # define TV_EQUAL_ENA			(1 << 31)
5638 /* Length of vsync, in half lines */
5639 # define TV_VEQ_LEN_MASK		0x007f0000
5640 # define TV_VEQ_LEN_SHIFT		16
5641 /* Offset of the start of equalization in field 1, measured in one less than
5642  * the number of half lines.
5643  */
5644 # define TV_VEQ_START_F1_MASK		0x0007f00
5645 # define TV_VEQ_START_F1_SHIFT		8
5646 /*
5647  * Offset of the start of equalization in field 2, measured in one less than
5648  * the number of half lines.
5649  */
5650 # define TV_VEQ_START_F2_MASK		0x000007f
5651 # define TV_VEQ_START_F2_SHIFT		0
5652 
5653 #define TV_V_CTL_4		_MMIO(0x68048)
5654 /*
5655  * Offset to start of vertical colorburst, measured in one less than the
5656  * number of lines from vertical start.
5657  */
5658 # define TV_VBURST_START_F1_MASK	0x003f0000
5659 # define TV_VBURST_START_F1_SHIFT	16
5660 /*
5661  * Offset to the end of vertical colorburst, measured in one less than the
5662  * number of lines from the start of NBR.
5663  */
5664 # define TV_VBURST_END_F1_MASK		0x000000ff
5665 # define TV_VBURST_END_F1_SHIFT		0
5666 
5667 #define TV_V_CTL_5		_MMIO(0x6804c)
5668 /*
5669  * Offset to start of vertical colorburst, measured in one less than the
5670  * number of lines from vertical start.
5671  */
5672 # define TV_VBURST_START_F2_MASK	0x003f0000
5673 # define TV_VBURST_START_F2_SHIFT	16
5674 /*
5675  * Offset to the end of vertical colorburst, measured in one less than the
5676  * number of lines from the start of NBR.
5677  */
5678 # define TV_VBURST_END_F2_MASK		0x000000ff
5679 # define TV_VBURST_END_F2_SHIFT		0
5680 
5681 #define TV_V_CTL_6		_MMIO(0x68050)
5682 /*
5683  * Offset to start of vertical colorburst, measured in one less than the
5684  * number of lines from vertical start.
5685  */
5686 # define TV_VBURST_START_F3_MASK	0x003f0000
5687 # define TV_VBURST_START_F3_SHIFT	16
5688 /*
5689  * Offset to the end of vertical colorburst, measured in one less than the
5690  * number of lines from the start of NBR.
5691  */
5692 # define TV_VBURST_END_F3_MASK		0x000000ff
5693 # define TV_VBURST_END_F3_SHIFT		0
5694 
5695 #define TV_V_CTL_7		_MMIO(0x68054)
5696 /*
5697  * Offset to start of vertical colorburst, measured in one less than the
5698  * number of lines from vertical start.
5699  */
5700 # define TV_VBURST_START_F4_MASK	0x003f0000
5701 # define TV_VBURST_START_F4_SHIFT	16
5702 /*
5703  * Offset to the end of vertical colorburst, measured in one less than the
5704  * number of lines from the start of NBR.
5705  */
5706 # define TV_VBURST_END_F4_MASK		0x000000ff
5707 # define TV_VBURST_END_F4_SHIFT		0
5708 
5709 #define TV_SC_CTL_1		_MMIO(0x68060)
5710 /* Turns on the first subcarrier phase generation DDA */
5711 # define TV_SC_DDA1_EN			(1 << 31)
5712 /* Turns on the first subcarrier phase generation DDA */
5713 # define TV_SC_DDA2_EN			(1 << 30)
5714 /* Turns on the first subcarrier phase generation DDA */
5715 # define TV_SC_DDA3_EN			(1 << 29)
5716 /* Sets the subcarrier DDA to reset frequency every other field */
5717 # define TV_SC_RESET_EVERY_2		(0 << 24)
5718 /* Sets the subcarrier DDA to reset frequency every fourth field */
5719 # define TV_SC_RESET_EVERY_4		(1 << 24)
5720 /* Sets the subcarrier DDA to reset frequency every eighth field */
5721 # define TV_SC_RESET_EVERY_8		(2 << 24)
5722 /* Sets the subcarrier DDA to never reset the frequency */
5723 # define TV_SC_RESET_NEVER		(3 << 24)
5724 /* Sets the peak amplitude of the colorburst.*/
5725 # define TV_BURST_LEVEL_MASK		0x00ff0000
5726 # define TV_BURST_LEVEL_SHIFT		16
5727 /* Sets the increment of the first subcarrier phase generation DDA */
5728 # define TV_SCDDA1_INC_MASK		0x00000fff
5729 # define TV_SCDDA1_INC_SHIFT		0
5730 
5731 #define TV_SC_CTL_2		_MMIO(0x68064)
5732 /* Sets the rollover for the second subcarrier phase generation DDA */
5733 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
5734 # define TV_SCDDA2_SIZE_SHIFT		16
5735 /* Sets the increent of the second subcarrier phase generation DDA */
5736 # define TV_SCDDA2_INC_MASK		0x00007fff
5737 # define TV_SCDDA2_INC_SHIFT		0
5738 
5739 #define TV_SC_CTL_3		_MMIO(0x68068)
5740 /* Sets the rollover for the third subcarrier phase generation DDA */
5741 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
5742 # define TV_SCDDA3_SIZE_SHIFT		16
5743 /* Sets the increent of the third subcarrier phase generation DDA */
5744 # define TV_SCDDA3_INC_MASK		0x00007fff
5745 # define TV_SCDDA3_INC_SHIFT		0
5746 
5747 #define TV_WIN_POS		_MMIO(0x68070)
5748 /* X coordinate of the display from the start of horizontal active */
5749 # define TV_XPOS_MASK			0x1fff0000
5750 # define TV_XPOS_SHIFT			16
5751 /* Y coordinate of the display from the start of vertical active (NBR) */
5752 # define TV_YPOS_MASK			0x00000fff
5753 # define TV_YPOS_SHIFT			0
5754 
5755 #define TV_WIN_SIZE		_MMIO(0x68074)
5756 /* Horizontal size of the display window, measured in pixels*/
5757 # define TV_XSIZE_MASK			0x1fff0000
5758 # define TV_XSIZE_SHIFT			16
5759 /*
5760  * Vertical size of the display window, measured in pixels.
5761  *
5762  * Must be even for interlaced modes.
5763  */
5764 # define TV_YSIZE_MASK			0x00000fff
5765 # define TV_YSIZE_SHIFT			0
5766 
5767 #define TV_FILTER_CTL_1		_MMIO(0x68080)
5768 /*
5769  * Enables automatic scaling calculation.
5770  *
5771  * If set, the rest of the registers are ignored, and the calculated values can
5772  * be read back from the register.
5773  */
5774 # define TV_AUTO_SCALE			(1 << 31)
5775 /*
5776  * Disables the vertical filter.
5777  *
5778  * This is required on modes more than 1024 pixels wide */
5779 # define TV_V_FILTER_BYPASS		(1 << 29)
5780 /* Enables adaptive vertical filtering */
5781 # define TV_VADAPT			(1 << 28)
5782 # define TV_VADAPT_MODE_MASK		(3 << 26)
5783 /* Selects the least adaptive vertical filtering mode */
5784 # define TV_VADAPT_MODE_LEAST		(0 << 26)
5785 /* Selects the moderately adaptive vertical filtering mode */
5786 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
5787 /* Selects the most adaptive vertical filtering mode */
5788 # define TV_VADAPT_MODE_MOST		(3 << 26)
5789 /*
5790  * Sets the horizontal scaling factor.
5791  *
5792  * This should be the fractional part of the horizontal scaling factor divided
5793  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
5794  *
5795  * (src width - 1) / ((oversample * dest width) - 1)
5796  */
5797 # define TV_HSCALE_FRAC_MASK		0x00003fff
5798 # define TV_HSCALE_FRAC_SHIFT		0
5799 
5800 #define TV_FILTER_CTL_2		_MMIO(0x68084)
5801 /*
5802  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5803  *
5804  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5805  */
5806 # define TV_VSCALE_INT_MASK		0x00038000
5807 # define TV_VSCALE_INT_SHIFT		15
5808 /*
5809  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5810  *
5811  * \sa TV_VSCALE_INT_MASK
5812  */
5813 # define TV_VSCALE_FRAC_MASK		0x00007fff
5814 # define TV_VSCALE_FRAC_SHIFT		0
5815 
5816 #define TV_FILTER_CTL_3		_MMIO(0x68088)
5817 /*
5818  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5819  *
5820  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5821  *
5822  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5823  */
5824 # define TV_VSCALE_IP_INT_MASK		0x00038000
5825 # define TV_VSCALE_IP_INT_SHIFT		15
5826 /*
5827  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5828  *
5829  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5830  *
5831  * \sa TV_VSCALE_IP_INT_MASK
5832  */
5833 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
5834 # define TV_VSCALE_IP_FRAC_SHIFT		0
5835 
5836 #define TV_CC_CONTROL		_MMIO(0x68090)
5837 # define TV_CC_ENABLE			(1 << 31)
5838 /*
5839  * Specifies which field to send the CC data in.
5840  *
5841  * CC data is usually sent in field 0.
5842  */
5843 # define TV_CC_FID_MASK			(1 << 27)
5844 # define TV_CC_FID_SHIFT		27
5845 /* Sets the horizontal position of the CC data.  Usually 135. */
5846 # define TV_CC_HOFF_MASK		0x03ff0000
5847 # define TV_CC_HOFF_SHIFT		16
5848 /* Sets the vertical position of the CC data.  Usually 21 */
5849 # define TV_CC_LINE_MASK		0x0000003f
5850 # define TV_CC_LINE_SHIFT		0
5851 
5852 #define TV_CC_DATA		_MMIO(0x68094)
5853 # define TV_CC_RDY			(1 << 31)
5854 /* Second word of CC data to be transmitted. */
5855 # define TV_CC_DATA_2_MASK		0x007f0000
5856 # define TV_CC_DATA_2_SHIFT		16
5857 /* First word of CC data to be transmitted. */
5858 # define TV_CC_DATA_1_MASK		0x0000007f
5859 # define TV_CC_DATA_1_SHIFT		0
5860 
5861 #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
5862 #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
5863 #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
5864 #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
5865 
5866 /* Display Port */
5867 #define DP_A			_MMIO(0x64000) /* eDP */
5868 #define DP_B			_MMIO(0x64100)
5869 #define DP_C			_MMIO(0x64200)
5870 #define DP_D			_MMIO(0x64300)
5871 
5872 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
5873 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
5874 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
5875 
5876 #define   DP_PORT_EN			(1 << 31)
5877 #define   DP_PIPE_SEL_SHIFT		30
5878 #define   DP_PIPE_SEL_MASK		(1 << 30)
5879 #define   DP_PIPE_SEL(pipe)		((pipe) << 30)
5880 #define   DP_PIPE_SEL_SHIFT_IVB		29
5881 #define   DP_PIPE_SEL_MASK_IVB		(3 << 29)
5882 #define   DP_PIPE_SEL_IVB(pipe)		((pipe) << 29)
5883 #define   DP_PIPE_SEL_SHIFT_CHV		16
5884 #define   DP_PIPE_SEL_MASK_CHV		(3 << 16)
5885 #define   DP_PIPE_SEL_CHV(pipe)		((pipe) << 16)
5886 
5887 /* Link training mode - select a suitable mode for each stage */
5888 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
5889 #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
5890 #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
5891 #define   DP_LINK_TRAIN_OFF		(3 << 28)
5892 #define   DP_LINK_TRAIN_MASK		(3 << 28)
5893 #define   DP_LINK_TRAIN_SHIFT		28
5894 
5895 /* CPT Link training mode */
5896 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
5897 #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
5898 #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
5899 #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
5900 #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
5901 #define   DP_LINK_TRAIN_SHIFT_CPT	8
5902 
5903 /* Signal voltages. These are mostly controlled by the other end */
5904 #define   DP_VOLTAGE_0_4		(0 << 25)
5905 #define   DP_VOLTAGE_0_6		(1 << 25)
5906 #define   DP_VOLTAGE_0_8		(2 << 25)
5907 #define   DP_VOLTAGE_1_2		(3 << 25)
5908 #define   DP_VOLTAGE_MASK		(7 << 25)
5909 #define   DP_VOLTAGE_SHIFT		25
5910 
5911 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5912  * they want
5913  */
5914 #define   DP_PRE_EMPHASIS_0		(0 << 22)
5915 #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
5916 #define   DP_PRE_EMPHASIS_6		(2 << 22)
5917 #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
5918 #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
5919 #define   DP_PRE_EMPHASIS_SHIFT		22
5920 
5921 /* How many wires to use. I guess 3 was too hard */
5922 #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
5923 #define   DP_PORT_WIDTH_MASK		(7 << 19)
5924 #define   DP_PORT_WIDTH_SHIFT		19
5925 
5926 /* Mystic DPCD version 1.1 special mode */
5927 #define   DP_ENHANCED_FRAMING		(1 << 18)
5928 
5929 /* eDP */
5930 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
5931 #define   DP_PLL_FREQ_162MHZ		(1 << 16)
5932 #define   DP_PLL_FREQ_MASK		(3 << 16)
5933 
5934 /* locked once port is enabled */
5935 #define   DP_PORT_REVERSAL		(1 << 15)
5936 
5937 /* eDP */
5938 #define   DP_PLL_ENABLE			(1 << 14)
5939 
5940 /* sends the clock on lane 15 of the PEG for debug */
5941 #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
5942 
5943 #define   DP_SCRAMBLING_DISABLE		(1 << 12)
5944 #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
5945 
5946 /* limit RGB values to avoid confusing TVs */
5947 #define   DP_COLOR_RANGE_16_235		(1 << 8)
5948 
5949 /* Turn on the audio link */
5950 #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
5951 
5952 /* vs and hs sync polarity */
5953 #define   DP_SYNC_VS_HIGH		(1 << 4)
5954 #define   DP_SYNC_HS_HIGH		(1 << 3)
5955 
5956 /* A fantasy */
5957 #define   DP_DETECTED			(1 << 2)
5958 
5959 /* The aux channel provides a way to talk to the
5960  * signal sink for DDC etc. Max packet size supported
5961  * is 20 bytes in each direction, hence the 5 fixed
5962  * data registers
5963  */
5964 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5965 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5966 
5967 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5968 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5969 
5970 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5971 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5972 
5973 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
5974 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
5975 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
5976 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
5977 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
5978 #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
5979 #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
5980 #define   DP_AUX_CH_CTL_TIME_OUT_MAX	    (3 << 26) /* Varies per platform */
5981 #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
5982 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
5983 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5984 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
5985 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5986 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
5987 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
5988 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
5989 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
5990 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
5991 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
5992 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5993 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5994 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
5995 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
5996 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
5997 #define   DP_AUX_CH_CTL_TBT_IO			(1 << 11)
5998 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5999 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
6000 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
6001 
6002 /*
6003  * Computing GMCH M and N values for the Display Port link
6004  *
6005  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
6006  *
6007  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
6008  *
6009  * The GMCH value is used internally
6010  *
6011  * bytes_per_pixel is the number of bytes coming out of the plane,
6012  * which is after the LUTs, so we want the bytes for our color format.
6013  * For our current usage, this is always 3, one byte for R, G and B.
6014  */
6015 #define _PIPEA_DATA_M_G4X	0x70050
6016 #define _PIPEB_DATA_M_G4X	0x71050
6017 
6018 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
6019 #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
6020 #define  TU_SIZE_SHIFT		25
6021 #define  TU_SIZE_MASK           (0x3f << 25)
6022 
6023 #define  DATA_LINK_M_N_MASK	(0xffffff)
6024 #define  DATA_LINK_N_MAX	(0x800000)
6025 
6026 #define _PIPEA_DATA_N_G4X	0x70054
6027 #define _PIPEB_DATA_N_G4X	0x71054
6028 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
6029 
6030 /*
6031  * Computing Link M and N values for the Display Port link
6032  *
6033  * Link M / N = pixel_clock / ls_clk
6034  *
6035  * (the DP spec calls pixel_clock the 'strm_clk')
6036  *
6037  * The Link value is transmitted in the Main Stream
6038  * Attributes and VB-ID.
6039  */
6040 
6041 #define _PIPEA_LINK_M_G4X	0x70060
6042 #define _PIPEB_LINK_M_G4X	0x71060
6043 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
6044 
6045 #define _PIPEA_LINK_N_G4X	0x70064
6046 #define _PIPEB_LINK_N_G4X	0x71064
6047 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
6048 
6049 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
6050 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
6051 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
6052 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
6053 
6054 /* Display & cursor control */
6055 
6056 /* Pipe A */
6057 #define _PIPEADSL		0x70000
6058 #define   DSL_LINEMASK_GEN2	0x00000fff
6059 #define   DSL_LINEMASK_GEN3	0x00001fff
6060 #define _PIPEACONF		0x70008
6061 #define   PIPECONF_ENABLE	(1 << 31)
6062 #define   PIPECONF_DISABLE	0
6063 #define   PIPECONF_DOUBLE_WIDE	(1 << 30)
6064 #define   I965_PIPECONF_ACTIVE	(1 << 30)
6065 #define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
6066 #define   PIPECONF_FRAME_START_DELAY_MASK	(3 << 27) /* pre-hsw */
6067 #define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
6068 #define   PIPECONF_SINGLE_WIDE	0
6069 #define   PIPECONF_PIPE_UNLOCKED 0
6070 #define   PIPECONF_PIPE_LOCKED	(1 << 25)
6071 #define   PIPECONF_FORCE_BORDER	(1 << 25)
6072 #define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
6073 #define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
6074 #define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
6075 #define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
6076 #define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
6077 #define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
6078 #define   PIPECONF_GAMMA_MODE(x)	((x) << 24) /* pass in GAMMA_MODE_MODE_* */
6079 #define   PIPECONF_GAMMA_MODE_SHIFT	24
6080 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
6081 #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
6082 /* Note that pre-gen3 does not support interlaced display directly. Panel
6083  * fitting must be disabled on pre-ilk for interlaced. */
6084 #define   PIPECONF_PROGRESSIVE			(0 << 21)
6085 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
6086 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
6087 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
6088 #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
6089 /* Ironlake and later have a complete new set of values for interlaced. PFIT
6090  * means panel fitter required, PF means progressive fetch, DBL means power
6091  * saving pixel doubling. */
6092 #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
6093 #define   PIPECONF_INTERLACED_ILK		(3 << 21)
6094 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
6095 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
6096 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
6097 #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
6098 #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
6099 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
6100 #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
6101 #define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
6102 #define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
6103 #define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
6104 #define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
6105 #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only */
6106 #define   PIPECONF_BPC_MASK	(0x7 << 5)
6107 #define   PIPECONF_8BPC		(0 << 5)
6108 #define   PIPECONF_10BPC	(1 << 5)
6109 #define   PIPECONF_6BPC		(2 << 5)
6110 #define   PIPECONF_12BPC	(3 << 5)
6111 #define   PIPECONF_DITHER_EN	(1 << 4)
6112 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
6113 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
6114 #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
6115 #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
6116 #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
6117 #define _PIPEASTAT		0x70024
6118 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
6119 #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
6120 #define   PIPE_CRC_ERROR_ENABLE			(1UL << 29)
6121 #define   PIPE_CRC_DONE_ENABLE			(1UL << 28)
6122 #define   PERF_COUNTER2_INTERRUPT_EN		(1UL << 27)
6123 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL << 27)
6124 #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL << 26)
6125 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL << 26)
6126 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL << 25)
6127 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL << 24)
6128 #define   PIPE_DPST_EVENT_ENABLE		(1UL << 23)
6129 #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL << 22)
6130 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL << 22)
6131 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL << 21)
6132 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL << 20)
6133 #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL << 19)
6134 #define   PERF_COUNTER_INTERRUPT_EN		(1UL << 19)
6135 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL << 18) /* pre-965 */
6136 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL << 18) /* 965 or later */
6137 #define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL << 17)
6138 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL << 17)
6139 #define   PIPEA_HBLANK_INT_EN_VLV		(1UL << 16)
6140 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL << 16)
6141 #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV	(1UL << 15)
6142 #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL << 14)
6143 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL << 13)
6144 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL << 12)
6145 #define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL << 11)
6146 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL << 11)
6147 #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL << 10)
6148 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL << 10)
6149 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL << 9)
6150 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL << 8)
6151 #define   PIPE_DPST_EVENT_STATUS		(1UL << 7)
6152 #define   PIPE_A_PSR_STATUS_VLV			(1UL << 6)
6153 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL << 6)
6154 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL << 5)
6155 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL << 4)
6156 #define   PIPE_B_PSR_STATUS_VLV			(1UL << 3)
6157 #define   PERF_COUNTER_INTERRUPT_STATUS		(1UL << 3)
6158 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL << 2) /* pre-965 */
6159 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL << 2) /* 965 or later */
6160 #define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL << 1)
6161 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)
6162 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
6163 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
6164 
6165 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
6166 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
6167 
6168 #define PIPE_A_OFFSET		0x70000
6169 #define PIPE_B_OFFSET		0x71000
6170 #define PIPE_C_OFFSET		0x72000
6171 #define PIPE_D_OFFSET		0x73000
6172 #define CHV_PIPE_C_OFFSET	0x74000
6173 /*
6174  * There's actually no pipe EDP. Some pipe registers have
6175  * simply shifted from the pipe to the transcoder, while
6176  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
6177  * to access such registers in transcoder EDP.
6178  */
6179 #define PIPE_EDP_OFFSET	0x7f000
6180 
6181 /* ICL DSI 0 and 1 */
6182 #define PIPE_DSI0_OFFSET	0x7b000
6183 #define PIPE_DSI1_OFFSET	0x7b800
6184 
6185 #define PIPECONF(pipe)		_MMIO_PIPE2(pipe, _PIPEACONF)
6186 #define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
6187 #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
6188 #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
6189 #define PIPESTAT(pipe)		_MMIO_PIPE2(pipe, _PIPEASTAT)
6190 
6191 #define  _PIPEAGCMAX           0x70010
6192 #define  _PIPEBGCMAX           0x71010
6193 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
6194 
6195 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
6196 #define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
6197 #define   PIPE_ARB_USE_PROG_SLOTS	REG_BIT(13)
6198 
6199 #define _PIPE_MISC_A			0x70030
6200 #define _PIPE_MISC_B			0x71030
6201 #define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
6202 #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
6203 #define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
6204 #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
6205 #define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
6206 /*
6207  * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
6208  * valid values of: 6, 8, 10 BPC.
6209  * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
6210  * 6, 8, 10, 12 BPC.
6211  */
6212 #define   PIPEMISC_BPC_MASK		(7 << 5)
6213 #define   PIPEMISC_8_BPC		(0 << 5)
6214 #define   PIPEMISC_10_BPC		(1 << 5)
6215 #define   PIPEMISC_6_BPC		(2 << 5)
6216 #define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */
6217 #define   PIPEMISC_DITHER_ENABLE	(1 << 4)
6218 #define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
6219 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
6220 #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
6221 
6222 #define _PIPE_MISC2_A					0x7002C
6223 #define _PIPE_MISC2_B					0x7102C
6224 #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
6225 #define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
6226 #define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
6227 #define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
6228 
6229 /* Skylake+ pipe bottom (background) color */
6230 #define _SKL_BOTTOM_COLOR_A		0x70034
6231 #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
6232 #define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
6233 #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
6234 
6235 #define _ICL_PIPE_A_STATUS			0x70058
6236 #define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
6237 #define   PIPE_STATUS_UNDERRUN				REG_BIT(31)
6238 #define   PIPE_STATUS_SOFT_UNDERRUN_XELPD		REG_BIT(28)
6239 #define   PIPE_STATUS_HARD_UNDERRUN_XELPD		REG_BIT(27)
6240 #define   PIPE_STATUS_PORT_UNDERRUN_XELPD		REG_BIT(26)
6241 
6242 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
6243 #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
6244 #define   PIPEB_HLINE_INT_EN			(1 << 28)
6245 #define   PIPEB_VBLANK_INT_EN			(1 << 27)
6246 #define   SPRITED_FLIP_DONE_INT_EN		(1 << 26)
6247 #define   SPRITEC_FLIP_DONE_INT_EN		(1 << 25)
6248 #define   PLANEB_FLIP_DONE_INT_EN		(1 << 24)
6249 #define   PIPE_PSR_INT_EN			(1 << 22)
6250 #define   PIPEA_LINE_COMPARE_INT_EN		(1 << 21)
6251 #define   PIPEA_HLINE_INT_EN			(1 << 20)
6252 #define   PIPEA_VBLANK_INT_EN			(1 << 19)
6253 #define   SPRITEB_FLIP_DONE_INT_EN		(1 << 18)
6254 #define   SPRITEA_FLIP_DONE_INT_EN		(1 << 17)
6255 #define   PLANEA_FLIPDONE_INT_EN		(1 << 16)
6256 #define   PIPEC_LINE_COMPARE_INT_EN		(1 << 13)
6257 #define   PIPEC_HLINE_INT_EN			(1 << 12)
6258 #define   PIPEC_VBLANK_INT_EN			(1 << 11)
6259 #define   SPRITEF_FLIPDONE_INT_EN		(1 << 10)
6260 #define   SPRITEE_FLIPDONE_INT_EN		(1 << 9)
6261 #define   PLANEC_FLIPDONE_INT_EN		(1 << 8)
6262 
6263 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
6264 #define   SPRITEF_INVALID_GTT_INT_EN		(1 << 27)
6265 #define   SPRITEE_INVALID_GTT_INT_EN		(1 << 26)
6266 #define   PLANEC_INVALID_GTT_INT_EN		(1 << 25)
6267 #define   CURSORC_INVALID_GTT_INT_EN		(1 << 24)
6268 #define   CURSORB_INVALID_GTT_INT_EN		(1 << 23)
6269 #define   CURSORA_INVALID_GTT_INT_EN		(1 << 22)
6270 #define   SPRITED_INVALID_GTT_INT_EN		(1 << 21)
6271 #define   SPRITEC_INVALID_GTT_INT_EN		(1 << 20)
6272 #define   PLANEB_INVALID_GTT_INT_EN		(1 << 19)
6273 #define   SPRITEB_INVALID_GTT_INT_EN		(1 << 18)
6274 #define   SPRITEA_INVALID_GTT_INT_EN		(1 << 17)
6275 #define   PLANEA_INVALID_GTT_INT_EN		(1 << 16)
6276 #define   DPINVGTT_EN_MASK			0xff0000
6277 #define   DPINVGTT_EN_MASK_CHV			0xfff0000
6278 #define   SPRITEF_INVALID_GTT_STATUS		(1 << 11)
6279 #define   SPRITEE_INVALID_GTT_STATUS		(1 << 10)
6280 #define   PLANEC_INVALID_GTT_STATUS		(1 << 9)
6281 #define   CURSORC_INVALID_GTT_STATUS		(1 << 8)
6282 #define   CURSORB_INVALID_GTT_STATUS		(1 << 7)
6283 #define   CURSORA_INVALID_GTT_STATUS		(1 << 6)
6284 #define   SPRITED_INVALID_GTT_STATUS		(1 << 5)
6285 #define   SPRITEC_INVALID_GTT_STATUS		(1 << 4)
6286 #define   PLANEB_INVALID_GTT_STATUS		(1 << 3)
6287 #define   SPRITEB_INVALID_GTT_STATUS		(1 << 2)
6288 #define   SPRITEA_INVALID_GTT_STATUS		(1 << 1)
6289 #define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
6290 #define   DPINVGTT_STATUS_MASK			0xff
6291 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
6292 
6293 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
6294 #define   DSPARB_CSTART_MASK	(0x7f << 7)
6295 #define   DSPARB_CSTART_SHIFT	7
6296 #define   DSPARB_BSTART_MASK	(0x7f)
6297 #define   DSPARB_BSTART_SHIFT	0
6298 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
6299 #define   DSPARB_AEND_SHIFT	0
6300 #define   DSPARB_SPRITEA_SHIFT_VLV	0
6301 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
6302 #define   DSPARB_SPRITEB_SHIFT_VLV	8
6303 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
6304 #define   DSPARB_SPRITEC_SHIFT_VLV	16
6305 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
6306 #define   DSPARB_SPRITED_SHIFT_VLV	24
6307 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
6308 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
6309 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
6310 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
6311 #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
6312 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
6313 #define   DSPARB_SPRITEC_HI_SHIFT_VLV	8
6314 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
6315 #define   DSPARB_SPRITED_HI_SHIFT_VLV	12
6316 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
6317 #define   DSPARB_SPRITEE_HI_SHIFT_VLV	16
6318 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
6319 #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
6320 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
6321 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
6322 #define   DSPARB_SPRITEE_SHIFT_VLV	0
6323 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
6324 #define   DSPARB_SPRITEF_SHIFT_VLV	8
6325 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
6326 
6327 /* pnv/gen4/g4x/vlv/chv */
6328 #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
6329 #define   DSPFW_SR_SHIFT		23
6330 #define   DSPFW_SR_MASK			(0x1ff << 23)
6331 #define   DSPFW_CURSORB_SHIFT		16
6332 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
6333 #define   DSPFW_PLANEB_SHIFT		8
6334 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
6335 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
6336 #define   DSPFW_PLANEA_SHIFT		0
6337 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
6338 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
6339 #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
6340 #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
6341 #define   DSPFW_FBC_SR_SHIFT		28
6342 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
6343 #define   DSPFW_FBC_HPLL_SR_SHIFT	24
6344 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
6345 #define   DSPFW_SPRITEB_SHIFT		(16)
6346 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
6347 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
6348 #define   DSPFW_CURSORA_SHIFT		8
6349 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
6350 #define   DSPFW_PLANEC_OLD_SHIFT	0
6351 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
6352 #define   DSPFW_SPRITEA_SHIFT		0
6353 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
6354 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
6355 #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6356 #define   DSPFW_HPLL_SR_EN		(1 << 31)
6357 #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
6358 #define   DSPFW_CURSOR_SR_SHIFT		24
6359 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
6360 #define   DSPFW_HPLL_CURSOR_SHIFT	16
6361 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
6362 #define   DSPFW_HPLL_SR_SHIFT		0
6363 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
6364 
6365 /* vlv/chv */
6366 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
6367 #define   DSPFW_SPRITEB_WM1_SHIFT	16
6368 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
6369 #define   DSPFW_CURSORA_WM1_SHIFT	8
6370 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
6371 #define   DSPFW_SPRITEA_WM1_SHIFT	0
6372 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
6373 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
6374 #define   DSPFW_PLANEB_WM1_SHIFT	24
6375 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
6376 #define   DSPFW_PLANEA_WM1_SHIFT	16
6377 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
6378 #define   DSPFW_CURSORB_WM1_SHIFT	8
6379 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
6380 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
6381 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
6382 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
6383 #define   DSPFW_SR_WM1_SHIFT		0
6384 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
6385 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
6386 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
6387 #define   DSPFW_SPRITED_WM1_SHIFT	24
6388 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
6389 #define   DSPFW_SPRITED_SHIFT		16
6390 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
6391 #define   DSPFW_SPRITEC_WM1_SHIFT	8
6392 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
6393 #define   DSPFW_SPRITEC_SHIFT		0
6394 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
6395 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
6396 #define   DSPFW_SPRITEF_WM1_SHIFT	24
6397 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
6398 #define   DSPFW_SPRITEF_SHIFT		16
6399 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
6400 #define   DSPFW_SPRITEE_WM1_SHIFT	8
6401 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
6402 #define   DSPFW_SPRITEE_SHIFT		0
6403 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
6404 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
6405 #define   DSPFW_PLANEC_WM1_SHIFT	24
6406 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
6407 #define   DSPFW_PLANEC_SHIFT		16
6408 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
6409 #define   DSPFW_CURSORC_WM1_SHIFT	8
6410 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
6411 #define   DSPFW_CURSORC_SHIFT		0
6412 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
6413 
6414 /* vlv/chv high order bits */
6415 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
6416 #define   DSPFW_SR_HI_SHIFT		24
6417 #define   DSPFW_SR_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
6418 #define   DSPFW_SPRITEF_HI_SHIFT	23
6419 #define   DSPFW_SPRITEF_HI_MASK		(1 << 23)
6420 #define   DSPFW_SPRITEE_HI_SHIFT	22
6421 #define   DSPFW_SPRITEE_HI_MASK		(1 << 22)
6422 #define   DSPFW_PLANEC_HI_SHIFT		21
6423 #define   DSPFW_PLANEC_HI_MASK		(1 << 21)
6424 #define   DSPFW_SPRITED_HI_SHIFT	20
6425 #define   DSPFW_SPRITED_HI_MASK		(1 << 20)
6426 #define   DSPFW_SPRITEC_HI_SHIFT	16
6427 #define   DSPFW_SPRITEC_HI_MASK		(1 << 16)
6428 #define   DSPFW_PLANEB_HI_SHIFT		12
6429 #define   DSPFW_PLANEB_HI_MASK		(1 << 12)
6430 #define   DSPFW_SPRITEB_HI_SHIFT	8
6431 #define   DSPFW_SPRITEB_HI_MASK		(1 << 8)
6432 #define   DSPFW_SPRITEA_HI_SHIFT	4
6433 #define   DSPFW_SPRITEA_HI_MASK		(1 << 4)
6434 #define   DSPFW_PLANEA_HI_SHIFT		0
6435 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
6436 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
6437 #define   DSPFW_SR_WM1_HI_SHIFT		24
6438 #define   DSPFW_SR_WM1_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
6439 #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
6440 #define   DSPFW_SPRITEF_WM1_HI_MASK	(1 << 23)
6441 #define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
6442 #define   DSPFW_SPRITEE_WM1_HI_MASK	(1 << 22)
6443 #define   DSPFW_PLANEC_WM1_HI_SHIFT	21
6444 #define   DSPFW_PLANEC_WM1_HI_MASK	(1 << 21)
6445 #define   DSPFW_SPRITED_WM1_HI_SHIFT	20
6446 #define   DSPFW_SPRITED_WM1_HI_MASK	(1 << 20)
6447 #define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
6448 #define   DSPFW_SPRITEC_WM1_HI_MASK	(1 << 16)
6449 #define   DSPFW_PLANEB_WM1_HI_SHIFT	12
6450 #define   DSPFW_PLANEB_WM1_HI_MASK	(1 << 12)
6451 #define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
6452 #define   DSPFW_SPRITEB_WM1_HI_MASK	(1 << 8)
6453 #define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
6454 #define   DSPFW_SPRITEA_WM1_HI_MASK	(1 << 4)
6455 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
6456 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
6457 
6458 /* drain latency register values*/
6459 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6460 #define DDL_CURSOR_SHIFT		24
6461 #define DDL_SPRITE_SHIFT(sprite)	(8 + 8 * (sprite))
6462 #define DDL_PLANE_SHIFT			0
6463 #define DDL_PRECISION_HIGH		(1 << 7)
6464 #define DDL_PRECISION_LOW		(0 << 7)
6465 #define DRAIN_LATENCY_MASK		0x7f
6466 
6467 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
6468 #define  CBR_PND_DEADLINE_DISABLE	(1 << 31)
6469 #define  CBR_PWM_CLOCK_MUX_SELECT	(1 << 30)
6470 
6471 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
6472 #define  CBR_DPLLBMD_PIPE(pipe)		(1 << (7 + (pipe) * 11)) /* pipes B and C */
6473 
6474 /* FIFO watermark sizes etc */
6475 #define G4X_FIFO_LINE_SIZE	64
6476 #define I915_FIFO_LINE_SIZE	64
6477 #define I830_FIFO_LINE_SIZE	32
6478 
6479 #define VALLEYVIEW_FIFO_SIZE	255
6480 #define G4X_FIFO_SIZE		127
6481 #define I965_FIFO_SIZE		512
6482 #define I945_FIFO_SIZE		127
6483 #define I915_FIFO_SIZE		95
6484 #define I855GM_FIFO_SIZE	127 /* In cachelines */
6485 #define I830_FIFO_SIZE		95
6486 
6487 #define VALLEYVIEW_MAX_WM	0xff
6488 #define G4X_MAX_WM		0x3f
6489 #define I915_MAX_WM		0x3f
6490 
6491 #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
6492 #define PINEVIEW_FIFO_LINE_SIZE	64
6493 #define PINEVIEW_MAX_WM		0x1ff
6494 #define PINEVIEW_DFT_WM		0x3f
6495 #define PINEVIEW_DFT_HPLLOFF_WM	0
6496 #define PINEVIEW_GUARD_WM		10
6497 #define PINEVIEW_CURSOR_FIFO		64
6498 #define PINEVIEW_CURSOR_MAX_WM	0x3f
6499 #define PINEVIEW_CURSOR_DFT_WM	0
6500 #define PINEVIEW_CURSOR_GUARD_WM	5
6501 
6502 #define VALLEYVIEW_CURSOR_MAX_WM 64
6503 #define I965_CURSOR_FIFO	64
6504 #define I965_CURSOR_MAX_WM	32
6505 #define I965_CURSOR_DFT_WM	8
6506 
6507 /* Watermark register definitions for SKL */
6508 #define _CUR_WM_A_0		0x70140
6509 #define _CUR_WM_B_0		0x71140
6510 #define _CUR_WM_SAGV_A		0x70158
6511 #define _CUR_WM_SAGV_B		0x71158
6512 #define _CUR_WM_SAGV_TRANS_A	0x7015C
6513 #define _CUR_WM_SAGV_TRANS_B	0x7115C
6514 #define _CUR_WM_TRANS_A		0x70168
6515 #define _CUR_WM_TRANS_B		0x71168
6516 #define _PLANE_WM_1_A_0		0x70240
6517 #define _PLANE_WM_1_B_0		0x71240
6518 #define _PLANE_WM_2_A_0		0x70340
6519 #define _PLANE_WM_2_B_0		0x71340
6520 #define _PLANE_WM_SAGV_1_A	0x70258
6521 #define _PLANE_WM_SAGV_1_B	0x71258
6522 #define _PLANE_WM_SAGV_2_A	0x70358
6523 #define _PLANE_WM_SAGV_2_B	0x71358
6524 #define _PLANE_WM_SAGV_TRANS_1_A	0x7025C
6525 #define _PLANE_WM_SAGV_TRANS_1_B	0x7125C
6526 #define _PLANE_WM_SAGV_TRANS_2_A	0x7035C
6527 #define _PLANE_WM_SAGV_TRANS_2_B	0x7135C
6528 #define _PLANE_WM_TRANS_1_A	0x70268
6529 #define _PLANE_WM_TRANS_1_B	0x71268
6530 #define _PLANE_WM_TRANS_2_A	0x70368
6531 #define _PLANE_WM_TRANS_2_B	0x71368
6532 #define   PLANE_WM_EN		(1 << 31)
6533 #define   PLANE_WM_IGNORE_LINES	(1 << 30)
6534 #define   PLANE_WM_LINES_MASK	REG_GENMASK(26, 14)
6535 #define   PLANE_WM_BLOCKS_MASK	REG_GENMASK(11, 0)
6536 
6537 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6538 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6539 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
6540 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
6541 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
6542 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6543 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6544 #define _PLANE_WM_BASE(pipe, plane) \
6545 	_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6546 #define PLANE_WM(pipe, plane, level) \
6547 	_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6548 #define _PLANE_WM_SAGV_1(pipe) \
6549 	_PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
6550 #define _PLANE_WM_SAGV_2(pipe) \
6551 	_PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
6552 #define PLANE_WM_SAGV(pipe, plane) \
6553 	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
6554 #define _PLANE_WM_SAGV_TRANS_1(pipe) \
6555 	_PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
6556 #define _PLANE_WM_SAGV_TRANS_2(pipe) \
6557 	_PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
6558 #define PLANE_WM_SAGV_TRANS(pipe, plane) \
6559 	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
6560 #define _PLANE_WM_TRANS_1(pipe) \
6561 	_PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
6562 #define _PLANE_WM_TRANS_2(pipe) \
6563 	_PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
6564 #define PLANE_WM_TRANS(pipe, plane) \
6565 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6566 
6567 /* define the Watermark register on Ironlake */
6568 #define _WM0_PIPEA_ILK		0x45100
6569 #define _WM0_PIPEB_ILK		0x45104
6570 #define _WM0_PIPEC_IVB		0x45200
6571 #define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
6572 					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
6573 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
6574 #define  WM0_PIPE_PLANE_SHIFT	16
6575 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
6576 #define  WM0_PIPE_SPRITE_SHIFT	8
6577 #define  WM0_PIPE_CURSOR_MASK	(0xff)
6578 #define WM1_LP_ILK		_MMIO(0x45108)
6579 #define  WM1_LP_SR_EN		(1 << 31)
6580 #define  WM1_LP_LATENCY_SHIFT	24
6581 #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
6582 #define  WM1_LP_FBC_MASK	(0xf << 20)
6583 #define  WM1_LP_FBC_SHIFT	20
6584 #define  WM1_LP_FBC_SHIFT_BDW	19
6585 #define  WM1_LP_SR_MASK		(0x7ff << 8)
6586 #define  WM1_LP_SR_SHIFT	8
6587 #define  WM1_LP_CURSOR_MASK	(0xff)
6588 #define WM2_LP_ILK		_MMIO(0x4510c)
6589 #define  WM2_LP_EN		(1 << 31)
6590 #define WM3_LP_ILK		_MMIO(0x45110)
6591 #define  WM3_LP_EN		(1 << 31)
6592 #define WM1S_LP_ILK		_MMIO(0x45120)
6593 #define WM2S_LP_IVB		_MMIO(0x45124)
6594 #define WM3S_LP_IVB		_MMIO(0x45128)
6595 #define  WM1S_LP_EN		(1 << 31)
6596 
6597 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6598 	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6599 	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6600 
6601 /* Memory latency timer register */
6602 #define MLTR_ILK		_MMIO(0x11222)
6603 #define  MLTR_WM1_SHIFT		0
6604 #define  MLTR_WM2_SHIFT		8
6605 /* the unit of memory self-refresh latency time is 0.5us */
6606 #define  ILK_SRLT_MASK		0x3f
6607 
6608 
6609 /* the address where we get all kinds of latency value */
6610 #define SSKPD			_MMIO(0x5d10)
6611 #define SSKPD_WM_MASK		0x3f
6612 #define SSKPD_WM0_SHIFT		0
6613 #define SSKPD_WM1_SHIFT		8
6614 #define SSKPD_WM2_SHIFT		16
6615 #define SSKPD_WM3_SHIFT		24
6616 
6617 /*
6618  * The two pipe frame counter registers are not synchronized, so
6619  * reading a stable value is somewhat tricky. The following code
6620  * should work:
6621  *
6622  *  do {
6623  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6624  *             PIPE_FRAME_HIGH_SHIFT;
6625  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6626  *             PIPE_FRAME_LOW_SHIFT);
6627  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6628  *             PIPE_FRAME_HIGH_SHIFT);
6629  *  } while (high1 != high2);
6630  *  frame = (high1 << 8) | low1;
6631  */
6632 #define _PIPEAFRAMEHIGH          0x70040
6633 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6634 #define   PIPE_FRAME_HIGH_SHIFT   0
6635 #define _PIPEAFRAMEPIXEL         0x70044
6636 #define   PIPE_FRAME_LOW_MASK     0xff000000
6637 #define   PIPE_FRAME_LOW_SHIFT    24
6638 #define   PIPE_PIXEL_MASK         0x00ffffff
6639 #define   PIPE_PIXEL_SHIFT        0
6640 /* GM45+ just has to be different */
6641 #define _PIPEA_FRMCOUNT_G4X	0x70040
6642 #define _PIPEA_FLIPCOUNT_G4X	0x70044
6643 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6644 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6645 
6646 /* Cursor A & B regs */
6647 #define _CURACNTR		0x70080
6648 /* Old style CUR*CNTR flags (desktop 8xx) */
6649 #define   CURSOR_ENABLE		0x80000000
6650 #define   CURSOR_GAMMA_ENABLE	0x40000000
6651 #define   CURSOR_STRIDE_SHIFT	28
6652 #define   CURSOR_STRIDE(x)	((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6653 #define   CURSOR_FORMAT_SHIFT	24
6654 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
6655 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
6656 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
6657 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
6658 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
6659 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
6660 /* New style CUR*CNTR flags */
6661 #define   MCURSOR_MODE		0x27
6662 #define   MCURSOR_MODE_DISABLE   0x00
6663 #define   MCURSOR_MODE_128_32B_AX 0x02
6664 #define   MCURSOR_MODE_256_32B_AX 0x03
6665 #define   MCURSOR_MODE_64_32B_AX 0x07
6666 #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6667 #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6668 #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6669 #define   MCURSOR_ARB_SLOTS_MASK	REG_GENMASK(30, 28) /* icl+ */
6670 #define   MCURSOR_ARB_SLOTS(x)		REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
6671 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
6672 #define   MCURSOR_PIPE_SELECT_SHIFT	28
6673 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
6674 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
6675 #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6676 #define   MCURSOR_ROTATE_180	(1 << 15)
6677 #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
6678 #define _CURABASE		0x70084
6679 #define _CURAPOS		0x70088
6680 #define   CURSOR_POS_MASK       0x007FF
6681 #define   CURSOR_POS_SIGN       0x8000
6682 #define   CURSOR_X_SHIFT        0
6683 #define   CURSOR_Y_SHIFT        16
6684 #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
6685 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
6686 #define   CUR_FBC_CTL_EN	(1 << 31)
6687 #define _CURASURFLIVE		0x700ac /* g4x+ */
6688 #define _CURBCNTR		0x700c0
6689 #define _CURBBASE		0x700c4
6690 #define _CURBPOS		0x700c8
6691 
6692 #define _CURBCNTR_IVB		0x71080
6693 #define _CURBBASE_IVB		0x71084
6694 #define _CURBPOS_IVB		0x71088
6695 
6696 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6697 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6698 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6699 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6700 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6701 
6702 #define CURSOR_A_OFFSET 0x70080
6703 #define CURSOR_B_OFFSET 0x700c0
6704 #define CHV_CURSOR_C_OFFSET 0x700e0
6705 #define IVB_CURSOR_B_OFFSET 0x71080
6706 #define IVB_CURSOR_C_OFFSET 0x72080
6707 #define TGL_CURSOR_D_OFFSET 0x73080
6708 
6709 /* Display A control */
6710 #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
6711 #define _DSPACNTR				0x70180
6712 #define   DISPLAY_PLANE_ENABLE			(1 << 31)
6713 #define   DISPLAY_PLANE_DISABLE			0
6714 #define   DISPPLANE_GAMMA_ENABLE		(1 << 30)
6715 #define   DISPPLANE_GAMMA_DISABLE		0
6716 #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
6717 #define   DISPPLANE_YUV422			(0x0 << 26)
6718 #define   DISPPLANE_8BPP			(0x2 << 26)
6719 #define   DISPPLANE_BGRA555			(0x3 << 26)
6720 #define   DISPPLANE_BGRX555			(0x4 << 26)
6721 #define   DISPPLANE_BGRX565			(0x5 << 26)
6722 #define   DISPPLANE_BGRX888			(0x6 << 26)
6723 #define   DISPPLANE_BGRA888			(0x7 << 26)
6724 #define   DISPPLANE_RGBX101010			(0x8 << 26)
6725 #define   DISPPLANE_RGBA101010			(0x9 << 26)
6726 #define   DISPPLANE_BGRX101010			(0xa << 26)
6727 #define   DISPPLANE_BGRA101010			(0xb << 26)
6728 #define   DISPPLANE_RGBX161616			(0xc << 26)
6729 #define   DISPPLANE_RGBX888			(0xe << 26)
6730 #define   DISPPLANE_RGBA888			(0xf << 26)
6731 #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
6732 #define   DISPPLANE_STEREO_DISABLE		0
6733 #define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
6734 #define   DISPPLANE_SEL_PIPE_SHIFT		24
6735 #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
6736 #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6737 #define   DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
6738 #define   DISPPLANE_SRC_KEY_DISABLE		0
6739 #define   DISPPLANE_LINE_DOUBLE			(1 << 20)
6740 #define   DISPPLANE_NO_LINE_DOUBLE		0
6741 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
6742 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
6743 #define   DISPPLANE_ALPHA_PREMULTIPLY		(1 << 16) /* CHV pipe B */
6744 #define   DISPPLANE_ROTATE_180			(1 << 15)
6745 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1 << 14) /* Ironlake */
6746 #define   DISPPLANE_TILED			(1 << 10)
6747 #define   DISPPLANE_ASYNC_FLIP			(1 << 9) /* g4x+ */
6748 #define   DISPPLANE_MIRROR			(1 << 8) /* CHV pipe B */
6749 #define _DSPAADDR				0x70184
6750 #define _DSPASTRIDE				0x70188
6751 #define _DSPAPOS				0x7018C /* reserved */
6752 #define _DSPASIZE				0x70190
6753 #define _DSPASURF				0x7019C /* 965+ only */
6754 #define _DSPATILEOFF				0x701A4 /* 965+ only */
6755 #define _DSPAOFFSET				0x701A4 /* HSW */
6756 #define _DSPASURFLIVE				0x701AC
6757 #define _DSPAGAMC				0x701E0
6758 
6759 #define DSPADDR_VLV(plane)	_MMIO_PIPE2(plane, _DSPAADDR_VLV)
6760 #define DSPCNTR(plane)		_MMIO_PIPE2(plane, _DSPACNTR)
6761 #define DSPADDR(plane)		_MMIO_PIPE2(plane, _DSPAADDR)
6762 #define DSPSTRIDE(plane)	_MMIO_PIPE2(plane, _DSPASTRIDE)
6763 #define DSPPOS(plane)		_MMIO_PIPE2(plane, _DSPAPOS)
6764 #define DSPSIZE(plane)		_MMIO_PIPE2(plane, _DSPASIZE)
6765 #define DSPSURF(plane)		_MMIO_PIPE2(plane, _DSPASURF)
6766 #define DSPTILEOFF(plane)	_MMIO_PIPE2(plane, _DSPATILEOFF)
6767 #define DSPLINOFF(plane)	DSPADDR(plane)
6768 #define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
6769 #define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
6770 #define DSPGAMC(plane, i)	_MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6771 
6772 /* CHV pipe B blender and primary plane */
6773 #define _CHV_BLEND_A		0x60a00
6774 #define   CHV_BLEND_LEGACY		(0 << 30)
6775 #define   CHV_BLEND_ANDROID		(1 << 30)
6776 #define   CHV_BLEND_MPO			(2 << 30)
6777 #define   CHV_BLEND_MASK		(3 << 30)
6778 #define _CHV_CANVAS_A		0x60a04
6779 #define _PRIMPOS_A		0x60a08
6780 #define _PRIMSIZE_A		0x60a0c
6781 #define _PRIMCNSTALPHA_A	0x60a10
6782 #define   PRIM_CONST_ALPHA_ENABLE	(1 << 31)
6783 
6784 #define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
6785 #define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6786 #define PRIMPOS(plane)		_MMIO_TRANS2(plane, _PRIMPOS_A)
6787 #define PRIMSIZE(plane)		_MMIO_TRANS2(plane, _PRIMSIZE_A)
6788 #define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6789 
6790 /* Display/Sprite base address macros */
6791 #define DISP_BASEADDR_MASK	(0xfffff000)
6792 #define I915_LO_DISPBASE(val)	((val) & ~DISP_BASEADDR_MASK)
6793 #define I915_HI_DISPBASE(val)	((val) & DISP_BASEADDR_MASK)
6794 
6795 /*
6796  * VBIOS flags
6797  * gen2:
6798  * [00:06] alm,mgm
6799  * [10:16] all
6800  * [30:32] alm,mgm
6801  * gen3+:
6802  * [00:0f] all
6803  * [10:1f] all
6804  * [30:32] all
6805  */
6806 #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6807 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6808 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6809 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
6810 
6811 /* Pipe B */
6812 #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6813 #define _PIPEBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6814 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6815 #define _PIPEBFRAMEHIGH		0x71040
6816 #define _PIPEBFRAMEPIXEL	0x71044
6817 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6818 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6819 
6820 
6821 /* Display B control */
6822 #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6823 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
6824 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
6825 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
6826 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
6827 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6828 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6829 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6830 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6831 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6832 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6833 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6834 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6835 
6836 /* ICL DSI 0 and 1 */
6837 #define _PIPEDSI0CONF		0x7b008
6838 #define _PIPEDSI1CONF		0x7b808
6839 
6840 /* Sprite A control */
6841 #define _DVSACNTR		0x72180
6842 #define   DVS_ENABLE		(1 << 31)
6843 #define   DVS_GAMMA_ENABLE	(1 << 30)
6844 #define   DVS_YUV_RANGE_CORRECTION_DISABLE	(1 << 27)
6845 #define   DVS_PIXFORMAT_MASK	(3 << 25)
6846 #define   DVS_FORMAT_YUV422	(0 << 25)
6847 #define   DVS_FORMAT_RGBX101010	(1 << 25)
6848 #define   DVS_FORMAT_RGBX888	(2 << 25)
6849 #define   DVS_FORMAT_RGBX161616	(3 << 25)
6850 #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
6851 #define   DVS_SOURCE_KEY	(1 << 22)
6852 #define   DVS_RGB_ORDER_XBGR	(1 << 20)
6853 #define   DVS_YUV_FORMAT_BT709	(1 << 18)
6854 #define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6855 #define   DVS_YUV_ORDER_YUYV	(0 << 16)
6856 #define   DVS_YUV_ORDER_UYVY	(1 << 16)
6857 #define   DVS_YUV_ORDER_YVYU	(2 << 16)
6858 #define   DVS_YUV_ORDER_VYUY	(3 << 16)
6859 #define   DVS_ROTATE_180	(1 << 15)
6860 #define   DVS_DEST_KEY		(1 << 2)
6861 #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
6862 #define   DVS_TILED		(1 << 10)
6863 #define _DVSALINOFF		0x72184
6864 #define _DVSASTRIDE		0x72188
6865 #define _DVSAPOS		0x7218c
6866 #define _DVSASIZE		0x72190
6867 #define _DVSAKEYVAL		0x72194
6868 #define _DVSAKEYMSK		0x72198
6869 #define _DVSASURF		0x7219c
6870 #define _DVSAKEYMAXVAL		0x721a0
6871 #define _DVSATILEOFF		0x721a4
6872 #define _DVSASURFLIVE		0x721ac
6873 #define _DVSAGAMC_G4X		0x721e0 /* g4x */
6874 #define _DVSASCALE		0x72204
6875 #define   DVS_SCALE_ENABLE	(1 << 31)
6876 #define   DVS_FILTER_MASK	(3 << 29)
6877 #define   DVS_FILTER_MEDIUM	(0 << 29)
6878 #define   DVS_FILTER_ENHANCING	(1 << 29)
6879 #define   DVS_FILTER_SOFTENING	(2 << 29)
6880 #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6881 #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6882 #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
6883 #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
6884 
6885 #define _DVSBCNTR		0x73180
6886 #define _DVSBLINOFF		0x73184
6887 #define _DVSBSTRIDE		0x73188
6888 #define _DVSBPOS		0x7318c
6889 #define _DVSBSIZE		0x73190
6890 #define _DVSBKEYVAL		0x73194
6891 #define _DVSBKEYMSK		0x73198
6892 #define _DVSBSURF		0x7319c
6893 #define _DVSBKEYMAXVAL		0x731a0
6894 #define _DVSBTILEOFF		0x731a4
6895 #define _DVSBSURFLIVE		0x731ac
6896 #define _DVSBGAMC_G4X		0x731e0 /* g4x */
6897 #define _DVSBSCALE		0x73204
6898 #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
6899 #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
6900 
6901 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6902 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6903 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6904 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6905 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6906 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6907 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6908 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6909 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6910 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6911 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6912 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6913 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6914 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6915 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6916 
6917 #define _SPRA_CTL		0x70280
6918 #define   SPRITE_ENABLE			(1 << 31)
6919 #define   SPRITE_GAMMA_ENABLE		(1 << 30)
6920 #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6921 #define   SPRITE_PIXFORMAT_MASK		(7 << 25)
6922 #define   SPRITE_FORMAT_YUV422		(0 << 25)
6923 #define   SPRITE_FORMAT_RGBX101010	(1 << 25)
6924 #define   SPRITE_FORMAT_RGBX888		(2 << 25)
6925 #define   SPRITE_FORMAT_RGBX161616	(3 << 25)
6926 #define   SPRITE_FORMAT_YUV444		(4 << 25)
6927 #define   SPRITE_FORMAT_XR_BGR101010	(5 << 25) /* Extended range */
6928 #define   SPRITE_PIPE_CSC_ENABLE	(1 << 24)
6929 #define   SPRITE_SOURCE_KEY		(1 << 22)
6930 #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
6931 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
6932 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
6933 #define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
6934 #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
6935 #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
6936 #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
6937 #define   SPRITE_YUV_ORDER_VYUY		(3 << 16)
6938 #define   SPRITE_ROTATE_180		(1 << 15)
6939 #define   SPRITE_TRICKLE_FEED_DISABLE	(1 << 14)
6940 #define   SPRITE_INT_GAMMA_DISABLE	(1 << 13)
6941 #define   SPRITE_TILED			(1 << 10)
6942 #define   SPRITE_DEST_KEY		(1 << 2)
6943 #define _SPRA_LINOFF		0x70284
6944 #define _SPRA_STRIDE		0x70288
6945 #define _SPRA_POS		0x7028c
6946 #define _SPRA_SIZE		0x70290
6947 #define _SPRA_KEYVAL		0x70294
6948 #define _SPRA_KEYMSK		0x70298
6949 #define _SPRA_SURF		0x7029c
6950 #define _SPRA_KEYMAX		0x702a0
6951 #define _SPRA_TILEOFF		0x702a4
6952 #define _SPRA_OFFSET		0x702a4
6953 #define _SPRA_SURFLIVE		0x702ac
6954 #define _SPRA_SCALE		0x70304
6955 #define   SPRITE_SCALE_ENABLE	(1 << 31)
6956 #define   SPRITE_FILTER_MASK	(3 << 29)
6957 #define   SPRITE_FILTER_MEDIUM	(0 << 29)
6958 #define   SPRITE_FILTER_ENHANCING	(1 << 29)
6959 #define   SPRITE_FILTER_SOFTENING	(2 << 29)
6960 #define   SPRITE_VERTICAL_OFFSET_HALF	(1 << 28) /* must be enabled below */
6961 #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1 << 27)
6962 #define _SPRA_GAMC		0x70400
6963 #define _SPRA_GAMC16		0x70440
6964 #define _SPRA_GAMC17		0x7044c
6965 
6966 #define _SPRB_CTL		0x71280
6967 #define _SPRB_LINOFF		0x71284
6968 #define _SPRB_STRIDE		0x71288
6969 #define _SPRB_POS		0x7128c
6970 #define _SPRB_SIZE		0x71290
6971 #define _SPRB_KEYVAL		0x71294
6972 #define _SPRB_KEYMSK		0x71298
6973 #define _SPRB_SURF		0x7129c
6974 #define _SPRB_KEYMAX		0x712a0
6975 #define _SPRB_TILEOFF		0x712a4
6976 #define _SPRB_OFFSET		0x712a4
6977 #define _SPRB_SURFLIVE		0x712ac
6978 #define _SPRB_SCALE		0x71304
6979 #define _SPRB_GAMC		0x71400
6980 #define _SPRB_GAMC16		0x71440
6981 #define _SPRB_GAMC17		0x7144c
6982 
6983 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6984 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6985 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6986 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6987 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6988 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6989 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6990 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6991 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6992 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6993 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6994 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6995 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6996 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6997 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6998 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6999 
7000 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
7001 #define   SP_ENABLE			(1 << 31)
7002 #define   SP_GAMMA_ENABLE		(1 << 30)
7003 #define   SP_PIXFORMAT_MASK		(0xf << 26)
7004 #define   SP_FORMAT_YUV422		(0x0 << 26)
7005 #define   SP_FORMAT_8BPP		(0x2 << 26)
7006 #define   SP_FORMAT_BGR565		(0x5 << 26)
7007 #define   SP_FORMAT_BGRX8888		(0x6 << 26)
7008 #define   SP_FORMAT_BGRA8888		(0x7 << 26)
7009 #define   SP_FORMAT_RGBX1010102		(0x8 << 26)
7010 #define   SP_FORMAT_RGBA1010102		(0x9 << 26)
7011 #define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
7012 #define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
7013 #define   SP_FORMAT_RGBX8888		(0xe << 26)
7014 #define   SP_FORMAT_RGBA8888		(0xf << 26)
7015 #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
7016 #define   SP_SOURCE_KEY			(1 << 22)
7017 #define   SP_YUV_FORMAT_BT709		(1 << 18)
7018 #define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
7019 #define   SP_YUV_ORDER_YUYV		(0 << 16)
7020 #define   SP_YUV_ORDER_UYVY		(1 << 16)
7021 #define   SP_YUV_ORDER_YVYU		(2 << 16)
7022 #define   SP_YUV_ORDER_VYUY		(3 << 16)
7023 #define   SP_ROTATE_180			(1 << 15)
7024 #define   SP_TILED			(1 << 10)
7025 #define   SP_MIRROR			(1 << 8) /* CHV pipe B */
7026 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
7027 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
7028 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
7029 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
7030 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
7031 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
7032 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
7033 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
7034 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
7035 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
7036 #define   SP_CONST_ALPHA_ENABLE		(1 << 31)
7037 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
7038 #define   SP_CONTRAST(x)		((x) << 18) /* u3.6 */
7039 #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
7040 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
7041 #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
7042 #define   SP_SH_COS(x)			(x) /* u3.7 */
7043 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
7044 
7045 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
7046 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
7047 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
7048 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
7049 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
7050 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
7051 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
7052 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
7053 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
7054 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
7055 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
7056 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
7057 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
7058 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
7059 
7060 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
7061 	_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
7062 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
7063 	_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
7064 
7065 #define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
7066 #define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
7067 #define SPSTRIDE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
7068 #define SPPOS(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
7069 #define SPSIZE(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
7070 #define SPKEYMINVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
7071 #define SPKEYMSK(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
7072 #define SPSURF(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
7073 #define SPKEYMAXVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
7074 #define SPTILEOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
7075 #define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
7076 #define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
7077 #define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
7078 #define SPGAMC(pipe, plane_id, i)	_MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
7079 
7080 /*
7081  * CHV pipe B sprite CSC
7082  *
7083  * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
7084  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
7085  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
7086  */
7087 #define _MMIO_CHV_SPCSC(plane_id, reg) \
7088 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
7089 
7090 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
7091 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
7092 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
7093 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
7094 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
7095 
7096 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
7097 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
7098 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
7099 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
7100 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
7101 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
7102 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
7103 
7104 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
7105 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
7106 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
7107 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
7108 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
7109 
7110 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
7111 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
7112 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
7113 #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
7114 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
7115 
7116 /* Skylake plane registers */
7117 
7118 #define _PLANE_CTL_1_A				0x70180
7119 #define _PLANE_CTL_2_A				0x70280
7120 #define _PLANE_CTL_3_A				0x70380
7121 #define   PLANE_CTL_ENABLE			(1 << 31)
7122 #define   PLANE_CTL_ARB_SLOTS_MASK		REG_GENMASK(30, 28) /* icl+ */
7123 #define   PLANE_CTL_ARB_SLOTS(x)		REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
7124 #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
7125 #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
7126 /*
7127  * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
7128  * expanded to include bit 23 as well. However, the shift-24 based values
7129  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
7130  */
7131 #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
7132 #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
7133 #define   PLANE_CTL_FORMAT_NV12			(1 << 24)
7134 #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
7135 #define   PLANE_CTL_FORMAT_P010			(3 << 24)
7136 #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
7137 #define   PLANE_CTL_FORMAT_P012			(5 << 24)
7138 #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
7139 #define   PLANE_CTL_FORMAT_P016			(7 << 24)
7140 #define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
7141 #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
7142 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
7143 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
7144 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
7145 #define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
7146 #define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
7147 #define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
7148 #define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
7149 #define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
7150 #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
7151 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
7152 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
7153 #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
7154 #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
7155 #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
7156 #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
7157 #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
7158 #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
7159 #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
7160 #define   PLANE_CTL_YUV422_UYVY			(1 << 16)
7161 #define   PLANE_CTL_YUV422_YVYU			(2 << 16)
7162 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
7163 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
7164 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
7165 #define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
7166 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
7167 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
7168 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
7169 #define   PLANE_CTL_TILED_X			(1 << 10)
7170 #define   PLANE_CTL_TILED_Y			(4 << 10)
7171 #define   PLANE_CTL_TILED_YF			(5 << 10)
7172 #define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
7173 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
7174 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
7175 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
7176 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
7177 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
7178 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(3 << 4)
7179 #define   PLANE_CTL_ROTATE_MASK			0x3
7180 #define   PLANE_CTL_ROTATE_0			0x0
7181 #define   PLANE_CTL_ROTATE_90			0x1
7182 #define   PLANE_CTL_ROTATE_180			0x2
7183 #define   PLANE_CTL_ROTATE_270			0x3
7184 #define _PLANE_STRIDE_1_A			0x70188
7185 #define _PLANE_STRIDE_2_A			0x70288
7186 #define _PLANE_STRIDE_3_A			0x70388
7187 #define _PLANE_POS_1_A				0x7018c
7188 #define _PLANE_POS_2_A				0x7028c
7189 #define _PLANE_POS_3_A				0x7038c
7190 #define _PLANE_SIZE_1_A				0x70190
7191 #define _PLANE_SIZE_2_A				0x70290
7192 #define _PLANE_SIZE_3_A				0x70390
7193 #define _PLANE_SURF_1_A				0x7019c
7194 #define _PLANE_SURF_2_A				0x7029c
7195 #define _PLANE_SURF_3_A				0x7039c
7196 #define _PLANE_OFFSET_1_A			0x701a4
7197 #define _PLANE_OFFSET_2_A			0x702a4
7198 #define _PLANE_OFFSET_3_A			0x703a4
7199 #define _PLANE_KEYVAL_1_A			0x70194
7200 #define _PLANE_KEYVAL_2_A			0x70294
7201 #define _PLANE_KEYMSK_1_A			0x70198
7202 #define _PLANE_KEYMSK_2_A			0x70298
7203 #define  PLANE_KEYMSK_ALPHA_ENABLE		(1 << 31)
7204 #define _PLANE_KEYMAX_1_A			0x701a0
7205 #define _PLANE_KEYMAX_2_A			0x702a0
7206 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
7207 #define _PLANE_CC_VAL_1_A			0x701b4
7208 #define _PLANE_CC_VAL_2_A			0x702b4
7209 #define _PLANE_AUX_DIST_1_A			0x701c0
7210 #define _PLANE_AUX_DIST_2_A			0x702c0
7211 #define _PLANE_AUX_OFFSET_1_A			0x701c4
7212 #define _PLANE_AUX_OFFSET_2_A			0x702c4
7213 #define _PLANE_CUS_CTL_1_A			0x701c8
7214 #define _PLANE_CUS_CTL_2_A			0x702c8
7215 #define  PLANE_CUS_ENABLE			(1 << 31)
7216 #define  PLANE_CUS_PLANE_4_RKL			(0 << 30)
7217 #define  PLANE_CUS_PLANE_5_RKL			(1 << 30)
7218 #define  PLANE_CUS_PLANE_6			(0 << 30)
7219 #define  PLANE_CUS_PLANE_7			(1 << 30)
7220 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
7221 #define  PLANE_CUS_HPHASE_0			(0 << 16)
7222 #define  PLANE_CUS_HPHASE_0_25			(1 << 16)
7223 #define  PLANE_CUS_HPHASE_0_5			(2 << 16)
7224 #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE		(1 << 15)
7225 #define  PLANE_CUS_VPHASE_0			(0 << 12)
7226 #define  PLANE_CUS_VPHASE_0_25			(1 << 12)
7227 #define  PLANE_CUS_VPHASE_0_5			(2 << 12)
7228 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
7229 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
7230 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
7231 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
7232 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
7233 #define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
7234 #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
7235 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
7236 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601		(1 << 17)
7237 #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709		(2 << 17)
7238 #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	(3 << 17)
7239 #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	(4 << 17)
7240 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
7241 #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
7242 #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
7243 #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY	(2 << 4)
7244 #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY	(3 << 4)
7245 #define _PLANE_BUF_CFG_1_A			0x7027c
7246 #define _PLANE_BUF_CFG_2_A			0x7037c
7247 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
7248 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
7249 
7250 #define _PLANE_CC_VAL_1_B			0x711b4
7251 #define _PLANE_CC_VAL_2_B			0x712b4
7252 #define _PLANE_CC_VAL_1(pipe)	_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B)
7253 #define _PLANE_CC_VAL_2(pipe)	_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
7254 #define PLANE_CC_VAL(pipe, plane)	\
7255 	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
7256 
7257 /* Input CSC Register Definitions */
7258 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
7259 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
7260 
7261 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
7262 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
7263 
7264 #define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
7265 	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
7266 	     _PLANE_INPUT_CSC_RY_GY_1_B)
7267 #define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
7268 	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
7269 	     _PLANE_INPUT_CSC_RY_GY_2_B)
7270 
7271 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index)	\
7272 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
7273 		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
7274 
7275 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
7276 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
7277 
7278 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
7279 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
7280 
7281 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
7282 	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
7283 	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
7284 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
7285 	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
7286 	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
7287 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)	\
7288 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
7289 		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
7290 
7291 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
7292 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
7293 
7294 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
7295 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
7296 
7297 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
7298 	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
7299 	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
7300 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
7301 	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
7302 	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
7303 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)	\
7304 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
7305 		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
7306 
7307 #define _PLANE_CTL_1_B				0x71180
7308 #define _PLANE_CTL_2_B				0x71280
7309 #define _PLANE_CTL_3_B				0x71380
7310 #define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
7311 #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
7312 #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
7313 #define PLANE_CTL(pipe, plane)	\
7314 	_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
7315 
7316 #define _PLANE_STRIDE_1_B			0x71188
7317 #define _PLANE_STRIDE_2_B			0x71288
7318 #define _PLANE_STRIDE_3_B			0x71388
7319 #define _PLANE_STRIDE_1(pipe)	\
7320 	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
7321 #define _PLANE_STRIDE_2(pipe)	\
7322 	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
7323 #define _PLANE_STRIDE_3(pipe)	\
7324 	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
7325 #define PLANE_STRIDE(pipe, plane)	\
7326 	_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
7327 #define PLANE_STRIDE_MASK		REG_GENMASK(10, 0)
7328 #define PLANE_STRIDE_MASK_XELPD		REG_GENMASK(11, 0)
7329 
7330 #define _PLANE_POS_1_B				0x7118c
7331 #define _PLANE_POS_2_B				0x7128c
7332 #define _PLANE_POS_3_B				0x7138c
7333 #define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
7334 #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
7335 #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
7336 #define PLANE_POS(pipe, plane)	\
7337 	_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
7338 
7339 #define _PLANE_SIZE_1_B				0x71190
7340 #define _PLANE_SIZE_2_B				0x71290
7341 #define _PLANE_SIZE_3_B				0x71390
7342 #define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
7343 #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
7344 #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
7345 #define PLANE_SIZE(pipe, plane)	\
7346 	_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
7347 
7348 #define _PLANE_SURF_1_B				0x7119c
7349 #define _PLANE_SURF_2_B				0x7129c
7350 #define _PLANE_SURF_3_B				0x7139c
7351 #define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
7352 #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
7353 #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
7354 #define PLANE_SURF(pipe, plane)	\
7355 	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
7356 
7357 #define _PLANE_OFFSET_1_B			0x711a4
7358 #define _PLANE_OFFSET_2_B			0x712a4
7359 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
7360 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
7361 #define PLANE_OFFSET(pipe, plane)	\
7362 	_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
7363 
7364 #define _PLANE_KEYVAL_1_B			0x71194
7365 #define _PLANE_KEYVAL_2_B			0x71294
7366 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
7367 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
7368 #define PLANE_KEYVAL(pipe, plane)	\
7369 	_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
7370 
7371 #define _PLANE_KEYMSK_1_B			0x71198
7372 #define _PLANE_KEYMSK_2_B			0x71298
7373 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
7374 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
7375 #define PLANE_KEYMSK(pipe, plane)	\
7376 	_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
7377 
7378 #define _PLANE_KEYMAX_1_B			0x711a0
7379 #define _PLANE_KEYMAX_2_B			0x712a0
7380 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
7381 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
7382 #define PLANE_KEYMAX(pipe, plane)	\
7383 	_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
7384 
7385 #define _PLANE_BUF_CFG_1_B			0x7127c
7386 #define _PLANE_BUF_CFG_2_B			0x7137c
7387 #define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
7388 #define  DDB_ENTRY_END_SHIFT			16
7389 #define _PLANE_BUF_CFG_1(pipe)	\
7390 	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
7391 #define _PLANE_BUF_CFG_2(pipe)	\
7392 	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
7393 #define PLANE_BUF_CFG(pipe, plane)	\
7394 	_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
7395 
7396 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
7397 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
7398 #define _PLANE_NV12_BUF_CFG_1(pipe)	\
7399 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
7400 #define _PLANE_NV12_BUF_CFG_2(pipe)	\
7401 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
7402 #define PLANE_NV12_BUF_CFG(pipe, plane)	\
7403 	_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
7404 
7405 #define _PLANE_AUX_DIST_1_B		0x711c0
7406 #define _PLANE_AUX_DIST_2_B		0x712c0
7407 #define _PLANE_AUX_DIST_1(pipe) \
7408 			_PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
7409 #define _PLANE_AUX_DIST_2(pipe) \
7410 			_PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
7411 #define PLANE_AUX_DIST(pipe, plane)     \
7412 	_MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
7413 
7414 #define _PLANE_AUX_OFFSET_1_B		0x711c4
7415 #define _PLANE_AUX_OFFSET_2_B		0x712c4
7416 #define _PLANE_AUX_OFFSET_1(pipe)       \
7417 		_PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
7418 #define _PLANE_AUX_OFFSET_2(pipe)       \
7419 		_PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
7420 #define PLANE_AUX_OFFSET(pipe, plane)   \
7421 	_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
7422 
7423 #define _PLANE_CUS_CTL_1_B		0x711c8
7424 #define _PLANE_CUS_CTL_2_B		0x712c8
7425 #define _PLANE_CUS_CTL_1(pipe)       \
7426 		_PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
7427 #define _PLANE_CUS_CTL_2(pipe)       \
7428 		_PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
7429 #define PLANE_CUS_CTL(pipe, plane)   \
7430 	_MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
7431 
7432 #define _PLANE_COLOR_CTL_1_B			0x711CC
7433 #define _PLANE_COLOR_CTL_2_B			0x712CC
7434 #define _PLANE_COLOR_CTL_3_B			0x713CC
7435 #define _PLANE_COLOR_CTL_1(pipe)	\
7436 	_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
7437 #define _PLANE_COLOR_CTL_2(pipe)	\
7438 	_PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
7439 #define PLANE_COLOR_CTL(pipe, plane)	\
7440 	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
7441 
7442 #define _SEL_FETCH_PLANE_BASE_1_A		0x70890
7443 #define _SEL_FETCH_PLANE_BASE_2_A		0x708B0
7444 #define _SEL_FETCH_PLANE_BASE_3_A		0x708D0
7445 #define _SEL_FETCH_PLANE_BASE_4_A		0x708F0
7446 #define _SEL_FETCH_PLANE_BASE_5_A		0x70920
7447 #define _SEL_FETCH_PLANE_BASE_6_A		0x70940
7448 #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
7449 #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
7450 #define _SEL_FETCH_PLANE_BASE_1_B		0x70990
7451 
7452 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
7453 					     _SEL_FETCH_PLANE_BASE_1_A, \
7454 					     _SEL_FETCH_PLANE_BASE_2_A, \
7455 					     _SEL_FETCH_PLANE_BASE_3_A, \
7456 					     _SEL_FETCH_PLANE_BASE_4_A, \
7457 					     _SEL_FETCH_PLANE_BASE_5_A, \
7458 					     _SEL_FETCH_PLANE_BASE_6_A, \
7459 					     _SEL_FETCH_PLANE_BASE_7_A, \
7460 					     _SEL_FETCH_PLANE_BASE_CUR_A)
7461 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
7462 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
7463 					    _SEL_FETCH_PLANE_BASE_1_A + \
7464 					    _SEL_FETCH_PLANE_BASE_A(plane))
7465 
7466 #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
7467 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7468 					       _SEL_FETCH_PLANE_CTL_1_A - \
7469 					       _SEL_FETCH_PLANE_BASE_1_A)
7470 #define PLANE_SEL_FETCH_CTL_ENABLE		REG_BIT(31)
7471 
7472 #define _SEL_FETCH_PLANE_POS_1_A		0x70894
7473 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7474 					       _SEL_FETCH_PLANE_POS_1_A - \
7475 					       _SEL_FETCH_PLANE_BASE_1_A)
7476 
7477 #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
7478 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7479 						_SEL_FETCH_PLANE_SIZE_1_A - \
7480 						_SEL_FETCH_PLANE_BASE_1_A)
7481 
7482 #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
7483 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7484 						  _SEL_FETCH_PLANE_OFFSET_1_A - \
7485 						  _SEL_FETCH_PLANE_BASE_1_A)
7486 
7487 /* SKL new cursor registers */
7488 #define _CUR_BUF_CFG_A				0x7017c
7489 #define _CUR_BUF_CFG_B				0x7117c
7490 #define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
7491 
7492 /* VBIOS regs */
7493 #define VGACNTRL		_MMIO(0x71400)
7494 # define VGA_DISP_DISABLE			(1 << 31)
7495 # define VGA_2X_MODE				(1 << 30)
7496 # define VGA_PIPE_B_SELECT			(1 << 29)
7497 
7498 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
7499 
7500 /* Ironlake */
7501 
7502 #define CPU_VGACNTRL	_MMIO(0x41000)
7503 
7504 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
7505 #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
7506 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
7507 #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
7508 #define  DIGITAL_PORTA_PULSE_DURATION_6ms	(2 << 2) /* pre-HSW */
7509 #define  DIGITAL_PORTA_PULSE_DURATION_100ms	(3 << 2) /* pre-HSW */
7510 #define  DIGITAL_PORTA_PULSE_DURATION_MASK	(3 << 2) /* pre-HSW */
7511 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
7512 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
7513 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
7514 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
7515 
7516 /* refresh rate hardware control */
7517 #define RR_HW_CTL       _MMIO(0x45300)
7518 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
7519 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
7520 
7521 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
7522 #define  FDI_PLL_FB_CLOCK_MASK  0xff
7523 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
7524 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
7525 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
7526 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
7527 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
7528 
7529 #define PCH_3DCGDIS0		_MMIO(0x46020)
7530 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
7531 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
7532 
7533 #define PCH_3DCGDIS1		_MMIO(0x46024)
7534 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
7535 
7536 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
7537 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
7538 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
7539 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
7540 
7541 
7542 #define _PIPEA_DATA_M1		0x60030
7543 #define  PIPE_DATA_M1_OFFSET    0
7544 #define _PIPEA_DATA_N1		0x60034
7545 #define  PIPE_DATA_N1_OFFSET    0
7546 
7547 #define _PIPEA_DATA_M2		0x60038
7548 #define  PIPE_DATA_M2_OFFSET    0
7549 #define _PIPEA_DATA_N2		0x6003c
7550 #define  PIPE_DATA_N2_OFFSET    0
7551 
7552 #define _PIPEA_LINK_M1		0x60040
7553 #define  PIPE_LINK_M1_OFFSET    0
7554 #define _PIPEA_LINK_N1		0x60044
7555 #define  PIPE_LINK_N1_OFFSET    0
7556 
7557 #define _PIPEA_LINK_M2		0x60048
7558 #define  PIPE_LINK_M2_OFFSET    0
7559 #define _PIPEA_LINK_N2		0x6004c
7560 #define  PIPE_LINK_N2_OFFSET    0
7561 
7562 /* PIPEB timing regs are same start from 0x61000 */
7563 
7564 #define _PIPEB_DATA_M1		0x61030
7565 #define _PIPEB_DATA_N1		0x61034
7566 #define _PIPEB_DATA_M2		0x61038
7567 #define _PIPEB_DATA_N2		0x6103c
7568 #define _PIPEB_LINK_M1		0x61040
7569 #define _PIPEB_LINK_N1		0x61044
7570 #define _PIPEB_LINK_M2		0x61048
7571 #define _PIPEB_LINK_N2		0x6104c
7572 
7573 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7574 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7575 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7576 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7577 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7578 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7579 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7580 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7581 
7582 /* CPU panel fitter */
7583 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7584 #define _PFA_CTL_1               0x68080
7585 #define _PFB_CTL_1               0x68880
7586 #define  PF_ENABLE              (1 << 31)
7587 #define  PF_PIPE_SEL_MASK_IVB	(3 << 29)
7588 #define  PF_PIPE_SEL_IVB(pipe)	((pipe) << 29)
7589 #define  PF_FILTER_MASK		(3 << 23)
7590 #define  PF_FILTER_PROGRAMMED	(0 << 23)
7591 #define  PF_FILTER_MED_3x3	(1 << 23)
7592 #define  PF_FILTER_EDGE_ENHANCE	(2 << 23)
7593 #define  PF_FILTER_EDGE_SOFTEN	(3 << 23)
7594 #define _PFA_WIN_SZ		0x68074
7595 #define _PFB_WIN_SZ		0x68874
7596 #define _PFA_WIN_POS		0x68070
7597 #define _PFB_WIN_POS		0x68870
7598 #define _PFA_VSCALE		0x68084
7599 #define _PFB_VSCALE		0x68884
7600 #define _PFA_HSCALE		0x68090
7601 #define _PFB_HSCALE		0x68890
7602 
7603 #define PF_CTL(pipe)		_MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7604 #define PF_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7605 #define PF_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7606 #define PF_VSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7607 #define PF_HSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7608 
7609 #define _PSA_CTL		0x68180
7610 #define _PSB_CTL		0x68980
7611 #define PS_ENABLE		(1 << 31)
7612 #define _PSA_WIN_SZ		0x68174
7613 #define _PSB_WIN_SZ		0x68974
7614 #define _PSA_WIN_POS		0x68170
7615 #define _PSB_WIN_POS		0x68970
7616 
7617 #define PS_CTL(pipe)		_MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7618 #define PS_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7619 #define PS_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7620 
7621 /*
7622  * Skylake scalers
7623  */
7624 #define _PS_1A_CTRL      0x68180
7625 #define _PS_2A_CTRL      0x68280
7626 #define _PS_1B_CTRL      0x68980
7627 #define _PS_2B_CTRL      0x68A80
7628 #define _PS_1C_CTRL      0x69180
7629 #define PS_SCALER_EN        (1 << 31)
7630 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
7631 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
7632 #define SKL_PS_SCALER_MODE_HQ  (1 << 28)
7633 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7634 #define PS_SCALER_MODE_PLANAR (1 << 29)
7635 #define PS_SCALER_MODE_NORMAL (0 << 29)
7636 #define PS_PLANE_SEL_MASK  (7 << 25)
7637 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7638 #define PS_FILTER_MASK         (3 << 23)
7639 #define PS_FILTER_MEDIUM       (0 << 23)
7640 #define PS_FILTER_PROGRAMMED   (1 << 23)
7641 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
7642 #define PS_FILTER_BILINEAR     (3 << 23)
7643 #define PS_VERT3TAP            (1 << 21)
7644 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7645 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7646 #define PS_PWRUP_PROGRESS         (1 << 17)
7647 #define PS_V_FILTER_BYPASS        (1 << 8)
7648 #define PS_VADAPT_EN              (1 << 7)
7649 #define PS_VADAPT_MODE_MASK        (3 << 5)
7650 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7651 #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
7652 #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
7653 #define PS_PLANE_Y_SEL_MASK  (7 << 5)
7654 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7655 #define PS_Y_VERT_FILTER_SELECT(set)   ((set) << 4)
7656 #define PS_Y_HORZ_FILTER_SELECT(set)   ((set) << 3)
7657 #define PS_UV_VERT_FILTER_SELECT(set)  ((set) << 2)
7658 #define PS_UV_HORZ_FILTER_SELECT(set)  ((set) << 1)
7659 
7660 #define _PS_PWR_GATE_1A     0x68160
7661 #define _PS_PWR_GATE_2A     0x68260
7662 #define _PS_PWR_GATE_1B     0x68960
7663 #define _PS_PWR_GATE_2B     0x68A60
7664 #define _PS_PWR_GATE_1C     0x69160
7665 #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
7666 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
7667 #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
7668 #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
7669 #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
7670 #define PS_PWR_GATE_SLPEN_8             0
7671 #define PS_PWR_GATE_SLPEN_16            1
7672 #define PS_PWR_GATE_SLPEN_24            2
7673 #define PS_PWR_GATE_SLPEN_32            3
7674 
7675 #define _PS_WIN_POS_1A      0x68170
7676 #define _PS_WIN_POS_2A      0x68270
7677 #define _PS_WIN_POS_1B      0x68970
7678 #define _PS_WIN_POS_2B      0x68A70
7679 #define _PS_WIN_POS_1C      0x69170
7680 
7681 #define _PS_WIN_SZ_1A       0x68174
7682 #define _PS_WIN_SZ_2A       0x68274
7683 #define _PS_WIN_SZ_1B       0x68974
7684 #define _PS_WIN_SZ_2B       0x68A74
7685 #define _PS_WIN_SZ_1C       0x69174
7686 
7687 #define _PS_VSCALE_1A       0x68184
7688 #define _PS_VSCALE_2A       0x68284
7689 #define _PS_VSCALE_1B       0x68984
7690 #define _PS_VSCALE_2B       0x68A84
7691 #define _PS_VSCALE_1C       0x69184
7692 
7693 #define _PS_HSCALE_1A       0x68190
7694 #define _PS_HSCALE_2A       0x68290
7695 #define _PS_HSCALE_1B       0x68990
7696 #define _PS_HSCALE_2B       0x68A90
7697 #define _PS_HSCALE_1C       0x69190
7698 
7699 #define _PS_VPHASE_1A       0x68188
7700 #define _PS_VPHASE_2A       0x68288
7701 #define _PS_VPHASE_1B       0x68988
7702 #define _PS_VPHASE_2B       0x68A88
7703 #define _PS_VPHASE_1C       0x69188
7704 #define  PS_Y_PHASE(x)		((x) << 16)
7705 #define  PS_UV_RGB_PHASE(x)	((x) << 0)
7706 #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
7707 #define   PS_PHASE_TRIP	(1 << 0)
7708 
7709 #define _PS_HPHASE_1A       0x68194
7710 #define _PS_HPHASE_2A       0x68294
7711 #define _PS_HPHASE_1B       0x68994
7712 #define _PS_HPHASE_2B       0x68A94
7713 #define _PS_HPHASE_1C       0x69194
7714 
7715 #define _PS_ECC_STAT_1A     0x681D0
7716 #define _PS_ECC_STAT_2A     0x682D0
7717 #define _PS_ECC_STAT_1B     0x689D0
7718 #define _PS_ECC_STAT_2B     0x68AD0
7719 #define _PS_ECC_STAT_1C     0x691D0
7720 
7721 #define _PS_COEF_SET0_INDEX_1A	   0x68198
7722 #define _PS_COEF_SET0_INDEX_2A	   0x68298
7723 #define _PS_COEF_SET0_INDEX_1B	   0x68998
7724 #define _PS_COEF_SET0_INDEX_2B	   0x68A98
7725 #define PS_COEE_INDEX_AUTO_INC	   (1 << 10)
7726 
7727 #define _PS_COEF_SET0_DATA_1A	   0x6819C
7728 #define _PS_COEF_SET0_DATA_2A	   0x6829C
7729 #define _PS_COEF_SET0_DATA_1B	   0x6899C
7730 #define _PS_COEF_SET0_DATA_2B	   0x68A9C
7731 
7732 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7733 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
7734 			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
7735 			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7736 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
7737 			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7738 			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7739 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
7740 			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7741 			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7742 #define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
7743 			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
7744 			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7745 #define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7746 			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
7747 			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7748 #define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7749 			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
7750 			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7751 #define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7752 			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
7753 			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7754 #define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7755 			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
7756 			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7757 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
7758 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
7759 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7760 #define GLK_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
7761 			_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
7762 			_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
7763 
7764 #define GLK_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
7765 			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
7766 			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
7767 /* legacy palette */
7768 #define _LGC_PALETTE_A           0x4a000
7769 #define _LGC_PALETTE_B           0x4a800
7770 #define LGC_PALETTE_RED_MASK     REG_GENMASK(23, 16)
7771 #define LGC_PALETTE_GREEN_MASK   REG_GENMASK(15, 8)
7772 #define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
7773 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7774 
7775 /* ilk/snb precision palette */
7776 #define _PREC_PALETTE_A           0x4b000
7777 #define _PREC_PALETTE_B           0x4c000
7778 #define   PREC_PALETTE_RED_MASK   REG_GENMASK(29, 20)
7779 #define   PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
7780 #define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
7781 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7782 
7783 #define  _PREC_PIPEAGCMAX              0x4d000
7784 #define  _PREC_PIPEBGCMAX              0x4d010
7785 #define PREC_PIPEGCMAX(pipe, i)        _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7786 
7787 #define _GAMMA_MODE_A		0x4a480
7788 #define _GAMMA_MODE_B		0x4ac80
7789 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7790 #define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
7791 #define  POST_CSC_GAMMA_ENABLE	(1 << 30)
7792 #define  GAMMA_MODE_MODE_MASK	(3 << 0)
7793 #define  GAMMA_MODE_MODE_8BIT	(0 << 0)
7794 #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
7795 #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
7796 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
7797 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
7798 
7799 /* DMC */
7800 #define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
7801 #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
7802 #define DMC_HTP_ADDR_SKL	0x00500034
7803 #define DMC_SSP_BASE		_MMIO(0x8F074)
7804 #define DMC_HTP_SKL		_MMIO(0x8F004)
7805 #define DMC_LAST_WRITE		_MMIO(0x8F034)
7806 #define DMC_LAST_WRITE_VALUE	0xc003b400
7807 /* MMIO address range for DMC program (0x80000 - 0x82FFF) */
7808 #define DMC_MMIO_START_RANGE	0x80000
7809 #define DMC_MMIO_END_RANGE	0x8FFFF
7810 #define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
7811 #define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
7812 #define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
7813 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
7814 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
7815 #define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
7816 
7817 #define DMC_DEBUG3		_MMIO(0x101090)
7818 
7819 /* Display Internal Timeout Register */
7820 #define RM_TIMEOUT		_MMIO(0x42060)
7821 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
7822 
7823 /* interrupts */
7824 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
7825 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
7826 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
7827 #define DE_PLANEB_FLIP_DONE     (1 << 27)
7828 #define DE_PLANEA_FLIP_DONE     (1 << 26)
7829 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7830 #define DE_PCU_EVENT            (1 << 25)
7831 #define DE_GTT_FAULT            (1 << 24)
7832 #define DE_POISON               (1 << 23)
7833 #define DE_PERFORM_COUNTER      (1 << 22)
7834 #define DE_PCH_EVENT            (1 << 21)
7835 #define DE_AUX_CHANNEL_A        (1 << 20)
7836 #define DE_DP_A_HOTPLUG         (1 << 19)
7837 #define DE_GSE                  (1 << 18)
7838 #define DE_PIPEB_VBLANK         (1 << 15)
7839 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
7840 #define DE_PIPEB_ODD_FIELD      (1 << 13)
7841 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
7842 #define DE_PIPEB_VSYNC          (1 << 11)
7843 #define DE_PIPEB_CRC_DONE	(1 << 10)
7844 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
7845 #define DE_PIPEA_VBLANK         (1 << 7)
7846 #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
7847 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
7848 #define DE_PIPEA_ODD_FIELD      (1 << 5)
7849 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
7850 #define DE_PIPEA_VSYNC          (1 << 3)
7851 #define DE_PIPEA_CRC_DONE	(1 << 2)
7852 #define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
7853 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7854 #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
7855 
7856 /* More Ivybridge lolz */
7857 #define DE_ERR_INT_IVB			(1 << 30)
7858 #define DE_GSE_IVB			(1 << 29)
7859 #define DE_PCH_EVENT_IVB		(1 << 28)
7860 #define DE_DP_A_HOTPLUG_IVB		(1 << 27)
7861 #define DE_AUX_CHANNEL_A_IVB		(1 << 26)
7862 #define DE_EDP_PSR_INT_HSW		(1 << 19)
7863 #define DE_SPRITEC_FLIP_DONE_IVB	(1 << 14)
7864 #define DE_PLANEC_FLIP_DONE_IVB		(1 << 13)
7865 #define DE_PIPEC_VBLANK_IVB		(1 << 10)
7866 #define DE_SPRITEB_FLIP_DONE_IVB	(1 << 9)
7867 #define DE_PLANEB_FLIP_DONE_IVB		(1 << 8)
7868 #define DE_PIPEB_VBLANK_IVB		(1 << 5)
7869 #define DE_SPRITEA_FLIP_DONE_IVB	(1 << 4)
7870 #define DE_PLANEA_FLIP_DONE_IVB		(1 << 3)
7871 #define DE_PLANE_FLIP_DONE_IVB(plane)	(1 << (3 + 5 * (plane)))
7872 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
7873 #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
7874 
7875 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
7876 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
7877 
7878 #define DEISR   _MMIO(0x44000)
7879 #define DEIMR   _MMIO(0x44004)
7880 #define DEIIR   _MMIO(0x44008)
7881 #define DEIER   _MMIO(0x4400c)
7882 
7883 #define GTISR   _MMIO(0x44010)
7884 #define GTIMR   _MMIO(0x44014)
7885 #define GTIIR   _MMIO(0x44018)
7886 #define GTIER   _MMIO(0x4401c)
7887 
7888 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
7889 #define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
7890 #define  GEN8_PCU_IRQ			(1 << 30)
7891 #define  GEN8_DE_PCH_IRQ		(1 << 23)
7892 #define  GEN8_DE_MISC_IRQ		(1 << 22)
7893 #define  GEN8_DE_PORT_IRQ		(1 << 20)
7894 #define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
7895 #define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
7896 #define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
7897 #define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
7898 #define  GEN8_GT_VECS_IRQ		(1 << 6)
7899 #define  GEN8_GT_GUC_IRQ		(1 << 5)
7900 #define  GEN8_GT_PM_IRQ			(1 << 4)
7901 #define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
7902 #define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
7903 #define  GEN8_GT_BCS_IRQ		(1 << 1)
7904 #define  GEN8_GT_RCS_IRQ		(1 << 0)
7905 
7906 #define XELPD_DISPLAY_ERR_FATAL_MASK	_MMIO(0x4421c)
7907 
7908 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7909 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7910 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7911 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7912 
7913 #define GEN8_RCS_IRQ_SHIFT 0
7914 #define GEN8_BCS_IRQ_SHIFT 16
7915 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
7916 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7917 #define GEN8_VECS_IRQ_SHIFT 0
7918 #define GEN8_WD_IRQ_SHIFT 16
7919 
7920 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7921 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7922 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7923 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7924 #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
7925 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
7926 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
7927 #define  XELPD_PIPE_SOFT_UNDERRUN	(1 << 22)
7928 #define  XELPD_PIPE_HARD_UNDERRUN	(1 << 21)
7929 #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
7930 #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
7931 #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
7932 #define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
7933 #define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
7934 #define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
7935 #define  GEN8_PIPE_VSYNC		(1 << 1)
7936 #define  GEN8_PIPE_VBLANK		(1 << 0)
7937 #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
7938 #define  GEN11_PIPE_PLANE7_FAULT	(1 << 22)
7939 #define  GEN11_PIPE_PLANE6_FAULT	(1 << 21)
7940 #define  GEN11_PIPE_PLANE5_FAULT	(1 << 20)
7941 #define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
7942 #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
7943 #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
7944 #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
7945 #define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
7946 #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
7947 #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
7948 #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
7949 #define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
7950 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7951 	(GEN8_PIPE_CURSOR_FAULT | \
7952 	 GEN8_PIPE_SPRITE_FAULT | \
7953 	 GEN8_PIPE_PRIMARY_FAULT)
7954 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7955 	(GEN9_PIPE_CURSOR_FAULT | \
7956 	 GEN9_PIPE_PLANE4_FAULT | \
7957 	 GEN9_PIPE_PLANE3_FAULT | \
7958 	 GEN9_PIPE_PLANE2_FAULT | \
7959 	 GEN9_PIPE_PLANE1_FAULT)
7960 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
7961 	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
7962 	 GEN11_PIPE_PLANE7_FAULT | \
7963 	 GEN11_PIPE_PLANE6_FAULT | \
7964 	 GEN11_PIPE_PLANE5_FAULT)
7965 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
7966 	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
7967 	 GEN11_PIPE_PLANE5_FAULT)
7968 
7969 #define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
7970 #define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)
7971 
7972 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7973 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7974 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7975 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7976 #define  DSI1_NON_TE			(1 << 31)
7977 #define  DSI0_NON_TE			(1 << 30)
7978 #define  ICL_AUX_CHANNEL_E		(1 << 29)
7979 #define  ICL_AUX_CHANNEL_F		(1 << 28)
7980 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
7981 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
7982 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
7983 #define  DSI1_TE			(1 << 24)
7984 #define  DSI0_TE			(1 << 23)
7985 #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
7986 #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
7987 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
7988 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
7989 #define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
7990 #define  BXT_DE_PORT_GMBUS		(1 << 1)
7991 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
7992 #define  TGL_DE_PORT_AUX_USBC6		REG_BIT(13)
7993 #define  XELPD_DE_PORT_AUX_DDIE		REG_BIT(13)
7994 #define  TGL_DE_PORT_AUX_USBC5		REG_BIT(12)
7995 #define  XELPD_DE_PORT_AUX_DDID		REG_BIT(12)
7996 #define  TGL_DE_PORT_AUX_USBC4		REG_BIT(11)
7997 #define  TGL_DE_PORT_AUX_USBC3		REG_BIT(10)
7998 #define  TGL_DE_PORT_AUX_USBC2		REG_BIT(9)
7999 #define  TGL_DE_PORT_AUX_USBC1		REG_BIT(8)
8000 #define  TGL_DE_PORT_AUX_DDIC		REG_BIT(2)
8001 #define  TGL_DE_PORT_AUX_DDIB		REG_BIT(1)
8002 #define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
8003 
8004 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
8005 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
8006 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
8007 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
8008 #define  GEN8_DE_MISC_GSE		(1 << 27)
8009 #define  GEN8_DE_EDP_PSR		(1 << 19)
8010 
8011 #define GEN8_PCU_ISR _MMIO(0x444e0)
8012 #define GEN8_PCU_IMR _MMIO(0x444e4)
8013 #define GEN8_PCU_IIR _MMIO(0x444e8)
8014 #define GEN8_PCU_IER _MMIO(0x444ec)
8015 
8016 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
8017 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
8018 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
8019 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
8020 #define  GEN11_GU_MISC_GSE	(1 << 27)
8021 
8022 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
8023 #define  GEN11_MASTER_IRQ		(1 << 31)
8024 #define  GEN11_PCU_IRQ			(1 << 30)
8025 #define  GEN11_GU_MISC_IRQ		(1 << 29)
8026 #define  GEN11_DISPLAY_IRQ		(1 << 16)
8027 #define  GEN11_GT_DW_IRQ(x)		(1 << (x))
8028 #define  GEN11_GT_DW1_IRQ		(1 << 1)
8029 #define  GEN11_GT_DW0_IRQ		(1 << 0)
8030 
8031 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
8032 #define   DG1_MSTR_IRQ			REG_BIT(31)
8033 #define   DG1_MSTR_TILE(t)		REG_BIT(t)
8034 
8035 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
8036 #define  GEN11_DISPLAY_IRQ_ENABLE	(1 << 31)
8037 #define  GEN11_AUDIO_CODEC_IRQ		(1 << 24)
8038 #define  GEN11_DE_PCH_IRQ		(1 << 23)
8039 #define  GEN11_DE_MISC_IRQ		(1 << 22)
8040 #define  GEN11_DE_HPD_IRQ		(1 << 21)
8041 #define  GEN11_DE_PORT_IRQ		(1 << 20)
8042 #define  GEN11_DE_PIPE_C		(1 << 18)
8043 #define  GEN11_DE_PIPE_B		(1 << 17)
8044 #define  GEN11_DE_PIPE_A		(1 << 16)
8045 
8046 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
8047 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
8048 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
8049 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
8050 #define  GEN11_TC_HOTPLUG(hpd_pin)		REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
8051 #define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
8052 						 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
8053 						 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
8054 						 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
8055 						 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
8056 						 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
8057 #define  GEN11_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
8058 #define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
8059 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
8060 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
8061 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
8062 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
8063 						 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
8064 
8065 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
8066 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
8067 #define  GEN11_HOTPLUG_CTL_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
8068 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin)		(2 << (_HPD_PIN_TC(hpd_pin) * 4))
8069 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
8070 #define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
8071 
8072 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
8073 #define  GEN11_CSME			(31)
8074 #define  GEN11_GUNIT			(28)
8075 #define  GEN11_GUC			(25)
8076 #define  GEN11_WDPERF			(20)
8077 #define  GEN11_KCR			(19)
8078 #define  GEN11_GTPM			(16)
8079 #define  GEN11_BCS			(15)
8080 #define  GEN11_RCS0			(0)
8081 
8082 #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
8083 #define  GEN11_VECS(x)			(31 - (x))
8084 #define  GEN11_VCS(x)			(x)
8085 
8086 #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
8087 
8088 #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
8089 #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
8090 #define  GEN11_INTR_DATA_VALID		(1 << 31)
8091 #define  GEN11_INTR_ENGINE_CLASS(x)	(((x) & GENMASK(18, 16)) >> 16)
8092 #define  GEN11_INTR_ENGINE_INSTANCE(x)	(((x) & GENMASK(25, 20)) >> 20)
8093 #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
8094 /* irq instances for OTHER_CLASS */
8095 #define OTHER_GUC_INSTANCE	0
8096 #define OTHER_GTPM_INSTANCE	1
8097 
8098 #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
8099 
8100 #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
8101 #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
8102 
8103 #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
8104 
8105 #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
8106 #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
8107 #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
8108 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
8109 #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
8110 #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
8111 
8112 #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
8113 #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
8114 #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
8115 #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
8116 #define GEN12_VCS4_VCS5_INTR_MASK	_MMIO(0x1900b0)
8117 #define GEN12_VCS6_VCS7_INTR_MASK	_MMIO(0x1900b4)
8118 #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
8119 #define GEN12_VECS2_VECS3_INTR_MASK	_MMIO(0x1900d4)
8120 #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
8121 #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
8122 #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
8123 #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
8124 
8125 #define   ENGINE1_MASK			REG_GENMASK(31, 16)
8126 #define   ENGINE0_MASK			REG_GENMASK(15, 0)
8127 
8128 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
8129 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
8130 #define  ILK_ELPIN_409_SELECT	(1 << 25)
8131 #define  ILK_DPARB_GATE	(1 << 22)
8132 #define  ILK_VSDPFD_FULL	(1 << 21)
8133 #define FUSE_STRAP			_MMIO(0x42014)
8134 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
8135 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
8136 #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
8137 #define  IVB_PIPE_C_DISABLE		(1 << 28)
8138 #define  ILK_HDCP_DISABLE		(1 << 25)
8139 #define  ILK_eDP_A_DISABLE		(1 << 24)
8140 #define  HSW_CDCLK_LIMIT		(1 << 24)
8141 #define  ILK_DESKTOP			(1 << 23)
8142 #define  HSW_CPU_SSC_ENABLE		(1 << 21)
8143 
8144 #define FUSE_STRAP3			_MMIO(0x42020)
8145 #define  HSW_REF_CLK_SELECT		(1 << 1)
8146 
8147 #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
8148 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
8149 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
8150 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
8151 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
8152 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
8153 
8154 #define IVB_CHICKEN3	_MMIO(0x4200c)
8155 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
8156 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
8157 
8158 #define CHICKEN_PAR1_1			_MMIO(0x42080)
8159 #define  IGNORE_KVMR_PIPE_A		REG_BIT(23)
8160 #define  KBL_ARB_FILL_SPARE_22		REG_BIT(22)
8161 #define  DIS_RAM_BYPASS_PSR2_MAN_TRACK	(1 << 16)
8162 #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
8163 #define  DPA_MASK_VBLANK_SRD		(1 << 15)
8164 #define  FORCE_ARB_IDLE_PLANES		(1 << 14)
8165 #define  SKL_EDP_PSR_FIX_RDWRAP		(1 << 3)
8166 #define  IGNORE_PSR2_HW_TRACKING	(1 << 1)
8167 
8168 #define CHICKEN_PAR2_1		_MMIO(0x42090)
8169 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
8170 
8171 #define CHICKEN_MISC_2		_MMIO(0x42084)
8172 #define  KBL_ARB_FILL_SPARE_14	REG_BIT(14)
8173 #define  KBL_ARB_FILL_SPARE_13	REG_BIT(13)
8174 #define  GLK_CL2_PWR_DOWN	(1 << 12)
8175 #define  GLK_CL1_PWR_DOWN	(1 << 11)
8176 #define  GLK_CL0_PWR_DOWN	(1 << 10)
8177 
8178 #define CHICKEN_MISC_4		_MMIO(0x4208c)
8179 #define   FBC_STRIDE_OVERRIDE	(1 << 13)
8180 #define   FBC_STRIDE_MASK	0x1FFF
8181 
8182 #define _CHICKEN_PIPESL_1_A	0x420b0
8183 #define _CHICKEN_PIPESL_1_B	0x420b4
8184 #define  HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
8185 #define  HSW_PRI_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
8186 #define  HSW_PRI_STRETCH_MAX_X4		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
8187 #define  HSW_PRI_STRETCH_MAX_X2		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
8188 #define  HSW_PRI_STRETCH_MAX_X1		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
8189 #define  HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
8190 #define  HSW_SPR_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
8191 #define  HSW_SPR_STRETCH_MAX_X4		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
8192 #define  HSW_SPR_STRETCH_MAX_X2		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
8193 #define  HSW_SPR_STRETCH_MAX_X1		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
8194 #define  HSW_FBCQ_DIS			(1 << 22)
8195 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
8196 #define  SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
8197 #define  SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
8198 #define  SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
8199 #define  SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
8200 #define  SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
8201 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
8202 
8203 #define _CHICKEN_TRANS_A	0x420c0
8204 #define _CHICKEN_TRANS_B	0x420c4
8205 #define _CHICKEN_TRANS_C	0x420c8
8206 #define _CHICKEN_TRANS_EDP	0x420cc
8207 #define _CHICKEN_TRANS_D	0x420d8
8208 #define CHICKEN_TRANS(trans)	_MMIO(_PICK((trans), \
8209 					    [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
8210 					    [TRANSCODER_A] = _CHICKEN_TRANS_A, \
8211 					    [TRANSCODER_B] = _CHICKEN_TRANS_B, \
8212 					    [TRANSCODER_C] = _CHICKEN_TRANS_C, \
8213 					    [TRANSCODER_D] = _CHICKEN_TRANS_D))
8214 #define  HSW_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27)
8215 #define  HSW_FRAME_START_DELAY(x)	REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
8216 #define  VSC_DATA_SEL_SOFTWARE_CONTROL	REG_BIT(25) /* GLK */
8217 #define  FECSTALL_DIS_DPTSTREAM_DPTTG	REG_BIT(23)
8218 #define  DDI_TRAINING_OVERRIDE_ENABLE	REG_BIT(19)
8219 #define  DDI_TRAINING_OVERRIDE_VALUE	REG_BIT(18)
8220 #define  DDIE_TRAINING_OVERRIDE_ENABLE	REG_BIT(17) /* CHICKEN_TRANS_A only */
8221 #define  DDIE_TRAINING_OVERRIDE_VALUE	REG_BIT(16) /* CHICKEN_TRANS_A only */
8222 #define  PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
8223 #define  PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
8224 
8225 #define DISP_ARB_CTL	_MMIO(0x45000)
8226 #define  DISP_FBC_MEMORY_WAKE		(1 << 31)
8227 #define  DISP_TILE_SURFACE_SWIZZLING	(1 << 13)
8228 #define  DISP_FBC_WM_DIS		(1 << 15)
8229 #define DISP_ARB_CTL2	_MMIO(0x45004)
8230 #define  DISP_DATA_PARTITION_5_6	(1 << 6)
8231 #define  DISP_IPC_ENABLE		(1 << 3)
8232 
8233 /*
8234  * The below are numbered starting from "S1" on gen11/gen12, but starting
8235  * with gen13 display, the bspec switches to a 0-based numbering scheme
8236  * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
8237  * We'll just use the 0-based numbering here for all platforms since it's the
8238  * way things will be named by the hardware team going forward, plus it's more
8239  * consistent with how most of the rest of our registers are named.
8240  */
8241 #define _DBUF_CTL_S0				0x45008
8242 #define _DBUF_CTL_S1				0x44FE8
8243 #define _DBUF_CTL_S2				0x44300
8244 #define _DBUF_CTL_S3				0x44304
8245 #define DBUF_CTL_S(slice)			_MMIO(_PICK(slice, \
8246 							    _DBUF_CTL_S0, \
8247 							    _DBUF_CTL_S1, \
8248 							    _DBUF_CTL_S2, \
8249 							    _DBUF_CTL_S3))
8250 #define  DBUF_POWER_REQUEST			REG_BIT(31)
8251 #define  DBUF_POWER_STATE			REG_BIT(30)
8252 #define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
8253 #define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
8254 #define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(18, 16) /* ADL-P+ */
8255 #define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
8256 
8257 #define GEN7_MSG_CTL	_MMIO(0x45010)
8258 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
8259 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
8260 
8261 #define _BW_BUDDY0_CTL			0x45130
8262 #define _BW_BUDDY1_CTL			0x45140
8263 #define BW_BUDDY_CTL(x)			_MMIO(_PICK_EVEN(x, \
8264 							 _BW_BUDDY0_CTL, \
8265 							 _BW_BUDDY1_CTL))
8266 #define   BW_BUDDY_DISABLE		REG_BIT(31)
8267 #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
8268 #define   BW_BUDDY_TLB_REQ_TIMER(x)	REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
8269 
8270 #define _BW_BUDDY0_PAGE_MASK		0x45134
8271 #define _BW_BUDDY1_PAGE_MASK		0x45144
8272 #define BW_BUDDY_PAGE_MASK(x)		_MMIO(_PICK_EVEN(x, \
8273 							 _BW_BUDDY0_PAGE_MASK, \
8274 							 _BW_BUDDY1_PAGE_MASK))
8275 
8276 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
8277 #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
8278 
8279 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
8280 #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
8281 #define   ICL_DELAY_PMRSP		(1 << 22)
8282 #define   MASK_WAKEMEM			(1 << 13)
8283 
8284 #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
8285 #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR	REG_BIT(27)
8286 #define   DCPR_MASK_LPMODE			REG_BIT(26)
8287 #define   DCPR_SEND_RESP_IMM			REG_BIT(25)
8288 #define   DCPR_CLEAR_MEMSTAT_DIS		REG_BIT(24)
8289 
8290 #define SKL_DFSM			_MMIO(0x51000)
8291 #define   SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)
8292 #define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)
8293 #define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
8294 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
8295 #define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
8296 #define   SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
8297 #define   SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
8298 #define   ICL_DFSM_DMC_DISABLE		(1 << 23)
8299 #define   SKL_DFSM_PIPE_A_DISABLE	(1 << 30)
8300 #define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
8301 #define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
8302 #define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
8303 #define   GLK_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
8304 
8305 #define SKL_DSSM				_MMIO(0x51004)
8306 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
8307 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
8308 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
8309 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
8310 
8311 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
8312 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1 << 14)
8313 
8314 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
8315 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1 << 8)
8316 #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
8317 
8318 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
8319 #define   FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(1)
8320 #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
8321 #define   GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
8322 
8323 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
8324 #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
8325 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)	(((hi) << 2) | ((lo) << 1))
8326 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8327 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8328 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8329 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK		GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
8330 
8331 /* GEN7 chicken */
8332 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
8333   #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	(1 << 10)
8334   #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
8335 
8336 #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
8337   #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
8338   #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
8339   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
8340   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
8341 
8342 #define GEN8_L3CNTLREG	_MMIO(0x7034)
8343   #define GEN8_ERRDETBCTRL (1 << 9)
8344 
8345 #define GEN11_COMMON_SLICE_CHICKEN3			_MMIO(0x7304)
8346   #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
8347   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC		REG_BIT(11)
8348   #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE		REG_BIT(9)
8349 
8350 #define HIZ_CHICKEN					_MMIO(0x7018)
8351 # define CHV_HZ_8X8_MODE_IN_1X				REG_BIT(15)
8352 # define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE   REG_BIT(14)
8353 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT(3)
8354 
8355 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
8356 #define  DISABLE_PIXEL_MASK_CAMMING		(1 << 14)
8357 
8358 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
8359 #define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
8360 
8361 #define GEN7_SARCHKMD				_MMIO(0xB000)
8362 #define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
8363 #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
8364 
8365 #define GEN7_L3SQCREG1				_MMIO(0xB010)
8366 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
8367 
8368 #define GEN8_L3SQCREG1				_MMIO(0xB100)
8369 /*
8370  * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8371  * Using the formula in BSpec leads to a hang, while the formula here works
8372  * fine and matches the formulas for all other platforms. A BSpec change
8373  * request has been filed to clarify this.
8374  */
8375 #define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)
8376 #define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)
8377 #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
8378 
8379 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
8380 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
8381 #define  GEN7_L3AGDIS				(1 << 19)
8382 #define GEN7_L3CNTLREG2				_MMIO(0xB020)
8383 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
8384 
8385 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
8386 #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
8387 #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
8388 #define   GEN11_I2M_WRITE_DISABLE		(1 << 28)
8389 
8390 #define GEN7_L3SQCREG4				_MMIO(0xb034)
8391 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)
8392 
8393 #define GEN11_SCRATCH2					_MMIO(0xb140)
8394 #define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE	(1 << 19)
8395 
8396 #define GEN8_L3SQCREG4				_MMIO(0xb118)
8397 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
8398 #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
8399 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
8400 #define  GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
8401 
8402 /* GEN8 chicken */
8403 #define HDC_CHICKEN0				_MMIO(0x7300)
8404 #define ICL_HDC_MODE				_MMIO(0xE5F4)
8405 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
8406 #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
8407 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
8408 #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
8409 #define  HDC_FORCE_NON_COHERENT			(1 << 4)
8410 #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
8411 
8412 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
8413 
8414 /* GEN9 chicken */
8415 #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
8416 #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
8417 
8418 #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
8419 #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
8420 
8421 /* WaCatErrorRejectionIssue */
8422 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
8423 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1 << 11)
8424 
8425 #define HSW_SCRATCH1				_MMIO(0xb038)
8426 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1 << 27)
8427 
8428 #define BDW_SCRATCH1					_MMIO(0xb11c)
8429 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
8430 
8431 /*GEN11 chicken */
8432 #define _PIPEA_CHICKEN				0x70038
8433 #define _PIPEB_CHICKEN				0x71038
8434 #define _PIPEC_CHICKEN				0x72038
8435 #define PIPE_CHICKEN(pipe)			_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
8436 							   _PIPEB_CHICKEN)
8437 #define   UNDERRUN_RECOVERY_DISABLE_ADLP	REG_BIT(30)
8438 #define   UNDERRUN_RECOVERY_ENABLE_DG2		REG_BIT(30)
8439 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
8440 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
8441 
8442 #define FF_MODE2			_MMIO(0x6604)
8443 #define   FF_MODE2_GS_TIMER_MASK	REG_GENMASK(31, 24)
8444 #define   FF_MODE2_GS_TIMER_224		REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
8445 #define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
8446 #define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
8447 
8448 /* PCH */
8449 
8450 #define PCH_DISPLAY_BASE	0xc0000u
8451 
8452 /* south display engine interrupt: IBX */
8453 #define SDE_AUDIO_POWER_D	(1 << 27)
8454 #define SDE_AUDIO_POWER_C	(1 << 26)
8455 #define SDE_AUDIO_POWER_B	(1 << 25)
8456 #define SDE_AUDIO_POWER_SHIFT	(25)
8457 #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
8458 #define SDE_GMBUS		(1 << 24)
8459 #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
8460 #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
8461 #define SDE_AUDIO_HDCP_MASK	(3 << 22)
8462 #define SDE_AUDIO_TRANSB	(1 << 21)
8463 #define SDE_AUDIO_TRANSA	(1 << 20)
8464 #define SDE_AUDIO_TRANS_MASK	(3 << 20)
8465 #define SDE_POISON		(1 << 19)
8466 /* 18 reserved */
8467 #define SDE_FDI_RXB		(1 << 17)
8468 #define SDE_FDI_RXA		(1 << 16)
8469 #define SDE_FDI_MASK		(3 << 16)
8470 #define SDE_AUXD		(1 << 15)
8471 #define SDE_AUXC		(1 << 14)
8472 #define SDE_AUXB		(1 << 13)
8473 #define SDE_AUX_MASK		(7 << 13)
8474 /* 12 reserved */
8475 #define SDE_CRT_HOTPLUG         (1 << 11)
8476 #define SDE_PORTD_HOTPLUG       (1 << 10)
8477 #define SDE_PORTC_HOTPLUG       (1 << 9)
8478 #define SDE_PORTB_HOTPLUG       (1 << 8)
8479 #define SDE_SDVOB_HOTPLUG       (1 << 6)
8480 #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
8481 				 SDE_SDVOB_HOTPLUG |	\
8482 				 SDE_PORTB_HOTPLUG |	\
8483 				 SDE_PORTC_HOTPLUG |	\
8484 				 SDE_PORTD_HOTPLUG)
8485 #define SDE_TRANSB_CRC_DONE	(1 << 5)
8486 #define SDE_TRANSB_CRC_ERR	(1 << 4)
8487 #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
8488 #define SDE_TRANSA_CRC_DONE	(1 << 2)
8489 #define SDE_TRANSA_CRC_ERR	(1 << 1)
8490 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
8491 #define SDE_TRANS_MASK		(0x3f)
8492 
8493 /* south display engine interrupt: CPT - CNP */
8494 #define SDE_AUDIO_POWER_D_CPT	(1 << 31)
8495 #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
8496 #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
8497 #define SDE_AUDIO_POWER_SHIFT_CPT   29
8498 #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
8499 #define SDE_AUXD_CPT		(1 << 27)
8500 #define SDE_AUXC_CPT		(1 << 26)
8501 #define SDE_AUXB_CPT		(1 << 25)
8502 #define SDE_AUX_MASK_CPT	(7 << 25)
8503 #define SDE_PORTE_HOTPLUG_SPT	(1 << 25)
8504 #define SDE_PORTA_HOTPLUG_SPT	(1 << 24)
8505 #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
8506 #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
8507 #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
8508 #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
8509 #define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
8510 #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
8511 				 SDE_SDVOB_HOTPLUG_CPT |	\
8512 				 SDE_PORTD_HOTPLUG_CPT |	\
8513 				 SDE_PORTC_HOTPLUG_CPT |	\
8514 				 SDE_PORTB_HOTPLUG_CPT)
8515 #define SDE_HOTPLUG_MASK_SPT	(SDE_PORTE_HOTPLUG_SPT |	\
8516 				 SDE_PORTD_HOTPLUG_CPT |	\
8517 				 SDE_PORTC_HOTPLUG_CPT |	\
8518 				 SDE_PORTB_HOTPLUG_CPT |	\
8519 				 SDE_PORTA_HOTPLUG_SPT)
8520 #define SDE_GMBUS_CPT		(1 << 17)
8521 #define SDE_ERROR_CPT		(1 << 16)
8522 #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
8523 #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
8524 #define SDE_FDI_RXC_CPT		(1 << 8)
8525 #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
8526 #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
8527 #define SDE_FDI_RXB_CPT		(1 << 4)
8528 #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
8529 #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
8530 #define SDE_FDI_RXA_CPT		(1 << 0)
8531 #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
8532 				 SDE_AUDIO_CP_REQ_B_CPT | \
8533 				 SDE_AUDIO_CP_REQ_A_CPT)
8534 #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
8535 				 SDE_AUDIO_CP_CHG_B_CPT | \
8536 				 SDE_AUDIO_CP_CHG_A_CPT)
8537 #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
8538 				 SDE_FDI_RXB_CPT | \
8539 				 SDE_FDI_RXA_CPT)
8540 
8541 /* south display engine interrupt: ICP/TGP */
8542 #define SDE_GMBUS_ICP			(1 << 23)
8543 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
8544 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
8545 #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
8546 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
8547 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
8548 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
8549 #define SDE_TC_HOTPLUG_MASK_ICP		(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
8550 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
8551 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
8552 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
8553 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
8554 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
8555 
8556 #define SDEISR  _MMIO(0xc4000)
8557 #define SDEIMR  _MMIO(0xc4004)
8558 #define SDEIIR  _MMIO(0xc4008)
8559 #define SDEIER  _MMIO(0xc400c)
8560 
8561 #define SERR_INT			_MMIO(0xc4040)
8562 #define  SERR_INT_POISON		(1 << 31)
8563 #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
8564 
8565 /* digital port hotplug */
8566 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
8567 #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
8568 #define  BXT_DDIA_HPD_INVERT            (1 << 27)
8569 #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
8570 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
8571 #define  PORTA_HOTPLUG_SHORT_DETECT	(1 << 24) /* SPT+ & BXT */
8572 #define  PORTA_HOTPLUG_LONG_DETECT	(2 << 24) /* SPT+ & BXT */
8573 #define  PORTD_HOTPLUG_ENABLE		(1 << 20)
8574 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
8575 #define  PORTD_PULSE_DURATION_4_5ms	(1 << 18) /* pre-LPT */
8576 #define  PORTD_PULSE_DURATION_6ms	(2 << 18) /* pre-LPT */
8577 #define  PORTD_PULSE_DURATION_100ms	(3 << 18) /* pre-LPT */
8578 #define  PORTD_PULSE_DURATION_MASK	(3 << 18) /* pre-LPT */
8579 #define  PORTD_HOTPLUG_STATUS_MASK	(3 << 16)
8580 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
8581 #define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
8582 #define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
8583 #define  PORTC_HOTPLUG_ENABLE		(1 << 12)
8584 #define  BXT_DDIC_HPD_INVERT            (1 << 11)
8585 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
8586 #define  PORTC_PULSE_DURATION_4_5ms	(1 << 10) /* pre-LPT */
8587 #define  PORTC_PULSE_DURATION_6ms	(2 << 10) /* pre-LPT */
8588 #define  PORTC_PULSE_DURATION_100ms	(3 << 10) /* pre-LPT */
8589 #define  PORTC_PULSE_DURATION_MASK	(3 << 10) /* pre-LPT */
8590 #define  PORTC_HOTPLUG_STATUS_MASK	(3 << 8)
8591 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
8592 #define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
8593 #define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
8594 #define  PORTB_HOTPLUG_ENABLE		(1 << 4)
8595 #define  BXT_DDIB_HPD_INVERT            (1 << 3)
8596 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
8597 #define  PORTB_PULSE_DURATION_4_5ms	(1 << 2) /* pre-LPT */
8598 #define  PORTB_PULSE_DURATION_6ms	(2 << 2) /* pre-LPT */
8599 #define  PORTB_PULSE_DURATION_100ms	(3 << 2) /* pre-LPT */
8600 #define  PORTB_PULSE_DURATION_MASK	(3 << 2) /* pre-LPT */
8601 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
8602 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
8603 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
8604 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
8605 #define  BXT_DDI_HPD_INVERT_MASK	(BXT_DDIA_HPD_INVERT | \
8606 					BXT_DDIB_HPD_INVERT | \
8607 					BXT_DDIC_HPD_INVERT)
8608 
8609 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
8610 #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
8611 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
8612 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
8613 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
8614 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
8615 
8616 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
8617  * functionality covered in PCH_PORT_HOTPLUG is split into
8618  * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
8619  */
8620 
8621 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
8622 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
8623 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8624 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
8625 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
8626 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
8627 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8628 
8629 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
8630 #define   ICP_TC_HPD_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
8631 #define   ICP_TC_HPD_LONG_DETECT(hpd_pin)	(2 << (_HPD_PIN_TC(hpd_pin) * 4))
8632 #define   ICP_TC_HPD_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
8633 
8634 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
8635 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
8636 
8637 #define _PCH_DPLL_A              0xc6014
8638 #define _PCH_DPLL_B              0xc6018
8639 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8640 
8641 #define _PCH_FPA0                0xc6040
8642 #define  FP_CB_TUNE		(0x3 << 22)
8643 #define _PCH_FPA1                0xc6044
8644 #define _PCH_FPB0                0xc6048
8645 #define _PCH_FPB1                0xc604c
8646 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8647 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8648 
8649 #define PCH_DPLL_TEST           _MMIO(0xc606c)
8650 
8651 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
8652 #define  DREF_CONTROL_MASK      0x7fc3
8653 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
8654 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2 << 13)
8655 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3 << 13)
8656 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3 << 13)
8657 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
8658 #define  DREF_SSC_SOURCE_ENABLE                 (2 << 11)
8659 #define  DREF_SSC_SOURCE_MASK			(3 << 11)
8660 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
8661 #define  DREF_NONSPREAD_CK505_ENABLE		(1 << 9)
8662 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2 << 9)
8663 #define  DREF_NONSPREAD_SOURCE_MASK		(3 << 9)
8664 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
8665 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2 << 7)
8666 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3 << 7)
8667 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
8668 #define  DREF_SSC4_CENTERSPREAD                 (1 << 6)
8669 #define  DREF_SSC1_DISABLE                      (0 << 1)
8670 #define  DREF_SSC1_ENABLE                       (1 << 1)
8671 #define  DREF_SSC4_DISABLE                      (0)
8672 #define  DREF_SSC4_ENABLE                       (1)
8673 
8674 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
8675 #define  FDL_TP1_TIMER_SHIFT    12
8676 #define  FDL_TP1_TIMER_MASK     (3 << 12)
8677 #define  FDL_TP2_TIMER_SHIFT    10
8678 #define  FDL_TP2_TIMER_MASK     (3 << 10)
8679 #define  RAWCLK_FREQ_MASK       0x3ff
8680 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
8681 #define  CNP_RAWCLK_DIV(div)	((div) << 16)
8682 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
8683 #define  CNP_RAWCLK_DEN(den)	((den) << 26)
8684 #define  ICP_RAWCLK_NUM(num)	((num) << 11)
8685 
8686 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
8687 
8688 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
8689 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
8690 
8691 #define PCH_DPLL_SEL		_MMIO(0xc7000)
8692 #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
8693 #define	 TRANS_DPLLA_SEL(pipe)		0
8694 #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
8695 
8696 /* transcoder */
8697 
8698 #define _PCH_TRANS_HTOTAL_A		0xe0000
8699 #define  TRANS_HTOTAL_SHIFT		16
8700 #define  TRANS_HACTIVE_SHIFT		0
8701 #define _PCH_TRANS_HBLANK_A		0xe0004
8702 #define  TRANS_HBLANK_END_SHIFT		16
8703 #define  TRANS_HBLANK_START_SHIFT	0
8704 #define _PCH_TRANS_HSYNC_A		0xe0008
8705 #define  TRANS_HSYNC_END_SHIFT		16
8706 #define  TRANS_HSYNC_START_SHIFT	0
8707 #define _PCH_TRANS_VTOTAL_A		0xe000c
8708 #define  TRANS_VTOTAL_SHIFT		16
8709 #define  TRANS_VACTIVE_SHIFT		0
8710 #define _PCH_TRANS_VBLANK_A		0xe0010
8711 #define  TRANS_VBLANK_END_SHIFT		16
8712 #define  TRANS_VBLANK_START_SHIFT	0
8713 #define _PCH_TRANS_VSYNC_A		0xe0014
8714 #define  TRANS_VSYNC_END_SHIFT		16
8715 #define  TRANS_VSYNC_START_SHIFT	0
8716 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
8717 
8718 #define _PCH_TRANSA_DATA_M1	0xe0030
8719 #define _PCH_TRANSA_DATA_N1	0xe0034
8720 #define _PCH_TRANSA_DATA_M2	0xe0038
8721 #define _PCH_TRANSA_DATA_N2	0xe003c
8722 #define _PCH_TRANSA_LINK_M1	0xe0040
8723 #define _PCH_TRANSA_LINK_N1	0xe0044
8724 #define _PCH_TRANSA_LINK_M2	0xe0048
8725 #define _PCH_TRANSA_LINK_N2	0xe004c
8726 
8727 /* Per-transcoder DIP controls (PCH) */
8728 #define _VIDEO_DIP_CTL_A         0xe0200
8729 #define _VIDEO_DIP_DATA_A        0xe0208
8730 #define _VIDEO_DIP_GCP_A         0xe0210
8731 #define  GCP_COLOR_INDICATION		(1 << 2)
8732 #define  GCP_DEFAULT_PHASE_ENABLE	(1 << 1)
8733 #define  GCP_AV_MUTE			(1 << 0)
8734 
8735 #define _VIDEO_DIP_CTL_B         0xe1200
8736 #define _VIDEO_DIP_DATA_B        0xe1208
8737 #define _VIDEO_DIP_GCP_B         0xe1210
8738 
8739 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8740 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8741 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8742 
8743 /* Per-transcoder DIP controls (VLV) */
8744 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
8745 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
8746 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
8747 
8748 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
8749 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
8750 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
8751 
8752 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
8753 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
8754 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
8755 
8756 #define VLV_TVIDEO_DIP_CTL(pipe) \
8757 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8758 	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8759 #define VLV_TVIDEO_DIP_DATA(pipe) \
8760 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8761 	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8762 #define VLV_TVIDEO_DIP_GCP(pipe) \
8763 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8764 		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8765 
8766 /* Haswell DIP controls */
8767 
8768 #define _HSW_VIDEO_DIP_CTL_A		0x60200
8769 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
8770 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
8771 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
8772 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
8773 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
8774 #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
8775 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
8776 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
8777 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
8778 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
8779 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
8780 #define _HSW_VIDEO_DIP_GCP_A		0x60210
8781 
8782 #define _HSW_VIDEO_DIP_CTL_B		0x61200
8783 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
8784 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
8785 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
8786 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
8787 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
8788 #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
8789 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
8790 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
8791 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
8792 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
8793 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
8794 #define _HSW_VIDEO_DIP_GCP_B		0x61210
8795 
8796 /* Icelake PPS_DATA and _ECC DIP Registers.
8797  * These are available for transcoders B,C and eDP.
8798  * Adding the _A so as to reuse the _MMIO_TRANS2
8799  * definition, with which it offsets to the right location.
8800  */
8801 
8802 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
8803 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
8804 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
8805 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
8806 
8807 #define HSW_TVIDEO_DIP_CTL(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8808 #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8809 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8810 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8811 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8812 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8813 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8814 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8815 #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8816 #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8817 
8818 #define _HSW_STEREO_3D_CTL_A		0x70020
8819 #define   S3D_ENABLE			(1 << 31)
8820 #define _HSW_STEREO_3D_CTL_B		0x71020
8821 
8822 #define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8823 
8824 #define _PCH_TRANS_HTOTAL_B          0xe1000
8825 #define _PCH_TRANS_HBLANK_B          0xe1004
8826 #define _PCH_TRANS_HSYNC_B           0xe1008
8827 #define _PCH_TRANS_VTOTAL_B          0xe100c
8828 #define _PCH_TRANS_VBLANK_B          0xe1010
8829 #define _PCH_TRANS_VSYNC_B           0xe1014
8830 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8831 
8832 #define PCH_TRANS_HTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8833 #define PCH_TRANS_HBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8834 #define PCH_TRANS_HSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8835 #define PCH_TRANS_VTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8836 #define PCH_TRANS_VBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8837 #define PCH_TRANS_VSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8838 #define PCH_TRANS_VSYNCSHIFT(pipe)	_MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8839 
8840 #define _PCH_TRANSB_DATA_M1	0xe1030
8841 #define _PCH_TRANSB_DATA_N1	0xe1034
8842 #define _PCH_TRANSB_DATA_M2	0xe1038
8843 #define _PCH_TRANSB_DATA_N2	0xe103c
8844 #define _PCH_TRANSB_LINK_M1	0xe1040
8845 #define _PCH_TRANSB_LINK_N1	0xe1044
8846 #define _PCH_TRANSB_LINK_M2	0xe1048
8847 #define _PCH_TRANSB_LINK_N2	0xe104c
8848 
8849 #define PCH_TRANS_DATA_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8850 #define PCH_TRANS_DATA_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8851 #define PCH_TRANS_DATA_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8852 #define PCH_TRANS_DATA_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8853 #define PCH_TRANS_LINK_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8854 #define PCH_TRANS_LINK_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8855 #define PCH_TRANS_LINK_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8856 #define PCH_TRANS_LINK_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8857 
8858 #define _PCH_TRANSACONF              0xf0008
8859 #define _PCH_TRANSBCONF              0xf1008
8860 #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8861 #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8862 #define  TRANS_DISABLE          (0 << 31)
8863 #define  TRANS_ENABLE           (1 << 31)
8864 #define  TRANS_STATE_MASK       (1 << 30)
8865 #define  TRANS_STATE_DISABLE    (0 << 30)
8866 #define  TRANS_STATE_ENABLE     (1 << 30)
8867 #define  TRANS_FRAME_START_DELAY_MASK	(3 << 27) /* ibx */
8868 #define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
8869 #define  TRANS_INTERLACE_MASK   (7 << 21)
8870 #define  TRANS_PROGRESSIVE      (0 << 21)
8871 #define  TRANS_INTERLACED       (3 << 21)
8872 #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8873 #define  TRANS_8BPC             (0 << 5)
8874 #define  TRANS_10BPC            (1 << 5)
8875 #define  TRANS_6BPC             (2 << 5)
8876 #define  TRANS_12BPC            (3 << 5)
8877 
8878 #define _TRANSA_CHICKEN1	 0xf0060
8879 #define _TRANSB_CHICKEN1	 0xf1060
8880 #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8881 #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1 << 10)
8882 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1 << 4)
8883 #define _TRANSA_CHICKEN2	 0xf0064
8884 #define _TRANSB_CHICKEN2	 0xf1064
8885 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8886 #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1 << 31)
8887 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1 << 29)
8888 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3 << 27)
8889 #define  TRANS_CHICKEN2_FRAME_START_DELAY(x)		((x) << 27) /* 0-3 */
8890 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1 << 26)
8891 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1 << 25)
8892 
8893 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
8894 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
8895 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
8896 #define  INVERT_DDID_HPD			(1 << 18)
8897 #define  INVERT_DDIC_HPD			(1 << 17)
8898 #define  INVERT_DDIB_HPD			(1 << 16)
8899 #define  INVERT_DDIA_HPD			(1 << 15)
8900 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8901 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8902 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
8903 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
8904 #define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
8905 #define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
8906 #define  SPT_PWM_GRANULARITY		(1 << 0)
8907 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
8908 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
8909 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
8910 #define  LPT_PWM_GRANULARITY		(1 << 5)
8911 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
8912 
8913 #define _FDI_RXA_CHICKEN        0xc200c
8914 #define _FDI_RXB_CHICKEN        0xc2010
8915 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
8916 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
8917 #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8918 
8919 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
8920 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8921 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8922 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8923 #define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
8924 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8925 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8926 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
8927 
8928 /* CPU: FDI_TX */
8929 #define _FDI_TXA_CTL            0x60100
8930 #define _FDI_TXB_CTL            0x61100
8931 #define FDI_TX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8932 #define  FDI_TX_DISABLE         (0 << 31)
8933 #define  FDI_TX_ENABLE          (1 << 31)
8934 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8935 #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
8936 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
8937 #define  FDI_LINK_TRAIN_NONE            (3 << 28)
8938 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8939 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
8940 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
8941 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
8942 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8943 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8944 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
8945 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
8946 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8947    SNB has different settings. */
8948 /* SNB A-stepping */
8949 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8950 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8951 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8952 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8953 /* SNB B-stepping */
8954 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
8955 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
8956 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
8957 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
8958 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
8959 #define  FDI_DP_PORT_WIDTH_SHIFT		19
8960 #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
8961 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8962 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
8963 /* Ironlake: hardwired to 1 */
8964 #define  FDI_TX_PLL_ENABLE              (1 << 14)
8965 
8966 /* Ivybridge has different bits for lolz */
8967 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8968 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
8969 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
8970 #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
8971 
8972 /* both Tx and Rx */
8973 #define  FDI_COMPOSITE_SYNC		(1 << 11)
8974 #define  FDI_LINK_TRAIN_AUTO		(1 << 10)
8975 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8976 #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
8977 
8978 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8979 #define _FDI_RXA_CTL             0xf000c
8980 #define _FDI_RXB_CTL             0xf100c
8981 #define FDI_RX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8982 #define  FDI_RX_ENABLE          (1 << 31)
8983 /* train, dp width same as FDI_TX */
8984 #define  FDI_FS_ERRC_ENABLE		(1 << 27)
8985 #define  FDI_FE_ERRC_ENABLE		(1 << 26)
8986 #define  FDI_RX_POLARITY_REVERSED_LPT	(1 << 16)
8987 #define  FDI_8BPC                       (0 << 16)
8988 #define  FDI_10BPC                      (1 << 16)
8989 #define  FDI_6BPC                       (2 << 16)
8990 #define  FDI_12BPC                      (3 << 16)
8991 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
8992 #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
8993 #define  FDI_RX_PLL_ENABLE              (1 << 13)
8994 #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
8995 #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
8996 #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
8997 #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
8998 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
8999 #define  FDI_PCDCLK	                (1 << 4)
9000 /* CPT */
9001 #define  FDI_AUTO_TRAINING			(1 << 10)
9002 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
9003 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1 << 8)
9004 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
9005 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
9006 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
9007 
9008 #define _FDI_RXA_MISC			0xf0010
9009 #define _FDI_RXB_MISC			0xf1010
9010 #define  FDI_RX_PWRDN_LANE1_MASK	(3 << 26)
9011 #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
9012 #define  FDI_RX_PWRDN_LANE0_MASK	(3 << 24)
9013 #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
9014 #define  FDI_RX_TP1_TO_TP2_48		(2 << 20)
9015 #define  FDI_RX_TP1_TO_TP2_64		(3 << 20)
9016 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
9017 #define FDI_RX_MISC(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
9018 
9019 #define _FDI_RXA_TUSIZE1        0xf0030
9020 #define _FDI_RXA_TUSIZE2        0xf0038
9021 #define _FDI_RXB_TUSIZE1        0xf1030
9022 #define _FDI_RXB_TUSIZE2        0xf1038
9023 #define FDI_RX_TUSIZE1(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
9024 #define FDI_RX_TUSIZE2(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
9025 
9026 /* FDI_RX interrupt register format */
9027 #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
9028 #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
9029 #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
9030 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
9031 #define FDI_RX_FS_CODE_ERR              (1 << 6)
9032 #define FDI_RX_FE_CODE_ERR              (1 << 5)
9033 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
9034 #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
9035 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
9036 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
9037 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
9038 
9039 #define _FDI_RXA_IIR            0xf0014
9040 #define _FDI_RXA_IMR            0xf0018
9041 #define _FDI_RXB_IIR            0xf1014
9042 #define _FDI_RXB_IMR            0xf1018
9043 #define FDI_RX_IIR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
9044 #define FDI_RX_IMR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
9045 
9046 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
9047 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
9048 
9049 #define PCH_LVDS	_MMIO(0xe1180)
9050 #define  LVDS_DETECTED	(1 << 1)
9051 
9052 #define _PCH_DP_B		0xe4100
9053 #define PCH_DP_B		_MMIO(_PCH_DP_B)
9054 #define _PCH_DPB_AUX_CH_CTL	0xe4110
9055 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
9056 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
9057 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
9058 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
9059 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
9060 
9061 #define _PCH_DP_C		0xe4200
9062 #define PCH_DP_C		_MMIO(_PCH_DP_C)
9063 #define _PCH_DPC_AUX_CH_CTL	0xe4210
9064 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
9065 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
9066 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
9067 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
9068 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
9069 
9070 #define _PCH_DP_D		0xe4300
9071 #define PCH_DP_D		_MMIO(_PCH_DP_D)
9072 #define _PCH_DPD_AUX_CH_CTL	0xe4310
9073 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
9074 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
9075 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
9076 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
9077 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
9078 
9079 #define PCH_DP_AUX_CH_CTL(aux_ch)		_MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
9080 #define PCH_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
9081 
9082 /* CPT */
9083 #define _TRANS_DP_CTL_A		0xe0300
9084 #define _TRANS_DP_CTL_B		0xe1300
9085 #define _TRANS_DP_CTL_C		0xe2300
9086 #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
9087 #define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
9088 #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
9089 #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
9090 #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
9091 #define  TRANS_DP_AUDIO_ONLY	(1 << 26)
9092 #define  TRANS_DP_ENH_FRAMING	(1 << 18)
9093 #define  TRANS_DP_8BPC		(0 << 9)
9094 #define  TRANS_DP_10BPC		(1 << 9)
9095 #define  TRANS_DP_6BPC		(2 << 9)
9096 #define  TRANS_DP_12BPC		(3 << 9)
9097 #define  TRANS_DP_BPC_MASK	(3 << 9)
9098 #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
9099 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
9100 #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
9101 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
9102 #define  TRANS_DP_SYNC_MASK	(3 << 3)
9103 
9104 /* SNB eDP training params */
9105 /* SNB A-stepping */
9106 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
9107 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
9108 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
9109 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
9110 /* SNB B-stepping */
9111 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
9112 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
9113 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
9114 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
9115 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
9116 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
9117 
9118 /* IVB */
9119 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
9120 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
9121 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
9122 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
9123 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
9124 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
9125 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
9126 
9127 /* legacy values */
9128 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
9129 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
9130 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
9131 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
9132 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
9133 
9134 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
9135 
9136 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
9137 
9138 #define  RC6_LOCATION				_MMIO(0xD40)
9139 #define	   RC6_CTX_IN_DRAM			(1 << 0)
9140 #define  RC6_CTX_BASE				_MMIO(0xD48)
9141 #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
9142 #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
9143 #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
9144 #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
9145 #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
9146 #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
9147 #define    IDLE_TIME_MASK			0xFFFFF
9148 #define  FORCEWAKE				_MMIO(0xA18C)
9149 #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
9150 #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
9151 #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
9152 #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
9153 #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
9154 #define  FORCEWAKE_ACK				_MMIO(0x130090)
9155 #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
9156 #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
9157 #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
9158 #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
9159 
9160 #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
9161 #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
9162 #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
9163 #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
9164 #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
9165 #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
9166 #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
9167 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
9168 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
9169 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
9170 #define  FORCEWAKE_GT_GEN9			_MMIO(0xa188)
9171 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
9172 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
9173 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
9174 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
9175 #define  FORCEWAKE_ACK_GT_GEN9			_MMIO(0x130044)
9176 #define   FORCEWAKE_KERNEL			BIT(0)
9177 #define   FORCEWAKE_USER			BIT(1)
9178 #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
9179 #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
9180 #define  ECOBUS					_MMIO(0xa180)
9181 #define    FORCEWAKE_MT_ENABLE			(1 << 5)
9182 #define  VLV_SPAREG2H				_MMIO(0xA194)
9183 #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
9184 #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
9185 #define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
9186 
9187 #define  GTFIFODBG				_MMIO(0x120000)
9188 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
9189 #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
9190 #define    GT_FIFO_SBDROPERR			(1 << 6)
9191 #define    GT_FIFO_BLOBDROPERR			(1 << 5)
9192 #define    GT_FIFO_SB_READ_ABORTERR		(1 << 4)
9193 #define    GT_FIFO_DROPERR			(1 << 3)
9194 #define    GT_FIFO_OVFERR			(1 << 2)
9195 #define    GT_FIFO_IAWRERR			(1 << 1)
9196 #define    GT_FIFO_IARDERR			(1 << 0)
9197 
9198 #define  GTFIFOCTL				_MMIO(0x120008)
9199 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
9200 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
9201 #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
9202 #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
9203 
9204 #define  HSW_IDICR				_MMIO(0x9008)
9205 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
9206 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
9207 #define    EDRAM_ENABLED			0x1
9208 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
9209 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
9210 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
9211 
9212 #define GEN6_UCGCTL1				_MMIO(0x9400)
9213 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)
9214 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
9215 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
9216 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
9217 
9218 #define GEN6_UCGCTL2				_MMIO(0x9404)
9219 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
9220 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
9221 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
9222 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
9223 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
9224 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
9225 
9226 #define GEN6_UCGCTL3				_MMIO(0x9408)
9227 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE		(1 << 20)
9228 
9229 #define GEN7_UCGCTL4				_MMIO(0x940c)
9230 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1 << 25)
9231 #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1 << 14)
9232 
9233 #define GEN6_RCGCTL1				_MMIO(0x9410)
9234 #define GEN6_RCGCTL2				_MMIO(0x9414)
9235 #define GEN6_RSTCTL				_MMIO(0x9420)
9236 
9237 #define GEN8_UCGCTL6				_MMIO(0x9430)
9238 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1 << 24)
9239 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1 << 14)
9240 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
9241 
9242 #define GEN6_GFXPAUSE				_MMIO(0xA000)
9243 #define GEN6_RPNSWREQ				_MMIO(0xA008)
9244 #define   GEN6_TURBO_DISABLE			(1 << 31)
9245 #define   GEN6_FREQUENCY(x)			((x) << 25)
9246 #define   HSW_FREQUENCY(x)			((x) << 24)
9247 #define   GEN9_FREQUENCY(x)			((x) << 23)
9248 #define   GEN6_OFFSET(x)			((x) << 19)
9249 #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
9250 #define   GEN9_SW_REQ_UNSLICE_RATIO_SHIFT	23
9251 
9252 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
9253 #define GEN6_RC_CONTROL				_MMIO(0xA090)
9254 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
9255 #define   GEN6_RC_CTL_RC6p_ENABLE		(1 << 17)
9256 #define   GEN6_RC_CTL_RC6_ENABLE		(1 << 18)
9257 #define   GEN6_RC_CTL_RC1e_ENABLE		(1 << 20)
9258 #define   GEN6_RC_CTL_RC7_ENABLE		(1 << 22)
9259 #define   VLV_RC_CTL_CTX_RST_PARALLEL		(1 << 24)
9260 #define   GEN7_RC_CTL_TO_MODE			(1 << 28)
9261 #define   GEN6_RC_CTL_EI_MODE(x)		((x) << 27)
9262 #define   GEN6_RC_CTL_HW_ENABLE			(1 << 31)
9263 #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
9264 #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
9265 #define GEN6_RPSTAT1				_MMIO(0xA01C)
9266 #define   GEN6_CAGF_SHIFT			8
9267 #define   HSW_CAGF_SHIFT			7
9268 #define   GEN9_CAGF_SHIFT			23
9269 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
9270 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
9271 #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
9272 #define GEN6_RP_CONTROL				_MMIO(0xA024)
9273 #define   GEN6_RP_MEDIA_TURBO			(1 << 11)
9274 #define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
9275 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3 << 9)
9276 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2 << 9)
9277 #define   GEN6_RP_MEDIA_HW_MODE			(1 << 9)
9278 #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
9279 #define   GEN6_RP_MEDIA_IS_GFX			(1 << 8)
9280 #define   GEN6_RP_ENABLE			(1 << 7)
9281 #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
9282 #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
9283 #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
9284 #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
9285 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
9286 #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
9287 #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
9288 #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
9289 #define   GEN6_RP_EI_MASK			0xffffff
9290 #define   GEN6_CURICONT_MASK			GEN6_RP_EI_MASK
9291 #define GEN6_RP_CUR_UP				_MMIO(0xA054)
9292 #define   GEN6_CURBSYTAVG_MASK			GEN6_RP_EI_MASK
9293 #define GEN6_RP_PREV_UP				_MMIO(0xA058)
9294 #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
9295 #define   GEN6_CURIAVG_MASK			GEN6_RP_EI_MASK
9296 #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
9297 #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
9298 #define GEN6_RP_UP_EI				_MMIO(0xA068)
9299 #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
9300 #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
9301 #define GEN6_RPDEUHWTC				_MMIO(0xA080)
9302 #define GEN6_RPDEUC				_MMIO(0xA084)
9303 #define GEN6_RPDEUCSW				_MMIO(0xA088)
9304 #define GEN6_RC_STATE				_MMIO(0xA094)
9305 #define   RC_SW_TARGET_STATE_SHIFT		16
9306 #define   RC_SW_TARGET_STATE_MASK		(7 << RC_SW_TARGET_STATE_SHIFT)
9307 #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
9308 #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
9309 #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
9310 #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
9311 #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
9312 #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
9313 #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
9314 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
9315 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
9316 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
9317 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
9318 #define VLV_RCEDATA				_MMIO(0xA0BC)
9319 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
9320 #define GEN6_PMINTRMSK				_MMIO(0xA168)
9321 #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC	(1 << 31)
9322 #define   ARAT_EXPIRED_INTRMSK			(1 << 9)
9323 #define GEN8_MISC_CTRL0				_MMIO(0xA180)
9324 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
9325 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
9326 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
9327 #define GEN9_PG_ENABLE				_MMIO(0xA210)
9328 #define   GEN9_RENDER_PG_ENABLE			REG_BIT(0)
9329 #define   GEN9_MEDIA_PG_ENABLE			REG_BIT(1)
9330 #define   GEN11_MEDIA_SAMPLER_PG_ENABLE		REG_BIT(2)
9331 #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
9332 #define   VDN_MFX_POWERGATE_ENABLE(n)		REG_BIT(4 + 2 * (n))
9333 #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
9334 #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
9335 #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
9336 
9337 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
9338 #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
9339 #define  PIXEL_OVERLAP_CNT_SHIFT		30
9340 
9341 #define GEN6_PMISR				_MMIO(0x44020)
9342 #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
9343 #define GEN6_PMIIR				_MMIO(0x44028)
9344 #define GEN6_PMIER				_MMIO(0x4402C)
9345 #define  GEN6_PM_MBOX_EVENT			(1 << 25)
9346 #define  GEN6_PM_THERMAL_EVENT			(1 << 24)
9347 
9348 /*
9349  * For Gen11 these are in the upper word of the GPM_WGBOXPERF
9350  * registers. Shifting is handled on accessing the imr and ier.
9351  */
9352 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1 << 6)
9353 #define  GEN6_PM_RP_UP_THRESHOLD		(1 << 5)
9354 #define  GEN6_PM_RP_DOWN_THRESHOLD		(1 << 4)
9355 #define  GEN6_PM_RP_UP_EI_EXPIRED		(1 << 2)
9356 #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1 << 1)
9357 #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_EI_EXPIRED   | \
9358 						 GEN6_PM_RP_UP_THRESHOLD    | \
9359 						 GEN6_PM_RP_DOWN_EI_EXPIRED | \
9360 						 GEN6_PM_RP_DOWN_THRESHOLD  | \
9361 						 GEN6_PM_RP_DOWN_TIMEOUT)
9362 
9363 #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
9364 #define GEN7_GT_SCRATCH_REG_NUM			8
9365 
9366 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
9367 #define VLV_GFX_CLK_STATUS_BIT			(1 << 3)
9368 #define VLV_GFX_CLK_FORCE_ON_BIT		(1 << 2)
9369 
9370 #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
9371 #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
9372 #define   VLV_COUNT_RANGE_HIGH			(1 << 15)
9373 #define   VLV_MEDIA_RC0_COUNT_EN		(1 << 5)
9374 #define   VLV_RENDER_RC0_COUNT_EN		(1 << 4)
9375 #define   VLV_MEDIA_RC6_COUNT_EN		(1 << 1)
9376 #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
9377 #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
9378 #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
9379 #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
9380 
9381 #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
9382 #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
9383 #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
9384 #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
9385 
9386 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
9387 #define   GEN6_PCODE_READY			(1 << 31)
9388 #define   GEN6_PCODE_ERROR_MASK			0xFF
9389 #define     GEN6_PCODE_SUCCESS			0x0
9390 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
9391 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
9392 #define     GEN6_PCODE_TIMEOUT			0x3
9393 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
9394 #define     GEN7_PCODE_TIMEOUT			0x2
9395 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
9396 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
9397 #define     GEN11_PCODE_LOCKED			0x6
9398 #define     GEN11_PCODE_REJECTED		0x11
9399 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
9400 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
9401 #define   GEN6_PCODE_READ_RC6VIDS		0x5
9402 #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
9403 #define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
9404 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
9405 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
9406 #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
9407 #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
9408 #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
9409 #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
9410 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
9411 #define   SKL_PCODE_CDCLK_CONTROL		0x7
9412 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
9413 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
9414 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
9415 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
9416 #define   GEN6_READ_OC_PARAMS			0xc
9417 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
9418 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
9419 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
9420 #define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
9421 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
9422 #define     ICL_PCODE_POINTS_RESTRICTED		0x0
9423 #define     ICL_PCODE_POINTS_RESTRICTED_MASK	0xf
9424 #define   ADLS_PSF_PT_SHIFT			8
9425 #define   ADLS_QGV_PT_MASK			REG_GENMASK(7, 0)
9426 #define   ADLS_PSF_PT_MASK			REG_GENMASK(10, 8)
9427 #define   GEN6_PCODE_READ_D_COMP		0x10
9428 #define   GEN6_PCODE_WRITE_D_COMP		0x11
9429 #define   ICL_PCODE_EXIT_TCCOLD			0x12
9430 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
9431 #define   DISPLAY_IPS_CONTROL			0x19
9432 #define   TGL_PCODE_TCCOLD			0x26
9433 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
9434 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
9435 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
9436             /* See also IPS_CTL */
9437 #define     IPS_PCODE_CONTROL			(1 << 30)
9438 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
9439 #define   GEN9_PCODE_SAGV_CONTROL		0x21
9440 #define     GEN9_SAGV_DISABLE			0x0
9441 #define     GEN9_SAGV_IS_DISABLED		0x1
9442 #define     GEN9_SAGV_ENABLE			0x3
9443 #define   DG1_PCODE_STATUS			0x7E
9444 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
9445 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
9446 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
9447 #define GEN6_PCODE_DATA				_MMIO(0x138128)
9448 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
9449 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
9450 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
9451 
9452 #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
9453 #define   GEN6_CORE_CPD_STATE_MASK	(7 << 4)
9454 #define   GEN6_RCn_MASK			7
9455 #define   GEN6_RC0			0
9456 #define   GEN6_RC3			2
9457 #define   GEN6_RC6			3
9458 #define   GEN6_RC7			4
9459 
9460 #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
9461 #define   GEN8_LSLICESTAT_MASK		0x7
9462 
9463 #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
9464 #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
9465 #define   CHV_SS_PG_ENABLE		(1 << 1)
9466 #define   CHV_EU08_PG_ENABLE		(1 << 9)
9467 #define   CHV_EU19_PG_ENABLE		(1 << 17)
9468 #define   CHV_EU210_PG_ENABLE		(1 << 25)
9469 
9470 #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
9471 #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
9472 #define   CHV_EU311_PG_ENABLE		(1 << 1)
9473 
9474 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
9475 #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
9476 					      ((slice) % 3) * 0x4)
9477 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
9478 #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
9479 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9480 
9481 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
9482 #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
9483 					      ((slice) % 3) * 0x8)
9484 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
9485 #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9486 					      ((slice) % 3) * 0x8)
9487 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
9488 #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
9489 #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
9490 #define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
9491 #define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
9492 #define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
9493 #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
9494 #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
9495 
9496 #define GEN7_MISCCPCTL				_MMIO(0x9424)
9497 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
9498 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)
9499 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
9500 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
9501 
9502 #define GEN8_GARBCNTL				_MMIO(0xB004)
9503 #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
9504 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
9505 #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
9506 #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
9507 
9508 #define GEN11_GLBLINVL				_MMIO(0xB404)
9509 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
9510 #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
9511 
9512 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
9513 #define   DFR_DISABLE			(1 << 9)
9514 
9515 #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
9516 #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
9517 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
9518 #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
9519 
9520 #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
9521 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC	(1 << 9)
9522 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
9523 
9524 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
9525 #define   ENABLE_SMALLPL			REG_BIT(15)
9526 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
9527 
9528 /* IVYBRIDGE DPF */
9529 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
9530 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
9531 #define   GEN7_PARITY_ERROR_VALID	(1 << 13)
9532 #define   GEN7_L3CDERRST1_BANK_MASK	(3 << 11)
9533 #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7 << 8)
9534 #define GEN7_PARITY_ERROR_ROW(reg) \
9535 		(((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
9536 #define GEN7_PARITY_ERROR_BANK(reg) \
9537 		(((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
9538 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
9539 		(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
9540 #define   GEN7_L3CDERRST1_ENABLE	(1 << 7)
9541 
9542 #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9543 #define GEN7_L3LOG_SIZE			0x80
9544 
9545 #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
9546 #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
9547 #define   GEN7_MAX_PS_THREAD_DEP		(8 << 12)
9548 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1 << 10)
9549 #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1 << 4)
9550 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1 << 3)
9551 
9552 #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
9553 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
9554 #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
9555 
9556 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
9557 #define   FLOW_CONTROL_ENABLE		(1 << 15)
9558 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
9559 #define   STALL_DOP_GATING_DISABLE		(1 << 5)
9560 #define   THROTTLE_12_5				(7 << 2)
9561 #define   DISABLE_EARLY_EOT			(1 << 1)
9562 
9563 #define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)
9564 #define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)
9565 #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)
9566 
9567 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
9568 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
9569 #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
9570 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
9571 
9572 #define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)
9573 #define   GEN12_DISABLE_TDL_PUSH	REG_BIT(9)
9574 #define   GEN11_DIS_PICK_2ND_EU		REG_BIT(7)
9575 
9576 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
9577 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
9578 
9579 #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
9580 #define   GEN8_ST_PO_DISABLE		(1 << 13)
9581 
9582 #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
9583 #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
9584 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
9585 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
9586 #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
9587 
9588 #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
9589 #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR	(1 << 8)
9590 #define   GEN9_ENABLE_YV12_BUGFIX	(1 << 4)
9591 #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1 << 2)
9592 
9593 /* Audio */
9594 #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9595 #define   INTEL_AUDIO_DEVCL		0x808629FB
9596 #define   INTEL_AUDIO_DEVBLC		0x80862801
9597 #define   INTEL_AUDIO_DEVCTG		0x80862802
9598 
9599 #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
9600 #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
9601 #define   G4X_ELDV_DEVCTG		(1 << 14)
9602 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
9603 #define   G4X_ELD_ACK			(1 << 4)
9604 #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
9605 
9606 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
9607 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
9608 #define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9609 						  _IBX_HDMIW_HDMIEDID_B)
9610 #define _IBX_AUD_CNTL_ST_A		0xE20B4
9611 #define _IBX_AUD_CNTL_ST_B		0xE21B4
9612 #define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9613 						  _IBX_AUD_CNTL_ST_B)
9614 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
9615 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
9616 #define   IBX_ELD_ACK			(1 << 4)
9617 #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
9618 #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
9619 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
9620 
9621 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
9622 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
9623 #define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9624 #define _CPT_AUD_CNTL_ST_A		0xE50B4
9625 #define _CPT_AUD_CNTL_ST_B		0xE51B4
9626 #define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9627 #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
9628 
9629 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
9630 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
9631 #define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9632 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
9633 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
9634 #define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9635 #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
9636 
9637 /* These are the 4 32-bit write offset registers for each stream
9638  * output buffer.  It determines the offset from the
9639  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9640  */
9641 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
9642 
9643 #define _IBX_AUD_CONFIG_A		0xe2000
9644 #define _IBX_AUD_CONFIG_B		0xe2100
9645 #define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9646 #define _CPT_AUD_CONFIG_A		0xe5000
9647 #define _CPT_AUD_CONFIG_B		0xe5100
9648 #define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9649 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
9650 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
9651 #define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9652 
9653 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
9654 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
9655 #define   AUD_CONFIG_UPPER_N_SHIFT		20
9656 #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
9657 #define   AUD_CONFIG_LOWER_N_SHIFT		4
9658 #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
9659 #define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9660 #define   AUD_CONFIG_N(n) \
9661 	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
9662 	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9663 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
9664 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
9665 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
9666 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
9667 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
9668 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
9669 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
9670 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
9671 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
9672 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
9673 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
9674 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
9675 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)
9676 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)
9677 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)
9678 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)
9679 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
9680 
9681 /* HSW Audio */
9682 #define _HSW_AUD_CONFIG_A		0x65000
9683 #define _HSW_AUD_CONFIG_B		0x65100
9684 #define HSW_AUD_CFG(trans)		_MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9685 
9686 #define _HSW_AUD_MISC_CTRL_A		0x65010
9687 #define _HSW_AUD_MISC_CTRL_B		0x65110
9688 #define HSW_AUD_MISC_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9689 
9690 #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
9691 #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
9692 #define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9693 #define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
9694 #define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
9695 #define   AUD_CONFIG_M_MASK		0xfffff
9696 
9697 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
9698 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
9699 #define HSW_AUD_DIP_ELD_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9700 
9701 /* Audio Digital Converter */
9702 #define _HSW_AUD_DIG_CNVT_1		0x65080
9703 #define _HSW_AUD_DIG_CNVT_2		0x65180
9704 #define AUD_DIG_CNVT(trans)		_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9705 #define DIP_PORT_SEL_MASK		0x3
9706 
9707 #define _HSW_AUD_EDID_DATA_A		0x65050
9708 #define _HSW_AUD_EDID_DATA_B		0x65150
9709 #define HSW_AUD_EDID_DATA(trans)	_MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9710 
9711 #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
9712 #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
9713 #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
9714 #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
9715 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
9716 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
9717 
9718 #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
9719 #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
9720 
9721 #define AUD_FREQ_CNTRL			_MMIO(0x65900)
9722 #define AUD_PIN_BUF_CTL		_MMIO(0x48414)
9723 #define   AUD_PIN_BUF_ENABLE		REG_BIT(31)
9724 
9725 /* Display Audio Config Reg */
9726 #define AUD_CONFIG_BE			_MMIO(0x65ef0)
9727 #define HBLANK_EARLY_ENABLE_ICL(pipe)		(0x1 << (20 - (pipe)))
9728 #define HBLANK_EARLY_ENABLE_TGL(pipe)		(0x1 << (24 + (pipe)))
9729 #define HBLANK_START_COUNT_MASK(pipe)		(0x7 << (3 + ((pipe) * 6)))
9730 #define HBLANK_START_COUNT(pipe, val)		(((val) & 0x7) << (3 + ((pipe)) * 6))
9731 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe)	(0x3 << ((pipe) * 6))
9732 #define NUMBER_SAMPLES_PER_LINE(pipe, val)	(((val) & 0x3) << ((pipe) * 6))
9733 
9734 #define HBLANK_START_COUNT_8	0
9735 #define HBLANK_START_COUNT_16	1
9736 #define HBLANK_START_COUNT_32	2
9737 #define HBLANK_START_COUNT_64	3
9738 #define HBLANK_START_COUNT_96	4
9739 #define HBLANK_START_COUNT_128	5
9740 
9741 /*
9742  * HSW - ICL power wells
9743  *
9744  * Platforms have up to 3 power well control register sets, each set
9745  * controlling up to 16 power wells via a request/status HW flag tuple:
9746  * - main (HSW_PWR_WELL_CTL[1-4])
9747  * - AUX  (ICL_PWR_WELL_CTL_AUX[1-4])
9748  * - DDI  (ICL_PWR_WELL_CTL_DDI[1-4])
9749  * Each control register set consists of up to 4 registers used by different
9750  * sources that can request a power well to be enabled:
9751  * - BIOS   (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9752  * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9753  * - KVMR   (HSW_PWR_WELL_CTL3)   (only in the main register set)
9754  * - DEBUG  (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9755  */
9756 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
9757 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
9758 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
9759 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
9760 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
9761 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
9762 
9763 /* HSW/BDW power well */
9764 #define   HSW_PW_CTL_IDX_GLOBAL			15
9765 
9766 /* SKL/BXT/GLK power wells */
9767 #define   SKL_PW_CTL_IDX_PW_2			15
9768 #define   SKL_PW_CTL_IDX_PW_1			14
9769 #define   GLK_PW_CTL_IDX_AUX_C			10
9770 #define   GLK_PW_CTL_IDX_AUX_B			9
9771 #define   GLK_PW_CTL_IDX_AUX_A			8
9772 #define   SKL_PW_CTL_IDX_DDI_D			4
9773 #define   SKL_PW_CTL_IDX_DDI_C			3
9774 #define   SKL_PW_CTL_IDX_DDI_B			2
9775 #define   SKL_PW_CTL_IDX_DDI_A_E		1
9776 #define   GLK_PW_CTL_IDX_DDI_A			1
9777 #define   SKL_PW_CTL_IDX_MISC_IO		0
9778 
9779 /* ICL/TGL - power wells */
9780 #define   TGL_PW_CTL_IDX_PW_5			4
9781 #define   ICL_PW_CTL_IDX_PW_4			3
9782 #define   ICL_PW_CTL_IDX_PW_3			2
9783 #define   ICL_PW_CTL_IDX_PW_2			1
9784 #define   ICL_PW_CTL_IDX_PW_1			0
9785 
9786 /* XE_LPD - power wells */
9787 #define   XELPD_PW_CTL_IDX_PW_D			8
9788 #define   XELPD_PW_CTL_IDX_PW_C			7
9789 #define   XELPD_PW_CTL_IDX_PW_B			6
9790 #define   XELPD_PW_CTL_IDX_PW_A			5
9791 
9792 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
9793 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
9794 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
9795 #define   TGL_PW_CTL_IDX_AUX_TBT6		14
9796 #define   TGL_PW_CTL_IDX_AUX_TBT5		13
9797 #define   TGL_PW_CTL_IDX_AUX_TBT4		12
9798 #define   ICL_PW_CTL_IDX_AUX_TBT4		11
9799 #define   TGL_PW_CTL_IDX_AUX_TBT3		11
9800 #define   ICL_PW_CTL_IDX_AUX_TBT3		10
9801 #define   TGL_PW_CTL_IDX_AUX_TBT2		10
9802 #define   ICL_PW_CTL_IDX_AUX_TBT2		9
9803 #define   TGL_PW_CTL_IDX_AUX_TBT1		9
9804 #define   ICL_PW_CTL_IDX_AUX_TBT1		8
9805 #define   TGL_PW_CTL_IDX_AUX_TC6		8
9806 #define   XELPD_PW_CTL_IDX_AUX_E			8
9807 #define   TGL_PW_CTL_IDX_AUX_TC5		7
9808 #define   XELPD_PW_CTL_IDX_AUX_D			7
9809 #define   TGL_PW_CTL_IDX_AUX_TC4		6
9810 #define   ICL_PW_CTL_IDX_AUX_F			5
9811 #define   TGL_PW_CTL_IDX_AUX_TC3		5
9812 #define   ICL_PW_CTL_IDX_AUX_E			4
9813 #define   TGL_PW_CTL_IDX_AUX_TC2		4
9814 #define   ICL_PW_CTL_IDX_AUX_D			3
9815 #define   TGL_PW_CTL_IDX_AUX_TC1		3
9816 #define   ICL_PW_CTL_IDX_AUX_C			2
9817 #define   ICL_PW_CTL_IDX_AUX_B			1
9818 #define   ICL_PW_CTL_IDX_AUX_A			0
9819 
9820 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
9821 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
9822 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
9823 #define   XELPD_PW_CTL_IDX_DDI_E			8
9824 #define   TGL_PW_CTL_IDX_DDI_TC6		8
9825 #define   XELPD_PW_CTL_IDX_DDI_D			7
9826 #define   TGL_PW_CTL_IDX_DDI_TC5		7
9827 #define   TGL_PW_CTL_IDX_DDI_TC4		6
9828 #define   ICL_PW_CTL_IDX_DDI_F			5
9829 #define   TGL_PW_CTL_IDX_DDI_TC3		5
9830 #define   ICL_PW_CTL_IDX_DDI_E			4
9831 #define   TGL_PW_CTL_IDX_DDI_TC2		4
9832 #define   ICL_PW_CTL_IDX_DDI_D			3
9833 #define   TGL_PW_CTL_IDX_DDI_TC1		3
9834 #define   ICL_PW_CTL_IDX_DDI_C			2
9835 #define   ICL_PW_CTL_IDX_DDI_B			1
9836 #define   ICL_PW_CTL_IDX_DDI_A			0
9837 
9838 /* HSW - power well misc debug registers */
9839 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
9840 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1 << 31)
9841 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1 << 20)
9842 #define   HSW_PWR_WELL_FORCE_ON			(1 << 19)
9843 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
9844 
9845 /* SKL Fuse Status */
9846 enum skl_power_gate {
9847 	SKL_PG0,
9848 	SKL_PG1,
9849 	SKL_PG2,
9850 	ICL_PG3,
9851 	ICL_PG4,
9852 };
9853 
9854 #define SKL_FUSE_STATUS				_MMIO(0x42000)
9855 #define  SKL_FUSE_DOWNLOAD_STATUS		(1 << 31)
9856 /*
9857  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9858  * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9859  */
9860 #define  SKL_PW_CTL_IDX_TO_PG(pw_idx)		\
9861 	((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9862 /*
9863  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9864  * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9865  */
9866 #define  ICL_PW_CTL_IDX_TO_PG(pw_idx)		\
9867 	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9868 #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
9869 
9870 #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9871 #define _ICL_AUX_ANAOVRD1_A		0x162398
9872 #define _ICL_AUX_ANAOVRD1_B		0x6C398
9873 #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9874 						    _ICL_AUX_ANAOVRD1_A, \
9875 						    _ICL_AUX_ANAOVRD1_B))
9876 #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
9877 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
9878 
9879 /* HDCP Key Registers */
9880 #define HDCP_KEY_CONF			_MMIO(0x66c00)
9881 #define  HDCP_AKSV_SEND_TRIGGER		BIT(31)
9882 #define  HDCP_CLEAR_KEYS_TRIGGER	BIT(30)
9883 #define  HDCP_KEY_LOAD_TRIGGER		BIT(8)
9884 #define HDCP_KEY_STATUS			_MMIO(0x66c04)
9885 #define  HDCP_FUSE_IN_PROGRESS		BIT(7)
9886 #define  HDCP_FUSE_ERROR		BIT(6)
9887 #define  HDCP_FUSE_DONE			BIT(5)
9888 #define  HDCP_KEY_LOAD_STATUS		BIT(1)
9889 #define  HDCP_KEY_LOAD_DONE		BIT(0)
9890 #define HDCP_AKSV_LO			_MMIO(0x66c10)
9891 #define HDCP_AKSV_HI			_MMIO(0x66c14)
9892 
9893 /* HDCP Repeater Registers */
9894 #define HDCP_REP_CTL			_MMIO(0x66d00)
9895 #define  HDCP_TRANSA_REP_PRESENT	BIT(31)
9896 #define  HDCP_TRANSB_REP_PRESENT	BIT(30)
9897 #define  HDCP_TRANSC_REP_PRESENT	BIT(29)
9898 #define  HDCP_TRANSD_REP_PRESENT	BIT(28)
9899 #define  HDCP_DDIB_REP_PRESENT		BIT(30)
9900 #define  HDCP_DDIA_REP_PRESENT		BIT(29)
9901 #define  HDCP_DDIC_REP_PRESENT		BIT(28)
9902 #define  HDCP_DDID_REP_PRESENT		BIT(27)
9903 #define  HDCP_DDIF_REP_PRESENT		BIT(26)
9904 #define  HDCP_DDIE_REP_PRESENT		BIT(25)
9905 #define  HDCP_TRANSA_SHA1_M0		(1 << 20)
9906 #define  HDCP_TRANSB_SHA1_M0		(2 << 20)
9907 #define  HDCP_TRANSC_SHA1_M0		(3 << 20)
9908 #define  HDCP_TRANSD_SHA1_M0		(4 << 20)
9909 #define  HDCP_DDIB_SHA1_M0		(1 << 20)
9910 #define  HDCP_DDIA_SHA1_M0		(2 << 20)
9911 #define  HDCP_DDIC_SHA1_M0		(3 << 20)
9912 #define  HDCP_DDID_SHA1_M0		(4 << 20)
9913 #define  HDCP_DDIF_SHA1_M0		(5 << 20)
9914 #define  HDCP_DDIE_SHA1_M0		(6 << 20) /* Bspec says 5? */
9915 #define  HDCP_SHA1_BUSY			BIT(16)
9916 #define  HDCP_SHA1_READY		BIT(17)
9917 #define  HDCP_SHA1_COMPLETE		BIT(18)
9918 #define  HDCP_SHA1_V_MATCH		BIT(19)
9919 #define  HDCP_SHA1_TEXT_32		(1 << 1)
9920 #define  HDCP_SHA1_COMPLETE_HASH	(2 << 1)
9921 #define  HDCP_SHA1_TEXT_24		(4 << 1)
9922 #define  HDCP_SHA1_TEXT_16		(5 << 1)
9923 #define  HDCP_SHA1_TEXT_8		(6 << 1)
9924 #define  HDCP_SHA1_TEXT_0		(7 << 1)
9925 #define HDCP_SHA_V_PRIME_H0		_MMIO(0x66d04)
9926 #define HDCP_SHA_V_PRIME_H1		_MMIO(0x66d08)
9927 #define HDCP_SHA_V_PRIME_H2		_MMIO(0x66d0C)
9928 #define HDCP_SHA_V_PRIME_H3		_MMIO(0x66d10)
9929 #define HDCP_SHA_V_PRIME_H4		_MMIO(0x66d14)
9930 #define HDCP_SHA_V_PRIME(h)		_MMIO((0x66d04 + (h) * 4))
9931 #define HDCP_SHA_TEXT			_MMIO(0x66d18)
9932 
9933 /* HDCP Auth Registers */
9934 #define _PORTA_HDCP_AUTHENC		0x66800
9935 #define _PORTB_HDCP_AUTHENC		0x66500
9936 #define _PORTC_HDCP_AUTHENC		0x66600
9937 #define _PORTD_HDCP_AUTHENC		0x66700
9938 #define _PORTE_HDCP_AUTHENC		0x66A00
9939 #define _PORTF_HDCP_AUTHENC		0x66900
9940 #define _PORT_HDCP_AUTHENC(port, x)	_MMIO(_PICK(port, \
9941 					  _PORTA_HDCP_AUTHENC, \
9942 					  _PORTB_HDCP_AUTHENC, \
9943 					  _PORTC_HDCP_AUTHENC, \
9944 					  _PORTD_HDCP_AUTHENC, \
9945 					  _PORTE_HDCP_AUTHENC, \
9946 					  _PORTF_HDCP_AUTHENC) + (x))
9947 #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
9948 #define _TRANSA_HDCP_CONF		0x66400
9949 #define _TRANSB_HDCP_CONF		0x66500
9950 #define TRANS_HDCP_CONF(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
9951 						    _TRANSB_HDCP_CONF)
9952 #define HDCP_CONF(dev_priv, trans, port) \
9953 					(GRAPHICS_VER(dev_priv) >= 12 ? \
9954 					 TRANS_HDCP_CONF(trans) : \
9955 					 PORT_HDCP_CONF(port))
9956 
9957 #define  HDCP_CONF_CAPTURE_AN		BIT(0)
9958 #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
9959 #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
9960 #define _TRANSA_HDCP_ANINIT		0x66404
9961 #define _TRANSB_HDCP_ANINIT		0x66504
9962 #define TRANS_HDCP_ANINIT(trans)	_MMIO_TRANS(trans, \
9963 						    _TRANSA_HDCP_ANINIT, \
9964 						    _TRANSB_HDCP_ANINIT)
9965 #define HDCP_ANINIT(dev_priv, trans, port) \
9966 					(GRAPHICS_VER(dev_priv) >= 12 ? \
9967 					 TRANS_HDCP_ANINIT(trans) : \
9968 					 PORT_HDCP_ANINIT(port))
9969 
9970 #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
9971 #define _TRANSA_HDCP_ANLO		0x66408
9972 #define _TRANSB_HDCP_ANLO		0x66508
9973 #define TRANS_HDCP_ANLO(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
9974 						    _TRANSB_HDCP_ANLO)
9975 #define HDCP_ANLO(dev_priv, trans, port) \
9976 					(GRAPHICS_VER(dev_priv) >= 12 ? \
9977 					 TRANS_HDCP_ANLO(trans) : \
9978 					 PORT_HDCP_ANLO(port))
9979 
9980 #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
9981 #define _TRANSA_HDCP_ANHI		0x6640C
9982 #define _TRANSB_HDCP_ANHI		0x6650C
9983 #define TRANS_HDCP_ANHI(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
9984 						    _TRANSB_HDCP_ANHI)
9985 #define HDCP_ANHI(dev_priv, trans, port) \
9986 					(GRAPHICS_VER(dev_priv) >= 12 ? \
9987 					 TRANS_HDCP_ANHI(trans) : \
9988 					 PORT_HDCP_ANHI(port))
9989 
9990 #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
9991 #define _TRANSA_HDCP_BKSVLO		0x66410
9992 #define _TRANSB_HDCP_BKSVLO		0x66510
9993 #define TRANS_HDCP_BKSVLO(trans)	_MMIO_TRANS(trans, \
9994 						    _TRANSA_HDCP_BKSVLO, \
9995 						    _TRANSB_HDCP_BKSVLO)
9996 #define HDCP_BKSVLO(dev_priv, trans, port) \
9997 					(GRAPHICS_VER(dev_priv) >= 12 ? \
9998 					 TRANS_HDCP_BKSVLO(trans) : \
9999 					 PORT_HDCP_BKSVLO(port))
10000 
10001 #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
10002 #define _TRANSA_HDCP_BKSVHI		0x66414
10003 #define _TRANSB_HDCP_BKSVHI		0x66514
10004 #define TRANS_HDCP_BKSVHI(trans)	_MMIO_TRANS(trans, \
10005 						    _TRANSA_HDCP_BKSVHI, \
10006 						    _TRANSB_HDCP_BKSVHI)
10007 #define HDCP_BKSVHI(dev_priv, trans, port) \
10008 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10009 					 TRANS_HDCP_BKSVHI(trans) : \
10010 					 PORT_HDCP_BKSVHI(port))
10011 
10012 #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
10013 #define _TRANSA_HDCP_RPRIME		0x66418
10014 #define _TRANSB_HDCP_RPRIME		0x66518
10015 #define TRANS_HDCP_RPRIME(trans)	_MMIO_TRANS(trans, \
10016 						    _TRANSA_HDCP_RPRIME, \
10017 						    _TRANSB_HDCP_RPRIME)
10018 #define HDCP_RPRIME(dev_priv, trans, port) \
10019 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10020 					 TRANS_HDCP_RPRIME(trans) : \
10021 					 PORT_HDCP_RPRIME(port))
10022 
10023 #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
10024 #define _TRANSA_HDCP_STATUS		0x6641C
10025 #define _TRANSB_HDCP_STATUS		0x6651C
10026 #define TRANS_HDCP_STATUS(trans)	_MMIO_TRANS(trans, \
10027 						    _TRANSA_HDCP_STATUS, \
10028 						    _TRANSB_HDCP_STATUS)
10029 #define HDCP_STATUS(dev_priv, trans, port) \
10030 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10031 					 TRANS_HDCP_STATUS(trans) : \
10032 					 PORT_HDCP_STATUS(port))
10033 
10034 #define  HDCP_STATUS_STREAM_A_ENC	BIT(31)
10035 #define  HDCP_STATUS_STREAM_B_ENC	BIT(30)
10036 #define  HDCP_STATUS_STREAM_C_ENC	BIT(29)
10037 #define  HDCP_STATUS_STREAM_D_ENC	BIT(28)
10038 #define  HDCP_STATUS_AUTH		BIT(21)
10039 #define  HDCP_STATUS_ENC		BIT(20)
10040 #define  HDCP_STATUS_RI_MATCH		BIT(19)
10041 #define  HDCP_STATUS_R0_READY		BIT(18)
10042 #define  HDCP_STATUS_AN_READY		BIT(17)
10043 #define  HDCP_STATUS_CIPHER		BIT(16)
10044 #define  HDCP_STATUS_FRAME_CNT(x)	(((x) >> 8) & 0xff)
10045 
10046 /* HDCP2.2 Registers */
10047 #define _PORTA_HDCP2_BASE		0x66800
10048 #define _PORTB_HDCP2_BASE		0x66500
10049 #define _PORTC_HDCP2_BASE		0x66600
10050 #define _PORTD_HDCP2_BASE		0x66700
10051 #define _PORTE_HDCP2_BASE		0x66A00
10052 #define _PORTF_HDCP2_BASE		0x66900
10053 #define _PORT_HDCP2_BASE(port, x)	_MMIO(_PICK((port), \
10054 					  _PORTA_HDCP2_BASE, \
10055 					  _PORTB_HDCP2_BASE, \
10056 					  _PORTC_HDCP2_BASE, \
10057 					  _PORTD_HDCP2_BASE, \
10058 					  _PORTE_HDCP2_BASE, \
10059 					  _PORTF_HDCP2_BASE) + (x))
10060 
10061 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
10062 #define _TRANSA_HDCP2_AUTH		0x66498
10063 #define _TRANSB_HDCP2_AUTH		0x66598
10064 #define TRANS_HDCP2_AUTH(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
10065 						    _TRANSB_HDCP2_AUTH)
10066 #define   AUTH_LINK_AUTHENTICATED	BIT(31)
10067 #define   AUTH_LINK_TYPE		BIT(30)
10068 #define   AUTH_FORCE_CLR_INPUTCTR	BIT(19)
10069 #define   AUTH_CLR_KEYS			BIT(18)
10070 #define HDCP2_AUTH(dev_priv, trans, port) \
10071 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10072 					 TRANS_HDCP2_AUTH(trans) : \
10073 					 PORT_HDCP2_AUTH(port))
10074 
10075 #define PORT_HDCP2_CTL(port)		_PORT_HDCP2_BASE(port, 0xB0)
10076 #define _TRANSA_HDCP2_CTL		0x664B0
10077 #define _TRANSB_HDCP2_CTL		0x665B0
10078 #define TRANS_HDCP2_CTL(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
10079 						    _TRANSB_HDCP2_CTL)
10080 #define   CTL_LINK_ENCRYPTION_REQ	BIT(31)
10081 #define HDCP2_CTL(dev_priv, trans, port) \
10082 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10083 					 TRANS_HDCP2_CTL(trans) : \
10084 					 PORT_HDCP2_CTL(port))
10085 
10086 #define PORT_HDCP2_STATUS(port)		_PORT_HDCP2_BASE(port, 0xB4)
10087 #define _TRANSA_HDCP2_STATUS		0x664B4
10088 #define _TRANSB_HDCP2_STATUS		0x665B4
10089 #define TRANS_HDCP2_STATUS(trans)	_MMIO_TRANS(trans, \
10090 						    _TRANSA_HDCP2_STATUS, \
10091 						    _TRANSB_HDCP2_STATUS)
10092 #define   LINK_TYPE_STATUS		BIT(22)
10093 #define   LINK_AUTH_STATUS		BIT(21)
10094 #define   LINK_ENCRYPTION_STATUS	BIT(20)
10095 #define HDCP2_STATUS(dev_priv, trans, port) \
10096 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10097 					 TRANS_HDCP2_STATUS(trans) : \
10098 					 PORT_HDCP2_STATUS(port))
10099 
10100 #define _PIPEA_HDCP2_STREAM_STATUS	0x668C0
10101 #define _PIPEB_HDCP2_STREAM_STATUS	0x665C0
10102 #define _PIPEC_HDCP2_STREAM_STATUS	0x666C0
10103 #define _PIPED_HDCP2_STREAM_STATUS	0x667C0
10104 #define PIPE_HDCP2_STREAM_STATUS(pipe)		_MMIO(_PICK((pipe), \
10105 						      _PIPEA_HDCP2_STREAM_STATUS, \
10106 						      _PIPEB_HDCP2_STREAM_STATUS, \
10107 						      _PIPEC_HDCP2_STREAM_STATUS, \
10108 						      _PIPED_HDCP2_STREAM_STATUS))
10109 
10110 #define _TRANSA_HDCP2_STREAM_STATUS		0x664C0
10111 #define _TRANSB_HDCP2_STREAM_STATUS		0x665C0
10112 #define TRANS_HDCP2_STREAM_STATUS(trans)	_MMIO_TRANS(trans, \
10113 						    _TRANSA_HDCP2_STREAM_STATUS, \
10114 						    _TRANSB_HDCP2_STREAM_STATUS)
10115 #define   STREAM_ENCRYPTION_STATUS	BIT(31)
10116 #define   STREAM_TYPE_STATUS		BIT(30)
10117 #define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
10118 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10119 					 TRANS_HDCP2_STREAM_STATUS(trans) : \
10120 					 PIPE_HDCP2_STREAM_STATUS(pipe))
10121 
10122 #define _PORTA_HDCP2_AUTH_STREAM		0x66F00
10123 #define _PORTB_HDCP2_AUTH_STREAM		0x66F04
10124 #define PORT_HDCP2_AUTH_STREAM(port)	_MMIO_PORT(port, \
10125 						   _PORTA_HDCP2_AUTH_STREAM, \
10126 						   _PORTB_HDCP2_AUTH_STREAM)
10127 #define _TRANSA_HDCP2_AUTH_STREAM		0x66F00
10128 #define _TRANSB_HDCP2_AUTH_STREAM		0x66F04
10129 #define TRANS_HDCP2_AUTH_STREAM(trans)	_MMIO_TRANS(trans, \
10130 						    _TRANSA_HDCP2_AUTH_STREAM, \
10131 						    _TRANSB_HDCP2_AUTH_STREAM)
10132 #define   AUTH_STREAM_TYPE		BIT(31)
10133 #define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
10134 					(GRAPHICS_VER(dev_priv) >= 12 ? \
10135 					 TRANS_HDCP2_AUTH_STREAM(trans) : \
10136 					 PORT_HDCP2_AUTH_STREAM(port))
10137 
10138 /* Per-pipe DDI Function Control */
10139 #define _TRANS_DDI_FUNC_CTL_A		0x60400
10140 #define _TRANS_DDI_FUNC_CTL_B		0x61400
10141 #define _TRANS_DDI_FUNC_CTL_C		0x62400
10142 #define _TRANS_DDI_FUNC_CTL_D		0x63400
10143 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
10144 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
10145 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
10146 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
10147 
10148 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
10149 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
10150 #define  TRANS_DDI_PORT_SHIFT		28
10151 #define  TGL_TRANS_DDI_PORT_SHIFT	27
10152 #define  TRANS_DDI_PORT_MASK		(7 << TRANS_DDI_PORT_SHIFT)
10153 #define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
10154 #define  TRANS_DDI_SELECT_PORT(x)	((x) << TRANS_DDI_PORT_SHIFT)
10155 #define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
10156 #define  TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)	 (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
10157 #define  TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
10158 #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
10159 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
10160 #define  TRANS_DDI_MODE_SELECT_DVI	(1 << 24)
10161 #define  TRANS_DDI_MODE_SELECT_DP_SST	(2 << 24)
10162 #define  TRANS_DDI_MODE_SELECT_DP_MST	(3 << 24)
10163 #define  TRANS_DDI_MODE_SELECT_FDI	(4 << 24)
10164 #define  TRANS_DDI_BPC_MASK		(7 << 20)
10165 #define  TRANS_DDI_BPC_8		(0 << 20)
10166 #define  TRANS_DDI_BPC_10		(1 << 20)
10167 #define  TRANS_DDI_BPC_6		(2 << 20)
10168 #define  TRANS_DDI_BPC_12		(3 << 20)
10169 #define  TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK	REG_GENMASK(19, 18)
10170 #define  TRANS_DDI_PORT_SYNC_MASTER_SELECT(x)	REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
10171 #define  TRANS_DDI_PVSYNC		(1 << 17)
10172 #define  TRANS_DDI_PHSYNC		(1 << 16)
10173 #define  TRANS_DDI_PORT_SYNC_ENABLE	REG_BIT(15)
10174 #define  TRANS_DDI_EDP_INPUT_MASK	(7 << 12)
10175 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
10176 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
10177 #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
10178 #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
10179 #define  TRANS_DDI_EDP_INPUT_D_ONOFF	(7 << 12)
10180 #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK	REG_GENMASK(11, 10)
10181 #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans)	\
10182 	REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
10183 #define  TRANS_DDI_HDCP_SIGNALLING	(1 << 9)
10184 #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1 << 8)
10185 #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
10186 #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
10187 #define  TRANS_DDI_HDCP_SELECT		REG_BIT(5)
10188 #define  TRANS_DDI_BFI_ENABLE		(1 << 4)
10189 #define  TRANS_DDI_HIGH_TMDS_CHAR_RATE	(1 << 4)
10190 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
10191 #define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
10192 					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
10193 					| TRANS_DDI_HDMI_SCRAMBLING)
10194 
10195 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
10196 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
10197 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
10198 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
10199 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
10200 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
10201 #define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
10202 #define  PORT_SYNC_MODE_ENABLE			REG_BIT(4)
10203 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
10204 #define  PORT_SYNC_MODE_MASTER_SELECT(x)	REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
10205 
10206 #define TRANS_CMTG_CHICKEN		_MMIO(0x6fa90)
10207 #define  DISABLE_DPT_CLK_GATING		REG_BIT(1)
10208 
10209 /* DisplayPort Transport Control */
10210 #define _DP_TP_CTL_A			0x64040
10211 #define _DP_TP_CTL_B			0x64140
10212 #define _TGL_DP_TP_CTL_A		0x60540
10213 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
10214 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
10215 #define  DP_TP_CTL_ENABLE			(1 << 31)
10216 #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
10217 #define  DP_TP_CTL_MODE_SST			(0 << 27)
10218 #define  DP_TP_CTL_MODE_MST			(1 << 27)
10219 #define  DP_TP_CTL_FORCE_ACT			(1 << 25)
10220 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1 << 18)
10221 #define  DP_TP_CTL_FDI_AUTOTRAIN		(1 << 15)
10222 #define  DP_TP_CTL_LINK_TRAIN_MASK		(7 << 8)
10223 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
10224 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1 << 8)
10225 #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4 << 8)
10226 #define  DP_TP_CTL_LINK_TRAIN_PAT4		(5 << 8)
10227 #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2 << 8)
10228 #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3 << 8)
10229 #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1 << 7)
10230 
10231 /* DisplayPort Transport Status */
10232 #define _DP_TP_STATUS_A			0x64044
10233 #define _DP_TP_STATUS_B			0x64144
10234 #define _TGL_DP_TP_STATUS_A		0x60544
10235 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
10236 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
10237 #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
10238 #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
10239 #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
10240 #define  DP_TP_STATUS_MODE_STATUS_MST		(1 << 23)
10241 #define  DP_TP_STATUS_AUTOTRAIN_DONE		(1 << 12)
10242 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2	(3 << 8)
10243 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1	(3 << 4)
10244 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
10245 
10246 /* DDI Buffer Control */
10247 #define _DDI_BUF_CTL_A				0x64000
10248 #define _DDI_BUF_CTL_B				0x64100
10249 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
10250 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
10251 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
10252 #define  DDI_BUF_EMP_MASK			(0xf << 24)
10253 #define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
10254 #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
10255 #define  DDI_BUF_IS_IDLE			(1 << 7)
10256 #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
10257 #define  DDI_A_4_LANES				(1 << 4)
10258 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
10259 #define  DDI_PORT_WIDTH_MASK			(7 << 1)
10260 #define  DDI_PORT_WIDTH_SHIFT			1
10261 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
10262 
10263 /* DDI Buffer Translations */
10264 #define _DDI_BUF_TRANS_A		0x64E00
10265 #define _DDI_BUF_TRANS_B		0x64E60
10266 #define DDI_BUF_TRANS_LO(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
10267 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
10268 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
10269 
10270 /* DDI DP Compliance Control */
10271 #define _DDI_DP_COMP_CTL_A			0x605F0
10272 #define _DDI_DP_COMP_CTL_B			0x615F0
10273 #define DDI_DP_COMP_CTL(pipe)			_MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
10274 #define   DDI_DP_COMP_CTL_ENABLE		(1 << 31)
10275 #define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
10276 #define   DDI_DP_COMP_CTL_SCRAMBLED_0		(1 << 28)
10277 #define   DDI_DP_COMP_CTL_PRBS7			(2 << 28)
10278 #define   DDI_DP_COMP_CTL_CUSTOM80		(3 << 28)
10279 #define   DDI_DP_COMP_CTL_HBR2			(4 << 28)
10280 #define   DDI_DP_COMP_CTL_SCRAMBLED_1		(5 << 28)
10281 #define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
10282 
10283 /* DDI DP Compliance Pattern */
10284 #define _DDI_DP_COMP_PAT_A			0x605F4
10285 #define _DDI_DP_COMP_PAT_B			0x615F4
10286 #define DDI_DP_COMP_PAT(pipe, i)		_MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
10287 
10288 /* Sideband Interface (SBI) is programmed indirectly, via
10289  * SBI_ADDR, which contains the register offset; and SBI_DATA,
10290  * which contains the payload */
10291 #define SBI_ADDR			_MMIO(0xC6000)
10292 #define SBI_DATA			_MMIO(0xC6004)
10293 #define SBI_CTL_STAT			_MMIO(0xC6008)
10294 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
10295 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
10296 #define  SBI_CTL_OP_IORD		(0x2 << 8)
10297 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
10298 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
10299 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
10300 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
10301 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
10302 #define  SBI_BUSY			(0x1 << 0)
10303 #define  SBI_READY			(0x0 << 0)
10304 
10305 /* SBI offsets */
10306 #define  SBI_SSCDIVINTPHASE			0x0200
10307 #define  SBI_SSCDIVINTPHASE6			0x0600
10308 #define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT	1
10309 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
10310 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x) << 1)
10311 #define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT	8
10312 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
10313 #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x) << 8)
10314 #define   SBI_SSCDIVINTPHASE_DIR(x)		((x) << 15)
10315 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
10316 #define  SBI_SSCDITHPHASE			0x0204
10317 #define  SBI_SSCCTL				0x020c
10318 #define  SBI_SSCCTL6				0x060C
10319 #define   SBI_SSCCTL_PATHALT			(1 << 3)
10320 #define   SBI_SSCCTL_DISABLE			(1 << 0)
10321 #define  SBI_SSCAUXDIV6				0x0610
10322 #define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT	4
10323 #define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK	(1 << 4)
10324 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x) << 4)
10325 #define  SBI_DBUFF0				0x2a00
10326 #define  SBI_GEN0				0x1f00
10327 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
10328 
10329 /* LPT PIXCLK_GATE */
10330 #define PIXCLK_GATE			_MMIO(0xC6020)
10331 #define  PIXCLK_GATE_UNGATE		(1 << 0)
10332 #define  PIXCLK_GATE_GATE		(0 << 0)
10333 
10334 /* SPLL */
10335 #define SPLL_CTL			_MMIO(0x46020)
10336 #define  SPLL_PLL_ENABLE		(1 << 31)
10337 #define  SPLL_REF_BCLK			(0 << 28)
10338 #define  SPLL_REF_MUXED_SSC		(1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10339 #define  SPLL_REF_NON_SSC_HSW		(2 << 28)
10340 #define  SPLL_REF_PCH_SSC_BDW		(2 << 28)
10341 #define  SPLL_REF_LCPLL			(3 << 28)
10342 #define  SPLL_REF_MASK			(3 << 28)
10343 #define  SPLL_FREQ_810MHz		(0 << 26)
10344 #define  SPLL_FREQ_1350MHz		(1 << 26)
10345 #define  SPLL_FREQ_2700MHz		(2 << 26)
10346 #define  SPLL_FREQ_MASK			(3 << 26)
10347 
10348 /* WRPLL */
10349 #define _WRPLL_CTL1			0x46040
10350 #define _WRPLL_CTL2			0x46060
10351 #define WRPLL_CTL(pll)			_MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
10352 #define  WRPLL_PLL_ENABLE		(1 << 31)
10353 #define  WRPLL_REF_BCLK			(0 << 28)
10354 #define  WRPLL_REF_PCH_SSC		(1 << 28)
10355 #define  WRPLL_REF_MUXED_SSC_BDW	(2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10356 #define  WRPLL_REF_SPECIAL_HSW		(2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
10357 #define  WRPLL_REF_LCPLL		(3 << 28)
10358 #define  WRPLL_REF_MASK			(3 << 28)
10359 /* WRPLL divider programming */
10360 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
10361 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
10362 #define  WRPLL_DIVIDER_POST(x)		((x) << 8)
10363 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
10364 #define  WRPLL_DIVIDER_POST_SHIFT	8
10365 #define  WRPLL_DIVIDER_FEEDBACK(x)	((x) << 16)
10366 #define  WRPLL_DIVIDER_FB_SHIFT		16
10367 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
10368 
10369 /* Port clock selection */
10370 #define _PORT_CLK_SEL_A			0x46100
10371 #define _PORT_CLK_SEL_B			0x46104
10372 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
10373 #define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
10374 #define  PORT_CLK_SEL_LCPLL_1350	(1 << 29)
10375 #define  PORT_CLK_SEL_LCPLL_810		(2 << 29)
10376 #define  PORT_CLK_SEL_SPLL		(3 << 29)
10377 #define  PORT_CLK_SEL_WRPLL(pll)	(((pll) + 4) << 29)
10378 #define  PORT_CLK_SEL_WRPLL1		(4 << 29)
10379 #define  PORT_CLK_SEL_WRPLL2		(5 << 29)
10380 #define  PORT_CLK_SEL_NONE		(7 << 29)
10381 #define  PORT_CLK_SEL_MASK		(7 << 29)
10382 
10383 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
10384 #define DDI_CLK_SEL(port)		PORT_CLK_SEL(port)
10385 #define  DDI_CLK_SEL_NONE		(0x0 << 28)
10386 #define  DDI_CLK_SEL_MG			(0x8 << 28)
10387 #define  DDI_CLK_SEL_TBT_162		(0xC << 28)
10388 #define  DDI_CLK_SEL_TBT_270		(0xD << 28)
10389 #define  DDI_CLK_SEL_TBT_540		(0xE << 28)
10390 #define  DDI_CLK_SEL_TBT_810		(0xF << 28)
10391 #define  DDI_CLK_SEL_MASK		(0xF << 28)
10392 
10393 /* Transcoder clock selection */
10394 #define _TRANS_CLK_SEL_A		0x46140
10395 #define _TRANS_CLK_SEL_B		0x46144
10396 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
10397 /* For each transcoder, we need to select the corresponding port clock */
10398 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
10399 #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
10400 #define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
10401 #define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)
10402 
10403 
10404 #define CDCLK_FREQ			_MMIO(0x46200)
10405 
10406 #define _TRANSA_MSA_MISC		0x60410
10407 #define _TRANSB_MSA_MISC		0x61410
10408 #define _TRANSC_MSA_MISC		0x62410
10409 #define _TRANS_EDP_MSA_MISC		0x6f410
10410 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
10411 /* See DP_MSA_MISC_* for the bit definitions */
10412 
10413 #define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
10414 #define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
10415 #define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
10416 #define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
10417 #define TRANS_SET_CONTEXT_LATENCY(tran)		_MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
10418 #define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
10419 #define  TRANS_SET_CONTEXT_LATENCY_VALUE(x)	REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
10420 
10421 /* LCPLL Control */
10422 #define LCPLL_CTL			_MMIO(0x130040)
10423 #define  LCPLL_PLL_DISABLE		(1 << 31)
10424 #define  LCPLL_PLL_LOCK			(1 << 30)
10425 #define  LCPLL_REF_NON_SSC		(0 << 28)
10426 #define  LCPLL_REF_BCLK			(2 << 28)
10427 #define  LCPLL_REF_PCH_SSC		(3 << 28)
10428 #define  LCPLL_REF_MASK			(3 << 28)
10429 #define  LCPLL_CLK_FREQ_MASK		(3 << 26)
10430 #define  LCPLL_CLK_FREQ_450		(0 << 26)
10431 #define  LCPLL_CLK_FREQ_54O_BDW		(1 << 26)
10432 #define  LCPLL_CLK_FREQ_337_5_BDW	(2 << 26)
10433 #define  LCPLL_CLK_FREQ_675_BDW		(3 << 26)
10434 #define  LCPLL_CD_CLOCK_DISABLE		(1 << 25)
10435 #define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1 << 24)
10436 #define  LCPLL_CD2X_CLOCK_DISABLE	(1 << 23)
10437 #define  LCPLL_POWER_DOWN_ALLOW		(1 << 22)
10438 #define  LCPLL_CD_SOURCE_FCLK		(1 << 21)
10439 #define  LCPLL_CD_SOURCE_FCLK_DONE	(1 << 19)
10440 
10441 /*
10442  * SKL Clocks
10443  */
10444 
10445 /* CDCLK_CTL */
10446 #define CDCLK_CTL			_MMIO(0x46000)
10447 #define  CDCLK_FREQ_SEL_MASK		(3 << 26)
10448 #define  CDCLK_FREQ_450_432		(0 << 26)
10449 #define  CDCLK_FREQ_540			(1 << 26)
10450 #define  CDCLK_FREQ_337_308		(2 << 26)
10451 #define  CDCLK_FREQ_675_617		(3 << 26)
10452 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
10453 #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
10454 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
10455 #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
10456 #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
10457 #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
10458 #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
10459 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
10460 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
10461 #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
10462 #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
10463 #define  TGL_CDCLK_CD2X_PIPE_NONE	ICL_CDCLK_CD2X_PIPE_NONE
10464 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
10465 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
10466 
10467 /* LCPLL_CTL */
10468 #define LCPLL1_CTL		_MMIO(0x46010)
10469 #define LCPLL2_CTL		_MMIO(0x46014)
10470 #define  LCPLL_PLL_ENABLE	(1 << 31)
10471 
10472 /* DPLL control1 */
10473 #define DPLL_CTRL1		_MMIO(0x6C058)
10474 #define  DPLL_CTRL1_HDMI_MODE(id)		(1 << ((id) * 6 + 5))
10475 #define  DPLL_CTRL1_SSC(id)			(1 << ((id) * 6 + 4))
10476 #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7 << ((id) * 6 + 1))
10477 #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)		((id) * 6 + 1)
10478 #define  DPLL_CTRL1_LINK_RATE(linkrate, id)	((linkrate) << ((id) * 6 + 1))
10479 #define  DPLL_CTRL1_OVERRIDE(id)		(1 << ((id) * 6))
10480 #define  DPLL_CTRL1_LINK_RATE_2700		0
10481 #define  DPLL_CTRL1_LINK_RATE_1350		1
10482 #define  DPLL_CTRL1_LINK_RATE_810		2
10483 #define  DPLL_CTRL1_LINK_RATE_1620		3
10484 #define  DPLL_CTRL1_LINK_RATE_1080		4
10485 #define  DPLL_CTRL1_LINK_RATE_2160		5
10486 
10487 /* DPLL control2 */
10488 #define DPLL_CTRL2				_MMIO(0x6C05C)
10489 #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1 << ((port) + 15))
10490 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3 << ((port) * 3 + 1))
10491 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port) * 3 + 1)
10492 #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk) << ((port) * 3 + 1))
10493 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1 << ((port) * 3))
10494 
10495 /* DPLL Status */
10496 #define DPLL_STATUS	_MMIO(0x6C060)
10497 #define  DPLL_LOCK(id) (1 << ((id) * 8))
10498 
10499 /* DPLL cfg */
10500 #define _DPLL1_CFGCR1	0x6C040
10501 #define _DPLL2_CFGCR1	0x6C048
10502 #define _DPLL3_CFGCR1	0x6C050
10503 #define  DPLL_CFGCR1_FREQ_ENABLE	(1 << 31)
10504 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
10505 #define  DPLL_CFGCR1_DCO_FRACTION(x)	((x) << 9)
10506 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
10507 
10508 #define _DPLL1_CFGCR2	0x6C044
10509 #define _DPLL2_CFGCR2	0x6C04C
10510 #define _DPLL3_CFGCR2	0x6C054
10511 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
10512 #define  DPLL_CFGCR2_QDIV_RATIO(x)	((x) << 8)
10513 #define  DPLL_CFGCR2_QDIV_MODE(x)	((x) << 7)
10514 #define  DPLL_CFGCR2_KDIV_MASK		(3 << 5)
10515 #define  DPLL_CFGCR2_KDIV(x)		((x) << 5)
10516 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
10517 #define  DPLL_CFGCR2_KDIV_2 (1 << 5)
10518 #define  DPLL_CFGCR2_KDIV_3 (2 << 5)
10519 #define  DPLL_CFGCR2_KDIV_1 (3 << 5)
10520 #define  DPLL_CFGCR2_PDIV_MASK		(7 << 2)
10521 #define  DPLL_CFGCR2_PDIV(x)		((x) << 2)
10522 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
10523 #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
10524 #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
10525 #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
10526 #define  DPLL_CFGCR2_PDIV_7_INVALID	(5 << 2)
10527 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
10528 
10529 #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10530 #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10531 
10532 /* ICL Clocks */
10533 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
10534 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
10535 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
10536 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
10537 						       (tc_port) + 12 : \
10538 						       (tc_port) - TC_PORT_4 + 21))
10539 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
10540 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10541 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10542 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
10543 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
10544 	(3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10545 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
10546 	((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10547 
10548 /*
10549  * DG1 Clocks
10550  * First registers controls the first A and B, while the second register
10551  * controls the phy C and D. The bits on these registers are the
10552  * same, but refer to different phys
10553  */
10554 #define _DG1_DPCLKA_CFGCR0				0x164280
10555 #define _DG1_DPCLKA1_CFGCR0				0x16C280
10556 #define _DG1_DPCLKA_PHY_IDX(phy)			((phy) % 2)
10557 #define _DG1_DPCLKA_PLL_IDX(pll)			((pll) % 2)
10558 #define DG1_DPCLKA_CFGCR0(phy)				_MMIO_PHY((phy) / 2, \
10559 								  _DG1_DPCLKA_CFGCR0, \
10560 								  _DG1_DPCLKA1_CFGCR0)
10561 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)		REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
10562 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	(_DG1_DPCLKA_PHY_IDX(phy) * 2)
10563 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	(_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10564 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10565 
10566 /* ADLS Clocks */
10567 #define _ADLS_DPCLKA_CFGCR0			0x164280
10568 #define _ADLS_DPCLKA_CFGCR1			0x1642BC
10569 #define ADLS_DPCLKA_CFGCR(phy)			_MMIO_PHY((phy) / 3, \
10570 							  _ADLS_DPCLKA_CFGCR0, \
10571 							  _ADLS_DPCLKA_CFGCR1)
10572 #define  ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)		(((phy) % 3) * 2)
10573 /* ADLS DPCLKA_CFGCR0 DDI mask */
10574 #define  ADLS_DPCLKA_DDII_SEL_MASK			REG_GENMASK(5, 4)
10575 #define  ADLS_DPCLKA_DDIB_SEL_MASK			REG_GENMASK(3, 2)
10576 #define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
10577 /* ADLS DPCLKA_CFGCR1 DDI mask */
10578 #define  ADLS_DPCLKA_DDIK_SEL_MASK			REG_GENMASK(3, 2)
10579 #define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
10580 #define  ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)	_PICK((phy), \
10581 							ADLS_DPCLKA_DDIA_SEL_MASK, \
10582 							ADLS_DPCLKA_DDIB_SEL_MASK, \
10583 							ADLS_DPCLKA_DDII_SEL_MASK, \
10584 							ADLS_DPCLKA_DDIJ_SEL_MASK, \
10585 							ADLS_DPCLKA_DDIK_SEL_MASK)
10586 
10587 /* ICL PLL */
10588 #define DPLL0_ENABLE		0x46010
10589 #define DPLL1_ENABLE		0x46014
10590 #define _ADLS_DPLL2_ENABLE	0x46018
10591 #define _ADLS_DPLL3_ENABLE	0x46030
10592 #define  PLL_ENABLE		(1 << 31)
10593 #define  PLL_LOCK		(1 << 30)
10594 #define  PLL_POWER_ENABLE	(1 << 27)
10595 #define  PLL_POWER_STATE	(1 << 26)
10596 #define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10597 					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
10598 
10599 #define _DG2_PLL3_ENABLE	0x4601C
10600 
10601 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10602 				       _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
10603 
10604 #define TBT_PLL_ENABLE		_MMIO(0x46020)
10605 
10606 #define _MG_PLL1_ENABLE		0x46030
10607 #define _MG_PLL2_ENABLE		0x46034
10608 #define _MG_PLL3_ENABLE		0x46038
10609 #define _MG_PLL4_ENABLE		0x4603C
10610 /* Bits are the same as DPLL0_ENABLE */
10611 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
10612 					   _MG_PLL2_ENABLE)
10613 
10614 /* DG1 PLL */
10615 #define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10616 					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
10617 
10618 /* ADL-P Type C PLL */
10619 #define PORTTC1_PLL_ENABLE	0x46038
10620 #define PORTTC2_PLL_ENABLE	0x46040
10621 
10622 #define ADLP_PORTTC_PLL_ENABLE(tc_port)		_MMIO_PORT((tc_port), \
10623 							    PORTTC1_PLL_ENABLE, \
10624 							    PORTTC2_PLL_ENABLE)
10625 
10626 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
10627 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
10628 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
10629 #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
10630 #define   MG_REFCLKIN_CTL_OD_2_MUX(x)			((x) << 8)
10631 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
10632 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10633 					    _MG_REFCLKIN_CTL_PORT1, \
10634 					    _MG_REFCLKIN_CTL_PORT2)
10635 
10636 #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
10637 #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
10638 #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
10639 #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
10640 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)		((x) << 16)
10641 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
10642 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)
10643 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
10644 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10645 						   _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10646 						   _MG_CLKTOP2_CORECLKCTL1_PORT2)
10647 
10648 #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
10649 #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
10650 #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
10651 #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
10652 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)		((x) << 16)
10653 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
10654 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)
10655 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
10656 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
10657 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
10658 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)
10659 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)
10660 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)
10661 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)
10662 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT		8
10663 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
10664 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10665 						_MG_CLKTOP2_HSCLKCTL_PORT1, \
10666 						_MG_CLKTOP2_HSCLKCTL_PORT2)
10667 
10668 #define _MG_PLL_DIV0_PORT1				0x168A00
10669 #define _MG_PLL_DIV0_PORT2				0x169A00
10670 #define _MG_PLL_DIV0_PORT3				0x16AA00
10671 #define _MG_PLL_DIV0_PORT4				0x16BA00
10672 #define   MG_PLL_DIV0_FRACNEN_H				(1 << 30)
10673 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
10674 #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT			8
10675 #define   MG_PLL_DIV0_FBDIV_FRAC(x)			((x) << 8)
10676 #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
10677 #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
10678 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10679 					_MG_PLL_DIV0_PORT2)
10680 
10681 #define _MG_PLL_DIV1_PORT1				0x168A04
10682 #define _MG_PLL_DIV1_PORT2				0x169A04
10683 #define _MG_PLL_DIV1_PORT3				0x16AA04
10684 #define _MG_PLL_DIV1_PORT4				0x16BA04
10685 #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)			((x) << 16)
10686 #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
10687 #define   MG_PLL_DIV1_DITHER_DIV_2			(1 << 12)
10688 #define   MG_PLL_DIV1_DITHER_DIV_4			(2 << 12)
10689 #define   MG_PLL_DIV1_DITHER_DIV_8			(3 << 12)
10690 #define   MG_PLL_DIV1_NDIVRATIO(x)			((x) << 4)
10691 #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
10692 #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
10693 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10694 					_MG_PLL_DIV1_PORT2)
10695 
10696 #define _MG_PLL_LF_PORT1				0x168A08
10697 #define _MG_PLL_LF_PORT2				0x169A08
10698 #define _MG_PLL_LF_PORT3				0x16AA08
10699 #define _MG_PLL_LF_PORT4				0x16BA08
10700 #define   MG_PLL_LF_TDCTARGETCNT(x)			((x) << 24)
10701 #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
10702 #define   MG_PLL_LF_AFCCNTSEL_512			(1 << 20)
10703 #define   MG_PLL_LF_GAINCTRL(x)				((x) << 16)
10704 #define   MG_PLL_LF_INT_COEFF(x)			((x) << 8)
10705 #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
10706 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10707 				      _MG_PLL_LF_PORT2)
10708 
10709 #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
10710 #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
10711 #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
10712 #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
10713 #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32		(1 << 18)
10714 #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32		(1 << 16)
10715 #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)		((x) << 11)
10716 #define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)
10717 #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)
10718 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
10719 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10720 					     _MG_PLL_FRAC_LOCK_PORT1, \
10721 					     _MG_PLL_FRAC_LOCK_PORT2)
10722 
10723 #define _MG_PLL_SSC_PORT1				0x168A10
10724 #define _MG_PLL_SSC_PORT2				0x169A10
10725 #define _MG_PLL_SSC_PORT3				0x16AA10
10726 #define _MG_PLL_SSC_PORT4				0x16BA10
10727 #define   MG_PLL_SSC_EN					(1 << 28)
10728 #define   MG_PLL_SSC_TYPE(x)				((x) << 26)
10729 #define   MG_PLL_SSC_STEPLENGTH(x)			((x) << 16)
10730 #define   MG_PLL_SSC_STEPNUM(x)				((x) << 10)
10731 #define   MG_PLL_SSC_FLLEN				(1 << 9)
10732 #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
10733 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10734 				       _MG_PLL_SSC_PORT2)
10735 
10736 #define _MG_PLL_BIAS_PORT1				0x168A14
10737 #define _MG_PLL_BIAS_PORT2				0x169A14
10738 #define _MG_PLL_BIAS_PORT3				0x16AA14
10739 #define _MG_PLL_BIAS_PORT4				0x16BA14
10740 #define   MG_PLL_BIAS_BIAS_GB_SEL(x)			((x) << 30)
10741 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
10742 #define   MG_PLL_BIAS_INIT_DCOAMP(x)			((x) << 24)
10743 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
10744 #define   MG_PLL_BIAS_BIAS_BONUS(x)			((x) << 16)
10745 #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
10746 #define   MG_PLL_BIAS_BIASCAL_EN			(1 << 15)
10747 #define   MG_PLL_BIAS_CTRIM(x)				((x) << 8)
10748 #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
10749 #define   MG_PLL_BIAS_VREF_RDAC(x)			((x) << 5)
10750 #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
10751 #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
10752 #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
10753 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10754 					_MG_PLL_BIAS_PORT2)
10755 
10756 #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
10757 #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
10758 #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
10759 #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
10760 #define   MG_PLL_TDC_COLDST_IREFINT_EN			(1 << 27)
10761 #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)	((x) << 17)
10762 #define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)
10763 #define   MG_PLL_TDC_TDCOVCCORR_EN			(1 << 2)
10764 #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
10765 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10766 						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10767 						   _MG_PLL_TDC_COLDST_BIAS_PORT2)
10768 
10769 #define _ICL_DPLL0_CFGCR0		0x164000
10770 #define _ICL_DPLL1_CFGCR0		0x164080
10771 #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10772 						  _ICL_DPLL1_CFGCR0)
10773 #define   DPLL_CFGCR0_HDMI_MODE		(1 << 30)
10774 #define   DPLL_CFGCR0_SSC_ENABLE	(1 << 29)
10775 #define   DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
10776 #define   DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
10777 #define   DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
10778 #define   DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
10779 #define   DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
10780 #define   DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
10781 #define   DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
10782 #define   DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
10783 #define   DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
10784 #define   DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
10785 #define   DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
10786 #define   DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
10787 #define   DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
10788 #define   DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
10789 
10790 #define _ICL_DPLL0_CFGCR1		0x164004
10791 #define _ICL_DPLL1_CFGCR1		0x164084
10792 #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
10793 						  _ICL_DPLL1_CFGCR1)
10794 #define   DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
10795 #define   DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
10796 #define   DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
10797 #define   DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
10798 #define   DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
10799 #define   DPLL_CFGCR1_KDIV_MASK		(7 << 6)
10800 #define   DPLL_CFGCR1_KDIV_SHIFT		(6)
10801 #define   DPLL_CFGCR1_KDIV(x)		((x) << 6)
10802 #define   DPLL_CFGCR1_KDIV_1		(1 << 6)
10803 #define   DPLL_CFGCR1_KDIV_2		(2 << 6)
10804 #define   DPLL_CFGCR1_KDIV_3		(4 << 6)
10805 #define   DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
10806 #define   DPLL_CFGCR1_PDIV_SHIFT		(2)
10807 #define   DPLL_CFGCR1_PDIV(x)		((x) << 2)
10808 #define   DPLL_CFGCR1_PDIV_2		(1 << 2)
10809 #define   DPLL_CFGCR1_PDIV_3		(2 << 2)
10810 #define   DPLL_CFGCR1_PDIV_5		(4 << 2)
10811 #define   DPLL_CFGCR1_PDIV_7		(8 << 2)
10812 #define   DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
10813 #define   DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
10814 #define   TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
10815 
10816 #define _TGL_DPLL0_CFGCR0		0x164284
10817 #define _TGL_DPLL1_CFGCR0		0x16428C
10818 #define _TGL_TBTPLL_CFGCR0		0x16429C
10819 #define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10820 						  _TGL_DPLL1_CFGCR0, \
10821 						  _TGL_TBTPLL_CFGCR0)
10822 #define RKL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
10823 						  _TGL_DPLL1_CFGCR0)
10824 
10825 #define _TGL_DPLL0_CFGCR1		0x164288
10826 #define _TGL_DPLL1_CFGCR1		0x164290
10827 #define _TGL_TBTPLL_CFGCR1		0x1642A0
10828 #define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10829 						   _TGL_DPLL1_CFGCR1, \
10830 						   _TGL_TBTPLL_CFGCR1)
10831 #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
10832 						  _TGL_DPLL1_CFGCR1)
10833 
10834 #define _DG1_DPLL2_CFGCR0		0x16C284
10835 #define _DG1_DPLL3_CFGCR0		0x16C28C
10836 #define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10837 						   _TGL_DPLL1_CFGCR0, \
10838 						   _DG1_DPLL2_CFGCR0, \
10839 						   _DG1_DPLL3_CFGCR0)
10840 
10841 #define _DG1_DPLL2_CFGCR1               0x16C288
10842 #define _DG1_DPLL3_CFGCR1               0x16C290
10843 #define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10844 						   _TGL_DPLL1_CFGCR1, \
10845 						   _DG1_DPLL2_CFGCR1, \
10846 						   _DG1_DPLL3_CFGCR1)
10847 
10848 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
10849 #define _ADLS_DPLL3_CFGCR0		0x1642C0
10850 #define _ADLS_DPLL4_CFGCR0		0x164294
10851 #define ADLS_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10852 						   _TGL_DPLL1_CFGCR0, \
10853 						   _ADLS_DPLL4_CFGCR0, \
10854 						   _ADLS_DPLL3_CFGCR0)
10855 
10856 #define _ADLS_DPLL3_CFGCR1		0x1642C4
10857 #define _ADLS_DPLL4_CFGCR1		0x164298
10858 #define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10859 						   _TGL_DPLL1_CFGCR1, \
10860 						   _ADLS_DPLL4_CFGCR1, \
10861 						   _ADLS_DPLL3_CFGCR1)
10862 
10863 #define _DKL_PHY1_BASE			0x168000
10864 #define _DKL_PHY2_BASE			0x169000
10865 #define _DKL_PHY3_BASE			0x16A000
10866 #define _DKL_PHY4_BASE			0x16B000
10867 #define _DKL_PHY5_BASE			0x16C000
10868 #define _DKL_PHY6_BASE			0x16D000
10869 
10870 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
10871 #define _DKL_PLL_DIV0			0x200
10872 #define   DKL_PLL_DIV0_INTEG_COEFF(x)	((x) << 16)
10873 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
10874 #define   DKL_PLL_DIV0_PROP_COEFF(x)	((x) << 12)
10875 #define   DKL_PLL_DIV0_PROP_COEFF_MASK	(0xF << 12)
10876 #define   DKL_PLL_DIV0_FBPREDIV_SHIFT   (8)
10877 #define   DKL_PLL_DIV0_FBPREDIV(x)	((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10878 #define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10879 #define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
10880 #define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
10881 #define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10882 						    _DKL_PHY2_BASE) + \
10883 						    _DKL_PLL_DIV0)
10884 
10885 #define _DKL_PLL_DIV1				0x204
10886 #define   DKL_PLL_DIV1_IREF_TRIM(x)		((x) << 16)
10887 #define   DKL_PLL_DIV1_IREF_TRIM_MASK		(0x1F << 16)
10888 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)	((x) << 0)
10889 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK	(0xFF << 0)
10890 #define DKL_PLL_DIV1(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10891 						    _DKL_PHY2_BASE) + \
10892 						    _DKL_PLL_DIV1)
10893 
10894 #define _DKL_PLL_SSC				0x210
10895 #define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)	((x) << 29)
10896 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK	(0x7 << 29)
10897 #define   DKL_PLL_SSC_STEP_LEN(x)		((x) << 16)
10898 #define   DKL_PLL_SSC_STEP_LEN_MASK		(0xFF << 16)
10899 #define   DKL_PLL_SSC_STEP_NUM(x)		((x) << 11)
10900 #define   DKL_PLL_SSC_STEP_NUM_MASK		(0x7 << 11)
10901 #define   DKL_PLL_SSC_EN			(1 << 9)
10902 #define DKL_PLL_SSC(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10903 						    _DKL_PHY2_BASE) + \
10904 						    _DKL_PLL_SSC)
10905 
10906 #define _DKL_PLL_BIAS			0x214
10907 #define   DKL_PLL_BIAS_FRAC_EN_H	(1 << 30)
10908 #define   DKL_PLL_BIAS_FBDIV_SHIFT	(8)
10909 #define   DKL_PLL_BIAS_FBDIV_FRAC(x)	((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
10910 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK	(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
10911 #define DKL_PLL_BIAS(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10912 						    _DKL_PHY2_BASE) + \
10913 						    _DKL_PLL_BIAS)
10914 
10915 #define _DKL_PLL_TDC_COLDST_BIAS		0x218
10916 #define   DKL_PLL_TDC_SSC_STEP_SIZE(x)		((x) << 8)
10917 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK	(0xFF << 8)
10918 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)		((x) << 0)
10919 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK	(0xFF << 0)
10920 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
10921 						     _DKL_PHY1_BASE, \
10922 						     _DKL_PHY2_BASE) + \
10923 						     _DKL_PLL_TDC_COLDST_BIAS)
10924 
10925 #define _DKL_REFCLKIN_CTL		0x12C
10926 /* Bits are the same as MG_REFCLKIN_CTL */
10927 #define DKL_REFCLKIN_CTL(tc_port)	_MMIO(_PORT(tc_port, \
10928 						    _DKL_PHY1_BASE, \
10929 						    _DKL_PHY2_BASE) + \
10930 					      _DKL_REFCLKIN_CTL)
10931 
10932 #define _DKL_CLKTOP2_HSCLKCTL		0xD4
10933 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */
10934 #define DKL_CLKTOP2_HSCLKCTL(tc_port)	_MMIO(_PORT(tc_port, \
10935 						    _DKL_PHY1_BASE, \
10936 						    _DKL_PHY2_BASE) + \
10937 					      _DKL_CLKTOP2_HSCLKCTL)
10938 
10939 #define _DKL_CLKTOP2_CORECLKCTL1		0xD8
10940 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
10941 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)	_MMIO(_PORT(tc_port, \
10942 							    _DKL_PHY1_BASE, \
10943 							    _DKL_PHY2_BASE) + \
10944 						      _DKL_CLKTOP2_CORECLKCTL1)
10945 
10946 #define _DKL_TX_DPCNTL0				0x2C0
10947 #define  DKL_TX_PRESHOOT_COEFF(x)			((x) << 13)
10948 #define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
10949 #define  DKL_TX_DE_EMPHASIS_COEFF(x)		((x) << 8)
10950 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK		(0x1f << 8)
10951 #define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
10952 #define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
10953 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
10954 						     _DKL_PHY1_BASE, \
10955 						     _DKL_PHY2_BASE) + \
10956 						     _DKL_TX_DPCNTL0)
10957 
10958 #define _DKL_TX_DPCNTL1				0x2C4
10959 /* Bits are the same as DKL_TX_DPCNTRL0 */
10960 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
10961 						     _DKL_PHY1_BASE, \
10962 						     _DKL_PHY2_BASE) + \
10963 						     _DKL_TX_DPCNTL1)
10964 
10965 #define _DKL_TX_DPCNTL2				0x2C8
10966 #define  DKL_TX_LOADGEN_SHARING_PMD_DISABLE            REG_BIT(12)
10967 #define  DKL_TX_DP20BITMODE				(1 << 2)
10968 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
10969 						     _DKL_PHY1_BASE, \
10970 						     _DKL_PHY2_BASE) + \
10971 						     _DKL_TX_DPCNTL2)
10972 
10973 #define _DKL_TX_FW_CALIB				0x2F8
10974 #define  DKL_TX_CFG_DISABLE_WAIT_INIT			(1 << 7)
10975 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
10976 						     _DKL_PHY1_BASE, \
10977 						     _DKL_PHY2_BASE) + \
10978 						     _DKL_TX_FW_CALIB)
10979 
10980 #define _DKL_TX_PMD_LANE_SUS				0xD00
10981 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
10982 							  _DKL_PHY1_BASE, \
10983 							  _DKL_PHY2_BASE) + \
10984 							  _DKL_TX_PMD_LANE_SUS)
10985 
10986 #define _DKL_TX_DW17					0xDC4
10987 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
10988 						     _DKL_PHY1_BASE, \
10989 						     _DKL_PHY2_BASE) + \
10990 						     _DKL_TX_DW17)
10991 
10992 #define _DKL_TX_DW18					0xDC8
10993 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
10994 						     _DKL_PHY1_BASE, \
10995 						     _DKL_PHY2_BASE) + \
10996 						     _DKL_TX_DW18)
10997 
10998 #define _DKL_DP_MODE					0xA0
10999 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
11000 						     _DKL_PHY1_BASE, \
11001 						     _DKL_PHY2_BASE) + \
11002 						     _DKL_DP_MODE)
11003 
11004 #define _DKL_CMN_UC_DW27			0x36C
11005 #define  DKL_CMN_UC_DW27_UC_HEALTH		(0x1 << 15)
11006 #define DKL_CMN_UC_DW_27(tc_port)		_MMIO(_PORT(tc_port, \
11007 							    _DKL_PHY1_BASE, \
11008 							    _DKL_PHY2_BASE) + \
11009 							    _DKL_CMN_UC_DW27)
11010 
11011 /*
11012  * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
11013  * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
11014  * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
11015  * bits that point the 4KB window into the full PHY register space.
11016  */
11017 #define _HIP_INDEX_REG0			0x1010A0
11018 #define _HIP_INDEX_REG1			0x1010A4
11019 #define HIP_INDEX_REG(tc_port)		_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
11020 					      : _HIP_INDEX_REG1)
11021 #define _HIP_INDEX_SHIFT(tc_port)	(8 * ((tc_port) % 4))
11022 #define HIP_INDEX_VAL(tc_port, val)	((val) << _HIP_INDEX_SHIFT(tc_port))
11023 
11024 /* BXT display engine PLL */
11025 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
11026 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
11027 #define   BXT_DE_PLL_RATIO_MASK		0xff
11028 
11029 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
11030 #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
11031 #define   BXT_DE_PLL_LOCK		(1 << 30)
11032 #define   BXT_DE_PLL_FREQ_REQ		(1 << 23)
11033 #define   BXT_DE_PLL_FREQ_REQ_ACK	(1 << 22)
11034 #define   ICL_CDCLK_PLL_RATIO(x)	(x)
11035 #define   ICL_CDCLK_PLL_RATIO_MASK	0xff
11036 
11037 /* GEN9 DC */
11038 #define DC_STATE_EN			_MMIO(0x45504)
11039 #define  DC_STATE_DISABLE		0
11040 #define  DC_STATE_EN_DC3CO		REG_BIT(30)
11041 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
11042 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
11043 #define  DC_STATE_EN_DC9		(1 << 3)
11044 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
11045 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
11046 
11047 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
11048 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
11049 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
11050 
11051 #define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
11052 #define  BXT_REQ_DATA_MASK			0x3F
11053 #define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT		12
11054 #define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)
11055 #define  BXT_MEMORY_FREQ_MULTIPLIER_HZ		133333333
11056 
11057 #define BXT_D_CR_DRP0_DUNIT8			0x1000
11058 #define BXT_D_CR_DRP0_DUNIT9			0x1200
11059 #define  BXT_D_CR_DRP0_DUNIT_START		8
11060 #define  BXT_D_CR_DRP0_DUNIT_END		11
11061 #define BXT_D_CR_DRP0_DUNIT(x)	_MMIO(MCHBAR_MIRROR_BASE_SNB + \
11062 				      _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
11063 						 BXT_D_CR_DRP0_DUNIT9))
11064 #define  BXT_DRAM_RANK_MASK			0x3
11065 #define  BXT_DRAM_RANK_SINGLE			0x1
11066 #define  BXT_DRAM_RANK_DUAL			0x3
11067 #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
11068 #define  BXT_DRAM_WIDTH_SHIFT			4
11069 #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
11070 #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
11071 #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
11072 #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
11073 #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
11074 #define  BXT_DRAM_SIZE_SHIFT			6
11075 #define  BXT_DRAM_SIZE_4GBIT			(0x0 << 6)
11076 #define  BXT_DRAM_SIZE_6GBIT			(0x1 << 6)
11077 #define  BXT_DRAM_SIZE_8GBIT			(0x2 << 6)
11078 #define  BXT_DRAM_SIZE_12GBIT			(0x3 << 6)
11079 #define  BXT_DRAM_SIZE_16GBIT			(0x4 << 6)
11080 #define  BXT_DRAM_TYPE_MASK			(0x7 << 22)
11081 #define  BXT_DRAM_TYPE_SHIFT			22
11082 #define  BXT_DRAM_TYPE_DDR3			(0x0 << 22)
11083 #define  BXT_DRAM_TYPE_LPDDR3			(0x1 << 22)
11084 #define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)
11085 #define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)
11086 
11087 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
11088 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
11089 #define  SKL_REQ_DATA_MASK			(0xF << 0)
11090 #define  DG1_GEAR_TYPE				REG_BIT(16)
11091 
11092 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
11093 #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
11094 #define  SKL_DRAM_DDR_TYPE_DDR4			(0 << 0)
11095 #define  SKL_DRAM_DDR_TYPE_DDR3			(1 << 0)
11096 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
11097 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
11098 
11099 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
11100 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
11101 #define  SKL_DRAM_S_SHIFT			16
11102 #define  SKL_DRAM_SIZE_MASK			0x3F
11103 #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
11104 #define  SKL_DRAM_WIDTH_SHIFT			8
11105 #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
11106 #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
11107 #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
11108 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
11109 #define  SKL_DRAM_RANK_SHIFT			10
11110 #define  SKL_DRAM_RANK_1			(0x0 << 10)
11111 #define  SKL_DRAM_RANK_2			(0x1 << 10)
11112 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
11113 #define  ICL_DRAM_SIZE_MASK			0x7F
11114 #define  ICL_DRAM_WIDTH_MASK			(0x3 << 7)
11115 #define  ICL_DRAM_WIDTH_SHIFT			7
11116 #define  ICL_DRAM_WIDTH_X8			(0x0 << 7)
11117 #define  ICL_DRAM_WIDTH_X16			(0x1 << 7)
11118 #define  ICL_DRAM_WIDTH_X32			(0x2 << 7)
11119 #define  ICL_DRAM_RANK_MASK			(0x3 << 9)
11120 #define  ICL_DRAM_RANK_SHIFT			9
11121 #define  ICL_DRAM_RANK_1			(0x0 << 9)
11122 #define  ICL_DRAM_RANK_2			(0x1 << 9)
11123 #define  ICL_DRAM_RANK_3			(0x2 << 9)
11124 #define  ICL_DRAM_RANK_4			(0x3 << 9)
11125 
11126 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
11127 #define  DG1_QCLK_RATIO_MASK			REG_GENMASK(9, 2)
11128 #define  DG1_QCLK_REFERENCE			REG_BIT(10)
11129 
11130 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
11131 #define   DG1_DRAM_T_RDPRE_MASK			REG_GENMASK(16, 11)
11132 #define   DG1_DRAM_T_RP_MASK			REG_GENMASK(6, 0)
11133 #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
11134 #define   DG1_DRAM_T_RCD_MASK			REG_GENMASK(15, 9)
11135 #define   DG1_DRAM_T_RAS_MASK			REG_GENMASK(8, 1)
11136 
11137 /*
11138  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
11139  * since on HSW we can't write to it using intel_uncore_write.
11140  */
11141 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
11142 #define D_COMP_BDW			_MMIO(0x138144)
11143 #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
11144 #define  D_COMP_COMP_FORCE		(1 << 8)
11145 #define  D_COMP_COMP_DISABLE		(1 << 0)
11146 
11147 /* Pipe WM_LINETIME - watermark line time */
11148 #define _WM_LINETIME_A		0x45270
11149 #define _WM_LINETIME_B		0x45274
11150 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
11151 #define  HSW_LINETIME_MASK	REG_GENMASK(8, 0)
11152 #define  HSW_LINETIME(x)	REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
11153 #define  HSW_IPS_LINETIME_MASK	REG_GENMASK(24, 16)
11154 #define  HSW_IPS_LINETIME(x)	REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
11155 
11156 /* SFUSE_STRAP */
11157 #define SFUSE_STRAP			_MMIO(0xc2014)
11158 #define  SFUSE_STRAP_FUSE_LOCK		(1 << 13)
11159 #define  SFUSE_STRAP_RAW_FREQUENCY	(1 << 8)
11160 #define  SFUSE_STRAP_DISPLAY_DISABLED	(1 << 7)
11161 #define  SFUSE_STRAP_CRT_DISABLED	(1 << 6)
11162 #define  SFUSE_STRAP_DDIF_DETECTED	(1 << 3)
11163 #define  SFUSE_STRAP_DDIB_DETECTED	(1 << 2)
11164 #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
11165 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
11166 
11167 #define WM_MISC				_MMIO(0x45260)
11168 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
11169 
11170 #define WM_DBG				_MMIO(0x45280)
11171 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
11172 #define  WM_DBG_DISALLOW_MAXFIFO	(1 << 1)
11173 #define  WM_DBG_DISALLOW_SPRITE		(1 << 2)
11174 
11175 /* pipe CSC */
11176 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
11177 #define _PIPE_A_CSC_COEFF_BY	0x49014
11178 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
11179 #define _PIPE_A_CSC_COEFF_BU	0x4901c
11180 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
11181 #define _PIPE_A_CSC_COEFF_BV	0x49024
11182 
11183 #define _PIPE_A_CSC_MODE	0x49028
11184 #define  ICL_CSC_ENABLE			(1 << 31) /* icl+ */
11185 #define  ICL_OUTPUT_CSC_ENABLE		(1 << 30) /* icl+ */
11186 #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2) /* ilk/snb */
11187 #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1) /* pre-glk */
11188 #define  CSC_MODE_YUV_TO_RGB		(1 << 0) /* ilk/snb */
11189 
11190 #define _PIPE_A_CSC_PREOFF_HI	0x49030
11191 #define _PIPE_A_CSC_PREOFF_ME	0x49034
11192 #define _PIPE_A_CSC_PREOFF_LO	0x49038
11193 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
11194 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
11195 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
11196 
11197 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
11198 #define _PIPE_B_CSC_COEFF_BY	0x49114
11199 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
11200 #define _PIPE_B_CSC_COEFF_BU	0x4911c
11201 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
11202 #define _PIPE_B_CSC_COEFF_BV	0x49124
11203 #define _PIPE_B_CSC_MODE	0x49128
11204 #define _PIPE_B_CSC_PREOFF_HI	0x49130
11205 #define _PIPE_B_CSC_PREOFF_ME	0x49134
11206 #define _PIPE_B_CSC_PREOFF_LO	0x49138
11207 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
11208 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
11209 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
11210 
11211 #define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
11212 #define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
11213 #define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
11214 #define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
11215 #define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
11216 #define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
11217 #define PIPE_CSC_MODE(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
11218 #define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
11219 #define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
11220 #define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
11221 #define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
11222 #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
11223 #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
11224 
11225 /* Pipe Output CSC */
11226 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
11227 #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
11228 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
11229 #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
11230 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
11231 #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
11232 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
11233 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
11234 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
11235 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
11236 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
11237 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
11238 
11239 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
11240 #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
11241 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
11242 #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
11243 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
11244 #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
11245 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
11246 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
11247 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
11248 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
11249 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
11250 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
11251 
11252 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe,\
11253 							   _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
11254 							   _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
11255 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, \
11256 							   _PIPE_A_OUTPUT_CSC_COEFF_BY, \
11257 							   _PIPE_B_OUTPUT_CSC_COEFF_BY)
11258 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, \
11259 							   _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
11260 							   _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
11261 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, \
11262 							   _PIPE_A_OUTPUT_CSC_COEFF_BU, \
11263 							   _PIPE_B_OUTPUT_CSC_COEFF_BU)
11264 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, \
11265 							   _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
11266 							   _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
11267 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, \
11268 							   _PIPE_A_OUTPUT_CSC_COEFF_BV, \
11269 							   _PIPE_B_OUTPUT_CSC_COEFF_BV)
11270 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, \
11271 							   _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
11272 							   _PIPE_B_OUTPUT_CSC_PREOFF_HI)
11273 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, \
11274 							   _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
11275 							   _PIPE_B_OUTPUT_CSC_PREOFF_ME)
11276 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, \
11277 							   _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
11278 							   _PIPE_B_OUTPUT_CSC_PREOFF_LO)
11279 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, \
11280 							   _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
11281 							   _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
11282 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, \
11283 							   _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
11284 							   _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
11285 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, \
11286 							   _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
11287 							   _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
11288 
11289 /* pipe degamma/gamma LUTs on IVB+ */
11290 #define _PAL_PREC_INDEX_A	0x4A400
11291 #define _PAL_PREC_INDEX_B	0x4AC00
11292 #define _PAL_PREC_INDEX_C	0x4B400
11293 #define   PAL_PREC_10_12_BIT		(0 << 31)
11294 #define   PAL_PREC_SPLIT_MODE		(1 << 31)
11295 #define   PAL_PREC_AUTO_INCREMENT	(1 << 15)
11296 #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
11297 #define   PAL_PREC_INDEX_VALUE(x)	((x) << 0)
11298 #define _PAL_PREC_DATA_A	0x4A404
11299 #define _PAL_PREC_DATA_B	0x4AC04
11300 #define _PAL_PREC_DATA_C	0x4B404
11301 #define _PAL_PREC_GC_MAX_A	0x4A410
11302 #define _PAL_PREC_GC_MAX_B	0x4AC10
11303 #define _PAL_PREC_GC_MAX_C	0x4B410
11304 #define   PREC_PAL_DATA_RED_MASK	REG_GENMASK(29, 20)
11305 #define   PREC_PAL_DATA_GREEN_MASK	REG_GENMASK(19, 10)
11306 #define   PREC_PAL_DATA_BLUE_MASK	REG_GENMASK(9, 0)
11307 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
11308 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
11309 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
11310 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
11311 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
11312 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
11313 
11314 #define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
11315 #define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
11316 #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
11317 #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
11318 #define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
11319 
11320 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
11321 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
11322 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
11323 #define   PRE_CSC_GAMC_AUTO_INCREMENT	(1 << 10)
11324 #define _PRE_CSC_GAMC_DATA_A	0x4A488
11325 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
11326 #define _PRE_CSC_GAMC_DATA_C	0x4B488
11327 
11328 #define PRE_CSC_GAMC_INDEX(pipe)	_MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
11329 #define PRE_CSC_GAMC_DATA(pipe)		_MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
11330 
11331 /* ICL Multi segmented gamma */
11332 #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
11333 #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
11334 #define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT		REG_BIT(15)
11335 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
11336 
11337 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
11338 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
11339 #define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
11340 #define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
11341 #define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
11342 #define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
11343 #define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4)
11344 #define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
11345 
11346 #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
11347 					_PAL_PREC_MULTI_SEG_INDEX_A, \
11348 					_PAL_PREC_MULTI_SEG_INDEX_B)
11349 #define PREC_PAL_MULTI_SEG_DATA(pipe)	_MMIO_PIPE(pipe, \
11350 					_PAL_PREC_MULTI_SEG_DATA_A, \
11351 					_PAL_PREC_MULTI_SEG_DATA_B)
11352 
11353 /* pipe CSC & degamma/gamma LUTs on CHV */
11354 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
11355 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
11356 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
11357 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
11358 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
11359 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
11360 #define   CGM_PIPE_DEGAMMA_RED_MASK	REG_GENMASK(13, 0)
11361 #define   CGM_PIPE_DEGAMMA_GREEN_MASK	REG_GENMASK(29, 16)
11362 #define   CGM_PIPE_DEGAMMA_BLUE_MASK	REG_GENMASK(13, 0)
11363 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
11364 #define   CGM_PIPE_GAMMA_RED_MASK	REG_GENMASK(9, 0)
11365 #define   CGM_PIPE_GAMMA_GREEN_MASK	REG_GENMASK(25, 16)
11366 #define   CGM_PIPE_GAMMA_BLUE_MASK	REG_GENMASK(9, 0)
11367 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
11368 #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
11369 #define   CGM_PIPE_MODE_CSC	(1 << 1)
11370 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
11371 
11372 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
11373 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
11374 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
11375 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
11376 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
11377 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
11378 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
11379 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
11380 
11381 #define CGM_PIPE_CSC_COEFF01(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
11382 #define CGM_PIPE_CSC_COEFF23(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
11383 #define CGM_PIPE_CSC_COEFF45(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
11384 #define CGM_PIPE_CSC_COEFF67(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
11385 #define CGM_PIPE_CSC_COEFF8(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
11386 #define CGM_PIPE_DEGAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
11387 #define CGM_PIPE_GAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
11388 #define CGM_PIPE_MODE(pipe)		_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
11389 
11390 /* MIPI DSI registers */
11391 
11392 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
11393 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
11394 
11395 /* Gen11 DSI */
11396 #define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
11397 						    dsi0, dsi1)
11398 
11399 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
11400 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
11401 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
11402 #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
11403 
11404 #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
11405 #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
11406 #define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
11407 							_ICL_DSI_ESC_CLK_DIV0, \
11408 							_ICL_DSI_ESC_CLK_DIV1)
11409 #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
11410 #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
11411 #define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
11412 						_ICL_DPHY_ESC_CLK_DIV0, \
11413 						_ICL_DPHY_ESC_CLK_DIV1)
11414 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
11415 #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
11416 #define  ICL_ESC_CLK_DIV_MASK			0x1ff
11417 #define  ICL_ESC_CLK_DIV_SHIFT			0
11418 #define DSI_MAX_ESC_CLK			20000		/* in KHz */
11419 
11420 #define _ADL_MIPIO_REG			0x180
11421 #define ADL_MIPIO_DW(port, dw)		_MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
11422 #define   TX_ESC_CLK_DIV_PHY_SEL	REGBIT(16)
11423 #define   TX_ESC_CLK_DIV_PHY_MASK	REG_GENMASK(23, 16)
11424 #define   TX_ESC_CLK_DIV_PHY		REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
11425 
11426 #define _DSI_CMD_FRMCTL_0		0x6b034
11427 #define _DSI_CMD_FRMCTL_1		0x6b834
11428 #define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
11429 						   _DSI_CMD_FRMCTL_0,\
11430 						   _DSI_CMD_FRMCTL_1)
11431 #define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
11432 #define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
11433 #define   DSI_NULL_PACKET_ENABLE		(1 << 28)
11434 #define   DSI_FRAME_IN_PROGRESS			(1 << 0)
11435 
11436 #define _DSI_INTR_MASK_REG_0		0x6b070
11437 #define _DSI_INTR_MASK_REG_1		0x6b870
11438 #define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
11439 						   _DSI_INTR_MASK_REG_0,\
11440 						   _DSI_INTR_MASK_REG_1)
11441 
11442 #define _DSI_INTR_IDENT_REG_0		0x6b074
11443 #define _DSI_INTR_IDENT_REG_1		0x6b874
11444 #define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
11445 						   _DSI_INTR_IDENT_REG_0,\
11446 						   _DSI_INTR_IDENT_REG_1)
11447 #define   DSI_TE_EVENT				(1 << 31)
11448 #define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
11449 #define   DSI_TX_DATA				(1 << 29)
11450 #define   DSI_ULPS_ENTRY_DONE			(1 << 28)
11451 #define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
11452 #define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
11453 #define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
11454 #define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
11455 #define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
11456 #define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
11457 #define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
11458 #define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
11459 #define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
11460 #define   DSI_FRAME_UPDATE_DONE			(1 << 16)
11461 #define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
11462 #define   DSI_INVALID_TX_LENGTH			(1 << 13)
11463 #define   DSI_INVALID_VC			(1 << 12)
11464 #define   DSI_INVALID_DATA_TYPE			(1 << 11)
11465 #define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
11466 #define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
11467 #define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
11468 #define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
11469 #define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
11470 #define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
11471 #define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
11472 #define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
11473 #define   DSI_EOT_SYNC_ERROR			(1 << 2)
11474 #define   DSI_SOT_SYNC_ERROR			(1 << 1)
11475 #define   DSI_SOT_ERROR				(1 << 0)
11476 
11477 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
11478 #define GEN4_TIMESTAMP		_MMIO(0x2358)
11479 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
11480 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
11481 
11482 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
11483 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
11484 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
11485 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT	12
11486 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
11487 
11488 #define _PIPE_FRMTMSTMP_A		0x70048
11489 #define PIPE_FRMTMSTMP(pipe)		\
11490 			_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
11491 
11492 /* BXT MIPI clock controls */
11493 #define BXT_MAX_VAR_OUTPUT_KHZ			39500
11494 
11495 #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
11496 #define  BXT_MIPI1_DIV_SHIFT			26
11497 #define  BXT_MIPI2_DIV_SHIFT			10
11498 #define  BXT_MIPI_DIV_SHIFT(port)		\
11499 			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
11500 					BXT_MIPI2_DIV_SHIFT)
11501 
11502 /* TX control divider to select actual TX clock output from (8x/var) */
11503 #define  BXT_MIPI1_TX_ESCLK_SHIFT		26
11504 #define  BXT_MIPI2_TX_ESCLK_SHIFT		10
11505 #define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
11506 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
11507 					BXT_MIPI2_TX_ESCLK_SHIFT)
11508 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
11509 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
11510 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
11511 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
11512 					BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
11513 #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)	\
11514 		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
11515 /* RX upper control divider to select actual RX clock output from 8x */
11516 #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT		21
11517 #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT		5
11518 #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)		\
11519 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
11520 					BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
11521 #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 21)
11522 #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 5)
11523 #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)	\
11524 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
11525 					BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
11526 #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)	\
11527 		(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
11528 /* 8/3X divider to select the actual 8/3X clock output from 8x */
11529 #define  BXT_MIPI1_8X_BY3_SHIFT                19
11530 #define  BXT_MIPI2_8X_BY3_SHIFT                3
11531 #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
11532 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
11533 					BXT_MIPI2_8X_BY3_SHIFT)
11534 #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
11535 #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
11536 #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
11537 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
11538 						BXT_MIPI2_8X_BY3_DIVIDER_MASK)
11539 #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
11540 			(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
11541 /* RX lower control divider to select actual RX clock output from 8x */
11542 #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT		16
11543 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
11544 #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)		\
11545 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
11546 					BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
11547 #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 16)
11548 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
11549 #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)	\
11550 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
11551 					BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
11552 #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)	\
11553 		(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
11554 
11555 #define RX_DIVIDER_BIT_1_2                     0x3
11556 #define RX_DIVIDER_BIT_3_4                     0xC
11557 
11558 /* BXT MIPI mode configure */
11559 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
11560 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
11561 #define  BXT_MIPI_TRANS_HACTIVE(tc)	_MMIO_MIPI(tc, \
11562 		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
11563 
11564 #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
11565 #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
11566 #define  BXT_MIPI_TRANS_VACTIVE(tc)	_MMIO_MIPI(tc, \
11567 		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
11568 
11569 #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
11570 #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
11571 #define  BXT_MIPI_TRANS_VTOTAL(tc)	_MMIO_MIPI(tc, \
11572 		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
11573 
11574 #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
11575 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
11576 #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11577 #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11578 #define  BXT_DSIC_16X_BY1		(0 << 10)
11579 #define  BXT_DSIC_16X_BY2		(1 << 10)
11580 #define  BXT_DSIC_16X_BY3		(2 << 10)
11581 #define  BXT_DSIC_16X_BY4		(3 << 10)
11582 #define  BXT_DSIC_16X_MASK		(3 << 10)
11583 #define  BXT_DSIA_16X_BY1		(0 << 8)
11584 #define  BXT_DSIA_16X_BY2		(1 << 8)
11585 #define  BXT_DSIA_16X_BY3		(2 << 8)
11586 #define  BXT_DSIA_16X_BY4		(3 << 8)
11587 #define  BXT_DSIA_16X_MASK		(3 << 8)
11588 #define  BXT_DSI_FREQ_SEL_SHIFT		8
11589 #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
11590 
11591 #define BXT_DSI_PLL_RATIO_MAX		0x7D
11592 #define BXT_DSI_PLL_RATIO_MIN		0x22
11593 #define GLK_DSI_PLL_RATIO_MAX		0x6F
11594 #define GLK_DSI_PLL_RATIO_MIN		0x22
11595 #define BXT_DSI_PLL_RATIO_MASK		0xFF
11596 #define BXT_REF_CLOCK_KHZ		19200
11597 
11598 #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
11599 #define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
11600 #define  BXT_DSI_PLL_LOCKED		(1 << 30)
11601 
11602 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
11603 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
11604 #define MIPI_PORT_CTRL(port)	_MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
11605 
11606  /* BXT port control */
11607 #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
11608 #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
11609 #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
11610 
11611 /* ICL DSI MODE control */
11612 #define _ICL_DSI_IO_MODECTL_0				0x6B094
11613 #define _ICL_DSI_IO_MODECTL_1				0x6B894
11614 #define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
11615 						    _ICL_DSI_IO_MODECTL_0, \
11616 						    _ICL_DSI_IO_MODECTL_1)
11617 #define  COMBO_PHY_MODE_DSI				(1 << 0)
11618 
11619 /* Display Stream Splitter Control */
11620 #define DSS_CTL1				_MMIO(0x67400)
11621 #define  SPLITTER_ENABLE			(1 << 31)
11622 #define  JOINER_ENABLE				(1 << 30)
11623 #define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
11624 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
11625 #define  OVERLAP_PIXELS_MASK			(0xf << 16)
11626 #define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
11627 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11628 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11629 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
11630 
11631 #define DSS_CTL2				_MMIO(0x67404)
11632 #define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
11633 #define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
11634 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11635 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11636 
11637 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
11638 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
11639 #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
11640 							   _ICL_PIPE_DSS_CTL1_PB, \
11641 							   _ICL_PIPE_DSS_CTL1_PC)
11642 #define  BIG_JOINER_ENABLE			(1 << 29)
11643 #define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
11644 #define  VGA_CENTERING_ENABLE			(1 << 27)
11645 #define  SPLITTER_CONFIGURATION_MASK		REG_GENMASK(26, 25)
11646 #define  SPLITTER_CONFIGURATION_2_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
11647 #define  SPLITTER_CONFIGURATION_4_SEGMENT	REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
11648 #define  UNCOMPRESSED_JOINER_MASTER		(1 << 21)
11649 #define  UNCOMPRESSED_JOINER_SLAVE		(1 << 20)
11650 
11651 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
11652 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
11653 #define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
11654 							   _ICL_PIPE_DSS_CTL2_PB, \
11655 							   _ICL_PIPE_DSS_CTL2_PC)
11656 
11657 #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
11658 #define  STAP_SELECT					(1 << 0)
11659 
11660 #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
11661 #define  HS_IO_CTRL_SELECT				(1 << 0)
11662 
11663 #define  DPI_ENABLE					(1 << 31) /* A + C */
11664 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
11665 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
11666 #define  DUAL_LINK_MODE_SHIFT				26
11667 #define  DUAL_LINK_MODE_MASK				(1 << 26)
11668 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
11669 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
11670 #define  DITHERING_ENABLE				(1 << 25) /* A + C */
11671 #define  FLOPPED_HSTX					(1 << 23)
11672 #define  DE_INVERT					(1 << 19) /* XXX */
11673 #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
11674 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
11675 #define  AFE_LATCHOUT					(1 << 17)
11676 #define  LP_OUTPUT_HOLD					(1 << 16)
11677 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
11678 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
11679 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
11680 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
11681 #define  CSB_SHIFT					9
11682 #define  CSB_MASK					(3 << 9)
11683 #define  CSB_20MHZ					(0 << 9)
11684 #define  CSB_10MHZ					(1 << 9)
11685 #define  CSB_40MHZ					(2 << 9)
11686 #define  BANDGAP_MASK					(1 << 8)
11687 #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
11688 #define  BANDGAP_LNC_CIRCUIT				(1 << 8)
11689 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
11690 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
11691 #define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
11692 #define  TEARING_EFFECT_SHIFT				2 /* A + C */
11693 #define  TEARING_EFFECT_MASK				(3 << 2)
11694 #define  TEARING_EFFECT_OFF				(0 << 2)
11695 #define  TEARING_EFFECT_DSI				(1 << 2)
11696 #define  TEARING_EFFECT_GPIO				(2 << 2)
11697 #define  LANE_CONFIGURATION_SHIFT			0
11698 #define  LANE_CONFIGURATION_MASK			(3 << 0)
11699 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
11700 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
11701 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
11702 
11703 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
11704 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
11705 #define MIPI_TEARING_CTRL(port)			_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
11706 #define  TEARING_EFFECT_DELAY_SHIFT			0
11707 #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
11708 
11709 /* XXX: all bits reserved */
11710 #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
11711 
11712 /* MIPI DSI Controller and D-PHY registers */
11713 
11714 #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
11715 #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
11716 #define MIPI_DEVICE_READY(port)		_MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
11717 #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
11718 #define  ULPS_STATE_MASK				(3 << 1)
11719 #define  ULPS_STATE_ENTER				(2 << 1)
11720 #define  ULPS_STATE_EXIT				(1 << 1)
11721 #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
11722 #define  DEVICE_READY					(1 << 0)
11723 
11724 #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
11725 #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
11726 #define MIPI_INTR_STAT(port)		_MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
11727 #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
11728 #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
11729 #define MIPI_INTR_EN(port)		_MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
11730 #define  TEARING_EFFECT					(1 << 31)
11731 #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
11732 #define  GEN_READ_DATA_AVAIL				(1 << 29)
11733 #define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
11734 #define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
11735 #define  RX_PROT_VIOLATION				(1 << 26)
11736 #define  RX_INVALID_TX_LENGTH				(1 << 25)
11737 #define  ACK_WITH_NO_ERROR				(1 << 24)
11738 #define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
11739 #define  LP_RX_TIMEOUT					(1 << 22)
11740 #define  HS_TX_TIMEOUT					(1 << 21)
11741 #define  DPI_FIFO_UNDERRUN				(1 << 20)
11742 #define  LOW_CONTENTION					(1 << 19)
11743 #define  HIGH_CONTENTION				(1 << 18)
11744 #define  TXDSI_VC_ID_INVALID				(1 << 17)
11745 #define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
11746 #define  TXCHECKSUM_ERROR				(1 << 15)
11747 #define  TXECC_MULTIBIT_ERROR				(1 << 14)
11748 #define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
11749 #define  TXFALSE_CONTROL_ERROR				(1 << 12)
11750 #define  RXDSI_VC_ID_INVALID				(1 << 11)
11751 #define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
11752 #define  RXCHECKSUM_ERROR				(1 << 9)
11753 #define  RXECC_MULTIBIT_ERROR				(1 << 8)
11754 #define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
11755 #define  RXFALSE_CONTROL_ERROR				(1 << 6)
11756 #define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
11757 #define  RX_LP_TX_SYNC_ERROR				(1 << 4)
11758 #define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
11759 #define  RXEOT_SYNC_ERROR				(1 << 2)
11760 #define  RXSOT_SYNC_ERROR				(1 << 1)
11761 #define  RXSOT_ERROR					(1 << 0)
11762 
11763 #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
11764 #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
11765 #define MIPI_DSI_FUNC_PRG(port)		_MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
11766 #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
11767 #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
11768 #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
11769 #define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
11770 #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
11771 #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
11772 #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
11773 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
11774 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
11775 #define  VID_MODE_FORMAT_RGB565				(1 << 7)
11776 #define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
11777 #define  VID_MODE_FORMAT_RGB666				(3 << 7)
11778 #define  VID_MODE_FORMAT_RGB888				(4 << 7)
11779 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
11780 #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
11781 #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
11782 #define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
11783 #define  DATA_LANES_PRG_REG_SHIFT			0
11784 #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
11785 
11786 #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
11787 #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
11788 #define MIPI_HS_TX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
11789 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
11790 
11791 #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
11792 #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
11793 #define MIPI_LP_RX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
11794 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
11795 
11796 #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
11797 #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
11798 #define MIPI_TURN_AROUND_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
11799 #define  TURN_AROUND_TIMEOUT_MASK			0x3f
11800 
11801 #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
11802 #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
11803 #define MIPI_DEVICE_RESET_TIMER(port)	_MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
11804 #define  DEVICE_RESET_TIMER_MASK			0xffff
11805 
11806 #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
11807 #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
11808 #define MIPI_DPI_RESOLUTION(port)	_MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
11809 #define  VERTICAL_ADDRESS_SHIFT				16
11810 #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
11811 #define  HORIZONTAL_ADDRESS_SHIFT			0
11812 #define  HORIZONTAL_ADDRESS_MASK			0xffff
11813 
11814 #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
11815 #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
11816 #define MIPI_DBI_FIFO_THROTTLE(port)	_MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
11817 #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
11818 #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
11819 #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
11820 
11821 /* regs below are bits 15:0 */
11822 #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
11823 #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
11824 #define MIPI_HSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
11825 
11826 #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
11827 #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
11828 #define MIPI_HBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
11829 
11830 #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
11831 #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
11832 #define MIPI_HFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
11833 
11834 #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
11835 #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
11836 #define MIPI_HACTIVE_AREA_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
11837 
11838 #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
11839 #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
11840 #define MIPI_VSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
11841 
11842 #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
11843 #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
11844 #define MIPI_VBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
11845 
11846 #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
11847 #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
11848 #define MIPI_VFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
11849 
11850 #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
11851 #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
11852 #define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MMIO_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
11853 
11854 /* regs above are bits 15:0 */
11855 
11856 #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
11857 #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
11858 #define MIPI_DPI_CONTROL(port)		_MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
11859 #define  DPI_LP_MODE					(1 << 6)
11860 #define  BACKLIGHT_OFF					(1 << 5)
11861 #define  BACKLIGHT_ON					(1 << 4)
11862 #define  COLOR_MODE_OFF					(1 << 3)
11863 #define  COLOR_MODE_ON					(1 << 2)
11864 #define  TURN_ON					(1 << 1)
11865 #define  SHUTDOWN					(1 << 0)
11866 
11867 #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
11868 #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
11869 #define MIPI_DPI_DATA(port)		_MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
11870 #define  COMMAND_BYTE_SHIFT				0
11871 #define  COMMAND_BYTE_MASK				(0x3f << 0)
11872 
11873 #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
11874 #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
11875 #define MIPI_INIT_COUNT(port)		_MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
11876 #define  MASTER_INIT_TIMER_SHIFT			0
11877 #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
11878 
11879 #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
11880 #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
11881 #define MIPI_MAX_RETURN_PKT_SIZE(port)	_MMIO_MIPI(port, \
11882 			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
11883 #define  MAX_RETURN_PKT_SIZE_SHIFT			0
11884 #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
11885 
11886 #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
11887 #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
11888 #define MIPI_VIDEO_MODE_FORMAT(port)	_MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
11889 #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
11890 #define  DISABLE_VIDEO_BTA				(1 << 3)
11891 #define  IP_TG_CONFIG					(1 << 2)
11892 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
11893 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
11894 #define  VIDEO_MODE_BURST				(3 << 0)
11895 
11896 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
11897 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
11898 #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
11899 #define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
11900 #define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
11901 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
11902 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
11903 #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
11904 #define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
11905 #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
11906 #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
11907 #define  CLOCKSTOP					(1 << 1)
11908 #define  EOT_DISABLE					(1 << 0)
11909 
11910 #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
11911 #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
11912 #define MIPI_LP_BYTECLK(port)		_MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
11913 #define  LP_BYTECLK_SHIFT				0
11914 #define  LP_BYTECLK_MASK				(0xffff << 0)
11915 
11916 #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
11917 #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
11918 #define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
11919 
11920 #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
11921 #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
11922 #define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
11923 
11924 /* bits 31:0 */
11925 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
11926 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
11927 #define MIPI_LP_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
11928 
11929 /* bits 31:0 */
11930 #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
11931 #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
11932 #define MIPI_HS_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
11933 
11934 #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
11935 #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
11936 #define MIPI_LP_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
11937 #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
11938 #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
11939 #define MIPI_HS_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
11940 #define  LONG_PACKET_WORD_COUNT_SHIFT			8
11941 #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
11942 #define  SHORT_PACKET_PARAM_SHIFT			8
11943 #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
11944 #define  VIRTUAL_CHANNEL_SHIFT				6
11945 #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
11946 #define  DATA_TYPE_SHIFT				0
11947 #define  DATA_TYPE_MASK					(0x3f << 0)
11948 /* data type values, see include/video/mipi_display.h */
11949 
11950 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
11951 #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
11952 #define MIPI_GEN_FIFO_STAT(port)	_MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
11953 #define  DPI_FIFO_EMPTY					(1 << 28)
11954 #define  DBI_FIFO_EMPTY					(1 << 27)
11955 #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
11956 #define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
11957 #define  LP_CTRL_FIFO_FULL				(1 << 24)
11958 #define  HS_CTRL_FIFO_EMPTY				(1 << 18)
11959 #define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
11960 #define  HS_CTRL_FIFO_FULL				(1 << 16)
11961 #define  LP_DATA_FIFO_EMPTY				(1 << 10)
11962 #define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
11963 #define  LP_DATA_FIFO_FULL				(1 << 8)
11964 #define  HS_DATA_FIFO_EMPTY				(1 << 2)
11965 #define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
11966 #define  HS_DATA_FIFO_FULL				(1 << 0)
11967 
11968 #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
11969 #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
11970 #define MIPI_HS_LP_DBI_ENABLE(port)	_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
11971 #define  DBI_HS_LP_MODE_MASK				(1 << 0)
11972 #define  DBI_LP_MODE					(1 << 0)
11973 #define  DBI_HS_MODE					(0 << 0)
11974 
11975 #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
11976 #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
11977 #define MIPI_DPHY_PARAM(port)		_MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
11978 #define  EXIT_ZERO_COUNT_SHIFT				24
11979 #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
11980 #define  TRAIL_COUNT_SHIFT				16
11981 #define  TRAIL_COUNT_MASK				(0x1f << 16)
11982 #define  CLK_ZERO_COUNT_SHIFT				8
11983 #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
11984 #define  PREPARE_COUNT_SHIFT				0
11985 #define  PREPARE_COUNT_MASK				(0x3f << 0)
11986 
11987 #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
11988 #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
11989 #define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
11990 						   _ICL_DSI_T_INIT_MASTER_0,\
11991 						   _ICL_DSI_T_INIT_MASTER_1)
11992 
11993 #define _DPHY_CLK_TIMING_PARAM_0	0x162180
11994 #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
11995 #define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11996 						   _DPHY_CLK_TIMING_PARAM_0,\
11997 						   _DPHY_CLK_TIMING_PARAM_1)
11998 #define _DSI_CLK_TIMING_PARAM_0		0x6b080
11999 #define _DSI_CLK_TIMING_PARAM_1		0x6b880
12000 #define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
12001 						   _DSI_CLK_TIMING_PARAM_0,\
12002 						   _DSI_CLK_TIMING_PARAM_1)
12003 #define  CLK_PREPARE_OVERRIDE		(1 << 31)
12004 #define  CLK_PREPARE(x)		((x) << 28)
12005 #define  CLK_PREPARE_MASK		(0x7 << 28)
12006 #define  CLK_PREPARE_SHIFT		28
12007 #define  CLK_ZERO_OVERRIDE		(1 << 27)
12008 #define  CLK_ZERO(x)			((x) << 20)
12009 #define  CLK_ZERO_MASK			(0xf << 20)
12010 #define  CLK_ZERO_SHIFT		20
12011 #define  CLK_PRE_OVERRIDE		(1 << 19)
12012 #define  CLK_PRE(x)			((x) << 16)
12013 #define  CLK_PRE_MASK			(0x3 << 16)
12014 #define  CLK_PRE_SHIFT			16
12015 #define  CLK_POST_OVERRIDE		(1 << 15)
12016 #define  CLK_POST(x)			((x) << 8)
12017 #define  CLK_POST_MASK			(0x7 << 8)
12018 #define  CLK_POST_SHIFT		8
12019 #define  CLK_TRAIL_OVERRIDE		(1 << 7)
12020 #define  CLK_TRAIL(x)			((x) << 0)
12021 #define  CLK_TRAIL_MASK		(0xf << 0)
12022 #define  CLK_TRAIL_SHIFT		0
12023 
12024 #define _DPHY_DATA_TIMING_PARAM_0	0x162184
12025 #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
12026 #define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
12027 						   _DPHY_DATA_TIMING_PARAM_0,\
12028 						   _DPHY_DATA_TIMING_PARAM_1)
12029 #define _DSI_DATA_TIMING_PARAM_0	0x6B084
12030 #define _DSI_DATA_TIMING_PARAM_1	0x6B884
12031 #define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
12032 						   _DSI_DATA_TIMING_PARAM_0,\
12033 						   _DSI_DATA_TIMING_PARAM_1)
12034 #define  HS_PREPARE_OVERRIDE		(1 << 31)
12035 #define  HS_PREPARE(x)			((x) << 24)
12036 #define  HS_PREPARE_MASK		(0x7 << 24)
12037 #define  HS_PREPARE_SHIFT		24
12038 #define  HS_ZERO_OVERRIDE		(1 << 23)
12039 #define  HS_ZERO(x)			((x) << 16)
12040 #define  HS_ZERO_MASK			(0xf << 16)
12041 #define  HS_ZERO_SHIFT			16
12042 #define  HS_TRAIL_OVERRIDE		(1 << 15)
12043 #define  HS_TRAIL(x)			((x) << 8)
12044 #define  HS_TRAIL_MASK			(0x7 << 8)
12045 #define  HS_TRAIL_SHIFT		8
12046 #define  HS_EXIT_OVERRIDE		(1 << 7)
12047 #define  HS_EXIT(x)			((x) << 0)
12048 #define  HS_EXIT_MASK			(0x7 << 0)
12049 #define  HS_EXIT_SHIFT			0
12050 
12051 #define _DPHY_TA_TIMING_PARAM_0		0x162188
12052 #define _DPHY_TA_TIMING_PARAM_1		0x6c188
12053 #define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
12054 						   _DPHY_TA_TIMING_PARAM_0,\
12055 						   _DPHY_TA_TIMING_PARAM_1)
12056 #define _DSI_TA_TIMING_PARAM_0		0x6b098
12057 #define _DSI_TA_TIMING_PARAM_1		0x6b898
12058 #define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
12059 						   _DSI_TA_TIMING_PARAM_0,\
12060 						   _DSI_TA_TIMING_PARAM_1)
12061 #define  TA_SURE_OVERRIDE		(1 << 31)
12062 #define  TA_SURE(x)			((x) << 16)
12063 #define  TA_SURE_MASK			(0x1f << 16)
12064 #define  TA_SURE_SHIFT			16
12065 #define  TA_GO_OVERRIDE		(1 << 15)
12066 #define  TA_GO(x)			((x) << 8)
12067 #define  TA_GO_MASK			(0xf << 8)
12068 #define  TA_GO_SHIFT			8
12069 #define  TA_GET_OVERRIDE		(1 << 7)
12070 #define  TA_GET(x)			((x) << 0)
12071 #define  TA_GET_MASK			(0xf << 0)
12072 #define  TA_GET_SHIFT			0
12073 
12074 /* DSI transcoder configuration */
12075 #define _DSI_TRANS_FUNC_CONF_0		0x6b030
12076 #define _DSI_TRANS_FUNC_CONF_1		0x6b830
12077 #define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
12078 						  _DSI_TRANS_FUNC_CONF_0,\
12079 						  _DSI_TRANS_FUNC_CONF_1)
12080 #define  OP_MODE_MASK			(0x3 << 28)
12081 #define  OP_MODE_SHIFT			28
12082 #define  CMD_MODE_NO_GATE		(0x0 << 28)
12083 #define  CMD_MODE_TE_GATE		(0x1 << 28)
12084 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
12085 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
12086 #define  TE_SOURCE_GPIO			(1 << 27)
12087 #define  LINK_READY			(1 << 20)
12088 #define  PIX_FMT_MASK			(0x3 << 16)
12089 #define  PIX_FMT_SHIFT			16
12090 #define  PIX_FMT_RGB565			(0x0 << 16)
12091 #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
12092 #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
12093 #define  PIX_FMT_RGB888			(0x3 << 16)
12094 #define  PIX_FMT_RGB101010		(0x4 << 16)
12095 #define  PIX_FMT_RGB121212		(0x5 << 16)
12096 #define  PIX_FMT_COMPRESSED		(0x6 << 16)
12097 #define  BGR_TRANSMISSION		(1 << 15)
12098 #define  PIX_VIRT_CHAN(x)		((x) << 12)
12099 #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
12100 #define  PIX_VIRT_CHAN_SHIFT		12
12101 #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
12102 #define  PIX_BUF_THRESHOLD_SHIFT	10
12103 #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
12104 #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
12105 #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
12106 #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
12107 #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
12108 #define  CONTINUOUS_CLK_SHIFT		8
12109 #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
12110 #define  CLK_HS_OR_LP			(0x2 << 8)
12111 #define  CLK_HS_CONTINUOUS		(0x3 << 8)
12112 #define  LINK_CALIBRATION_MASK		(0x3 << 4)
12113 #define  LINK_CALIBRATION_SHIFT		4
12114 #define  CALIBRATION_DISABLED		(0x0 << 4)
12115 #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
12116 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
12117 #define  BLANKING_PACKET_ENABLE		(1 << 2)
12118 #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
12119 #define  EOTP_DISABLED			(1 << 0)
12120 
12121 #define _DSI_CMD_RXCTL_0		0x6b0d4
12122 #define _DSI_CMD_RXCTL_1		0x6b8d4
12123 #define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
12124 						  _DSI_CMD_RXCTL_0,\
12125 						  _DSI_CMD_RXCTL_1)
12126 #define  READ_UNLOADS_DW		(1 << 16)
12127 #define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
12128 #define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
12129 #define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
12130 #define  RECEIVED_RESET_TRIGGER		(1 << 12)
12131 #define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
12132 #define  RECEIVED_CRC_WAS_LOST		(1 << 10)
12133 #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
12134 #define  NUMBER_RX_PLOAD_DW_SHIFT	0
12135 
12136 #define _DSI_CMD_TXCTL_0		0x6b0d0
12137 #define _DSI_CMD_TXCTL_1		0x6b8d0
12138 #define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
12139 						  _DSI_CMD_TXCTL_0,\
12140 						  _DSI_CMD_TXCTL_1)
12141 #define  KEEP_LINK_IN_HS		(1 << 24)
12142 #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
12143 #define  FREE_HEADER_CREDIT_SHIFT	0x8
12144 #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
12145 #define  FREE_PLOAD_CREDIT_SHIFT	0
12146 #define  MAX_HEADER_CREDIT		0x10
12147 #define  MAX_PLOAD_CREDIT		0x40
12148 
12149 #define _DSI_CMD_TXHDR_0		0x6b100
12150 #define _DSI_CMD_TXHDR_1		0x6b900
12151 #define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
12152 						  _DSI_CMD_TXHDR_0,\
12153 						  _DSI_CMD_TXHDR_1)
12154 #define  PAYLOAD_PRESENT		(1 << 31)
12155 #define  LP_DATA_TRANSFER		(1 << 30)
12156 #define  VBLANK_FENCE			(1 << 29)
12157 #define  PARAM_WC_MASK			(0xffff << 8)
12158 #define  PARAM_WC_LOWER_SHIFT		8
12159 #define  PARAM_WC_UPPER_SHIFT		16
12160 #define  VC_MASK			(0x3 << 6)
12161 #define  VC_SHIFT			6
12162 #define  DT_MASK			(0x3f << 0)
12163 #define  DT_SHIFT			0
12164 
12165 #define _DSI_CMD_TXPYLD_0		0x6b104
12166 #define _DSI_CMD_TXPYLD_1		0x6b904
12167 #define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
12168 						  _DSI_CMD_TXPYLD_0,\
12169 						  _DSI_CMD_TXPYLD_1)
12170 
12171 #define _DSI_LP_MSG_0			0x6b0d8
12172 #define _DSI_LP_MSG_1			0x6b8d8
12173 #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
12174 						  _DSI_LP_MSG_0,\
12175 						  _DSI_LP_MSG_1)
12176 #define  LPTX_IN_PROGRESS		(1 << 17)
12177 #define  LINK_IN_ULPS			(1 << 16)
12178 #define  LINK_ULPS_TYPE_LP11		(1 << 8)
12179 #define  LINK_ENTER_ULPS		(1 << 0)
12180 
12181 /* DSI timeout registers */
12182 #define _DSI_HSTX_TO_0			0x6b044
12183 #define _DSI_HSTX_TO_1			0x6b844
12184 #define DSI_HSTX_TO(tc)			_MMIO_DSI(tc,	\
12185 						  _DSI_HSTX_TO_0,\
12186 						  _DSI_HSTX_TO_1)
12187 #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
12188 #define  HSTX_TIMEOUT_VALUE_SHIFT	16
12189 #define  HSTX_TIMEOUT_VALUE(x)		((x) << 16)
12190 #define  HSTX_TIMED_OUT			(1 << 0)
12191 
12192 #define _DSI_LPRX_HOST_TO_0		0x6b048
12193 #define _DSI_LPRX_HOST_TO_1		0x6b848
12194 #define DSI_LPRX_HOST_TO(tc)		_MMIO_DSI(tc,	\
12195 						  _DSI_LPRX_HOST_TO_0,\
12196 						  _DSI_LPRX_HOST_TO_1)
12197 #define  LPRX_TIMED_OUT			(1 << 16)
12198 #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
12199 #define  LPRX_TIMEOUT_VALUE_SHIFT	0
12200 #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
12201 
12202 #define _DSI_PWAIT_TO_0			0x6b040
12203 #define _DSI_PWAIT_TO_1			0x6b840
12204 #define DSI_PWAIT_TO(tc)		_MMIO_DSI(tc,	\
12205 						  _DSI_PWAIT_TO_0,\
12206 						  _DSI_PWAIT_TO_1)
12207 #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
12208 #define  PRESET_TIMEOUT_VALUE_SHIFT	16
12209 #define  PRESET_TIMEOUT_VALUE(x)	((x) << 16)
12210 #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
12211 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
12212 #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
12213 
12214 #define _DSI_TA_TO_0			0x6b04c
12215 #define _DSI_TA_TO_1			0x6b84c
12216 #define DSI_TA_TO(tc)			_MMIO_DSI(tc,	\
12217 						  _DSI_TA_TO_0,\
12218 						  _DSI_TA_TO_1)
12219 #define  TA_TIMED_OUT			(1 << 16)
12220 #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
12221 #define  TA_TIMEOUT_VALUE_SHIFT		0
12222 #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
12223 
12224 /* bits 31:0 */
12225 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
12226 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
12227 #define MIPI_DBI_BW_CTRL(port)		_MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
12228 
12229 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
12230 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
12231 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
12232 #define  LP_HS_SSW_CNT_SHIFT				16
12233 #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
12234 #define  HS_LP_PWR_SW_CNT_SHIFT				0
12235 #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
12236 
12237 #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
12238 #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
12239 #define MIPI_STOP_STATE_STALL(port)	_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
12240 #define  STOP_STATE_STALL_COUNTER_SHIFT			0
12241 #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
12242 
12243 #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
12244 #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
12245 #define MIPI_INTR_STAT_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
12246 #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
12247 #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
12248 #define MIPI_INTR_EN_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
12249 #define  RX_CONTENTION_DETECTED				(1 << 0)
12250 
12251 /* XXX: only pipe A ?!? */
12252 #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
12253 #define  DBI_TYPEC_ENABLE				(1 << 31)
12254 #define  DBI_TYPEC_WIP					(1 << 30)
12255 #define  DBI_TYPEC_OPTION_SHIFT				28
12256 #define  DBI_TYPEC_OPTION_MASK				(3 << 28)
12257 #define  DBI_TYPEC_FREQ_SHIFT				24
12258 #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
12259 #define  DBI_TYPEC_OVERRIDE				(1 << 8)
12260 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
12261 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
12262 
12263 
12264 /* MIPI adapter registers */
12265 
12266 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
12267 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
12268 #define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
12269 #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
12270 #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
12271 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
12272 #define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
12273 #define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
12274 #define  READ_REQUEST_PRIORITY_SHIFT			3
12275 #define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
12276 #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
12277 #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
12278 #define  RGB_FLIP_TO_BGR				(1 << 2)
12279 
12280 #define  BXT_PIPE_SELECT_SHIFT				7
12281 #define  BXT_PIPE_SELECT_MASK				(7 << 7)
12282 #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
12283 #define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
12284 #define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
12285 #define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
12286 #define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
12287 #define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
12288 #define  GLK_LP_WAKE					(1 << 22)
12289 #define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
12290 #define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
12291 #define  GLK_FIREWALL_ENABLE				(1 << 16)
12292 #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
12293 #define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
12294 #define  BXT_DSC_ENABLE					(1 << 3)
12295 #define  BXT_RGB_FLIP					(1 << 2)
12296 #define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
12297 #define  GLK_MIPIIO_ENABLE				(1 << 0)
12298 
12299 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
12300 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
12301 #define MIPI_DATA_ADDRESS(port)		_MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
12302 #define  DATA_MEM_ADDRESS_SHIFT				5
12303 #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
12304 #define  DATA_VALID					(1 << 0)
12305 
12306 #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
12307 #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
12308 #define MIPI_DATA_LENGTH(port)		_MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
12309 #define  DATA_LENGTH_SHIFT				0
12310 #define  DATA_LENGTH_MASK				(0xfffff << 0)
12311 
12312 #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
12313 #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
12314 #define MIPI_COMMAND_ADDRESS(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
12315 #define  COMMAND_MEM_ADDRESS_SHIFT			5
12316 #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
12317 #define  AUTO_PWG_ENABLE				(1 << 2)
12318 #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
12319 #define  COMMAND_VALID					(1 << 0)
12320 
12321 #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
12322 #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
12323 #define MIPI_COMMAND_LENGTH(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
12324 #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
12325 #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
12326 
12327 #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
12328 #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
12329 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
12330 
12331 #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
12332 #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
12333 #define MIPI_READ_DATA_VALID(port)	_MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
12334 #define  READ_DATA_VALID(n)				(1 << (n))
12335 
12336 /* MOCS (Memory Object Control State) registers */
12337 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
12338 #define GEN9_LNCFCMOCS_REG_COUNT	32
12339 
12340 #define __GEN9_RCS0_MOCS0	0xc800
12341 #define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
12342 #define __GEN9_VCS0_MOCS0	0xc900
12343 #define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
12344 #define __GEN9_VCS1_MOCS0	0xca00
12345 #define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
12346 #define __GEN9_VECS0_MOCS0	0xcb00
12347 #define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
12348 #define __GEN9_BCS0_MOCS0	0xcc00
12349 #define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
12350 #define __GEN11_VCS2_MOCS0	0x10000
12351 #define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
12352 
12353 #define GEN9_SCRATCH_LNCF1		_MMIO(0xb008)
12354 #define   GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0)
12355 
12356 #define GEN9_SCRATCH1			_MMIO(0xb11c)
12357 #define   EVICTION_PERF_FIX_ENABLE	REG_BIT(8)
12358 
12359 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
12360 #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
12361 #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
12362 #define   PMFLUSHDONE_LNEBLK		(1 << 22)
12363 
12364 #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
12365 
12366 #define GEN12_GSMBASE			_MMIO(0x108100)
12367 #define GEN12_DSMBASE			_MMIO(0x1080C0)
12368 
12369 /* gamt regs */
12370 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
12371 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
12372 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
12373 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
12374 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
12375 
12376 #define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
12377 #define  MMCD_PCLA		(1 << 31)
12378 #define  MMCD_HOTSPOT_EN	(1 << 27)
12379 
12380 #define _ICL_PHY_MISC_A		0x64C00
12381 #define _ICL_PHY_MISC_B		0x64C04
12382 #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
12383 						 _ICL_PHY_MISC_B)
12384 #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
12385 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
12386 #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
12387 
12388 /* Icelake Display Stream Compression Registers */
12389 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
12390 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
12391 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
12392 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
12393 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
12394 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
12395 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12396 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
12397 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
12398 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12399 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
12400 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
12401 #define  DSC_VBR_ENABLE			(1 << 19)
12402 #define  DSC_422_ENABLE			(1 << 18)
12403 #define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
12404 #define  DSC_BLOCK_PREDICTION		(1 << 16)
12405 #define  DSC_LINE_BUF_DEPTH_SHIFT	12
12406 #define  DSC_BPC_SHIFT			8
12407 #define  DSC_VER_MIN_SHIFT		4
12408 #define  DSC_VER_MAJ			(0x1 << 0)
12409 
12410 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
12411 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
12412 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
12413 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
12414 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
12415 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
12416 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12417 							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
12418 							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
12419 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12420 							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
12421 							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
12422 #define  DSC_BPP(bpp)				((bpp) << 0)
12423 
12424 #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
12425 #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
12426 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
12427 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
12428 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
12429 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
12430 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12431 							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
12432 							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
12433 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12434 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
12435 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
12436 #define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
12437 #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
12438 
12439 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
12440 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
12441 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
12442 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
12443 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
12444 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
12445 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12446 							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
12447 							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
12448 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12449 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
12450 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
12451 #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
12452 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
12453 
12454 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
12455 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
12456 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
12457 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
12458 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
12459 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
12460 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12461 							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
12462 							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
12463 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12464 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
12465 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
12466 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
12467 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
12468 
12469 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
12470 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
12471 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
12472 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
12473 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
12474 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
12475 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12476 							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
12477 							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
12478 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12479 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
12480 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
12481 #define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
12482 #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
12483 
12484 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
12485 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
12486 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
12487 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
12488 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
12489 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
12490 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12491 							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
12492 							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
12493 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12494 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
12495 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
12496 #define  DSC_FLATNESS_MAX_QP(max_qp)		((max_qp) << 24)
12497 #define  DSC_FLATNESS_MIN_QP(min_qp)		((min_qp) << 16)
12498 #define  DSC_FIRST_LINE_BPG_OFFSET(offset)	((offset) << 8)
12499 #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
12500 
12501 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
12502 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
12503 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
12504 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
12505 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
12506 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
12507 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12508 							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
12509 							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
12510 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12511 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
12512 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
12513 #define  DSC_NFL_BPG_OFFSET(bpg_offset)		((bpg_offset) << 16)
12514 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
12515 
12516 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
12517 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
12518 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
12519 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
12520 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
12521 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
12522 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12523 							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
12524 							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
12525 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12526 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
12527 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
12528 #define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
12529 #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
12530 
12531 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
12532 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
12533 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
12534 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
12535 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
12536 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
12537 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12538 							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
12539 							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
12540 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12541 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
12542 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
12543 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	((rc_edge_fact) << 16)
12544 #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
12545 
12546 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
12547 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
12548 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
12549 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
12550 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
12551 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
12552 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12553 							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
12554 							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
12555 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12556 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
12557 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
12558 #define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		((rc_tgt_off_low) << 20)
12559 #define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	((rc_tgt_off_high) << 16)
12560 #define  DSC_RC_QUANT_INC_LIMIT1(lim)			((lim) << 8)
12561 #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
12562 
12563 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
12564 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
12565 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
12566 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
12567 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
12568 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
12569 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12570 							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
12571 							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
12572 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12573 							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
12574 							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
12575 
12576 #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
12577 #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
12578 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
12579 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
12580 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
12581 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
12582 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12583 							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
12584 							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
12585 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12586 							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
12587 							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
12588 
12589 #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
12590 #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
12591 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
12592 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
12593 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
12594 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
12595 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12596 							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
12597 							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
12598 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12599 							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
12600 							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
12601 
12602 #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
12603 #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
12604 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
12605 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
12606 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
12607 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
12608 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12609 							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
12610 							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
12611 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12612 							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
12613 							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
12614 
12615 #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
12616 #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
12617 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
12618 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
12619 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
12620 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
12621 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12622 							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
12623 							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
12624 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12625 							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
12626 							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
12627 
12628 #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
12629 #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
12630 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
12631 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
12632 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
12633 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
12634 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12635 							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
12636 							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
12637 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12638 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
12639 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
12640 #define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
12641 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
12642 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
12643 
12644 /* Icelake Rate Control Buffer Threshold Registers */
12645 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
12646 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
12647 #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
12648 #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
12649 #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
12650 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
12651 #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
12652 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
12653 #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
12654 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
12655 #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
12656 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
12657 #define ICL_DSC0_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12658 						_ICL_DSC0_RC_BUF_THRESH_0_PB, \
12659 						_ICL_DSC0_RC_BUF_THRESH_0_PC)
12660 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12661 						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
12662 						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
12663 #define ICL_DSC1_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12664 						_ICL_DSC1_RC_BUF_THRESH_0_PB, \
12665 						_ICL_DSC1_RC_BUF_THRESH_0_PC)
12666 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12667 						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
12668 						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
12669 
12670 #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
12671 #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
12672 #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
12673 #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
12674 #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
12675 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
12676 #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
12677 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
12678 #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
12679 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
12680 #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
12681 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
12682 #define ICL_DSC0_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12683 						_ICL_DSC0_RC_BUF_THRESH_1_PB, \
12684 						_ICL_DSC0_RC_BUF_THRESH_1_PC)
12685 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12686 						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
12687 						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
12688 #define ICL_DSC1_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12689 						_ICL_DSC1_RC_BUF_THRESH_1_PB, \
12690 						_ICL_DSC1_RC_BUF_THRESH_1_PC)
12691 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12692 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
12693 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
12694 
12695 #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
12696 #define   MODULAR_FIA_MASK			(1 << 4)
12697 #define   TC_LIVE_STATE_TBT(idx)		(1 << ((idx) * 8 + 6))
12698 #define   TC_LIVE_STATE_TC(idx)			(1 << ((idx) * 8 + 5))
12699 #define   DP_LANE_ASSIGNMENT_SHIFT(idx)		((idx) * 8)
12700 #define   DP_LANE_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 8))
12701 #define   DP_LANE_ASSIGNMENT(idx, x)		((x) << ((idx) * 8))
12702 
12703 #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
12704 #define   DP_PHY_MODE_STATUS_COMPLETED(idx)	(1 << (idx))
12705 
12706 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
12707 #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)	(1 << (idx))
12708 
12709 #define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
12710 #define   DP_PIN_ASSIGNMENT_SHIFT(idx)		((idx) * 4)
12711 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
12712 #define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
12713 
12714 #define _TCSS_DDI_STATUS_1			0x161500
12715 #define _TCSS_DDI_STATUS_2			0x161504
12716 #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
12717 								 _TCSS_DDI_STATUS_1, \
12718 								 _TCSS_DDI_STATUS_2))
12719 #define  TCSS_DDI_STATUS_READY			REG_BIT(2)
12720 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
12721 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
12722 
12723 /* This register controls the Display State Buffer (DSB) engines. */
12724 #define _DSBSL_INSTANCE_BASE		0x70B00
12725 #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
12726 					 (pipe) * 0x1000 + (id) * 0x100)
12727 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
12728 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
12729 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
12730 #define   DSB_ENABLE			(1 << 31)
12731 #define   DSB_STATUS			(1 << 0)
12732 
12733 #define TGL_ROOT_DEVICE_ID		0x9A00
12734 #define TGL_ROOT_DEVICE_MASK		0xFF00
12735 #define TGL_ROOT_DEVICE_SKU_MASK	0xF
12736 #define TGL_ROOT_DEVICE_SKU_ULX		0x2
12737 #define TGL_ROOT_DEVICE_SKU_ULT		0x4
12738 
12739 #define CLKREQ_POLICY			_MMIO(0x101038)
12740 #define  CLKREQ_POLICY_MEM_UP_OVRD	REG_BIT(1)
12741 
12742 #endif /* _I915_REG_H_ */
12743