1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 /* 29 * The Bridge device's PCI config space has information about the 30 * fb aperture size and the amount of pre-reserved memory. 31 */ 32 #define INTEL_GMCH_CTRL 0x52 33 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 34 #define INTEL_GMCH_ENABLED 0x4 35 #define INTEL_GMCH_MEM_MASK 0x1 36 #define INTEL_GMCH_MEM_64M 0x1 37 #define INTEL_GMCH_MEM_128M 0 38 39 #define INTEL_GMCH_GMS_MASK (0xf << 4) 40 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 41 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 42 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 43 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 44 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 45 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 46 47 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 48 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 49 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) 50 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) 51 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 52 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 53 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 54 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 55 56 /* PCI config space */ 57 58 #define HPLLCC 0xc0 /* 855 only */ 59 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 60 #define GC_CLOCK_133_200 (0 << 0) 61 #define GC_CLOCK_100_200 (1 << 0) 62 #define GC_CLOCK_100_133 (2 << 0) 63 #define GC_CLOCK_166_250 (3 << 0) 64 #define GCFGC 0xf0 /* 915+ only */ 65 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 66 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 67 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 68 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 69 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 70 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 71 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 72 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 73 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 74 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 75 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 76 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 77 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 78 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 79 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 80 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 81 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 82 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 83 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 84 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 85 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 86 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 87 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 88 #define LBB 0xf4 89 #define GDRST 0xc0 90 #define GDRST_FULL (0<<2) 91 #define GDRST_RENDER (1<<2) 92 #define GDRST_MEDIA (3<<2) 93 94 /* VGA stuff */ 95 96 #define VGA_ST01_MDA 0x3ba 97 #define VGA_ST01_CGA 0x3da 98 99 #define VGA_MSR_WRITE 0x3c2 100 #define VGA_MSR_READ 0x3cc 101 #define VGA_MSR_MEM_EN (1<<1) 102 #define VGA_MSR_CGA_MODE (1<<0) 103 104 #define VGA_SR_INDEX 0x3c4 105 #define VGA_SR_DATA 0x3c5 106 107 #define VGA_AR_INDEX 0x3c0 108 #define VGA_AR_VID_EN (1<<5) 109 #define VGA_AR_DATA_WRITE 0x3c0 110 #define VGA_AR_DATA_READ 0x3c1 111 112 #define VGA_GR_INDEX 0x3ce 113 #define VGA_GR_DATA 0x3cf 114 /* GR05 */ 115 #define VGA_GR_MEM_READ_MODE_SHIFT 3 116 #define VGA_GR_MEM_READ_MODE_PLANE 1 117 /* GR06 */ 118 #define VGA_GR_MEM_MODE_MASK 0xc 119 #define VGA_GR_MEM_MODE_SHIFT 2 120 #define VGA_GR_MEM_A0000_AFFFF 0 121 #define VGA_GR_MEM_A0000_BFFFF 1 122 #define VGA_GR_MEM_B0000_B7FFF 2 123 #define VGA_GR_MEM_B0000_BFFFF 3 124 125 #define VGA_DACMASK 0x3c6 126 #define VGA_DACRX 0x3c7 127 #define VGA_DACWX 0x3c8 128 #define VGA_DACDATA 0x3c9 129 130 #define VGA_CR_INDEX_MDA 0x3b4 131 #define VGA_CR_DATA_MDA 0x3b5 132 #define VGA_CR_INDEX_CGA 0x3d4 133 #define VGA_CR_DATA_CGA 0x3d5 134 135 /* 136 * Memory interface instructions used by the kernel 137 */ 138 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 139 140 #define MI_NOOP MI_INSTR(0, 0) 141 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 142 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 143 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 144 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 145 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 146 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 147 #define MI_FLUSH MI_INSTR(0x04, 0) 148 #define MI_READ_FLUSH (1 << 0) 149 #define MI_EXE_FLUSH (1 << 1) 150 #define MI_NO_WRITE_FLUSH (1 << 2) 151 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 152 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 153 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 154 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 155 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 156 #define MI_OVERLAY_CONTINUE (0x0<<21) 157 #define MI_OVERLAY_ON (0x1<<21) 158 #define MI_OVERLAY_OFF (0x2<<21) 159 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 160 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 161 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 162 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 163 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 164 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 165 #define MI_STORE_DWORD_INDEX_SHIFT 2 166 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 167 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 168 #define MI_BATCH_NON_SECURE (1) 169 #define MI_BATCH_NON_SECURE_I965 (1<<8) 170 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 171 172 /* 173 * 3D instructions used by the kernel 174 */ 175 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 176 177 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 178 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 179 #define SC_UPDATE_SCISSOR (0x1<<1) 180 #define SC_ENABLE_MASK (0x1<<0) 181 #define SC_ENABLE (0x1<<0) 182 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 183 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 184 #define SCI_YMIN_MASK (0xffff<<16) 185 #define SCI_XMIN_MASK (0xffff<<0) 186 #define SCI_YMAX_MASK (0xffff<<16) 187 #define SCI_XMAX_MASK (0xffff<<0) 188 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 189 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 190 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 191 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 192 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 193 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 194 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 195 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 196 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 197 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 198 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 199 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 200 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 201 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 202 #define BLT_DEPTH_8 (0<<24) 203 #define BLT_DEPTH_16_565 (1<<24) 204 #define BLT_DEPTH_16_1555 (2<<24) 205 #define BLT_DEPTH_32 (3<<24) 206 #define BLT_ROP_GXCOPY (0xcc<<16) 207 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 208 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 209 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 210 #define ASYNC_FLIP (1<<22) 211 #define DISPLAY_PLANE_A (0<<20) 212 #define DISPLAY_PLANE_B (1<<20) 213 214 /* 215 * Fence registers 216 */ 217 #define FENCE_REG_830_0 0x2000 218 #define FENCE_REG_945_8 0x3000 219 #define I830_FENCE_START_MASK 0x07f80000 220 #define I830_FENCE_TILING_Y_SHIFT 12 221 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 222 #define I830_FENCE_PITCH_SHIFT 4 223 #define I830_FENCE_REG_VALID (1<<0) 224 #define I915_FENCE_MAX_PITCH_VAL 0x10 225 #define I830_FENCE_MAX_PITCH_VAL 6 226 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 227 228 #define I915_FENCE_START_MASK 0x0ff00000 229 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 230 231 #define FENCE_REG_965_0 0x03000 232 #define I965_FENCE_PITCH_SHIFT 2 233 #define I965_FENCE_TILING_Y_SHIFT 1 234 #define I965_FENCE_REG_VALID (1<<0) 235 #define I965_FENCE_MAX_PITCH_VAL 0x0400 236 237 /* 238 * Instruction and interrupt control regs 239 */ 240 #define PGTBL_ER 0x02024 241 #define PRB0_TAIL 0x02030 242 #define PRB0_HEAD 0x02034 243 #define PRB0_START 0x02038 244 #define PRB0_CTL 0x0203c 245 #define TAIL_ADDR 0x001FFFF8 246 #define HEAD_WRAP_COUNT 0xFFE00000 247 #define HEAD_WRAP_ONE 0x00200000 248 #define HEAD_ADDR 0x001FFFFC 249 #define RING_NR_PAGES 0x001FF000 250 #define RING_REPORT_MASK 0x00000006 251 #define RING_REPORT_64K 0x00000002 252 #define RING_REPORT_128K 0x00000004 253 #define RING_NO_REPORT 0x00000000 254 #define RING_VALID_MASK 0x00000001 255 #define RING_VALID 0x00000001 256 #define RING_INVALID 0x00000000 257 #define PRB1_TAIL 0x02040 /* 915+ only */ 258 #define PRB1_HEAD 0x02044 /* 915+ only */ 259 #define PRB1_START 0x02048 /* 915+ only */ 260 #define PRB1_CTL 0x0204c /* 915+ only */ 261 #define IPEIR_I965 0x02064 262 #define IPEHR_I965 0x02068 263 #define INSTDONE_I965 0x0206c 264 #define INSTPS 0x02070 /* 965+ only */ 265 #define INSTDONE1 0x0207c /* 965+ only */ 266 #define ACTHD_I965 0x02074 267 #define HWS_PGA 0x02080 268 #define HWS_ADDRESS_MASK 0xfffff000 269 #define HWS_START_ADDRESS_SHIFT 4 270 #define PWRCTXA 0x2088 /* 965GM+ only */ 271 #define PWRCTX_EN (1<<0) 272 #define IPEIR 0x02088 273 #define IPEHR 0x0208c 274 #define INSTDONE 0x02090 275 #define NOPID 0x02094 276 #define HWSTAM 0x02098 277 #define SCPD0 0x0209c /* 915+ only */ 278 #define IER 0x020a0 279 #define IIR 0x020a4 280 #define IMR 0x020a8 281 #define ISR 0x020ac 282 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 283 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 284 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 285 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 286 #define I915_HWB_OOM_INTERRUPT (1<<13) 287 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 288 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 289 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 290 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 291 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 292 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 293 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 294 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 295 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 296 #define I915_DEBUG_INTERRUPT (1<<2) 297 #define I915_USER_INTERRUPT (1<<1) 298 #define I915_ASLE_INTERRUPT (1<<0) 299 #define EIR 0x020b0 300 #define EMR 0x020b4 301 #define ESR 0x020b8 302 #define GM45_ERROR_PAGE_TABLE (1<<5) 303 #define GM45_ERROR_MEM_PRIV (1<<4) 304 #define I915_ERROR_PAGE_TABLE (1<<4) 305 #define GM45_ERROR_CP_PRIV (1<<3) 306 #define I915_ERROR_MEMORY_REFRESH (1<<1) 307 #define I915_ERROR_INSTRUCTION (1<<0) 308 #define INSTPM 0x020c0 309 #define ACTHD 0x020c8 310 #define FW_BLC 0x020d8 311 #define FW_BLC2 0x020dc 312 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 313 #define FW_BLC_SELF_EN (1<<15) 314 #define MM_BURST_LENGTH 0x00700000 315 #define MM_FIFO_WATERMARK 0x0001F000 316 #define LM_BURST_LENGTH 0x00000700 317 #define LM_FIFO_WATERMARK 0x0000001F 318 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 319 #define CACHE_MODE_0 0x02120 /* 915+ only */ 320 #define CM0_MASK_SHIFT 16 321 #define CM0_IZ_OPT_DISABLE (1<<6) 322 #define CM0_ZR_OPT_DISABLE (1<<5) 323 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 324 #define CM0_COLOR_EVICT_DISABLE (1<<3) 325 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 326 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 327 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 328 329 330 /* 331 * Framebuffer compression (915+ only) 332 */ 333 334 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 335 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 336 #define FBC_CONTROL 0x03208 337 #define FBC_CTL_EN (1<<31) 338 #define FBC_CTL_PERIODIC (1<<30) 339 #define FBC_CTL_INTERVAL_SHIFT (16) 340 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 341 #define FBC_C3_IDLE (1<<13) 342 #define FBC_CTL_STRIDE_SHIFT (5) 343 #define FBC_CTL_FENCENO (1<<0) 344 #define FBC_COMMAND 0x0320c 345 #define FBC_CMD_COMPRESS (1<<0) 346 #define FBC_STATUS 0x03210 347 #define FBC_STAT_COMPRESSING (1<<31) 348 #define FBC_STAT_COMPRESSED (1<<30) 349 #define FBC_STAT_MODIFIED (1<<29) 350 #define FBC_STAT_CURRENT_LINE (1<<0) 351 #define FBC_CONTROL2 0x03214 352 #define FBC_CTL_FENCE_DBL (0<<4) 353 #define FBC_CTL_IDLE_IMM (0<<2) 354 #define FBC_CTL_IDLE_FULL (1<<2) 355 #define FBC_CTL_IDLE_LINE (2<<2) 356 #define FBC_CTL_IDLE_DEBUG (3<<2) 357 #define FBC_CTL_CPU_FENCE (1<<1) 358 #define FBC_CTL_PLANEA (0<<0) 359 #define FBC_CTL_PLANEB (1<<0) 360 #define FBC_FENCE_OFF 0x0321b 361 #define FBC_TAG 0x03300 362 363 #define FBC_LL_SIZE (1536) 364 365 /* Framebuffer compression for GM45+ */ 366 #define DPFC_CB_BASE 0x3200 367 #define DPFC_CONTROL 0x3208 368 #define DPFC_CTL_EN (1<<31) 369 #define DPFC_CTL_PLANEA (0<<30) 370 #define DPFC_CTL_PLANEB (1<<30) 371 #define DPFC_CTL_FENCE_EN (1<<29) 372 #define DPFC_SR_EN (1<<10) 373 #define DPFC_CTL_LIMIT_1X (0<<6) 374 #define DPFC_CTL_LIMIT_2X (1<<6) 375 #define DPFC_CTL_LIMIT_4X (2<<6) 376 #define DPFC_RECOMP_CTL 0x320c 377 #define DPFC_RECOMP_STALL_EN (1<<27) 378 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 379 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 380 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 381 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 382 #define DPFC_STATUS 0x3210 383 #define DPFC_INVAL_SEG_SHIFT (16) 384 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 385 #define DPFC_COMP_SEG_SHIFT (0) 386 #define DPFC_COMP_SEG_MASK (0x000003ff) 387 #define DPFC_STATUS2 0x3214 388 #define DPFC_FENCE_YOFF 0x3218 389 #define DPFC_CHICKEN 0x3224 390 #define DPFC_HT_MODIFY (1<<31) 391 392 /* 393 * GPIO regs 394 */ 395 #define GPIOA 0x5010 396 #define GPIOB 0x5014 397 #define GPIOC 0x5018 398 #define GPIOD 0x501c 399 #define GPIOE 0x5020 400 #define GPIOF 0x5024 401 #define GPIOG 0x5028 402 #define GPIOH 0x502c 403 # define GPIO_CLOCK_DIR_MASK (1 << 0) 404 # define GPIO_CLOCK_DIR_IN (0 << 1) 405 # define GPIO_CLOCK_DIR_OUT (1 << 1) 406 # define GPIO_CLOCK_VAL_MASK (1 << 2) 407 # define GPIO_CLOCK_VAL_OUT (1 << 3) 408 # define GPIO_CLOCK_VAL_IN (1 << 4) 409 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 410 # define GPIO_DATA_DIR_MASK (1 << 8) 411 # define GPIO_DATA_DIR_IN (0 << 9) 412 # define GPIO_DATA_DIR_OUT (1 << 9) 413 # define GPIO_DATA_VAL_MASK (1 << 10) 414 # define GPIO_DATA_VAL_OUT (1 << 11) 415 # define GPIO_DATA_VAL_IN (1 << 12) 416 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 417 418 #define GMBUS0 0x5100 419 #define GMBUS1 0x5104 420 #define GMBUS2 0x5108 421 #define GMBUS3 0x510c 422 #define GMBUS4 0x5110 423 #define GMBUS5 0x5120 424 425 /* 426 * Clock control & power management 427 */ 428 429 #define VGA0 0x6000 430 #define VGA1 0x6004 431 #define VGA_PD 0x6010 432 #define VGA0_PD_P2_DIV_4 (1 << 7) 433 #define VGA0_PD_P1_DIV_2 (1 << 5) 434 #define VGA0_PD_P1_SHIFT 0 435 #define VGA0_PD_P1_MASK (0x1f << 0) 436 #define VGA1_PD_P2_DIV_4 (1 << 15) 437 #define VGA1_PD_P1_DIV_2 (1 << 13) 438 #define VGA1_PD_P1_SHIFT 8 439 #define VGA1_PD_P1_MASK (0x1f << 8) 440 #define DPLL_A 0x06014 441 #define DPLL_B 0x06018 442 #define DPLL_VCO_ENABLE (1 << 31) 443 #define DPLL_DVO_HIGH_SPEED (1 << 30) 444 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 445 #define DPLL_VGA_MODE_DIS (1 << 28) 446 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 447 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 448 #define DPLL_MODE_MASK (3 << 26) 449 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 450 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 451 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 452 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 453 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 454 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 455 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 456 457 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 458 #define I915_CRC_ERROR_ENABLE (1UL<<29) 459 #define I915_CRC_DONE_ENABLE (1UL<<28) 460 #define I915_GMBUS_EVENT_ENABLE (1UL<<27) 461 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 462 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 463 #define I915_DPST_EVENT_ENABLE (1UL<<23) 464 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 465 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 466 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 467 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 468 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 469 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 470 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 471 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 472 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 473 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 474 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 475 #define I915_DPST_EVENT_STATUS (1UL<<7) 476 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 477 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 478 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 479 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 480 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) 481 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 482 483 #define SRX_INDEX 0x3c4 484 #define SRX_DATA 0x3c5 485 #define SR01 1 486 #define SR01_SCREEN_OFF (1<<5) 487 488 #define PPCR 0x61204 489 #define PPCR_ON (1<<0) 490 491 #define DVOB 0x61140 492 #define DVOB_ON (1<<31) 493 #define DVOC 0x61160 494 #define DVOC_ON (1<<31) 495 #define LVDS 0x61180 496 #define LVDS_ON (1<<31) 497 498 #define ADPA 0x61100 499 #define ADPA_DPMS_MASK (~(3<<10)) 500 #define ADPA_DPMS_ON (0<<10) 501 #define ADPA_DPMS_SUSPEND (1<<10) 502 #define ADPA_DPMS_STANDBY (2<<10) 503 #define ADPA_DPMS_OFF (3<<10) 504 505 #define RING_TAIL 0x00 506 #define TAIL_ADDR 0x001FFFF8 507 #define RING_HEAD 0x04 508 #define HEAD_WRAP_COUNT 0xFFE00000 509 #define HEAD_WRAP_ONE 0x00200000 510 #define HEAD_ADDR 0x001FFFFC 511 #define RING_START 0x08 512 #define START_ADDR 0xFFFFF000 513 #define RING_LEN 0x0C 514 #define RING_NR_PAGES 0x001FF000 515 #define RING_REPORT_MASK 0x00000006 516 #define RING_REPORT_64K 0x00000002 517 #define RING_REPORT_128K 0x00000004 518 #define RING_NO_REPORT 0x00000000 519 #define RING_VALID_MASK 0x00000001 520 #define RING_VALID 0x00000001 521 #define RING_INVALID 0x00000000 522 523 /* Scratch pad debug 0 reg: 524 */ 525 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 526 /* 527 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 528 * this field (only one bit may be set). 529 */ 530 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 531 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 532 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 533 /* i830, required in DVO non-gang */ 534 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 535 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 536 #define PLL_REF_INPUT_DREFCLK (0 << 13) 537 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 538 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 539 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 540 #define PLL_REF_INPUT_MASK (3 << 13) 541 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 542 /* Ironlake */ 543 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 544 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 545 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 546 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 547 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 548 549 /* 550 * Parallel to Serial Load Pulse phase selection. 551 * Selects the phase for the 10X DPLL clock for the PCIe 552 * digital display port. The range is 4 to 13; 10 or more 553 * is just a flip delay. The default is 6 554 */ 555 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 556 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 557 /* 558 * SDVO multiplier for 945G/GM. Not used on 965. 559 */ 560 #define SDVO_MULTIPLIER_MASK 0x000000ff 561 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 562 #define SDVO_MULTIPLIER_SHIFT_VGA 0 563 #define DPLL_A_MD 0x0601c /* 965+ only */ 564 /* 565 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 566 * 567 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 568 */ 569 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 570 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 571 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 572 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 573 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 574 /* 575 * SDVO/UDI pixel multiplier. 576 * 577 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 578 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 579 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 580 * dummy bytes in the datastream at an increased clock rate, with both sides of 581 * the link knowing how many bytes are fill. 582 * 583 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 584 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 585 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 586 * through an SDVO command. 587 * 588 * This register field has values of multiplication factor minus 1, with 589 * a maximum multiplier of 5 for SDVO. 590 */ 591 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 592 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 593 /* 594 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 595 * This best be set to the default value (3) or the CRT won't work. No, 596 * I don't entirely understand what this does... 597 */ 598 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 599 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 600 #define DPLL_B_MD 0x06020 /* 965+ only */ 601 #define FPA0 0x06040 602 #define FPA1 0x06044 603 #define FPB0 0x06048 604 #define FPB1 0x0604c 605 #define FP_N_DIV_MASK 0x003f0000 606 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 607 #define FP_N_DIV_SHIFT 16 608 #define FP_M1_DIV_MASK 0x00003f00 609 #define FP_M1_DIV_SHIFT 8 610 #define FP_M2_DIV_MASK 0x0000003f 611 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 612 #define FP_M2_DIV_SHIFT 0 613 #define DPLL_TEST 0x606c 614 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 615 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 616 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 617 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 618 #define DPLLB_TEST_N_BYPASS (1 << 19) 619 #define DPLLB_TEST_M_BYPASS (1 << 18) 620 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 621 #define DPLLA_TEST_N_BYPASS (1 << 3) 622 #define DPLLA_TEST_M_BYPASS (1 << 2) 623 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 624 #define D_STATE 0x6104 625 #define DSTATE_PLL_D3_OFF (1<<3) 626 #define DSTATE_GFX_CLOCK_GATING (1<<1) 627 #define DSTATE_DOT_CLOCK_GATING (1<<0) 628 #define DSPCLK_GATE_D 0x6200 629 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 630 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 631 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 632 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 633 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 634 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 635 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 636 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 637 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 638 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 639 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 640 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 641 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 642 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 643 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 644 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 645 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 646 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 647 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 648 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 649 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 650 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 651 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 652 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 653 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 654 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 655 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 656 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 657 /** 658 * This bit must be set on the 830 to prevent hangs when turning off the 659 * overlay scaler. 660 */ 661 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 662 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 663 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 664 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 665 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 666 667 #define RENCLK_GATE_D1 0x6204 668 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 669 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 670 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 671 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 672 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 673 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 674 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 675 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 676 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 677 /** This bit must be unset on 855,865 */ 678 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 679 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 680 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 681 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 682 /** This bit must be set on 855,865. */ 683 # define SV_CLOCK_GATE_DISABLE (1 << 0) 684 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 685 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 686 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 687 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 688 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 689 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 690 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 691 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 692 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 693 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 694 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 695 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 696 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 697 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 698 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 699 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 700 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 701 702 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 703 /** This bit must always be set on 965G/965GM */ 704 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 705 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 706 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 707 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 708 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 709 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 710 /** This bit must always be set on 965G */ 711 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 712 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 713 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 714 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 715 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 716 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 717 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 718 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 719 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 720 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 721 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 722 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 723 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 724 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 725 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 726 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 727 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 728 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 729 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 730 731 #define RENCLK_GATE_D2 0x6208 732 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 733 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 734 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 735 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 736 #define DEUC 0x6214 /* CRL only */ 737 738 /* 739 * Palette regs 740 */ 741 742 #define PALETTE_A 0x0a000 743 #define PALETTE_B 0x0a800 744 745 /* MCH MMIO space */ 746 747 /* 748 * MCHBAR mirror. 749 * 750 * This mirrors the MCHBAR MMIO space whose location is determined by 751 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 752 * every way. It is not accessible from the CP register read instructions. 753 * 754 */ 755 #define MCHBAR_MIRROR_BASE 0x10000 756 757 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 758 #define DCC 0x10200 759 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 760 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 761 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 762 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 763 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 764 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 765 766 /** 965 MCH register controlling DRAM channel configuration */ 767 #define C0DRB3 0x10206 768 #define C1DRB3 0x10606 769 770 /* Clocking configuration register */ 771 #define CLKCFG 0x10c00 772 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 773 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 774 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 775 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 776 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 777 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 778 /* Note, below two are guess */ 779 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 780 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 781 #define CLKCFG_FSB_MASK (7 << 0) 782 #define CLKCFG_MEM_533 (1 << 4) 783 #define CLKCFG_MEM_667 (2 << 4) 784 #define CLKCFG_MEM_800 (3 << 4) 785 #define CLKCFG_MEM_MASK (7 << 4) 786 787 /** GM965 GM45 render standby register */ 788 #define MCHBAR_RENDER_STANDBY 0x111B8 789 #define RCX_SW_EXIT (1<<23) 790 #define RSX_STATUS_MASK 0x00700000 791 #define PEG_BAND_GAP_DATA 0x14d68 792 793 /* 794 * Overlay regs 795 */ 796 797 #define OVADD 0x30000 798 #define DOVSTA 0x30008 799 #define OC_BUF (0x3<<20) 800 #define OGAMC5 0x30010 801 #define OGAMC4 0x30014 802 #define OGAMC3 0x30018 803 #define OGAMC2 0x3001c 804 #define OGAMC1 0x30020 805 #define OGAMC0 0x30024 806 807 /* 808 * Display engine regs 809 */ 810 811 /* Pipe A timing regs */ 812 #define HTOTAL_A 0x60000 813 #define HBLANK_A 0x60004 814 #define HSYNC_A 0x60008 815 #define VTOTAL_A 0x6000c 816 #define VBLANK_A 0x60010 817 #define VSYNC_A 0x60014 818 #define PIPEASRC 0x6001c 819 #define BCLRPAT_A 0x60020 820 821 /* Pipe B timing regs */ 822 #define HTOTAL_B 0x61000 823 #define HBLANK_B 0x61004 824 #define HSYNC_B 0x61008 825 #define VTOTAL_B 0x6100c 826 #define VBLANK_B 0x61010 827 #define VSYNC_B 0x61014 828 #define PIPEBSRC 0x6101c 829 #define BCLRPAT_B 0x61020 830 831 /* VGA port control */ 832 #define ADPA 0x61100 833 #define ADPA_DAC_ENABLE (1<<31) 834 #define ADPA_DAC_DISABLE 0 835 #define ADPA_PIPE_SELECT_MASK (1<<30) 836 #define ADPA_PIPE_A_SELECT 0 837 #define ADPA_PIPE_B_SELECT (1<<30) 838 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 839 #define ADPA_SETS_HVPOLARITY 0 840 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 841 #define ADPA_VSYNC_CNTL_ENABLE 0 842 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 843 #define ADPA_HSYNC_CNTL_ENABLE 0 844 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 845 #define ADPA_VSYNC_ACTIVE_LOW 0 846 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 847 #define ADPA_HSYNC_ACTIVE_LOW 0 848 #define ADPA_DPMS_MASK (~(3<<10)) 849 #define ADPA_DPMS_ON (0<<10) 850 #define ADPA_DPMS_SUSPEND (1<<10) 851 #define ADPA_DPMS_STANDBY (2<<10) 852 #define ADPA_DPMS_OFF (3<<10) 853 854 /* Hotplug control (945+ only) */ 855 #define PORT_HOTPLUG_EN 0x61110 856 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 857 #define DPB_HOTPLUG_INT_EN (1 << 29) 858 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 859 #define DPC_HOTPLUG_INT_EN (1 << 28) 860 #define HDMID_HOTPLUG_INT_EN (1 << 27) 861 #define DPD_HOTPLUG_INT_EN (1 << 27) 862 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 863 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 864 #define TV_HOTPLUG_INT_EN (1 << 18) 865 #define CRT_HOTPLUG_INT_EN (1 << 9) 866 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 867 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 868 /* must use period 64 on GM45 according to docs */ 869 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 870 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 871 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 872 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 873 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 874 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 875 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 876 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 877 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 878 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 879 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 880 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 881 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ 882 #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f 883 884 #define PORT_HOTPLUG_STAT 0x61114 885 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 886 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 887 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 888 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 889 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 890 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 891 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 892 #define TV_HOTPLUG_INT_STATUS (1 << 10) 893 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 894 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 895 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 896 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 897 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 898 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 899 900 /* SDVO port control */ 901 #define SDVOB 0x61140 902 #define SDVOC 0x61160 903 #define SDVO_ENABLE (1 << 31) 904 #define SDVO_PIPE_B_SELECT (1 << 30) 905 #define SDVO_STALL_SELECT (1 << 29) 906 #define SDVO_INTERRUPT_ENABLE (1 << 26) 907 /** 908 * 915G/GM SDVO pixel multiplier. 909 * 910 * Programmed value is multiplier - 1, up to 5x. 911 * 912 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 913 */ 914 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 915 #define SDVO_PORT_MULTIPLY_SHIFT 23 916 #define SDVO_PHASE_SELECT_MASK (15 << 19) 917 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 918 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 919 #define SDVOC_GANG_MODE (1 << 16) 920 #define SDVO_ENCODING_SDVO (0x0 << 10) 921 #define SDVO_ENCODING_HDMI (0x2 << 10) 922 /** Requird for HDMI operation */ 923 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 924 #define SDVO_BORDER_ENABLE (1 << 7) 925 #define SDVO_AUDIO_ENABLE (1 << 6) 926 /** New with 965, default is to be set */ 927 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 928 /** New with 965, default is to be set */ 929 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 930 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 931 #define SDVO_DETECTED (1 << 2) 932 /* Bits to be preserved when writing */ 933 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 934 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 935 936 /* DVO port control */ 937 #define DVOA 0x61120 938 #define DVOB 0x61140 939 #define DVOC 0x61160 940 #define DVO_ENABLE (1 << 31) 941 #define DVO_PIPE_B_SELECT (1 << 30) 942 #define DVO_PIPE_STALL_UNUSED (0 << 28) 943 #define DVO_PIPE_STALL (1 << 28) 944 #define DVO_PIPE_STALL_TV (2 << 28) 945 #define DVO_PIPE_STALL_MASK (3 << 28) 946 #define DVO_USE_VGA_SYNC (1 << 15) 947 #define DVO_DATA_ORDER_I740 (0 << 14) 948 #define DVO_DATA_ORDER_FP (1 << 14) 949 #define DVO_VSYNC_DISABLE (1 << 11) 950 #define DVO_HSYNC_DISABLE (1 << 10) 951 #define DVO_VSYNC_TRISTATE (1 << 9) 952 #define DVO_HSYNC_TRISTATE (1 << 8) 953 #define DVO_BORDER_ENABLE (1 << 7) 954 #define DVO_DATA_ORDER_GBRG (1 << 6) 955 #define DVO_DATA_ORDER_RGGB (0 << 6) 956 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 957 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 958 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 959 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 960 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 961 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 962 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 963 #define DVO_PRESERVE_MASK (0x7<<24) 964 #define DVOA_SRCDIM 0x61124 965 #define DVOB_SRCDIM 0x61144 966 #define DVOC_SRCDIM 0x61164 967 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 968 #define DVO_SRCDIM_VERTICAL_SHIFT 0 969 970 /* LVDS port control */ 971 #define LVDS 0x61180 972 /* 973 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 974 * the DPLL semantics change when the LVDS is assigned to that pipe. 975 */ 976 #define LVDS_PORT_EN (1 << 31) 977 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 978 #define LVDS_PIPEB_SELECT (1 << 30) 979 /* LVDS dithering flag on 965/g4x platform */ 980 #define LVDS_ENABLE_DITHER (1 << 25) 981 /* Enable border for unscaled (or aspect-scaled) display */ 982 #define LVDS_BORDER_ENABLE (1 << 15) 983 /* 984 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 985 * pixel. 986 */ 987 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 988 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 989 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 990 /* 991 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 992 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 993 * on. 994 */ 995 #define LVDS_A3_POWER_MASK (3 << 6) 996 #define LVDS_A3_POWER_DOWN (0 << 6) 997 #define LVDS_A3_POWER_UP (3 << 6) 998 /* 999 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1000 * is set. 1001 */ 1002 #define LVDS_CLKB_POWER_MASK (3 << 4) 1003 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1004 #define LVDS_CLKB_POWER_UP (3 << 4) 1005 /* 1006 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1007 * setting for whether we are in dual-channel mode. The B3 pair will 1008 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1009 */ 1010 #define LVDS_B0B3_POWER_MASK (3 << 2) 1011 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1012 #define LVDS_B0B3_POWER_UP (3 << 2) 1013 1014 /* Panel power sequencing */ 1015 #define PP_STATUS 0x61200 1016 #define PP_ON (1 << 31) 1017 /* 1018 * Indicates that all dependencies of the panel are on: 1019 * 1020 * - PLL enabled 1021 * - pipe enabled 1022 * - LVDS/DVOB/DVOC on 1023 */ 1024 #define PP_READY (1 << 30) 1025 #define PP_SEQUENCE_NONE (0 << 28) 1026 #define PP_SEQUENCE_ON (1 << 28) 1027 #define PP_SEQUENCE_OFF (2 << 28) 1028 #define PP_SEQUENCE_MASK 0x30000000 1029 #define PP_CONTROL 0x61204 1030 #define POWER_TARGET_ON (1 << 0) 1031 #define PP_ON_DELAYS 0x61208 1032 #define PP_OFF_DELAYS 0x6120c 1033 #define PP_DIVISOR 0x61210 1034 1035 /* Panel fitting */ 1036 #define PFIT_CONTROL 0x61230 1037 #define PFIT_ENABLE (1 << 31) 1038 #define PFIT_PIPE_MASK (3 << 29) 1039 #define PFIT_PIPE_SHIFT 29 1040 #define VERT_INTERP_DISABLE (0 << 10) 1041 #define VERT_INTERP_BILINEAR (1 << 10) 1042 #define VERT_INTERP_MASK (3 << 10) 1043 #define VERT_AUTO_SCALE (1 << 9) 1044 #define HORIZ_INTERP_DISABLE (0 << 6) 1045 #define HORIZ_INTERP_BILINEAR (1 << 6) 1046 #define HORIZ_INTERP_MASK (3 << 6) 1047 #define HORIZ_AUTO_SCALE (1 << 5) 1048 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1049 #define PFIT_FILTER_FUZZY (0 << 24) 1050 #define PFIT_SCALING_AUTO (0 << 26) 1051 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1052 #define PFIT_SCALING_PILLAR (2 << 26) 1053 #define PFIT_SCALING_LETTER (3 << 26) 1054 #define PFIT_PGM_RATIOS 0x61234 1055 #define PFIT_VERT_SCALE_MASK 0xfff00000 1056 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1057 /* Pre-965 */ 1058 #define PFIT_VERT_SCALE_SHIFT 20 1059 #define PFIT_VERT_SCALE_MASK 0xfff00000 1060 #define PFIT_HORIZ_SCALE_SHIFT 4 1061 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1062 /* 965+ */ 1063 #define PFIT_VERT_SCALE_SHIFT_965 16 1064 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1065 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1066 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1067 1068 #define PFIT_AUTO_RATIOS 0x61238 1069 1070 /* Backlight control */ 1071 #define BLC_PWM_CTL 0x61254 1072 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1073 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1074 #define BLM_COMBINATION_MODE (1 << 30) 1075 /* 1076 * This is the most significant 15 bits of the number of backlight cycles in a 1077 * complete cycle of the modulated backlight control. 1078 * 1079 * The actual value is this field multiplied by two. 1080 */ 1081 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1082 #define BLM_LEGACY_MODE (1 << 16) 1083 /* 1084 * This is the number of cycles out of the backlight modulation cycle for which 1085 * the backlight is on. 1086 * 1087 * This field must be no greater than the number of cycles in the complete 1088 * backlight modulation cycle. 1089 */ 1090 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1091 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1092 1093 #define BLC_HIST_CTL 0x61260 1094 1095 /* TV port control */ 1096 #define TV_CTL 0x68000 1097 /** Enables the TV encoder */ 1098 # define TV_ENC_ENABLE (1 << 31) 1099 /** Sources the TV encoder input from pipe B instead of A. */ 1100 # define TV_ENC_PIPEB_SELECT (1 << 30) 1101 /** Outputs composite video (DAC A only) */ 1102 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1103 /** Outputs SVideo video (DAC B/C) */ 1104 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1105 /** Outputs Component video (DAC A/B/C) */ 1106 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1107 /** Outputs Composite and SVideo (DAC A/B/C) */ 1108 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1109 # define TV_TRILEVEL_SYNC (1 << 21) 1110 /** Enables slow sync generation (945GM only) */ 1111 # define TV_SLOW_SYNC (1 << 20) 1112 /** Selects 4x oversampling for 480i and 576p */ 1113 # define TV_OVERSAMPLE_4X (0 << 18) 1114 /** Selects 2x oversampling for 720p and 1080i */ 1115 # define TV_OVERSAMPLE_2X (1 << 18) 1116 /** Selects no oversampling for 1080p */ 1117 # define TV_OVERSAMPLE_NONE (2 << 18) 1118 /** Selects 8x oversampling */ 1119 # define TV_OVERSAMPLE_8X (3 << 18) 1120 /** Selects progressive mode rather than interlaced */ 1121 # define TV_PROGRESSIVE (1 << 17) 1122 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1123 # define TV_PAL_BURST (1 << 16) 1124 /** Field for setting delay of Y compared to C */ 1125 # define TV_YC_SKEW_MASK (7 << 12) 1126 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1127 # define TV_ENC_SDP_FIX (1 << 11) 1128 /** 1129 * Enables a fix for the 915GM only. 1130 * 1131 * Not sure what it does. 1132 */ 1133 # define TV_ENC_C0_FIX (1 << 10) 1134 /** Bits that must be preserved by software */ 1135 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1136 # define TV_FUSE_STATE_MASK (3 << 4) 1137 /** Read-only state that reports all features enabled */ 1138 # define TV_FUSE_STATE_ENABLED (0 << 4) 1139 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1140 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1141 /** Read-only state that reports that TV-out is disabled in hardware. */ 1142 # define TV_FUSE_STATE_DISABLED (2 << 4) 1143 /** Normal operation */ 1144 # define TV_TEST_MODE_NORMAL (0 << 0) 1145 /** Encoder test pattern 1 - combo pattern */ 1146 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1147 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1148 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1149 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1150 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1151 /** Encoder test pattern 4 - random noise */ 1152 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1153 /** Encoder test pattern 5 - linear color ramps */ 1154 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1155 /** 1156 * This test mode forces the DACs to 50% of full output. 1157 * 1158 * This is used for load detection in combination with TVDAC_SENSE_MASK 1159 */ 1160 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1161 # define TV_TEST_MODE_MASK (7 << 0) 1162 1163 #define TV_DAC 0x68004 1164 /** 1165 * Reports that DAC state change logic has reported change (RO). 1166 * 1167 * This gets cleared when TV_DAC_STATE_EN is cleared 1168 */ 1169 # define TVDAC_STATE_CHG (1 << 31) 1170 # define TVDAC_SENSE_MASK (7 << 28) 1171 /** Reports that DAC A voltage is above the detect threshold */ 1172 # define TVDAC_A_SENSE (1 << 30) 1173 /** Reports that DAC B voltage is above the detect threshold */ 1174 # define TVDAC_B_SENSE (1 << 29) 1175 /** Reports that DAC C voltage is above the detect threshold */ 1176 # define TVDAC_C_SENSE (1 << 28) 1177 /** 1178 * Enables DAC state detection logic, for load-based TV detection. 1179 * 1180 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1181 * to off, for load detection to work. 1182 */ 1183 # define TVDAC_STATE_CHG_EN (1 << 27) 1184 /** Sets the DAC A sense value to high */ 1185 # define TVDAC_A_SENSE_CTL (1 << 26) 1186 /** Sets the DAC B sense value to high */ 1187 # define TVDAC_B_SENSE_CTL (1 << 25) 1188 /** Sets the DAC C sense value to high */ 1189 # define TVDAC_C_SENSE_CTL (1 << 24) 1190 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1191 # define DAC_CTL_OVERRIDE (1 << 7) 1192 /** Sets the slew rate. Must be preserved in software */ 1193 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1194 # define DAC_A_1_3_V (0 << 4) 1195 # define DAC_A_1_1_V (1 << 4) 1196 # define DAC_A_0_7_V (2 << 4) 1197 # define DAC_A_MASK (3 << 4) 1198 # define DAC_B_1_3_V (0 << 2) 1199 # define DAC_B_1_1_V (1 << 2) 1200 # define DAC_B_0_7_V (2 << 2) 1201 # define DAC_B_MASK (3 << 2) 1202 # define DAC_C_1_3_V (0 << 0) 1203 # define DAC_C_1_1_V (1 << 0) 1204 # define DAC_C_0_7_V (2 << 0) 1205 # define DAC_C_MASK (3 << 0) 1206 1207 /** 1208 * CSC coefficients are stored in a floating point format with 9 bits of 1209 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1210 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1211 * -1 (0x3) being the only legal negative value. 1212 */ 1213 #define TV_CSC_Y 0x68010 1214 # define TV_RY_MASK 0x07ff0000 1215 # define TV_RY_SHIFT 16 1216 # define TV_GY_MASK 0x00000fff 1217 # define TV_GY_SHIFT 0 1218 1219 #define TV_CSC_Y2 0x68014 1220 # define TV_BY_MASK 0x07ff0000 1221 # define TV_BY_SHIFT 16 1222 /** 1223 * Y attenuation for component video. 1224 * 1225 * Stored in 1.9 fixed point. 1226 */ 1227 # define TV_AY_MASK 0x000003ff 1228 # define TV_AY_SHIFT 0 1229 1230 #define TV_CSC_U 0x68018 1231 # define TV_RU_MASK 0x07ff0000 1232 # define TV_RU_SHIFT 16 1233 # define TV_GU_MASK 0x000007ff 1234 # define TV_GU_SHIFT 0 1235 1236 #define TV_CSC_U2 0x6801c 1237 # define TV_BU_MASK 0x07ff0000 1238 # define TV_BU_SHIFT 16 1239 /** 1240 * U attenuation for component video. 1241 * 1242 * Stored in 1.9 fixed point. 1243 */ 1244 # define TV_AU_MASK 0x000003ff 1245 # define TV_AU_SHIFT 0 1246 1247 #define TV_CSC_V 0x68020 1248 # define TV_RV_MASK 0x0fff0000 1249 # define TV_RV_SHIFT 16 1250 # define TV_GV_MASK 0x000007ff 1251 # define TV_GV_SHIFT 0 1252 1253 #define TV_CSC_V2 0x68024 1254 # define TV_BV_MASK 0x07ff0000 1255 # define TV_BV_SHIFT 16 1256 /** 1257 * V attenuation for component video. 1258 * 1259 * Stored in 1.9 fixed point. 1260 */ 1261 # define TV_AV_MASK 0x000007ff 1262 # define TV_AV_SHIFT 0 1263 1264 #define TV_CLR_KNOBS 0x68028 1265 /** 2s-complement brightness adjustment */ 1266 # define TV_BRIGHTNESS_MASK 0xff000000 1267 # define TV_BRIGHTNESS_SHIFT 24 1268 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1269 # define TV_CONTRAST_MASK 0x00ff0000 1270 # define TV_CONTRAST_SHIFT 16 1271 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1272 # define TV_SATURATION_MASK 0x0000ff00 1273 # define TV_SATURATION_SHIFT 8 1274 /** Hue adjustment, as an integer phase angle in degrees */ 1275 # define TV_HUE_MASK 0x000000ff 1276 # define TV_HUE_SHIFT 0 1277 1278 #define TV_CLR_LEVEL 0x6802c 1279 /** Controls the DAC level for black */ 1280 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1281 # define TV_BLACK_LEVEL_SHIFT 16 1282 /** Controls the DAC level for blanking */ 1283 # define TV_BLANK_LEVEL_MASK 0x000001ff 1284 # define TV_BLANK_LEVEL_SHIFT 0 1285 1286 #define TV_H_CTL_1 0x68030 1287 /** Number of pixels in the hsync. */ 1288 # define TV_HSYNC_END_MASK 0x1fff0000 1289 # define TV_HSYNC_END_SHIFT 16 1290 /** Total number of pixels minus one in the line (display and blanking). */ 1291 # define TV_HTOTAL_MASK 0x00001fff 1292 # define TV_HTOTAL_SHIFT 0 1293 1294 #define TV_H_CTL_2 0x68034 1295 /** Enables the colorburst (needed for non-component color) */ 1296 # define TV_BURST_ENA (1 << 31) 1297 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1298 # define TV_HBURST_START_SHIFT 16 1299 # define TV_HBURST_START_MASK 0x1fff0000 1300 /** Length of the colorburst */ 1301 # define TV_HBURST_LEN_SHIFT 0 1302 # define TV_HBURST_LEN_MASK 0x0001fff 1303 1304 #define TV_H_CTL_3 0x68038 1305 /** End of hblank, measured in pixels minus one from start of hsync */ 1306 # define TV_HBLANK_END_SHIFT 16 1307 # define TV_HBLANK_END_MASK 0x1fff0000 1308 /** Start of hblank, measured in pixels minus one from start of hsync */ 1309 # define TV_HBLANK_START_SHIFT 0 1310 # define TV_HBLANK_START_MASK 0x0001fff 1311 1312 #define TV_V_CTL_1 0x6803c 1313 /** XXX */ 1314 # define TV_NBR_END_SHIFT 16 1315 # define TV_NBR_END_MASK 0x07ff0000 1316 /** XXX */ 1317 # define TV_VI_END_F1_SHIFT 8 1318 # define TV_VI_END_F1_MASK 0x00003f00 1319 /** XXX */ 1320 # define TV_VI_END_F2_SHIFT 0 1321 # define TV_VI_END_F2_MASK 0x0000003f 1322 1323 #define TV_V_CTL_2 0x68040 1324 /** Length of vsync, in half lines */ 1325 # define TV_VSYNC_LEN_MASK 0x07ff0000 1326 # define TV_VSYNC_LEN_SHIFT 16 1327 /** Offset of the start of vsync in field 1, measured in one less than the 1328 * number of half lines. 1329 */ 1330 # define TV_VSYNC_START_F1_MASK 0x00007f00 1331 # define TV_VSYNC_START_F1_SHIFT 8 1332 /** 1333 * Offset of the start of vsync in field 2, measured in one less than the 1334 * number of half lines. 1335 */ 1336 # define TV_VSYNC_START_F2_MASK 0x0000007f 1337 # define TV_VSYNC_START_F2_SHIFT 0 1338 1339 #define TV_V_CTL_3 0x68044 1340 /** Enables generation of the equalization signal */ 1341 # define TV_EQUAL_ENA (1 << 31) 1342 /** Length of vsync, in half lines */ 1343 # define TV_VEQ_LEN_MASK 0x007f0000 1344 # define TV_VEQ_LEN_SHIFT 16 1345 /** Offset of the start of equalization in field 1, measured in one less than 1346 * the number of half lines. 1347 */ 1348 # define TV_VEQ_START_F1_MASK 0x0007f00 1349 # define TV_VEQ_START_F1_SHIFT 8 1350 /** 1351 * Offset of the start of equalization in field 2, measured in one less than 1352 * the number of half lines. 1353 */ 1354 # define TV_VEQ_START_F2_MASK 0x000007f 1355 # define TV_VEQ_START_F2_SHIFT 0 1356 1357 #define TV_V_CTL_4 0x68048 1358 /** 1359 * Offset to start of vertical colorburst, measured in one less than the 1360 * number of lines from vertical start. 1361 */ 1362 # define TV_VBURST_START_F1_MASK 0x003f0000 1363 # define TV_VBURST_START_F1_SHIFT 16 1364 /** 1365 * Offset to the end of vertical colorburst, measured in one less than the 1366 * number of lines from the start of NBR. 1367 */ 1368 # define TV_VBURST_END_F1_MASK 0x000000ff 1369 # define TV_VBURST_END_F1_SHIFT 0 1370 1371 #define TV_V_CTL_5 0x6804c 1372 /** 1373 * Offset to start of vertical colorburst, measured in one less than the 1374 * number of lines from vertical start. 1375 */ 1376 # define TV_VBURST_START_F2_MASK 0x003f0000 1377 # define TV_VBURST_START_F2_SHIFT 16 1378 /** 1379 * Offset to the end of vertical colorburst, measured in one less than the 1380 * number of lines from the start of NBR. 1381 */ 1382 # define TV_VBURST_END_F2_MASK 0x000000ff 1383 # define TV_VBURST_END_F2_SHIFT 0 1384 1385 #define TV_V_CTL_6 0x68050 1386 /** 1387 * Offset to start of vertical colorburst, measured in one less than the 1388 * number of lines from vertical start. 1389 */ 1390 # define TV_VBURST_START_F3_MASK 0x003f0000 1391 # define TV_VBURST_START_F3_SHIFT 16 1392 /** 1393 * Offset to the end of vertical colorburst, measured in one less than the 1394 * number of lines from the start of NBR. 1395 */ 1396 # define TV_VBURST_END_F3_MASK 0x000000ff 1397 # define TV_VBURST_END_F3_SHIFT 0 1398 1399 #define TV_V_CTL_7 0x68054 1400 /** 1401 * Offset to start of vertical colorburst, measured in one less than the 1402 * number of lines from vertical start. 1403 */ 1404 # define TV_VBURST_START_F4_MASK 0x003f0000 1405 # define TV_VBURST_START_F4_SHIFT 16 1406 /** 1407 * Offset to the end of vertical colorburst, measured in one less than the 1408 * number of lines from the start of NBR. 1409 */ 1410 # define TV_VBURST_END_F4_MASK 0x000000ff 1411 # define TV_VBURST_END_F4_SHIFT 0 1412 1413 #define TV_SC_CTL_1 0x68060 1414 /** Turns on the first subcarrier phase generation DDA */ 1415 # define TV_SC_DDA1_EN (1 << 31) 1416 /** Turns on the first subcarrier phase generation DDA */ 1417 # define TV_SC_DDA2_EN (1 << 30) 1418 /** Turns on the first subcarrier phase generation DDA */ 1419 # define TV_SC_DDA3_EN (1 << 29) 1420 /** Sets the subcarrier DDA to reset frequency every other field */ 1421 # define TV_SC_RESET_EVERY_2 (0 << 24) 1422 /** Sets the subcarrier DDA to reset frequency every fourth field */ 1423 # define TV_SC_RESET_EVERY_4 (1 << 24) 1424 /** Sets the subcarrier DDA to reset frequency every eighth field */ 1425 # define TV_SC_RESET_EVERY_8 (2 << 24) 1426 /** Sets the subcarrier DDA to never reset the frequency */ 1427 # define TV_SC_RESET_NEVER (3 << 24) 1428 /** Sets the peak amplitude of the colorburst.*/ 1429 # define TV_BURST_LEVEL_MASK 0x00ff0000 1430 # define TV_BURST_LEVEL_SHIFT 16 1431 /** Sets the increment of the first subcarrier phase generation DDA */ 1432 # define TV_SCDDA1_INC_MASK 0x00000fff 1433 # define TV_SCDDA1_INC_SHIFT 0 1434 1435 #define TV_SC_CTL_2 0x68064 1436 /** Sets the rollover for the second subcarrier phase generation DDA */ 1437 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 1438 # define TV_SCDDA2_SIZE_SHIFT 16 1439 /** Sets the increent of the second subcarrier phase generation DDA */ 1440 # define TV_SCDDA2_INC_MASK 0x00007fff 1441 # define TV_SCDDA2_INC_SHIFT 0 1442 1443 #define TV_SC_CTL_3 0x68068 1444 /** Sets the rollover for the third subcarrier phase generation DDA */ 1445 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 1446 # define TV_SCDDA3_SIZE_SHIFT 16 1447 /** Sets the increent of the third subcarrier phase generation DDA */ 1448 # define TV_SCDDA3_INC_MASK 0x00007fff 1449 # define TV_SCDDA3_INC_SHIFT 0 1450 1451 #define TV_WIN_POS 0x68070 1452 /** X coordinate of the display from the start of horizontal active */ 1453 # define TV_XPOS_MASK 0x1fff0000 1454 # define TV_XPOS_SHIFT 16 1455 /** Y coordinate of the display from the start of vertical active (NBR) */ 1456 # define TV_YPOS_MASK 0x00000fff 1457 # define TV_YPOS_SHIFT 0 1458 1459 #define TV_WIN_SIZE 0x68074 1460 /** Horizontal size of the display window, measured in pixels*/ 1461 # define TV_XSIZE_MASK 0x1fff0000 1462 # define TV_XSIZE_SHIFT 16 1463 /** 1464 * Vertical size of the display window, measured in pixels. 1465 * 1466 * Must be even for interlaced modes. 1467 */ 1468 # define TV_YSIZE_MASK 0x00000fff 1469 # define TV_YSIZE_SHIFT 0 1470 1471 #define TV_FILTER_CTL_1 0x68080 1472 /** 1473 * Enables automatic scaling calculation. 1474 * 1475 * If set, the rest of the registers are ignored, and the calculated values can 1476 * be read back from the register. 1477 */ 1478 # define TV_AUTO_SCALE (1 << 31) 1479 /** 1480 * Disables the vertical filter. 1481 * 1482 * This is required on modes more than 1024 pixels wide */ 1483 # define TV_V_FILTER_BYPASS (1 << 29) 1484 /** Enables adaptive vertical filtering */ 1485 # define TV_VADAPT (1 << 28) 1486 # define TV_VADAPT_MODE_MASK (3 << 26) 1487 /** Selects the least adaptive vertical filtering mode */ 1488 # define TV_VADAPT_MODE_LEAST (0 << 26) 1489 /** Selects the moderately adaptive vertical filtering mode */ 1490 # define TV_VADAPT_MODE_MODERATE (1 << 26) 1491 /** Selects the most adaptive vertical filtering mode */ 1492 # define TV_VADAPT_MODE_MOST (3 << 26) 1493 /** 1494 * Sets the horizontal scaling factor. 1495 * 1496 * This should be the fractional part of the horizontal scaling factor divided 1497 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1498 * 1499 * (src width - 1) / ((oversample * dest width) - 1) 1500 */ 1501 # define TV_HSCALE_FRAC_MASK 0x00003fff 1502 # define TV_HSCALE_FRAC_SHIFT 0 1503 1504 #define TV_FILTER_CTL_2 0x68084 1505 /** 1506 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1507 * 1508 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1509 */ 1510 # define TV_VSCALE_INT_MASK 0x00038000 1511 # define TV_VSCALE_INT_SHIFT 15 1512 /** 1513 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1514 * 1515 * \sa TV_VSCALE_INT_MASK 1516 */ 1517 # define TV_VSCALE_FRAC_MASK 0x00007fff 1518 # define TV_VSCALE_FRAC_SHIFT 0 1519 1520 #define TV_FILTER_CTL_3 0x68088 1521 /** 1522 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1523 * 1524 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 1525 * 1526 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1527 */ 1528 # define TV_VSCALE_IP_INT_MASK 0x00038000 1529 # define TV_VSCALE_IP_INT_SHIFT 15 1530 /** 1531 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1532 * 1533 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1534 * 1535 * \sa TV_VSCALE_IP_INT_MASK 1536 */ 1537 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 1538 # define TV_VSCALE_IP_FRAC_SHIFT 0 1539 1540 #define TV_CC_CONTROL 0x68090 1541 # define TV_CC_ENABLE (1 << 31) 1542 /** 1543 * Specifies which field to send the CC data in. 1544 * 1545 * CC data is usually sent in field 0. 1546 */ 1547 # define TV_CC_FID_MASK (1 << 27) 1548 # define TV_CC_FID_SHIFT 27 1549 /** Sets the horizontal position of the CC data. Usually 135. */ 1550 # define TV_CC_HOFF_MASK 0x03ff0000 1551 # define TV_CC_HOFF_SHIFT 16 1552 /** Sets the vertical position of the CC data. Usually 21 */ 1553 # define TV_CC_LINE_MASK 0x0000003f 1554 # define TV_CC_LINE_SHIFT 0 1555 1556 #define TV_CC_DATA 0x68094 1557 # define TV_CC_RDY (1 << 31) 1558 /** Second word of CC data to be transmitted. */ 1559 # define TV_CC_DATA_2_MASK 0x007f0000 1560 # define TV_CC_DATA_2_SHIFT 16 1561 /** First word of CC data to be transmitted. */ 1562 # define TV_CC_DATA_1_MASK 0x0000007f 1563 # define TV_CC_DATA_1_SHIFT 0 1564 1565 #define TV_H_LUMA_0 0x68100 1566 #define TV_H_LUMA_59 0x681ec 1567 #define TV_H_CHROMA_0 0x68200 1568 #define TV_H_CHROMA_59 0x682ec 1569 #define TV_V_LUMA_0 0x68300 1570 #define TV_V_LUMA_42 0x683a8 1571 #define TV_V_CHROMA_0 0x68400 1572 #define TV_V_CHROMA_42 0x684a8 1573 1574 /* Display Port */ 1575 #define DP_A 0x64000 /* eDP */ 1576 #define DP_B 0x64100 1577 #define DP_C 0x64200 1578 #define DP_D 0x64300 1579 1580 #define DP_PORT_EN (1 << 31) 1581 #define DP_PIPEB_SELECT (1 << 30) 1582 1583 /* Link training mode - select a suitable mode for each stage */ 1584 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 1585 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 1586 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 1587 #define DP_LINK_TRAIN_OFF (3 << 28) 1588 #define DP_LINK_TRAIN_MASK (3 << 28) 1589 #define DP_LINK_TRAIN_SHIFT 28 1590 1591 /* Signal voltages. These are mostly controlled by the other end */ 1592 #define DP_VOLTAGE_0_4 (0 << 25) 1593 #define DP_VOLTAGE_0_6 (1 << 25) 1594 #define DP_VOLTAGE_0_8 (2 << 25) 1595 #define DP_VOLTAGE_1_2 (3 << 25) 1596 #define DP_VOLTAGE_MASK (7 << 25) 1597 #define DP_VOLTAGE_SHIFT 25 1598 1599 /* Signal pre-emphasis levels, like voltages, the other end tells us what 1600 * they want 1601 */ 1602 #define DP_PRE_EMPHASIS_0 (0 << 22) 1603 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 1604 #define DP_PRE_EMPHASIS_6 (2 << 22) 1605 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 1606 #define DP_PRE_EMPHASIS_MASK (7 << 22) 1607 #define DP_PRE_EMPHASIS_SHIFT 22 1608 1609 /* How many wires to use. I guess 3 was too hard */ 1610 #define DP_PORT_WIDTH_1 (0 << 19) 1611 #define DP_PORT_WIDTH_2 (1 << 19) 1612 #define DP_PORT_WIDTH_4 (3 << 19) 1613 #define DP_PORT_WIDTH_MASK (7 << 19) 1614 1615 /* Mystic DPCD version 1.1 special mode */ 1616 #define DP_ENHANCED_FRAMING (1 << 18) 1617 1618 /* eDP */ 1619 #define DP_PLL_FREQ_270MHZ (0 << 16) 1620 #define DP_PLL_FREQ_160MHZ (1 << 16) 1621 #define DP_PLL_FREQ_MASK (3 << 16) 1622 1623 /** locked once port is enabled */ 1624 #define DP_PORT_REVERSAL (1 << 15) 1625 1626 /* eDP */ 1627 #define DP_PLL_ENABLE (1 << 14) 1628 1629 /** sends the clock on lane 15 of the PEG for debug */ 1630 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1631 1632 #define DP_SCRAMBLING_DISABLE (1 << 12) 1633 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 1634 1635 /** limit RGB values to avoid confusing TVs */ 1636 #define DP_COLOR_RANGE_16_235 (1 << 8) 1637 1638 /** Turn on the audio link */ 1639 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 1640 1641 /** vs and hs sync polarity */ 1642 #define DP_SYNC_VS_HIGH (1 << 4) 1643 #define DP_SYNC_HS_HIGH (1 << 3) 1644 1645 /** A fantasy */ 1646 #define DP_DETECTED (1 << 2) 1647 1648 /** The aux channel provides a way to talk to the 1649 * signal sink for DDC etc. Max packet size supported 1650 * is 20 bytes in each direction, hence the 5 fixed 1651 * data registers 1652 */ 1653 #define DPA_AUX_CH_CTL 0x64010 1654 #define DPA_AUX_CH_DATA1 0x64014 1655 #define DPA_AUX_CH_DATA2 0x64018 1656 #define DPA_AUX_CH_DATA3 0x6401c 1657 #define DPA_AUX_CH_DATA4 0x64020 1658 #define DPA_AUX_CH_DATA5 0x64024 1659 1660 #define DPB_AUX_CH_CTL 0x64110 1661 #define DPB_AUX_CH_DATA1 0x64114 1662 #define DPB_AUX_CH_DATA2 0x64118 1663 #define DPB_AUX_CH_DATA3 0x6411c 1664 #define DPB_AUX_CH_DATA4 0x64120 1665 #define DPB_AUX_CH_DATA5 0x64124 1666 1667 #define DPC_AUX_CH_CTL 0x64210 1668 #define DPC_AUX_CH_DATA1 0x64214 1669 #define DPC_AUX_CH_DATA2 0x64218 1670 #define DPC_AUX_CH_DATA3 0x6421c 1671 #define DPC_AUX_CH_DATA4 0x64220 1672 #define DPC_AUX_CH_DATA5 0x64224 1673 1674 #define DPD_AUX_CH_CTL 0x64310 1675 #define DPD_AUX_CH_DATA1 0x64314 1676 #define DPD_AUX_CH_DATA2 0x64318 1677 #define DPD_AUX_CH_DATA3 0x6431c 1678 #define DPD_AUX_CH_DATA4 0x64320 1679 #define DPD_AUX_CH_DATA5 0x64324 1680 1681 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 1682 #define DP_AUX_CH_CTL_DONE (1 << 30) 1683 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 1684 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 1685 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 1686 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 1687 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 1688 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 1689 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 1690 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 1691 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 1692 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 1693 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 1694 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 1695 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 1696 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 1697 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 1698 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 1699 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 1700 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 1701 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 1702 1703 /* 1704 * Computing GMCH M and N values for the Display Port link 1705 * 1706 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 1707 * 1708 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 1709 * 1710 * The GMCH value is used internally 1711 * 1712 * bytes_per_pixel is the number of bytes coming out of the plane, 1713 * which is after the LUTs, so we want the bytes for our color format. 1714 * For our current usage, this is always 3, one byte for R, G and B. 1715 */ 1716 #define PIPEA_GMCH_DATA_M 0x70050 1717 #define PIPEB_GMCH_DATA_M 0x71050 1718 1719 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 1720 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 1721 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 1722 1723 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 1724 1725 #define PIPEA_GMCH_DATA_N 0x70054 1726 #define PIPEB_GMCH_DATA_N 0x71054 1727 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 1728 1729 /* 1730 * Computing Link M and N values for the Display Port link 1731 * 1732 * Link M / N = pixel_clock / ls_clk 1733 * 1734 * (the DP spec calls pixel_clock the 'strm_clk') 1735 * 1736 * The Link value is transmitted in the Main Stream 1737 * Attributes and VB-ID. 1738 */ 1739 1740 #define PIPEA_DP_LINK_M 0x70060 1741 #define PIPEB_DP_LINK_M 0x71060 1742 #define PIPEA_DP_LINK_M_MASK (0xffffff) 1743 1744 #define PIPEA_DP_LINK_N 0x70064 1745 #define PIPEB_DP_LINK_N 0x71064 1746 #define PIPEA_DP_LINK_N_MASK (0xffffff) 1747 1748 /* Display & cursor control */ 1749 1750 /* dithering flag on Ironlake */ 1751 #define PIPE_ENABLE_DITHER (1 << 4) 1752 /* Pipe A */ 1753 #define PIPEADSL 0x70000 1754 #define PIPEACONF 0x70008 1755 #define PIPEACONF_ENABLE (1<<31) 1756 #define PIPEACONF_DISABLE 0 1757 #define PIPEACONF_DOUBLE_WIDE (1<<30) 1758 #define I965_PIPECONF_ACTIVE (1<<30) 1759 #define PIPEACONF_SINGLE_WIDE 0 1760 #define PIPEACONF_PIPE_UNLOCKED 0 1761 #define PIPEACONF_PIPE_LOCKED (1<<25) 1762 #define PIPEACONF_PALETTE 0 1763 #define PIPEACONF_GAMMA (1<<24) 1764 #define PIPECONF_FORCE_BORDER (1<<25) 1765 #define PIPECONF_PROGRESSIVE (0 << 21) 1766 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1767 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1768 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 1769 #define PIPEASTAT 0x70024 1770 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 1771 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 1772 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 1773 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 1774 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 1775 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1776 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1777 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 1778 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1779 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1780 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1781 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 1782 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1783 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1784 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 1785 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1786 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1787 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 1788 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 1789 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 1790 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1791 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 1792 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1793 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1794 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1795 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 1796 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1797 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1798 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 1799 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 1800 #define PIPE_8BPC (0 << 5) 1801 #define PIPE_10BPC (1 << 5) 1802 #define PIPE_6BPC (2 << 5) 1803 #define PIPE_12BPC (3 << 5) 1804 1805 #define DSPARB 0x70030 1806 #define DSPARB_CSTART_MASK (0x7f << 7) 1807 #define DSPARB_CSTART_SHIFT 7 1808 #define DSPARB_BSTART_MASK (0x7f) 1809 #define DSPARB_BSTART_SHIFT 0 1810 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 1811 #define DSPARB_AEND_SHIFT 0 1812 1813 #define DSPFW1 0x70034 1814 #define DSPFW_SR_SHIFT 23 1815 #define DSPFW_CURSORB_SHIFT 16 1816 #define DSPFW_PLANEB_SHIFT 8 1817 #define DSPFW2 0x70038 1818 #define DSPFW_CURSORA_MASK 0x00003f00 1819 #define DSPFW_CURSORA_SHIFT 8 1820 #define DSPFW3 0x7003c 1821 #define DSPFW_HPLL_SR_EN (1<<31) 1822 #define DSPFW_CURSOR_SR_SHIFT 24 1823 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 1824 1825 /* FIFO watermark sizes etc */ 1826 #define G4X_FIFO_LINE_SIZE 64 1827 #define I915_FIFO_LINE_SIZE 64 1828 #define I830_FIFO_LINE_SIZE 32 1829 1830 #define G4X_FIFO_SIZE 127 1831 #define I945_FIFO_SIZE 127 /* 945 & 965 */ 1832 #define I915_FIFO_SIZE 95 1833 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 1834 #define I830_FIFO_SIZE 95 1835 1836 #define G4X_MAX_WM 0x3f 1837 #define I915_MAX_WM 0x3f 1838 1839 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 1840 #define PINEVIEW_FIFO_LINE_SIZE 64 1841 #define PINEVIEW_MAX_WM 0x1ff 1842 #define PINEVIEW_DFT_WM 0x3f 1843 #define PINEVIEW_DFT_HPLLOFF_WM 0 1844 #define PINEVIEW_GUARD_WM 10 1845 #define PINEVIEW_CURSOR_FIFO 64 1846 #define PINEVIEW_CURSOR_MAX_WM 0x3f 1847 #define PINEVIEW_CURSOR_DFT_WM 0 1848 #define PINEVIEW_CURSOR_GUARD_WM 5 1849 1850 /* 1851 * The two pipe frame counter registers are not synchronized, so 1852 * reading a stable value is somewhat tricky. The following code 1853 * should work: 1854 * 1855 * do { 1856 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1857 * PIPE_FRAME_HIGH_SHIFT; 1858 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 1859 * PIPE_FRAME_LOW_SHIFT); 1860 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1861 * PIPE_FRAME_HIGH_SHIFT); 1862 * } while (high1 != high2); 1863 * frame = (high1 << 8) | low1; 1864 */ 1865 #define PIPEAFRAMEHIGH 0x70040 1866 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 1867 #define PIPE_FRAME_HIGH_SHIFT 0 1868 #define PIPEAFRAMEPIXEL 0x70044 1869 #define PIPE_FRAME_LOW_MASK 0xff000000 1870 #define PIPE_FRAME_LOW_SHIFT 24 1871 #define PIPE_PIXEL_MASK 0x00ffffff 1872 #define PIPE_PIXEL_SHIFT 0 1873 /* GM45+ just has to be different */ 1874 #define PIPEA_FRMCOUNT_GM45 0x70040 1875 #define PIPEA_FLIPCOUNT_GM45 0x70044 1876 1877 /* Cursor A & B regs */ 1878 #define CURACNTR 0x70080 1879 /* Old style CUR*CNTR flags (desktop 8xx) */ 1880 #define CURSOR_ENABLE 0x80000000 1881 #define CURSOR_GAMMA_ENABLE 0x40000000 1882 #define CURSOR_STRIDE_MASK 0x30000000 1883 #define CURSOR_FORMAT_SHIFT 24 1884 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 1885 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 1886 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 1887 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 1888 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 1889 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 1890 /* New style CUR*CNTR flags */ 1891 #define CURSOR_MODE 0x27 1892 #define CURSOR_MODE_DISABLE 0x00 1893 #define CURSOR_MODE_64_32B_AX 0x07 1894 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 1895 #define MCURSOR_PIPE_SELECT (1 << 28) 1896 #define MCURSOR_PIPE_A 0x00 1897 #define MCURSOR_PIPE_B (1 << 28) 1898 #define MCURSOR_GAMMA_ENABLE (1 << 26) 1899 #define CURABASE 0x70084 1900 #define CURAPOS 0x70088 1901 #define CURSOR_POS_MASK 0x007FF 1902 #define CURSOR_POS_SIGN 0x8000 1903 #define CURSOR_X_SHIFT 0 1904 #define CURSOR_Y_SHIFT 16 1905 #define CURSIZE 0x700a0 1906 #define CURBCNTR 0x700c0 1907 #define CURBBASE 0x700c4 1908 #define CURBPOS 0x700c8 1909 1910 /* Display A control */ 1911 #define DSPACNTR 0x70180 1912 #define DISPLAY_PLANE_ENABLE (1<<31) 1913 #define DISPLAY_PLANE_DISABLE 0 1914 #define DISPPLANE_GAMMA_ENABLE (1<<30) 1915 #define DISPPLANE_GAMMA_DISABLE 0 1916 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1917 #define DISPPLANE_8BPP (0x2<<26) 1918 #define DISPPLANE_15_16BPP (0x4<<26) 1919 #define DISPPLANE_16BPP (0x5<<26) 1920 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1921 #define DISPPLANE_32BPP (0x7<<26) 1922 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 1923 #define DISPPLANE_STEREO_ENABLE (1<<25) 1924 #define DISPPLANE_STEREO_DISABLE 0 1925 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 1926 #define DISPPLANE_SEL_PIPE_A 0 1927 #define DISPPLANE_SEL_PIPE_B (1<<24) 1928 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1929 #define DISPPLANE_SRC_KEY_DISABLE 0 1930 #define DISPPLANE_LINE_DOUBLE (1<<20) 1931 #define DISPPLANE_NO_LINE_DOUBLE 0 1932 #define DISPPLANE_STEREO_POLARITY_FIRST 0 1933 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1934 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 1935 #define DISPPLANE_TILED (1<<10) 1936 #define DSPAADDR 0x70184 1937 #define DSPASTRIDE 0x70188 1938 #define DSPAPOS 0x7018C /* reserved */ 1939 #define DSPASIZE 0x70190 1940 #define DSPASURF 0x7019C /* 965+ only */ 1941 #define DSPATILEOFF 0x701A4 /* 965+ only */ 1942 1943 /* VBIOS flags */ 1944 #define SWF00 0x71410 1945 #define SWF01 0x71414 1946 #define SWF02 0x71418 1947 #define SWF03 0x7141c 1948 #define SWF04 0x71420 1949 #define SWF05 0x71424 1950 #define SWF06 0x71428 1951 #define SWF10 0x70410 1952 #define SWF11 0x70414 1953 #define SWF14 0x71420 1954 #define SWF30 0x72414 1955 #define SWF31 0x72418 1956 #define SWF32 0x7241c 1957 1958 /* Pipe B */ 1959 #define PIPEBDSL 0x71000 1960 #define PIPEBCONF 0x71008 1961 #define PIPEBSTAT 0x71024 1962 #define PIPEBFRAMEHIGH 0x71040 1963 #define PIPEBFRAMEPIXEL 0x71044 1964 #define PIPEB_FRMCOUNT_GM45 0x71040 1965 #define PIPEB_FLIPCOUNT_GM45 0x71044 1966 1967 1968 /* Display B control */ 1969 #define DSPBCNTR 0x71180 1970 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1971 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 1972 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 1973 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1974 #define DSPBADDR 0x71184 1975 #define DSPBSTRIDE 0x71188 1976 #define DSPBPOS 0x7118C 1977 #define DSPBSIZE 0x71190 1978 #define DSPBSURF 0x7119C 1979 #define DSPBTILEOFF 0x711A4 1980 1981 /* VBIOS regs */ 1982 #define VGACNTRL 0x71400 1983 # define VGA_DISP_DISABLE (1 << 31) 1984 # define VGA_2X_MODE (1 << 30) 1985 # define VGA_PIPE_B_SELECT (1 << 29) 1986 1987 /* Ironlake */ 1988 1989 #define CPU_VGACNTRL 0x41000 1990 1991 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 1992 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 1993 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 1994 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 1995 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 1996 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 1997 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 1998 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 1999 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2000 2001 /* refresh rate hardware control */ 2002 #define RR_HW_CTL 0x45300 2003 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2004 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2005 2006 #define FDI_PLL_BIOS_0 0x46000 2007 #define FDI_PLL_BIOS_1 0x46004 2008 #define FDI_PLL_BIOS_2 0x46008 2009 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2010 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2011 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2012 2013 #define FDI_PLL_FREQ_CTL 0x46030 2014 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2015 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2016 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2017 2018 2019 #define PIPEA_DATA_M1 0x60030 2020 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2021 #define TU_SIZE_MASK 0x7e000000 2022 #define PIPEA_DATA_M1_OFFSET 0 2023 #define PIPEA_DATA_N1 0x60034 2024 #define PIPEA_DATA_N1_OFFSET 0 2025 2026 #define PIPEA_DATA_M2 0x60038 2027 #define PIPEA_DATA_M2_OFFSET 0 2028 #define PIPEA_DATA_N2 0x6003c 2029 #define PIPEA_DATA_N2_OFFSET 0 2030 2031 #define PIPEA_LINK_M1 0x60040 2032 #define PIPEA_LINK_M1_OFFSET 0 2033 #define PIPEA_LINK_N1 0x60044 2034 #define PIPEA_LINK_N1_OFFSET 0 2035 2036 #define PIPEA_LINK_M2 0x60048 2037 #define PIPEA_LINK_M2_OFFSET 0 2038 #define PIPEA_LINK_N2 0x6004c 2039 #define PIPEA_LINK_N2_OFFSET 0 2040 2041 /* PIPEB timing regs are same start from 0x61000 */ 2042 2043 #define PIPEB_DATA_M1 0x61030 2044 #define PIPEB_DATA_M1_OFFSET 0 2045 #define PIPEB_DATA_N1 0x61034 2046 #define PIPEB_DATA_N1_OFFSET 0 2047 2048 #define PIPEB_DATA_M2 0x61038 2049 #define PIPEB_DATA_M2_OFFSET 0 2050 #define PIPEB_DATA_N2 0x6103c 2051 #define PIPEB_DATA_N2_OFFSET 0 2052 2053 #define PIPEB_LINK_M1 0x61040 2054 #define PIPEB_LINK_M1_OFFSET 0 2055 #define PIPEB_LINK_N1 0x61044 2056 #define PIPEB_LINK_N1_OFFSET 0 2057 2058 #define PIPEB_LINK_M2 0x61048 2059 #define PIPEB_LINK_M2_OFFSET 0 2060 #define PIPEB_LINK_N2 0x6104c 2061 #define PIPEB_LINK_N2_OFFSET 0 2062 2063 /* CPU panel fitter */ 2064 #define PFA_CTL_1 0x68080 2065 #define PFB_CTL_1 0x68880 2066 #define PF_ENABLE (1<<31) 2067 #define PF_FILTER_MASK (3<<23) 2068 #define PF_FILTER_PROGRAMMED (0<<23) 2069 #define PF_FILTER_MED_3x3 (1<<23) 2070 #define PF_FILTER_EDGE_ENHANCE (2<<23) 2071 #define PF_FILTER_EDGE_SOFTEN (3<<23) 2072 #define PFA_WIN_SZ 0x68074 2073 #define PFB_WIN_SZ 0x68874 2074 #define PFA_WIN_POS 0x68070 2075 #define PFB_WIN_POS 0x68870 2076 2077 /* legacy palette */ 2078 #define LGC_PALETTE_A 0x4a000 2079 #define LGC_PALETTE_B 0x4a800 2080 2081 /* interrupts */ 2082 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2083 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2084 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2085 #define DE_PLANEB_FLIP_DONE (1 << 27) 2086 #define DE_PLANEA_FLIP_DONE (1 << 26) 2087 #define DE_PCU_EVENT (1 << 25) 2088 #define DE_GTT_FAULT (1 << 24) 2089 #define DE_POISON (1 << 23) 2090 #define DE_PERFORM_COUNTER (1 << 22) 2091 #define DE_PCH_EVENT (1 << 21) 2092 #define DE_AUX_CHANNEL_A (1 << 20) 2093 #define DE_DP_A_HOTPLUG (1 << 19) 2094 #define DE_GSE (1 << 18) 2095 #define DE_PIPEB_VBLANK (1 << 15) 2096 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2097 #define DE_PIPEB_ODD_FIELD (1 << 13) 2098 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2099 #define DE_PIPEB_VSYNC (1 << 11) 2100 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2101 #define DE_PIPEA_VBLANK (1 << 7) 2102 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2103 #define DE_PIPEA_ODD_FIELD (1 << 5) 2104 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2105 #define DE_PIPEA_VSYNC (1 << 3) 2106 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2107 2108 #define DEISR 0x44000 2109 #define DEIMR 0x44004 2110 #define DEIIR 0x44008 2111 #define DEIER 0x4400c 2112 2113 /* GT interrupt */ 2114 #define GT_SYNC_STATUS (1 << 2) 2115 #define GT_USER_INTERRUPT (1 << 0) 2116 2117 #define GTISR 0x44010 2118 #define GTIMR 0x44014 2119 #define GTIIR 0x44018 2120 #define GTIER 0x4401c 2121 2122 #define DISP_ARB_CTL 0x45000 2123 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 2124 2125 /* PCH */ 2126 2127 /* south display engine interrupt */ 2128 #define SDE_CRT_HOTPLUG (1 << 11) 2129 #define SDE_PORTD_HOTPLUG (1 << 10) 2130 #define SDE_PORTC_HOTPLUG (1 << 9) 2131 #define SDE_PORTB_HOTPLUG (1 << 8) 2132 #define SDE_SDVOB_HOTPLUG (1 << 6) 2133 #define SDE_HOTPLUG_MASK (0xf << 8) 2134 2135 #define SDEISR 0xc4000 2136 #define SDEIMR 0xc4004 2137 #define SDEIIR 0xc4008 2138 #define SDEIER 0xc400c 2139 2140 /* digital port hotplug */ 2141 #define PCH_PORT_HOTPLUG 0xc4030 2142 #define PORTD_HOTPLUG_ENABLE (1 << 20) 2143 #define PORTD_PULSE_DURATION_2ms (0) 2144 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 2145 #define PORTD_PULSE_DURATION_6ms (2 << 18) 2146 #define PORTD_PULSE_DURATION_100ms (3 << 18) 2147 #define PORTD_HOTPLUG_NO_DETECT (0) 2148 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 2149 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 2150 #define PORTC_HOTPLUG_ENABLE (1 << 12) 2151 #define PORTC_PULSE_DURATION_2ms (0) 2152 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 2153 #define PORTC_PULSE_DURATION_6ms (2 << 10) 2154 #define PORTC_PULSE_DURATION_100ms (3 << 10) 2155 #define PORTC_HOTPLUG_NO_DETECT (0) 2156 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 2157 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 2158 #define PORTB_HOTPLUG_ENABLE (1 << 4) 2159 #define PORTB_PULSE_DURATION_2ms (0) 2160 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 2161 #define PORTB_PULSE_DURATION_6ms (2 << 2) 2162 #define PORTB_PULSE_DURATION_100ms (3 << 2) 2163 #define PORTB_HOTPLUG_NO_DETECT (0) 2164 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 2165 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 2166 2167 #define PCH_GPIOA 0xc5010 2168 #define PCH_GPIOB 0xc5014 2169 #define PCH_GPIOC 0xc5018 2170 #define PCH_GPIOD 0xc501c 2171 #define PCH_GPIOE 0xc5020 2172 #define PCH_GPIOF 0xc5024 2173 2174 #define PCH_GMBUS0 0xc5100 2175 #define PCH_GMBUS1 0xc5104 2176 #define PCH_GMBUS2 0xc5108 2177 #define PCH_GMBUS3 0xc510c 2178 #define PCH_GMBUS4 0xc5110 2179 #define PCH_GMBUS5 0xc5120 2180 2181 #define PCH_DPLL_A 0xc6014 2182 #define PCH_DPLL_B 0xc6018 2183 2184 #define PCH_FPA0 0xc6040 2185 #define PCH_FPA1 0xc6044 2186 #define PCH_FPB0 0xc6048 2187 #define PCH_FPB1 0xc604c 2188 2189 #define PCH_DPLL_TEST 0xc606c 2190 2191 #define PCH_DREF_CONTROL 0xC6200 2192 #define DREF_CONTROL_MASK 0x7fc3 2193 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 2194 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 2195 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 2196 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 2197 #define DREF_SSC_SOURCE_DISABLE (0<<11) 2198 #define DREF_SSC_SOURCE_ENABLE (2<<11) 2199 #define DREF_SSC_SOURCE_MASK (3<<11) 2200 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 2201 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 2202 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 2203 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 2204 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2205 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2206 #define DREF_SSC4_DOWNSPREAD (0<<6) 2207 #define DREF_SSC4_CENTERSPREAD (1<<6) 2208 #define DREF_SSC1_DISABLE (0<<1) 2209 #define DREF_SSC1_ENABLE (1<<1) 2210 #define DREF_SSC4_DISABLE (0) 2211 #define DREF_SSC4_ENABLE (1) 2212 2213 #define PCH_RAWCLK_FREQ 0xc6204 2214 #define FDL_TP1_TIMER_SHIFT 12 2215 #define FDL_TP1_TIMER_MASK (3<<12) 2216 #define FDL_TP2_TIMER_SHIFT 10 2217 #define FDL_TP2_TIMER_MASK (3<<10) 2218 #define RAWCLK_FREQ_MASK 0x3ff 2219 2220 #define PCH_DPLL_TMR_CFG 0xc6208 2221 2222 #define PCH_SSC4_PARMS 0xc6210 2223 #define PCH_SSC4_AUX_PARMS 0xc6214 2224 2225 /* transcoder */ 2226 2227 #define TRANS_HTOTAL_A 0xe0000 2228 #define TRANS_HTOTAL_SHIFT 16 2229 #define TRANS_HACTIVE_SHIFT 0 2230 #define TRANS_HBLANK_A 0xe0004 2231 #define TRANS_HBLANK_END_SHIFT 16 2232 #define TRANS_HBLANK_START_SHIFT 0 2233 #define TRANS_HSYNC_A 0xe0008 2234 #define TRANS_HSYNC_END_SHIFT 16 2235 #define TRANS_HSYNC_START_SHIFT 0 2236 #define TRANS_VTOTAL_A 0xe000c 2237 #define TRANS_VTOTAL_SHIFT 16 2238 #define TRANS_VACTIVE_SHIFT 0 2239 #define TRANS_VBLANK_A 0xe0010 2240 #define TRANS_VBLANK_END_SHIFT 16 2241 #define TRANS_VBLANK_START_SHIFT 0 2242 #define TRANS_VSYNC_A 0xe0014 2243 #define TRANS_VSYNC_END_SHIFT 16 2244 #define TRANS_VSYNC_START_SHIFT 0 2245 2246 #define TRANSA_DATA_M1 0xe0030 2247 #define TRANSA_DATA_N1 0xe0034 2248 #define TRANSA_DATA_M2 0xe0038 2249 #define TRANSA_DATA_N2 0xe003c 2250 #define TRANSA_DP_LINK_M1 0xe0040 2251 #define TRANSA_DP_LINK_N1 0xe0044 2252 #define TRANSA_DP_LINK_M2 0xe0048 2253 #define TRANSA_DP_LINK_N2 0xe004c 2254 2255 #define TRANS_HTOTAL_B 0xe1000 2256 #define TRANS_HBLANK_B 0xe1004 2257 #define TRANS_HSYNC_B 0xe1008 2258 #define TRANS_VTOTAL_B 0xe100c 2259 #define TRANS_VBLANK_B 0xe1010 2260 #define TRANS_VSYNC_B 0xe1014 2261 2262 #define TRANSB_DATA_M1 0xe1030 2263 #define TRANSB_DATA_N1 0xe1034 2264 #define TRANSB_DATA_M2 0xe1038 2265 #define TRANSB_DATA_N2 0xe103c 2266 #define TRANSB_DP_LINK_M1 0xe1040 2267 #define TRANSB_DP_LINK_N1 0xe1044 2268 #define TRANSB_DP_LINK_M2 0xe1048 2269 #define TRANSB_DP_LINK_N2 0xe104c 2270 2271 #define TRANSACONF 0xf0008 2272 #define TRANSBCONF 0xf1008 2273 #define TRANS_DISABLE (0<<31) 2274 #define TRANS_ENABLE (1<<31) 2275 #define TRANS_STATE_MASK (1<<30) 2276 #define TRANS_STATE_DISABLE (0<<30) 2277 #define TRANS_STATE_ENABLE (1<<30) 2278 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 2279 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 2280 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 2281 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 2282 #define TRANS_DP_AUDIO_ONLY (1<<26) 2283 #define TRANS_DP_VIDEO_AUDIO (0<<26) 2284 #define TRANS_PROGRESSIVE (0<<21) 2285 #define TRANS_8BPC (0<<5) 2286 #define TRANS_10BPC (1<<5) 2287 #define TRANS_6BPC (2<<5) 2288 #define TRANS_12BPC (3<<5) 2289 2290 #define FDI_RXA_CHICKEN 0xc200c 2291 #define FDI_RXB_CHICKEN 0xc2010 2292 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 2293 2294 /* CPU: FDI_TX */ 2295 #define FDI_TXA_CTL 0x60100 2296 #define FDI_TXB_CTL 0x61100 2297 #define FDI_TX_DISABLE (0<<31) 2298 #define FDI_TX_ENABLE (1<<31) 2299 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 2300 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 2301 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 2302 #define FDI_LINK_TRAIN_NONE (3<<28) 2303 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 2304 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 2305 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 2306 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 2307 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 2308 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 2309 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 2310 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 2311 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 2312 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 2313 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 2314 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 2315 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 2316 /* Ironlake: hardwired to 1 */ 2317 #define FDI_TX_PLL_ENABLE (1<<14) 2318 /* both Tx and Rx */ 2319 #define FDI_SCRAMBLING_ENABLE (0<<7) 2320 #define FDI_SCRAMBLING_DISABLE (1<<7) 2321 2322 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 2323 #define FDI_RXA_CTL 0xf000c 2324 #define FDI_RXB_CTL 0xf100c 2325 #define FDI_RX_ENABLE (1<<31) 2326 #define FDI_RX_DISABLE (0<<31) 2327 /* train, dp width same as FDI_TX */ 2328 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 2329 #define FDI_8BPC (0<<16) 2330 #define FDI_10BPC (1<<16) 2331 #define FDI_6BPC (2<<16) 2332 #define FDI_12BPC (3<<16) 2333 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 2334 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 2335 #define FDI_RX_PLL_ENABLE (1<<13) 2336 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 2337 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 2338 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 2339 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 2340 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 2341 #define FDI_SEL_RAWCLK (0<<4) 2342 #define FDI_SEL_PCDCLK (1<<4) 2343 2344 #define FDI_RXA_MISC 0xf0010 2345 #define FDI_RXB_MISC 0xf1010 2346 #define FDI_RXA_TUSIZE1 0xf0030 2347 #define FDI_RXA_TUSIZE2 0xf0038 2348 #define FDI_RXB_TUSIZE1 0xf1030 2349 #define FDI_RXB_TUSIZE2 0xf1038 2350 2351 /* FDI_RX interrupt register format */ 2352 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 2353 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 2354 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 2355 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 2356 #define FDI_RX_FS_CODE_ERR (1<<6) 2357 #define FDI_RX_FE_CODE_ERR (1<<5) 2358 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 2359 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 2360 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 2361 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 2362 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 2363 2364 #define FDI_RXA_IIR 0xf0014 2365 #define FDI_RXA_IMR 0xf0018 2366 #define FDI_RXB_IIR 0xf1014 2367 #define FDI_RXB_IMR 0xf1018 2368 2369 #define FDI_PLL_CTL_1 0xfe000 2370 #define FDI_PLL_CTL_2 0xfe004 2371 2372 /* CRT */ 2373 #define PCH_ADPA 0xe1100 2374 #define ADPA_TRANS_SELECT_MASK (1<<30) 2375 #define ADPA_TRANS_A_SELECT 0 2376 #define ADPA_TRANS_B_SELECT (1<<30) 2377 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2378 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 2379 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 2380 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 2381 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 2382 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 2383 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 2384 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 2385 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 2386 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 2387 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 2388 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 2389 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 2390 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 2391 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 2392 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 2393 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 2394 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 2395 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 2396 2397 /* or SDVOB */ 2398 #define HDMIB 0xe1140 2399 #define PORT_ENABLE (1 << 31) 2400 #define TRANSCODER_A (0) 2401 #define TRANSCODER_B (1 << 30) 2402 #define COLOR_FORMAT_8bpc (0) 2403 #define COLOR_FORMAT_12bpc (3 << 26) 2404 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 2405 #define SDVO_ENCODING (0) 2406 #define TMDS_ENCODING (2 << 10) 2407 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 2408 #define SDVOB_BORDER_ENABLE (1 << 7) 2409 #define AUDIO_ENABLE (1 << 6) 2410 #define VSYNC_ACTIVE_HIGH (1 << 4) 2411 #define HSYNC_ACTIVE_HIGH (1 << 3) 2412 #define PORT_DETECTED (1 << 2) 2413 2414 #define HDMIC 0xe1150 2415 #define HDMID 0xe1160 2416 2417 #define PCH_LVDS 0xe1180 2418 #define LVDS_DETECTED (1 << 1) 2419 2420 #define BLC_PWM_CPU_CTL2 0x48250 2421 #define PWM_ENABLE (1 << 31) 2422 #define PWM_PIPE_A (0 << 29) 2423 #define PWM_PIPE_B (1 << 29) 2424 #define BLC_PWM_CPU_CTL 0x48254 2425 2426 #define BLC_PWM_PCH_CTL1 0xc8250 2427 #define PWM_PCH_ENABLE (1 << 31) 2428 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 2429 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 2430 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 2431 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 2432 2433 #define BLC_PWM_PCH_CTL2 0xc8254 2434 2435 #define PCH_PP_STATUS 0xc7200 2436 #define PCH_PP_CONTROL 0xc7204 2437 #define EDP_FORCE_VDD (1 << 3) 2438 #define EDP_BLC_ENABLE (1 << 2) 2439 #define PANEL_POWER_RESET (1 << 1) 2440 #define PANEL_POWER_OFF (0 << 0) 2441 #define PANEL_POWER_ON (1 << 0) 2442 #define PCH_PP_ON_DELAYS 0xc7208 2443 #define EDP_PANEL (1 << 30) 2444 #define PCH_PP_OFF_DELAYS 0xc720c 2445 #define PCH_PP_DIVISOR 0xc7210 2446 2447 #define PCH_DP_B 0xe4100 2448 #define PCH_DPB_AUX_CH_CTL 0xe4110 2449 #define PCH_DPB_AUX_CH_DATA1 0xe4114 2450 #define PCH_DPB_AUX_CH_DATA2 0xe4118 2451 #define PCH_DPB_AUX_CH_DATA3 0xe411c 2452 #define PCH_DPB_AUX_CH_DATA4 0xe4120 2453 #define PCH_DPB_AUX_CH_DATA5 0xe4124 2454 2455 #define PCH_DP_C 0xe4200 2456 #define PCH_DPC_AUX_CH_CTL 0xe4210 2457 #define PCH_DPC_AUX_CH_DATA1 0xe4214 2458 #define PCH_DPC_AUX_CH_DATA2 0xe4218 2459 #define PCH_DPC_AUX_CH_DATA3 0xe421c 2460 #define PCH_DPC_AUX_CH_DATA4 0xe4220 2461 #define PCH_DPC_AUX_CH_DATA5 0xe4224 2462 2463 #define PCH_DP_D 0xe4300 2464 #define PCH_DPD_AUX_CH_CTL 0xe4310 2465 #define PCH_DPD_AUX_CH_DATA1 0xe4314 2466 #define PCH_DPD_AUX_CH_DATA2 0xe4318 2467 #define PCH_DPD_AUX_CH_DATA3 0xe431c 2468 #define PCH_DPD_AUX_CH_DATA4 0xe4320 2469 #define PCH_DPD_AUX_CH_DATA5 0xe4324 2470 2471 #endif /* _I915_REG_H_ */ 2472