xref: /openbmc/linux/drivers/gpu/drm/i915/i915_reg.h (revision b58c6630)
1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2  * All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27 
28 #include <linux/bitfield.h>
29 #include <linux/bits.h>
30 
31 /**
32  * DOC: The i915 register macro definition style guide
33  *
34  * Follow the style described here for new macros, and while changing existing
35  * macros. Do **not** mass change existing definitions just to update the style.
36  *
37  * File Layout
38  * ~~~~~~~~~~~
39  *
40  * Keep helper macros near the top. For example, _PIPE() and friends.
41  *
42  * Prefix macros that generally should not be used outside of this file with
43  * underscore '_'. For example, _PIPE() and friends, single instances of
44  * registers that are defined solely for the use by function-like macros.
45  *
46  * Avoid using the underscore prefixed macros outside of this file. There are
47  * exceptions, but keep them to a minimum.
48  *
49  * There are two basic types of register definitions: Single registers and
50  * register groups. Register groups are registers which have two or more
51  * instances, for example one per pipe, port, transcoder, etc. Register groups
52  * should be defined using function-like macros.
53  *
54  * For single registers, define the register offset first, followed by register
55  * contents.
56  *
57  * For register groups, define the register instance offsets first, prefixed
58  * with underscore, followed by a function-like macro choosing the right
59  * instance based on the parameter, followed by register contents.
60  *
61  * Define the register contents (i.e. bit and bit field macros) from most
62  * significant to least significant bit. Indent the register content macros
63  * using two extra spaces between ``#define`` and the macro name.
64  *
65  * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66  * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67  * shifted in place, so they can be directly OR'd together. For convenience,
68  * function-like macros may be used to define bit fields, but do note that the
69  * macros may be needed to read as well as write the register contents.
70  *
71  * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72  *
73  * Group the register and its contents together without blank lines, separate
74  * from other registers and their contents with one blank line.
75  *
76  * Indent macro values from macro names using TABs. Align values vertically. Use
77  * braces in macro values as needed to avoid unintended precedence after macro
78  * substitution. Use spaces in macro values according to kernel coding
79  * style. Use lower case in hexadecimal values.
80  *
81  * Naming
82  * ~~~~~~
83  *
84  * Try to name registers according to the specs. If the register name changes in
85  * the specs from platform to another, stick to the original name.
86  *
87  * Try to re-use existing register macro definitions. Only add new macros for
88  * new register offsets, or when the register contents have changed enough to
89  * warrant a full redefinition.
90  *
91  * When a register macro changes for a new platform, prefix the new macro using
92  * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93  * prefix signifies the start platform/generation using the register.
94  *
95  * When a bit (field) macro changes or gets added for a new platform, while
96  * retaining the existing register macro, add a platform acronym or generation
97  * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98  *
99  * Examples
100  * ~~~~~~~~
101  *
102  * (Note that the values in the example are indented using spaces instead of
103  * TABs to avoid misalignment in generated documentation. Use TABs in the
104  * definitions.)::
105  *
106  *  #define _FOO_A                      0xf000
107  *  #define _FOO_B                      0xf001
108  *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109  *  #define   FOO_ENABLE                REG_BIT(31)
110  *  #define   FOO_MODE_MASK             REG_GENMASK(19, 16)
111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
112  *  #define   FOO_MODE_BAZ              REG_FIELD_PREP(FOO_MODE_MASK, 1)
113  *  #define   FOO_MODE_QUX_SNB          REG_FIELD_PREP(FOO_MODE_MASK, 2)
114  *
115  *  #define BAR                         _MMIO(0xb000)
116  *  #define GEN8_BAR                    _MMIO(0xb888)
117  */
118 
119 /**
120  * REG_BIT() - Prepare a u32 bit value
121  * @__n: 0-based bit number
122  *
123  * Local wrapper for BIT() to force u32, with compile time checks.
124  *
125  * @return: Value with bit @__n set.
126  */
127 #define REG_BIT(__n)							\
128 	((u32)(BIT(__n) +						\
129 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&		\
130 				 ((__n) < 0 || (__n) > 31))))
131 
132 /**
133  * REG_GENMASK() - Prepare a continuous u32 bitmask
134  * @__high: 0-based high bit
135  * @__low: 0-based low bit
136  *
137  * Local wrapper for GENMASK() to force u32, with compile time checks.
138  *
139  * @return: Continuous bitmask from @__high to @__low, inclusive.
140  */
141 #define REG_GENMASK(__high, __low)					\
142 	((u32)(GENMASK(__high, __low) +					\
143 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&	\
144 				 __is_constexpr(__low) &&		\
145 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146 
147 /*
148  * Local integer constant expression version of is_power_of_2().
149  */
150 #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
151 
152 /**
153  * REG_FIELD_PREP() - Prepare a u32 bitfield value
154  * @__mask: shifted mask defining the field's length and position
155  * @__val: value to put in the field
156  *
157  * Local copy of FIELD_PREP() to generate an integer constant expression, force
158  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
159  *
160  * @return: @__val masked and shifted into the field defined by @__mask.
161  */
162 #define REG_FIELD_PREP(__mask, __val)						\
163 	((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +	\
164 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +		\
165 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
166 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
168 
169 /**
170  * REG_FIELD_GET() - Extract a u32 bitfield value
171  * @__mask: shifted mask defining the field's length and position
172  * @__val: value to extract the bitfield value from
173  *
174  * Local wrapper for FIELD_GET() to force u32 and for consistency with
175  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176  *
177  * @return: Masked and shifted value of the field defined by @__mask in @__val.
178  */
179 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
180 
181 typedef struct {
182 	u32 reg;
183 } i915_reg_t;
184 
185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186 
187 #define INVALID_MMIO_REG _MMIO(0)
188 
189 static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
190 {
191 	return reg.reg;
192 }
193 
194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195 {
196 	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197 }
198 
199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200 {
201 	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202 }
203 
204 #define VLV_DISPLAY_BASE		0x180000
205 #define VLV_MIPI_BASE			VLV_DISPLAY_BASE
206 #define BXT_MIPI_BASE			0x60000
207 
208 #define DISPLAY_MMIO_BASE(dev_priv)	(INTEL_INFO(dev_priv)->display_mmio_offset)
209 
210 /*
211  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212  * numbers, pick the 0-based __index'th value.
213  *
214  * Always prefer this over _PICK() if the numbers are evenly spaced.
215  */
216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
217 
218 /*
219  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
220  *
221  * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
222  */
223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
224 
225 /*
226  * Named helper wrappers around _PICK_EVEN() and _PICK().
227  */
228 #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
229 #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
230 #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
231 #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
232 #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
233 
234 #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
235 #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
236 #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
237 #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
238 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
239 
240 #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
241 
242 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
243 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
244 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
245 #define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
246 
247 /*
248  * Device info offset array based helpers for groups of registers with unevenly
249  * spaced base offsets.
250  */
251 #define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
252 					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
253 					      DISPLAY_MMIO_BASE(dev_priv))
254 #define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
255 					 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
256 					 DISPLAY_MMIO_BASE(dev_priv))
257 #define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))
258 #define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
259 					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
260 					      DISPLAY_MMIO_BASE(dev_priv))
261 
262 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
263 #define _MASKED_FIELD(mask, value) ({					   \
264 	if (__builtin_constant_p(mask))					   \
265 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
266 	if (__builtin_constant_p(value))				   \
267 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
268 	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
269 		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
270 				 "Incorrect value for mask");		   \
271 	__MASKED_FIELD(mask, value); })
272 #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
273 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
274 
275 /* PCI config space */
276 
277 #define MCHBAR_I915 0x44
278 #define MCHBAR_I965 0x48
279 #define MCHBAR_SIZE (4 * 4096)
280 
281 #define DEVEN 0x54
282 #define   DEVEN_MCHBAR_EN (1 << 28)
283 
284 /* BSM in include/drm/i915_drm.h */
285 
286 #define HPLLCC	0xc0 /* 85x only */
287 #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
288 #define   GC_CLOCK_133_200		(0 << 0)
289 #define   GC_CLOCK_100_200		(1 << 0)
290 #define   GC_CLOCK_100_133		(2 << 0)
291 #define   GC_CLOCK_133_266		(3 << 0)
292 #define   GC_CLOCK_133_200_2		(4 << 0)
293 #define   GC_CLOCK_133_266_2		(5 << 0)
294 #define   GC_CLOCK_166_266		(6 << 0)
295 #define   GC_CLOCK_166_250		(7 << 0)
296 
297 #define I915_GDRST 0xc0 /* PCI config register */
298 #define   GRDOM_FULL		(0 << 2)
299 #define   GRDOM_RENDER		(1 << 2)
300 #define   GRDOM_MEDIA		(3 << 2)
301 #define   GRDOM_MASK		(3 << 2)
302 #define   GRDOM_RESET_STATUS	(1 << 1)
303 #define   GRDOM_RESET_ENABLE	(1 << 0)
304 
305 /* BSpec only has register offset, PCI device and bit found empirically */
306 #define I830_CLOCK_GATE	0xc8 /* device 0 */
307 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
308 
309 #define GCDGMBUS 0xcc
310 
311 #define GCFGC2	0xda
312 #define GCFGC	0xf0 /* 915+ only */
313 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
314 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
315 #define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
316 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
317 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
318 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
319 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
320 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
321 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
322 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
323 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
324 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
325 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
326 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
327 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
328 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
329 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
330 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
331 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
332 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
333 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
334 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
335 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
336 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
337 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
338 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
339 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
340 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
341 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
342 
343 #define ASLE	0xe4
344 #define ASLS	0xfc
345 
346 #define SWSCI	0xe8
347 #define   SWSCI_SCISEL	(1 << 15)
348 #define   SWSCI_GSSCIE	(1 << 0)
349 
350 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
351 
352 
353 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
354 #define  ILK_GRDOM_FULL		(0 << 1)
355 #define  ILK_GRDOM_RENDER	(1 << 1)
356 #define  ILK_GRDOM_MEDIA	(3 << 1)
357 #define  ILK_GRDOM_MASK		(3 << 1)
358 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
359 
360 #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
361 #define   GEN6_MBC_SNPCR_SHIFT	21
362 #define   GEN6_MBC_SNPCR_MASK	(3 << 21)
363 #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
364 #define   GEN6_MBC_SNPCR_MED	(1 << 21)
365 #define   GEN6_MBC_SNPCR_LOW	(2 << 21)
366 #define   GEN6_MBC_SNPCR_MIN	(3 << 21) /* only 1/16th of the cache is shared */
367 
368 #define VLV_G3DCTL		_MMIO(0x9024)
369 #define VLV_GSCKGCTL		_MMIO(0x9028)
370 
371 #define GEN6_MBCTL		_MMIO(0x0907c)
372 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
373 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
374 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
375 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
376 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
377 
378 #define GEN6_GDRST	_MMIO(0x941c)
379 #define  GEN6_GRDOM_FULL		(1 << 0)
380 #define  GEN6_GRDOM_RENDER		(1 << 1)
381 #define  GEN6_GRDOM_MEDIA		(1 << 2)
382 #define  GEN6_GRDOM_BLT			(1 << 3)
383 #define  GEN6_GRDOM_VECS		(1 << 4)
384 #define  GEN9_GRDOM_GUC			(1 << 5)
385 #define  GEN8_GRDOM_MEDIA2		(1 << 7)
386 /* GEN11 changed all bit defs except for FULL & RENDER */
387 #define  GEN11_GRDOM_FULL		GEN6_GRDOM_FULL
388 #define  GEN11_GRDOM_RENDER		GEN6_GRDOM_RENDER
389 #define  GEN11_GRDOM_BLT		(1 << 2)
390 #define  GEN11_GRDOM_GUC		(1 << 3)
391 #define  GEN11_GRDOM_MEDIA		(1 << 5)
392 #define  GEN11_GRDOM_MEDIA2		(1 << 6)
393 #define  GEN11_GRDOM_MEDIA3		(1 << 7)
394 #define  GEN11_GRDOM_MEDIA4		(1 << 8)
395 #define  GEN11_GRDOM_VECS		(1 << 13)
396 #define  GEN11_GRDOM_VECS2		(1 << 14)
397 #define  GEN11_GRDOM_SFC0		(1 << 17)
398 #define  GEN11_GRDOM_SFC1		(1 << 18)
399 
400 #define  GEN11_VCS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << ((instance) >> 1))
401 #define  GEN11_VECS_SFC_RESET_BIT(instance)	(GEN11_GRDOM_SFC0 << (instance))
402 
403 #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
404 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT		(1 << 0)
405 #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
406 #define   GEN11_VCS_SFC_USAGE_BIT		(1 << 0)
407 #define   GEN11_VCS_SFC_LOCK_ACK_BIT		(1 << 1)
408 
409 #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
410 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT	(1 << 0)
411 #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
412 #define   GEN11_VECS_SFC_LOCK_ACK_BIT		(1 << 0)
413 #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
414 #define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)
415 
416 #define GEN12_SFC_DONE(n)		_MMIO(0x1cc00 + (n) * 0x100)
417 #define GEN12_SFC_DONE_MAX		4
418 
419 #define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)
420 #define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)
421 #define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)
422 #define   PP_DIR_DCLV_2G		0xffffffff
423 
424 #define GEN8_RING_PDP_UDW(base, n)	_MMIO((base) + 0x270 + (n) * 8 + 4)
425 #define GEN8_RING_PDP_LDW(base, n)	_MMIO((base) + 0x270 + (n) * 8)
426 
427 #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
428 #define   GEN8_RPCS_ENABLE		(1 << 31)
429 #define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
430 #define   GEN8_RPCS_S_CNT_SHIFT		15
431 #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
432 #define   GEN11_RPCS_S_CNT_SHIFT	12
433 #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
434 #define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
435 #define   GEN8_RPCS_SS_CNT_SHIFT	8
436 #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
437 #define   GEN8_RPCS_EU_MAX_SHIFT	4
438 #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
439 #define   GEN8_RPCS_EU_MIN_SHIFT	0
440 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
441 
442 #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
443 /* HSW only */
444 #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2
445 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
446 #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT		4
447 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
448 /* HSW+ */
449 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
450 #define   HSW_RCS_CONTEXT_ENABLE			(1 << 7)
451 #define   HSW_RCS_INHIBIT				(1 << 8)
452 /* Gen8 */
453 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
454 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
455 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT		4
456 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
457 #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE	(1 << 6)
458 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT	9
459 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
460 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT	11
461 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
462 #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
463 
464 #define GAM_ECOCHK			_MMIO(0x4090)
465 #define   BDW_DISABLE_HDC_INVALIDATION	(1 << 25)
466 #define   ECOCHK_SNB_BIT		(1 << 10)
467 #define   ECOCHK_DIS_TLB		(1 << 8)
468 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1 << 6)
469 #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
470 #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
471 #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
472 #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
473 #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
474 #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
475 #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
476 
477 #define GEN8_RC6_CTX_INFO		_MMIO(0x8504)
478 
479 #define GAC_ECO_BITS			_MMIO(0x14090)
480 #define   ECOBITS_SNB_BIT		(1 << 13)
481 #define   ECOBITS_PPGTT_CACHE64B	(3 << 8)
482 #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
483 
484 #define GAB_CTL				_MMIO(0x24000)
485 #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1 << 8)
486 
487 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
488 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
489 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
490 #define GEN6_STOLEN_RESERVED_SIZE_MASK	(3 << 4)
491 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
492 #define GEN6_STOLEN_RESERVED_512K	(1 << 4)
493 #define GEN6_STOLEN_RESERVED_256K	(2 << 4)
494 #define GEN6_STOLEN_RESERVED_128K	(3 << 4)
495 #define GEN7_STOLEN_RESERVED_SIZE_MASK	(1 << 5)
496 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
497 #define GEN7_STOLEN_RESERVED_256K	(1 << 5)
498 #define GEN8_STOLEN_RESERVED_SIZE_MASK	(3 << 7)
499 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
500 #define GEN8_STOLEN_RESERVED_2M		(1 << 7)
501 #define GEN8_STOLEN_RESERVED_4M		(2 << 7)
502 #define GEN8_STOLEN_RESERVED_8M		(3 << 7)
503 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
504 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
505 
506 /* VGA stuff */
507 
508 #define VGA_ST01_MDA 0x3ba
509 #define VGA_ST01_CGA 0x3da
510 
511 #define _VGA_MSR_WRITE _MMIO(0x3c2)
512 #define VGA_MSR_WRITE 0x3c2
513 #define VGA_MSR_READ 0x3cc
514 #define   VGA_MSR_MEM_EN (1 << 1)
515 #define   VGA_MSR_CGA_MODE (1 << 0)
516 
517 #define VGA_SR_INDEX 0x3c4
518 #define SR01			1
519 #define VGA_SR_DATA 0x3c5
520 
521 #define VGA_AR_INDEX 0x3c0
522 #define   VGA_AR_VID_EN (1 << 5)
523 #define VGA_AR_DATA_WRITE 0x3c0
524 #define VGA_AR_DATA_READ 0x3c1
525 
526 #define VGA_GR_INDEX 0x3ce
527 #define VGA_GR_DATA 0x3cf
528 /* GR05 */
529 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
530 #define     VGA_GR_MEM_READ_MODE_PLANE 1
531 /* GR06 */
532 #define   VGA_GR_MEM_MODE_MASK 0xc
533 #define   VGA_GR_MEM_MODE_SHIFT 2
534 #define   VGA_GR_MEM_A0000_AFFFF 0
535 #define   VGA_GR_MEM_A0000_BFFFF 1
536 #define   VGA_GR_MEM_B0000_B7FFF 2
537 #define   VGA_GR_MEM_B0000_BFFFF 3
538 
539 #define VGA_DACMASK 0x3c6
540 #define VGA_DACRX 0x3c7
541 #define VGA_DACWX 0x3c8
542 #define VGA_DACDATA 0x3c9
543 
544 #define VGA_CR_INDEX_MDA 0x3b4
545 #define VGA_CR_DATA_MDA 0x3b5
546 #define VGA_CR_INDEX_CGA 0x3d4
547 #define VGA_CR_DATA_CGA 0x3d5
548 
549 #define MI_PREDICATE_SRC0	_MMIO(0x2400)
550 #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
551 #define MI_PREDICATE_SRC1	_MMIO(0x2408)
552 #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
553 #define MI_PREDICATE_DATA       _MMIO(0x2410)
554 #define MI_PREDICATE_RESULT     _MMIO(0x2418)
555 #define MI_PREDICATE_RESULT_1   _MMIO(0x241c)
556 #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
557 #define  LOWER_SLICE_ENABLED	(1 << 0)
558 #define  LOWER_SLICE_DISABLED	(0 << 0)
559 
560 /*
561  * Registers used only by the command parser
562  */
563 #define BCS_SWCTRL _MMIO(0x22200)
564 
565 /* There are 16 GPR registers */
566 #define BCS_GPR(n)	_MMIO(0x22600 + (n) * 8)
567 #define BCS_GPR_UDW(n)	_MMIO(0x22600 + (n) * 8 + 4)
568 
569 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
570 #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
571 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
572 #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
573 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
574 #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
575 #define IA_VERTICES_COUNT               _MMIO(0x2310)
576 #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
577 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
578 #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
579 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
580 #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
581 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
582 #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
583 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
584 #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
585 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
586 #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
587 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
588 #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
589 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
590 #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
591 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
592 #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
593 
594 /* There are the 4 64-bit counter registers, one for each stream output */
595 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
596 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
597 
598 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
599 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
600 
601 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
602 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
603 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
604 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
605 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
606 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
607 
608 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
609 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
610 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
611 
612 /* There are the 16 64-bit CS General Purpose Registers */
613 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
614 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
615 
616 #define GEN7_OACONTROL _MMIO(0x2360)
617 #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
618 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
619 #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
620 #define  GEN7_OACONTROL_TIMER_ENABLE	    (1 << 5)
621 #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
622 #define  GEN7_OACONTROL_FORMAT_A29	    (1 << 2)
623 #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
624 #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
625 #define  GEN7_OACONTROL_FORMAT_B4_C8	    (4 << 2)
626 #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
627 #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
628 #define  GEN7_OACONTROL_FORMAT_C4_B8	    (7 << 2)
629 #define  GEN7_OACONTROL_FORMAT_SHIFT	    2
630 #define  GEN7_OACONTROL_PER_CTX_ENABLE	    (1 << 1)
631 #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
632 
633 #define GEN8_OACTXID _MMIO(0x2364)
634 
635 #define GEN8_OA_DEBUG _MMIO(0x2B04)
636 #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
637 #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO	    (1 << 6)
638 #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS	    (1 << 2)
639 #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
640 
641 #define GEN8_OACONTROL _MMIO(0x2B00)
642 #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
643 #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
644 #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
645 #define  GEN8_OA_REPORT_FORMAT_C4_B8	    (7 << 2)
646 #define  GEN8_OA_REPORT_FORMAT_SHIFT	    2
647 #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
648 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
649 
650 #define GEN8_OACTXCONTROL _MMIO(0x2360)
651 #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
652 #define  GEN8_OA_TIMER_PERIOD_SHIFT	    2
653 #define  GEN8_OA_TIMER_ENABLE		    (1 << 1)
654 #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
655 
656 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
657 #define  GEN7_OABUFFER_OVERRUN_DISABLE	    (1 << 3)
658 #define  GEN7_OABUFFER_EDGE_TRIGGER	    (1 << 2)
659 #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
660 #define  GEN7_OABUFFER_RESUME		    (1 << 0)
661 
662 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
663 #define GEN8_OABUFFER _MMIO(0x2b14)
664 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
665 
666 #define GEN7_OASTATUS1 _MMIO(0x2364)
667 #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
668 #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
669 #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
670 #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
671 
672 #define GEN7_OASTATUS2 _MMIO(0x2368)
673 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
674 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
675 
676 #define GEN8_OASTATUS _MMIO(0x2b08)
677 #define  GEN8_OASTATUS_OVERRUN_STATUS	    (1 << 3)
678 #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
679 #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
680 #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
681 
682 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
683 #define GEN8_OAHEADPTR_MASK    0xffffffc0
684 #define GEN8_OATAILPTR _MMIO(0x2B10)
685 #define GEN8_OATAILPTR_MASK    0xffffffc0
686 
687 #define OABUFFER_SIZE_128K  (0 << 3)
688 #define OABUFFER_SIZE_256K  (1 << 3)
689 #define OABUFFER_SIZE_512K  (2 << 3)
690 #define OABUFFER_SIZE_1M    (3 << 3)
691 #define OABUFFER_SIZE_2M    (4 << 3)
692 #define OABUFFER_SIZE_4M    (5 << 3)
693 #define OABUFFER_SIZE_8M    (6 << 3)
694 #define OABUFFER_SIZE_16M   (7 << 3)
695 
696 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
697 
698 /* Gen12 OAR unit */
699 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
700 #define  GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
701 #define  GEN12_OAR_OACONTROL_COUNTER_ENABLE       (1 << 0)
702 
703 #define GEN12_OACTXCONTROL _MMIO(0x2360)
704 #define GEN12_OAR_OASTATUS _MMIO(0x2968)
705 
706 /* Gen12 OAG unit */
707 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
708 #define  GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
709 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
710 #define  GEN12_OAG_OATAILPTR_MASK 0xffffffc0
711 
712 #define GEN12_OAG_OABUFFER  _MMIO(0xdb08)
713 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK  (0x7)
714 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
715 #define  GEN12_OAG_OABUFFER_MEMORY_SELECT     (1 << 0) /* 0: PPGTT, 1: GGTT */
716 
717 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
718 #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
719 #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE       (1 << 1)
720 #define  GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME     (1 << 0)
721 
722 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
723 #define  GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
724 #define  GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE       (1 << 0)
725 
726 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
727 #define  GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO          (1 << 6)
728 #define  GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS  (1 << 5)
729 #define  GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS     (1 << 2)
730 #define  GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
731 
732 #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
733 #define  GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
734 #define  GEN12_OAG_OASTATUS_BUFFER_OVERFLOW  (1 << 1)
735 #define  GEN12_OAG_OASTATUS_REPORT_LOST      (1 << 0)
736 
737 /*
738  * Flexible, Aggregate EU Counter Registers.
739  * Note: these aren't contiguous
740  */
741 #define EU_PERF_CNTL0	    _MMIO(0xe458)
742 #define EU_PERF_CNTL1	    _MMIO(0xe558)
743 #define EU_PERF_CNTL2	    _MMIO(0xe658)
744 #define EU_PERF_CNTL3	    _MMIO(0xe758)
745 #define EU_PERF_CNTL4	    _MMIO(0xe45c)
746 #define EU_PERF_CNTL5	    _MMIO(0xe55c)
747 #define EU_PERF_CNTL6	    _MMIO(0xe65c)
748 
749 /*
750  * OA Boolean state
751  */
752 
753 #define OASTARTTRIG1 _MMIO(0x2710)
754 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
755 #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
756 
757 #define OASTARTTRIG2 _MMIO(0x2714)
758 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
759 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
760 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
761 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
762 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
763 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
764 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
765 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
766 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
767 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
768 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
769 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
770 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
771 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
772 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
773 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
774 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
775 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
776 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
777 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
778 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
779 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
780 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
781 #define OASTARTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
782 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
783 #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
784 #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
785 #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
786 #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
787 
788 #define OASTARTTRIG3 _MMIO(0x2718)
789 #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
790 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
791 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
792 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
793 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
794 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
795 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
796 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
797 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
798 
799 #define OASTARTTRIG4 _MMIO(0x271c)
800 #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
801 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
802 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
803 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
804 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
805 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
806 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
807 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
808 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
809 
810 #define OASTARTTRIG5 _MMIO(0x2720)
811 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
812 #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
813 
814 #define OASTARTTRIG6 _MMIO(0x2724)
815 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
816 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
817 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
818 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
819 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
820 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
821 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
822 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
823 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
824 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
825 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
826 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
827 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
828 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
829 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
830 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
831 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
832 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
833 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
834 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
835 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
836 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
837 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
838 #define OASTARTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
839 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
840 #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
841 #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
842 #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
843 #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
844 
845 #define OASTARTTRIG7 _MMIO(0x2728)
846 #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
847 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
848 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
849 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
850 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
851 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
852 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
853 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
854 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
855 
856 #define OASTARTTRIG8 _MMIO(0x272c)
857 #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
858 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
859 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
860 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
861 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
862 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
863 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
864 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
865 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
866 
867 #define OAREPORTTRIG1 _MMIO(0x2740)
868 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
869 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
870 
871 #define OAREPORTTRIG2 _MMIO(0x2744)
872 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
873 #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
874 #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
875 #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
876 #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
877 #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
878 #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
879 #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
880 #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
881 #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
882 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
883 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
884 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
885 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
886 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
887 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
888 #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
889 #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
890 #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
891 #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
892 #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
893 #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
894 #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
895 #define OAREPORTTRIG2_THRESHOLD_ENABLE	    (1 << 23)
896 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
897 
898 #define OAREPORTTRIG3 _MMIO(0x2748)
899 #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
900 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
901 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
902 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
903 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
904 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
905 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
906 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
907 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
908 
909 #define OAREPORTTRIG4 _MMIO(0x274c)
910 #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
911 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
912 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
913 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
914 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
915 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
916 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
917 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
918 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
919 
920 #define OAREPORTTRIG5 _MMIO(0x2750)
921 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
922 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
923 
924 #define OAREPORTTRIG6 _MMIO(0x2754)
925 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
926 #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
927 #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
928 #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
929 #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
930 #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
931 #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
932 #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
933 #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
934 #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
935 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
936 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
937 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
938 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
939 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
940 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
941 #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
942 #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
943 #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
944 #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
945 #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
946 #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
947 #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
948 #define OAREPORTTRIG6_THRESHOLD_ENABLE	    (1 << 23)
949 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
950 
951 #define OAREPORTTRIG7 _MMIO(0x2758)
952 #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
953 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
954 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
955 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
956 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
957 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
958 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
959 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
960 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
961 
962 #define OAREPORTTRIG8 _MMIO(0x275c)
963 #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
964 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
965 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
966 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
967 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
968 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
969 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
970 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
971 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
972 
973 /* Same layout as OASTARTTRIGX */
974 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
975 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
976 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
977 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
978 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
979 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
980 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
981 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
982 
983 /* Same layout as OAREPORTTRIGX */
984 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
985 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
986 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
987 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
988 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
989 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
990 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
991 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
992 
993 /* CECX_0 */
994 #define OACEC_COMPARE_LESS_OR_EQUAL	6
995 #define OACEC_COMPARE_NOT_EQUAL		5
996 #define OACEC_COMPARE_LESS_THAN		4
997 #define OACEC_COMPARE_GREATER_OR_EQUAL	3
998 #define OACEC_COMPARE_EQUAL		2
999 #define OACEC_COMPARE_GREATER_THAN	1
1000 #define OACEC_COMPARE_ANY_EQUAL		0
1001 
1002 #define OACEC_COMPARE_VALUE_MASK    0xffff
1003 #define OACEC_COMPARE_VALUE_SHIFT   3
1004 
1005 #define OACEC_SELECT_NOA	(0 << 19)
1006 #define OACEC_SELECT_PREV	(1 << 19)
1007 #define OACEC_SELECT_BOOLEAN	(2 << 19)
1008 
1009 /* 11-bit array 0: pass-through, 1: negated */
1010 #define GEN12_OASCEC_NEGATE_MASK  0x7ff
1011 #define GEN12_OASCEC_NEGATE_SHIFT 21
1012 
1013 /* CECX_1 */
1014 #define OACEC_MASK_MASK		    0xffff
1015 #define OACEC_CONSIDERATIONS_MASK   0xffff
1016 #define OACEC_CONSIDERATIONS_SHIFT  16
1017 
1018 #define OACEC0_0 _MMIO(0x2770)
1019 #define OACEC0_1 _MMIO(0x2774)
1020 #define OACEC1_0 _MMIO(0x2778)
1021 #define OACEC1_1 _MMIO(0x277c)
1022 #define OACEC2_0 _MMIO(0x2780)
1023 #define OACEC2_1 _MMIO(0x2784)
1024 #define OACEC3_0 _MMIO(0x2788)
1025 #define OACEC3_1 _MMIO(0x278c)
1026 #define OACEC4_0 _MMIO(0x2790)
1027 #define OACEC4_1 _MMIO(0x2794)
1028 #define OACEC5_0 _MMIO(0x2798)
1029 #define OACEC5_1 _MMIO(0x279c)
1030 #define OACEC6_0 _MMIO(0x27a0)
1031 #define OACEC6_1 _MMIO(0x27a4)
1032 #define OACEC7_0 _MMIO(0x27a8)
1033 #define OACEC7_1 _MMIO(0x27ac)
1034 
1035 /* Same layout as CECX_Y */
1036 #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1037 #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1038 #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1039 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1040 #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1041 #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1042 #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1043 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1044 #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1045 #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1046 #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1047 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1048 #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1049 #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1050 #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1051 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1052 
1053 /* Same layout as CECX_Y + negate 11-bit array */
1054 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1055 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1056 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1057 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1058 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1059 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1060 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1061 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1062 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1063 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1064 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1065 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1066 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1067 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1068 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1069 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1070 
1071 /* OA perf counters */
1072 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
1073 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
1074 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
1075 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
1076 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
1077 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
1078 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
1079 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
1080 
1081 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
1082 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
1083 
1084 /* RPM unit config (Gen8+) */
1085 #define RPM_CONFIG0	    _MMIO(0x0D00)
1086 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
1087 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1088 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
1089 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	1
1090 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
1091 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1092 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
1093 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
1094 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
1095 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	3
1096 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT	1
1097 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1098 
1099 #define RPM_CONFIG1	    _MMIO(0x0D04)
1100 #define  GEN10_GT_NOA_ENABLE  (1 << 9)
1101 
1102 /* GPM unit config (Gen9+) */
1103 #define CTC_MODE			_MMIO(0xA26C)
1104 #define  CTC_SOURCE_PARAMETER_MASK 1
1105 #define  CTC_SOURCE_CRYSTAL_CLOCK	0
1106 #define  CTC_SOURCE_DIVIDE_LOGIC	1
1107 #define  CTC_SHIFT_PARAMETER_SHIFT	1
1108 #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1109 
1110 /* RCP unit config (Gen8+) */
1111 #define RCP_CONFIG	    _MMIO(0x0D08)
1112 
1113 /* NOA (HSW) */
1114 #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
1115 #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
1116 #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
1117 #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
1118 #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
1119 #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
1120 #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
1121 #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
1122 #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
1123 #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
1124 
1125 #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
1126 
1127 /* NOA (Gen8+) */
1128 #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
1129 
1130 #define MICRO_BP0_0	    _MMIO(0x9800)
1131 #define MICRO_BP0_2	    _MMIO(0x9804)
1132 #define MICRO_BP0_1	    _MMIO(0x9808)
1133 
1134 #define MICRO_BP1_0	    _MMIO(0x980C)
1135 #define MICRO_BP1_2	    _MMIO(0x9810)
1136 #define MICRO_BP1_1	    _MMIO(0x9814)
1137 
1138 #define MICRO_BP2_0	    _MMIO(0x9818)
1139 #define MICRO_BP2_2	    _MMIO(0x981C)
1140 #define MICRO_BP2_1	    _MMIO(0x9820)
1141 
1142 #define MICRO_BP3_0	    _MMIO(0x9824)
1143 #define MICRO_BP3_2	    _MMIO(0x9828)
1144 #define MICRO_BP3_1	    _MMIO(0x982C)
1145 
1146 #define MICRO_BP_TRIGGER		_MMIO(0x9830)
1147 #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
1148 #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
1149 #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
1150 
1151 #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1152 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1153 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1154 
1155 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
1156 #define   GT_NOA_ENABLE	    0x00000080
1157 
1158 #define NOA_DATA	    _MMIO(0x986C)
1159 #define NOA_WRITE	    _MMIO(0x9888)
1160 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1161 
1162 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
1163 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
1164 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1165 
1166 /*
1167  * Reset registers
1168  */
1169 #define DEBUG_RESET_I830		_MMIO(0x6070)
1170 #define  DEBUG_RESET_FULL		(1 << 7)
1171 #define  DEBUG_RESET_RENDER		(1 << 8)
1172 #define  DEBUG_RESET_DISPLAY		(1 << 9)
1173 
1174 /*
1175  * IOSF sideband
1176  */
1177 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
1178 #define   IOSF_DEVFN_SHIFT			24
1179 #define   IOSF_OPCODE_SHIFT			16
1180 #define   IOSF_PORT_SHIFT			8
1181 #define   IOSF_BYTE_ENABLES_SHIFT		4
1182 #define   IOSF_BAR_SHIFT			1
1183 #define   IOSF_SB_BUSY				(1 << 0)
1184 #define   IOSF_PORT_BUNIT			0x03
1185 #define   IOSF_PORT_PUNIT			0x04
1186 #define   IOSF_PORT_NC				0x11
1187 #define   IOSF_PORT_DPIO			0x12
1188 #define   IOSF_PORT_GPIO_NC			0x13
1189 #define   IOSF_PORT_CCK				0x14
1190 #define   IOSF_PORT_DPIO_2			0x1a
1191 #define   IOSF_PORT_FLISDSI			0x1b
1192 #define   IOSF_PORT_GPIO_SC			0x48
1193 #define   IOSF_PORT_GPIO_SUS			0xa8
1194 #define   IOSF_PORT_CCU				0xa9
1195 #define   CHV_IOSF_PORT_GPIO_N			0x13
1196 #define   CHV_IOSF_PORT_GPIO_SE			0x48
1197 #define   CHV_IOSF_PORT_GPIO_E			0xa8
1198 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
1199 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
1200 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
1201 
1202 /* See configdb bunit SB addr map */
1203 #define BUNIT_REG_BISOC				0x11
1204 
1205 /* PUNIT_REG_*SSPM0 */
1206 #define   _SSPM0_SSC(val)			((val) << 0)
1207 #define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
1208 #define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
1209 #define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
1210 #define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
1211 #define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
1212 #define   _SSPM0_SSS(val)			((val) << 24)
1213 #define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
1214 #define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
1215 #define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
1216 #define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
1217 #define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
1218 
1219 /* PUNIT_REG_*SSPM1 */
1220 #define   SSPM1_FREQSTAT_SHIFT			24
1221 #define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
1222 #define   SSPM1_FREQGUAR_SHIFT			8
1223 #define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
1224 #define   SSPM1_FREQ_SHIFT			0
1225 #define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
1226 
1227 #define PUNIT_REG_VEDSSPM0			0x32
1228 #define PUNIT_REG_VEDSSPM1			0x33
1229 
1230 #define PUNIT_REG_DSPSSPM			0x36
1231 #define   DSPFREQSTAT_SHIFT_CHV			24
1232 #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
1233 #define   DSPFREQGUAR_SHIFT_CHV			8
1234 #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
1235 #define   DSPFREQSTAT_SHIFT			30
1236 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
1237 #define   DSPFREQGUAR_SHIFT			14
1238 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
1239 #define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
1240 #define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
1241 #define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
1242 #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
1243 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
1244 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
1245 #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
1246 #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
1247 #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
1248 #define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
1249 #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
1250 #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
1251 #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
1252 #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
1253 #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
1254 
1255 #define PUNIT_REG_ISPSSPM0			0x39
1256 #define PUNIT_REG_ISPSSPM1			0x3a
1257 
1258 #define PUNIT_REG_PWRGT_CTRL			0x60
1259 #define PUNIT_REG_PWRGT_STATUS			0x61
1260 #define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
1261 #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
1262 #define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
1263 #define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
1264 #define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
1265 
1266 #define PUNIT_PWGT_IDX_RENDER			0
1267 #define PUNIT_PWGT_IDX_MEDIA			1
1268 #define PUNIT_PWGT_IDX_DISP2D			3
1269 #define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
1270 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
1271 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
1272 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
1273 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
1274 #define PUNIT_PWGT_IDX_DPIO_RX0			10
1275 #define PUNIT_PWGT_IDX_DPIO_RX1			11
1276 #define PUNIT_PWGT_IDX_DPIO_CMN_D		12
1277 
1278 #define PUNIT_REG_GPU_LFM			0xd3
1279 #define PUNIT_REG_GPU_FREQ_REQ			0xd4
1280 #define PUNIT_REG_GPU_FREQ_STS			0xd8
1281 #define   GPLLENABLE				(1 << 4)
1282 #define   GENFREQSTATUS				(1 << 0)
1283 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
1284 #define PUNIT_REG_CZ_TIMESTAMP			0xce
1285 
1286 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
1287 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
1288 
1289 #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
1290 #define FB_GFX_FREQ_FUSE_MASK			0xff
1291 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
1292 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
1293 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
1294 
1295 #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
1296 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
1297 
1298 #define PUNIT_REG_DDR_SETUP2			0x139
1299 #define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
1300 #define   FORCE_DDR_LOW_FREQ			(1 << 1)
1301 #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
1302 
1303 #define PUNIT_GPU_STATUS_REG			0xdb
1304 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
1305 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
1306 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
1307 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
1308 
1309 #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
1310 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
1311 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
1312 
1313 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
1314 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
1315 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
1316 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
1317 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
1318 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
1319 #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
1320 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
1321 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
1322 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
1323 
1324 #define VLV_TURBO_SOC_OVERRIDE		0x04
1325 #define   VLV_OVERRIDE_EN		1
1326 #define   VLV_SOC_TDP_EN		(1 << 1)
1327 #define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
1328 #define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
1329 
1330 /* vlv2 north clock has */
1331 #define CCK_FUSE_REG				0x8
1332 #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
1333 #define CCK_REG_DSI_PLL_FUSE			0x44
1334 #define CCK_REG_DSI_PLL_CONTROL			0x48
1335 #define  DSI_PLL_VCO_EN				(1 << 31)
1336 #define  DSI_PLL_LDO_GATE			(1 << 30)
1337 #define  DSI_PLL_P1_POST_DIV_SHIFT		17
1338 #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
1339 #define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
1340 #define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
1341 #define  DSI_PLL_MUX_MASK			(3 << 9)
1342 #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
1343 #define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
1344 #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
1345 #define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
1346 #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
1347 #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
1348 #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
1349 #define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
1350 #define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
1351 #define  DSI_PLL_LOCK				(1 << 0)
1352 #define CCK_REG_DSI_PLL_DIVIDER			0x4c
1353 #define  DSI_PLL_LFSR				(1 << 31)
1354 #define  DSI_PLL_FRACTION_EN			(1 << 30)
1355 #define  DSI_PLL_FRAC_COUNTER_SHIFT		27
1356 #define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
1357 #define  DSI_PLL_USYNC_CNT_SHIFT		18
1358 #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
1359 #define  DSI_PLL_N1_DIV_SHIFT			16
1360 #define  DSI_PLL_N1_DIV_MASK			(3 << 16)
1361 #define  DSI_PLL_M1_DIV_SHIFT			0
1362 #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
1363 #define CCK_CZ_CLOCK_CONTROL			0x62
1364 #define CCK_GPLL_CLOCK_CONTROL			0x67
1365 #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
1366 #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
1367 #define  CCK_TRUNK_FORCE_ON			(1 << 17)
1368 #define  CCK_TRUNK_FORCE_OFF			(1 << 16)
1369 #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
1370 #define  CCK_FREQUENCY_STATUS_SHIFT		8
1371 #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
1372 
1373 /* DPIO registers */
1374 #define DPIO_DEVFN			0
1375 
1376 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
1377 #define  DPIO_MODSEL1			(1 << 3) /* if ref clk b == 27 */
1378 #define  DPIO_MODSEL0			(1 << 2) /* if ref clk a == 27 */
1379 #define  DPIO_SFR_BYPASS		(1 << 1)
1380 #define  DPIO_CMNRST			(1 << 0)
1381 
1382 #define DPIO_PHY(pipe)			((pipe) >> 1)
1383 #define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])
1384 
1385 /*
1386  * Per pipe/PLL DPIO regs
1387  */
1388 #define _VLV_PLL_DW3_CH0		0x800c
1389 #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
1390 #define   DPIO_POST_DIV_DAC		0
1391 #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
1392 #define   DPIO_POST_DIV_LVDS1		2
1393 #define   DPIO_POST_DIV_LVDS2		3
1394 #define   DPIO_K_SHIFT			(24) /* 4 bits */
1395 #define   DPIO_P1_SHIFT			(21) /* 3 bits */
1396 #define   DPIO_P2_SHIFT			(16) /* 5 bits */
1397 #define   DPIO_N_SHIFT			(12) /* 4 bits */
1398 #define   DPIO_ENABLE_CALIBRATION	(1 << 11)
1399 #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
1400 #define   DPIO_M2DIV_MASK		0xff
1401 #define _VLV_PLL_DW3_CH1		0x802c
1402 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1403 
1404 #define _VLV_PLL_DW5_CH0		0x8014
1405 #define   DPIO_REFSEL_OVERRIDE		27
1406 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
1407 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
1408 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
1409 #define   DPIO_PLL_REFCLK_SEL_MASK	3
1410 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
1411 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
1412 #define _VLV_PLL_DW5_CH1		0x8034
1413 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1414 
1415 #define _VLV_PLL_DW7_CH0		0x801c
1416 #define _VLV_PLL_DW7_CH1		0x803c
1417 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1418 
1419 #define _VLV_PLL_DW8_CH0		0x8040
1420 #define _VLV_PLL_DW8_CH1		0x8060
1421 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1422 
1423 #define VLV_PLL_DW9_BCAST		0xc044
1424 #define _VLV_PLL_DW9_CH0		0x8044
1425 #define _VLV_PLL_DW9_CH1		0x8064
1426 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1427 
1428 #define _VLV_PLL_DW10_CH0		0x8048
1429 #define _VLV_PLL_DW10_CH1		0x8068
1430 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1431 
1432 #define _VLV_PLL_DW11_CH0		0x804c
1433 #define _VLV_PLL_DW11_CH1		0x806c
1434 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1435 
1436 /* Spec for ref block start counts at DW10 */
1437 #define VLV_REF_DW13			0x80ac
1438 
1439 #define VLV_CMN_DW0			0x8100
1440 
1441 /*
1442  * Per DDI channel DPIO regs
1443  */
1444 
1445 #define _VLV_PCS_DW0_CH0		0x8200
1446 #define _VLV_PCS_DW0_CH1		0x8400
1447 #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
1448 #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
1449 #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
1450 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
1451 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1452 
1453 #define _VLV_PCS01_DW0_CH0		0x200
1454 #define _VLV_PCS23_DW0_CH0		0x400
1455 #define _VLV_PCS01_DW0_CH1		0x2600
1456 #define _VLV_PCS23_DW0_CH1		0x2800
1457 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1458 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1459 
1460 #define _VLV_PCS_DW1_CH0		0x8204
1461 #define _VLV_PCS_DW1_CH1		0x8404
1462 #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
1463 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
1464 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1465 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
1466 #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
1467 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1468 
1469 #define _VLV_PCS01_DW1_CH0		0x204
1470 #define _VLV_PCS23_DW1_CH0		0x404
1471 #define _VLV_PCS01_DW1_CH1		0x2604
1472 #define _VLV_PCS23_DW1_CH1		0x2804
1473 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1474 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1475 
1476 #define _VLV_PCS_DW8_CH0		0x8220
1477 #define _VLV_PCS_DW8_CH1		0x8420
1478 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
1479 #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
1480 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1481 
1482 #define _VLV_PCS01_DW8_CH0		0x0220
1483 #define _VLV_PCS23_DW8_CH0		0x0420
1484 #define _VLV_PCS01_DW8_CH1		0x2620
1485 #define _VLV_PCS23_DW8_CH1		0x2820
1486 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1487 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1488 
1489 #define _VLV_PCS_DW9_CH0		0x8224
1490 #define _VLV_PCS_DW9_CH1		0x8424
1491 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
1492 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
1493 #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
1494 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
1495 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
1496 #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
1497 #define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1498 
1499 #define _VLV_PCS01_DW9_CH0		0x224
1500 #define _VLV_PCS23_DW9_CH0		0x424
1501 #define _VLV_PCS01_DW9_CH1		0x2624
1502 #define _VLV_PCS23_DW9_CH1		0x2824
1503 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1504 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1505 
1506 #define _CHV_PCS_DW10_CH0		0x8228
1507 #define _CHV_PCS_DW10_CH1		0x8428
1508 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
1509 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
1510 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
1511 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
1512 #define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
1513 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
1514 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
1515 #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
1516 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1517 
1518 #define _VLV_PCS01_DW10_CH0		0x0228
1519 #define _VLV_PCS23_DW10_CH0		0x0428
1520 #define _VLV_PCS01_DW10_CH1		0x2628
1521 #define _VLV_PCS23_DW10_CH1		0x2828
1522 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1523 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1524 
1525 #define _VLV_PCS_DW11_CH0		0x822c
1526 #define _VLV_PCS_DW11_CH1		0x842c
1527 #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
1528 #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
1529 #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
1530 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
1531 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1532 
1533 #define _VLV_PCS01_DW11_CH0		0x022c
1534 #define _VLV_PCS23_DW11_CH0		0x042c
1535 #define _VLV_PCS01_DW11_CH1		0x262c
1536 #define _VLV_PCS23_DW11_CH1		0x282c
1537 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1538 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1539 
1540 #define _VLV_PCS01_DW12_CH0		0x0230
1541 #define _VLV_PCS23_DW12_CH0		0x0430
1542 #define _VLV_PCS01_DW12_CH1		0x2630
1543 #define _VLV_PCS23_DW12_CH1		0x2830
1544 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1545 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1546 
1547 #define _VLV_PCS_DW12_CH0		0x8230
1548 #define _VLV_PCS_DW12_CH1		0x8430
1549 #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
1550 #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
1551 #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
1552 #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
1553 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
1554 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1555 
1556 #define _VLV_PCS_DW14_CH0		0x8238
1557 #define _VLV_PCS_DW14_CH1		0x8438
1558 #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1559 
1560 #define _VLV_PCS_DW23_CH0		0x825c
1561 #define _VLV_PCS_DW23_CH1		0x845c
1562 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1563 
1564 #define _VLV_TX_DW2_CH0			0x8288
1565 #define _VLV_TX_DW2_CH1			0x8488
1566 #define   DPIO_SWING_MARGIN000_SHIFT	16
1567 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
1568 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
1569 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1570 
1571 #define _VLV_TX_DW3_CH0			0x828c
1572 #define _VLV_TX_DW3_CH1			0x848c
1573 /* The following bit for CHV phy */
1574 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
1575 #define   DPIO_SWING_MARGIN101_SHIFT	16
1576 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
1577 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1578 
1579 #define _VLV_TX_DW4_CH0			0x8290
1580 #define _VLV_TX_DW4_CH1			0x8490
1581 #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
1582 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1583 #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
1584 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1585 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1586 
1587 #define _VLV_TX3_DW4_CH0		0x690
1588 #define _VLV_TX3_DW4_CH1		0x2a90
1589 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1590 
1591 #define _VLV_TX_DW5_CH0			0x8294
1592 #define _VLV_TX_DW5_CH1			0x8494
1593 #define   DPIO_TX_OCALINIT_EN		(1 << 31)
1594 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1595 
1596 #define _VLV_TX_DW11_CH0		0x82ac
1597 #define _VLV_TX_DW11_CH1		0x84ac
1598 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1599 
1600 #define _VLV_TX_DW14_CH0		0x82b8
1601 #define _VLV_TX_DW14_CH1		0x84b8
1602 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1603 
1604 /* CHV dpPhy registers */
1605 #define _CHV_PLL_DW0_CH0		0x8000
1606 #define _CHV_PLL_DW0_CH1		0x8180
1607 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1608 
1609 #define _CHV_PLL_DW1_CH0		0x8004
1610 #define _CHV_PLL_DW1_CH1		0x8184
1611 #define   DPIO_CHV_N_DIV_SHIFT		8
1612 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1613 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1614 
1615 #define _CHV_PLL_DW2_CH0		0x8008
1616 #define _CHV_PLL_DW2_CH1		0x8188
1617 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1618 
1619 #define _CHV_PLL_DW3_CH0		0x800c
1620 #define _CHV_PLL_DW3_CH1		0x818c
1621 #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
1622 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
1623 #define  DPIO_CHV_SECOND_MOD		(1 << 8)
1624 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
1625 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
1626 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1627 
1628 #define _CHV_PLL_DW6_CH0		0x8018
1629 #define _CHV_PLL_DW6_CH1		0x8198
1630 #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
1631 #define	  DPIO_CHV_INT_COEFF_SHIFT	8
1632 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
1633 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1634 
1635 #define _CHV_PLL_DW8_CH0		0x8020
1636 #define _CHV_PLL_DW8_CH1		0x81A0
1637 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1638 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1639 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1640 
1641 #define _CHV_PLL_DW9_CH0		0x8024
1642 #define _CHV_PLL_DW9_CH1		0x81A4
1643 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
1644 #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
1645 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1646 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1647 
1648 #define _CHV_CMN_DW0_CH0               0x8100
1649 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
1650 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
1651 #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
1652 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1653 
1654 #define _CHV_CMN_DW5_CH0               0x8114
1655 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1656 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
1657 #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
1658 #define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
1659 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1660 #define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
1661 #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
1662 #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
1663 
1664 #define _CHV_CMN_DW13_CH0		0x8134
1665 #define _CHV_CMN_DW0_CH1		0x8080
1666 #define   DPIO_CHV_S1_DIV_SHIFT		21
1667 #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
1668 #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
1669 #define   DPIO_CHV_K_DIV_SHIFT		4
1670 #define   DPIO_PLL_FREQLOCK		(1 << 1)
1671 #define   DPIO_PLL_LOCK			(1 << 0)
1672 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1673 
1674 #define _CHV_CMN_DW14_CH0		0x8138
1675 #define _CHV_CMN_DW1_CH1		0x8084
1676 #define   DPIO_AFC_RECAL		(1 << 14)
1677 #define   DPIO_DCLKP_EN			(1 << 13)
1678 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1679 #define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
1680 #define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
1681 #define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
1682 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1683 #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
1684 #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
1685 #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
1686 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1687 
1688 #define _CHV_CMN_DW19_CH0		0x814c
1689 #define _CHV_CMN_DW6_CH1		0x8098
1690 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
1691 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
1692 #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
1693 #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
1694 
1695 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1696 
1697 #define CHV_CMN_DW28			0x8170
1698 #define   DPIO_CL1POWERDOWNEN		(1 << 23)
1699 #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
1700 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1701 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1702 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1703 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1704 
1705 #define CHV_CMN_DW30			0x8178
1706 #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
1707 #define   DPIO_LRC_BYPASS		(1 << 3)
1708 
1709 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1710 					(lane) * 0x200 + (offset))
1711 
1712 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1713 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1714 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1715 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1716 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1717 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1718 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1719 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1720 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1721 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1722 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1723 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1724 #define   DPIO_FRC_LATENCY_SHFIT	8
1725 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1726 #define   DPIO_UPAR_SHIFT		30
1727 
1728 /* BXT PHY registers */
1729 #define _BXT_PHY0_BASE			0x6C000
1730 #define _BXT_PHY1_BASE			0x162000
1731 #define _BXT_PHY2_BASE			0x163000
1732 #define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
1733 						     _BXT_PHY1_BASE, \
1734 						     _BXT_PHY2_BASE)
1735 
1736 #define _BXT_PHY(phy, reg)						\
1737 	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1738 
1739 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
1740 	(BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,	\
1741 					 (reg_ch1) - _BXT_PHY0_BASE))
1742 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)		\
1743 	_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1744 
1745 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
1746 #define  MIPIO_RST_CTRL				(1 << 2)
1747 
1748 #define _BXT_PHY_CTL_DDI_A		0x64C00
1749 #define _BXT_PHY_CTL_DDI_B		0x64C10
1750 #define _BXT_PHY_CTL_DDI_C		0x64C20
1751 #define   BXT_PHY_CMNLANE_POWERDOWN_ACK	(1 << 10)
1752 #define   BXT_PHY_LANE_POWERDOWN_ACK	(1 << 9)
1753 #define   BXT_PHY_LANE_ENABLED		(1 << 8)
1754 #define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1755 							 _BXT_PHY_CTL_DDI_B)
1756 
1757 #define _PHY_CTL_FAMILY_EDP		0x64C80
1758 #define _PHY_CTL_FAMILY_DDI		0x64C90
1759 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
1760 #define   COMMON_RESET_DIS		(1 << 31)
1761 #define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1762 							  _PHY_CTL_FAMILY_EDP, \
1763 							  _PHY_CTL_FAMILY_DDI_C)
1764 
1765 /* BXT PHY PLL registers */
1766 #define _PORT_PLL_A			0x46074
1767 #define _PORT_PLL_B			0x46078
1768 #define _PORT_PLL_C			0x4607c
1769 #define   PORT_PLL_ENABLE		(1 << 31)
1770 #define   PORT_PLL_LOCK			(1 << 30)
1771 #define   PORT_PLL_REF_SEL		(1 << 27)
1772 #define   PORT_PLL_POWER_ENABLE		(1 << 26)
1773 #define   PORT_PLL_POWER_STATE		(1 << 25)
1774 #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1775 
1776 #define _PORT_PLL_EBB_0_A		0x162034
1777 #define _PORT_PLL_EBB_0_B		0x6C034
1778 #define _PORT_PLL_EBB_0_C		0x6C340
1779 #define   PORT_PLL_P1_SHIFT		13
1780 #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1781 #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
1782 #define   PORT_PLL_P2_SHIFT		8
1783 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1784 #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
1785 #define BXT_PORT_PLL_EBB_0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
1786 							 _PORT_PLL_EBB_0_B, \
1787 							 _PORT_PLL_EBB_0_C)
1788 
1789 #define _PORT_PLL_EBB_4_A		0x162038
1790 #define _PORT_PLL_EBB_4_B		0x6C038
1791 #define _PORT_PLL_EBB_4_C		0x6C344
1792 #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
1793 #define   PORT_PLL_RECALIBRATE		(1 << 14)
1794 #define BXT_PORT_PLL_EBB_4(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
1795 							 _PORT_PLL_EBB_4_B, \
1796 							 _PORT_PLL_EBB_4_C)
1797 
1798 #define _PORT_PLL_0_A			0x162100
1799 #define _PORT_PLL_0_B			0x6C100
1800 #define _PORT_PLL_0_C			0x6C380
1801 /* PORT_PLL_0_A */
1802 #define   PORT_PLL_M2_MASK		0xFF
1803 /* PORT_PLL_1_A */
1804 #define   PORT_PLL_N_SHIFT		8
1805 #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1806 #define   PORT_PLL_N(x)			((x) << PORT_PLL_N_SHIFT)
1807 /* PORT_PLL_2_A */
1808 #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1809 /* PORT_PLL_3_A */
1810 #define   PORT_PLL_M2_FRAC_ENABLE	(1 << 16)
1811 /* PORT_PLL_6_A */
1812 #define   PORT_PLL_PROP_COEFF_MASK	0xF
1813 #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1814 #define   PORT_PLL_INT_COEFF(x)		((x)  << 8)
1815 #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1816 #define   PORT_PLL_GAIN_CTL(x)		((x)  << 16)
1817 /* PORT_PLL_8_A */
1818 #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1819 /* PORT_PLL_9_A */
1820 #define  PORT_PLL_LOCK_THRESHOLD_SHIFT	1
1821 #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1822 /* PORT_PLL_10_A */
1823 #define  PORT_PLL_DCO_AMP_OVR_EN_H	(1 << 27)
1824 #define  PORT_PLL_DCO_AMP_DEFAULT	15
1825 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
1826 #define  PORT_PLL_DCO_AMP(x)		((x) << 10)
1827 #define _PORT_PLL_BASE(phy, ch)		_BXT_PHY_CH(phy, ch, \
1828 						    _PORT_PLL_0_B, \
1829 						    _PORT_PLL_0_C)
1830 #define BXT_PORT_PLL(phy, ch, idx)	_MMIO(_PORT_PLL_BASE(phy, ch) + \
1831 					      (idx) * 4)
1832 
1833 /* BXT PHY common lane registers */
1834 #define _PORT_CL1CM_DW0_A		0x162000
1835 #define _PORT_CL1CM_DW0_BC		0x6C000
1836 #define   PHY_POWER_GOOD		(1 << 16)
1837 #define   PHY_RESERVED			(1 << 7)
1838 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1839 
1840 #define _PORT_CL1CM_DW9_A		0x162024
1841 #define _PORT_CL1CM_DW9_BC		0x6C024
1842 #define   IREF0RC_OFFSET_SHIFT		8
1843 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1844 #define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1845 
1846 #define _PORT_CL1CM_DW10_A		0x162028
1847 #define _PORT_CL1CM_DW10_BC		0x6C028
1848 #define   IREF1RC_OFFSET_SHIFT		8
1849 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1850 #define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1851 
1852 #define _PORT_CL1CM_DW28_A		0x162070
1853 #define _PORT_CL1CM_DW28_BC		0x6C070
1854 #define   OCL1_POWER_DOWN_EN		(1 << 23)
1855 #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
1856 #define   SUS_CLK_CONFIG		0x3
1857 #define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1858 
1859 #define _PORT_CL1CM_DW30_A		0x162078
1860 #define _PORT_CL1CM_DW30_BC		0x6C078
1861 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
1862 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1863 
1864 /*
1865  * CNL/ICL Port/COMBO-PHY Registers
1866  */
1867 #define _ICL_COMBOPHY_A			0x162000
1868 #define _ICL_COMBOPHY_B			0x6C000
1869 #define _EHL_COMBOPHY_C			0x160000
1870 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
1871 					      _ICL_COMBOPHY_B, \
1872 					      _EHL_COMBOPHY_C)
1873 
1874 /* CNL/ICL Port CL_DW registers */
1875 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
1876 					 4 * (dw))
1877 
1878 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
1879 #define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
1880 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
1881 #define   SUS_CLOCK_CONFIG		(3 << 0)
1882 
1883 #define ICL_PORT_CL_DW10(phy)		_MMIO(_ICL_PORT_CL_DW(10, phy))
1884 #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
1885 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
1886 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
1887 #define  PWR_UP_ALL_LANES		(0x0 << 4)
1888 #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
1889 #define  PWR_DOWN_LN_3_2		(0xc << 4)
1890 #define  PWR_DOWN_LN_3			(0x8 << 4)
1891 #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
1892 #define  PWR_DOWN_LN_1_0		(0x3 << 4)
1893 #define  PWR_DOWN_LN_3_1		(0xa << 4)
1894 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
1895 #define  PWR_DOWN_LN_MASK		(0xf << 4)
1896 #define  PWR_DOWN_LN_SHIFT		4
1897 
1898 #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
1899 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
1900 
1901 /* CNL/ICL Port COMP_DW registers */
1902 #define _ICL_PORT_COMP			0x100
1903 #define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
1904 					 _ICL_PORT_COMP + 4 * (dw))
1905 
1906 #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
1907 #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
1908 #define   COMP_INIT			(1 << 31)
1909 
1910 #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
1911 #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
1912 
1913 #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
1914 #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
1915 #define   PROCESS_INFO_DOT_0		(0 << 26)
1916 #define   PROCESS_INFO_DOT_1		(1 << 26)
1917 #define   PROCESS_INFO_DOT_4		(2 << 26)
1918 #define   PROCESS_INFO_MASK		(7 << 26)
1919 #define   PROCESS_INFO_SHIFT		26
1920 #define   VOLTAGE_INFO_0_85V		(0 << 24)
1921 #define   VOLTAGE_INFO_0_95V		(1 << 24)
1922 #define   VOLTAGE_INFO_1_05V		(2 << 24)
1923 #define   VOLTAGE_INFO_MASK		(3 << 24)
1924 #define   VOLTAGE_INFO_SHIFT		24
1925 
1926 #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
1927 #define   IREFGEN			(1 << 24)
1928 
1929 #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
1930 #define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
1931 
1932 #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
1933 #define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
1934 
1935 /* CNL/ICL Port PCS registers */
1936 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
1937 #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
1938 #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
1939 #define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
1940 #define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
1941 #define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
1942 #define _CNL_PORT_PCS_DW1_LN0_B		0x162604
1943 #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
1944 #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
1945 #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
1946 #define CNL_PORT_PCS_DW1_GRP(phy)	_MMIO(_PICK(phy, \
1947 						    _CNL_PORT_PCS_DW1_GRP_AE, \
1948 						    _CNL_PORT_PCS_DW1_GRP_B, \
1949 						    _CNL_PORT_PCS_DW1_GRP_C, \
1950 						    _CNL_PORT_PCS_DW1_GRP_D, \
1951 						    _CNL_PORT_PCS_DW1_GRP_AE, \
1952 						    _CNL_PORT_PCS_DW1_GRP_F))
1953 #define CNL_PORT_PCS_DW1_LN0(phy)	_MMIO(_PICK(phy, \
1954 						    _CNL_PORT_PCS_DW1_LN0_AE, \
1955 						    _CNL_PORT_PCS_DW1_LN0_B, \
1956 						    _CNL_PORT_PCS_DW1_LN0_C, \
1957 						    _CNL_PORT_PCS_DW1_LN0_D, \
1958 						    _CNL_PORT_PCS_DW1_LN0_AE, \
1959 						    _CNL_PORT_PCS_DW1_LN0_F))
1960 
1961 #define _ICL_PORT_PCS_AUX		0x300
1962 #define _ICL_PORT_PCS_GRP		0x600
1963 #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
1964 #define _ICL_PORT_PCS_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
1965 					 _ICL_PORT_PCS_AUX + 4 * (dw))
1966 #define _ICL_PORT_PCS_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
1967 					 _ICL_PORT_PCS_GRP + 4 * (dw))
1968 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1969 					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1970 #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1971 #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1972 #define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1973 #define   COMMON_KEEPER_EN		(1 << 26)
1974 #define   LATENCY_OPTIM_MASK		(0x3 << 2)
1975 #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
1976 
1977 /* CNL/ICL Port TX registers */
1978 #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
1979 #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
1980 #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
1981 #define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
1982 #define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
1983 #define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
1984 #define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
1985 #define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
1986 #define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
1987 #define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
1988 #define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \
1989 					       _CNL_PORT_TX_AE_GRP_OFFSET, \
1990 					       _CNL_PORT_TX_B_GRP_OFFSET, \
1991 					       _CNL_PORT_TX_B_GRP_OFFSET, \
1992 					       _CNL_PORT_TX_D_GRP_OFFSET, \
1993 					       _CNL_PORT_TX_AE_GRP_OFFSET, \
1994 					       _CNL_PORT_TX_F_GRP_OFFSET) + \
1995 					       4 * (dw))
1996 #define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \
1997 					       _CNL_PORT_TX_AE_LN0_OFFSET, \
1998 					       _CNL_PORT_TX_B_LN0_OFFSET, \
1999 					       _CNL_PORT_TX_B_LN0_OFFSET, \
2000 					       _CNL_PORT_TX_D_LN0_OFFSET, \
2001 					       _CNL_PORT_TX_AE_LN0_OFFSET, \
2002 					       _CNL_PORT_TX_F_LN0_OFFSET) + \
2003 					       4 * (dw))
2004 
2005 #define _ICL_PORT_TX_AUX		0x380
2006 #define _ICL_PORT_TX_GRP		0x680
2007 #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
2008 
2009 #define _ICL_PORT_TX_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
2010 					 _ICL_PORT_TX_AUX + 4 * (dw))
2011 #define _ICL_PORT_TX_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
2012 					 _ICL_PORT_TX_GRP + 4 * (dw))
2013 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
2014 					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
2015 
2016 #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
2017 #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
2018 #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
2019 #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
2020 #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
2021 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
2022 #define   SWING_SEL_UPPER_MASK		(1 << 15)
2023 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
2024 #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
2025 #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
2026 #define   FRC_LATENCY_OPTIM_VAL(x)	((x) << 8)
2027 #define   RCOMP_SCALAR(x)		((x) << 0)
2028 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
2029 
2030 #define _CNL_PORT_TX_DW4_LN0_AE		0x162450
2031 #define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
2032 #define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
2033 #define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
2034 #define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
2035 					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
2036 						    _CNL_PORT_TX_DW4_LN0_AE)))
2037 #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2038 #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
2039 #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
2040 #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
2041 #define   LOADGEN_SELECT		(1 << 31)
2042 #define   POST_CURSOR_1(x)		((x) << 12)
2043 #define   POST_CURSOR_1_MASK		(0x3F << 12)
2044 #define   POST_CURSOR_2(x)		((x) << 6)
2045 #define   POST_CURSOR_2_MASK		(0x3F << 6)
2046 #define   CURSOR_COEFF(x)		((x) << 0)
2047 #define   CURSOR_COEFF_MASK		(0x3F << 0)
2048 
2049 #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
2050 #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
2051 #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2052 #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
2053 #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
2054 #define   TX_TRAINING_EN		(1 << 31)
2055 #define   TAP2_DISABLE			(1 << 30)
2056 #define   TAP3_DISABLE			(1 << 29)
2057 #define   SCALING_MODE_SEL(x)		((x) << 18)
2058 #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
2059 #define   RTERM_SELECT(x)		((x) << 3)
2060 #define   RTERM_SELECT_MASK		(0x7 << 3)
2061 
2062 #define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
2063 #define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
2064 #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2065 #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
2066 #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
2067 #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
2068 #define   N_SCALAR(x)			((x) << 24)
2069 #define   N_SCALAR_MASK			(0x7F << 24)
2070 
2071 #define _ICL_DPHY_CHKN_REG			0x194
2072 #define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2073 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
2074 
2075 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2076 	_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2077 
2078 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
2079 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
2080 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
2081 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
2082 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
2083 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
2084 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
2085 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
2086 #define MG_TX1_LINK_PARAMS(ln, tc_port) \
2087 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2088 				    MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2089 				    MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2090 
2091 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
2092 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
2093 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
2094 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
2095 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
2096 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
2097 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
2098 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
2099 #define MG_TX2_LINK_PARAMS(ln, tc_port) \
2100 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2101 				    MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2102 				    MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2103 #define   CRI_USE_FS32			(1 << 5)
2104 
2105 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
2106 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
2107 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
2108 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
2109 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
2110 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
2111 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
2112 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
2113 #define MG_TX1_PISO_READLOAD(ln, tc_port) \
2114 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2115 				    MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2116 				    MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2117 
2118 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
2119 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
2120 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
2121 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
2122 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
2123 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
2124 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
2125 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
2126 #define MG_TX2_PISO_READLOAD(ln, tc_port) \
2127 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2128 				    MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2129 				    MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2130 #define   CRI_CALCINIT					(1 << 1)
2131 
2132 #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
2133 #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
2134 #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
2135 #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
2136 #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
2137 #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
2138 #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
2139 #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
2140 #define MG_TX1_SWINGCTRL(ln, tc_port) \
2141 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2142 				    MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2143 				    MG_TX_SWINGCTRL_TX1LN1_PORT1)
2144 
2145 #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
2146 #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
2147 #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
2148 #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
2149 #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
2150 #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
2151 #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
2152 #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
2153 #define MG_TX2_SWINGCTRL(ln, tc_port) \
2154 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2155 				    MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2156 				    MG_TX_SWINGCTRL_TX2LN1_PORT1)
2157 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
2158 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
2159 
2160 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
2161 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
2162 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
2163 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
2164 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
2165 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
2166 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
2167 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
2168 #define MG_TX1_DRVCTRL(ln, tc_port) \
2169 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2170 				    MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2171 				    MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2172 
2173 #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
2174 #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
2175 #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
2176 #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
2177 #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
2178 #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
2179 #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
2180 #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
2181 #define MG_TX2_DRVCTRL(ln, tc_port) \
2182 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2183 				    MG_TX_DRVCTRL_TX2LN0_PORT2, \
2184 				    MG_TX_DRVCTRL_TX2LN1_PORT1)
2185 #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
2186 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
2187 #define   CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)
2188 #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
2189 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
2190 #define   CRI_LOADGEN_SEL(x)				((x) << 12)
2191 #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
2192 
2193 #define MG_CLKHUB_LN0_PORT1			0x16839C
2194 #define MG_CLKHUB_LN1_PORT1			0x16879C
2195 #define MG_CLKHUB_LN0_PORT2			0x16939C
2196 #define MG_CLKHUB_LN1_PORT2			0x16979C
2197 #define MG_CLKHUB_LN0_PORT3			0x16A39C
2198 #define MG_CLKHUB_LN1_PORT3			0x16A79C
2199 #define MG_CLKHUB_LN0_PORT4			0x16B39C
2200 #define MG_CLKHUB_LN1_PORT4			0x16B79C
2201 #define MG_CLKHUB(ln, tc_port) \
2202 	MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2203 				    MG_CLKHUB_LN0_PORT2, \
2204 				    MG_CLKHUB_LN1_PORT1)
2205 #define   CFG_LOW_RATE_LKREN_EN				(1 << 11)
2206 
2207 #define MG_TX_DCC_TX1LN0_PORT1			0x168110
2208 #define MG_TX_DCC_TX1LN1_PORT1			0x168510
2209 #define MG_TX_DCC_TX1LN0_PORT2			0x169110
2210 #define MG_TX_DCC_TX1LN1_PORT2			0x169510
2211 #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
2212 #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
2213 #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
2214 #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
2215 #define MG_TX1_DCC(ln, tc_port) \
2216 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2217 				    MG_TX_DCC_TX1LN0_PORT2, \
2218 				    MG_TX_DCC_TX1LN1_PORT1)
2219 #define MG_TX_DCC_TX2LN0_PORT1			0x168090
2220 #define MG_TX_DCC_TX2LN1_PORT1			0x168490
2221 #define MG_TX_DCC_TX2LN0_PORT2			0x169090
2222 #define MG_TX_DCC_TX2LN1_PORT2			0x169490
2223 #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
2224 #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
2225 #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
2226 #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
2227 #define MG_TX2_DCC(ln, tc_port) \
2228 	MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2229 				    MG_TX_DCC_TX2LN0_PORT2, \
2230 				    MG_TX_DCC_TX2LN1_PORT1)
2231 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)	((x) << 25)
2232 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
2233 #define   CFG_AMI_CK_DIV_OVERRIDE_EN		(1 << 24)
2234 
2235 #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
2236 #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
2237 #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
2238 #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
2239 #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
2240 #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
2241 #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
2242 #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
2243 #define MG_DP_MODE(ln, tc_port)	\
2244 	MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2245 				    MG_DP_MODE_LN0_ACU_PORT2, \
2246 				    MG_DP_MODE_LN1_ACU_PORT1)
2247 #define   MG_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
2248 #define   MG_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
2249 
2250 /* The spec defines this only for BXT PHY0, but lets assume that this
2251  * would exist for PHY1 too if it had a second channel.
2252  */
2253 #define _PORT_CL2CM_DW6_A		0x162358
2254 #define _PORT_CL2CM_DW6_BC		0x6C358
2255 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2256 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
2257 
2258 #define FIA1_BASE			0x163000
2259 #define FIA2_BASE			0x16E000
2260 #define FIA3_BASE			0x16F000
2261 #define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2262 #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
2263 
2264 /* ICL PHY DFLEX registers */
2265 #define PORT_TX_DFLEXDPMLE1(fia)		_MMIO_FIA((fia),  0x008C0)
2266 #define   DFLEXDPMLE1_DPMLETC_MASK(idx)		(0xf << (4 * (idx)))
2267 #define   DFLEXDPMLE1_DPMLETC_ML0(idx)		(1 << (4 * (idx)))
2268 #define   DFLEXDPMLE1_DPMLETC_ML1_0(idx)	(3 << (4 * (idx)))
2269 #define   DFLEXDPMLE1_DPMLETC_ML3(idx)		(8 << (4 * (idx)))
2270 #define   DFLEXDPMLE1_DPMLETC_ML3_2(idx)	(12 << (4 * (idx)))
2271 #define   DFLEXDPMLE1_DPMLETC_ML3_0(idx)	(15 << (4 * (idx)))
2272 
2273 /* BXT PHY Ref registers */
2274 #define _PORT_REF_DW3_A			0x16218C
2275 #define _PORT_REF_DW3_BC		0x6C18C
2276 #define   GRC_DONE			(1 << 22)
2277 #define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC)
2278 
2279 #define _PORT_REF_DW6_A			0x162198
2280 #define _PORT_REF_DW6_BC		0x6C198
2281 #define   GRC_CODE_SHIFT		24
2282 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
2283 #define   GRC_CODE_FAST_SHIFT		16
2284 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
2285 #define   GRC_CODE_SLOW_SHIFT		8
2286 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
2287 #define   GRC_CODE_NOM_MASK		0xFF
2288 #define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC)
2289 
2290 #define _PORT_REF_DW8_A			0x1621A0
2291 #define _PORT_REF_DW8_BC		0x6C1A0
2292 #define   GRC_DIS			(1 << 15)
2293 #define   GRC_RDY_OVRD			(1 << 1)
2294 #define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC)
2295 
2296 /* BXT PHY PCS registers */
2297 #define _PORT_PCS_DW10_LN01_A		0x162428
2298 #define _PORT_PCS_DW10_LN01_B		0x6C428
2299 #define _PORT_PCS_DW10_LN01_C		0x6C828
2300 #define _PORT_PCS_DW10_GRP_A		0x162C28
2301 #define _PORT_PCS_DW10_GRP_B		0x6CC28
2302 #define _PORT_PCS_DW10_GRP_C		0x6CE28
2303 #define BXT_PORT_PCS_DW10_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2304 							 _PORT_PCS_DW10_LN01_B, \
2305 							 _PORT_PCS_DW10_LN01_C)
2306 #define BXT_PORT_PCS_DW10_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2307 							 _PORT_PCS_DW10_GRP_B, \
2308 							 _PORT_PCS_DW10_GRP_C)
2309 
2310 #define   TX2_SWING_CALC_INIT		(1 << 31)
2311 #define   TX1_SWING_CALC_INIT		(1 << 30)
2312 
2313 #define _PORT_PCS_DW12_LN01_A		0x162430
2314 #define _PORT_PCS_DW12_LN01_B		0x6C430
2315 #define _PORT_PCS_DW12_LN01_C		0x6C830
2316 #define _PORT_PCS_DW12_LN23_A		0x162630
2317 #define _PORT_PCS_DW12_LN23_B		0x6C630
2318 #define _PORT_PCS_DW12_LN23_C		0x6CA30
2319 #define _PORT_PCS_DW12_GRP_A		0x162c30
2320 #define _PORT_PCS_DW12_GRP_B		0x6CC30
2321 #define _PORT_PCS_DW12_GRP_C		0x6CE30
2322 #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
2323 #define   LANE_STAGGER_MASK		0x1F
2324 #define BXT_PORT_PCS_DW12_LN01(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2325 							 _PORT_PCS_DW12_LN01_B, \
2326 							 _PORT_PCS_DW12_LN01_C)
2327 #define BXT_PORT_PCS_DW12_LN23(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2328 							 _PORT_PCS_DW12_LN23_B, \
2329 							 _PORT_PCS_DW12_LN23_C)
2330 #define BXT_PORT_PCS_DW12_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2331 							 _PORT_PCS_DW12_GRP_B, \
2332 							 _PORT_PCS_DW12_GRP_C)
2333 
2334 /* BXT PHY TX registers */
2335 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
2336 					  ((lane) & 1) * 0x80)
2337 
2338 #define _PORT_TX_DW2_LN0_A		0x162508
2339 #define _PORT_TX_DW2_LN0_B		0x6C508
2340 #define _PORT_TX_DW2_LN0_C		0x6C908
2341 #define _PORT_TX_DW2_GRP_A		0x162D08
2342 #define _PORT_TX_DW2_GRP_B		0x6CD08
2343 #define _PORT_TX_DW2_GRP_C		0x6CF08
2344 #define BXT_PORT_TX_DW2_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2345 							 _PORT_TX_DW2_LN0_B, \
2346 							 _PORT_TX_DW2_LN0_C)
2347 #define BXT_PORT_TX_DW2_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2348 							 _PORT_TX_DW2_GRP_B, \
2349 							 _PORT_TX_DW2_GRP_C)
2350 #define   MARGIN_000_SHIFT		16
2351 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
2352 #define   UNIQ_TRANS_SCALE_SHIFT	8
2353 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
2354 
2355 #define _PORT_TX_DW3_LN0_A		0x16250C
2356 #define _PORT_TX_DW3_LN0_B		0x6C50C
2357 #define _PORT_TX_DW3_LN0_C		0x6C90C
2358 #define _PORT_TX_DW3_GRP_A		0x162D0C
2359 #define _PORT_TX_DW3_GRP_B		0x6CD0C
2360 #define _PORT_TX_DW3_GRP_C		0x6CF0C
2361 #define BXT_PORT_TX_DW3_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2362 							 _PORT_TX_DW3_LN0_B, \
2363 							 _PORT_TX_DW3_LN0_C)
2364 #define BXT_PORT_TX_DW3_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2365 							 _PORT_TX_DW3_GRP_B, \
2366 							 _PORT_TX_DW3_GRP_C)
2367 #define   SCALE_DCOMP_METHOD		(1 << 26)
2368 #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
2369 
2370 #define _PORT_TX_DW4_LN0_A		0x162510
2371 #define _PORT_TX_DW4_LN0_B		0x6C510
2372 #define _PORT_TX_DW4_LN0_C		0x6C910
2373 #define _PORT_TX_DW4_GRP_A		0x162D10
2374 #define _PORT_TX_DW4_GRP_B		0x6CD10
2375 #define _PORT_TX_DW4_GRP_C		0x6CF10
2376 #define BXT_PORT_TX_DW4_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2377 							 _PORT_TX_DW4_LN0_B, \
2378 							 _PORT_TX_DW4_LN0_C)
2379 #define BXT_PORT_TX_DW4_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2380 							 _PORT_TX_DW4_GRP_B, \
2381 							 _PORT_TX_DW4_GRP_C)
2382 #define   DEEMPH_SHIFT			24
2383 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
2384 
2385 #define _PORT_TX_DW5_LN0_A		0x162514
2386 #define _PORT_TX_DW5_LN0_B		0x6C514
2387 #define _PORT_TX_DW5_LN0_C		0x6C914
2388 #define _PORT_TX_DW5_GRP_A		0x162D14
2389 #define _PORT_TX_DW5_GRP_B		0x6CD14
2390 #define _PORT_TX_DW5_GRP_C		0x6CF14
2391 #define BXT_PORT_TX_DW5_LN0(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2392 							 _PORT_TX_DW5_LN0_B, \
2393 							 _PORT_TX_DW5_LN0_C)
2394 #define BXT_PORT_TX_DW5_GRP(phy, ch)	_MMIO_BXT_PHY_CH(phy, ch, \
2395 							 _PORT_TX_DW5_GRP_B, \
2396 							 _PORT_TX_DW5_GRP_C)
2397 #define   DCC_DELAY_RANGE_1		(1 << 9)
2398 #define   DCC_DELAY_RANGE_2		(1 << 8)
2399 
2400 #define _PORT_TX_DW14_LN0_A		0x162538
2401 #define _PORT_TX_DW14_LN0_B		0x6C538
2402 #define _PORT_TX_DW14_LN0_C		0x6C938
2403 #define   LATENCY_OPTIM_SHIFT		30
2404 #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
2405 #define BXT_PORT_TX_DW14_LN(phy, ch, lane)				\
2406 	_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,			\
2407 				   _PORT_TX_DW14_LN0_C) +		\
2408 	      _BXT_LANE_OFFSET(lane))
2409 
2410 /* UAIMI scratch pad register 1 */
2411 #define UAIMI_SPR1			_MMIO(0x4F074)
2412 /* SKL VccIO mask */
2413 #define SKL_VCCIO_MASK			0x1
2414 /* SKL balance leg register */
2415 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
2416 /* I_boost values */
2417 #define BALANCE_LEG_SHIFT(port)		(8 + 3 * (port))
2418 #define BALANCE_LEG_MASK(port)		(7 << (8 + 3 * (port)))
2419 /* Balance leg disable bits */
2420 #define BALANCE_LEG_DISABLE_SHIFT	23
2421 #define BALANCE_LEG_DISABLE(port)	(1 << (23 + (port)))
2422 
2423 /*
2424  * Fence registers
2425  * [0-7]  @ 0x2000 gen2,gen3
2426  * [8-15] @ 0x3000 945,g33,pnv
2427  *
2428  * [0-15] @ 0x3000 gen4,gen5
2429  *
2430  * [0-15] @ 0x100000 gen6,vlv,chv
2431  * [0-31] @ 0x100000 gen7+
2432  */
2433 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2434 #define   I830_FENCE_START_MASK		0x07f80000
2435 #define   I830_FENCE_TILING_Y_SHIFT	12
2436 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
2437 #define   I830_FENCE_PITCH_SHIFT	4
2438 #define   I830_FENCE_REG_VALID		(1 << 0)
2439 #define   I915_FENCE_MAX_PITCH_VAL	4
2440 #define   I830_FENCE_MAX_PITCH_VAL	6
2441 #define   I830_FENCE_MAX_SIZE_VAL	(1 << 8)
2442 
2443 #define   I915_FENCE_START_MASK		0x0ff00000
2444 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
2445 
2446 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
2447 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
2448 #define   I965_FENCE_PITCH_SHIFT	2
2449 #define   I965_FENCE_TILING_Y_SHIFT	1
2450 #define   I965_FENCE_REG_VALID		(1 << 0)
2451 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
2452 
2453 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
2454 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
2455 #define   GEN6_FENCE_PITCH_SHIFT	32
2456 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2457 
2458 
2459 /* control register for cpu gtt access */
2460 #define TILECTL				_MMIO(0x101000)
2461 #define   TILECTL_SWZCTL			(1 << 0)
2462 #define   TILECTL_TLBPF			(1 << 1)
2463 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
2464 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
2465 
2466 /*
2467  * Instruction and interrupt control regs
2468  */
2469 #define PGTBL_CTL	_MMIO(0x02020)
2470 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
2471 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
2472 #define PGTBL_ER	_MMIO(0x02024)
2473 #define PRB0_BASE	(0x2030 - 0x30)
2474 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
2475 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
2476 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
2477 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
2478 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
2479 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
2480 #define RENDER_RING_BASE	0x02000
2481 #define BSD_RING_BASE		0x04000
2482 #define GEN6_BSD_RING_BASE	0x12000
2483 #define GEN8_BSD2_RING_BASE	0x1c000
2484 #define GEN11_BSD_RING_BASE	0x1c0000
2485 #define GEN11_BSD2_RING_BASE	0x1c4000
2486 #define GEN11_BSD3_RING_BASE	0x1d0000
2487 #define GEN11_BSD4_RING_BASE	0x1d4000
2488 #define VEBOX_RING_BASE		0x1a000
2489 #define GEN11_VEBOX_RING_BASE		0x1c8000
2490 #define GEN11_VEBOX2_RING_BASE		0x1d8000
2491 #define BLT_RING_BASE		0x22000
2492 #define RING_TAIL(base)		_MMIO((base) + 0x30)
2493 #define RING_HEAD(base)		_MMIO((base) + 0x34)
2494 #define RING_START(base)	_MMIO((base) + 0x38)
2495 #define RING_CTL(base)		_MMIO((base) + 0x3c)
2496 #define   RING_CTL_SIZE(size)	((size) - PAGE_SIZE) /* in bytes -> pages */
2497 #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
2498 #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
2499 #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
2500 #define GEN6_RVSYNC	(RING_SYNC_0(RENDER_RING_BASE))
2501 #define GEN6_RBSYNC	(RING_SYNC_1(RENDER_RING_BASE))
2502 #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
2503 #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
2504 #define GEN6_VRSYNC	(RING_SYNC_1(GEN6_BSD_RING_BASE))
2505 #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
2506 #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
2507 #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
2508 #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
2509 #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
2510 #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
2511 #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
2512 #define GEN6_NOSYNC	INVALID_MMIO_REG
2513 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
2514 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
2515 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
2516 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
2517 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
2518 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
2519 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
2520 #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
2521 
2522 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2523 
2524 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
2525 #define   GTT_CACHE_EN_ALL	0xF0007FFF
2526 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
2527 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
2528 #define ARB_MODE		_MMIO(0x4030)
2529 #define   ARB_MODE_SWIZZLE_SNB	(1 << 4)
2530 #define   ARB_MODE_SWIZZLE_IVB	(1 << 5)
2531 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
2532 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
2533 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2534 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
2535 #define GEN7_LRA_LIMITS_REG_NUM	13
2536 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
2537 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
2538 
2539 #define GAMTARBMODE		_MMIO(0x04a08)
2540 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
2541 #define   ARB_MODE_SWIZZLE_BDW	(1 << 1)
2542 #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
2543 #define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100 * (engine)->hw_id)
2544 #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
2545 #define GEN12_RING_FAULT_REG	_MMIO(0xcec4)
2546 #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
2547 #define   RING_FAULT_GTTSEL_MASK (1 << 11)
2548 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
2549 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2550 #define   RING_FAULT_VALID	(1 << 0)
2551 #define DONE_REG		_MMIO(0x40b0)
2552 #define GEN12_GAM_DONE		_MMIO(0xcf68)
2553 #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
2554 #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
2555 #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
2556 #define GEN12_PAT_INDEX(index)	_MMIO(0x4800 + (index) * 4)
2557 #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
2558 #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
2559 #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
2560 #define RING_ACTHD(base)	_MMIO((base) + 0x74)
2561 #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
2562 #define RING_NOPID(base)	_MMIO((base) + 0x94)
2563 #define RING_IMR(base)		_MMIO((base) + 0xa8)
2564 #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
2565 #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
2566 #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
2567 #define   TAIL_ADDR		0x001FFFF8
2568 #define   HEAD_WRAP_COUNT	0xFFE00000
2569 #define   HEAD_WRAP_ONE		0x00200000
2570 #define   HEAD_ADDR		0x001FFFFC
2571 #define   RING_NR_PAGES		0x001FF000
2572 #define   RING_REPORT_MASK	0x00000006
2573 #define   RING_REPORT_64K	0x00000002
2574 #define   RING_REPORT_128K	0x00000004
2575 #define   RING_NO_REPORT	0x00000000
2576 #define   RING_VALID_MASK	0x00000001
2577 #define   RING_VALID		0x00000001
2578 #define   RING_INVALID		0x00000000
2579 #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
2580 #define   RING_WAIT		(1 << 11) /* gen3+, PRBx_CTL */
2581 #define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */
2582 
2583 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2584 #define GEN8_RING_CS_GPR(base, n)	_MMIO((base) + 0x600 + (n) * 8)
2585 #define GEN8_RING_CS_GPR_UDW(base, n)	_MMIO((base) + 0x600 + (n) * 8 + 4)
2586 
2587 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2588 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)
2589 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
2590 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)
2591 #define   RING_FORCE_TO_NONPRIV_ACCESS_WR	(2 << 28)
2592 #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID	(3 << 28)
2593 #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	(3 << 28)
2594 #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
2595 #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
2596 #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
2597 #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
2598 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
2599 #define   RING_FORCE_TO_NONPRIV_MASK_VALID	\
2600 					(RING_FORCE_TO_NONPRIV_RANGE_MASK \
2601 					| RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2602 #define   RING_MAX_NONPRIV_SLOTS  12
2603 
2604 #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
2605 
2606 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2607 #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS	(1 << 18)
2608 
2609 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2610 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2611 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
2612 
2613 #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
2614 #define   GAMT_CHKN_DISABLE_L3_COH_PIPE			(1 << 31)
2615 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1 << 28)
2616 #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1 << 24)
2617 
2618 #if 0
2619 #define PRB0_TAIL	_MMIO(0x2030)
2620 #define PRB0_HEAD	_MMIO(0x2034)
2621 #define PRB0_START	_MMIO(0x2038)
2622 #define PRB0_CTL	_MMIO(0x203c)
2623 #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
2624 #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
2625 #define PRB1_START	_MMIO(0x2048) /* 915+ only */
2626 #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
2627 #endif
2628 #define IPEIR_I965	_MMIO(0x2064)
2629 #define IPEHR_I965	_MMIO(0x2068)
2630 #define GEN7_SC_INSTDONE	_MMIO(0x7100)
2631 #define GEN12_SC_INSTDONE_EXTRA		_MMIO(0x7104)
2632 #define GEN12_SC_INSTDONE_EXTRA2	_MMIO(0x7108)
2633 #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
2634 #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
2635 #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
2636 #define   GEN8_MCR_SLICE(slice)		(((slice) & 3) << 26)
2637 #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
2638 #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
2639 #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
2640 #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
2641 #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
2642 #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
2643 #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
2644 #define RING_IPEIR(base)	_MMIO((base) + 0x64)
2645 #define RING_IPEHR(base)	_MMIO((base) + 0x68)
2646 #define RING_EIR(base)		_MMIO((base) + 0xb0)
2647 #define RING_EMR(base)		_MMIO((base) + 0xb4)
2648 #define RING_ESR(base)		_MMIO((base) + 0xb8)
2649 /*
2650  * On GEN4, only the render ring INSTDONE exists and has a different
2651  * layout than the GEN7+ version.
2652  * The GEN2 counterpart of this register is GEN2_INSTDONE.
2653  */
2654 #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
2655 #define RING_INSTPS(base)	_MMIO((base) + 0x70)
2656 #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
2657 #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
2658 #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
2659 #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
2660 #define INSTPS		_MMIO(0x2070) /* 965+ only */
2661 #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2662 #define ACTHD_I965	_MMIO(0x2074)
2663 #define HWS_PGA		_MMIO(0x2080)
2664 #define HWS_ADDRESS_MASK	0xfffff000
2665 #define HWS_START_ADDRESS_SHIFT	4
2666 #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
2667 #define   PWRCTX_EN	(1 << 0)
2668 #define IPEIR(base)	_MMIO((base) + 0x88)
2669 #define IPEHR(base)	_MMIO((base) + 0x8c)
2670 #define GEN2_INSTDONE	_MMIO(0x2090)
2671 #define NOPID		_MMIO(0x2094)
2672 #define HWSTAM		_MMIO(0x2098)
2673 #define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)
2674 #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
2675 #define   RING_BB_PPGTT		(1 << 5)
2676 #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
2677 #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
2678 #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
2679 #define RING_BBADDR(base)	_MMIO((base) + 0x140)
2680 #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
2681 #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
2682 #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
2683 #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
2684 #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
2685 
2686 #define ERROR_GEN6	_MMIO(0x40a0)
2687 #define GEN7_ERR_INT	_MMIO(0x44040)
2688 #define   ERR_INT_POISON		(1 << 31)
2689 #define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
2690 #define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
2691 #define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
2692 #define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
2693 #define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
2694 #define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
2695 #define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
2696 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
2697 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
2698 
2699 #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
2700 #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
2701 #define GEN12_FAULT_TLB_DATA0		_MMIO(0xceb8)
2702 #define GEN12_FAULT_TLB_DATA1		_MMIO(0xcebc)
2703 #define   FAULT_VA_HIGH_BITS		(0xf << 0)
2704 #define   FAULT_GTT_SEL			(1 << 4)
2705 
2706 #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
2707 
2708 #define FPGA_DBG		_MMIO(0x42300)
2709 #define   FPGA_DBG_RM_NOCLAIM	(1 << 31)
2710 
2711 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
2712 #define   CLAIM_ER_CLR		(1 << 31)
2713 #define   CLAIM_ER_OVERFLOW	(1 << 16)
2714 #define   CLAIM_ER_CTR_MASK	0xffff
2715 
2716 #define DERRMR		_MMIO(0x44050)
2717 /* Note that HBLANK events are reserved on bdw+ */
2718 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
2719 #define   DERRMR_PIPEA_PRI_FLIP_DONE	(1 << 1)
2720 #define   DERRMR_PIPEA_SPR_FLIP_DONE	(1 << 2)
2721 #define   DERRMR_PIPEA_VBLANK		(1 << 3)
2722 #define   DERRMR_PIPEA_HBLANK		(1 << 5)
2723 #define   DERRMR_PIPEB_SCANLINE		(1 << 8)
2724 #define   DERRMR_PIPEB_PRI_FLIP_DONE	(1 << 9)
2725 #define   DERRMR_PIPEB_SPR_FLIP_DONE	(1 << 10)
2726 #define   DERRMR_PIPEB_VBLANK		(1 << 11)
2727 #define   DERRMR_PIPEB_HBLANK		(1 << 13)
2728 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2729 #define   DERRMR_PIPEC_SCANLINE		(1 << 14)
2730 #define   DERRMR_PIPEC_PRI_FLIP_DONE	(1 << 15)
2731 #define   DERRMR_PIPEC_SPR_FLIP_DONE	(1 << 20)
2732 #define   DERRMR_PIPEC_VBLANK		(1 << 21)
2733 #define   DERRMR_PIPEC_HBLANK		(1 << 22)
2734 
2735 
2736 /* GM45+ chicken bits -- debug workaround bits that may be required
2737  * for various sorts of correct behavior.  The top 16 bits of each are
2738  * the enables for writing to the corresponding low bit.
2739  */
2740 #define _3D_CHICKEN	_MMIO(0x2084)
2741 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
2742 #define _3D_CHICKEN2	_MMIO(0x208c)
2743 
2744 #define FF_SLICE_CHICKEN	_MMIO(0x2088)
2745 #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX	(1 << 1)
2746 
2747 /* Disables pipelining of read flushes past the SF-WIZ interface.
2748  * Required on all Ironlake steppings according to the B-Spec, but the
2749  * particular danger of not doing so is not specified.
2750  */
2751 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
2752 #define _3D_CHICKEN3	_MMIO(0x2090)
2753 #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX		(1 << 12)
2754 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
2755 #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
2756 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
2757 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x) << 1) /* gen8+ */
2758 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
2759 
2760 #define MI_MODE		_MMIO(0x209c)
2761 # define VS_TIMER_DISPATCH				(1 << 6)
2762 # define MI_FLUSH_ENABLE				(1 << 12)
2763 # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
2764 # define MODE_IDLE					(1 << 9)
2765 # define STOP_RING					(1 << 8)
2766 
2767 #define GEN6_GT_MODE	_MMIO(0x20d0)
2768 #define GEN7_GT_MODE	_MMIO(0x7008)
2769 #define   GEN6_WIZ_HASHING(hi, lo)			(((hi) << 9) | ((lo) << 7))
2770 #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
2771 #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
2772 #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
2773 #define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)
2774 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
2775 #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
2776 #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
2777 
2778 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2779 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2780 #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2781 #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2782 
2783 /* WaClearTdlStateAckDirtyBits */
2784 #define GEN8_STATE_ACK		_MMIO(0x20F0)
2785 #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
2786 #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
2787 #define   GEN9_STATE_ACK_TDL0 (1 << 12)
2788 #define   GEN9_STATE_ACK_TDL1 (1 << 13)
2789 #define   GEN9_STATE_ACK_TDL2 (1 << 14)
2790 #define   GEN9_STATE_ACK_TDL3 (1 << 15)
2791 #define   GEN9_SUBSLICE_TDL_ACK_BITS \
2792 	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2793 	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2794 
2795 #define GFX_MODE	_MMIO(0x2520)
2796 #define GFX_MODE_GEN7	_MMIO(0x229c)
2797 #define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
2798 #define   GFX_RUN_LIST_ENABLE		(1 << 15)
2799 #define   GFX_INTERRUPT_STEERING	(1 << 14)
2800 #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
2801 #define   GFX_SURFACE_FAULT_ENABLE	(1 << 12)
2802 #define   GFX_REPLAY_MODE		(1 << 11)
2803 #define   GFX_PSMI_GRANULARITY		(1 << 10)
2804 #define   GFX_PPGTT_ENABLE		(1 << 9)
2805 #define   GEN8_GFX_PPGTT_48B		(1 << 7)
2806 
2807 #define   GFX_FORWARD_VBLANK_MASK	(3 << 5)
2808 #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
2809 #define   GFX_FORWARD_VBLANK_ALWAYS	(1 << 5)
2810 #define   GFX_FORWARD_VBLANK_COND	(2 << 5)
2811 
2812 #define   GEN11_GFX_DISABLE_LEGACY_MODE	(1 << 3)
2813 
2814 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
2815 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
2816 #define SCPD0		_MMIO(0x209c) /* 915+ only */
2817 #define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
2818 #define GEN2_IER	_MMIO(0x20a0)
2819 #define GEN2_IIR	_MMIO(0x20a4)
2820 #define GEN2_IMR	_MMIO(0x20a8)
2821 #define GEN2_ISR	_MMIO(0x20ac)
2822 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
2823 #define   GINT_DIS		(1 << 22)
2824 #define   GCFG_DIS		(1 << 8)
2825 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
2826 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
2827 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
2828 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
2829 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
2830 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
2831 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
2832 #define VLV_PCBR_ADDR_SHIFT	12
2833 
2834 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2835 #define EIR		_MMIO(0x20b0)
2836 #define EMR		_MMIO(0x20b4)
2837 #define ESR		_MMIO(0x20b8)
2838 #define   GM45_ERROR_PAGE_TABLE				(1 << 5)
2839 #define   GM45_ERROR_MEM_PRIV				(1 << 4)
2840 #define   I915_ERROR_PAGE_TABLE				(1 << 4)
2841 #define   GM45_ERROR_CP_PRIV				(1 << 3)
2842 #define   I915_ERROR_MEMORY_REFRESH			(1 << 1)
2843 #define   I915_ERROR_INSTRUCTION			(1 << 0)
2844 #define INSTPM	        _MMIO(0x20c0)
2845 #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
2846 #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2847 					will not assert AGPBUSY# and will only
2848 					be delivered when out of C3. */
2849 #define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
2850 #define   INSTPM_TLB_INVALIDATE	(1 << 9)
2851 #define   INSTPM_SYNC_FLUSH	(1 << 5)
2852 #define ACTHD(base)	_MMIO((base) + 0xc8)
2853 #define MEM_MODE	_MMIO(0x20cc)
2854 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2855 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2856 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2857 #define FW_BLC		_MMIO(0x20d8)
2858 #define FW_BLC2		_MMIO(0x20dc)
2859 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
2860 #define   FW_BLC_SELF_EN_MASK      (1 << 31)
2861 #define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
2862 #define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
2863 #define MM_BURST_LENGTH     0x00700000
2864 #define MM_FIFO_WATERMARK   0x0001F000
2865 #define LM_BURST_LENGTH     0x00000700
2866 #define LM_FIFO_WATERMARK   0x0000001F
2867 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
2868 
2869 #define MBUS_ABOX_CTL			_MMIO(0x45038)
2870 #define MBUS_ABOX1_CTL			_MMIO(0x45048)
2871 #define MBUS_ABOX2_CTL			_MMIO(0x4504C)
2872 #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
2873 #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
2874 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
2875 #define MBUS_ABOX_B_CREDIT(x)		((x) << 16)
2876 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
2877 #define MBUS_ABOX_BT_CREDIT_POOL2(x)	((x) << 8)
2878 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
2879 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
2880 
2881 #define _PIPEA_MBUS_DBOX_CTL		0x7003C
2882 #define _PIPEB_MBUS_DBOX_CTL		0x7103C
2883 #define PIPE_MBUS_DBOX_CTL(pipe)	_MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2884 						   _PIPEB_MBUS_DBOX_CTL)
2885 #define MBUS_DBOX_BW_CREDIT_MASK	(3 << 14)
2886 #define MBUS_DBOX_BW_CREDIT(x)		((x) << 14)
2887 #define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
2888 #define MBUS_DBOX_B_CREDIT(x)		((x) << 8)
2889 #define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
2890 #define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
2891 
2892 #define MBUS_UBOX_CTL			_MMIO(0x4503C)
2893 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
2894 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
2895 
2896 /* Make render/texture TLB fetches lower priorty than associated data
2897  *   fetches. This is not turned on by default
2898  */
2899 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
2900 
2901 /* Isoch request wait on GTT enable (Display A/B/C streams).
2902  * Make isoch requests stall on the TLB update. May cause
2903  * display underruns (test mode only)
2904  */
2905 #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
2906 
2907 /* Block grant count for isoch requests when block count is
2908  * set to a finite value.
2909  */
2910 #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
2911 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
2912 #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
2913 #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
2914 #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
2915 
2916 /* Enable render writes to complete in C2/C3/C4 power states.
2917  * If this isn't enabled, render writes are prevented in low
2918  * power states. That seems bad to me.
2919  */
2920 #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
2921 
2922 /* This acknowledges an async flip immediately instead
2923  * of waiting for 2TLB fetches.
2924  */
2925 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
2926 
2927 /* Enables non-sequential data reads through arbiter
2928  */
2929 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
2930 
2931 /* Disable FSB snooping of cacheable write cycles from binner/render
2932  * command stream
2933  */
2934 #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
2935 
2936 /* Arbiter time slice for non-isoch streams */
2937 #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
2938 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
2939 #define   MI_ARB_TIME_SLICE_2			(1 << 5)
2940 #define   MI_ARB_TIME_SLICE_4			(2 << 5)
2941 #define   MI_ARB_TIME_SLICE_6			(3 << 5)
2942 #define   MI_ARB_TIME_SLICE_8			(4 << 5)
2943 #define   MI_ARB_TIME_SLICE_10			(5 << 5)
2944 #define   MI_ARB_TIME_SLICE_14			(6 << 5)
2945 #define   MI_ARB_TIME_SLICE_16			(7 << 5)
2946 
2947 /* Low priority grace period page size */
2948 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
2949 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
2950 
2951 /* Disable display A/B trickle feed */
2952 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
2953 
2954 /* Set display plane priority */
2955 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
2956 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
2957 
2958 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
2959 #define   MI_AGPBUSY_INT_EN			(1 << 1) /* 85x only */
2960 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
2961 
2962 #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
2963 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2964 #define   CM0_IZ_OPT_DISABLE      (1 << 6)
2965 #define   CM0_ZR_OPT_DISABLE      (1 << 5)
2966 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1 << 5)
2967 #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
2968 #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
2969 #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
2970 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2971 #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
2972 #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
2973 #define   GFX_FLSH_CNTL_EN	(1 << 0)
2974 #define ECOSKPD		_MMIO(0x21d0)
2975 #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
2976 #define   ECO_GATING_CX_ONLY	(1 << 3)
2977 #define   ECO_FLIP_DONE		(1 << 0)
2978 
2979 #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
2980 #define RC_OP_FLUSH_ENABLE (1 << 0)
2981 #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2982 #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
2983 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE	(1 << 6)
2984 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)
2985 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)
2986 
2987 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
2988 #define   GEN6_BLITTER_LOCK_SHIFT			16
2989 #define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)
2990 
2991 #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
2992 #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
2993 #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
2994 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
2995 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1 << 10)
2996 
2997 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2998 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2999 
3000 #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
3001 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
3002 
3003 /* Fuse readout registers for GT */
3004 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
3005 #define   HSW_F1_EU_DIS_SHIFT		16
3006 #define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
3007 #define   HSW_F1_EU_DIS_10EUS		0
3008 #define   HSW_F1_EU_DIS_8EUS		1
3009 #define   HSW_F1_EU_DIS_6EUS		2
3010 
3011 #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
3012 #define   CHV_FGT_DISABLE_SS0		(1 << 10)
3013 #define   CHV_FGT_DISABLE_SS1		(1 << 11)
3014 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
3015 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3016 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
3017 #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3018 #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
3019 #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3020 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
3021 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3022 
3023 #define GEN8_FUSE2			_MMIO(0x9120)
3024 #define   GEN8_F2_SS_DIS_SHIFT		21
3025 #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
3026 #define   GEN8_F2_S_ENA_SHIFT		25
3027 #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
3028 
3029 #define   GEN9_F2_SS_DIS_SHIFT		20
3030 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
3031 
3032 #define   GEN10_F2_S_ENA_SHIFT		22
3033 #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
3034 #define   GEN10_F2_SS_DIS_SHIFT		18
3035 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
3036 
3037 #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
3038 #define GEN10_L3BANK_PAIR_COUNT     4
3039 #define GEN10_L3BANK_MASK   0x0F
3040 
3041 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
3042 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
3043 #define   GEN8_EU_DIS0_S1_SHIFT		24
3044 #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
3045 
3046 #define GEN8_EU_DISABLE1		_MMIO(0x9138)
3047 #define   GEN8_EU_DIS1_S1_MASK		0xffff
3048 #define   GEN8_EU_DIS1_S2_SHIFT		16
3049 #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
3050 
3051 #define GEN8_EU_DISABLE2		_MMIO(0x913c)
3052 #define   GEN8_EU_DIS2_S2_MASK		0xff
3053 
3054 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
3055 
3056 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
3057 #define   GEN10_EU_DIS_SS_MASK		0xff
3058 
3059 #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
3060 #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
3061 #define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
3062 #define   GEN11_GT_VEBOX_DISABLE_MASK	(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3063 
3064 #define GEN11_EU_DISABLE _MMIO(0x9134)
3065 #define GEN11_EU_DIS_MASK 0xFF
3066 
3067 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3068 #define GEN11_GT_S_ENA_MASK 0xFF
3069 
3070 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3071 
3072 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
3073 
3074 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
3075 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
3076 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
3077 #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
3078 #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
3079 
3080 /* On modern GEN architectures interrupt control consists of two sets
3081  * of registers. The first set pertains to the ring generating the
3082  * interrupt. The second control is for the functional block generating the
3083  * interrupt. These are PM, GT, DE, etc.
3084  *
3085  * Luckily *knocks on wood* all the ring interrupt bits match up with the
3086  * GT interrupt bits, so we don't need to duplicate the defines.
3087  *
3088  * These defines should cover us well from SNB->HSW with minor exceptions
3089  * it can also work on ILK.
3090  */
3091 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
3092 #define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
3093 #define GT_BLT_USER_INTERRUPT			(1 << 22)
3094 #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
3095 #define GT_BSD_USER_INTERRUPT			(1 << 12)
3096 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
3097 #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
3098 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
3099 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
3100 #define GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
3101 #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
3102 #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
3103 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
3104 
3105 #define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
3106 #define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
3107 
3108 #define GT_PARITY_ERROR(dev_priv) \
3109 	(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3110 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3111 
3112 /* These are all the "old" interrupts */
3113 #define ILK_BSD_USER_INTERRUPT				(1 << 5)
3114 
3115 #define I915_PM_INTERRUPT				(1 << 31)
3116 #define I915_ISP_INTERRUPT				(1 << 22)
3117 #define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
3118 #define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
3119 #define I915_MIPIC_INTERRUPT				(1 << 19)
3120 #define I915_MIPIA_INTERRUPT				(1 << 18)
3121 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
3122 #define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
3123 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
3124 #define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
3125 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
3126 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
3127 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
3128 #define I915_HWB_OOM_INTERRUPT				(1 << 13)
3129 #define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
3130 #define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
3131 #define I915_MISC_INTERRUPT				(1 << 11)
3132 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
3133 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
3134 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
3135 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
3136 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
3137 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
3138 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
3139 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
3140 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
3141 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
3142 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
3143 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
3144 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
3145 #define I915_DEBUG_INTERRUPT				(1 << 2)
3146 #define I915_WINVALID_INTERRUPT				(1 << 1)
3147 #define I915_USER_INTERRUPT				(1 << 1)
3148 #define I915_ASLE_INTERRUPT				(1 << 0)
3149 #define I915_BSD_USER_INTERRUPT				(1 << 25)
3150 
3151 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
3152 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
3153 
3154 /* DisplayPort Audio w/ LPE */
3155 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
3156 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
3157 
3158 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
3159 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
3160 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
3161 #define VLV_AUD_PORT_EN_DBG(port)	_MMIO_PORT3((port) - PORT_B,	   \
3162 						    _VLV_AUD_PORT_EN_B_DBG, \
3163 						    _VLV_AUD_PORT_EN_C_DBG, \
3164 						    _VLV_AUD_PORT_EN_D_DBG)
3165 #define VLV_AMP_MUTE		        (1 << 1)
3166 
3167 #define GEN6_BSD_RNCID			_MMIO(0x12198)
3168 
3169 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
3170 #define   GEN7_FF_SCHED_MASK		0x0077070
3171 #define   GEN8_FF_DS_REF_CNT_FFME	(1 << 19)
3172 #define   GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
3173 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
3174 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
3175 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
3176 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
3177 #define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
3178 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
3179 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
3180 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
3181 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
3182 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
3183 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
3184 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
3185 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
3186 
3187 /*
3188  * Framebuffer compression (915+ only)
3189  */
3190 
3191 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
3192 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
3193 #define FBC_CONTROL		_MMIO(0x3208)
3194 #define   FBC_CTL_EN		(1 << 31)
3195 #define   FBC_CTL_PERIODIC	(1 << 30)
3196 #define   FBC_CTL_INTERVAL_SHIFT (16)
3197 #define   FBC_CTL_UNCOMPRESSIBLE (1 << 14)
3198 #define   FBC_CTL_C3_IDLE	(1 << 13)
3199 #define   FBC_CTL_STRIDE_SHIFT	(5)
3200 #define   FBC_CTL_FENCENO_SHIFT	(0)
3201 #define FBC_COMMAND		_MMIO(0x320c)
3202 #define   FBC_CMD_COMPRESS	(1 << 0)
3203 #define FBC_STATUS		_MMIO(0x3210)
3204 #define   FBC_STAT_COMPRESSING	(1 << 31)
3205 #define   FBC_STAT_COMPRESSED	(1 << 30)
3206 #define   FBC_STAT_MODIFIED	(1 << 29)
3207 #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
3208 #define FBC_CONTROL2		_MMIO(0x3214)
3209 #define   FBC_CTL_FENCE_DBL	(0 << 4)
3210 #define   FBC_CTL_IDLE_IMM	(0 << 2)
3211 #define   FBC_CTL_IDLE_FULL	(1 << 2)
3212 #define   FBC_CTL_IDLE_LINE	(2 << 2)
3213 #define   FBC_CTL_IDLE_DEBUG	(3 << 2)
3214 #define   FBC_CTL_CPU_FENCE	(1 << 1)
3215 #define   FBC_CTL_PLANE(plane)	((plane) << 0)
3216 #define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
3217 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
3218 
3219 #define FBC_LL_SIZE		(1536)
3220 
3221 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
3222 #define   FBC_LLC_FULLY_OPEN	(1 << 30)
3223 
3224 /* Framebuffer compression for GM45+ */
3225 #define DPFC_CB_BASE		_MMIO(0x3200)
3226 #define DPFC_CONTROL		_MMIO(0x3208)
3227 #define   DPFC_CTL_EN		(1 << 31)
3228 #define   DPFC_CTL_PLANE(plane)	((plane) << 30)
3229 #define   IVB_DPFC_CTL_PLANE(plane)	((plane) << 29)
3230 #define   DPFC_CTL_FENCE_EN	(1 << 29)
3231 #define   IVB_DPFC_CTL_FENCE_EN	(1 << 28)
3232 #define   DPFC_CTL_PERSISTENT_MODE	(1 << 25)
3233 #define   DPFC_SR_EN		(1 << 10)
3234 #define   DPFC_CTL_LIMIT_1X	(0 << 6)
3235 #define   DPFC_CTL_LIMIT_2X	(1 << 6)
3236 #define   DPFC_CTL_LIMIT_4X	(2 << 6)
3237 #define DPFC_RECOMP_CTL		_MMIO(0x320c)
3238 #define   DPFC_RECOMP_STALL_EN	(1 << 27)
3239 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
3240 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3241 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3242 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3243 #define DPFC_STATUS		_MMIO(0x3210)
3244 #define   DPFC_INVAL_SEG_SHIFT  (16)
3245 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
3246 #define   DPFC_COMP_SEG_SHIFT	(0)
3247 #define   DPFC_COMP_SEG_MASK	(0x000007ff)
3248 #define DPFC_STATUS2		_MMIO(0x3214)
3249 #define DPFC_FENCE_YOFF		_MMIO(0x3218)
3250 #define DPFC_CHICKEN		_MMIO(0x3224)
3251 #define   DPFC_HT_MODIFY	(1 << 31)
3252 
3253 /* Framebuffer compression for Ironlake */
3254 #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
3255 #define ILK_DPFC_CONTROL	_MMIO(0x43208)
3256 #define   FBC_CTL_FALSE_COLOR	(1 << 10)
3257 /* The bit 28-8 is reserved */
3258 #define   DPFC_RESERVED		(0x1FFFFF00)
3259 #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
3260 #define ILK_DPFC_STATUS		_MMIO(0x43210)
3261 #define  ILK_DPFC_COMP_SEG_MASK	0x7ff
3262 #define IVB_FBC_STATUS2		_MMIO(0x43214)
3263 #define  IVB_FBC_COMP_SEG_MASK	0x7ff
3264 #define  BDW_FBC_COMP_SEG_MASK	0xfff
3265 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
3266 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
3267 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3268 #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL	(1 << 14)
3269 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1 << 23)
3270 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
3271 #define   ILK_FBC_RT_VALID	(1 << 0)
3272 #define   SNB_FBC_FRONT_BUFFER	(1 << 1)
3273 
3274 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
3275 #define   ILK_FBCQ_DIS		(1 << 22)
3276 #define	  ILK_PABSTRETCH_DIS	(1 << 21)
3277 
3278 
3279 /*
3280  * Framebuffer compression for Sandybridge
3281  *
3282  * The following two registers are of type GTTMMADR
3283  */
3284 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
3285 #define   SNB_CPU_FENCE_ENABLE	(1 << 29)
3286 #define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
3287 
3288 /* Framebuffer compression for Ivybridge */
3289 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
3290 #define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
3291 
3292 #define IPS_CTL		_MMIO(0x43408)
3293 #define   IPS_ENABLE	(1 << 31)
3294 
3295 #define MSG_FBC_REND_STATE	_MMIO(0x50380)
3296 #define   FBC_REND_NUKE		(1 << 2)
3297 #define   FBC_REND_CACHE_CLEAN	(1 << 1)
3298 
3299 /*
3300  * GPIO regs
3301  */
3302 #define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3303 				      4 * (gpio))
3304 
3305 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
3306 # define GPIO_CLOCK_DIR_IN		(0 << 1)
3307 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
3308 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
3309 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
3310 # define GPIO_CLOCK_VAL_IN		(1 << 4)
3311 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
3312 # define GPIO_DATA_DIR_MASK		(1 << 8)
3313 # define GPIO_DATA_DIR_IN		(0 << 9)
3314 # define GPIO_DATA_DIR_OUT		(1 << 9)
3315 # define GPIO_DATA_VAL_MASK		(1 << 10)
3316 # define GPIO_DATA_VAL_OUT		(1 << 11)
3317 # define GPIO_DATA_VAL_IN		(1 << 12)
3318 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
3319 
3320 #define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3321 #define   GMBUS_AKSV_SELECT	(1 << 11)
3322 #define   GMBUS_RATE_100KHZ	(0 << 8)
3323 #define   GMBUS_RATE_50KHZ	(1 << 8)
3324 #define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */
3325 #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
3326 #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
3327 #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3328 
3329 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3330 #define   GMBUS_SW_CLR_INT	(1 << 31)
3331 #define   GMBUS_SW_RDY		(1 << 30)
3332 #define   GMBUS_ENT		(1 << 29) /* enable timeout */
3333 #define   GMBUS_CYCLE_NONE	(0 << 25)
3334 #define   GMBUS_CYCLE_WAIT	(1 << 25)
3335 #define   GMBUS_CYCLE_INDEX	(2 << 25)
3336 #define   GMBUS_CYCLE_STOP	(4 << 25)
3337 #define   GMBUS_BYTE_COUNT_SHIFT 16
3338 #define   GMBUS_BYTE_COUNT_MAX   256U
3339 #define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
3340 #define   GMBUS_SLAVE_INDEX_SHIFT 8
3341 #define   GMBUS_SLAVE_ADDR_SHIFT 1
3342 #define   GMBUS_SLAVE_READ	(1 << 0)
3343 #define   GMBUS_SLAVE_WRITE	(0 << 0)
3344 #define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3345 #define   GMBUS_INUSE		(1 << 15)
3346 #define   GMBUS_HW_WAIT_PHASE	(1 << 14)
3347 #define   GMBUS_STALL_TIMEOUT	(1 << 13)
3348 #define   GMBUS_INT		(1 << 12)
3349 #define   GMBUS_HW_RDY		(1 << 11)
3350 #define   GMBUS_SATOER		(1 << 10)
3351 #define   GMBUS_ACTIVE		(1 << 9)
3352 #define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3353 #define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3354 #define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3355 #define   GMBUS_NAK_EN		(1 << 3)
3356 #define   GMBUS_IDLE_EN		(1 << 2)
3357 #define   GMBUS_HW_WAIT_EN	(1 << 1)
3358 #define   GMBUS_HW_RDY_EN	(1 << 0)
3359 #define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3360 #define   GMBUS_2BYTE_INDEX_EN	(1 << 31)
3361 
3362 /*
3363  * Clock control & power management
3364  */
3365 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3366 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3367 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3368 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3369 
3370 #define VGA0	_MMIO(0x6000)
3371 #define VGA1	_MMIO(0x6004)
3372 #define VGA_PD	_MMIO(0x6010)
3373 #define   VGA0_PD_P2_DIV_4	(1 << 7)
3374 #define   VGA0_PD_P1_DIV_2	(1 << 5)
3375 #define   VGA0_PD_P1_SHIFT	0
3376 #define   VGA0_PD_P1_MASK	(0x1f << 0)
3377 #define   VGA1_PD_P2_DIV_4	(1 << 15)
3378 #define   VGA1_PD_P1_DIV_2	(1 << 13)
3379 #define   VGA1_PD_P1_SHIFT	8
3380 #define   VGA1_PD_P1_MASK	(0x1f << 8)
3381 #define   DPLL_VCO_ENABLE		(1 << 31)
3382 #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
3383 #define   DPLL_DVO_2X_MODE		(1 << 30)
3384 #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
3385 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
3386 #define   DPLL_REF_CLK_ENABLE_VLV	(1 << 29)
3387 #define   DPLL_VGA_MODE_DIS		(1 << 28)
3388 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
3389 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
3390 #define   DPLL_MODE_MASK		(3 << 26)
3391 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3392 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3393 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
3394 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
3395 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
3396 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
3397 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3398 #define   DPLL_LOCK_VLV			(1 << 15)
3399 #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1 << 14)
3400 #define   DPLL_INTEGRATED_REF_CLK_VLV	(1 << 13)
3401 #define   DPLL_SSC_REF_CLK_CHV		(1 << 13)
3402 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
3403 #define   DPLL_PORTB_READY_MASK		(0xf)
3404 
3405 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
3406 
3407 /* Additional CHV pll/phy registers */
3408 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
3409 #define   DPLL_PORTD_READY_MASK		(0xf)
3410 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3411 #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)	(1 << (2 * (phy) + (ch) + 27))
3412 #define   PHY_LDO_DELAY_0NS			0x0
3413 #define   PHY_LDO_DELAY_200NS			0x1
3414 #define   PHY_LDO_DELAY_600NS			0x2
3415 #define   PHY_LDO_SEQ_DELAY(delay, phy)		((delay) << (2 * (phy) + 23))
3416 #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch)	((mask) << (8 * (phy) + 4 * (ch) + 11))
3417 #define   PHY_CH_SU_PSR				0x1
3418 #define   PHY_CH_DEEP_PSR			0x7
3419 #define   PHY_CH_POWER_MODE(mode, phy, ch)	((mode) << (6 * (phy) + 3 * (ch) + 2))
3420 #define   PHY_COM_LANE_RESET_DEASSERT(phy)	(1 << (phy))
3421 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3422 #define   PHY_POWERGOOD(phy)	(((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3423 #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
3424 #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3425 
3426 /*
3427  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3428  * this field (only one bit may be set).
3429  */
3430 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
3431 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
3432 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3433 /* i830, required in DVO non-gang */
3434 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
3435 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
3436 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
3437 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
3438 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
3439 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3440 #define   PLL_REF_INPUT_MASK		(3 << 13)
3441 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
3442 /* Ironlake */
3443 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
3444 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
3445 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x) - 1) << 9)
3446 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3447 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3448 
3449 /*
3450  * Parallel to Serial Load Pulse phase selection.
3451  * Selects the phase for the 10X DPLL clock for the PCIe
3452  * digital display port. The range is 4 to 13; 10 or more
3453  * is just a flip delay. The default is 6
3454  */
3455 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3456 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
3457 /*
3458  * SDVO multiplier for 945G/GM. Not used on 965.
3459  */
3460 #define   SDVO_MULTIPLIER_MASK			0x000000ff
3461 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
3462 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
3463 
3464 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3465 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3466 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3467 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3468 
3469 /*
3470  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3471  *
3472  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
3473  */
3474 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
3475 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
3476 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3477 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
3478 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
3479 /*
3480  * SDVO/UDI pixel multiplier.
3481  *
3482  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3483  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
3484  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3485  * dummy bytes in the datastream at an increased clock rate, with both sides of
3486  * the link knowing how many bytes are fill.
3487  *
3488  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3489  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
3490  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3491  * through an SDVO command.
3492  *
3493  * This register field has values of multiplication factor minus 1, with
3494  * a maximum multiplier of 5 for SDVO.
3495  */
3496 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
3497 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
3498 /*
3499  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3500  * This best be set to the default value (3) or the CRT won't work. No,
3501  * I don't entirely understand what this does...
3502  */
3503 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
3504 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3505 
3506 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
3507 
3508 #define _FPA0	0x6040
3509 #define _FPA1	0x6044
3510 #define _FPB0	0x6048
3511 #define _FPB1	0x604c
3512 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3513 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3514 #define   FP_N_DIV_MASK		0x003f0000
3515 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
3516 #define   FP_N_DIV_SHIFT		16
3517 #define   FP_M1_DIV_MASK	0x00003f00
3518 #define   FP_M1_DIV_SHIFT		 8
3519 #define   FP_M2_DIV_MASK	0x0000003f
3520 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
3521 #define   FP_M2_DIV_SHIFT		 0
3522 #define DPLL_TEST	_MMIO(0x606c)
3523 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
3524 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
3525 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
3526 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
3527 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
3528 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
3529 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
3530 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
3531 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
3532 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
3533 #define D_STATE		_MMIO(0x6104)
3534 #define  DSTATE_GFX_RESET_I830			(1 << 6)
3535 #define  DSTATE_PLL_D3_OFF			(1 << 3)
3536 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
3537 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
3538 #define DSPCLK_GATE_D	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3539 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
3540 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
3541 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
3542 # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
3543 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
3544 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
3545 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
3546 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
3547 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
3548 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
3549 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
3550 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
3551 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
3552 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
3553 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
3554 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
3555 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
3556 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
3557 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
3558 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
3559 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3560 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
3561 # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
3562 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
3563 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
3564 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
3565 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
3566 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
3567 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
3568 /*
3569  * This bit must be set on the 830 to prevent hangs when turning off the
3570  * overlay scaler.
3571  */
3572 # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
3573 # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
3574 # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3575 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
3576 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
3577 
3578 #define RENCLK_GATE_D1		_MMIO(0x6204)
3579 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
3580 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
3581 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
3582 # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
3583 # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
3584 # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
3585 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
3586 # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
3587 # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
3588 /* This bit must be unset on 855,865 */
3589 # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
3590 # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
3591 # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
3592 # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
3593 /* This bit must be set on 855,865. */
3594 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
3595 # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
3596 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
3597 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
3598 # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
3599 # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
3600 # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
3601 # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
3602 # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
3603 # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
3604 # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
3605 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
3606 # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
3607 # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
3608 # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
3609 # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
3610 # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
3611 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
3612 
3613 # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
3614 /* This bit must always be set on 965G/965GM */
3615 # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
3616 # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
3617 # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
3618 # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
3619 # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
3620 # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
3621 /* This bit must always be set on 965G */
3622 # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
3623 # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
3624 # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
3625 # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
3626 # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
3627 # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
3628 # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
3629 # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
3630 # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
3631 # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
3632 # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
3633 # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
3634 # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
3635 # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
3636 # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
3637 # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
3638 # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
3639 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
3640 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
3641 
3642 #define RENCLK_GATE_D2		_MMIO(0x6208)
3643 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
3644 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
3645 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
3646 
3647 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
3648 #define  VCP_UNIT_CLOCK_GATE_DISABLE		(1 << 4)
3649 
3650 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
3651 #define DEUC			_MMIO(0x6214)          /* CRL only */
3652 
3653 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
3654 #define  FW_CSPWRDWNEN		(1 << 15)
3655 
3656 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
3657 
3658 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
3659 #define   CDCLK_FREQ_SHIFT	4
3660 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
3661 #define   CZCLK_FREQ_MASK	0xf
3662 
3663 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
3664 #define   PFI_CREDIT_63		(9 << 28)		/* chv only */
3665 #define   PFI_CREDIT_31		(8 << 28)		/* chv only */
3666 #define   PFI_CREDIT(x)		(((x) - 8) << 28)	/* 8-15 */
3667 #define   PFI_CREDIT_RESEND	(1 << 27)
3668 #define   VGA_FAST_MODE_DISABLE	(1 << 14)
3669 
3670 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
3671 
3672 /*
3673  * Palette regs
3674  */
3675 #define _PALETTE_A		0xa000
3676 #define _PALETTE_B		0xa800
3677 #define _CHV_PALETTE_C		0xc000
3678 #define PALETTE_RED_MASK        REG_GENMASK(23, 16)
3679 #define PALETTE_GREEN_MASK      REG_GENMASK(15, 8)
3680 #define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
3681 #define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3682 				      _PICK((pipe), _PALETTE_A,		\
3683 					    _PALETTE_B, _CHV_PALETTE_C) + \
3684 				      (i) * 4)
3685 
3686 /* MCH MMIO space */
3687 
3688 /*
3689  * MCHBAR mirror.
3690  *
3691  * This mirrors the MCHBAR MMIO space whose location is determined by
3692  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3693  * every way.  It is not accessible from the CP register read instructions.
3694  *
3695  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3696  * just read.
3697  */
3698 #define MCHBAR_MIRROR_BASE	0x10000
3699 
3700 #define MCHBAR_MIRROR_BASE_SNB	0x140000
3701 
3702 #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
3703 #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
3704 #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
3705 #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
3706 #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
3707 
3708 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3709 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3710 
3711 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3712 #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
3713 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
3714 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
3715 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
3716 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
3717 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
3718 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
3719 #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
3720 #define DCC2_MODIFIED_ENHANCED_DISABLE			(1 << 20)
3721 
3722 /* Pineview MCH register contains DDR3 setting */
3723 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3724 #define CSHRDDR3CTL_DDR3       (1 << 2)
3725 
3726 /* 965 MCH register controlling DRAM channel configuration */
3727 #define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
3728 #define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
3729 
3730 /* snb MCH registers for reading the DRAM channel configuration */
3731 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3732 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3733 #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3734 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
3735 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
3736 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
3737 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
3738 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
3739 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
3740 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
3741 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
3742 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
3743 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
3744 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
3745 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
3746 /* DIMM sizes are in multiples of 256mb. */
3747 #define   MAD_DIMM_B_SIZE_SHIFT		8
3748 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
3749 #define   MAD_DIMM_A_SIZE_SHIFT		0
3750 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
3751 
3752 /* snb MCH registers for priority tuning */
3753 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3754 #define   MCH_SSKPD_WM0_MASK		0x3f
3755 #define   MCH_SSKPD_WM0_VAL		0xc
3756 
3757 /* Clocking configuration register */
3758 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3759 #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
3760 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
3761 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
3762 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
3763 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
3764 #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
3765 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
3766 /*
3767  * Note that on at least on ELK the below value is reported for both
3768  * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3769  * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3770  */
3771 #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
3772 #define CLKCFG_FSB_MASK					(7 << 0)
3773 #define CLKCFG_MEM_533					(1 << 4)
3774 #define CLKCFG_MEM_667					(2 << 4)
3775 #define CLKCFG_MEM_800					(3 << 4)
3776 #define CLKCFG_MEM_MASK					(7 << 4)
3777 
3778 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3779 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3780 
3781 #define TSC1			_MMIO(0x11001)
3782 #define   TSE			(1 << 0)
3783 #define TR1			_MMIO(0x11006)
3784 #define TSFS			_MMIO(0x11020)
3785 #define   TSFS_SLOPE_MASK	0x0000ff00
3786 #define   TSFS_SLOPE_SHIFT	8
3787 #define   TSFS_INTR_MASK	0x000000ff
3788 
3789 #define CRSTANDVID		_MMIO(0x11100)
3790 #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3791 #define   PXVFREQ_PX_MASK	0x7f000000
3792 #define   PXVFREQ_PX_SHIFT	24
3793 #define VIDFREQ_BASE		_MMIO(0x11110)
3794 #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3795 #define VIDFREQ2		_MMIO(0x11114)
3796 #define VIDFREQ3		_MMIO(0x11118)
3797 #define VIDFREQ4		_MMIO(0x1111c)
3798 #define   VIDFREQ_P0_MASK	0x1f000000
3799 #define   VIDFREQ_P0_SHIFT	24
3800 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
3801 #define   VIDFREQ_P0_CSCLK_SHIFT 20
3802 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
3803 #define   VIDFREQ_P0_CRCLK_SHIFT 16
3804 #define   VIDFREQ_P1_MASK	0x00001f00
3805 #define   VIDFREQ_P1_SHIFT	8
3806 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
3807 #define   VIDFREQ_P1_CSCLK_SHIFT 4
3808 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
3809 #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
3810 #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3811 #define   INTTOEXT_MAP3_SHIFT	24
3812 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
3813 #define   INTTOEXT_MAP2_SHIFT	16
3814 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
3815 #define   INTTOEXT_MAP1_SHIFT	8
3816 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
3817 #define   INTTOEXT_MAP0_SHIFT	0
3818 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
3819 #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
3820 #define   MEMCTL_CMD_MASK	0xe000
3821 #define   MEMCTL_CMD_SHIFT	13
3822 #define   MEMCTL_CMD_RCLK_OFF	0
3823 #define   MEMCTL_CMD_RCLK_ON	1
3824 #define   MEMCTL_CMD_CHFREQ	2
3825 #define   MEMCTL_CMD_CHVID	3
3826 #define   MEMCTL_CMD_VMMOFF	4
3827 #define   MEMCTL_CMD_VMMON	5
3828 #define   MEMCTL_CMD_STS	(1 << 12) /* write 1 triggers command, clears
3829 					   when command complete */
3830 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
3831 #define   MEMCTL_FREQ_SHIFT	8
3832 #define   MEMCTL_SFCAVM		(1 << 7)
3833 #define   MEMCTL_TGT_VID_MASK	0x007f
3834 #define MEMIHYST		_MMIO(0x1117c)
3835 #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
3836 #define   MEMINT_RSEXIT_EN	(1 << 8)
3837 #define   MEMINT_CX_SUPR_EN	(1 << 7)
3838 #define   MEMINT_CONT_BUSY_EN	(1 << 6)
3839 #define   MEMINT_AVG_BUSY_EN	(1 << 5)
3840 #define   MEMINT_EVAL_CHG_EN	(1 << 4)
3841 #define   MEMINT_MON_IDLE_EN	(1 << 3)
3842 #define   MEMINT_UP_EVAL_EN	(1 << 2)
3843 #define   MEMINT_DOWN_EVAL_EN	(1 << 1)
3844 #define   MEMINT_SW_CMD_EN	(1 << 0)
3845 #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
3846 #define   MEM_RSEXIT_MASK	0xc000
3847 #define   MEM_RSEXIT_SHIFT	14
3848 #define   MEM_CONT_BUSY_MASK	0x3000
3849 #define   MEM_CONT_BUSY_SHIFT	12
3850 #define   MEM_AVG_BUSY_MASK	0x0c00
3851 #define   MEM_AVG_BUSY_SHIFT	10
3852 #define   MEM_EVAL_CHG_MASK	0x0300
3853 #define   MEM_EVAL_BUSY_SHIFT	8
3854 #define   MEM_MON_IDLE_MASK	0x00c0
3855 #define   MEM_MON_IDLE_SHIFT	6
3856 #define   MEM_UP_EVAL_MASK	0x0030
3857 #define   MEM_UP_EVAL_SHIFT	4
3858 #define   MEM_DOWN_EVAL_MASK	0x000c
3859 #define   MEM_DOWN_EVAL_SHIFT	2
3860 #define   MEM_SW_CMD_MASK	0x0003
3861 #define   MEM_INT_STEER_GFX	0
3862 #define   MEM_INT_STEER_CMR	1
3863 #define   MEM_INT_STEER_SMI	2
3864 #define   MEM_INT_STEER_SCI	3
3865 #define MEMINTRSTS		_MMIO(0x11184)
3866 #define   MEMINT_RSEXIT		(1 << 7)
3867 #define   MEMINT_CONT_BUSY	(1 << 6)
3868 #define   MEMINT_AVG_BUSY	(1 << 5)
3869 #define   MEMINT_EVAL_CHG	(1 << 4)
3870 #define   MEMINT_MON_IDLE	(1 << 3)
3871 #define   MEMINT_UP_EVAL	(1 << 2)
3872 #define   MEMINT_DOWN_EVAL	(1 << 1)
3873 #define   MEMINT_SW_CMD		(1 << 0)
3874 #define MEMMODECTL		_MMIO(0x11190)
3875 #define   MEMMODE_BOOST_EN	(1 << 31)
3876 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3877 #define   MEMMODE_BOOST_FREQ_SHIFT 24
3878 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3879 #define   MEMMODE_IDLE_MODE_SHIFT 16
3880 #define   MEMMODE_IDLE_MODE_EVAL 0
3881 #define   MEMMODE_IDLE_MODE_CONT 1
3882 #define   MEMMODE_HWIDLE_EN	(1 << 15)
3883 #define   MEMMODE_SWMODE_EN	(1 << 14)
3884 #define   MEMMODE_RCLK_GATE	(1 << 13)
3885 #define   MEMMODE_HW_UPDATE	(1 << 12)
3886 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
3887 #define   MEMMODE_FSTART_SHIFT	8
3888 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
3889 #define   MEMMODE_FMAX_SHIFT	4
3890 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
3891 #define RCBMAXAVG		_MMIO(0x1119c)
3892 #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
3893 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
3894 #define   SWMEMCMD_RENDER_ON	(1 << 13)
3895 #define   SWMEMCMD_SWFREQ	(2 << 13)
3896 #define   SWMEMCMD_TARVID	(3 << 13)
3897 #define   SWMEMCMD_VRM_OFF	(4 << 13)
3898 #define   SWMEMCMD_VRM_ON	(5 << 13)
3899 #define   CMDSTS		(1 << 12)
3900 #define   SFCAVM		(1 << 11)
3901 #define   SWFREQ_MASK		0x0380 /* P0-7 */
3902 #define   SWFREQ_SHIFT		7
3903 #define   TARVID_MASK		0x001f
3904 #define MEMSTAT_CTG		_MMIO(0x111a0)
3905 #define RCBMINAVG		_MMIO(0x111a0)
3906 #define RCUPEI			_MMIO(0x111b0)
3907 #define RCDNEI			_MMIO(0x111b4)
3908 #define RSTDBYCTL		_MMIO(0x111b8)
3909 #define   RS1EN			(1 << 31)
3910 #define   RS2EN			(1 << 30)
3911 #define   RS3EN			(1 << 29)
3912 #define   D3RS3EN		(1 << 28) /* Display D3 imlies RS3 */
3913 #define   SWPROMORSX		(1 << 27) /* RSx promotion timers ignored */
3914 #define   RCWAKERW		(1 << 26) /* Resetwarn from PCH causes wakeup */
3915 #define   DPRSLPVREN		(1 << 25) /* Fast voltage ramp enable */
3916 #define   GFXTGHYST		(1 << 24) /* Hysteresis to allow trunk gating */
3917 #define   RCX_SW_EXIT		(1 << 23) /* Leave RSx and prevent re-entry */
3918 #define   RSX_STATUS_MASK	(7 << 20)
3919 #define   RSX_STATUS_ON		(0 << 20)
3920 #define   RSX_STATUS_RC1	(1 << 20)
3921 #define   RSX_STATUS_RC1E	(2 << 20)
3922 #define   RSX_STATUS_RS1	(3 << 20)
3923 #define   RSX_STATUS_RS2	(4 << 20) /* aka rc6 */
3924 #define   RSX_STATUS_RSVD	(5 << 20) /* deep rc6 unsupported on ilk */
3925 #define   RSX_STATUS_RS3	(6 << 20) /* rs3 unsupported on ilk */
3926 #define   RSX_STATUS_RSVD2	(7 << 20)
3927 #define   UWRCRSXE		(1 << 19) /* wake counter limit prevents rsx */
3928 #define   RSCRP			(1 << 18) /* rs requests control on rs1/2 reqs */
3929 #define   JRSC			(1 << 17) /* rsx coupled to cpu c-state */
3930 #define   RS2INC0		(1 << 16) /* allow rs2 in cpu c0 */
3931 #define   RS1CONTSAV_MASK	(3 << 14)
3932 #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
3933 #define   RS1CONTSAV_RSVD	(1 << 14)
3934 #define   RS1CONTSAV_SAVE_RS1	(2 << 14) /* rs1 saves context */
3935 #define   RS1CONTSAV_FULL_RS1	(3 << 14) /* rs1 saves and restores context */
3936 #define   NORMSLEXLAT_MASK	(3 << 12)
3937 #define   SLOW_RS123		(0 << 12)
3938 #define   SLOW_RS23		(1 << 12)
3939 #define   SLOW_RS3		(2 << 12)
3940 #define   NORMAL_RS123		(3 << 12)
3941 #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
3942 #define   IMPROMOEN		(1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3943 #define   RCENTSYNC		(1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3944 #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
3945 #define   RS_CSTATE_MASK	(3 << 4)
3946 #define   RS_CSTATE_C367_RS1	(0 << 4)
3947 #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3948 #define   RS_CSTATE_RSVD	(2 << 4)
3949 #define   RS_CSTATE_C367_RS2	(3 << 4)
3950 #define   REDSAVES		(1 << 3) /* no context save if was idle during rs0 */
3951 #define   REDRESTORES		(1 << 2) /* no restore if was idle during rs0 */
3952 #define VIDCTL			_MMIO(0x111c0)
3953 #define VIDSTS			_MMIO(0x111c8)
3954 #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
3955 #define MEMSTAT_ILK		_MMIO(0x111f8)
3956 #define   MEMSTAT_VID_MASK	0x7f00
3957 #define   MEMSTAT_VID_SHIFT	8
3958 #define   MEMSTAT_PSTATE_MASK	0x00f8
3959 #define   MEMSTAT_PSTATE_SHIFT  3
3960 #define   MEMSTAT_MON_ACTV	(1 << 2)
3961 #define   MEMSTAT_SRC_CTL_MASK	0x0003
3962 #define   MEMSTAT_SRC_CTL_CORE	0
3963 #define   MEMSTAT_SRC_CTL_TRB	1
3964 #define   MEMSTAT_SRC_CTL_THM	2
3965 #define   MEMSTAT_SRC_CTL_STDBY 3
3966 #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
3967 #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
3968 #define PMMISC			_MMIO(0x11214)
3969 #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
3970 #define SDEW			_MMIO(0x1124c)
3971 #define CSIEW0			_MMIO(0x11250)
3972 #define CSIEW1			_MMIO(0x11254)
3973 #define CSIEW2			_MMIO(0x11258)
3974 #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
3975 #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
3976 #define MCHAFE			_MMIO(0x112c0)
3977 #define CSIEC			_MMIO(0x112e0)
3978 #define DMIEC			_MMIO(0x112e4)
3979 #define DDREC			_MMIO(0x112e8)
3980 #define PEG0EC			_MMIO(0x112ec)
3981 #define PEG1EC			_MMIO(0x112f0)
3982 #define GFXEC			_MMIO(0x112f4)
3983 #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
3984 #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
3985 #define ECR			_MMIO(0x11600)
3986 #define   ECR_GPFE		(1 << 31)
3987 #define   ECR_IMONE		(1 << 30)
3988 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
3989 #define OGW0			_MMIO(0x11608)
3990 #define OGW1			_MMIO(0x1160c)
3991 #define EG0			_MMIO(0x11610)
3992 #define EG1			_MMIO(0x11614)
3993 #define EG2			_MMIO(0x11618)
3994 #define EG3			_MMIO(0x1161c)
3995 #define EG4			_MMIO(0x11620)
3996 #define EG5			_MMIO(0x11624)
3997 #define EG6			_MMIO(0x11628)
3998 #define EG7			_MMIO(0x1162c)
3999 #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
4000 #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
4001 #define LCFUSE02		_MMIO(0x116c0)
4002 #define   LCFUSE_HIV_MASK	0x000000ff
4003 #define CSIPLL0			_MMIO(0x12c10)
4004 #define DDRMPLL1		_MMIO(0X12c20)
4005 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
4006 
4007 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4008 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4009 
4010 #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4011 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4012 #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4013 #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4014 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
4015 
4016 /*
4017  * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
4018  * 8300) freezing up around GPU hangs. Looks as if even
4019  * scheduling/timer interrupts start misbehaving if the RPS
4020  * EI/thresholds are "bad", leading to a very sluggish or even
4021  * frozen machine.
4022  */
4023 #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
4024 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
4025 #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
4026 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
4027 				(IS_GEN9_LP(dev_priv) ? \
4028 				INTERVAL_0_833_US(us) : \
4029 				INTERVAL_1_33_US(us)) : \
4030 				INTERVAL_1_28_US(us))
4031 
4032 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
4033 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
4034 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
4035 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
4036                            (IS_GEN9_LP(dev_priv) ? \
4037                            INTERVAL_0_833_TO_US(interval) : \
4038                            INTERVAL_1_33_TO_US(interval)) : \
4039                            INTERVAL_1_28_TO_US(interval))
4040 
4041 /*
4042  * Logical Context regs
4043  */
4044 #define CCID(base)			_MMIO((base) + 0x180)
4045 #define   CCID_EN			BIT(0)
4046 #define   CCID_EXTENDED_STATE_RESTORE	BIT(2)
4047 #define   CCID_EXTENDED_STATE_SAVE	BIT(3)
4048 /*
4049  * Notes on SNB/IVB/VLV context size:
4050  * - Power context is saved elsewhere (LLC or stolen)
4051  * - Ring/execlist context is saved on SNB, not on IVB
4052  * - Extended context size already includes render context size
4053  * - We always need to follow the extended context size.
4054  *   SNB BSpec has comments indicating that we should use the
4055  *   render context size instead if execlists are disabled, but
4056  *   based on empirical testing that's just nonsense.
4057  * - Pipelined/VF state is saved on SNB/IVB respectively
4058  * - GT1 size just indicates how much of render context
4059  *   doesn't need saving on GT1
4060  */
4061 #define CXT_SIZE		_MMIO(0x21a0)
4062 #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
4063 #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
4064 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
4065 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
4066 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
4067 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_RING_SIZE(cxt_reg) + \
4068 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4069 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4070 #define GEN7_CXT_SIZE		_MMIO(0x21a8)
4071 #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
4072 #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
4073 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
4074 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
4075 #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
4076 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
4077 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4078 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4079 
4080 enum {
4081 	INTEL_ADVANCED_CONTEXT = 0,
4082 	INTEL_LEGACY_32B_CONTEXT,
4083 	INTEL_ADVANCED_AD_CONTEXT,
4084 	INTEL_LEGACY_64B_CONTEXT
4085 };
4086 
4087 enum {
4088 	FAULT_AND_HANG = 0,
4089 	FAULT_AND_HALT, /* Debug only */
4090 	FAULT_AND_STREAM,
4091 	FAULT_AND_CONTINUE /* Unsupported */
4092 };
4093 
4094 #define GEN8_CTX_VALID (1 << 0)
4095 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4096 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
4097 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4098 #define GEN8_CTX_PRIVILEGE (1 << 8)
4099 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4100 
4101 #define GEN8_CTX_ID_SHIFT 32
4102 #define GEN8_CTX_ID_WIDTH 21
4103 #define GEN11_SW_CTX_ID_SHIFT 37
4104 #define GEN11_SW_CTX_ID_WIDTH 11
4105 #define GEN11_ENGINE_CLASS_SHIFT 61
4106 #define GEN11_ENGINE_CLASS_WIDTH 3
4107 #define GEN11_ENGINE_INSTANCE_SHIFT 48
4108 #define GEN11_ENGINE_INSTANCE_WIDTH 6
4109 
4110 #define CHV_CLK_CTL1			_MMIO(0x101100)
4111 #define VLV_CLK_CTL2			_MMIO(0x101104)
4112 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
4113 
4114 /*
4115  * Overlay regs
4116  */
4117 
4118 #define OVADD			_MMIO(0x30000)
4119 #define DOVSTA			_MMIO(0x30008)
4120 #define OC_BUF			(0x3 << 20)
4121 #define OGAMC5			_MMIO(0x30010)
4122 #define OGAMC4			_MMIO(0x30014)
4123 #define OGAMC3			_MMIO(0x30018)
4124 #define OGAMC2			_MMIO(0x3001c)
4125 #define OGAMC1			_MMIO(0x30020)
4126 #define OGAMC0			_MMIO(0x30024)
4127 
4128 /*
4129  * GEN9 clock gating regs
4130  */
4131 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
4132 #define   DARBF_GATING_DIS		(1 << 27)
4133 #define   PWM2_GATING_DIS		(1 << 14)
4134 #define   PWM1_GATING_DIS		(1 << 13)
4135 
4136 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
4137 #define   TGL_VRH_GATING_DIS		REG_BIT(31)
4138 
4139 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
4140 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
4141 
4142 #define _CLKGATE_DIS_PSL_A		0x46520
4143 #define _CLKGATE_DIS_PSL_B		0x46524
4144 #define _CLKGATE_DIS_PSL_C		0x46528
4145 #define   DUPS1_GATING_DIS		(1 << 15)
4146 #define   DUPS2_GATING_DIS		(1 << 19)
4147 #define   DUPS3_GATING_DIS		(1 << 23)
4148 #define   DPF_GATING_DIS		(1 << 10)
4149 #define   DPF_RAM_GATING_DIS		(1 << 9)
4150 #define   DPFR_GATING_DIS		(1 << 8)
4151 
4152 #define CLKGATE_DIS_PSL(pipe) \
4153 	_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4154 
4155 /*
4156  * GEN10 clock gating regs
4157  */
4158 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
4159 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
4160 #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
4161 #define  MSCUNIT_CLKGATE_DIS		(1 << 10)
4162 #define  L3_CLKGATE_DIS			REG_BIT(16)
4163 #define  L3_CR2X_CLKGATE_DIS		REG_BIT(17)
4164 
4165 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
4166 #define  GWUNIT_CLKGATE_DIS		(1 << 16)
4167 
4168 #define SUBSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x9528)
4169 #define  CPSSUNIT_CLKGATE_DIS		REG_BIT(9)
4170 
4171 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
4172 #define   VFUNIT_CLKGATE_DIS		REG_BIT(20)
4173 #define   HSUNIT_CLKGATE_DIS		REG_BIT(8)
4174 #define   VSUNIT_CLKGATE_DIS		REG_BIT(3)
4175 
4176 #define UNSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x94e4)
4177 #define   VSUNIT_CLKGATE_DIS_TGL	REG_BIT(19)
4178 #define   PSDUNIT_CLKGATE_DIS		REG_BIT(5)
4179 
4180 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
4181 #define   CGPSF_CLKGATE_DIS		(1 << 3)
4182 
4183 /*
4184  * Display engine regs
4185  */
4186 
4187 /* Pipe A CRC regs */
4188 #define _PIPE_CRC_CTL_A			0x60050
4189 #define   PIPE_CRC_ENABLE		(1 << 31)
4190 /* skl+ source selection */
4191 #define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
4192 #define   PIPE_CRC_SOURCE_PLANE_2_SKL	(2 << 28)
4193 #define   PIPE_CRC_SOURCE_DMUX_SKL	(4 << 28)
4194 #define   PIPE_CRC_SOURCE_PLANE_3_SKL	(6 << 28)
4195 #define   PIPE_CRC_SOURCE_PLANE_4_SKL	(7 << 28)
4196 #define   PIPE_CRC_SOURCE_PLANE_5_SKL	(5 << 28)
4197 #define   PIPE_CRC_SOURCE_PLANE_6_SKL	(3 << 28)
4198 #define   PIPE_CRC_SOURCE_PLANE_7_SKL	(1 << 28)
4199 /* ivb+ source selection */
4200 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
4201 #define   PIPE_CRC_SOURCE_SPRITE_IVB	(1 << 29)
4202 #define   PIPE_CRC_SOURCE_PF_IVB	(2 << 29)
4203 /* ilk+ source selection */
4204 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
4205 #define   PIPE_CRC_SOURCE_SPRITE_ILK	(1 << 28)
4206 #define   PIPE_CRC_SOURCE_PIPE_ILK	(2 << 28)
4207 /* embedded DP port on the north display block, reserved on ivb */
4208 #define   PIPE_CRC_SOURCE_PORT_A_ILK	(4 << 28)
4209 #define   PIPE_CRC_SOURCE_FDI_ILK	(5 << 28) /* reserved on ivb */
4210 /* vlv source selection */
4211 #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
4212 #define   PIPE_CRC_SOURCE_HDMIB_VLV	(1 << 27)
4213 #define   PIPE_CRC_SOURCE_HDMIC_VLV	(2 << 27)
4214 /* with DP port the pipe source is invalid */
4215 #define   PIPE_CRC_SOURCE_DP_D_VLV	(3 << 27)
4216 #define   PIPE_CRC_SOURCE_DP_B_VLV	(6 << 27)
4217 #define   PIPE_CRC_SOURCE_DP_C_VLV	(7 << 27)
4218 /* gen3+ source selection */
4219 #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
4220 #define   PIPE_CRC_SOURCE_SDVOB_I9XX	(1 << 28)
4221 #define   PIPE_CRC_SOURCE_SDVOC_I9XX	(2 << 28)
4222 /* with DP/TV port the pipe source is invalid */
4223 #define   PIPE_CRC_SOURCE_DP_D_G4X	(3 << 28)
4224 #define   PIPE_CRC_SOURCE_TV_PRE	(4 << 28)
4225 #define   PIPE_CRC_SOURCE_TV_POST	(5 << 28)
4226 #define   PIPE_CRC_SOURCE_DP_B_G4X	(6 << 28)
4227 #define   PIPE_CRC_SOURCE_DP_C_G4X	(7 << 28)
4228 /* gen2 doesn't have source selection bits */
4229 #define   PIPE_CRC_INCLUDE_BORDER_I8XX	(1 << 30)
4230 
4231 #define _PIPE_CRC_RES_1_A_IVB		0x60064
4232 #define _PIPE_CRC_RES_2_A_IVB		0x60068
4233 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
4234 #define _PIPE_CRC_RES_4_A_IVB		0x60070
4235 #define _PIPE_CRC_RES_5_A_IVB		0x60074
4236 
4237 #define _PIPE_CRC_RES_RED_A		0x60060
4238 #define _PIPE_CRC_RES_GREEN_A		0x60064
4239 #define _PIPE_CRC_RES_BLUE_A		0x60068
4240 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
4241 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
4242 
4243 /* Pipe B CRC regs */
4244 #define _PIPE_CRC_RES_1_B_IVB		0x61064
4245 #define _PIPE_CRC_RES_2_B_IVB		0x61068
4246 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
4247 #define _PIPE_CRC_RES_4_B_IVB		0x61070
4248 #define _PIPE_CRC_RES_5_B_IVB		0x61074
4249 
4250 #define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4251 #define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4252 #define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4253 #define PIPE_CRC_RES_3_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4254 #define PIPE_CRC_RES_4_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4255 #define PIPE_CRC_RES_5_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4256 
4257 #define PIPE_CRC_RES_RED(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4258 #define PIPE_CRC_RES_GREEN(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4259 #define PIPE_CRC_RES_BLUE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4260 #define PIPE_CRC_RES_RES1_I915(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4261 #define PIPE_CRC_RES_RES2_G4X(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4262 
4263 /* Pipe A timing regs */
4264 #define _HTOTAL_A	0x60000
4265 #define _HBLANK_A	0x60004
4266 #define _HSYNC_A	0x60008
4267 #define _VTOTAL_A	0x6000c
4268 #define _VBLANK_A	0x60010
4269 #define _VSYNC_A	0x60014
4270 #define _EXITLINE_A	0x60018
4271 #define _PIPEASRC	0x6001c
4272 #define _BCLRPAT_A	0x60020
4273 #define _VSYNCSHIFT_A	0x60028
4274 #define _PIPE_MULT_A	0x6002c
4275 
4276 /* Pipe B timing regs */
4277 #define _HTOTAL_B	0x61000
4278 #define _HBLANK_B	0x61004
4279 #define _HSYNC_B	0x61008
4280 #define _VTOTAL_B	0x6100c
4281 #define _VBLANK_B	0x61010
4282 #define _VSYNC_B	0x61014
4283 #define _PIPEBSRC	0x6101c
4284 #define _BCLRPAT_B	0x61020
4285 #define _VSYNCSHIFT_B	0x61028
4286 #define _PIPE_MULT_B	0x6102c
4287 
4288 /* DSI 0 timing regs */
4289 #define _HTOTAL_DSI0		0x6b000
4290 #define _HSYNC_DSI0		0x6b008
4291 #define _VTOTAL_DSI0		0x6b00c
4292 #define _VSYNC_DSI0		0x6b014
4293 #define _VSYNCSHIFT_DSI0	0x6b028
4294 
4295 /* DSI 1 timing regs */
4296 #define _HTOTAL_DSI1		0x6b800
4297 #define _HSYNC_DSI1		0x6b808
4298 #define _VTOTAL_DSI1		0x6b80c
4299 #define _VSYNC_DSI1		0x6b814
4300 #define _VSYNCSHIFT_DSI1	0x6b828
4301 
4302 #define TRANSCODER_A_OFFSET 0x60000
4303 #define TRANSCODER_B_OFFSET 0x61000
4304 #define TRANSCODER_C_OFFSET 0x62000
4305 #define CHV_TRANSCODER_C_OFFSET 0x63000
4306 #define TRANSCODER_D_OFFSET 0x63000
4307 #define TRANSCODER_EDP_OFFSET 0x6f000
4308 #define TRANSCODER_DSI0_OFFSET	0x6b000
4309 #define TRANSCODER_DSI1_OFFSET	0x6b800
4310 
4311 #define HTOTAL(trans)		_MMIO_TRANS2(trans, _HTOTAL_A)
4312 #define HBLANK(trans)		_MMIO_TRANS2(trans, _HBLANK_A)
4313 #define HSYNC(trans)		_MMIO_TRANS2(trans, _HSYNC_A)
4314 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
4315 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
4316 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
4317 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
4318 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4319 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
4320 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
4321 
4322 #define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
4323 #define   EXITLINE_ENABLE	REG_BIT(31)
4324 #define   EXITLINE_MASK		REG_GENMASK(12, 0)
4325 #define   EXITLINE_SHIFT	0
4326 
4327 /*
4328  * HSW+ eDP PSR registers
4329  *
4330  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4331  * instance of it
4332  */
4333 #define _HSW_EDP_PSR_BASE			0x64800
4334 #define _SRD_CTL_A				0x60800
4335 #define _SRD_CTL_EDP				0x6f800
4336 #define _PSR_ADJ(tran, reg)			(_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4337 #define EDP_PSR_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
4338 #define   EDP_PSR_ENABLE			(1 << 31)
4339 #define   BDW_PSR_SINGLE_FRAME			(1 << 30)
4340 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1 << 29) /* SW can't modify */
4341 #define   EDP_PSR_LINK_STANDBY			(1 << 27)
4342 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK	(3 << 25)
4343 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
4344 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES	(1 << 25)
4345 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES	(2 << 25)
4346 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES	(3 << 25)
4347 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT		20
4348 #define   EDP_PSR_SKIP_AUX_EXIT			(1 << 12)
4349 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
4350 #define   EDP_PSR_TP1_TP3_SEL			(1 << 11)
4351 #define   EDP_PSR_CRC_ENABLE			(1 << 10) /* BDW+ */
4352 #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
4353 #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
4354 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
4355 #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
4356 #define   EDP_PSR_TP4_TIME_0US			(3 << 6) /* ICL+ */
4357 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
4358 #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
4359 #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
4360 #define   EDP_PSR_TP1_TIME_0us			(3 << 4)
4361 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
4362 
4363 /*
4364  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4365  * to transcoder and bits defined for each one as if using no shift (i.e. as if
4366  * it was for TRANSCODER_EDP)
4367  */
4368 #define EDP_PSR_IMR				_MMIO(0x64834)
4369 #define EDP_PSR_IIR				_MMIO(0x64838)
4370 #define _PSR_IMR_A				0x60814
4371 #define _PSR_IIR_A				0x60818
4372 #define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(tran, _PSR_IMR_A)
4373 #define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(tran, _PSR_IIR_A)
4374 #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
4375 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
4376 #define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4377 #define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4378 #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4379 #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4380 
4381 #define _SRD_AUX_CTL_A				0x60810
4382 #define _SRD_AUX_CTL_EDP			0x6f810
4383 #define EDP_PSR_AUX_CTL(tran)			_MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
4384 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
4385 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
4386 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
4387 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
4388 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
4389 
4390 #define _SRD_AUX_DATA_A				0x60814
4391 #define _SRD_AUX_DATA_EDP			0x6f814
4392 #define EDP_PSR_AUX_DATA(tran, i)		_MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
4393 
4394 #define _SRD_STATUS_A				0x60840
4395 #define _SRD_STATUS_EDP				0x6f840
4396 #define EDP_PSR_STATUS(tran)			_MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
4397 #define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)
4398 #define   EDP_PSR_STATUS_STATE_SHIFT		29
4399 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
4400 #define   EDP_PSR_STATUS_STATE_SRDONACK		(1 << 29)
4401 #define   EDP_PSR_STATUS_STATE_SRDENT		(2 << 29)
4402 #define   EDP_PSR_STATUS_STATE_BUFOFF		(3 << 29)
4403 #define   EDP_PSR_STATUS_STATE_BUFON		(4 << 29)
4404 #define   EDP_PSR_STATUS_STATE_AUXACK		(5 << 29)
4405 #define   EDP_PSR_STATUS_STATE_SRDOFFACK	(6 << 29)
4406 #define   EDP_PSR_STATUS_LINK_MASK		(3 << 26)
4407 #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
4408 #define   EDP_PSR_STATUS_LINK_FULL_ON		(1 << 26)
4409 #define   EDP_PSR_STATUS_LINK_STANDBY		(2 << 26)
4410 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT	20
4411 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
4412 #define   EDP_PSR_STATUS_COUNT_SHIFT		16
4413 #define   EDP_PSR_STATUS_COUNT_MASK		0xf
4414 #define   EDP_PSR_STATUS_AUX_ERROR		(1 << 15)
4415 #define   EDP_PSR_STATUS_AUX_SENDING		(1 << 12)
4416 #define   EDP_PSR_STATUS_SENDING_IDLE		(1 << 9)
4417 #define   EDP_PSR_STATUS_SENDING_TP2_TP3	(1 << 8)
4418 #define   EDP_PSR_STATUS_SENDING_TP1		(1 << 4)
4419 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
4420 
4421 #define _SRD_PERF_CNT_A			0x60844
4422 #define _SRD_PERF_CNT_EDP		0x6f844
4423 #define EDP_PSR_PERF_CNT(tran)		_MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
4424 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
4425 
4426 /* PSR_MASK on SKL+ */
4427 #define _SRD_DEBUG_A				0x60860
4428 #define _SRD_DEBUG_EDP				0x6f860
4429 #define EDP_PSR_DEBUG(tran)			_MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
4430 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
4431 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
4432 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
4433 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
4434 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
4435 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4436 
4437 #define _PSR2_CTL_A			0x60900
4438 #define _PSR2_CTL_EDP			0x6f900
4439 #define EDP_PSR2_CTL(tran)		_MMIO_TRANS2(tran, _PSR2_CTL_A)
4440 #define   EDP_PSR2_ENABLE		(1 << 31)
4441 #define   EDP_SU_TRACK_ENABLE		(1 << 30)
4442 #define   EDP_Y_COORDINATE_VALID	(1 << 26) /* GLK and CNL+ */
4443 #define   EDP_Y_COORDINATE_ENABLE	(1 << 25) /* GLK and CNL+ */
4444 #define   EDP_MAX_SU_DISABLE_TIME(t)	((t) << 20)
4445 #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f << 20)
4446 #define   EDP_PSR2_TP2_TIME_500us	(0 << 8)
4447 #define   EDP_PSR2_TP2_TIME_100us	(1 << 8)
4448 #define   EDP_PSR2_TP2_TIME_2500us	(2 << 8)
4449 #define   EDP_PSR2_TP2_TIME_50us	(3 << 8)
4450 #define   EDP_PSR2_TP2_TIME_MASK	(3 << 8)
4451 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4452 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf << 4)
4453 #define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a) << 4)
4454 #define   EDP_PSR2_IDLE_FRAME_MASK	0xf
4455 #define   EDP_PSR2_IDLE_FRAME_SHIFT	0
4456 
4457 #define _PSR_EVENT_TRANS_A			0x60848
4458 #define _PSR_EVENT_TRANS_B			0x61848
4459 #define _PSR_EVENT_TRANS_C			0x62848
4460 #define _PSR_EVENT_TRANS_D			0x63848
4461 #define _PSR_EVENT_TRANS_EDP			0x6f848
4462 #define PSR_EVENT(tran)				_MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
4463 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE		(1 << 17)
4464 #define  PSR_EVENT_PSR2_DISABLED		(1 << 16)
4465 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN	(1 << 15)
4466 #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN		(1 << 14)
4467 #define  PSR_EVENT_GRAPHICS_RESET		(1 << 12)
4468 #define  PSR_EVENT_PCH_INTERRUPT		(1 << 11)
4469 #define  PSR_EVENT_MEMORY_UP			(1 << 10)
4470 #define  PSR_EVENT_FRONT_BUFFER_MODIFY		(1 << 9)
4471 #define  PSR_EVENT_WD_TIMER_EXPIRE		(1 << 8)
4472 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE	(1 << 6)
4473 #define  PSR_EVENT_REGISTER_UPDATE		(1 << 5) /* Reserved in ICL+ */
4474 #define  PSR_EVENT_HDCP_ENABLE			(1 << 4)
4475 #define  PSR_EVENT_KVMR_SESSION_ENABLE		(1 << 3)
4476 #define  PSR_EVENT_VBI_ENABLE			(1 << 2)
4477 #define  PSR_EVENT_LPSP_MODE_EXIT		(1 << 1)
4478 #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
4479 
4480 #define _PSR2_STATUS_A			0x60940
4481 #define _PSR2_STATUS_EDP		0x6f940
4482 #define EDP_PSR2_STATUS(tran)		_MMIO_TRANS2(tran, _PSR2_STATUS_A)
4483 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4484 #define EDP_PSR2_STATUS_STATE_SHIFT    28
4485 
4486 #define _PSR2_SU_STATUS_A		0x60914
4487 #define _PSR2_SU_STATUS_EDP		0x6f914
4488 #define _PSR2_SU_STATUS(tran, index)	_MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
4489 #define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
4490 #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
4491 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4492 #define PSR2_SU_STATUS_FRAMES		8
4493 
4494 /* VGA port control */
4495 #define ADPA			_MMIO(0x61100)
4496 #define PCH_ADPA                _MMIO(0xe1100)
4497 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
4498 
4499 #define   ADPA_DAC_ENABLE	(1 << 31)
4500 #define   ADPA_DAC_DISABLE	0
4501 #define   ADPA_PIPE_SEL_SHIFT		30
4502 #define   ADPA_PIPE_SEL_MASK		(1 << 30)
4503 #define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
4504 #define   ADPA_PIPE_SEL_SHIFT_CPT	29
4505 #define   ADPA_PIPE_SEL_MASK_CPT	(3 << 29)
4506 #define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
4507 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4508 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4509 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
4510 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4511 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
4512 #define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
4513 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4514 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
4515 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4516 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
4517 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4518 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
4519 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4520 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
4521 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
4522 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
4523 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4524 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
4525 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4526 #define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
4527 #define   ADPA_SETS_HVPOLARITY	0
4528 #define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4529 #define   ADPA_VSYNC_CNTL_ENABLE 0
4530 #define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4531 #define   ADPA_HSYNC_CNTL_ENABLE 0
4532 #define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4533 #define   ADPA_VSYNC_ACTIVE_LOW	0
4534 #define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4535 #define   ADPA_HSYNC_ACTIVE_LOW	0
4536 #define   ADPA_DPMS_MASK	(~(3 << 10))
4537 #define   ADPA_DPMS_ON		(0 << 10)
4538 #define   ADPA_DPMS_SUSPEND	(1 << 10)
4539 #define   ADPA_DPMS_STANDBY	(2 << 10)
4540 #define   ADPA_DPMS_OFF		(3 << 10)
4541 
4542 
4543 /* Hotplug control (945+ only) */
4544 #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4545 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
4546 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
4547 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
4548 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
4549 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
4550 #define   TV_HOTPLUG_INT_EN			(1 << 18)
4551 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
4552 #define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
4553 						 PORTC_HOTPLUG_INT_EN | \
4554 						 PORTD_HOTPLUG_INT_EN | \
4555 						 SDVOC_HOTPLUG_INT_EN | \
4556 						 SDVOB_HOTPLUG_INT_EN | \
4557 						 CRT_HOTPLUG_INT_EN)
4558 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
4559 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
4560 /* must use period 64 on GM45 according to docs */
4561 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
4562 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
4563 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
4564 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
4565 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
4566 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
4567 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
4568 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
4569 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
4570 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
4571 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
4572 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
4573 
4574 #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4575 /*
4576  * HDMI/DP bits are g4x+
4577  *
4578  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4579  * Please check the detailed lore in the commit message for for experimental
4580  * evidence.
4581  */
4582 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4583 #define   PORTD_HOTPLUG_LIVE_STATUS_GM45	(1 << 29)
4584 #define   PORTC_HOTPLUG_LIVE_STATUS_GM45	(1 << 28)
4585 #define   PORTB_HOTPLUG_LIVE_STATUS_GM45	(1 << 27)
4586 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4587 #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
4588 #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
4589 #define   PORTB_HOTPLUG_LIVE_STATUS_G4X		(1 << 29)
4590 #define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
4591 #define   PORTD_HOTPLUG_INT_LONG_PULSE		(2 << 21)
4592 #define   PORTD_HOTPLUG_INT_SHORT_PULSE		(1 << 21)
4593 #define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
4594 #define   PORTC_HOTPLUG_INT_LONG_PULSE		(2 << 19)
4595 #define   PORTC_HOTPLUG_INT_SHORT_PULSE		(1 << 19)
4596 #define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
4597 #define   PORTB_HOTPLUG_INT_LONG_PULSE		(2 << 17)
4598 #define   PORTB_HOTPLUG_INT_SHORT_PLUSE		(1 << 17)
4599 /* CRT/TV common between gen3+ */
4600 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
4601 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
4602 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
4603 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
4604 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
4605 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4606 #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X	(1 << 6)
4607 #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X	(1 << 5)
4608 #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X	(1 << 4)
4609 #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X	(7 << 4)
4610 
4611 /* SDVO is different across gen3/4 */
4612 #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
4613 #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
4614 /*
4615  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4616  * since reality corrobates that they're the same as on gen3. But keep these
4617  * bits here (and the comment!) to help any other lost wanderers back onto the
4618  * right tracks.
4619  */
4620 #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
4621 #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
4622 #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
4623 #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
4624 #define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
4625 						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4626 						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4627 						 PORTB_HOTPLUG_INT_STATUS | \
4628 						 PORTC_HOTPLUG_INT_STATUS | \
4629 						 PORTD_HOTPLUG_INT_STATUS)
4630 
4631 #define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
4632 						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4633 						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4634 						 PORTB_HOTPLUG_INT_STATUS | \
4635 						 PORTC_HOTPLUG_INT_STATUS | \
4636 						 PORTD_HOTPLUG_INT_STATUS)
4637 
4638 /* SDVO and HDMI port control.
4639  * The same register may be used for SDVO or HDMI */
4640 #define _GEN3_SDVOB	0x61140
4641 #define _GEN3_SDVOC	0x61160
4642 #define GEN3_SDVOB	_MMIO(_GEN3_SDVOB)
4643 #define GEN3_SDVOC	_MMIO(_GEN3_SDVOC)
4644 #define GEN4_HDMIB	GEN3_SDVOB
4645 #define GEN4_HDMIC	GEN3_SDVOC
4646 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
4647 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
4648 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
4649 #define PCH_SDVOB	_MMIO(0xe1140)
4650 #define PCH_HDMIB	PCH_SDVOB
4651 #define PCH_HDMIC	_MMIO(0xe1150)
4652 #define PCH_HDMID	_MMIO(0xe1160)
4653 
4654 #define PORT_DFT_I9XX				_MMIO(0x61150)
4655 #define   DC_BALANCE_RESET			(1 << 25)
4656 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4657 #define   DC_BALANCE_RESET_VLV			(1 << 31)
4658 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
4659 #define   PIPE_C_SCRAMBLE_RESET			(1 << 14) /* chv */
4660 #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
4661 #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
4662 
4663 /* Gen 3 SDVO bits: */
4664 #define   SDVO_ENABLE				(1 << 31)
4665 #define   SDVO_PIPE_SEL_SHIFT			30
4666 #define   SDVO_PIPE_SEL_MASK			(1 << 30)
4667 #define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
4668 #define   SDVO_STALL_SELECT			(1 << 29)
4669 #define   SDVO_INTERRUPT_ENABLE			(1 << 26)
4670 /*
4671  * 915G/GM SDVO pixel multiplier.
4672  * Programmed value is multiplier - 1, up to 5x.
4673  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4674  */
4675 #define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
4676 #define   SDVO_PORT_MULTIPLY_SHIFT		23
4677 #define   SDVO_PHASE_SELECT_MASK		(15 << 19)
4678 #define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
4679 #define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
4680 #define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
4681 #define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
4682 #define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
4683 #define   SDVO_DETECTED				(1 << 2)
4684 /* Bits to be preserved when writing */
4685 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4686 			       SDVO_INTERRUPT_ENABLE)
4687 #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4688 
4689 /* Gen 4 SDVO/HDMI bits: */
4690 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
4691 #define   SDVO_COLOR_FORMAT_MASK		(7 << 26)
4692 #define   SDVO_ENCODING_SDVO			(0 << 10)
4693 #define   SDVO_ENCODING_HDMI			(2 << 10)
4694 #define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
4695 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
4696 #define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
4697 #define   HDMI_AUDIO_ENABLE			(1 << 6) /* HDMI only */
4698 /* VSYNC/HSYNC bits new with 965, default is to be set */
4699 #define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
4700 #define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
4701 
4702 /* Gen 5 (IBX) SDVO/HDMI bits: */
4703 #define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
4704 #define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
4705 
4706 /* Gen 6 (CPT) SDVO/HDMI bits: */
4707 #define   SDVO_PIPE_SEL_SHIFT_CPT		29
4708 #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
4709 #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
4710 
4711 /* CHV SDVO/HDMI bits: */
4712 #define   SDVO_PIPE_SEL_SHIFT_CHV		24
4713 #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
4714 #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
4715 
4716 
4717 /* DVO port control */
4718 #define _DVOA			0x61120
4719 #define DVOA			_MMIO(_DVOA)
4720 #define _DVOB			0x61140
4721 #define DVOB			_MMIO(_DVOB)
4722 #define _DVOC			0x61160
4723 #define DVOC			_MMIO(_DVOC)
4724 #define   DVO_ENABLE			(1 << 31)
4725 #define   DVO_PIPE_SEL_SHIFT		30
4726 #define   DVO_PIPE_SEL_MASK		(1 << 30)
4727 #define   DVO_PIPE_SEL(pipe)		((pipe) << 30)
4728 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
4729 #define   DVO_PIPE_STALL		(1 << 28)
4730 #define   DVO_PIPE_STALL_TV		(2 << 28)
4731 #define   DVO_PIPE_STALL_MASK		(3 << 28)
4732 #define   DVO_USE_VGA_SYNC		(1 << 15)
4733 #define   DVO_DATA_ORDER_I740		(0 << 14)
4734 #define   DVO_DATA_ORDER_FP		(1 << 14)
4735 #define   DVO_VSYNC_DISABLE		(1 << 11)
4736 #define   DVO_HSYNC_DISABLE		(1 << 10)
4737 #define   DVO_VSYNC_TRISTATE		(1 << 9)
4738 #define   DVO_HSYNC_TRISTATE		(1 << 8)
4739 #define   DVO_BORDER_ENABLE		(1 << 7)
4740 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
4741 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
4742 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
4743 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
4744 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
4745 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
4746 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
4747 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
4748 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
4749 #define   DVO_PRESERVE_MASK		(0x7 << 24)
4750 #define DVOA_SRCDIM		_MMIO(0x61124)
4751 #define DVOB_SRCDIM		_MMIO(0x61144)
4752 #define DVOC_SRCDIM		_MMIO(0x61164)
4753 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
4754 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
4755 
4756 /* LVDS port control */
4757 #define LVDS			_MMIO(0x61180)
4758 /*
4759  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
4760  * the DPLL semantics change when the LVDS is assigned to that pipe.
4761  */
4762 #define   LVDS_PORT_EN			(1 << 31)
4763 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
4764 #define   LVDS_PIPE_SEL_SHIFT		30
4765 #define   LVDS_PIPE_SEL_MASK		(1 << 30)
4766 #define   LVDS_PIPE_SEL(pipe)		((pipe) << 30)
4767 #define   LVDS_PIPE_SEL_SHIFT_CPT	29
4768 #define   LVDS_PIPE_SEL_MASK_CPT	(3 << 29)
4769 #define   LVDS_PIPE_SEL_CPT(pipe)	((pipe) << 29)
4770 /* LVDS dithering flag on 965/g4x platform */
4771 #define   LVDS_ENABLE_DITHER		(1 << 25)
4772 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4773 #define   LVDS_VSYNC_POLARITY		(1 << 21)
4774 #define   LVDS_HSYNC_POLARITY		(1 << 20)
4775 
4776 /* Enable border for unscaled (or aspect-scaled) display */
4777 #define   LVDS_BORDER_ENABLE		(1 << 15)
4778 /*
4779  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4780  * pixel.
4781  */
4782 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
4783 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
4784 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
4785 /*
4786  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4787  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4788  * on.
4789  */
4790 #define   LVDS_A3_POWER_MASK		(3 << 6)
4791 #define   LVDS_A3_POWER_DOWN		(0 << 6)
4792 #define   LVDS_A3_POWER_UP		(3 << 6)
4793 /*
4794  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
4795  * is set.
4796  */
4797 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
4798 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
4799 #define   LVDS_CLKB_POWER_UP		(3 << 4)
4800 /*
4801  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
4802  * setting for whether we are in dual-channel mode.  The B3 pair will
4803  * additionally only be powered up when LVDS_A3_POWER_UP is set.
4804  */
4805 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
4806 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
4807 #define   LVDS_B0B3_POWER_UP		(3 << 2)
4808 
4809 /* Video Data Island Packet control */
4810 #define VIDEO_DIP_DATA		_MMIO(0x61178)
4811 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4812  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4813  * of the infoframe structure specified by CEA-861. */
4814 #define   VIDEO_DIP_DATA_SIZE	32
4815 #define   VIDEO_DIP_GMP_DATA_SIZE	36
4816 #define   VIDEO_DIP_VSC_DATA_SIZE	36
4817 #define   VIDEO_DIP_PPS_DATA_SIZE	132
4818 #define VIDEO_DIP_CTL		_MMIO(0x61170)
4819 /* Pre HSW: */
4820 #define   VIDEO_DIP_ENABLE		(1 << 31)
4821 #define   VIDEO_DIP_PORT(port)		((port) << 29)
4822 #define   VIDEO_DIP_PORT_MASK		(3 << 29)
4823 #define   VIDEO_DIP_ENABLE_GCP		(1 << 25) /* ilk+ */
4824 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
4825 #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
4826 #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21) /* ilk+ */
4827 #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
4828 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
4829 #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
4830 #define   VIDEO_DIP_SELECT_GAMUT	(2 << 19)
4831 #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
4832 #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
4833 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
4834 #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
4835 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
4836 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
4837 /* HSW and later: */
4838 #define   VIDEO_DIP_ENABLE_DRM_GLK	(1 << 28)
4839 #define   PSR_VSC_BIT_7_SET		(1 << 27)
4840 #define   VSC_SELECT_MASK		(0x3 << 25)
4841 #define   VSC_SELECT_SHIFT		25
4842 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
4843 #define   VSC_DIP_HW_HEA_SW_DATA	(1 << 25)
4844 #define   VSC_DIP_HW_DATA_SW_HEA	(2 << 25)
4845 #define   VSC_DIP_SW_HEA_DATA		(3 << 25)
4846 #define   VDIP_ENABLE_PPS		(1 << 24)
4847 #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
4848 #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
4849 #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
4850 #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
4851 #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
4852 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
4853 
4854 /* Panel power sequencing */
4855 #define PPS_BASE			0x61200
4856 #define VLV_PPS_BASE			(VLV_DISPLAY_BASE + PPS_BASE)
4857 #define PCH_PPS_BASE			0xC7200
4858 
4859 #define _MMIO_PPS(pps_idx, reg)		_MMIO(dev_priv->pps_mmio_base -	\
4860 					      PPS_BASE + (reg) +	\
4861 					      (pps_idx) * 0x100)
4862 
4863 #define _PP_STATUS			0x61200
4864 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
4865 #define   PP_ON				REG_BIT(31)
4866 /*
4867  * Indicates that all dependencies of the panel are on:
4868  *
4869  * - PLL enabled
4870  * - pipe enabled
4871  * - LVDS/DVOB/DVOC on
4872  */
4873 #define   PP_READY			REG_BIT(30)
4874 #define   PP_SEQUENCE_MASK		REG_GENMASK(29, 28)
4875 #define   PP_SEQUENCE_NONE		REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4876 #define   PP_SEQUENCE_POWER_UP		REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4877 #define   PP_SEQUENCE_POWER_DOWN	REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4878 #define   PP_CYCLE_DELAY_ACTIVE		REG_BIT(27)
4879 #define   PP_SEQUENCE_STATE_MASK	REG_GENMASK(3, 0)
4880 #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4881 #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4882 #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4883 #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4884 #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4885 #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
4886 #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
4887 #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
4888 #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
4889 
4890 #define _PP_CONTROL			0x61204
4891 #define PP_CONTROL(pps_idx)		_MMIO_PPS(pps_idx, _PP_CONTROL)
4892 #define  PANEL_UNLOCK_MASK		REG_GENMASK(31, 16)
4893 #define  PANEL_UNLOCK_REGS		REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
4894 #define  BXT_POWER_CYCLE_DELAY_MASK	REG_GENMASK(8, 4)
4895 #define  EDP_FORCE_VDD			REG_BIT(3)
4896 #define  EDP_BLC_ENABLE			REG_BIT(2)
4897 #define  PANEL_POWER_RESET		REG_BIT(1)
4898 #define  PANEL_POWER_ON			REG_BIT(0)
4899 
4900 #define _PP_ON_DELAYS			0x61208
4901 #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4902 #define  PANEL_PORT_SELECT_MASK		REG_GENMASK(31, 30)
4903 #define  PANEL_PORT_SELECT_LVDS		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
4904 #define  PANEL_PORT_SELECT_DPA		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
4905 #define  PANEL_PORT_SELECT_DPC		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
4906 #define  PANEL_PORT_SELECT_DPD		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
4907 #define  PANEL_PORT_SELECT_VLV(port)	REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
4908 #define  PANEL_POWER_UP_DELAY_MASK	REG_GENMASK(28, 16)
4909 #define  PANEL_LIGHT_ON_DELAY_MASK	REG_GENMASK(12, 0)
4910 
4911 #define _PP_OFF_DELAYS			0x6120C
4912 #define PP_OFF_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4913 #define  PANEL_POWER_DOWN_DELAY_MASK	REG_GENMASK(28, 16)
4914 #define  PANEL_LIGHT_OFF_DELAY_MASK	REG_GENMASK(12, 0)
4915 
4916 #define _PP_DIVISOR			0x61210
4917 #define PP_DIVISOR(pps_idx)		_MMIO_PPS(pps_idx, _PP_DIVISOR)
4918 #define  PP_REFERENCE_DIVIDER_MASK	REG_GENMASK(31, 8)
4919 #define  PANEL_POWER_CYCLE_DELAY_MASK	REG_GENMASK(4, 0)
4920 
4921 /* Panel fitting */
4922 #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4923 #define   PFIT_ENABLE		(1 << 31)
4924 #define   PFIT_PIPE_MASK	(3 << 29)
4925 #define   PFIT_PIPE_SHIFT	29
4926 #define   PFIT_PIPE(pipe)	((pipe) << 29)
4927 #define   VERT_INTERP_DISABLE	(0 << 10)
4928 #define   VERT_INTERP_BILINEAR	(1 << 10)
4929 #define   VERT_INTERP_MASK	(3 << 10)
4930 #define   VERT_AUTO_SCALE	(1 << 9)
4931 #define   HORIZ_INTERP_DISABLE	(0 << 6)
4932 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
4933 #define   HORIZ_INTERP_MASK	(3 << 6)
4934 #define   HORIZ_AUTO_SCALE	(1 << 5)
4935 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
4936 #define   PFIT_FILTER_FUZZY	(0 << 24)
4937 #define   PFIT_SCALING_AUTO	(0 << 26)
4938 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
4939 #define   PFIT_SCALING_PILLAR	(2 << 26)
4940 #define   PFIT_SCALING_LETTER	(3 << 26)
4941 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4942 /* Pre-965 */
4943 #define		PFIT_VERT_SCALE_SHIFT		20
4944 #define		PFIT_VERT_SCALE_MASK		0xfff00000
4945 #define		PFIT_HORIZ_SCALE_SHIFT		4
4946 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
4947 /* 965+ */
4948 #define		PFIT_VERT_SCALE_SHIFT_965	16
4949 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
4950 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
4951 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
4952 
4953 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4954 
4955 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
4956 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4957 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4958 					 _VLV_BLC_PWM_CTL2_B)
4959 
4960 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4961 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4962 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4963 					_VLV_BLC_PWM_CTL_B)
4964 
4965 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4966 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4967 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4968 					 _VLV_BLC_HIST_CTL_B)
4969 
4970 /* Backlight control */
4971 #define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4972 #define   BLM_PWM_ENABLE		(1 << 31)
4973 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
4974 #define   BLM_PIPE_SELECT		(1 << 29)
4975 #define   BLM_PIPE_SELECT_IVB		(3 << 29)
4976 #define   BLM_PIPE_A			(0 << 29)
4977 #define   BLM_PIPE_B			(1 << 29)
4978 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
4979 #define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
4980 #define   BLM_TRANSCODER_B		BLM_PIPE_B
4981 #define   BLM_TRANSCODER_C		BLM_PIPE_C
4982 #define   BLM_TRANSCODER_EDP		(3 << 29)
4983 #define   BLM_PIPE(pipe)		((pipe) << 29)
4984 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
4985 #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
4986 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
4987 #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
4988 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
4989 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
4990 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
4991 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
4992 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
4993 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
4994 #define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4995 /*
4996  * This is the most significant 15 bits of the number of backlight cycles in a
4997  * complete cycle of the modulated backlight control.
4998  *
4999  * The actual value is this field multiplied by two.
5000  */
5001 #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
5002 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
5003 #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
5004 /*
5005  * This is the number of cycles out of the backlight modulation cycle for which
5006  * the backlight is on.
5007  *
5008  * This field must be no greater than the number of cycles in the complete
5009  * backlight modulation cycle.
5010  */
5011 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
5012 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
5013 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
5014 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
5015 
5016 #define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5017 #define  BLM_HISTOGRAM_ENABLE			(1 << 31)
5018 
5019 /* New registers for PCH-split platforms. Safe where new bits show up, the
5020  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
5021 #define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
5022 #define BLC_PWM_CPU_CTL		_MMIO(0x48254)
5023 
5024 #define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
5025 
5026 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
5027  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
5028 #define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
5029 #define   BLM_PCH_PWM_ENABLE			(1 << 31)
5030 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
5031 #define   BLM_PCH_POLARITY			(1 << 29)
5032 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
5033 
5034 #define UTIL_PIN_CTL			_MMIO(0x48400)
5035 #define   UTIL_PIN_ENABLE		(1 << 31)
5036 #define   UTIL_PIN_PIPE_MASK		(3 << 29)
5037 #define   UTIL_PIN_PIPE(x)		((x) << 29)
5038 #define   UTIL_PIN_MODE_MASK		(0xf << 24)
5039 #define   UTIL_PIN_MODE_DATA		(0 << 24)
5040 #define   UTIL_PIN_MODE_PWM		(1 << 24)
5041 #define   UTIL_PIN_MODE_VBLANK		(4 << 24)
5042 #define   UTIL_PIN_MODE_VSYNC		(5 << 24)
5043 #define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
5044 #define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
5045 #define   UTIL_PIN_POLARITY		(1 << 22)
5046 #define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
5047 #define   UTIL_PIN_INPUT_DATA		(1 << 16)
5048 
5049 /* BXT backlight register definition. */
5050 #define _BXT_BLC_PWM_CTL1			0xC8250
5051 #define   BXT_BLC_PWM_ENABLE			(1 << 31)
5052 #define   BXT_BLC_PWM_POLARITY			(1 << 29)
5053 #define _BXT_BLC_PWM_FREQ1			0xC8254
5054 #define _BXT_BLC_PWM_DUTY1			0xC8258
5055 
5056 #define _BXT_BLC_PWM_CTL2			0xC8350
5057 #define _BXT_BLC_PWM_FREQ2			0xC8354
5058 #define _BXT_BLC_PWM_DUTY2			0xC8358
5059 
5060 #define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
5061 					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
5062 #define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
5063 					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
5064 #define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
5065 					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
5066 
5067 #define PCH_GTC_CTL		_MMIO(0xe7000)
5068 #define   PCH_GTC_ENABLE	(1 << 31)
5069 
5070 /* TV port control */
5071 #define TV_CTL			_MMIO(0x68000)
5072 /* Enables the TV encoder */
5073 # define TV_ENC_ENABLE			(1 << 31)
5074 /* Sources the TV encoder input from pipe B instead of A. */
5075 # define TV_ENC_PIPE_SEL_SHIFT		30
5076 # define TV_ENC_PIPE_SEL_MASK		(1 << 30)
5077 # define TV_ENC_PIPE_SEL(pipe)		((pipe) << 30)
5078 /* Outputs composite video (DAC A only) */
5079 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
5080 /* Outputs SVideo video (DAC B/C) */
5081 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
5082 /* Outputs Component video (DAC A/B/C) */
5083 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
5084 /* Outputs Composite and SVideo (DAC A/B/C) */
5085 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
5086 # define TV_TRILEVEL_SYNC		(1 << 21)
5087 /* Enables slow sync generation (945GM only) */
5088 # define TV_SLOW_SYNC			(1 << 20)
5089 /* Selects 4x oversampling for 480i and 576p */
5090 # define TV_OVERSAMPLE_4X		(0 << 18)
5091 /* Selects 2x oversampling for 720p and 1080i */
5092 # define TV_OVERSAMPLE_2X		(1 << 18)
5093 /* Selects no oversampling for 1080p */
5094 # define TV_OVERSAMPLE_NONE		(2 << 18)
5095 /* Selects 8x oversampling */
5096 # define TV_OVERSAMPLE_8X		(3 << 18)
5097 # define TV_OVERSAMPLE_MASK		(3 << 18)
5098 /* Selects progressive mode rather than interlaced */
5099 # define TV_PROGRESSIVE			(1 << 17)
5100 /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
5101 # define TV_PAL_BURST			(1 << 16)
5102 /* Field for setting delay of Y compared to C */
5103 # define TV_YC_SKEW_MASK		(7 << 12)
5104 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
5105 # define TV_ENC_SDP_FIX			(1 << 11)
5106 /*
5107  * Enables a fix for the 915GM only.
5108  *
5109  * Not sure what it does.
5110  */
5111 # define TV_ENC_C0_FIX			(1 << 10)
5112 /* Bits that must be preserved by software */
5113 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5114 # define TV_FUSE_STATE_MASK		(3 << 4)
5115 /* Read-only state that reports all features enabled */
5116 # define TV_FUSE_STATE_ENABLED		(0 << 4)
5117 /* Read-only state that reports that Macrovision is disabled in hardware*/
5118 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
5119 /* Read-only state that reports that TV-out is disabled in hardware. */
5120 # define TV_FUSE_STATE_DISABLED		(2 << 4)
5121 /* Normal operation */
5122 # define TV_TEST_MODE_NORMAL		(0 << 0)
5123 /* Encoder test pattern 1 - combo pattern */
5124 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
5125 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5126 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
5127 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5128 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
5129 /* Encoder test pattern 4 - random noise */
5130 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
5131 /* Encoder test pattern 5 - linear color ramps */
5132 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
5133 /*
5134  * This test mode forces the DACs to 50% of full output.
5135  *
5136  * This is used for load detection in combination with TVDAC_SENSE_MASK
5137  */
5138 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
5139 # define TV_TEST_MODE_MASK		(7 << 0)
5140 
5141 #define TV_DAC			_MMIO(0x68004)
5142 # define TV_DAC_SAVE		0x00ffff00
5143 /*
5144  * Reports that DAC state change logic has reported change (RO).
5145  *
5146  * This gets cleared when TV_DAC_STATE_EN is cleared
5147 */
5148 # define TVDAC_STATE_CHG		(1 << 31)
5149 # define TVDAC_SENSE_MASK		(7 << 28)
5150 /* Reports that DAC A voltage is above the detect threshold */
5151 # define TVDAC_A_SENSE			(1 << 30)
5152 /* Reports that DAC B voltage is above the detect threshold */
5153 # define TVDAC_B_SENSE			(1 << 29)
5154 /* Reports that DAC C voltage is above the detect threshold */
5155 # define TVDAC_C_SENSE			(1 << 28)
5156 /*
5157  * Enables DAC state detection logic, for load-based TV detection.
5158  *
5159  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5160  * to off, for load detection to work.
5161  */
5162 # define TVDAC_STATE_CHG_EN		(1 << 27)
5163 /* Sets the DAC A sense value to high */
5164 # define TVDAC_A_SENSE_CTL		(1 << 26)
5165 /* Sets the DAC B sense value to high */
5166 # define TVDAC_B_SENSE_CTL		(1 << 25)
5167 /* Sets the DAC C sense value to high */
5168 # define TVDAC_C_SENSE_CTL		(1 << 24)
5169 /* Overrides the ENC_ENABLE and DAC voltage levels */
5170 # define DAC_CTL_OVERRIDE		(1 << 7)
5171 /* Sets the slew rate.  Must be preserved in software */
5172 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
5173 # define DAC_A_1_3_V			(0 << 4)
5174 # define DAC_A_1_1_V			(1 << 4)
5175 # define DAC_A_0_7_V			(2 << 4)
5176 # define DAC_A_MASK			(3 << 4)
5177 # define DAC_B_1_3_V			(0 << 2)
5178 # define DAC_B_1_1_V			(1 << 2)
5179 # define DAC_B_0_7_V			(2 << 2)
5180 # define DAC_B_MASK			(3 << 2)
5181 # define DAC_C_1_3_V			(0 << 0)
5182 # define DAC_C_1_1_V			(1 << 0)
5183 # define DAC_C_0_7_V			(2 << 0)
5184 # define DAC_C_MASK			(3 << 0)
5185 
5186 /*
5187  * CSC coefficients are stored in a floating point format with 9 bits of
5188  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
5189  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5190  * -1 (0x3) being the only legal negative value.
5191  */
5192 #define TV_CSC_Y		_MMIO(0x68010)
5193 # define TV_RY_MASK			0x07ff0000
5194 # define TV_RY_SHIFT			16
5195 # define TV_GY_MASK			0x00000fff
5196 # define TV_GY_SHIFT			0
5197 
5198 #define TV_CSC_Y2		_MMIO(0x68014)
5199 # define TV_BY_MASK			0x07ff0000
5200 # define TV_BY_SHIFT			16
5201 /*
5202  * Y attenuation for component video.
5203  *
5204  * Stored in 1.9 fixed point.
5205  */
5206 # define TV_AY_MASK			0x000003ff
5207 # define TV_AY_SHIFT			0
5208 
5209 #define TV_CSC_U		_MMIO(0x68018)
5210 # define TV_RU_MASK			0x07ff0000
5211 # define TV_RU_SHIFT			16
5212 # define TV_GU_MASK			0x000007ff
5213 # define TV_GU_SHIFT			0
5214 
5215 #define TV_CSC_U2		_MMIO(0x6801c)
5216 # define TV_BU_MASK			0x07ff0000
5217 # define TV_BU_SHIFT			16
5218 /*
5219  * U attenuation for component video.
5220  *
5221  * Stored in 1.9 fixed point.
5222  */
5223 # define TV_AU_MASK			0x000003ff
5224 # define TV_AU_SHIFT			0
5225 
5226 #define TV_CSC_V		_MMIO(0x68020)
5227 # define TV_RV_MASK			0x0fff0000
5228 # define TV_RV_SHIFT			16
5229 # define TV_GV_MASK			0x000007ff
5230 # define TV_GV_SHIFT			0
5231 
5232 #define TV_CSC_V2		_MMIO(0x68024)
5233 # define TV_BV_MASK			0x07ff0000
5234 # define TV_BV_SHIFT			16
5235 /*
5236  * V attenuation for component video.
5237  *
5238  * Stored in 1.9 fixed point.
5239  */
5240 # define TV_AV_MASK			0x000007ff
5241 # define TV_AV_SHIFT			0
5242 
5243 #define TV_CLR_KNOBS		_MMIO(0x68028)
5244 /* 2s-complement brightness adjustment */
5245 # define TV_BRIGHTNESS_MASK		0xff000000
5246 # define TV_BRIGHTNESS_SHIFT		24
5247 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5248 # define TV_CONTRAST_MASK		0x00ff0000
5249 # define TV_CONTRAST_SHIFT		16
5250 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5251 # define TV_SATURATION_MASK		0x0000ff00
5252 # define TV_SATURATION_SHIFT		8
5253 /* Hue adjustment, as an integer phase angle in degrees */
5254 # define TV_HUE_MASK			0x000000ff
5255 # define TV_HUE_SHIFT			0
5256 
5257 #define TV_CLR_LEVEL		_MMIO(0x6802c)
5258 /* Controls the DAC level for black */
5259 # define TV_BLACK_LEVEL_MASK		0x01ff0000
5260 # define TV_BLACK_LEVEL_SHIFT		16
5261 /* Controls the DAC level for blanking */
5262 # define TV_BLANK_LEVEL_MASK		0x000001ff
5263 # define TV_BLANK_LEVEL_SHIFT		0
5264 
5265 #define TV_H_CTL_1		_MMIO(0x68030)
5266 /* Number of pixels in the hsync. */
5267 # define TV_HSYNC_END_MASK		0x1fff0000
5268 # define TV_HSYNC_END_SHIFT		16
5269 /* Total number of pixels minus one in the line (display and blanking). */
5270 # define TV_HTOTAL_MASK			0x00001fff
5271 # define TV_HTOTAL_SHIFT		0
5272 
5273 #define TV_H_CTL_2		_MMIO(0x68034)
5274 /* Enables the colorburst (needed for non-component color) */
5275 # define TV_BURST_ENA			(1 << 31)
5276 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5277 # define TV_HBURST_START_SHIFT		16
5278 # define TV_HBURST_START_MASK		0x1fff0000
5279 /* Length of the colorburst */
5280 # define TV_HBURST_LEN_SHIFT		0
5281 # define TV_HBURST_LEN_MASK		0x0001fff
5282 
5283 #define TV_H_CTL_3		_MMIO(0x68038)
5284 /* End of hblank, measured in pixels minus one from start of hsync */
5285 # define TV_HBLANK_END_SHIFT		16
5286 # define TV_HBLANK_END_MASK		0x1fff0000
5287 /* Start of hblank, measured in pixels minus one from start of hsync */
5288 # define TV_HBLANK_START_SHIFT		0
5289 # define TV_HBLANK_START_MASK		0x0001fff
5290 
5291 #define TV_V_CTL_1		_MMIO(0x6803c)
5292 /* XXX */
5293 # define TV_NBR_END_SHIFT		16
5294 # define TV_NBR_END_MASK		0x07ff0000
5295 /* XXX */
5296 # define TV_VI_END_F1_SHIFT		8
5297 # define TV_VI_END_F1_MASK		0x00003f00
5298 /* XXX */
5299 # define TV_VI_END_F2_SHIFT		0
5300 # define TV_VI_END_F2_MASK		0x0000003f
5301 
5302 #define TV_V_CTL_2		_MMIO(0x68040)
5303 /* Length of vsync, in half lines */
5304 # define TV_VSYNC_LEN_MASK		0x07ff0000
5305 # define TV_VSYNC_LEN_SHIFT		16
5306 /* Offset of the start of vsync in field 1, measured in one less than the
5307  * number of half lines.
5308  */
5309 # define TV_VSYNC_START_F1_MASK		0x00007f00
5310 # define TV_VSYNC_START_F1_SHIFT	8
5311 /*
5312  * Offset of the start of vsync in field 2, measured in one less than the
5313  * number of half lines.
5314  */
5315 # define TV_VSYNC_START_F2_MASK		0x0000007f
5316 # define TV_VSYNC_START_F2_SHIFT	0
5317 
5318 #define TV_V_CTL_3		_MMIO(0x68044)
5319 /* Enables generation of the equalization signal */
5320 # define TV_EQUAL_ENA			(1 << 31)
5321 /* Length of vsync, in half lines */
5322 # define TV_VEQ_LEN_MASK		0x007f0000
5323 # define TV_VEQ_LEN_SHIFT		16
5324 /* Offset of the start of equalization in field 1, measured in one less than
5325  * the number of half lines.
5326  */
5327 # define TV_VEQ_START_F1_MASK		0x0007f00
5328 # define TV_VEQ_START_F1_SHIFT		8
5329 /*
5330  * Offset of the start of equalization in field 2, measured in one less than
5331  * the number of half lines.
5332  */
5333 # define TV_VEQ_START_F2_MASK		0x000007f
5334 # define TV_VEQ_START_F2_SHIFT		0
5335 
5336 #define TV_V_CTL_4		_MMIO(0x68048)
5337 /*
5338  * Offset to start of vertical colorburst, measured in one less than the
5339  * number of lines from vertical start.
5340  */
5341 # define TV_VBURST_START_F1_MASK	0x003f0000
5342 # define TV_VBURST_START_F1_SHIFT	16
5343 /*
5344  * Offset to the end of vertical colorburst, measured in one less than the
5345  * number of lines from the start of NBR.
5346  */
5347 # define TV_VBURST_END_F1_MASK		0x000000ff
5348 # define TV_VBURST_END_F1_SHIFT		0
5349 
5350 #define TV_V_CTL_5		_MMIO(0x6804c)
5351 /*
5352  * Offset to start of vertical colorburst, measured in one less than the
5353  * number of lines from vertical start.
5354  */
5355 # define TV_VBURST_START_F2_MASK	0x003f0000
5356 # define TV_VBURST_START_F2_SHIFT	16
5357 /*
5358  * Offset to the end of vertical colorburst, measured in one less than the
5359  * number of lines from the start of NBR.
5360  */
5361 # define TV_VBURST_END_F2_MASK		0x000000ff
5362 # define TV_VBURST_END_F2_SHIFT		0
5363 
5364 #define TV_V_CTL_6		_MMIO(0x68050)
5365 /*
5366  * Offset to start of vertical colorburst, measured in one less than the
5367  * number of lines from vertical start.
5368  */
5369 # define TV_VBURST_START_F3_MASK	0x003f0000
5370 # define TV_VBURST_START_F3_SHIFT	16
5371 /*
5372  * Offset to the end of vertical colorburst, measured in one less than the
5373  * number of lines from the start of NBR.
5374  */
5375 # define TV_VBURST_END_F3_MASK		0x000000ff
5376 # define TV_VBURST_END_F3_SHIFT		0
5377 
5378 #define TV_V_CTL_7		_MMIO(0x68054)
5379 /*
5380  * Offset to start of vertical colorburst, measured in one less than the
5381  * number of lines from vertical start.
5382  */
5383 # define TV_VBURST_START_F4_MASK	0x003f0000
5384 # define TV_VBURST_START_F4_SHIFT	16
5385 /*
5386  * Offset to the end of vertical colorburst, measured in one less than the
5387  * number of lines from the start of NBR.
5388  */
5389 # define TV_VBURST_END_F4_MASK		0x000000ff
5390 # define TV_VBURST_END_F4_SHIFT		0
5391 
5392 #define TV_SC_CTL_1		_MMIO(0x68060)
5393 /* Turns on the first subcarrier phase generation DDA */
5394 # define TV_SC_DDA1_EN			(1 << 31)
5395 /* Turns on the first subcarrier phase generation DDA */
5396 # define TV_SC_DDA2_EN			(1 << 30)
5397 /* Turns on the first subcarrier phase generation DDA */
5398 # define TV_SC_DDA3_EN			(1 << 29)
5399 /* Sets the subcarrier DDA to reset frequency every other field */
5400 # define TV_SC_RESET_EVERY_2		(0 << 24)
5401 /* Sets the subcarrier DDA to reset frequency every fourth field */
5402 # define TV_SC_RESET_EVERY_4		(1 << 24)
5403 /* Sets the subcarrier DDA to reset frequency every eighth field */
5404 # define TV_SC_RESET_EVERY_8		(2 << 24)
5405 /* Sets the subcarrier DDA to never reset the frequency */
5406 # define TV_SC_RESET_NEVER		(3 << 24)
5407 /* Sets the peak amplitude of the colorburst.*/
5408 # define TV_BURST_LEVEL_MASK		0x00ff0000
5409 # define TV_BURST_LEVEL_SHIFT		16
5410 /* Sets the increment of the first subcarrier phase generation DDA */
5411 # define TV_SCDDA1_INC_MASK		0x00000fff
5412 # define TV_SCDDA1_INC_SHIFT		0
5413 
5414 #define TV_SC_CTL_2		_MMIO(0x68064)
5415 /* Sets the rollover for the second subcarrier phase generation DDA */
5416 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
5417 # define TV_SCDDA2_SIZE_SHIFT		16
5418 /* Sets the increent of the second subcarrier phase generation DDA */
5419 # define TV_SCDDA2_INC_MASK		0x00007fff
5420 # define TV_SCDDA2_INC_SHIFT		0
5421 
5422 #define TV_SC_CTL_3		_MMIO(0x68068)
5423 /* Sets the rollover for the third subcarrier phase generation DDA */
5424 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
5425 # define TV_SCDDA3_SIZE_SHIFT		16
5426 /* Sets the increent of the third subcarrier phase generation DDA */
5427 # define TV_SCDDA3_INC_MASK		0x00007fff
5428 # define TV_SCDDA3_INC_SHIFT		0
5429 
5430 #define TV_WIN_POS		_MMIO(0x68070)
5431 /* X coordinate of the display from the start of horizontal active */
5432 # define TV_XPOS_MASK			0x1fff0000
5433 # define TV_XPOS_SHIFT			16
5434 /* Y coordinate of the display from the start of vertical active (NBR) */
5435 # define TV_YPOS_MASK			0x00000fff
5436 # define TV_YPOS_SHIFT			0
5437 
5438 #define TV_WIN_SIZE		_MMIO(0x68074)
5439 /* Horizontal size of the display window, measured in pixels*/
5440 # define TV_XSIZE_MASK			0x1fff0000
5441 # define TV_XSIZE_SHIFT			16
5442 /*
5443  * Vertical size of the display window, measured in pixels.
5444  *
5445  * Must be even for interlaced modes.
5446  */
5447 # define TV_YSIZE_MASK			0x00000fff
5448 # define TV_YSIZE_SHIFT			0
5449 
5450 #define TV_FILTER_CTL_1		_MMIO(0x68080)
5451 /*
5452  * Enables automatic scaling calculation.
5453  *
5454  * If set, the rest of the registers are ignored, and the calculated values can
5455  * be read back from the register.
5456  */
5457 # define TV_AUTO_SCALE			(1 << 31)
5458 /*
5459  * Disables the vertical filter.
5460  *
5461  * This is required on modes more than 1024 pixels wide */
5462 # define TV_V_FILTER_BYPASS		(1 << 29)
5463 /* Enables adaptive vertical filtering */
5464 # define TV_VADAPT			(1 << 28)
5465 # define TV_VADAPT_MODE_MASK		(3 << 26)
5466 /* Selects the least adaptive vertical filtering mode */
5467 # define TV_VADAPT_MODE_LEAST		(0 << 26)
5468 /* Selects the moderately adaptive vertical filtering mode */
5469 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
5470 /* Selects the most adaptive vertical filtering mode */
5471 # define TV_VADAPT_MODE_MOST		(3 << 26)
5472 /*
5473  * Sets the horizontal scaling factor.
5474  *
5475  * This should be the fractional part of the horizontal scaling factor divided
5476  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
5477  *
5478  * (src width - 1) / ((oversample * dest width) - 1)
5479  */
5480 # define TV_HSCALE_FRAC_MASK		0x00003fff
5481 # define TV_HSCALE_FRAC_SHIFT		0
5482 
5483 #define TV_FILTER_CTL_2		_MMIO(0x68084)
5484 /*
5485  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5486  *
5487  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5488  */
5489 # define TV_VSCALE_INT_MASK		0x00038000
5490 # define TV_VSCALE_INT_SHIFT		15
5491 /*
5492  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5493  *
5494  * \sa TV_VSCALE_INT_MASK
5495  */
5496 # define TV_VSCALE_FRAC_MASK		0x00007fff
5497 # define TV_VSCALE_FRAC_SHIFT		0
5498 
5499 #define TV_FILTER_CTL_3		_MMIO(0x68088)
5500 /*
5501  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5502  *
5503  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5504  *
5505  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5506  */
5507 # define TV_VSCALE_IP_INT_MASK		0x00038000
5508 # define TV_VSCALE_IP_INT_SHIFT		15
5509 /*
5510  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5511  *
5512  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5513  *
5514  * \sa TV_VSCALE_IP_INT_MASK
5515  */
5516 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
5517 # define TV_VSCALE_IP_FRAC_SHIFT		0
5518 
5519 #define TV_CC_CONTROL		_MMIO(0x68090)
5520 # define TV_CC_ENABLE			(1 << 31)
5521 /*
5522  * Specifies which field to send the CC data in.
5523  *
5524  * CC data is usually sent in field 0.
5525  */
5526 # define TV_CC_FID_MASK			(1 << 27)
5527 # define TV_CC_FID_SHIFT		27
5528 /* Sets the horizontal position of the CC data.  Usually 135. */
5529 # define TV_CC_HOFF_MASK		0x03ff0000
5530 # define TV_CC_HOFF_SHIFT		16
5531 /* Sets the vertical position of the CC data.  Usually 21 */
5532 # define TV_CC_LINE_MASK		0x0000003f
5533 # define TV_CC_LINE_SHIFT		0
5534 
5535 #define TV_CC_DATA		_MMIO(0x68094)
5536 # define TV_CC_RDY			(1 << 31)
5537 /* Second word of CC data to be transmitted. */
5538 # define TV_CC_DATA_2_MASK		0x007f0000
5539 # define TV_CC_DATA_2_SHIFT		16
5540 /* First word of CC data to be transmitted. */
5541 # define TV_CC_DATA_1_MASK		0x0000007f
5542 # define TV_CC_DATA_1_SHIFT		0
5543 
5544 #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
5545 #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
5546 #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
5547 #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
5548 
5549 /* Display Port */
5550 #define DP_A			_MMIO(0x64000) /* eDP */
5551 #define DP_B			_MMIO(0x64100)
5552 #define DP_C			_MMIO(0x64200)
5553 #define DP_D			_MMIO(0x64300)
5554 
5555 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
5556 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
5557 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
5558 
5559 #define   DP_PORT_EN			(1 << 31)
5560 #define   DP_PIPE_SEL_SHIFT		30
5561 #define   DP_PIPE_SEL_MASK		(1 << 30)
5562 #define   DP_PIPE_SEL(pipe)		((pipe) << 30)
5563 #define   DP_PIPE_SEL_SHIFT_IVB		29
5564 #define   DP_PIPE_SEL_MASK_IVB		(3 << 29)
5565 #define   DP_PIPE_SEL_IVB(pipe)		((pipe) << 29)
5566 #define   DP_PIPE_SEL_SHIFT_CHV		16
5567 #define   DP_PIPE_SEL_MASK_CHV		(3 << 16)
5568 #define   DP_PIPE_SEL_CHV(pipe)		((pipe) << 16)
5569 
5570 /* Link training mode - select a suitable mode for each stage */
5571 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
5572 #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
5573 #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
5574 #define   DP_LINK_TRAIN_OFF		(3 << 28)
5575 #define   DP_LINK_TRAIN_MASK		(3 << 28)
5576 #define   DP_LINK_TRAIN_SHIFT		28
5577 
5578 /* CPT Link training mode */
5579 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
5580 #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
5581 #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
5582 #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
5583 #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
5584 #define   DP_LINK_TRAIN_SHIFT_CPT	8
5585 
5586 /* Signal voltages. These are mostly controlled by the other end */
5587 #define   DP_VOLTAGE_0_4		(0 << 25)
5588 #define   DP_VOLTAGE_0_6		(1 << 25)
5589 #define   DP_VOLTAGE_0_8		(2 << 25)
5590 #define   DP_VOLTAGE_1_2		(3 << 25)
5591 #define   DP_VOLTAGE_MASK		(7 << 25)
5592 #define   DP_VOLTAGE_SHIFT		25
5593 
5594 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5595  * they want
5596  */
5597 #define   DP_PRE_EMPHASIS_0		(0 << 22)
5598 #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
5599 #define   DP_PRE_EMPHASIS_6		(2 << 22)
5600 #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
5601 #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
5602 #define   DP_PRE_EMPHASIS_SHIFT		22
5603 
5604 /* How many wires to use. I guess 3 was too hard */
5605 #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
5606 #define   DP_PORT_WIDTH_MASK		(7 << 19)
5607 #define   DP_PORT_WIDTH_SHIFT		19
5608 
5609 /* Mystic DPCD version 1.1 special mode */
5610 #define   DP_ENHANCED_FRAMING		(1 << 18)
5611 
5612 /* eDP */
5613 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
5614 #define   DP_PLL_FREQ_162MHZ		(1 << 16)
5615 #define   DP_PLL_FREQ_MASK		(3 << 16)
5616 
5617 /* locked once port is enabled */
5618 #define   DP_PORT_REVERSAL		(1 << 15)
5619 
5620 /* eDP */
5621 #define   DP_PLL_ENABLE			(1 << 14)
5622 
5623 /* sends the clock on lane 15 of the PEG for debug */
5624 #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
5625 
5626 #define   DP_SCRAMBLING_DISABLE		(1 << 12)
5627 #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
5628 
5629 /* limit RGB values to avoid confusing TVs */
5630 #define   DP_COLOR_RANGE_16_235		(1 << 8)
5631 
5632 /* Turn on the audio link */
5633 #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
5634 
5635 /* vs and hs sync polarity */
5636 #define   DP_SYNC_VS_HIGH		(1 << 4)
5637 #define   DP_SYNC_HS_HIGH		(1 << 3)
5638 
5639 /* A fantasy */
5640 #define   DP_DETECTED			(1 << 2)
5641 
5642 /* The aux channel provides a way to talk to the
5643  * signal sink for DDC etc. Max packet size supported
5644  * is 20 bytes in each direction, hence the 5 fixed
5645  * data registers
5646  */
5647 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5648 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5649 
5650 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5651 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5652 
5653 #define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5654 #define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5655 
5656 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
5657 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
5658 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
5659 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
5660 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
5661 #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
5662 #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
5663 #define   DP_AUX_CH_CTL_TIME_OUT_MAX	    (3 << 26) /* Varies per platform */
5664 #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
5665 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
5666 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5667 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
5668 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5669 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
5670 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
5671 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
5672 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
5673 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
5674 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
5675 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5676 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5677 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	(1 << 14)
5678 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	(1 << 13)
5679 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	(1 << 12)
5680 #define   DP_AUX_CH_CTL_TBT_IO			(1 << 11)
5681 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5682 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5683 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
5684 
5685 /*
5686  * Computing GMCH M and N values for the Display Port link
5687  *
5688  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5689  *
5690  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5691  *
5692  * The GMCH value is used internally
5693  *
5694  * bytes_per_pixel is the number of bytes coming out of the plane,
5695  * which is after the LUTs, so we want the bytes for our color format.
5696  * For our current usage, this is always 3, one byte for R, G and B.
5697  */
5698 #define _PIPEA_DATA_M_G4X	0x70050
5699 #define _PIPEB_DATA_M_G4X	0x71050
5700 
5701 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5702 #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
5703 #define  TU_SIZE_SHIFT		25
5704 #define  TU_SIZE_MASK           (0x3f << 25)
5705 
5706 #define  DATA_LINK_M_N_MASK	(0xffffff)
5707 #define  DATA_LINK_N_MAX	(0x800000)
5708 
5709 #define _PIPEA_DATA_N_G4X	0x70054
5710 #define _PIPEB_DATA_N_G4X	0x71054
5711 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
5712 
5713 /*
5714  * Computing Link M and N values for the Display Port link
5715  *
5716  * Link M / N = pixel_clock / ls_clk
5717  *
5718  * (the DP spec calls pixel_clock the 'strm_clk')
5719  *
5720  * The Link value is transmitted in the Main Stream
5721  * Attributes and VB-ID.
5722  */
5723 
5724 #define _PIPEA_LINK_M_G4X	0x70060
5725 #define _PIPEB_LINK_M_G4X	0x71060
5726 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
5727 
5728 #define _PIPEA_LINK_N_G4X	0x70064
5729 #define _PIPEB_LINK_N_G4X	0x71064
5730 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
5731 
5732 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5733 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5734 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5735 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5736 
5737 /* Display & cursor control */
5738 
5739 /* Pipe A */
5740 #define _PIPEADSL		0x70000
5741 #define   DSL_LINEMASK_GEN2	0x00000fff
5742 #define   DSL_LINEMASK_GEN3	0x00001fff
5743 #define _PIPEACONF		0x70008
5744 #define   PIPECONF_ENABLE	(1 << 31)
5745 #define   PIPECONF_DISABLE	0
5746 #define   PIPECONF_DOUBLE_WIDE	(1 << 30)
5747 #define   I965_PIPECONF_ACTIVE	(1 << 30)
5748 #define   PIPECONF_DSI_PLL_LOCKED	(1 << 29) /* vlv & pipe A only */
5749 #define   PIPECONF_FRAME_START_DELAY_MASK	(3 << 27) /* pre-hsw */
5750 #define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
5751 #define   PIPECONF_SINGLE_WIDE	0
5752 #define   PIPECONF_PIPE_UNLOCKED 0
5753 #define   PIPECONF_PIPE_LOCKED	(1 << 25)
5754 #define   PIPECONF_FORCE_BORDER	(1 << 25)
5755 #define   PIPECONF_GAMMA_MODE_MASK_I9XX	(1 << 24) /* gmch */
5756 #define   PIPECONF_GAMMA_MODE_MASK_ILK	(3 << 24) /* ilk-ivb */
5757 #define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
5758 #define   PIPECONF_GAMMA_MODE_10BIT	(1 << 24) /* gmch,ilk-ivb */
5759 #define   PIPECONF_GAMMA_MODE_12BIT	(2 << 24) /* ilk-ivb */
5760 #define   PIPECONF_GAMMA_MODE_SPLIT	(3 << 24) /* ivb */
5761 #define   PIPECONF_GAMMA_MODE(x)	((x) << 24) /* pass in GAMMA_MODE_MODE_* */
5762 #define   PIPECONF_GAMMA_MODE_SHIFT	24
5763 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
5764 #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
5765 /* Note that pre-gen3 does not support interlaced display directly. Panel
5766  * fitting must be disabled on pre-ilk for interlaced. */
5767 #define   PIPECONF_PROGRESSIVE			(0 << 21)
5768 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
5769 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
5770 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
5771 #define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
5772 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5773  * means panel fitter required, PF means progressive fetch, DBL means power
5774  * saving pixel doubling. */
5775 #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
5776 #define   PIPECONF_INTERLACED_ILK		(3 << 21)
5777 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
5778 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
5779 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
5780 #define   PIPECONF_EDP_RR_MODE_SWITCH		(1 << 20)
5781 #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
5782 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
5783 #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
5784 #define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
5785 #define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
5786 #define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
5787 #define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
5788 #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only */
5789 #define   PIPECONF_BPC_MASK	(0x7 << 5)
5790 #define   PIPECONF_8BPC		(0 << 5)
5791 #define   PIPECONF_10BPC	(1 << 5)
5792 #define   PIPECONF_6BPC		(2 << 5)
5793 #define   PIPECONF_12BPC	(3 << 5)
5794 #define   PIPECONF_DITHER_EN	(1 << 4)
5795 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5796 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
5797 #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5798 #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5799 #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5800 #define _PIPEASTAT		0x70024
5801 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
5802 #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
5803 #define   PIPE_CRC_ERROR_ENABLE			(1UL << 29)
5804 #define   PIPE_CRC_DONE_ENABLE			(1UL << 28)
5805 #define   PERF_COUNTER2_INTERRUPT_EN		(1UL << 27)
5806 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL << 27)
5807 #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL << 26)
5808 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL << 26)
5809 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL << 25)
5810 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL << 24)
5811 #define   PIPE_DPST_EVENT_ENABLE		(1UL << 23)
5812 #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL << 22)
5813 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL << 22)
5814 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL << 21)
5815 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL << 20)
5816 #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV	(1UL << 19)
5817 #define   PERF_COUNTER_INTERRUPT_EN		(1UL << 19)
5818 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL << 18) /* pre-965 */
5819 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL << 18) /* 965 or later */
5820 #define   PIPE_FRAMESTART_INTERRUPT_ENABLE	(1UL << 17)
5821 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL << 17)
5822 #define   PIPEA_HBLANK_INT_EN_VLV		(1UL << 16)
5823 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL << 16)
5824 #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV	(1UL << 15)
5825 #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV	(1UL << 14)
5826 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL << 13)
5827 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL << 12)
5828 #define   PERF_COUNTER2_INTERRUPT_STATUS	(1UL << 11)
5829 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL << 11)
5830 #define   PLANE_FLIP_DONE_INT_STATUS_VLV	(1UL << 10)
5831 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL << 10)
5832 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL << 9)
5833 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL << 8)
5834 #define   PIPE_DPST_EVENT_STATUS		(1UL << 7)
5835 #define   PIPE_A_PSR_STATUS_VLV			(1UL << 6)
5836 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL << 6)
5837 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL << 5)
5838 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL << 4)
5839 #define   PIPE_B_PSR_STATUS_VLV			(1UL << 3)
5840 #define   PERF_COUNTER_INTERRUPT_STATUS		(1UL << 3)
5841 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL << 2) /* pre-965 */
5842 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL << 2) /* 965 or later */
5843 #define   PIPE_FRAMESTART_INTERRUPT_STATUS	(1UL << 1)
5844 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)
5845 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
5846 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
5847 
5848 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
5849 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
5850 
5851 #define PIPE_A_OFFSET		0x70000
5852 #define PIPE_B_OFFSET		0x71000
5853 #define PIPE_C_OFFSET		0x72000
5854 #define PIPE_D_OFFSET		0x73000
5855 #define CHV_PIPE_C_OFFSET	0x74000
5856 /*
5857  * There's actually no pipe EDP. Some pipe registers have
5858  * simply shifted from the pipe to the transcoder, while
5859  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5860  * to access such registers in transcoder EDP.
5861  */
5862 #define PIPE_EDP_OFFSET	0x7f000
5863 
5864 /* ICL DSI 0 and 1 */
5865 #define PIPE_DSI0_OFFSET	0x7b000
5866 #define PIPE_DSI1_OFFSET	0x7b800
5867 
5868 #define PIPECONF(pipe)		_MMIO_PIPE2(pipe, _PIPEACONF)
5869 #define PIPEDSL(pipe)		_MMIO_PIPE2(pipe, _PIPEADSL)
5870 #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5871 #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5872 #define PIPESTAT(pipe)		_MMIO_PIPE2(pipe, _PIPEASTAT)
5873 
5874 #define  _PIPEAGCMAX           0x70010
5875 #define  _PIPEBGCMAX           0x71010
5876 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
5877 
5878 #define _PIPE_MISC_A			0x70030
5879 #define _PIPE_MISC_B			0x71030
5880 #define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */
5881 #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
5882 #define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
5883 #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
5884 #define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
5885 #define   PIPEMISC_DITHER_BPC_MASK	(7 << 5)
5886 #define   PIPEMISC_DITHER_8_BPC		(0 << 5)
5887 #define   PIPEMISC_DITHER_10_BPC	(1 << 5)
5888 #define   PIPEMISC_DITHER_6_BPC		(2 << 5)
5889 #define   PIPEMISC_DITHER_12_BPC	(3 << 5)
5890 #define   PIPEMISC_DITHER_ENABLE	(1 << 4)
5891 #define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
5892 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
5893 #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
5894 
5895 /* Skylake+ pipe bottom (background) color */
5896 #define _SKL_BOTTOM_COLOR_A		0x70034
5897 #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
5898 #define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
5899 #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5900 
5901 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
5902 #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
5903 #define   PIPEB_HLINE_INT_EN			(1 << 28)
5904 #define   PIPEB_VBLANK_INT_EN			(1 << 27)
5905 #define   SPRITED_FLIP_DONE_INT_EN		(1 << 26)
5906 #define   SPRITEC_FLIP_DONE_INT_EN		(1 << 25)
5907 #define   PLANEB_FLIP_DONE_INT_EN		(1 << 24)
5908 #define   PIPE_PSR_INT_EN			(1 << 22)
5909 #define   PIPEA_LINE_COMPARE_INT_EN		(1 << 21)
5910 #define   PIPEA_HLINE_INT_EN			(1 << 20)
5911 #define   PIPEA_VBLANK_INT_EN			(1 << 19)
5912 #define   SPRITEB_FLIP_DONE_INT_EN		(1 << 18)
5913 #define   SPRITEA_FLIP_DONE_INT_EN		(1 << 17)
5914 #define   PLANEA_FLIPDONE_INT_EN		(1 << 16)
5915 #define   PIPEC_LINE_COMPARE_INT_EN		(1 << 13)
5916 #define   PIPEC_HLINE_INT_EN			(1 << 12)
5917 #define   PIPEC_VBLANK_INT_EN			(1 << 11)
5918 #define   SPRITEF_FLIPDONE_INT_EN		(1 << 10)
5919 #define   SPRITEE_FLIPDONE_INT_EN		(1 << 9)
5920 #define   PLANEC_FLIPDONE_INT_EN		(1 << 8)
5921 
5922 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5923 #define   SPRITEF_INVALID_GTT_INT_EN		(1 << 27)
5924 #define   SPRITEE_INVALID_GTT_INT_EN		(1 << 26)
5925 #define   PLANEC_INVALID_GTT_INT_EN		(1 << 25)
5926 #define   CURSORC_INVALID_GTT_INT_EN		(1 << 24)
5927 #define   CURSORB_INVALID_GTT_INT_EN		(1 << 23)
5928 #define   CURSORA_INVALID_GTT_INT_EN		(1 << 22)
5929 #define   SPRITED_INVALID_GTT_INT_EN		(1 << 21)
5930 #define   SPRITEC_INVALID_GTT_INT_EN		(1 << 20)
5931 #define   PLANEB_INVALID_GTT_INT_EN		(1 << 19)
5932 #define   SPRITEB_INVALID_GTT_INT_EN		(1 << 18)
5933 #define   SPRITEA_INVALID_GTT_INT_EN		(1 << 17)
5934 #define   PLANEA_INVALID_GTT_INT_EN		(1 << 16)
5935 #define   DPINVGTT_EN_MASK			0xff0000
5936 #define   DPINVGTT_EN_MASK_CHV			0xfff0000
5937 #define   SPRITEF_INVALID_GTT_STATUS		(1 << 11)
5938 #define   SPRITEE_INVALID_GTT_STATUS		(1 << 10)
5939 #define   PLANEC_INVALID_GTT_STATUS		(1 << 9)
5940 #define   CURSORC_INVALID_GTT_STATUS		(1 << 8)
5941 #define   CURSORB_INVALID_GTT_STATUS		(1 << 7)
5942 #define   CURSORA_INVALID_GTT_STATUS		(1 << 6)
5943 #define   SPRITED_INVALID_GTT_STATUS		(1 << 5)
5944 #define   SPRITEC_INVALID_GTT_STATUS		(1 << 4)
5945 #define   PLANEB_INVALID_GTT_STATUS		(1 << 3)
5946 #define   SPRITEB_INVALID_GTT_STATUS		(1 << 2)
5947 #define   SPRITEA_INVALID_GTT_STATUS		(1 << 1)
5948 #define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
5949 #define   DPINVGTT_STATUS_MASK			0xff
5950 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
5951 
5952 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5953 #define   DSPARB_CSTART_MASK	(0x7f << 7)
5954 #define   DSPARB_CSTART_SHIFT	7
5955 #define   DSPARB_BSTART_MASK	(0x7f)
5956 #define   DSPARB_BSTART_SHIFT	0
5957 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
5958 #define   DSPARB_AEND_SHIFT	0
5959 #define   DSPARB_SPRITEA_SHIFT_VLV	0
5960 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
5961 #define   DSPARB_SPRITEB_SHIFT_VLV	8
5962 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
5963 #define   DSPARB_SPRITEC_SHIFT_VLV	16
5964 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
5965 #define   DSPARB_SPRITED_SHIFT_VLV	24
5966 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
5967 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5968 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
5969 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
5970 #define   DSPARB_SPRITEB_HI_SHIFT_VLV	4
5971 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
5972 #define   DSPARB_SPRITEC_HI_SHIFT_VLV	8
5973 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
5974 #define   DSPARB_SPRITED_HI_SHIFT_VLV	12
5975 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
5976 #define   DSPARB_SPRITEE_HI_SHIFT_VLV	16
5977 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
5978 #define   DSPARB_SPRITEF_HI_SHIFT_VLV	20
5979 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
5980 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5981 #define   DSPARB_SPRITEE_SHIFT_VLV	0
5982 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
5983 #define   DSPARB_SPRITEF_SHIFT_VLV	8
5984 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
5985 
5986 /* pnv/gen4/g4x/vlv/chv */
5987 #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5988 #define   DSPFW_SR_SHIFT		23
5989 #define   DSPFW_SR_MASK			(0x1ff << 23)
5990 #define   DSPFW_CURSORB_SHIFT		16
5991 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
5992 #define   DSPFW_PLANEB_SHIFT		8
5993 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
5994 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
5995 #define   DSPFW_PLANEA_SHIFT		0
5996 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
5997 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
5998 #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5999 #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
6000 #define   DSPFW_FBC_SR_SHIFT		28
6001 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
6002 #define   DSPFW_FBC_HPLL_SR_SHIFT	24
6003 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
6004 #define   DSPFW_SPRITEB_SHIFT		(16)
6005 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
6006 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
6007 #define   DSPFW_CURSORA_SHIFT		8
6008 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
6009 #define   DSPFW_PLANEC_OLD_SHIFT	0
6010 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
6011 #define   DSPFW_SPRITEA_SHIFT		0
6012 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
6013 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
6014 #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6015 #define   DSPFW_HPLL_SR_EN		(1 << 31)
6016 #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
6017 #define   DSPFW_CURSOR_SR_SHIFT		24
6018 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
6019 #define   DSPFW_HPLL_CURSOR_SHIFT	16
6020 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
6021 #define   DSPFW_HPLL_SR_SHIFT		0
6022 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
6023 
6024 /* vlv/chv */
6025 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
6026 #define   DSPFW_SPRITEB_WM1_SHIFT	16
6027 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
6028 #define   DSPFW_CURSORA_WM1_SHIFT	8
6029 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
6030 #define   DSPFW_SPRITEA_WM1_SHIFT	0
6031 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
6032 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
6033 #define   DSPFW_PLANEB_WM1_SHIFT	24
6034 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
6035 #define   DSPFW_PLANEA_WM1_SHIFT	16
6036 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
6037 #define   DSPFW_CURSORB_WM1_SHIFT	8
6038 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
6039 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
6040 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
6041 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
6042 #define   DSPFW_SR_WM1_SHIFT		0
6043 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
6044 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
6045 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
6046 #define   DSPFW_SPRITED_WM1_SHIFT	24
6047 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
6048 #define   DSPFW_SPRITED_SHIFT		16
6049 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
6050 #define   DSPFW_SPRITEC_WM1_SHIFT	8
6051 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
6052 #define   DSPFW_SPRITEC_SHIFT		0
6053 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
6054 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
6055 #define   DSPFW_SPRITEF_WM1_SHIFT	24
6056 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
6057 #define   DSPFW_SPRITEF_SHIFT		16
6058 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
6059 #define   DSPFW_SPRITEE_WM1_SHIFT	8
6060 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
6061 #define   DSPFW_SPRITEE_SHIFT		0
6062 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
6063 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
6064 #define   DSPFW_PLANEC_WM1_SHIFT	24
6065 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
6066 #define   DSPFW_PLANEC_SHIFT		16
6067 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
6068 #define   DSPFW_CURSORC_WM1_SHIFT	8
6069 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
6070 #define   DSPFW_CURSORC_SHIFT		0
6071 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
6072 
6073 /* vlv/chv high order bits */
6074 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
6075 #define   DSPFW_SR_HI_SHIFT		24
6076 #define   DSPFW_SR_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
6077 #define   DSPFW_SPRITEF_HI_SHIFT	23
6078 #define   DSPFW_SPRITEF_HI_MASK		(1 << 23)
6079 #define   DSPFW_SPRITEE_HI_SHIFT	22
6080 #define   DSPFW_SPRITEE_HI_MASK		(1 << 22)
6081 #define   DSPFW_PLANEC_HI_SHIFT		21
6082 #define   DSPFW_PLANEC_HI_MASK		(1 << 21)
6083 #define   DSPFW_SPRITED_HI_SHIFT	20
6084 #define   DSPFW_SPRITED_HI_MASK		(1 << 20)
6085 #define   DSPFW_SPRITEC_HI_SHIFT	16
6086 #define   DSPFW_SPRITEC_HI_MASK		(1 << 16)
6087 #define   DSPFW_PLANEB_HI_SHIFT		12
6088 #define   DSPFW_PLANEB_HI_MASK		(1 << 12)
6089 #define   DSPFW_SPRITEB_HI_SHIFT	8
6090 #define   DSPFW_SPRITEB_HI_MASK		(1 << 8)
6091 #define   DSPFW_SPRITEA_HI_SHIFT	4
6092 #define   DSPFW_SPRITEA_HI_MASK		(1 << 4)
6093 #define   DSPFW_PLANEA_HI_SHIFT		0
6094 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
6095 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
6096 #define   DSPFW_SR_WM1_HI_SHIFT		24
6097 #define   DSPFW_SR_WM1_HI_MASK		(3 << 24) /* 2 bits for chv, 1 for vlv */
6098 #define   DSPFW_SPRITEF_WM1_HI_SHIFT	23
6099 #define   DSPFW_SPRITEF_WM1_HI_MASK	(1 << 23)
6100 #define   DSPFW_SPRITEE_WM1_HI_SHIFT	22
6101 #define   DSPFW_SPRITEE_WM1_HI_MASK	(1 << 22)
6102 #define   DSPFW_PLANEC_WM1_HI_SHIFT	21
6103 #define   DSPFW_PLANEC_WM1_HI_MASK	(1 << 21)
6104 #define   DSPFW_SPRITED_WM1_HI_SHIFT	20
6105 #define   DSPFW_SPRITED_WM1_HI_MASK	(1 << 20)
6106 #define   DSPFW_SPRITEC_WM1_HI_SHIFT	16
6107 #define   DSPFW_SPRITEC_WM1_HI_MASK	(1 << 16)
6108 #define   DSPFW_PLANEB_WM1_HI_SHIFT	12
6109 #define   DSPFW_PLANEB_WM1_HI_MASK	(1 << 12)
6110 #define   DSPFW_SPRITEB_WM1_HI_SHIFT	8
6111 #define   DSPFW_SPRITEB_WM1_HI_MASK	(1 << 8)
6112 #define   DSPFW_SPRITEA_WM1_HI_SHIFT	4
6113 #define   DSPFW_SPRITEA_WM1_HI_MASK	(1 << 4)
6114 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
6115 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
6116 
6117 /* drain latency register values*/
6118 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6119 #define DDL_CURSOR_SHIFT		24
6120 #define DDL_SPRITE_SHIFT(sprite)	(8 + 8 * (sprite))
6121 #define DDL_PLANE_SHIFT			0
6122 #define DDL_PRECISION_HIGH		(1 << 7)
6123 #define DDL_PRECISION_LOW		(0 << 7)
6124 #define DRAIN_LATENCY_MASK		0x7f
6125 
6126 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
6127 #define  CBR_PND_DEADLINE_DISABLE	(1 << 31)
6128 #define  CBR_PWM_CLOCK_MUX_SELECT	(1 << 30)
6129 
6130 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
6131 #define  CBR_DPLLBMD_PIPE(pipe)		(1 << (7 + (pipe) * 11)) /* pipes B and C */
6132 
6133 /* FIFO watermark sizes etc */
6134 #define G4X_FIFO_LINE_SIZE	64
6135 #define I915_FIFO_LINE_SIZE	64
6136 #define I830_FIFO_LINE_SIZE	32
6137 
6138 #define VALLEYVIEW_FIFO_SIZE	255
6139 #define G4X_FIFO_SIZE		127
6140 #define I965_FIFO_SIZE		512
6141 #define I945_FIFO_SIZE		127
6142 #define I915_FIFO_SIZE		95
6143 #define I855GM_FIFO_SIZE	127 /* In cachelines */
6144 #define I830_FIFO_SIZE		95
6145 
6146 #define VALLEYVIEW_MAX_WM	0xff
6147 #define G4X_MAX_WM		0x3f
6148 #define I915_MAX_WM		0x3f
6149 
6150 #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
6151 #define PINEVIEW_FIFO_LINE_SIZE	64
6152 #define PINEVIEW_MAX_WM		0x1ff
6153 #define PINEVIEW_DFT_WM		0x3f
6154 #define PINEVIEW_DFT_HPLLOFF_WM	0
6155 #define PINEVIEW_GUARD_WM		10
6156 #define PINEVIEW_CURSOR_FIFO		64
6157 #define PINEVIEW_CURSOR_MAX_WM	0x3f
6158 #define PINEVIEW_CURSOR_DFT_WM	0
6159 #define PINEVIEW_CURSOR_GUARD_WM	5
6160 
6161 #define VALLEYVIEW_CURSOR_MAX_WM 64
6162 #define I965_CURSOR_FIFO	64
6163 #define I965_CURSOR_MAX_WM	32
6164 #define I965_CURSOR_DFT_WM	8
6165 
6166 /* Watermark register definitions for SKL */
6167 #define _CUR_WM_A_0		0x70140
6168 #define _CUR_WM_B_0		0x71140
6169 #define _PLANE_WM_1_A_0		0x70240
6170 #define _PLANE_WM_1_B_0		0x71240
6171 #define _PLANE_WM_2_A_0		0x70340
6172 #define _PLANE_WM_2_B_0		0x71340
6173 #define _PLANE_WM_TRANS_1_A_0	0x70268
6174 #define _PLANE_WM_TRANS_1_B_0	0x71268
6175 #define _PLANE_WM_TRANS_2_A_0	0x70368
6176 #define _PLANE_WM_TRANS_2_B_0	0x71368
6177 #define _CUR_WM_TRANS_A_0	0x70168
6178 #define _CUR_WM_TRANS_B_0	0x71168
6179 #define   PLANE_WM_EN		(1 << 31)
6180 #define   PLANE_WM_IGNORE_LINES	(1 << 30)
6181 #define   PLANE_WM_LINES_SHIFT	14
6182 #define   PLANE_WM_LINES_MASK	0x1f
6183 #define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */
6184 
6185 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6186 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6187 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6188 
6189 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6190 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6191 #define _PLANE_WM_BASE(pipe, plane)	\
6192 			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6193 #define PLANE_WM(pipe, plane, level)	\
6194 			_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6195 #define _PLANE_WM_TRANS_1(pipe)	\
6196 			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6197 #define _PLANE_WM_TRANS_2(pipe)	\
6198 			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6199 #define PLANE_WM_TRANS(pipe, plane)	\
6200 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6201 
6202 /* define the Watermark register on Ironlake */
6203 #define WM0_PIPEA_ILK		_MMIO(0x45100)
6204 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
6205 #define  WM0_PIPE_PLANE_SHIFT	16
6206 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
6207 #define  WM0_PIPE_SPRITE_SHIFT	8
6208 #define  WM0_PIPE_CURSOR_MASK	(0xff)
6209 
6210 #define WM0_PIPEB_ILK		_MMIO(0x45104)
6211 #define WM0_PIPEC_IVB		_MMIO(0x45200)
6212 #define WM1_LP_ILK		_MMIO(0x45108)
6213 #define  WM1_LP_SR_EN		(1 << 31)
6214 #define  WM1_LP_LATENCY_SHIFT	24
6215 #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
6216 #define  WM1_LP_FBC_MASK	(0xf << 20)
6217 #define  WM1_LP_FBC_SHIFT	20
6218 #define  WM1_LP_FBC_SHIFT_BDW	19
6219 #define  WM1_LP_SR_MASK		(0x7ff << 8)
6220 #define  WM1_LP_SR_SHIFT	8
6221 #define  WM1_LP_CURSOR_MASK	(0xff)
6222 #define WM2_LP_ILK		_MMIO(0x4510c)
6223 #define  WM2_LP_EN		(1 << 31)
6224 #define WM3_LP_ILK		_MMIO(0x45110)
6225 #define  WM3_LP_EN		(1 << 31)
6226 #define WM1S_LP_ILK		_MMIO(0x45120)
6227 #define WM2S_LP_IVB		_MMIO(0x45124)
6228 #define WM3S_LP_IVB		_MMIO(0x45128)
6229 #define  WM1S_LP_EN		(1 << 31)
6230 
6231 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6232 	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6233 	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6234 
6235 /* Memory latency timer register */
6236 #define MLTR_ILK		_MMIO(0x11222)
6237 #define  MLTR_WM1_SHIFT		0
6238 #define  MLTR_WM2_SHIFT		8
6239 /* the unit of memory self-refresh latency time is 0.5us */
6240 #define  ILK_SRLT_MASK		0x3f
6241 
6242 
6243 /* the address where we get all kinds of latency value */
6244 #define SSKPD			_MMIO(0x5d10)
6245 #define SSKPD_WM_MASK		0x3f
6246 #define SSKPD_WM0_SHIFT		0
6247 #define SSKPD_WM1_SHIFT		8
6248 #define SSKPD_WM2_SHIFT		16
6249 #define SSKPD_WM3_SHIFT		24
6250 
6251 /*
6252  * The two pipe frame counter registers are not synchronized, so
6253  * reading a stable value is somewhat tricky. The following code
6254  * should work:
6255  *
6256  *  do {
6257  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6258  *             PIPE_FRAME_HIGH_SHIFT;
6259  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6260  *             PIPE_FRAME_LOW_SHIFT);
6261  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6262  *             PIPE_FRAME_HIGH_SHIFT);
6263  *  } while (high1 != high2);
6264  *  frame = (high1 << 8) | low1;
6265  */
6266 #define _PIPEAFRAMEHIGH          0x70040
6267 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6268 #define   PIPE_FRAME_HIGH_SHIFT   0
6269 #define _PIPEAFRAMEPIXEL         0x70044
6270 #define   PIPE_FRAME_LOW_MASK     0xff000000
6271 #define   PIPE_FRAME_LOW_SHIFT    24
6272 #define   PIPE_PIXEL_MASK         0x00ffffff
6273 #define   PIPE_PIXEL_SHIFT        0
6274 /* GM45+ just has to be different */
6275 #define _PIPEA_FRMCOUNT_G4X	0x70040
6276 #define _PIPEA_FLIPCOUNT_G4X	0x70044
6277 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6278 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6279 
6280 /* Cursor A & B regs */
6281 #define _CURACNTR		0x70080
6282 /* Old style CUR*CNTR flags (desktop 8xx) */
6283 #define   CURSOR_ENABLE		0x80000000
6284 #define   CURSOR_GAMMA_ENABLE	0x40000000
6285 #define   CURSOR_STRIDE_SHIFT	28
6286 #define   CURSOR_STRIDE(x)	((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6287 #define   CURSOR_FORMAT_SHIFT	24
6288 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
6289 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
6290 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
6291 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
6292 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
6293 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
6294 /* New style CUR*CNTR flags */
6295 #define   MCURSOR_MODE		0x27
6296 #define   MCURSOR_MODE_DISABLE   0x00
6297 #define   MCURSOR_MODE_128_32B_AX 0x02
6298 #define   MCURSOR_MODE_256_32B_AX 0x03
6299 #define   MCURSOR_MODE_64_32B_AX 0x07
6300 #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6301 #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6302 #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6303 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
6304 #define   MCURSOR_PIPE_SELECT_SHIFT	28
6305 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
6306 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
6307 #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6308 #define   MCURSOR_ROTATE_180	(1 << 15)
6309 #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
6310 #define _CURABASE		0x70084
6311 #define _CURAPOS		0x70088
6312 #define   CURSOR_POS_MASK       0x007FF
6313 #define   CURSOR_POS_SIGN       0x8000
6314 #define   CURSOR_X_SHIFT        0
6315 #define   CURSOR_Y_SHIFT        16
6316 #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
6317 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
6318 #define   CUR_FBC_CTL_EN	(1 << 31)
6319 #define _CURASURFLIVE		0x700ac /* g4x+ */
6320 #define _CURBCNTR		0x700c0
6321 #define _CURBBASE		0x700c4
6322 #define _CURBPOS		0x700c8
6323 
6324 #define _CURBCNTR_IVB		0x71080
6325 #define _CURBBASE_IVB		0x71084
6326 #define _CURBPOS_IVB		0x71088
6327 
6328 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6329 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6330 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6331 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6332 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6333 
6334 #define CURSOR_A_OFFSET 0x70080
6335 #define CURSOR_B_OFFSET 0x700c0
6336 #define CHV_CURSOR_C_OFFSET 0x700e0
6337 #define IVB_CURSOR_B_OFFSET 0x71080
6338 #define IVB_CURSOR_C_OFFSET 0x72080
6339 #define TGL_CURSOR_D_OFFSET 0x73080
6340 
6341 /* Display A control */
6342 #define _DSPACNTR				0x70180
6343 #define   DISPLAY_PLANE_ENABLE			(1 << 31)
6344 #define   DISPLAY_PLANE_DISABLE			0
6345 #define   DISPPLANE_GAMMA_ENABLE		(1 << 30)
6346 #define   DISPPLANE_GAMMA_DISABLE		0
6347 #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
6348 #define   DISPPLANE_YUV422			(0x0 << 26)
6349 #define   DISPPLANE_8BPP			(0x2 << 26)
6350 #define   DISPPLANE_BGRA555			(0x3 << 26)
6351 #define   DISPPLANE_BGRX555			(0x4 << 26)
6352 #define   DISPPLANE_BGRX565			(0x5 << 26)
6353 #define   DISPPLANE_BGRX888			(0x6 << 26)
6354 #define   DISPPLANE_BGRA888			(0x7 << 26)
6355 #define   DISPPLANE_RGBX101010			(0x8 << 26)
6356 #define   DISPPLANE_RGBA101010			(0x9 << 26)
6357 #define   DISPPLANE_BGRX101010			(0xa << 26)
6358 #define   DISPPLANE_BGRA101010			(0xb << 26)
6359 #define   DISPPLANE_RGBX161616			(0xc << 26)
6360 #define   DISPPLANE_RGBX888			(0xe << 26)
6361 #define   DISPPLANE_RGBA888			(0xf << 26)
6362 #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
6363 #define   DISPPLANE_STEREO_DISABLE		0
6364 #define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
6365 #define   DISPPLANE_SEL_PIPE_SHIFT		24
6366 #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
6367 #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6368 #define   DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
6369 #define   DISPPLANE_SRC_KEY_DISABLE		0
6370 #define   DISPPLANE_LINE_DOUBLE			(1 << 20)
6371 #define   DISPPLANE_NO_LINE_DOUBLE		0
6372 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
6373 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
6374 #define   DISPPLANE_ALPHA_PREMULTIPLY		(1 << 16) /* CHV pipe B */
6375 #define   DISPPLANE_ROTATE_180			(1 << 15)
6376 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1 << 14) /* Ironlake */
6377 #define   DISPPLANE_TILED			(1 << 10)
6378 #define   DISPPLANE_MIRROR			(1 << 8) /* CHV pipe B */
6379 #define _DSPAADDR				0x70184
6380 #define _DSPASTRIDE				0x70188
6381 #define _DSPAPOS				0x7018C /* reserved */
6382 #define _DSPASIZE				0x70190
6383 #define _DSPASURF				0x7019C /* 965+ only */
6384 #define _DSPATILEOFF				0x701A4 /* 965+ only */
6385 #define _DSPAOFFSET				0x701A4 /* HSW */
6386 #define _DSPASURFLIVE				0x701AC
6387 #define _DSPAGAMC				0x701E0
6388 
6389 #define DSPCNTR(plane)		_MMIO_PIPE2(plane, _DSPACNTR)
6390 #define DSPADDR(plane)		_MMIO_PIPE2(plane, _DSPAADDR)
6391 #define DSPSTRIDE(plane)	_MMIO_PIPE2(plane, _DSPASTRIDE)
6392 #define DSPPOS(plane)		_MMIO_PIPE2(plane, _DSPAPOS)
6393 #define DSPSIZE(plane)		_MMIO_PIPE2(plane, _DSPASIZE)
6394 #define DSPSURF(plane)		_MMIO_PIPE2(plane, _DSPASURF)
6395 #define DSPTILEOFF(plane)	_MMIO_PIPE2(plane, _DSPATILEOFF)
6396 #define DSPLINOFF(plane)	DSPADDR(plane)
6397 #define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
6398 #define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
6399 #define DSPGAMC(plane, i)	_MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6400 
6401 /* CHV pipe B blender and primary plane */
6402 #define _CHV_BLEND_A		0x60a00
6403 #define   CHV_BLEND_LEGACY		(0 << 30)
6404 #define   CHV_BLEND_ANDROID		(1 << 30)
6405 #define   CHV_BLEND_MPO			(2 << 30)
6406 #define   CHV_BLEND_MASK		(3 << 30)
6407 #define _CHV_CANVAS_A		0x60a04
6408 #define _PRIMPOS_A		0x60a08
6409 #define _PRIMSIZE_A		0x60a0c
6410 #define _PRIMCNSTALPHA_A	0x60a10
6411 #define   PRIM_CONST_ALPHA_ENABLE	(1 << 31)
6412 
6413 #define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
6414 #define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6415 #define PRIMPOS(plane)		_MMIO_TRANS2(plane, _PRIMPOS_A)
6416 #define PRIMSIZE(plane)		_MMIO_TRANS2(plane, _PRIMSIZE_A)
6417 #define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6418 
6419 /* Display/Sprite base address macros */
6420 #define DISP_BASEADDR_MASK	(0xfffff000)
6421 #define I915_LO_DISPBASE(val)	((val) & ~DISP_BASEADDR_MASK)
6422 #define I915_HI_DISPBASE(val)	((val) & DISP_BASEADDR_MASK)
6423 
6424 /*
6425  * VBIOS flags
6426  * gen2:
6427  * [00:06] alm,mgm
6428  * [10:16] all
6429  * [30:32] alm,mgm
6430  * gen3+:
6431  * [00:0f] all
6432  * [10:1f] all
6433  * [30:32] all
6434  */
6435 #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6436 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6437 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6438 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
6439 
6440 /* Pipe B */
6441 #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6442 #define _PIPEBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6443 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6444 #define _PIPEBFRAMEHIGH		0x71040
6445 #define _PIPEBFRAMEPIXEL	0x71044
6446 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6447 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6448 
6449 
6450 /* Display B control */
6451 #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6452 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
6453 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
6454 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
6455 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
6456 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6457 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6458 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6459 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6460 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6461 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6462 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6463 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6464 
6465 /* ICL DSI 0 and 1 */
6466 #define _PIPEDSI0CONF		0x7b008
6467 #define _PIPEDSI1CONF		0x7b808
6468 
6469 /* Sprite A control */
6470 #define _DVSACNTR		0x72180
6471 #define   DVS_ENABLE		(1 << 31)
6472 #define   DVS_GAMMA_ENABLE	(1 << 30)
6473 #define   DVS_YUV_RANGE_CORRECTION_DISABLE	(1 << 27)
6474 #define   DVS_PIXFORMAT_MASK	(3 << 25)
6475 #define   DVS_FORMAT_YUV422	(0 << 25)
6476 #define   DVS_FORMAT_RGBX101010	(1 << 25)
6477 #define   DVS_FORMAT_RGBX888	(2 << 25)
6478 #define   DVS_FORMAT_RGBX161616	(3 << 25)
6479 #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
6480 #define   DVS_SOURCE_KEY	(1 << 22)
6481 #define   DVS_RGB_ORDER_XBGR	(1 << 20)
6482 #define   DVS_YUV_FORMAT_BT709	(1 << 18)
6483 #define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6484 #define   DVS_YUV_ORDER_YUYV	(0 << 16)
6485 #define   DVS_YUV_ORDER_UYVY	(1 << 16)
6486 #define   DVS_YUV_ORDER_YVYU	(2 << 16)
6487 #define   DVS_YUV_ORDER_VYUY	(3 << 16)
6488 #define   DVS_ROTATE_180	(1 << 15)
6489 #define   DVS_DEST_KEY		(1 << 2)
6490 #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
6491 #define   DVS_TILED		(1 << 10)
6492 #define _DVSALINOFF		0x72184
6493 #define _DVSASTRIDE		0x72188
6494 #define _DVSAPOS		0x7218c
6495 #define _DVSASIZE		0x72190
6496 #define _DVSAKEYVAL		0x72194
6497 #define _DVSAKEYMSK		0x72198
6498 #define _DVSASURF		0x7219c
6499 #define _DVSAKEYMAXVAL		0x721a0
6500 #define _DVSATILEOFF		0x721a4
6501 #define _DVSASURFLIVE		0x721ac
6502 #define _DVSAGAMC_G4X		0x721e0 /* g4x */
6503 #define _DVSASCALE		0x72204
6504 #define   DVS_SCALE_ENABLE	(1 << 31)
6505 #define   DVS_FILTER_MASK	(3 << 29)
6506 #define   DVS_FILTER_MEDIUM	(0 << 29)
6507 #define   DVS_FILTER_ENHANCING	(1 << 29)
6508 #define   DVS_FILTER_SOFTENING	(2 << 29)
6509 #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6510 #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6511 #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
6512 #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
6513 
6514 #define _DVSBCNTR		0x73180
6515 #define _DVSBLINOFF		0x73184
6516 #define _DVSBSTRIDE		0x73188
6517 #define _DVSBPOS		0x7318c
6518 #define _DVSBSIZE		0x73190
6519 #define _DVSBKEYVAL		0x73194
6520 #define _DVSBKEYMSK		0x73198
6521 #define _DVSBSURF		0x7319c
6522 #define _DVSBKEYMAXVAL		0x731a0
6523 #define _DVSBTILEOFF		0x731a4
6524 #define _DVSBSURFLIVE		0x731ac
6525 #define _DVSBGAMC_G4X		0x731e0 /* g4x */
6526 #define _DVSBSCALE		0x73204
6527 #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
6528 #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
6529 
6530 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6531 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6532 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6533 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6534 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6535 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6536 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6537 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6538 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6539 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6540 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6541 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6542 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6543 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6544 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6545 
6546 #define _SPRA_CTL		0x70280
6547 #define   SPRITE_ENABLE			(1 << 31)
6548 #define   SPRITE_GAMMA_ENABLE		(1 << 30)
6549 #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6550 #define   SPRITE_PIXFORMAT_MASK		(7 << 25)
6551 #define   SPRITE_FORMAT_YUV422		(0 << 25)
6552 #define   SPRITE_FORMAT_RGBX101010	(1 << 25)
6553 #define   SPRITE_FORMAT_RGBX888		(2 << 25)
6554 #define   SPRITE_FORMAT_RGBX161616	(3 << 25)
6555 #define   SPRITE_FORMAT_YUV444		(4 << 25)
6556 #define   SPRITE_FORMAT_XR_BGR101010	(5 << 25) /* Extended range */
6557 #define   SPRITE_PIPE_CSC_ENABLE	(1 << 24)
6558 #define   SPRITE_SOURCE_KEY		(1 << 22)
6559 #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
6560 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
6561 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
6562 #define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
6563 #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
6564 #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
6565 #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
6566 #define   SPRITE_YUV_ORDER_VYUY		(3 << 16)
6567 #define   SPRITE_ROTATE_180		(1 << 15)
6568 #define   SPRITE_TRICKLE_FEED_DISABLE	(1 << 14)
6569 #define   SPRITE_INT_GAMMA_DISABLE	(1 << 13)
6570 #define   SPRITE_TILED			(1 << 10)
6571 #define   SPRITE_DEST_KEY		(1 << 2)
6572 #define _SPRA_LINOFF		0x70284
6573 #define _SPRA_STRIDE		0x70288
6574 #define _SPRA_POS		0x7028c
6575 #define _SPRA_SIZE		0x70290
6576 #define _SPRA_KEYVAL		0x70294
6577 #define _SPRA_KEYMSK		0x70298
6578 #define _SPRA_SURF		0x7029c
6579 #define _SPRA_KEYMAX		0x702a0
6580 #define _SPRA_TILEOFF		0x702a4
6581 #define _SPRA_OFFSET		0x702a4
6582 #define _SPRA_SURFLIVE		0x702ac
6583 #define _SPRA_SCALE		0x70304
6584 #define   SPRITE_SCALE_ENABLE	(1 << 31)
6585 #define   SPRITE_FILTER_MASK	(3 << 29)
6586 #define   SPRITE_FILTER_MEDIUM	(0 << 29)
6587 #define   SPRITE_FILTER_ENHANCING	(1 << 29)
6588 #define   SPRITE_FILTER_SOFTENING	(2 << 29)
6589 #define   SPRITE_VERTICAL_OFFSET_HALF	(1 << 28) /* must be enabled below */
6590 #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1 << 27)
6591 #define _SPRA_GAMC		0x70400
6592 #define _SPRA_GAMC16		0x70440
6593 #define _SPRA_GAMC17		0x7044c
6594 
6595 #define _SPRB_CTL		0x71280
6596 #define _SPRB_LINOFF		0x71284
6597 #define _SPRB_STRIDE		0x71288
6598 #define _SPRB_POS		0x7128c
6599 #define _SPRB_SIZE		0x71290
6600 #define _SPRB_KEYVAL		0x71294
6601 #define _SPRB_KEYMSK		0x71298
6602 #define _SPRB_SURF		0x7129c
6603 #define _SPRB_KEYMAX		0x712a0
6604 #define _SPRB_TILEOFF		0x712a4
6605 #define _SPRB_OFFSET		0x712a4
6606 #define _SPRB_SURFLIVE		0x712ac
6607 #define _SPRB_SCALE		0x71304
6608 #define _SPRB_GAMC		0x71400
6609 #define _SPRB_GAMC16		0x71440
6610 #define _SPRB_GAMC17		0x7144c
6611 
6612 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6613 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6614 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6615 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6616 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6617 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6618 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6619 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6620 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6621 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6622 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6623 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6624 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6625 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6626 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6627 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6628 
6629 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
6630 #define   SP_ENABLE			(1 << 31)
6631 #define   SP_GAMMA_ENABLE		(1 << 30)
6632 #define   SP_PIXFORMAT_MASK		(0xf << 26)
6633 #define   SP_FORMAT_YUV422		(0x0 << 26)
6634 #define   SP_FORMAT_8BPP		(0x2 << 26)
6635 #define   SP_FORMAT_BGR565		(0x5 << 26)
6636 #define   SP_FORMAT_BGRX8888		(0x6 << 26)
6637 #define   SP_FORMAT_BGRA8888		(0x7 << 26)
6638 #define   SP_FORMAT_RGBX1010102		(0x8 << 26)
6639 #define   SP_FORMAT_RGBA1010102		(0x9 << 26)
6640 #define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
6641 #define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
6642 #define   SP_FORMAT_RGBX8888		(0xe << 26)
6643 #define   SP_FORMAT_RGBA8888		(0xf << 26)
6644 #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
6645 #define   SP_SOURCE_KEY			(1 << 22)
6646 #define   SP_YUV_FORMAT_BT709		(1 << 18)
6647 #define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
6648 #define   SP_YUV_ORDER_YUYV		(0 << 16)
6649 #define   SP_YUV_ORDER_UYVY		(1 << 16)
6650 #define   SP_YUV_ORDER_YVYU		(2 << 16)
6651 #define   SP_YUV_ORDER_VYUY		(3 << 16)
6652 #define   SP_ROTATE_180			(1 << 15)
6653 #define   SP_TILED			(1 << 10)
6654 #define   SP_MIRROR			(1 << 8) /* CHV pipe B */
6655 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
6656 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
6657 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
6658 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
6659 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
6660 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
6661 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
6662 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
6663 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
6664 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
6665 #define   SP_CONST_ALPHA_ENABLE		(1 << 31)
6666 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
6667 #define   SP_CONTRAST(x)		((x) << 18) /* u3.6 */
6668 #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
6669 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
6670 #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
6671 #define   SP_SH_COS(x)			(x) /* u3.7 */
6672 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
6673 
6674 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
6675 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
6676 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
6677 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
6678 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
6679 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
6680 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
6681 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
6682 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
6683 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
6684 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
6685 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
6686 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
6687 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
6688 
6689 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6690 	_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6691 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6692 	_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6693 
6694 #define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6695 #define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6696 #define SPSTRIDE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6697 #define SPPOS(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6698 #define SPSIZE(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6699 #define SPKEYMINVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6700 #define SPKEYMSK(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6701 #define SPSURF(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6702 #define SPKEYMAXVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6703 #define SPTILEOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6704 #define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6705 #define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6706 #define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6707 #define SPGAMC(pipe, plane_id, i)	_MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6708 
6709 /*
6710  * CHV pipe B sprite CSC
6711  *
6712  * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
6713  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6714  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
6715  */
6716 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6717 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6718 
6719 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
6720 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
6721 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
6722 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
6723 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
6724 
6725 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6726 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
6727 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
6728 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
6729 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6730 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
6731 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
6732 
6733 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
6734 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
6735 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
6736 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
6737 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
6738 
6739 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6740 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
6741 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
6742 #define  SPCSC_OMAX(x)		((x) << 16) /* u10 */
6743 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
6744 
6745 /* Skylake plane registers */
6746 
6747 #define _PLANE_CTL_1_A				0x70180
6748 #define _PLANE_CTL_2_A				0x70280
6749 #define _PLANE_CTL_3_A				0x70380
6750 #define   PLANE_CTL_ENABLE			(1 << 31)
6751 #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
6752 #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6753 /*
6754  * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6755  * expanded to include bit 23 as well. However, the shift-24 based values
6756  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6757  */
6758 #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
6759 #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
6760 #define   PLANE_CTL_FORMAT_NV12			(1 << 24)
6761 #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
6762 #define   PLANE_CTL_FORMAT_P010			(3 << 24)
6763 #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
6764 #define   PLANE_CTL_FORMAT_P012			(5 << 24)
6765 #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
6766 #define   PLANE_CTL_FORMAT_P016			(7 << 24)
6767 #define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
6768 #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
6769 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
6770 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
6771 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
6772 #define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
6773 #define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
6774 #define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
6775 #define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
6776 #define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
6777 #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
6778 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
6779 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
6780 #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
6781 #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
6782 #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
6783 #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
6784 #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
6785 #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
6786 #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
6787 #define   PLANE_CTL_YUV422_UYVY			(1 << 16)
6788 #define   PLANE_CTL_YUV422_YVYU			(2 << 16)
6789 #define   PLANE_CTL_YUV422_VYUY			(3 << 16)
6790 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
6791 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
6792 #define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
6793 #define   PLANE_CTL_PLANE_GAMMA_DISABLE		(1 << 13) /* Pre-GLK */
6794 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
6795 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
6796 #define   PLANE_CTL_TILED_X			(1 << 10)
6797 #define   PLANE_CTL_TILED_Y			(4 << 10)
6798 #define   PLANE_CTL_TILED_YF			(5 << 10)
6799 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
6800 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
6801 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
6802 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
6803 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY	(2 << 4)
6804 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY	(3 << 4)
6805 #define   PLANE_CTL_ROTATE_MASK			0x3
6806 #define   PLANE_CTL_ROTATE_0			0x0
6807 #define   PLANE_CTL_ROTATE_90			0x1
6808 #define   PLANE_CTL_ROTATE_180			0x2
6809 #define   PLANE_CTL_ROTATE_270			0x3
6810 #define _PLANE_STRIDE_1_A			0x70188
6811 #define _PLANE_STRIDE_2_A			0x70288
6812 #define _PLANE_STRIDE_3_A			0x70388
6813 #define _PLANE_POS_1_A				0x7018c
6814 #define _PLANE_POS_2_A				0x7028c
6815 #define _PLANE_POS_3_A				0x7038c
6816 #define _PLANE_SIZE_1_A				0x70190
6817 #define _PLANE_SIZE_2_A				0x70290
6818 #define _PLANE_SIZE_3_A				0x70390
6819 #define _PLANE_SURF_1_A				0x7019c
6820 #define _PLANE_SURF_2_A				0x7029c
6821 #define _PLANE_SURF_3_A				0x7039c
6822 #define _PLANE_OFFSET_1_A			0x701a4
6823 #define _PLANE_OFFSET_2_A			0x702a4
6824 #define _PLANE_OFFSET_3_A			0x703a4
6825 #define _PLANE_KEYVAL_1_A			0x70194
6826 #define _PLANE_KEYVAL_2_A			0x70294
6827 #define _PLANE_KEYMSK_1_A			0x70198
6828 #define _PLANE_KEYMSK_2_A			0x70298
6829 #define  PLANE_KEYMSK_ALPHA_ENABLE		(1 << 31)
6830 #define _PLANE_KEYMAX_1_A			0x701a0
6831 #define _PLANE_KEYMAX_2_A			0x702a0
6832 #define  PLANE_KEYMAX_ALPHA(a)			((a) << 24)
6833 #define _PLANE_AUX_DIST_1_A			0x701c0
6834 #define _PLANE_AUX_DIST_2_A			0x702c0
6835 #define _PLANE_AUX_OFFSET_1_A			0x701c4
6836 #define _PLANE_AUX_OFFSET_2_A			0x702c4
6837 #define _PLANE_CUS_CTL_1_A			0x701c8
6838 #define _PLANE_CUS_CTL_2_A			0x702c8
6839 #define  PLANE_CUS_ENABLE			(1 << 31)
6840 #define  PLANE_CUS_PLANE_6			(0 << 30)
6841 #define  PLANE_CUS_PLANE_7			(1 << 30)
6842 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE		(1 << 19)
6843 #define  PLANE_CUS_HPHASE_0			(0 << 16)
6844 #define  PLANE_CUS_HPHASE_0_25			(1 << 16)
6845 #define  PLANE_CUS_HPHASE_0_5			(2 << 16)
6846 #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE		(1 << 15)
6847 #define  PLANE_CUS_VPHASE_0			(0 << 12)
6848 #define  PLANE_CUS_VPHASE_0_25			(1 << 12)
6849 #define  PLANE_CUS_VPHASE_0_5			(2 << 12)
6850 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
6851 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
6852 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
6853 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
6854 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
6855 #define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
6856 #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
6857 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
6858 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709		(1 << 17)
6859 #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709		(2 << 17)
6860 #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020	(3 << 17)
6861 #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020	(4 << 17)
6862 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
6863 #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
6864 #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
6865 #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY	(2 << 4)
6866 #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY	(3 << 4)
6867 #define _PLANE_BUF_CFG_1_A			0x7027c
6868 #define _PLANE_BUF_CFG_2_A			0x7037c
6869 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
6870 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
6871 
6872 /* Input CSC Register Definitions */
6873 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
6874 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
6875 
6876 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
6877 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
6878 
6879 #define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
6880 	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6881 	     _PLANE_INPUT_CSC_RY_GY_1_B)
6882 #define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
6883 	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6884 	     _PLANE_INPUT_CSC_RY_GY_2_B)
6885 
6886 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index)	\
6887 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
6888 		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6889 
6890 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
6891 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
6892 
6893 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
6894 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
6895 
6896 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
6897 	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6898 	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6899 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
6900 	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6901 	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6902 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)	\
6903 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6904 		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6905 
6906 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
6907 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
6908 
6909 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
6910 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
6911 
6912 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
6913 	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6914 	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6915 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
6916 	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6917 	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6918 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)	\
6919 	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6920 		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6921 
6922 #define _PLANE_CTL_1_B				0x71180
6923 #define _PLANE_CTL_2_B				0x71280
6924 #define _PLANE_CTL_3_B				0x71380
6925 #define _PLANE_CTL_1(pipe)	_PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6926 #define _PLANE_CTL_2(pipe)	_PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6927 #define _PLANE_CTL_3(pipe)	_PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6928 #define PLANE_CTL(pipe, plane)	\
6929 	_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6930 
6931 #define _PLANE_STRIDE_1_B			0x71188
6932 #define _PLANE_STRIDE_2_B			0x71288
6933 #define _PLANE_STRIDE_3_B			0x71388
6934 #define _PLANE_STRIDE_1(pipe)	\
6935 	_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6936 #define _PLANE_STRIDE_2(pipe)	\
6937 	_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6938 #define _PLANE_STRIDE_3(pipe)	\
6939 	_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6940 #define PLANE_STRIDE(pipe, plane)	\
6941 	_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6942 
6943 #define _PLANE_POS_1_B				0x7118c
6944 #define _PLANE_POS_2_B				0x7128c
6945 #define _PLANE_POS_3_B				0x7138c
6946 #define _PLANE_POS_1(pipe)	_PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6947 #define _PLANE_POS_2(pipe)	_PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6948 #define _PLANE_POS_3(pipe)	_PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6949 #define PLANE_POS(pipe, plane)	\
6950 	_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6951 
6952 #define _PLANE_SIZE_1_B				0x71190
6953 #define _PLANE_SIZE_2_B				0x71290
6954 #define _PLANE_SIZE_3_B				0x71390
6955 #define _PLANE_SIZE_1(pipe)	_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6956 #define _PLANE_SIZE_2(pipe)	_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6957 #define _PLANE_SIZE_3(pipe)	_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6958 #define PLANE_SIZE(pipe, plane)	\
6959 	_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6960 
6961 #define _PLANE_SURF_1_B				0x7119c
6962 #define _PLANE_SURF_2_B				0x7129c
6963 #define _PLANE_SURF_3_B				0x7139c
6964 #define _PLANE_SURF_1(pipe)	_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6965 #define _PLANE_SURF_2(pipe)	_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6966 #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6967 #define PLANE_SURF(pipe, plane)	\
6968 	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6969 
6970 #define _PLANE_OFFSET_1_B			0x711a4
6971 #define _PLANE_OFFSET_2_B			0x712a4
6972 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6973 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6974 #define PLANE_OFFSET(pipe, plane)	\
6975 	_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6976 
6977 #define _PLANE_KEYVAL_1_B			0x71194
6978 #define _PLANE_KEYVAL_2_B			0x71294
6979 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6980 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6981 #define PLANE_KEYVAL(pipe, plane)	\
6982 	_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6983 
6984 #define _PLANE_KEYMSK_1_B			0x71198
6985 #define _PLANE_KEYMSK_2_B			0x71298
6986 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6987 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6988 #define PLANE_KEYMSK(pipe, plane)	\
6989 	_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6990 
6991 #define _PLANE_KEYMAX_1_B			0x711a0
6992 #define _PLANE_KEYMAX_2_B			0x712a0
6993 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6994 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6995 #define PLANE_KEYMAX(pipe, plane)	\
6996 	_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6997 
6998 #define _PLANE_BUF_CFG_1_B			0x7127c
6999 #define _PLANE_BUF_CFG_2_B			0x7137c
7000 #define  DDB_ENTRY_MASK				0x7FF /* skl+: 10 bits, icl+ 11 bits */
7001 #define  DDB_ENTRY_END_SHIFT			16
7002 #define _PLANE_BUF_CFG_1(pipe)	\
7003 	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
7004 #define _PLANE_BUF_CFG_2(pipe)	\
7005 	_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
7006 #define PLANE_BUF_CFG(pipe, plane)	\
7007 	_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
7008 
7009 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
7010 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
7011 #define _PLANE_NV12_BUF_CFG_1(pipe)	\
7012 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
7013 #define _PLANE_NV12_BUF_CFG_2(pipe)	\
7014 	_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
7015 #define PLANE_NV12_BUF_CFG(pipe, plane)	\
7016 	_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
7017 
7018 #define _PLANE_AUX_DIST_1_B		0x711c0
7019 #define _PLANE_AUX_DIST_2_B		0x712c0
7020 #define _PLANE_AUX_DIST_1(pipe) \
7021 			_PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
7022 #define _PLANE_AUX_DIST_2(pipe) \
7023 			_PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
7024 #define PLANE_AUX_DIST(pipe, plane)     \
7025 	_MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
7026 
7027 #define _PLANE_AUX_OFFSET_1_B		0x711c4
7028 #define _PLANE_AUX_OFFSET_2_B		0x712c4
7029 #define _PLANE_AUX_OFFSET_1(pipe)       \
7030 		_PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
7031 #define _PLANE_AUX_OFFSET_2(pipe)       \
7032 		_PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
7033 #define PLANE_AUX_OFFSET(pipe, plane)   \
7034 	_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
7035 
7036 #define _PLANE_CUS_CTL_1_B		0x711c8
7037 #define _PLANE_CUS_CTL_2_B		0x712c8
7038 #define _PLANE_CUS_CTL_1(pipe)       \
7039 		_PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
7040 #define _PLANE_CUS_CTL_2(pipe)       \
7041 		_PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
7042 #define PLANE_CUS_CTL(pipe, plane)   \
7043 	_MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
7044 
7045 #define _PLANE_COLOR_CTL_1_B			0x711CC
7046 #define _PLANE_COLOR_CTL_2_B			0x712CC
7047 #define _PLANE_COLOR_CTL_3_B			0x713CC
7048 #define _PLANE_COLOR_CTL_1(pipe)	\
7049 	_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
7050 #define _PLANE_COLOR_CTL_2(pipe)	\
7051 	_PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
7052 #define PLANE_COLOR_CTL(pipe, plane)	\
7053 	_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
7054 
7055 #/* SKL new cursor registers */
7056 #define _CUR_BUF_CFG_A				0x7017c
7057 #define _CUR_BUF_CFG_B				0x7117c
7058 #define CUR_BUF_CFG(pipe)	_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
7059 
7060 /* VBIOS regs */
7061 #define VGACNTRL		_MMIO(0x71400)
7062 # define VGA_DISP_DISABLE			(1 << 31)
7063 # define VGA_2X_MODE				(1 << 30)
7064 # define VGA_PIPE_B_SELECT			(1 << 29)
7065 
7066 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
7067 
7068 /* Ironlake */
7069 
7070 #define CPU_VGACNTRL	_MMIO(0x41000)
7071 
7072 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
7073 #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
7074 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
7075 #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms	(1 << 2) /* pre-HSW */
7076 #define  DIGITAL_PORTA_PULSE_DURATION_6ms	(2 << 2) /* pre-HSW */
7077 #define  DIGITAL_PORTA_PULSE_DURATION_100ms	(3 << 2) /* pre-HSW */
7078 #define  DIGITAL_PORTA_PULSE_DURATION_MASK	(3 << 2) /* pre-HSW */
7079 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
7080 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
7081 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
7082 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
7083 
7084 /* refresh rate hardware control */
7085 #define RR_HW_CTL       _MMIO(0x45300)
7086 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
7087 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
7088 
7089 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
7090 #define  FDI_PLL_FB_CLOCK_MASK  0xff
7091 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
7092 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
7093 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
7094 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
7095 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
7096 
7097 #define PCH_3DCGDIS0		_MMIO(0x46020)
7098 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
7099 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
7100 
7101 #define PCH_3DCGDIS1		_MMIO(0x46024)
7102 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
7103 
7104 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
7105 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
7106 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
7107 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
7108 
7109 
7110 #define _PIPEA_DATA_M1		0x60030
7111 #define  PIPE_DATA_M1_OFFSET    0
7112 #define _PIPEA_DATA_N1		0x60034
7113 #define  PIPE_DATA_N1_OFFSET    0
7114 
7115 #define _PIPEA_DATA_M2		0x60038
7116 #define  PIPE_DATA_M2_OFFSET    0
7117 #define _PIPEA_DATA_N2		0x6003c
7118 #define  PIPE_DATA_N2_OFFSET    0
7119 
7120 #define _PIPEA_LINK_M1		0x60040
7121 #define  PIPE_LINK_M1_OFFSET    0
7122 #define _PIPEA_LINK_N1		0x60044
7123 #define  PIPE_LINK_N1_OFFSET    0
7124 
7125 #define _PIPEA_LINK_M2		0x60048
7126 #define  PIPE_LINK_M2_OFFSET    0
7127 #define _PIPEA_LINK_N2		0x6004c
7128 #define  PIPE_LINK_N2_OFFSET    0
7129 
7130 /* PIPEB timing regs are same start from 0x61000 */
7131 
7132 #define _PIPEB_DATA_M1		0x61030
7133 #define _PIPEB_DATA_N1		0x61034
7134 #define _PIPEB_DATA_M2		0x61038
7135 #define _PIPEB_DATA_N2		0x6103c
7136 #define _PIPEB_LINK_M1		0x61040
7137 #define _PIPEB_LINK_N1		0x61044
7138 #define _PIPEB_LINK_M2		0x61048
7139 #define _PIPEB_LINK_N2		0x6104c
7140 
7141 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7142 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7143 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7144 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7145 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7146 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7147 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7148 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7149 
7150 /* CPU panel fitter */
7151 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7152 #define _PFA_CTL_1               0x68080
7153 #define _PFB_CTL_1               0x68880
7154 #define  PF_ENABLE              (1 << 31)
7155 #define  PF_PIPE_SEL_MASK_IVB	(3 << 29)
7156 #define  PF_PIPE_SEL_IVB(pipe)	((pipe) << 29)
7157 #define  PF_FILTER_MASK		(3 << 23)
7158 #define  PF_FILTER_PROGRAMMED	(0 << 23)
7159 #define  PF_FILTER_MED_3x3	(1 << 23)
7160 #define  PF_FILTER_EDGE_ENHANCE	(2 << 23)
7161 #define  PF_FILTER_EDGE_SOFTEN	(3 << 23)
7162 #define _PFA_WIN_SZ		0x68074
7163 #define _PFB_WIN_SZ		0x68874
7164 #define _PFA_WIN_POS		0x68070
7165 #define _PFB_WIN_POS		0x68870
7166 #define _PFA_VSCALE		0x68084
7167 #define _PFB_VSCALE		0x68884
7168 #define _PFA_HSCALE		0x68090
7169 #define _PFB_HSCALE		0x68890
7170 
7171 #define PF_CTL(pipe)		_MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7172 #define PF_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7173 #define PF_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7174 #define PF_VSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7175 #define PF_HSCALE(pipe)		_MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7176 
7177 #define _PSA_CTL		0x68180
7178 #define _PSB_CTL		0x68980
7179 #define PS_ENABLE		(1 << 31)
7180 #define _PSA_WIN_SZ		0x68174
7181 #define _PSB_WIN_SZ		0x68974
7182 #define _PSA_WIN_POS		0x68170
7183 #define _PSB_WIN_POS		0x68970
7184 
7185 #define PS_CTL(pipe)		_MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7186 #define PS_WIN_SZ(pipe)		_MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7187 #define PS_WIN_POS(pipe)	_MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7188 
7189 /*
7190  * Skylake scalers
7191  */
7192 #define _PS_1A_CTRL      0x68180
7193 #define _PS_2A_CTRL      0x68280
7194 #define _PS_1B_CTRL      0x68980
7195 #define _PS_2B_CTRL      0x68A80
7196 #define _PS_1C_CTRL      0x69180
7197 #define PS_SCALER_EN        (1 << 31)
7198 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
7199 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
7200 #define SKL_PS_SCALER_MODE_HQ  (1 << 28)
7201 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7202 #define PS_SCALER_MODE_PLANAR (1 << 29)
7203 #define PS_SCALER_MODE_NORMAL (0 << 29)
7204 #define PS_PLANE_SEL_MASK  (7 << 25)
7205 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7206 #define PS_FILTER_MASK         (3 << 23)
7207 #define PS_FILTER_MEDIUM       (0 << 23)
7208 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
7209 #define PS_FILTER_BILINEAR     (3 << 23)
7210 #define PS_VERT3TAP            (1 << 21)
7211 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7212 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7213 #define PS_PWRUP_PROGRESS         (1 << 17)
7214 #define PS_V_FILTER_BYPASS        (1 << 8)
7215 #define PS_VADAPT_EN              (1 << 7)
7216 #define PS_VADAPT_MODE_MASK        (3 << 5)
7217 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7218 #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
7219 #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
7220 #define PS_PLANE_Y_SEL_MASK  (7 << 5)
7221 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7222 
7223 #define _PS_PWR_GATE_1A     0x68160
7224 #define _PS_PWR_GATE_2A     0x68260
7225 #define _PS_PWR_GATE_1B     0x68960
7226 #define _PS_PWR_GATE_2B     0x68A60
7227 #define _PS_PWR_GATE_1C     0x69160
7228 #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
7229 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
7230 #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
7231 #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
7232 #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
7233 #define PS_PWR_GATE_SLPEN_8             0
7234 #define PS_PWR_GATE_SLPEN_16            1
7235 #define PS_PWR_GATE_SLPEN_24            2
7236 #define PS_PWR_GATE_SLPEN_32            3
7237 
7238 #define _PS_WIN_POS_1A      0x68170
7239 #define _PS_WIN_POS_2A      0x68270
7240 #define _PS_WIN_POS_1B      0x68970
7241 #define _PS_WIN_POS_2B      0x68A70
7242 #define _PS_WIN_POS_1C      0x69170
7243 
7244 #define _PS_WIN_SZ_1A       0x68174
7245 #define _PS_WIN_SZ_2A       0x68274
7246 #define _PS_WIN_SZ_1B       0x68974
7247 #define _PS_WIN_SZ_2B       0x68A74
7248 #define _PS_WIN_SZ_1C       0x69174
7249 
7250 #define _PS_VSCALE_1A       0x68184
7251 #define _PS_VSCALE_2A       0x68284
7252 #define _PS_VSCALE_1B       0x68984
7253 #define _PS_VSCALE_2B       0x68A84
7254 #define _PS_VSCALE_1C       0x69184
7255 
7256 #define _PS_HSCALE_1A       0x68190
7257 #define _PS_HSCALE_2A       0x68290
7258 #define _PS_HSCALE_1B       0x68990
7259 #define _PS_HSCALE_2B       0x68A90
7260 #define _PS_HSCALE_1C       0x69190
7261 
7262 #define _PS_VPHASE_1A       0x68188
7263 #define _PS_VPHASE_2A       0x68288
7264 #define _PS_VPHASE_1B       0x68988
7265 #define _PS_VPHASE_2B       0x68A88
7266 #define _PS_VPHASE_1C       0x69188
7267 #define  PS_Y_PHASE(x)		((x) << 16)
7268 #define  PS_UV_RGB_PHASE(x)	((x) << 0)
7269 #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
7270 #define   PS_PHASE_TRIP	(1 << 0)
7271 
7272 #define _PS_HPHASE_1A       0x68194
7273 #define _PS_HPHASE_2A       0x68294
7274 #define _PS_HPHASE_1B       0x68994
7275 #define _PS_HPHASE_2B       0x68A94
7276 #define _PS_HPHASE_1C       0x69194
7277 
7278 #define _PS_ECC_STAT_1A     0x681D0
7279 #define _PS_ECC_STAT_2A     0x682D0
7280 #define _PS_ECC_STAT_1B     0x689D0
7281 #define _PS_ECC_STAT_2B     0x68AD0
7282 #define _PS_ECC_STAT_1C     0x691D0
7283 
7284 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7285 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
7286 			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
7287 			_ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7288 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
7289 			_ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7290 			_ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7291 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
7292 			_ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7293 			_ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7294 #define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
7295 			_ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
7296 			_ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7297 #define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7298 			_ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
7299 			_ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7300 #define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7301 			_ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
7302 			_ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7303 #define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7304 			_ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
7305 			_ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7306 #define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7307 			_ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
7308 			_ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7309 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
7310 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
7311 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7312 
7313 /* legacy palette */
7314 #define _LGC_PALETTE_A           0x4a000
7315 #define _LGC_PALETTE_B           0x4a800
7316 #define LGC_PALETTE_RED_MASK     REG_GENMASK(23, 16)
7317 #define LGC_PALETTE_GREEN_MASK   REG_GENMASK(15, 8)
7318 #define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
7319 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7320 
7321 /* ilk/snb precision palette */
7322 #define _PREC_PALETTE_A           0x4b000
7323 #define _PREC_PALETTE_B           0x4c000
7324 #define   PREC_PALETTE_RED_MASK   REG_GENMASK(29, 20)
7325 #define   PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
7326 #define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
7327 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7328 
7329 #define  _PREC_PIPEAGCMAX              0x4d000
7330 #define  _PREC_PIPEBGCMAX              0x4d010
7331 #define PREC_PIPEGCMAX(pipe, i)        _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7332 
7333 #define _GAMMA_MODE_A		0x4a480
7334 #define _GAMMA_MODE_B		0x4ac80
7335 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7336 #define  PRE_CSC_GAMMA_ENABLE	(1 << 31)
7337 #define  POST_CSC_GAMMA_ENABLE	(1 << 30)
7338 #define  GAMMA_MODE_MODE_MASK	(3 << 0)
7339 #define  GAMMA_MODE_MODE_8BIT	(0 << 0)
7340 #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
7341 #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
7342 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
7343 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
7344 
7345 /* DMC/CSR */
7346 #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
7347 #define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
7348 #define CSR_HTP_ADDR_SKL	0x00500034
7349 #define CSR_SSP_BASE		_MMIO(0x8F074)
7350 #define CSR_HTP_SKL		_MMIO(0x8F004)
7351 #define CSR_LAST_WRITE		_MMIO(0x8F034)
7352 #define CSR_LAST_WRITE_VALUE	0xc003b400
7353 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7354 #define CSR_MMIO_START_RANGE	0x80000
7355 #define CSR_MMIO_END_RANGE	0x8FFFF
7356 #define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
7357 #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
7358 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
7359 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
7360 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
7361 
7362 #define DMC_DEBUG3		_MMIO(0x101090)
7363 
7364 /* Display Internal Timeout Register */
7365 #define RM_TIMEOUT		_MMIO(0x42060)
7366 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
7367 
7368 /* interrupts */
7369 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
7370 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
7371 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
7372 #define DE_PLANEB_FLIP_DONE     (1 << 27)
7373 #define DE_PLANEA_FLIP_DONE     (1 << 26)
7374 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7375 #define DE_PCU_EVENT            (1 << 25)
7376 #define DE_GTT_FAULT            (1 << 24)
7377 #define DE_POISON               (1 << 23)
7378 #define DE_PERFORM_COUNTER      (1 << 22)
7379 #define DE_PCH_EVENT            (1 << 21)
7380 #define DE_AUX_CHANNEL_A        (1 << 20)
7381 #define DE_DP_A_HOTPLUG         (1 << 19)
7382 #define DE_GSE                  (1 << 18)
7383 #define DE_PIPEB_VBLANK         (1 << 15)
7384 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
7385 #define DE_PIPEB_ODD_FIELD      (1 << 13)
7386 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
7387 #define DE_PIPEB_VSYNC          (1 << 11)
7388 #define DE_PIPEB_CRC_DONE	(1 << 10)
7389 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
7390 #define DE_PIPEA_VBLANK         (1 << 7)
7391 #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
7392 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
7393 #define DE_PIPEA_ODD_FIELD      (1 << 5)
7394 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
7395 #define DE_PIPEA_VSYNC          (1 << 3)
7396 #define DE_PIPEA_CRC_DONE	(1 << 2)
7397 #define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
7398 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7399 #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
7400 
7401 /* More Ivybridge lolz */
7402 #define DE_ERR_INT_IVB			(1 << 30)
7403 #define DE_GSE_IVB			(1 << 29)
7404 #define DE_PCH_EVENT_IVB		(1 << 28)
7405 #define DE_DP_A_HOTPLUG_IVB		(1 << 27)
7406 #define DE_AUX_CHANNEL_A_IVB		(1 << 26)
7407 #define DE_EDP_PSR_INT_HSW		(1 << 19)
7408 #define DE_SPRITEC_FLIP_DONE_IVB	(1 << 14)
7409 #define DE_PLANEC_FLIP_DONE_IVB		(1 << 13)
7410 #define DE_PIPEC_VBLANK_IVB		(1 << 10)
7411 #define DE_SPRITEB_FLIP_DONE_IVB	(1 << 9)
7412 #define DE_PLANEB_FLIP_DONE_IVB		(1 << 8)
7413 #define DE_PIPEB_VBLANK_IVB		(1 << 5)
7414 #define DE_SPRITEA_FLIP_DONE_IVB	(1 << 4)
7415 #define DE_PLANEA_FLIP_DONE_IVB		(1 << 3)
7416 #define DE_PLANE_FLIP_DONE_IVB(plane)	(1 << (3 + 5 * (plane)))
7417 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
7418 #define DE_PIPE_VBLANK_IVB(pipe)	(1 << ((pipe) * 5))
7419 
7420 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
7421 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
7422 
7423 #define DEISR   _MMIO(0x44000)
7424 #define DEIMR   _MMIO(0x44004)
7425 #define DEIIR   _MMIO(0x44008)
7426 #define DEIER   _MMIO(0x4400c)
7427 
7428 #define GTISR   _MMIO(0x44010)
7429 #define GTIMR   _MMIO(0x44014)
7430 #define GTIIR   _MMIO(0x44018)
7431 #define GTIER   _MMIO(0x4401c)
7432 
7433 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
7434 #define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
7435 #define  GEN8_PCU_IRQ			(1 << 30)
7436 #define  GEN8_DE_PCH_IRQ		(1 << 23)
7437 #define  GEN8_DE_MISC_IRQ		(1 << 22)
7438 #define  GEN8_DE_PORT_IRQ		(1 << 20)
7439 #define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
7440 #define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
7441 #define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
7442 #define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
7443 #define  GEN8_GT_VECS_IRQ		(1 << 6)
7444 #define  GEN8_GT_GUC_IRQ		(1 << 5)
7445 #define  GEN8_GT_PM_IRQ			(1 << 4)
7446 #define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
7447 #define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
7448 #define  GEN8_GT_BCS_IRQ		(1 << 1)
7449 #define  GEN8_GT_RCS_IRQ		(1 << 0)
7450 
7451 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7452 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7453 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7454 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7455 
7456 #define GEN8_RCS_IRQ_SHIFT 0
7457 #define GEN8_BCS_IRQ_SHIFT 16
7458 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
7459 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7460 #define GEN8_VECS_IRQ_SHIFT 0
7461 #define GEN8_WD_IRQ_SHIFT 16
7462 
7463 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7464 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7465 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7466 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7467 #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
7468 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
7469 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
7470 #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
7471 #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
7472 #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
7473 #define  GEN8_PIPE_SPRITE_FLIP_DONE	(1 << 5)
7474 #define  GEN8_PIPE_PRIMARY_FLIP_DONE	(1 << 4)
7475 #define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
7476 #define  GEN8_PIPE_VSYNC		(1 << 1)
7477 #define  GEN8_PIPE_VBLANK		(1 << 0)
7478 #define  GEN9_PIPE_CURSOR_FAULT		(1 << 11)
7479 #define  GEN11_PIPE_PLANE7_FAULT	(1 << 22)
7480 #define  GEN11_PIPE_PLANE6_FAULT	(1 << 21)
7481 #define  GEN11_PIPE_PLANE5_FAULT	(1 << 20)
7482 #define  GEN9_PIPE_PLANE4_FAULT		(1 << 10)
7483 #define  GEN9_PIPE_PLANE3_FAULT		(1 << 9)
7484 #define  GEN9_PIPE_PLANE2_FAULT		(1 << 8)
7485 #define  GEN9_PIPE_PLANE1_FAULT		(1 << 7)
7486 #define  GEN9_PIPE_PLANE4_FLIP_DONE	(1 << 6)
7487 #define  GEN9_PIPE_PLANE3_FLIP_DONE	(1 << 5)
7488 #define  GEN9_PIPE_PLANE2_FLIP_DONE	(1 << 4)
7489 #define  GEN9_PIPE_PLANE1_FLIP_DONE	(1 << 3)
7490 #define  GEN9_PIPE_PLANE_FLIP_DONE(p)	(1 << (3 + (p)))
7491 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7492 	(GEN8_PIPE_CURSOR_FAULT | \
7493 	 GEN8_PIPE_SPRITE_FAULT | \
7494 	 GEN8_PIPE_PRIMARY_FAULT)
7495 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7496 	(GEN9_PIPE_CURSOR_FAULT | \
7497 	 GEN9_PIPE_PLANE4_FAULT | \
7498 	 GEN9_PIPE_PLANE3_FAULT | \
7499 	 GEN9_PIPE_PLANE2_FAULT | \
7500 	 GEN9_PIPE_PLANE1_FAULT)
7501 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
7502 	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
7503 	 GEN11_PIPE_PLANE7_FAULT | \
7504 	 GEN11_PIPE_PLANE6_FAULT | \
7505 	 GEN11_PIPE_PLANE5_FAULT)
7506 
7507 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7508 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7509 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7510 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7511 #define  DSI1_NON_TE			(1 << 31)
7512 #define  DSI0_NON_TE			(1 << 30)
7513 #define  ICL_AUX_CHANNEL_E		(1 << 29)
7514 #define  CNL_AUX_CHANNEL_F		(1 << 28)
7515 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
7516 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
7517 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
7518 #define  DSI1_TE			(1 << 24)
7519 #define  DSI0_TE			(1 << 23)
7520 #define  BXT_DE_PORT_HP_DDIC		(1 << 5)
7521 #define  BXT_DE_PORT_HP_DDIB		(1 << 4)
7522 #define  BXT_DE_PORT_HP_DDIA		(1 << 3)
7523 #define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
7524 					 BXT_DE_PORT_HP_DDIB | \
7525 					 BXT_DE_PORT_HP_DDIC)
7526 #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
7527 #define  BXT_DE_PORT_GMBUS		(1 << 1)
7528 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
7529 #define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
7530 #define  TGL_DE_PORT_AUX_USBC5		(1 << 12)
7531 #define  TGL_DE_PORT_AUX_USBC4		(1 << 11)
7532 #define  TGL_DE_PORT_AUX_USBC3		(1 << 10)
7533 #define  TGL_DE_PORT_AUX_USBC2		(1 << 9)
7534 #define  TGL_DE_PORT_AUX_USBC1		(1 << 8)
7535 #define  TGL_DE_PORT_AUX_DDIC		(1 << 2)
7536 #define  TGL_DE_PORT_AUX_DDIB		(1 << 1)
7537 #define  TGL_DE_PORT_AUX_DDIA		(1 << 0)
7538 
7539 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7540 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7541 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7542 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7543 #define  GEN8_DE_MISC_GSE		(1 << 27)
7544 #define  GEN8_DE_EDP_PSR		(1 << 19)
7545 
7546 #define GEN8_PCU_ISR _MMIO(0x444e0)
7547 #define GEN8_PCU_IMR _MMIO(0x444e4)
7548 #define GEN8_PCU_IIR _MMIO(0x444e8)
7549 #define GEN8_PCU_IER _MMIO(0x444ec)
7550 
7551 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
7552 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
7553 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
7554 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
7555 #define  GEN11_GU_MISC_GSE	(1 << 27)
7556 
7557 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
7558 #define  GEN11_MASTER_IRQ		(1 << 31)
7559 #define  GEN11_PCU_IRQ			(1 << 30)
7560 #define  GEN11_GU_MISC_IRQ		(1 << 29)
7561 #define  GEN11_DISPLAY_IRQ		(1 << 16)
7562 #define  GEN11_GT_DW_IRQ(x)		(1 << (x))
7563 #define  GEN11_GT_DW1_IRQ		(1 << 1)
7564 #define  GEN11_GT_DW0_IRQ		(1 << 0)
7565 
7566 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
7567 #define  GEN11_DISPLAY_IRQ_ENABLE	(1 << 31)
7568 #define  GEN11_AUDIO_CODEC_IRQ		(1 << 24)
7569 #define  GEN11_DE_PCH_IRQ		(1 << 23)
7570 #define  GEN11_DE_MISC_IRQ		(1 << 22)
7571 #define  GEN11_DE_HPD_IRQ		(1 << 21)
7572 #define  GEN11_DE_PORT_IRQ		(1 << 20)
7573 #define  GEN11_DE_PIPE_C		(1 << 18)
7574 #define  GEN11_DE_PIPE_B		(1 << 17)
7575 #define  GEN11_DE_PIPE_A		(1 << 16)
7576 
7577 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
7578 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
7579 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
7580 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
7581 #define  GEN12_TC6_HOTPLUG			(1 << 21)
7582 #define  GEN12_TC5_HOTPLUG			(1 << 20)
7583 #define  GEN11_TC4_HOTPLUG			(1 << 19)
7584 #define  GEN11_TC3_HOTPLUG			(1 << 18)
7585 #define  GEN11_TC2_HOTPLUG			(1 << 17)
7586 #define  GEN11_TC1_HOTPLUG			(1 << 16)
7587 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
7588 #define  GEN11_DE_TC_HOTPLUG_MASK		(GEN12_TC6_HOTPLUG | \
7589 						 GEN12_TC5_HOTPLUG | \
7590 						 GEN11_TC4_HOTPLUG | \
7591 						 GEN11_TC3_HOTPLUG | \
7592 						 GEN11_TC2_HOTPLUG | \
7593 						 GEN11_TC1_HOTPLUG)
7594 #define  GEN12_TBT6_HOTPLUG			(1 << 5)
7595 #define  GEN12_TBT5_HOTPLUG			(1 << 4)
7596 #define  GEN11_TBT4_HOTPLUG			(1 << 3)
7597 #define  GEN11_TBT3_HOTPLUG			(1 << 2)
7598 #define  GEN11_TBT2_HOTPLUG			(1 << 1)
7599 #define  GEN11_TBT1_HOTPLUG			(1 << 0)
7600 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
7601 #define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN12_TBT6_HOTPLUG | \
7602 						 GEN12_TBT5_HOTPLUG | \
7603 						 GEN11_TBT4_HOTPLUG | \
7604 						 GEN11_TBT3_HOTPLUG | \
7605 						 GEN11_TBT2_HOTPLUG | \
7606 						 GEN11_TBT1_HOTPLUG)
7607 
7608 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
7609 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
7610 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
7611 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
7612 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
7613 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
7614 
7615 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
7616 #define  GEN11_CSME			(31)
7617 #define  GEN11_GUNIT			(28)
7618 #define  GEN11_GUC			(25)
7619 #define  GEN11_WDPERF			(20)
7620 #define  GEN11_KCR			(19)
7621 #define  GEN11_GTPM			(16)
7622 #define  GEN11_BCS			(15)
7623 #define  GEN11_RCS0			(0)
7624 
7625 #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
7626 #define  GEN11_VECS(x)			(31 - (x))
7627 #define  GEN11_VCS(x)			(x)
7628 
7629 #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
7630 
7631 #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
7632 #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
7633 #define  GEN11_INTR_DATA_VALID		(1 << 31)
7634 #define  GEN11_INTR_ENGINE_CLASS(x)	(((x) & GENMASK(18, 16)) >> 16)
7635 #define  GEN11_INTR_ENGINE_INSTANCE(x)	(((x) & GENMASK(25, 20)) >> 20)
7636 #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
7637 /* irq instances for OTHER_CLASS */
7638 #define OTHER_GUC_INSTANCE	0
7639 #define OTHER_GTPM_INSTANCE	1
7640 
7641 #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
7642 
7643 #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
7644 #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
7645 
7646 #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
7647 
7648 #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
7649 #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
7650 #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
7651 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
7652 #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
7653 #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
7654 
7655 #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
7656 #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
7657 #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
7658 #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
7659 #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
7660 #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
7661 #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
7662 #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
7663 #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
7664 
7665 #define   ENGINE1_MASK			REG_GENMASK(31, 16)
7666 #define   ENGINE0_MASK			REG_GENMASK(15, 0)
7667 
7668 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
7669 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7670 #define  ILK_ELPIN_409_SELECT	(1 << 25)
7671 #define  ILK_DPARB_GATE	(1 << 22)
7672 #define  ILK_VSDPFD_FULL	(1 << 21)
7673 #define FUSE_STRAP			_MMIO(0x42014)
7674 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
7675 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
7676 #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
7677 #define  IVB_PIPE_C_DISABLE		(1 << 28)
7678 #define  ILK_HDCP_DISABLE		(1 << 25)
7679 #define  ILK_eDP_A_DISABLE		(1 << 24)
7680 #define  HSW_CDCLK_LIMIT		(1 << 24)
7681 #define  ILK_DESKTOP			(1 << 23)
7682 #define  HSW_CPU_SSC_ENABLE		(1 << 21)
7683 
7684 #define FUSE_STRAP3			_MMIO(0x42020)
7685 #define  HSW_REF_CLK_SELECT		(1 << 1)
7686 
7687 #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
7688 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
7689 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
7690 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
7691 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
7692 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
7693 
7694 #define IVB_CHICKEN3	_MMIO(0x4200c)
7695 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
7696 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
7697 
7698 #define CHICKEN_PAR1_1		_MMIO(0x42080)
7699 #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
7700 #define  DPA_MASK_VBLANK_SRD	(1 << 15)
7701 #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
7702 #define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)
7703 
7704 #define CHICKEN_PAR2_1		_MMIO(0x42090)
7705 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
7706 
7707 #define CHICKEN_MISC_2		_MMIO(0x42084)
7708 #define  CNL_COMP_PWR_DOWN	(1 << 23)
7709 #define  GLK_CL2_PWR_DOWN	(1 << 12)
7710 #define  GLK_CL1_PWR_DOWN	(1 << 11)
7711 #define  GLK_CL0_PWR_DOWN	(1 << 10)
7712 
7713 #define CHICKEN_MISC_4		_MMIO(0x4208c)
7714 #define   FBC_STRIDE_OVERRIDE	(1 << 13)
7715 #define   FBC_STRIDE_MASK	0x1FFF
7716 
7717 #define _CHICKEN_PIPESL_1_A	0x420b0
7718 #define _CHICKEN_PIPESL_1_B	0x420b4
7719 #define  HSW_FBCQ_DIS			(1 << 22)
7720 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
7721 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7722 
7723 #define _CHICKEN_TRANS_A	0x420c0
7724 #define _CHICKEN_TRANS_B	0x420c4
7725 #define _CHICKEN_TRANS_C	0x420c8
7726 #define _CHICKEN_TRANS_EDP	0x420cc
7727 #define _CHICKEN_TRANS_D	0x420d8
7728 #define CHICKEN_TRANS(trans)	_MMIO(_PICK((trans), \
7729 					    [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
7730 					    [TRANSCODER_A] = _CHICKEN_TRANS_A, \
7731 					    [TRANSCODER_B] = _CHICKEN_TRANS_B, \
7732 					    [TRANSCODER_C] = _CHICKEN_TRANS_C, \
7733 					    [TRANSCODER_D] = _CHICKEN_TRANS_D))
7734 #define  HSW_FRAME_START_DELAY_MASK	(3 << 27)
7735 #define  HSW_FRAME_START_DELAY(x)	((x) << 27) /* 0-3 */
7736 #define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
7737 #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
7738 #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
7739 #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1 << 17) /* CHICKEN_TRANS_A only */
7740 #define  DDIE_TRAINING_OVERRIDE_VALUE	(1 << 16) /* CHICKEN_TRANS_A only */
7741 #define  PSR2_ADD_VERTICAL_LINE_COUNT   (1 << 15)
7742 #define  PSR2_VSC_ENABLE_PROG_HEADER    (1 << 12)
7743 
7744 #define DISP_ARB_CTL	_MMIO(0x45000)
7745 #define  DISP_FBC_MEMORY_WAKE		(1 << 31)
7746 #define  DISP_TILE_SURFACE_SWIZZLING	(1 << 13)
7747 #define  DISP_FBC_WM_DIS		(1 << 15)
7748 #define DISP_ARB_CTL2	_MMIO(0x45004)
7749 #define  DISP_DATA_PARTITION_5_6	(1 << 6)
7750 #define  DISP_IPC_ENABLE		(1 << 3)
7751 #define _DBUF_CTL_S1			0x45008
7752 #define _DBUF_CTL_S2			0x44FE8
7753 #define DBUF_CTL_S(slice)		_MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
7754 #define  DBUF_POWER_REQUEST		(1 << 31)
7755 #define  DBUF_POWER_STATE		(1 << 30)
7756 #define GEN7_MSG_CTL	_MMIO(0x45010)
7757 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
7758 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
7759 
7760 #define BW_BUDDY1_CTL			_MMIO(0x45140)
7761 #define BW_BUDDY2_CTL			_MMIO(0x45150)
7762 #define   BW_BUDDY_DISABLE		REG_BIT(31)
7763 #define   BW_BUDDY_TLB_REQ_TIMER_MASK	REG_GENMASK(21, 16)
7764 
7765 #define BW_BUDDY1_PAGE_MASK		_MMIO(0x45144)
7766 #define BW_BUDDY2_PAGE_MASK		_MMIO(0x45154)
7767 
7768 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
7769 #define  RESET_PCH_HANDSHAKE_ENABLE	(1 << 4)
7770 
7771 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
7772 #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
7773 #define   CNL_DELAY_PMRSP		(1 << 22)
7774 #define   MASK_WAKEMEM			(1 << 13)
7775 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
7776 
7777 #define SKL_DFSM			_MMIO(0x51000)
7778 #define   SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)
7779 #define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)
7780 #define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
7781 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
7782 #define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
7783 #define   SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
7784 #define   SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
7785 #define   ICL_DFSM_DMC_DISABLE		(1 << 23)
7786 #define   SKL_DFSM_PIPE_A_DISABLE	(1 << 30)
7787 #define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
7788 #define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
7789 #define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
7790 #define   CNL_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
7791 
7792 #define SKL_DSSM				_MMIO(0x51004)
7793 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
7794 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
7795 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
7796 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
7797 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz	(2 << 29)
7798 
7799 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
7800 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1 << 14)
7801 
7802 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
7803 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1 << 8)
7804 #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
7805 
7806 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
7807 #define   FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(1)
7808 #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
7809 #define   GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
7810 
7811 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
7812 #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
7813 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)	(((hi) << 2) | ((lo) << 1))
7814 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7815 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7816 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7817 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK		GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7818 
7819 /* GEN7 chicken */
7820 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
7821   #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1 << 10) | (1 << 26))
7822   #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
7823 
7824 #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
7825   #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
7826   #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
7827   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
7828   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
7829 
7830 #define GEN8_L3CNTLREG	_MMIO(0x7034)
7831   #define GEN8_ERRDETBCTRL (1 << 9)
7832 
7833 #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
7834   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
7835   #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE	(1 << 9)
7836 
7837 #define HIZ_CHICKEN					_MMIO(0x7018)
7838 # define CHV_HZ_8X8_MODE_IN_1X				(1 << 15)
7839 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1 << 3)
7840 
7841 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
7842 #define  DISABLE_PIXEL_MASK_CAMMING		(1 << 14)
7843 
7844 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
7845 #define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
7846 
7847 #define GEN7_SARCHKMD				_MMIO(0xB000)
7848 #define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
7849 #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
7850 
7851 #define GEN7_L3SQCREG1				_MMIO(0xB010)
7852 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
7853 
7854 #define GEN8_L3SQCREG1				_MMIO(0xB100)
7855 /*
7856  * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7857  * Using the formula in BSpec leads to a hang, while the formula here works
7858  * fine and matches the formulas for all other platforms. A BSpec change
7859  * request has been filed to clarify this.
7860  */
7861 #define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)
7862 #define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)
7863 #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
7864 
7865 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
7866 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
7867 #define  GEN7_L3AGDIS				(1 << 19)
7868 #define GEN7_L3CNTLREG2				_MMIO(0xB020)
7869 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
7870 
7871 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
7872 #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
7873 #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
7874 #define   GEN11_I2M_WRITE_DISABLE		(1 << 28)
7875 
7876 #define GEN7_L3SQCREG4				_MMIO(0xb034)
7877 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)
7878 
7879 #define GEN11_SCRATCH2					_MMIO(0xb140)
7880 #define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE	(1 << 19)
7881 
7882 #define GEN8_L3SQCREG4				_MMIO(0xb118)
7883 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
7884 #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
7885 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
7886 
7887 /* GEN8 chicken */
7888 #define HDC_CHICKEN0				_MMIO(0x7300)
7889 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
7890 #define ICL_HDC_MODE				_MMIO(0xE5F4)
7891 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
7892 #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
7893 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1 << 11)
7894 #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1 << 5)
7895 #define  HDC_FORCE_NON_COHERENT			(1 << 4)
7896 #define  HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)
7897 
7898 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
7899 
7900 /* GEN9 chicken */
7901 #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
7902 #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
7903 
7904 #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
7905 #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
7906 
7907 /* WaCatErrorRejectionIssue */
7908 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
7909 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1 << 11)
7910 
7911 #define HSW_SCRATCH1				_MMIO(0xb038)
7912 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1 << 27)
7913 
7914 #define BDW_SCRATCH1					_MMIO(0xb11c)
7915 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
7916 
7917 /*GEN11 chicken */
7918 #define _PIPEA_CHICKEN				0x70038
7919 #define _PIPEB_CHICKEN				0x71038
7920 #define _PIPEC_CHICKEN				0x72038
7921 #define PIPE_CHICKEN(pipe)			_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7922 							   _PIPEB_CHICKEN)
7923 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
7924 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
7925 
7926 #define FF_MODE2			_MMIO(0x6604)
7927 #define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
7928 #define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
7929 
7930 /* PCH */
7931 
7932 #define PCH_DISPLAY_BASE	0xc0000u
7933 
7934 /* south display engine interrupt: IBX */
7935 #define SDE_AUDIO_POWER_D	(1 << 27)
7936 #define SDE_AUDIO_POWER_C	(1 << 26)
7937 #define SDE_AUDIO_POWER_B	(1 << 25)
7938 #define SDE_AUDIO_POWER_SHIFT	(25)
7939 #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
7940 #define SDE_GMBUS		(1 << 24)
7941 #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
7942 #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
7943 #define SDE_AUDIO_HDCP_MASK	(3 << 22)
7944 #define SDE_AUDIO_TRANSB	(1 << 21)
7945 #define SDE_AUDIO_TRANSA	(1 << 20)
7946 #define SDE_AUDIO_TRANS_MASK	(3 << 20)
7947 #define SDE_POISON		(1 << 19)
7948 /* 18 reserved */
7949 #define SDE_FDI_RXB		(1 << 17)
7950 #define SDE_FDI_RXA		(1 << 16)
7951 #define SDE_FDI_MASK		(3 << 16)
7952 #define SDE_AUXD		(1 << 15)
7953 #define SDE_AUXC		(1 << 14)
7954 #define SDE_AUXB		(1 << 13)
7955 #define SDE_AUX_MASK		(7 << 13)
7956 /* 12 reserved */
7957 #define SDE_CRT_HOTPLUG         (1 << 11)
7958 #define SDE_PORTD_HOTPLUG       (1 << 10)
7959 #define SDE_PORTC_HOTPLUG       (1 << 9)
7960 #define SDE_PORTB_HOTPLUG       (1 << 8)
7961 #define SDE_SDVOB_HOTPLUG       (1 << 6)
7962 #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
7963 				 SDE_SDVOB_HOTPLUG |	\
7964 				 SDE_PORTB_HOTPLUG |	\
7965 				 SDE_PORTC_HOTPLUG |	\
7966 				 SDE_PORTD_HOTPLUG)
7967 #define SDE_TRANSB_CRC_DONE	(1 << 5)
7968 #define SDE_TRANSB_CRC_ERR	(1 << 4)
7969 #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
7970 #define SDE_TRANSA_CRC_DONE	(1 << 2)
7971 #define SDE_TRANSA_CRC_ERR	(1 << 1)
7972 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
7973 #define SDE_TRANS_MASK		(0x3f)
7974 
7975 /* south display engine interrupt: CPT - CNP */
7976 #define SDE_AUDIO_POWER_D_CPT	(1 << 31)
7977 #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
7978 #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
7979 #define SDE_AUDIO_POWER_SHIFT_CPT   29
7980 #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
7981 #define SDE_AUXD_CPT		(1 << 27)
7982 #define SDE_AUXC_CPT		(1 << 26)
7983 #define SDE_AUXB_CPT		(1 << 25)
7984 #define SDE_AUX_MASK_CPT	(7 << 25)
7985 #define SDE_PORTE_HOTPLUG_SPT	(1 << 25)
7986 #define SDE_PORTA_HOTPLUG_SPT	(1 << 24)
7987 #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
7988 #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
7989 #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
7990 #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
7991 #define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
7992 #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
7993 				 SDE_SDVOB_HOTPLUG_CPT |	\
7994 				 SDE_PORTD_HOTPLUG_CPT |	\
7995 				 SDE_PORTC_HOTPLUG_CPT |	\
7996 				 SDE_PORTB_HOTPLUG_CPT)
7997 #define SDE_HOTPLUG_MASK_SPT	(SDE_PORTE_HOTPLUG_SPT |	\
7998 				 SDE_PORTD_HOTPLUG_CPT |	\
7999 				 SDE_PORTC_HOTPLUG_CPT |	\
8000 				 SDE_PORTB_HOTPLUG_CPT |	\
8001 				 SDE_PORTA_HOTPLUG_SPT)
8002 #define SDE_GMBUS_CPT		(1 << 17)
8003 #define SDE_ERROR_CPT		(1 << 16)
8004 #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
8005 #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
8006 #define SDE_FDI_RXC_CPT		(1 << 8)
8007 #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
8008 #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
8009 #define SDE_FDI_RXB_CPT		(1 << 4)
8010 #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
8011 #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
8012 #define SDE_FDI_RXA_CPT		(1 << 0)
8013 #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
8014 				 SDE_AUDIO_CP_REQ_B_CPT | \
8015 				 SDE_AUDIO_CP_REQ_A_CPT)
8016 #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
8017 				 SDE_AUDIO_CP_CHG_B_CPT | \
8018 				 SDE_AUDIO_CP_CHG_A_CPT)
8019 #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
8020 				 SDE_FDI_RXB_CPT | \
8021 				 SDE_FDI_RXA_CPT)
8022 
8023 /* south display engine interrupt: ICP/TGP */
8024 #define SDE_GMBUS_ICP			(1 << 23)
8025 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
8026 #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
8027 #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
8028 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
8029 #define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
8030 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
8031 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
8032 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
8033 #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
8034 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
8035 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
8036 #define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
8037 					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
8038 					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
8039 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
8040 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
8041 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
8042 
8043 #define SDEISR  _MMIO(0xc4000)
8044 #define SDEIMR  _MMIO(0xc4004)
8045 #define SDEIIR  _MMIO(0xc4008)
8046 #define SDEIER  _MMIO(0xc400c)
8047 
8048 #define SERR_INT			_MMIO(0xc4040)
8049 #define  SERR_INT_POISON		(1 << 31)
8050 #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
8051 
8052 /* digital port hotplug */
8053 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
8054 #define  PORTA_HOTPLUG_ENABLE		(1 << 28) /* LPT:LP+ & BXT */
8055 #define  BXT_DDIA_HPD_INVERT            (1 << 27)
8056 #define  PORTA_HOTPLUG_STATUS_MASK	(3 << 24) /* SPT+ & BXT */
8057 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
8058 #define  PORTA_HOTPLUG_SHORT_DETECT	(1 << 24) /* SPT+ & BXT */
8059 #define  PORTA_HOTPLUG_LONG_DETECT	(2 << 24) /* SPT+ & BXT */
8060 #define  PORTD_HOTPLUG_ENABLE		(1 << 20)
8061 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
8062 #define  PORTD_PULSE_DURATION_4_5ms	(1 << 18) /* pre-LPT */
8063 #define  PORTD_PULSE_DURATION_6ms	(2 << 18) /* pre-LPT */
8064 #define  PORTD_PULSE_DURATION_100ms	(3 << 18) /* pre-LPT */
8065 #define  PORTD_PULSE_DURATION_MASK	(3 << 18) /* pre-LPT */
8066 #define  PORTD_HOTPLUG_STATUS_MASK	(3 << 16)
8067 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
8068 #define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
8069 #define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
8070 #define  PORTC_HOTPLUG_ENABLE		(1 << 12)
8071 #define  BXT_DDIC_HPD_INVERT            (1 << 11)
8072 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
8073 #define  PORTC_PULSE_DURATION_4_5ms	(1 << 10) /* pre-LPT */
8074 #define  PORTC_PULSE_DURATION_6ms	(2 << 10) /* pre-LPT */
8075 #define  PORTC_PULSE_DURATION_100ms	(3 << 10) /* pre-LPT */
8076 #define  PORTC_PULSE_DURATION_MASK	(3 << 10) /* pre-LPT */
8077 #define  PORTC_HOTPLUG_STATUS_MASK	(3 << 8)
8078 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
8079 #define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
8080 #define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
8081 #define  PORTB_HOTPLUG_ENABLE		(1 << 4)
8082 #define  BXT_DDIB_HPD_INVERT            (1 << 3)
8083 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
8084 #define  PORTB_PULSE_DURATION_4_5ms	(1 << 2) /* pre-LPT */
8085 #define  PORTB_PULSE_DURATION_6ms	(2 << 2) /* pre-LPT */
8086 #define  PORTB_PULSE_DURATION_100ms	(3 << 2) /* pre-LPT */
8087 #define  PORTB_PULSE_DURATION_MASK	(3 << 2) /* pre-LPT */
8088 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
8089 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
8090 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
8091 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
8092 #define  BXT_DDI_HPD_INVERT_MASK	(BXT_DDIA_HPD_INVERT | \
8093 					BXT_DDIB_HPD_INVERT | \
8094 					BXT_DDIC_HPD_INVERT)
8095 
8096 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
8097 #define  PORTE_HOTPLUG_ENABLE		(1 << 4)
8098 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
8099 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
8100 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
8101 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
8102 
8103 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
8104  * functionality covered in PCH_PORT_HOTPLUG is split into
8105  * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
8106  */
8107 
8108 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
8109 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(port)		(0x8 << (4 * (port)))
8110 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)	(0x3 << (4 * (port)))
8111 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)		(0x0 << (4 * (port)))
8112 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)	(0x1 << (4 * (port)))
8113 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)	(0x2 << (4 * (port)))
8114 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)	(0x3 << (4 * (port)))
8115 
8116 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
8117 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
8118 
8119 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
8120 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
8121 
8122 /* Icelake DSC Rate Control Range Parameter Registers */
8123 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
8124 #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
8125 #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
8126 #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
8127 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
8128 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
8129 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
8130 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
8131 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
8132 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
8133 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
8134 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
8135 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8136 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
8137 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
8138 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8139 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
8140 							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
8141 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8142 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
8143 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
8144 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8145 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
8146 							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
8147 #define RC_BPG_OFFSET_SHIFT			10
8148 #define RC_MAX_QP_SHIFT				5
8149 #define RC_MIN_QP_SHIFT				0
8150 
8151 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
8152 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
8153 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
8154 #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
8155 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
8156 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
8157 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
8158 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
8159 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
8160 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
8161 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
8162 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
8163 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8164 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
8165 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
8166 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8167 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
8168 							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
8169 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8170 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
8171 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
8172 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8173 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
8174 							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
8175 
8176 #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
8177 #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
8178 #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
8179 #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
8180 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
8181 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
8182 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
8183 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
8184 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
8185 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
8186 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
8187 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
8188 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8189 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
8190 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
8191 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8192 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
8193 							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
8194 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8195 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
8196 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
8197 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8198 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
8199 							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
8200 
8201 #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
8202 #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
8203 #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
8204 #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
8205 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
8206 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
8207 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
8208 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
8209 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
8210 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
8211 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
8212 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
8213 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8214 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
8215 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
8216 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8217 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
8218 							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
8219 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
8220 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
8221 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
8222 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
8223 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
8224 							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
8225 
8226 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
8227 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
8228 
8229 #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
8230 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
8231 #define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
8232 					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
8233 					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
8234 					 ICP_TC_HPD_ENABLE(PORT_TC1))
8235 #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
8236 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
8237 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
8238 #define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
8239 					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
8240 					 ICP_TC_HPD_ENABLE_MASK)
8241 
8242 #define _PCH_DPLL_A              0xc6014
8243 #define _PCH_DPLL_B              0xc6018
8244 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8245 
8246 #define _PCH_FPA0                0xc6040
8247 #define  FP_CB_TUNE		(0x3 << 22)
8248 #define _PCH_FPA1                0xc6044
8249 #define _PCH_FPB0                0xc6048
8250 #define _PCH_FPB1                0xc604c
8251 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8252 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8253 
8254 #define PCH_DPLL_TEST           _MMIO(0xc606c)
8255 
8256 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
8257 #define  DREF_CONTROL_MASK      0x7fc3
8258 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
8259 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2 << 13)
8260 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3 << 13)
8261 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3 << 13)
8262 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
8263 #define  DREF_SSC_SOURCE_ENABLE                 (2 << 11)
8264 #define  DREF_SSC_SOURCE_MASK			(3 << 11)
8265 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
8266 #define  DREF_NONSPREAD_CK505_ENABLE		(1 << 9)
8267 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2 << 9)
8268 #define  DREF_NONSPREAD_SOURCE_MASK		(3 << 9)
8269 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
8270 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2 << 7)
8271 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3 << 7)
8272 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
8273 #define  DREF_SSC4_CENTERSPREAD                 (1 << 6)
8274 #define  DREF_SSC1_DISABLE                      (0 << 1)
8275 #define  DREF_SSC1_ENABLE                       (1 << 1)
8276 #define  DREF_SSC4_DISABLE                      (0)
8277 #define  DREF_SSC4_ENABLE                       (1)
8278 
8279 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
8280 #define  FDL_TP1_TIMER_SHIFT    12
8281 #define  FDL_TP1_TIMER_MASK     (3 << 12)
8282 #define  FDL_TP2_TIMER_SHIFT    10
8283 #define  FDL_TP2_TIMER_MASK     (3 << 10)
8284 #define  RAWCLK_FREQ_MASK       0x3ff
8285 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
8286 #define  CNP_RAWCLK_DIV(div)	((div) << 16)
8287 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
8288 #define  CNP_RAWCLK_DEN(den)	((den) << 26)
8289 #define  ICP_RAWCLK_NUM(num)	((num) << 11)
8290 
8291 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
8292 
8293 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
8294 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
8295 
8296 #define PCH_DPLL_SEL		_MMIO(0xc7000)
8297 #define	 TRANS_DPLLB_SEL(pipe)		(1 << ((pipe) * 4))
8298 #define	 TRANS_DPLLA_SEL(pipe)		0
8299 #define  TRANS_DPLL_ENABLE(pipe)	(1 << ((pipe) * 4 + 3))
8300 
8301 /* transcoder */
8302 
8303 #define _PCH_TRANS_HTOTAL_A		0xe0000
8304 #define  TRANS_HTOTAL_SHIFT		16
8305 #define  TRANS_HACTIVE_SHIFT		0
8306 #define _PCH_TRANS_HBLANK_A		0xe0004
8307 #define  TRANS_HBLANK_END_SHIFT		16
8308 #define  TRANS_HBLANK_START_SHIFT	0
8309 #define _PCH_TRANS_HSYNC_A		0xe0008
8310 #define  TRANS_HSYNC_END_SHIFT		16
8311 #define  TRANS_HSYNC_START_SHIFT	0
8312 #define _PCH_TRANS_VTOTAL_A		0xe000c
8313 #define  TRANS_VTOTAL_SHIFT		16
8314 #define  TRANS_VACTIVE_SHIFT		0
8315 #define _PCH_TRANS_VBLANK_A		0xe0010
8316 #define  TRANS_VBLANK_END_SHIFT		16
8317 #define  TRANS_VBLANK_START_SHIFT	0
8318 #define _PCH_TRANS_VSYNC_A		0xe0014
8319 #define  TRANS_VSYNC_END_SHIFT		16
8320 #define  TRANS_VSYNC_START_SHIFT	0
8321 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
8322 
8323 #define _PCH_TRANSA_DATA_M1	0xe0030
8324 #define _PCH_TRANSA_DATA_N1	0xe0034
8325 #define _PCH_TRANSA_DATA_M2	0xe0038
8326 #define _PCH_TRANSA_DATA_N2	0xe003c
8327 #define _PCH_TRANSA_LINK_M1	0xe0040
8328 #define _PCH_TRANSA_LINK_N1	0xe0044
8329 #define _PCH_TRANSA_LINK_M2	0xe0048
8330 #define _PCH_TRANSA_LINK_N2	0xe004c
8331 
8332 /* Per-transcoder DIP controls (PCH) */
8333 #define _VIDEO_DIP_CTL_A         0xe0200
8334 #define _VIDEO_DIP_DATA_A        0xe0208
8335 #define _VIDEO_DIP_GCP_A         0xe0210
8336 #define  GCP_COLOR_INDICATION		(1 << 2)
8337 #define  GCP_DEFAULT_PHASE_ENABLE	(1 << 1)
8338 #define  GCP_AV_MUTE			(1 << 0)
8339 
8340 #define _VIDEO_DIP_CTL_B         0xe1200
8341 #define _VIDEO_DIP_DATA_B        0xe1208
8342 #define _VIDEO_DIP_GCP_B         0xe1210
8343 
8344 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8345 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8346 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8347 
8348 /* Per-transcoder DIP controls (VLV) */
8349 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
8350 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
8351 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
8352 
8353 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
8354 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
8355 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
8356 
8357 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
8358 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
8359 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
8360 
8361 #define VLV_TVIDEO_DIP_CTL(pipe) \
8362 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8363 	       _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8364 #define VLV_TVIDEO_DIP_DATA(pipe) \
8365 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8366 	       _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8367 #define VLV_TVIDEO_DIP_GCP(pipe) \
8368 	_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8369 		_VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8370 
8371 /* Haswell DIP controls */
8372 
8373 #define _HSW_VIDEO_DIP_CTL_A		0x60200
8374 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
8375 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
8376 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
8377 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
8378 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
8379 #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
8380 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
8381 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
8382 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
8383 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
8384 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
8385 #define _HSW_VIDEO_DIP_GCP_A		0x60210
8386 
8387 #define _HSW_VIDEO_DIP_CTL_B		0x61200
8388 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
8389 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
8390 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
8391 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
8392 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
8393 #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
8394 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
8395 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
8396 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
8397 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
8398 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
8399 #define _HSW_VIDEO_DIP_GCP_B		0x61210
8400 
8401 /* Icelake PPS_DATA and _ECC DIP Registers.
8402  * These are available for transcoders B,C and eDP.
8403  * Adding the _A so as to reuse the _MMIO_TRANS2
8404  * definition, with which it offsets to the right location.
8405  */
8406 
8407 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
8408 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
8409 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
8410 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
8411 
8412 #define HSW_TVIDEO_DIP_CTL(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8413 #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8414 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8415 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8416 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8417 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8418 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8419 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8420 #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8421 #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8422 
8423 #define _HSW_STEREO_3D_CTL_A		0x70020
8424 #define   S3D_ENABLE			(1 << 31)
8425 #define _HSW_STEREO_3D_CTL_B		0x71020
8426 
8427 #define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8428 
8429 #define _PCH_TRANS_HTOTAL_B          0xe1000
8430 #define _PCH_TRANS_HBLANK_B          0xe1004
8431 #define _PCH_TRANS_HSYNC_B           0xe1008
8432 #define _PCH_TRANS_VTOTAL_B          0xe100c
8433 #define _PCH_TRANS_VBLANK_B          0xe1010
8434 #define _PCH_TRANS_VSYNC_B           0xe1014
8435 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8436 
8437 #define PCH_TRANS_HTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8438 #define PCH_TRANS_HBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8439 #define PCH_TRANS_HSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8440 #define PCH_TRANS_VTOTAL(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8441 #define PCH_TRANS_VBLANK(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8442 #define PCH_TRANS_VSYNC(pipe)		_MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8443 #define PCH_TRANS_VSYNCSHIFT(pipe)	_MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8444 
8445 #define _PCH_TRANSB_DATA_M1	0xe1030
8446 #define _PCH_TRANSB_DATA_N1	0xe1034
8447 #define _PCH_TRANSB_DATA_M2	0xe1038
8448 #define _PCH_TRANSB_DATA_N2	0xe103c
8449 #define _PCH_TRANSB_LINK_M1	0xe1040
8450 #define _PCH_TRANSB_LINK_N1	0xe1044
8451 #define _PCH_TRANSB_LINK_M2	0xe1048
8452 #define _PCH_TRANSB_LINK_N2	0xe104c
8453 
8454 #define PCH_TRANS_DATA_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8455 #define PCH_TRANS_DATA_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8456 #define PCH_TRANS_DATA_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8457 #define PCH_TRANS_DATA_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8458 #define PCH_TRANS_LINK_M1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8459 #define PCH_TRANS_LINK_N1(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8460 #define PCH_TRANS_LINK_M2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8461 #define PCH_TRANS_LINK_N2(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8462 
8463 #define _PCH_TRANSACONF              0xf0008
8464 #define _PCH_TRANSBCONF              0xf1008
8465 #define PCH_TRANSCONF(pipe)	_MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8466 #define LPT_TRANSCONF		PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8467 #define  TRANS_DISABLE          (0 << 31)
8468 #define  TRANS_ENABLE           (1 << 31)
8469 #define  TRANS_STATE_MASK       (1 << 30)
8470 #define  TRANS_STATE_DISABLE    (0 << 30)
8471 #define  TRANS_STATE_ENABLE     (1 << 30)
8472 #define  TRANS_FRAME_START_DELAY_MASK	(3 << 27) /* ibx */
8473 #define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
8474 #define  TRANS_INTERLACE_MASK   (7 << 21)
8475 #define  TRANS_PROGRESSIVE      (0 << 21)
8476 #define  TRANS_INTERLACED       (3 << 21)
8477 #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8478 #define  TRANS_8BPC             (0 << 5)
8479 #define  TRANS_10BPC            (1 << 5)
8480 #define  TRANS_6BPC             (2 << 5)
8481 #define  TRANS_12BPC            (3 << 5)
8482 
8483 #define _TRANSA_CHICKEN1	 0xf0060
8484 #define _TRANSB_CHICKEN1	 0xf1060
8485 #define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8486 #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	(1 << 10)
8487 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1 << 4)
8488 #define _TRANSA_CHICKEN2	 0xf0064
8489 #define _TRANSB_CHICKEN2	 0xf1064
8490 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8491 #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1 << 31)
8492 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1 << 29)
8493 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3 << 27)
8494 #define  TRANS_CHICKEN2_FRAME_START_DELAY(x)		((x) << 27) /* 0-3 */
8495 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1 << 26)
8496 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1 << 25)
8497 
8498 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
8499 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
8500 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
8501 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8502 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8503 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
8504 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
8505 #define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
8506 #define  SPT_PWM_GRANULARITY		(1 << 0)
8507 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
8508 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
8509 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
8510 #define  LPT_PWM_GRANULARITY		(1 << 5)
8511 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
8512 
8513 #define _FDI_RXA_CHICKEN        0xc200c
8514 #define _FDI_RXB_CHICKEN        0xc2010
8515 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1 << 1)
8516 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
8517 #define FDI_RX_CHICKEN(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8518 
8519 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
8520 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8521 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8522 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8523 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8524 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8525 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
8526 
8527 /* CPU: FDI_TX */
8528 #define _FDI_TXA_CTL            0x60100
8529 #define _FDI_TXB_CTL            0x61100
8530 #define FDI_TX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8531 #define  FDI_TX_DISABLE         (0 << 31)
8532 #define  FDI_TX_ENABLE          (1 << 31)
8533 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8534 #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
8535 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
8536 #define  FDI_LINK_TRAIN_NONE            (3 << 28)
8537 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8538 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
8539 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
8540 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
8541 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8542 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8543 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
8544 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
8545 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8546    SNB has different settings. */
8547 /* SNB A-stepping */
8548 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8549 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8550 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8551 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8552 /* SNB B-stepping */
8553 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
8554 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
8555 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
8556 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
8557 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
8558 #define  FDI_DP_PORT_WIDTH_SHIFT		19
8559 #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
8560 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8561 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
8562 /* Ironlake: hardwired to 1 */
8563 #define  FDI_TX_PLL_ENABLE              (1 << 14)
8564 
8565 /* Ivybridge has different bits for lolz */
8566 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8567 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
8568 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
8569 #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
8570 
8571 /* both Tx and Rx */
8572 #define  FDI_COMPOSITE_SYNC		(1 << 11)
8573 #define  FDI_LINK_TRAIN_AUTO		(1 << 10)
8574 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8575 #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
8576 
8577 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8578 #define _FDI_RXA_CTL             0xf000c
8579 #define _FDI_RXB_CTL             0xf100c
8580 #define FDI_RX_CTL(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8581 #define  FDI_RX_ENABLE          (1 << 31)
8582 /* train, dp width same as FDI_TX */
8583 #define  FDI_FS_ERRC_ENABLE		(1 << 27)
8584 #define  FDI_FE_ERRC_ENABLE		(1 << 26)
8585 #define  FDI_RX_POLARITY_REVERSED_LPT	(1 << 16)
8586 #define  FDI_8BPC                       (0 << 16)
8587 #define  FDI_10BPC                      (1 << 16)
8588 #define  FDI_6BPC                       (2 << 16)
8589 #define  FDI_12BPC                      (3 << 16)
8590 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
8591 #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
8592 #define  FDI_RX_PLL_ENABLE              (1 << 13)
8593 #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
8594 #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
8595 #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
8596 #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
8597 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
8598 #define  FDI_PCDCLK	                (1 << 4)
8599 /* CPT */
8600 #define  FDI_AUTO_TRAINING			(1 << 10)
8601 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
8602 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1 << 8)
8603 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2 << 8)
8604 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3 << 8)
8605 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3 << 8)
8606 
8607 #define _FDI_RXA_MISC			0xf0010
8608 #define _FDI_RXB_MISC			0xf1010
8609 #define  FDI_RX_PWRDN_LANE1_MASK	(3 << 26)
8610 #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x) << 26)
8611 #define  FDI_RX_PWRDN_LANE0_MASK	(3 << 24)
8612 #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x) << 24)
8613 #define  FDI_RX_TP1_TO_TP2_48		(2 << 20)
8614 #define  FDI_RX_TP1_TO_TP2_64		(3 << 20)
8615 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
8616 #define FDI_RX_MISC(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8617 
8618 #define _FDI_RXA_TUSIZE1        0xf0030
8619 #define _FDI_RXA_TUSIZE2        0xf0038
8620 #define _FDI_RXB_TUSIZE1        0xf1030
8621 #define _FDI_RXB_TUSIZE2        0xf1038
8622 #define FDI_RX_TUSIZE1(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8623 #define FDI_RX_TUSIZE2(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8624 
8625 /* FDI_RX interrupt register format */
8626 #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
8627 #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
8628 #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
8629 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
8630 #define FDI_RX_FS_CODE_ERR              (1 << 6)
8631 #define FDI_RX_FE_CODE_ERR              (1 << 5)
8632 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
8633 #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
8634 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
8635 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
8636 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
8637 
8638 #define _FDI_RXA_IIR            0xf0014
8639 #define _FDI_RXA_IMR            0xf0018
8640 #define _FDI_RXB_IIR            0xf1014
8641 #define _FDI_RXB_IMR            0xf1018
8642 #define FDI_RX_IIR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8643 #define FDI_RX_IMR(pipe)	_MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8644 
8645 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
8646 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
8647 
8648 #define PCH_LVDS	_MMIO(0xe1180)
8649 #define  LVDS_DETECTED	(1 << 1)
8650 
8651 #define _PCH_DP_B		0xe4100
8652 #define PCH_DP_B		_MMIO(_PCH_DP_B)
8653 #define _PCH_DPB_AUX_CH_CTL	0xe4110
8654 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
8655 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
8656 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
8657 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
8658 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
8659 
8660 #define _PCH_DP_C		0xe4200
8661 #define PCH_DP_C		_MMIO(_PCH_DP_C)
8662 #define _PCH_DPC_AUX_CH_CTL	0xe4210
8663 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
8664 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
8665 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
8666 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
8667 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
8668 
8669 #define _PCH_DP_D		0xe4300
8670 #define PCH_DP_D		_MMIO(_PCH_DP_D)
8671 #define _PCH_DPD_AUX_CH_CTL	0xe4310
8672 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
8673 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
8674 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
8675 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
8676 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
8677 
8678 #define PCH_DP_AUX_CH_CTL(aux_ch)		_MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8679 #define PCH_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8680 
8681 /* CPT */
8682 #define _TRANS_DP_CTL_A		0xe0300
8683 #define _TRANS_DP_CTL_B		0xe1300
8684 #define _TRANS_DP_CTL_C		0xe2300
8685 #define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8686 #define  TRANS_DP_OUTPUT_ENABLE	(1 << 31)
8687 #define  TRANS_DP_PORT_SEL_MASK		(3 << 29)
8688 #define  TRANS_DP_PORT_SEL_NONE		(3 << 29)
8689 #define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)
8690 #define  TRANS_DP_AUDIO_ONLY	(1 << 26)
8691 #define  TRANS_DP_ENH_FRAMING	(1 << 18)
8692 #define  TRANS_DP_8BPC		(0 << 9)
8693 #define  TRANS_DP_10BPC		(1 << 9)
8694 #define  TRANS_DP_6BPC		(2 << 9)
8695 #define  TRANS_DP_12BPC		(3 << 9)
8696 #define  TRANS_DP_BPC_MASK	(3 << 9)
8697 #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1 << 4)
8698 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
8699 #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1 << 3)
8700 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
8701 #define  TRANS_DP_SYNC_MASK	(3 << 3)
8702 
8703 /* SNB eDP training params */
8704 /* SNB A-stepping */
8705 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8706 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8707 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8708 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8709 /* SNB B-stepping */
8710 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
8711 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
8712 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
8713 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
8714 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
8715 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
8716 
8717 /* IVB */
8718 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
8719 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
8720 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
8721 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
8722 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
8723 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
8724 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
8725 
8726 /* legacy values */
8727 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
8728 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
8729 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
8730 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
8731 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
8732 
8733 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
8734 
8735 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
8736 
8737 #define  RC6_LOCATION				_MMIO(0xD40)
8738 #define	   RC6_CTX_IN_DRAM			(1 << 0)
8739 #define  RC6_CTX_BASE				_MMIO(0xD48)
8740 #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
8741 #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
8742 #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
8743 #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
8744 #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
8745 #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
8746 #define    IDLE_TIME_MASK			0xFFFFF
8747 #define  FORCEWAKE				_MMIO(0xA18C)
8748 #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
8749 #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
8750 #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
8751 #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
8752 #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
8753 #define  FORCEWAKE_ACK				_MMIO(0x130090)
8754 #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
8755 #define   VLV_GTLC_RENDER_CTX_EXISTS		(1 << 25)
8756 #define   VLV_GTLC_MEDIA_CTX_EXISTS		(1 << 24)
8757 #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
8758 
8759 #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
8760 #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
8761 #define   VLV_GTLC_ALLOWWAKEERR			(1 << 1)
8762 #define   VLV_GTLC_PW_MEDIA_STATUS_MASK		(1 << 5)
8763 #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
8764 #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
8765 #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
8766 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
8767 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
8768 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
8769 #define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
8770 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
8771 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
8772 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
8773 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
8774 #define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
8775 #define   FORCEWAKE_KERNEL			BIT(0)
8776 #define   FORCEWAKE_USER			BIT(1)
8777 #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
8778 #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
8779 #define  ECOBUS					_MMIO(0xa180)
8780 #define    FORCEWAKE_MT_ENABLE			(1 << 5)
8781 #define  VLV_SPAREG2H				_MMIO(0xA194)
8782 #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
8783 #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
8784 #define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
8785 
8786 #define POWERGATE_ENABLE			_MMIO(0xa210)
8787 #define    VDN_HCP_POWERGATE_ENABLE(n)		BIT(((n) * 2) + 3)
8788 #define    VDN_MFX_POWERGATE_ENABLE(n)		BIT(((n) * 2) + 4)
8789 
8790 #define  GTFIFODBG				_MMIO(0x120000)
8791 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
8792 #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
8793 #define    GT_FIFO_SBDROPERR			(1 << 6)
8794 #define    GT_FIFO_BLOBDROPERR			(1 << 5)
8795 #define    GT_FIFO_SB_READ_ABORTERR		(1 << 4)
8796 #define    GT_FIFO_DROPERR			(1 << 3)
8797 #define    GT_FIFO_OVFERR			(1 << 2)
8798 #define    GT_FIFO_IAWRERR			(1 << 1)
8799 #define    GT_FIFO_IARDERR			(1 << 0)
8800 
8801 #define  GTFIFOCTL				_MMIO(0x120008)
8802 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
8803 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
8804 #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
8805 #define    GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
8806 
8807 #define  HSW_IDICR				_MMIO(0x9008)
8808 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
8809 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
8810 #define    EDRAM_ENABLED			0x1
8811 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
8812 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
8813 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
8814 
8815 #define GEN6_UCGCTL1				_MMIO(0x9400)
8816 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE		(1 << 22)
8817 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
8818 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
8819 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
8820 
8821 #define GEN6_UCGCTL2				_MMIO(0x9404)
8822 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
8823 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
8824 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
8825 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
8826 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
8827 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
8828 
8829 #define GEN6_UCGCTL3				_MMIO(0x9408)
8830 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE		(1 << 20)
8831 
8832 #define GEN7_UCGCTL4				_MMIO(0x940c)
8833 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1 << 25)
8834 #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE	(1 << 14)
8835 
8836 #define GEN6_RCGCTL1				_MMIO(0x9410)
8837 #define GEN6_RCGCTL2				_MMIO(0x9414)
8838 #define GEN6_RSTCTL				_MMIO(0x9420)
8839 
8840 #define GEN8_UCGCTL6				_MMIO(0x9430)
8841 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1 << 24)
8842 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1 << 14)
8843 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8844 
8845 #define GEN6_GFXPAUSE				_MMIO(0xA000)
8846 #define GEN6_RPNSWREQ				_MMIO(0xA008)
8847 #define   GEN6_TURBO_DISABLE			(1 << 31)
8848 #define   GEN6_FREQUENCY(x)			((x) << 25)
8849 #define   HSW_FREQUENCY(x)			((x) << 24)
8850 #define   GEN9_FREQUENCY(x)			((x) << 23)
8851 #define   GEN6_OFFSET(x)			((x) << 19)
8852 #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
8853 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
8854 #define GEN6_RC_CONTROL				_MMIO(0xA090)
8855 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1 << 16)
8856 #define   GEN6_RC_CTL_RC6p_ENABLE		(1 << 17)
8857 #define   GEN6_RC_CTL_RC6_ENABLE		(1 << 18)
8858 #define   GEN6_RC_CTL_RC1e_ENABLE		(1 << 20)
8859 #define   GEN6_RC_CTL_RC7_ENABLE		(1 << 22)
8860 #define   VLV_RC_CTL_CTX_RST_PARALLEL		(1 << 24)
8861 #define   GEN7_RC_CTL_TO_MODE			(1 << 28)
8862 #define   GEN6_RC_CTL_EI_MODE(x)		((x) << 27)
8863 #define   GEN6_RC_CTL_HW_ENABLE			(1 << 31)
8864 #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
8865 #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
8866 #define GEN6_RPSTAT1				_MMIO(0xA01C)
8867 #define   GEN6_CAGF_SHIFT			8
8868 #define   HSW_CAGF_SHIFT			7
8869 #define   GEN9_CAGF_SHIFT			23
8870 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
8871 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
8872 #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
8873 #define GEN6_RP_CONTROL				_MMIO(0xA024)
8874 #define   GEN6_RP_MEDIA_TURBO			(1 << 11)
8875 #define   GEN6_RP_MEDIA_MODE_MASK		(3 << 9)
8876 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3 << 9)
8877 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2 << 9)
8878 #define   GEN6_RP_MEDIA_HW_MODE			(1 << 9)
8879 #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
8880 #define   GEN6_RP_MEDIA_IS_GFX			(1 << 8)
8881 #define   GEN6_RP_ENABLE			(1 << 7)
8882 #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
8883 #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
8884 #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
8885 #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
8886 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
8887 #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
8888 #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
8889 #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
8890 #define   GEN6_RP_EI_MASK			0xffffff
8891 #define   GEN6_CURICONT_MASK			GEN6_RP_EI_MASK
8892 #define GEN6_RP_CUR_UP				_MMIO(0xA054)
8893 #define   GEN6_CURBSYTAVG_MASK			GEN6_RP_EI_MASK
8894 #define GEN6_RP_PREV_UP				_MMIO(0xA058)
8895 #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
8896 #define   GEN6_CURIAVG_MASK			GEN6_RP_EI_MASK
8897 #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
8898 #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
8899 #define GEN6_RP_UP_EI				_MMIO(0xA068)
8900 #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
8901 #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
8902 #define GEN6_RPDEUHWTC				_MMIO(0xA080)
8903 #define GEN6_RPDEUC				_MMIO(0xA084)
8904 #define GEN6_RPDEUCSW				_MMIO(0xA088)
8905 #define GEN6_RC_STATE				_MMIO(0xA094)
8906 #define   RC_SW_TARGET_STATE_SHIFT		16
8907 #define   RC_SW_TARGET_STATE_MASK		(7 << RC_SW_TARGET_STATE_SHIFT)
8908 #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
8909 #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
8910 #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
8911 #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
8912 #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
8913 #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
8914 #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
8915 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
8916 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
8917 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
8918 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
8919 #define VLV_RCEDATA				_MMIO(0xA0BC)
8920 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
8921 #define GEN6_PMINTRMSK				_MMIO(0xA168)
8922 #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC	(1 << 31)
8923 #define   ARAT_EXPIRED_INTRMSK			(1 << 9)
8924 #define GEN8_MISC_CTRL0				_MMIO(0xA180)
8925 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
8926 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
8927 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
8928 #define GEN9_PG_ENABLE				_MMIO(0xA210)
8929 #define GEN9_RENDER_PG_ENABLE			REG_BIT(0)
8930 #define GEN9_MEDIA_PG_ENABLE			REG_BIT(1)
8931 #define GEN11_MEDIA_SAMPLER_PG_ENABLE		REG_BIT(2)
8932 #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
8933 #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
8934 #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
8935 
8936 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
8937 #define  PIXEL_OVERLAP_CNT_MASK			(3 << 30)
8938 #define  PIXEL_OVERLAP_CNT_SHIFT		30
8939 
8940 #define GEN6_PMISR				_MMIO(0x44020)
8941 #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
8942 #define GEN6_PMIIR				_MMIO(0x44028)
8943 #define GEN6_PMIER				_MMIO(0x4402C)
8944 #define  GEN6_PM_MBOX_EVENT			(1 << 25)
8945 #define  GEN6_PM_THERMAL_EVENT			(1 << 24)
8946 
8947 /*
8948  * For Gen11 these are in the upper word of the GPM_WGBOXPERF
8949  * registers. Shifting is handled on accessing the imr and ier.
8950  */
8951 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1 << 6)
8952 #define  GEN6_PM_RP_UP_THRESHOLD		(1 << 5)
8953 #define  GEN6_PM_RP_DOWN_THRESHOLD		(1 << 4)
8954 #define  GEN6_PM_RP_UP_EI_EXPIRED		(1 << 2)
8955 #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1 << 1)
8956 #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_EI_EXPIRED   | \
8957 						 GEN6_PM_RP_UP_THRESHOLD    | \
8958 						 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8959 						 GEN6_PM_RP_DOWN_THRESHOLD  | \
8960 						 GEN6_PM_RP_DOWN_TIMEOUT)
8961 
8962 #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
8963 #define GEN7_GT_SCRATCH_REG_NUM			8
8964 
8965 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
8966 #define VLV_GFX_CLK_STATUS_BIT			(1 << 3)
8967 #define VLV_GFX_CLK_FORCE_ON_BIT		(1 << 2)
8968 
8969 #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
8970 #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
8971 #define   VLV_COUNT_RANGE_HIGH			(1 << 15)
8972 #define   VLV_MEDIA_RC0_COUNT_EN		(1 << 5)
8973 #define   VLV_RENDER_RC0_COUNT_EN		(1 << 4)
8974 #define   VLV_MEDIA_RC6_COUNT_EN		(1 << 1)
8975 #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
8976 #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
8977 #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
8978 #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
8979 
8980 #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
8981 #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
8982 #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
8983 #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
8984 
8985 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
8986 #define   GEN6_PCODE_READY			(1 << 31)
8987 #define   GEN6_PCODE_ERROR_MASK			0xFF
8988 #define     GEN6_PCODE_SUCCESS			0x0
8989 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
8990 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8991 #define     GEN6_PCODE_TIMEOUT			0x3
8992 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
8993 #define     GEN7_PCODE_TIMEOUT			0x2
8994 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
8995 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
8996 #define     GEN11_PCODE_LOCKED			0x6
8997 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8998 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
8999 #define   GEN6_PCODE_READ_RC6VIDS		0x5
9000 #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
9001 #define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
9002 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
9003 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
9004 #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
9005 #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT	8
9006 #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT	16
9007 #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT	24
9008 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
9009 #define   SKL_PCODE_CDCLK_CONTROL		0x7
9010 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
9011 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
9012 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
9013 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
9014 #define   GEN6_READ_OC_PARAMS			0xc
9015 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
9016 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
9017 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
9018 #define   GEN6_PCODE_READ_D_COMP		0x10
9019 #define   GEN6_PCODE_WRITE_D_COMP		0x11
9020 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
9021 #define   DISPLAY_IPS_CONTROL			0x19
9022             /* See also IPS_CTL */
9023 #define     IPS_PCODE_CONTROL			(1 << 30)
9024 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
9025 #define   GEN9_PCODE_SAGV_CONTROL		0x21
9026 #define     GEN9_SAGV_DISABLE			0x0
9027 #define     GEN9_SAGV_IS_DISABLED		0x1
9028 #define     GEN9_SAGV_ENABLE			0x3
9029 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
9030 #define GEN6_PCODE_DATA				_MMIO(0x138128)
9031 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
9032 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
9033 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
9034 
9035 #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
9036 #define   GEN6_CORE_CPD_STATE_MASK	(7 << 4)
9037 #define   GEN6_RCn_MASK			7
9038 #define   GEN6_RC0			0
9039 #define   GEN6_RC3			2
9040 #define   GEN6_RC6			3
9041 #define   GEN6_RC7			4
9042 
9043 #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
9044 #define   GEN8_LSLICESTAT_MASK		0x7
9045 
9046 #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
9047 #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
9048 #define   CHV_SS_PG_ENABLE		(1 << 1)
9049 #define   CHV_EU08_PG_ENABLE		(1 << 9)
9050 #define   CHV_EU19_PG_ENABLE		(1 << 17)
9051 #define   CHV_EU210_PG_ENABLE		(1 << 25)
9052 
9053 #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
9054 #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
9055 #define   CHV_EU311_PG_ENABLE		(1 << 1)
9056 
9057 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
9058 #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
9059 					      ((slice) % 3) * 0x4)
9060 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
9061 #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
9062 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9063 
9064 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
9065 #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
9066 					      ((slice) % 3) * 0x8)
9067 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
9068 #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9069 					      ((slice) % 3) * 0x8)
9070 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
9071 #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
9072 #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)
9073 #define   GEN9_PGCTL_SSA_EU311_ACK	(1 << 6)
9074 #define   GEN9_PGCTL_SSB_EU08_ACK	(1 << 8)
9075 #define   GEN9_PGCTL_SSB_EU19_ACK	(1 << 10)
9076 #define   GEN9_PGCTL_SSB_EU210_ACK	(1 << 12)
9077 #define   GEN9_PGCTL_SSB_EU311_ACK	(1 << 14)
9078 
9079 #define GEN7_MISCCPCTL				_MMIO(0x9424)
9080 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
9081 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)
9082 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
9083 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
9084 
9085 #define GEN8_GARBCNTL				_MMIO(0xB004)
9086 #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
9087 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
9088 #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
9089 #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
9090 
9091 #define GEN11_GLBLINVL				_MMIO(0xB404)
9092 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
9093 #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
9094 
9095 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
9096 #define   DFR_DISABLE			(1 << 9)
9097 
9098 #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
9099 #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
9100 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
9101 #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
9102 
9103 #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
9104 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC	(1 << 9)
9105 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
9106 
9107 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
9108 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
9109 
9110 /* IVYBRIDGE DPF */
9111 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
9112 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
9113 #define   GEN7_PARITY_ERROR_VALID	(1 << 13)
9114 #define   GEN7_L3CDERRST1_BANK_MASK	(3 << 11)
9115 #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7 << 8)
9116 #define GEN7_PARITY_ERROR_ROW(reg) \
9117 		(((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
9118 #define GEN7_PARITY_ERROR_BANK(reg) \
9119 		(((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
9120 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
9121 		(((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
9122 #define   GEN7_L3CDERRST1_ENABLE	(1 << 7)
9123 
9124 #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9125 #define GEN7_L3LOG_SIZE			0x80
9126 
9127 #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
9128 #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
9129 #define   GEN7_MAX_PS_THREAD_DEP		(8 << 12)
9130 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1 << 10)
9131 #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1 << 4)
9132 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1 << 3)
9133 
9134 #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
9135 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
9136 #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
9137 
9138 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
9139 #define   FLOW_CONTROL_ENABLE		(1 << 15)
9140 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
9141 #define   STALL_DOP_GATING_DISABLE		(1 << 5)
9142 #define   THROTTLE_12_5				(7 << 2)
9143 #define   DISABLE_EARLY_EOT			(1 << 1)
9144 
9145 #define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)
9146 #define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)
9147 #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)
9148 
9149 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
9150 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
9151 #define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
9152 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
9153 
9154 #define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)
9155 #define   GEN12_DISABLE_TDL_PUSH	REG_BIT(9)
9156 #define   GEN11_DIS_PICK_2ND_EU		REG_BIT(7)
9157 
9158 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
9159 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
9160 
9161 #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
9162 #define   GEN8_ST_PO_DISABLE		(1 << 13)
9163 
9164 #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
9165 #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
9166 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
9167 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
9168 #define   CNL_FAST_ANISO_L1_BANKING_FIX	(1 << 4)
9169 #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
9170 
9171 #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
9172 #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR	(1 << 8)
9173 #define   GEN9_ENABLE_YV12_BUGFIX	(1 << 4)
9174 #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1 << 2)
9175 
9176 /* Audio */
9177 #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9178 #define   INTEL_AUDIO_DEVCL		0x808629FB
9179 #define   INTEL_AUDIO_DEVBLC		0x80862801
9180 #define   INTEL_AUDIO_DEVCTG		0x80862802
9181 
9182 #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
9183 #define   G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
9184 #define   G4X_ELDV_DEVCTG		(1 << 14)
9185 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
9186 #define   G4X_ELD_ACK			(1 << 4)
9187 #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
9188 
9189 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
9190 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
9191 #define IBX_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9192 						  _IBX_HDMIW_HDMIEDID_B)
9193 #define _IBX_AUD_CNTL_ST_A		0xE20B4
9194 #define _IBX_AUD_CNTL_ST_B		0xE21B4
9195 #define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9196 						  _IBX_AUD_CNTL_ST_B)
9197 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
9198 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
9199 #define   IBX_ELD_ACK			(1 << 4)
9200 #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
9201 #define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))
9202 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
9203 
9204 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
9205 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
9206 #define CPT_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9207 #define _CPT_AUD_CNTL_ST_A		0xE50B4
9208 #define _CPT_AUD_CNTL_ST_B		0xE51B4
9209 #define CPT_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9210 #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
9211 
9212 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
9213 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
9214 #define VLV_HDMIW_HDMIEDID(pipe)	_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9215 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
9216 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
9217 #define VLV_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9218 #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
9219 
9220 /* These are the 4 32-bit write offset registers for each stream
9221  * output buffer.  It determines the offset from the
9222  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9223  */
9224 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
9225 
9226 #define _IBX_AUD_CONFIG_A		0xe2000
9227 #define _IBX_AUD_CONFIG_B		0xe2100
9228 #define IBX_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9229 #define _CPT_AUD_CONFIG_A		0xe5000
9230 #define _CPT_AUD_CONFIG_B		0xe5100
9231 #define CPT_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9232 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
9233 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
9234 #define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9235 
9236 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
9237 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
9238 #define   AUD_CONFIG_UPPER_N_SHIFT		20
9239 #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
9240 #define   AUD_CONFIG_LOWER_N_SHIFT		4
9241 #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
9242 #define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9243 #define   AUD_CONFIG_N(n) \
9244 	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
9245 	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9246 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
9247 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
9248 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
9249 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)
9250 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)
9251 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)
9252 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)
9253 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)
9254 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)
9255 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)
9256 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)
9257 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)
9258 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)
9259 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)
9260 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)
9261 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)
9262 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
9263 
9264 /* HSW Audio */
9265 #define _HSW_AUD_CONFIG_A		0x65000
9266 #define _HSW_AUD_CONFIG_B		0x65100
9267 #define HSW_AUD_CFG(trans)		_MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9268 
9269 #define _HSW_AUD_MISC_CTRL_A		0x65010
9270 #define _HSW_AUD_MISC_CTRL_B		0x65110
9271 #define HSW_AUD_MISC_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9272 
9273 #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
9274 #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
9275 #define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9276 #define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)
9277 #define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)
9278 #define   AUD_CONFIG_M_MASK		0xfffff
9279 
9280 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
9281 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
9282 #define HSW_AUD_DIP_ELD_CTRL(trans)	_MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9283 
9284 /* Audio Digital Converter */
9285 #define _HSW_AUD_DIG_CNVT_1		0x65080
9286 #define _HSW_AUD_DIG_CNVT_2		0x65180
9287 #define AUD_DIG_CNVT(trans)		_MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9288 #define DIP_PORT_SEL_MASK		0x3
9289 
9290 #define _HSW_AUD_EDID_DATA_A		0x65050
9291 #define _HSW_AUD_EDID_DATA_B		0x65150
9292 #define HSW_AUD_EDID_DATA(trans)	_MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9293 
9294 #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
9295 #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
9296 #define   AUDIO_INACTIVE(trans)		((1 << 3) << ((trans) * 4))
9297 #define   AUDIO_OUTPUT_ENABLE(trans)	((1 << 2) << ((trans) * 4))
9298 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
9299 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
9300 
9301 #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
9302 #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
9303 
9304 #define AUD_FREQ_CNTRL			_MMIO(0x65900)
9305 #define AUD_PIN_BUF_CTL		_MMIO(0x48414)
9306 #define   AUD_PIN_BUF_ENABLE		REG_BIT(31)
9307 
9308 /*
9309  * HSW - ICL power wells
9310  *
9311  * Platforms have up to 3 power well control register sets, each set
9312  * controlling up to 16 power wells via a request/status HW flag tuple:
9313  * - main (HSW_PWR_WELL_CTL[1-4])
9314  * - AUX  (ICL_PWR_WELL_CTL_AUX[1-4])
9315  * - DDI  (ICL_PWR_WELL_CTL_DDI[1-4])
9316  * Each control register set consists of up to 4 registers used by different
9317  * sources that can request a power well to be enabled:
9318  * - BIOS   (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9319  * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9320  * - KVMR   (HSW_PWR_WELL_CTL3)   (only in the main register set)
9321  * - DEBUG  (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9322  */
9323 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
9324 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
9325 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
9326 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
9327 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
9328 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
9329 
9330 /* HSW/BDW power well */
9331 #define   HSW_PW_CTL_IDX_GLOBAL			15
9332 
9333 /* SKL/BXT/GLK/CNL power wells */
9334 #define   SKL_PW_CTL_IDX_PW_2			15
9335 #define   SKL_PW_CTL_IDX_PW_1			14
9336 #define   CNL_PW_CTL_IDX_AUX_F			12
9337 #define   CNL_PW_CTL_IDX_AUX_D			11
9338 #define   GLK_PW_CTL_IDX_AUX_C			10
9339 #define   GLK_PW_CTL_IDX_AUX_B			9
9340 #define   GLK_PW_CTL_IDX_AUX_A			8
9341 #define   CNL_PW_CTL_IDX_DDI_F			6
9342 #define   SKL_PW_CTL_IDX_DDI_D			4
9343 #define   SKL_PW_CTL_IDX_DDI_C			3
9344 #define   SKL_PW_CTL_IDX_DDI_B			2
9345 #define   SKL_PW_CTL_IDX_DDI_A_E		1
9346 #define   GLK_PW_CTL_IDX_DDI_A			1
9347 #define   SKL_PW_CTL_IDX_MISC_IO		0
9348 
9349 /* ICL/TGL - power wells */
9350 #define   TGL_PW_CTL_IDX_PW_5			4
9351 #define   ICL_PW_CTL_IDX_PW_4			3
9352 #define   ICL_PW_CTL_IDX_PW_3			2
9353 #define   ICL_PW_CTL_IDX_PW_2			1
9354 #define   ICL_PW_CTL_IDX_PW_1			0
9355 
9356 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
9357 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
9358 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
9359 #define   TGL_PW_CTL_IDX_AUX_TBT6		14
9360 #define   TGL_PW_CTL_IDX_AUX_TBT5		13
9361 #define   TGL_PW_CTL_IDX_AUX_TBT4		12
9362 #define   ICL_PW_CTL_IDX_AUX_TBT4		11
9363 #define   TGL_PW_CTL_IDX_AUX_TBT3		11
9364 #define   ICL_PW_CTL_IDX_AUX_TBT3		10
9365 #define   TGL_PW_CTL_IDX_AUX_TBT2		10
9366 #define   ICL_PW_CTL_IDX_AUX_TBT2		9
9367 #define   TGL_PW_CTL_IDX_AUX_TBT1		9
9368 #define   ICL_PW_CTL_IDX_AUX_TBT1		8
9369 #define   TGL_PW_CTL_IDX_AUX_TC6		8
9370 #define   TGL_PW_CTL_IDX_AUX_TC5		7
9371 #define   TGL_PW_CTL_IDX_AUX_TC4		6
9372 #define   ICL_PW_CTL_IDX_AUX_F			5
9373 #define   TGL_PW_CTL_IDX_AUX_TC3		5
9374 #define   ICL_PW_CTL_IDX_AUX_E			4
9375 #define   TGL_PW_CTL_IDX_AUX_TC2		4
9376 #define   ICL_PW_CTL_IDX_AUX_D			3
9377 #define   TGL_PW_CTL_IDX_AUX_TC1		3
9378 #define   ICL_PW_CTL_IDX_AUX_C			2
9379 #define   ICL_PW_CTL_IDX_AUX_B			1
9380 #define   ICL_PW_CTL_IDX_AUX_A			0
9381 
9382 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
9383 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
9384 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
9385 #define   TGL_PW_CTL_IDX_DDI_TC6		8
9386 #define   TGL_PW_CTL_IDX_DDI_TC5		7
9387 #define   TGL_PW_CTL_IDX_DDI_TC4		6
9388 #define   ICL_PW_CTL_IDX_DDI_F			5
9389 #define   TGL_PW_CTL_IDX_DDI_TC3		5
9390 #define   ICL_PW_CTL_IDX_DDI_E			4
9391 #define   TGL_PW_CTL_IDX_DDI_TC2		4
9392 #define   ICL_PW_CTL_IDX_DDI_D			3
9393 #define   TGL_PW_CTL_IDX_DDI_TC1		3
9394 #define   ICL_PW_CTL_IDX_DDI_C			2
9395 #define   ICL_PW_CTL_IDX_DDI_B			1
9396 #define   ICL_PW_CTL_IDX_DDI_A			0
9397 
9398 /* HSW - power well misc debug registers */
9399 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
9400 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1 << 31)
9401 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1 << 20)
9402 #define   HSW_PWR_WELL_FORCE_ON			(1 << 19)
9403 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
9404 
9405 /* SKL Fuse Status */
9406 enum skl_power_gate {
9407 	SKL_PG0,
9408 	SKL_PG1,
9409 	SKL_PG2,
9410 	ICL_PG3,
9411 	ICL_PG4,
9412 };
9413 
9414 #define SKL_FUSE_STATUS				_MMIO(0x42000)
9415 #define  SKL_FUSE_DOWNLOAD_STATUS		(1 << 31)
9416 /*
9417  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9418  * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9419  */
9420 #define  SKL_PW_CTL_IDX_TO_PG(pw_idx)		\
9421 	((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9422 /*
9423  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9424  * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9425  */
9426 #define  ICL_PW_CTL_IDX_TO_PG(pw_idx)		\
9427 	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9428 #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
9429 
9430 #define _CNL_AUX_REG_IDX(pw_idx)	((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9431 #define _CNL_AUX_ANAOVRD1_B		0x162250
9432 #define _CNL_AUX_ANAOVRD1_C		0x162210
9433 #define _CNL_AUX_ANAOVRD1_D		0x1622D0
9434 #define _CNL_AUX_ANAOVRD1_F		0x162A90
9435 #define CNL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9436 						    _CNL_AUX_ANAOVRD1_B, \
9437 						    _CNL_AUX_ANAOVRD1_C, \
9438 						    _CNL_AUX_ANAOVRD1_D, \
9439 						    _CNL_AUX_ANAOVRD1_F))
9440 #define   CNL_AUX_ANAOVRD1_ENABLE	(1 << 16)
9441 #define   CNL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 23)
9442 
9443 #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9444 #define _ICL_AUX_ANAOVRD1_A		0x162398
9445 #define _ICL_AUX_ANAOVRD1_B		0x6C398
9446 #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9447 						    _ICL_AUX_ANAOVRD1_A, \
9448 						    _ICL_AUX_ANAOVRD1_B))
9449 #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
9450 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
9451 
9452 /* HDCP Key Registers */
9453 #define HDCP_KEY_CONF			_MMIO(0x66c00)
9454 #define  HDCP_AKSV_SEND_TRIGGER		BIT(31)
9455 #define  HDCP_CLEAR_KEYS_TRIGGER	BIT(30)
9456 #define  HDCP_KEY_LOAD_TRIGGER		BIT(8)
9457 #define HDCP_KEY_STATUS			_MMIO(0x66c04)
9458 #define  HDCP_FUSE_IN_PROGRESS		BIT(7)
9459 #define  HDCP_FUSE_ERROR		BIT(6)
9460 #define  HDCP_FUSE_DONE			BIT(5)
9461 #define  HDCP_KEY_LOAD_STATUS		BIT(1)
9462 #define  HDCP_KEY_LOAD_DONE		BIT(0)
9463 #define HDCP_AKSV_LO			_MMIO(0x66c10)
9464 #define HDCP_AKSV_HI			_MMIO(0x66c14)
9465 
9466 /* HDCP Repeater Registers */
9467 #define HDCP_REP_CTL			_MMIO(0x66d00)
9468 #define  HDCP_TRANSA_REP_PRESENT	BIT(31)
9469 #define  HDCP_TRANSB_REP_PRESENT	BIT(30)
9470 #define  HDCP_TRANSC_REP_PRESENT	BIT(29)
9471 #define  HDCP_TRANSD_REP_PRESENT	BIT(28)
9472 #define  HDCP_DDIB_REP_PRESENT		BIT(30)
9473 #define  HDCP_DDIA_REP_PRESENT		BIT(29)
9474 #define  HDCP_DDIC_REP_PRESENT		BIT(28)
9475 #define  HDCP_DDID_REP_PRESENT		BIT(27)
9476 #define  HDCP_DDIF_REP_PRESENT		BIT(26)
9477 #define  HDCP_DDIE_REP_PRESENT		BIT(25)
9478 #define  HDCP_TRANSA_SHA1_M0		(1 << 20)
9479 #define  HDCP_TRANSB_SHA1_M0		(2 << 20)
9480 #define  HDCP_TRANSC_SHA1_M0		(3 << 20)
9481 #define  HDCP_TRANSD_SHA1_M0		(4 << 20)
9482 #define  HDCP_DDIB_SHA1_M0		(1 << 20)
9483 #define  HDCP_DDIA_SHA1_M0		(2 << 20)
9484 #define  HDCP_DDIC_SHA1_M0		(3 << 20)
9485 #define  HDCP_DDID_SHA1_M0		(4 << 20)
9486 #define  HDCP_DDIF_SHA1_M0		(5 << 20)
9487 #define  HDCP_DDIE_SHA1_M0		(6 << 20) /* Bspec says 5? */
9488 #define  HDCP_SHA1_BUSY			BIT(16)
9489 #define  HDCP_SHA1_READY		BIT(17)
9490 #define  HDCP_SHA1_COMPLETE		BIT(18)
9491 #define  HDCP_SHA1_V_MATCH		BIT(19)
9492 #define  HDCP_SHA1_TEXT_32		(1 << 1)
9493 #define  HDCP_SHA1_COMPLETE_HASH	(2 << 1)
9494 #define  HDCP_SHA1_TEXT_24		(4 << 1)
9495 #define  HDCP_SHA1_TEXT_16		(5 << 1)
9496 #define  HDCP_SHA1_TEXT_8		(6 << 1)
9497 #define  HDCP_SHA1_TEXT_0		(7 << 1)
9498 #define HDCP_SHA_V_PRIME_H0		_MMIO(0x66d04)
9499 #define HDCP_SHA_V_PRIME_H1		_MMIO(0x66d08)
9500 #define HDCP_SHA_V_PRIME_H2		_MMIO(0x66d0C)
9501 #define HDCP_SHA_V_PRIME_H3		_MMIO(0x66d10)
9502 #define HDCP_SHA_V_PRIME_H4		_MMIO(0x66d14)
9503 #define HDCP_SHA_V_PRIME(h)		_MMIO((0x66d04 + (h) * 4))
9504 #define HDCP_SHA_TEXT			_MMIO(0x66d18)
9505 
9506 /* HDCP Auth Registers */
9507 #define _PORTA_HDCP_AUTHENC		0x66800
9508 #define _PORTB_HDCP_AUTHENC		0x66500
9509 #define _PORTC_HDCP_AUTHENC		0x66600
9510 #define _PORTD_HDCP_AUTHENC		0x66700
9511 #define _PORTE_HDCP_AUTHENC		0x66A00
9512 #define _PORTF_HDCP_AUTHENC		0x66900
9513 #define _PORT_HDCP_AUTHENC(port, x)	_MMIO(_PICK(port, \
9514 					  _PORTA_HDCP_AUTHENC, \
9515 					  _PORTB_HDCP_AUTHENC, \
9516 					  _PORTC_HDCP_AUTHENC, \
9517 					  _PORTD_HDCP_AUTHENC, \
9518 					  _PORTE_HDCP_AUTHENC, \
9519 					  _PORTF_HDCP_AUTHENC) + (x))
9520 #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
9521 #define _TRANSA_HDCP_CONF		0x66400
9522 #define _TRANSB_HDCP_CONF		0x66500
9523 #define TRANS_HDCP_CONF(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
9524 						    _TRANSB_HDCP_CONF)
9525 #define HDCP_CONF(dev_priv, trans, port) \
9526 					(INTEL_GEN(dev_priv) >= 12 ? \
9527 					 TRANS_HDCP_CONF(trans) : \
9528 					 PORT_HDCP_CONF(port))
9529 
9530 #define  HDCP_CONF_CAPTURE_AN		BIT(0)
9531 #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
9532 #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
9533 #define _TRANSA_HDCP_ANINIT		0x66404
9534 #define _TRANSB_HDCP_ANINIT		0x66504
9535 #define TRANS_HDCP_ANINIT(trans)	_MMIO_TRANS(trans, \
9536 						    _TRANSA_HDCP_ANINIT, \
9537 						    _TRANSB_HDCP_ANINIT)
9538 #define HDCP_ANINIT(dev_priv, trans, port) \
9539 					(INTEL_GEN(dev_priv) >= 12 ? \
9540 					 TRANS_HDCP_ANINIT(trans) : \
9541 					 PORT_HDCP_ANINIT(port))
9542 
9543 #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
9544 #define _TRANSA_HDCP_ANLO		0x66408
9545 #define _TRANSB_HDCP_ANLO		0x66508
9546 #define TRANS_HDCP_ANLO(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
9547 						    _TRANSB_HDCP_ANLO)
9548 #define HDCP_ANLO(dev_priv, trans, port) \
9549 					(INTEL_GEN(dev_priv) >= 12 ? \
9550 					 TRANS_HDCP_ANLO(trans) : \
9551 					 PORT_HDCP_ANLO(port))
9552 
9553 #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
9554 #define _TRANSA_HDCP_ANHI		0x6640C
9555 #define _TRANSB_HDCP_ANHI		0x6650C
9556 #define TRANS_HDCP_ANHI(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
9557 						    _TRANSB_HDCP_ANHI)
9558 #define HDCP_ANHI(dev_priv, trans, port) \
9559 					(INTEL_GEN(dev_priv) >= 12 ? \
9560 					 TRANS_HDCP_ANHI(trans) : \
9561 					 PORT_HDCP_ANHI(port))
9562 
9563 #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
9564 #define _TRANSA_HDCP_BKSVLO		0x66410
9565 #define _TRANSB_HDCP_BKSVLO		0x66510
9566 #define TRANS_HDCP_BKSVLO(trans)	_MMIO_TRANS(trans, \
9567 						    _TRANSA_HDCP_BKSVLO, \
9568 						    _TRANSB_HDCP_BKSVLO)
9569 #define HDCP_BKSVLO(dev_priv, trans, port) \
9570 					(INTEL_GEN(dev_priv) >= 12 ? \
9571 					 TRANS_HDCP_BKSVLO(trans) : \
9572 					 PORT_HDCP_BKSVLO(port))
9573 
9574 #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
9575 #define _TRANSA_HDCP_BKSVHI		0x66414
9576 #define _TRANSB_HDCP_BKSVHI		0x66514
9577 #define TRANS_HDCP_BKSVHI(trans)	_MMIO_TRANS(trans, \
9578 						    _TRANSA_HDCP_BKSVHI, \
9579 						    _TRANSB_HDCP_BKSVHI)
9580 #define HDCP_BKSVHI(dev_priv, trans, port) \
9581 					(INTEL_GEN(dev_priv) >= 12 ? \
9582 					 TRANS_HDCP_BKSVHI(trans) : \
9583 					 PORT_HDCP_BKSVHI(port))
9584 
9585 #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
9586 #define _TRANSA_HDCP_RPRIME		0x66418
9587 #define _TRANSB_HDCP_RPRIME		0x66518
9588 #define TRANS_HDCP_RPRIME(trans)	_MMIO_TRANS(trans, \
9589 						    _TRANSA_HDCP_RPRIME, \
9590 						    _TRANSB_HDCP_RPRIME)
9591 #define HDCP_RPRIME(dev_priv, trans, port) \
9592 					(INTEL_GEN(dev_priv) >= 12 ? \
9593 					 TRANS_HDCP_RPRIME(trans) : \
9594 					 PORT_HDCP_RPRIME(port))
9595 
9596 #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
9597 #define _TRANSA_HDCP_STATUS		0x6641C
9598 #define _TRANSB_HDCP_STATUS		0x6651C
9599 #define TRANS_HDCP_STATUS(trans)	_MMIO_TRANS(trans, \
9600 						    _TRANSA_HDCP_STATUS, \
9601 						    _TRANSB_HDCP_STATUS)
9602 #define HDCP_STATUS(dev_priv, trans, port) \
9603 					(INTEL_GEN(dev_priv) >= 12 ? \
9604 					 TRANS_HDCP_STATUS(trans) : \
9605 					 PORT_HDCP_STATUS(port))
9606 
9607 #define  HDCP_STATUS_STREAM_A_ENC	BIT(31)
9608 #define  HDCP_STATUS_STREAM_B_ENC	BIT(30)
9609 #define  HDCP_STATUS_STREAM_C_ENC	BIT(29)
9610 #define  HDCP_STATUS_STREAM_D_ENC	BIT(28)
9611 #define  HDCP_STATUS_AUTH		BIT(21)
9612 #define  HDCP_STATUS_ENC		BIT(20)
9613 #define  HDCP_STATUS_RI_MATCH		BIT(19)
9614 #define  HDCP_STATUS_R0_READY		BIT(18)
9615 #define  HDCP_STATUS_AN_READY		BIT(17)
9616 #define  HDCP_STATUS_CIPHER		BIT(16)
9617 #define  HDCP_STATUS_FRAME_CNT(x)	(((x) >> 8) & 0xff)
9618 
9619 /* HDCP2.2 Registers */
9620 #define _PORTA_HDCP2_BASE		0x66800
9621 #define _PORTB_HDCP2_BASE		0x66500
9622 #define _PORTC_HDCP2_BASE		0x66600
9623 #define _PORTD_HDCP2_BASE		0x66700
9624 #define _PORTE_HDCP2_BASE		0x66A00
9625 #define _PORTF_HDCP2_BASE		0x66900
9626 #define _PORT_HDCP2_BASE(port, x)	_MMIO(_PICK((port), \
9627 					  _PORTA_HDCP2_BASE, \
9628 					  _PORTB_HDCP2_BASE, \
9629 					  _PORTC_HDCP2_BASE, \
9630 					  _PORTD_HDCP2_BASE, \
9631 					  _PORTE_HDCP2_BASE, \
9632 					  _PORTF_HDCP2_BASE) + (x))
9633 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
9634 #define _TRANSA_HDCP2_AUTH		0x66498
9635 #define _TRANSB_HDCP2_AUTH		0x66598
9636 #define TRANS_HDCP2_AUTH(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
9637 						    _TRANSB_HDCP2_AUTH)
9638 #define   AUTH_LINK_AUTHENTICATED	BIT(31)
9639 #define   AUTH_LINK_TYPE		BIT(30)
9640 #define   AUTH_FORCE_CLR_INPUTCTR	BIT(19)
9641 #define   AUTH_CLR_KEYS			BIT(18)
9642 #define HDCP2_AUTH(dev_priv, trans, port) \
9643 					(INTEL_GEN(dev_priv) >= 12 ? \
9644 					 TRANS_HDCP2_AUTH(trans) : \
9645 					 PORT_HDCP2_AUTH(port))
9646 
9647 #define PORT_HDCP2_CTL(port)		_PORT_HDCP2_BASE(port, 0xB0)
9648 #define _TRANSA_HDCP2_CTL		0x664B0
9649 #define _TRANSB_HDCP2_CTL		0x665B0
9650 #define TRANS_HDCP2_CTL(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
9651 						    _TRANSB_HDCP2_CTL)
9652 #define   CTL_LINK_ENCRYPTION_REQ	BIT(31)
9653 #define HDCP2_CTL(dev_priv, trans, port) \
9654 					(INTEL_GEN(dev_priv) >= 12 ? \
9655 					 TRANS_HDCP2_CTL(trans) : \
9656 					 PORT_HDCP2_CTL(port))
9657 
9658 #define PORT_HDCP2_STATUS(port)		_PORT_HDCP2_BASE(port, 0xB4)
9659 #define _TRANSA_HDCP2_STATUS		0x664B4
9660 #define _TRANSB_HDCP2_STATUS		0x665B4
9661 #define TRANS_HDCP2_STATUS(trans)	_MMIO_TRANS(trans, \
9662 						    _TRANSA_HDCP2_STATUS, \
9663 						    _TRANSB_HDCP2_STATUS)
9664 #define   LINK_TYPE_STATUS		BIT(22)
9665 #define   LINK_AUTH_STATUS		BIT(21)
9666 #define   LINK_ENCRYPTION_STATUS	BIT(20)
9667 #define HDCP2_STATUS(dev_priv, trans, port) \
9668 					(INTEL_GEN(dev_priv) >= 12 ? \
9669 					 TRANS_HDCP2_STATUS(trans) : \
9670 					 PORT_HDCP2_STATUS(port))
9671 
9672 /* Per-pipe DDI Function Control */
9673 #define _TRANS_DDI_FUNC_CTL_A		0x60400
9674 #define _TRANS_DDI_FUNC_CTL_B		0x61400
9675 #define _TRANS_DDI_FUNC_CTL_C		0x62400
9676 #define _TRANS_DDI_FUNC_CTL_D		0x63400
9677 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
9678 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
9679 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
9680 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9681 
9682 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
9683 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9684 #define  TRANS_DDI_PORT_SHIFT		28
9685 #define  TGL_TRANS_DDI_PORT_SHIFT	27
9686 #define  TRANS_DDI_PORT_MASK		(7 << TRANS_DDI_PORT_SHIFT)
9687 #define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
9688 #define  TRANS_DDI_SELECT_PORT(x)	((x) << TRANS_DDI_PORT_SHIFT)
9689 #define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
9690 #define  TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)	 (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
9691 #define  TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9692 #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
9693 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
9694 #define  TRANS_DDI_MODE_SELECT_DVI	(1 << 24)
9695 #define  TRANS_DDI_MODE_SELECT_DP_SST	(2 << 24)
9696 #define  TRANS_DDI_MODE_SELECT_DP_MST	(3 << 24)
9697 #define  TRANS_DDI_MODE_SELECT_FDI	(4 << 24)
9698 #define  TRANS_DDI_BPC_MASK		(7 << 20)
9699 #define  TRANS_DDI_BPC_8		(0 << 20)
9700 #define  TRANS_DDI_BPC_10		(1 << 20)
9701 #define  TRANS_DDI_BPC_6		(2 << 20)
9702 #define  TRANS_DDI_BPC_12		(3 << 20)
9703 #define  TRANS_DDI_PVSYNC		(1 << 17)
9704 #define  TRANS_DDI_PHSYNC		(1 << 16)
9705 #define  TRANS_DDI_EDP_INPUT_MASK	(7 << 12)
9706 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
9707 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
9708 #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5 << 12)
9709 #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6 << 12)
9710 #define  TRANS_DDI_EDP_INPUT_D_ONOFF	(7 << 12)
9711 #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK	REG_GENMASK(11, 10)
9712 #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans)	\
9713 	REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
9714 #define  TRANS_DDI_HDCP_SIGNALLING	(1 << 9)
9715 #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC	(1 << 8)
9716 #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9717 #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9718 #define  TRANS_DDI_BFI_ENABLE		(1 << 4)
9719 #define  TRANS_DDI_HIGH_TMDS_CHAR_RATE	(1 << 4)
9720 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
9721 #define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9722 					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9723 					| TRANS_DDI_HDMI_SCRAMBLING)
9724 
9725 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
9726 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
9727 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
9728 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
9729 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
9730 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
9731 #define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
9732 						     _TRANS_DDI_FUNC_CTL2_A)
9733 #define  PORT_SYNC_MODE_ENABLE			(1 << 4)
9734 #define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) << 0)
9735 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
9736 #define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
9737 
9738 /* DisplayPort Transport Control */
9739 #define _DP_TP_CTL_A			0x64040
9740 #define _DP_TP_CTL_B			0x64140
9741 #define _TGL_DP_TP_CTL_A		0x60540
9742 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9743 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
9744 #define  DP_TP_CTL_ENABLE			(1 << 31)
9745 #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
9746 #define  DP_TP_CTL_MODE_SST			(0 << 27)
9747 #define  DP_TP_CTL_MODE_MST			(1 << 27)
9748 #define  DP_TP_CTL_FORCE_ACT			(1 << 25)
9749 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1 << 18)
9750 #define  DP_TP_CTL_FDI_AUTOTRAIN		(1 << 15)
9751 #define  DP_TP_CTL_LINK_TRAIN_MASK		(7 << 8)
9752 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
9753 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1 << 8)
9754 #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4 << 8)
9755 #define  DP_TP_CTL_LINK_TRAIN_PAT4		(5 << 8)
9756 #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2 << 8)
9757 #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3 << 8)
9758 #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1 << 7)
9759 
9760 /* DisplayPort Transport Status */
9761 #define _DP_TP_STATUS_A			0x64044
9762 #define _DP_TP_STATUS_B			0x64144
9763 #define _TGL_DP_TP_STATUS_A		0x60544
9764 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9765 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
9766 #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
9767 #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
9768 #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
9769 #define  DP_TP_STATUS_MODE_STATUS_MST		(1 << 23)
9770 #define  DP_TP_STATUS_AUTOTRAIN_DONE		(1 << 12)
9771 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2	(3 << 8)
9772 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1	(3 << 4)
9773 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
9774 
9775 /* DDI Buffer Control */
9776 #define _DDI_BUF_CTL_A				0x64000
9777 #define _DDI_BUF_CTL_B				0x64100
9778 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9779 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
9780 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
9781 #define  DDI_BUF_EMP_MASK			(0xf << 24)
9782 #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
9783 #define  DDI_BUF_IS_IDLE			(1 << 7)
9784 #define  DDI_A_4_LANES				(1 << 4)
9785 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
9786 #define  DDI_PORT_WIDTH_MASK			(7 << 1)
9787 #define  DDI_PORT_WIDTH_SHIFT			1
9788 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
9789 
9790 /* DDI Buffer Translations */
9791 #define _DDI_BUF_TRANS_A		0x64E00
9792 #define _DDI_BUF_TRANS_B		0x64E60
9793 #define DDI_BUF_TRANS_LO(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9794 #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
9795 #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9796 
9797 /* Sideband Interface (SBI) is programmed indirectly, via
9798  * SBI_ADDR, which contains the register offset; and SBI_DATA,
9799  * which contains the payload */
9800 #define SBI_ADDR			_MMIO(0xC6000)
9801 #define SBI_DATA			_MMIO(0xC6004)
9802 #define SBI_CTL_STAT			_MMIO(0xC6008)
9803 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
9804 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
9805 #define  SBI_CTL_OP_IORD		(0x2 << 8)
9806 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
9807 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
9808 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
9809 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
9810 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
9811 #define  SBI_BUSY			(0x1 << 0)
9812 #define  SBI_READY			(0x0 << 0)
9813 
9814 /* SBI offsets */
9815 #define  SBI_SSCDIVINTPHASE			0x0200
9816 #define  SBI_SSCDIVINTPHASE6			0x0600
9817 #define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT	1
9818 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
9819 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x) << 1)
9820 #define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT	8
9821 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
9822 #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x) << 8)
9823 #define   SBI_SSCDIVINTPHASE_DIR(x)		((x) << 15)
9824 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
9825 #define  SBI_SSCDITHPHASE			0x0204
9826 #define  SBI_SSCCTL				0x020c
9827 #define  SBI_SSCCTL6				0x060C
9828 #define   SBI_SSCCTL_PATHALT			(1 << 3)
9829 #define   SBI_SSCCTL_DISABLE			(1 << 0)
9830 #define  SBI_SSCAUXDIV6				0x0610
9831 #define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT	4
9832 #define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK	(1 << 4)
9833 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x) << 4)
9834 #define  SBI_DBUFF0				0x2a00
9835 #define  SBI_GEN0				0x1f00
9836 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
9837 
9838 /* LPT PIXCLK_GATE */
9839 #define PIXCLK_GATE			_MMIO(0xC6020)
9840 #define  PIXCLK_GATE_UNGATE		(1 << 0)
9841 #define  PIXCLK_GATE_GATE		(0 << 0)
9842 
9843 /* SPLL */
9844 #define SPLL_CTL			_MMIO(0x46020)
9845 #define  SPLL_PLL_ENABLE		(1 << 31)
9846 #define  SPLL_REF_BCLK			(0 << 28)
9847 #define  SPLL_REF_MUXED_SSC		(1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9848 #define  SPLL_REF_NON_SSC_HSW		(2 << 28)
9849 #define  SPLL_REF_PCH_SSC_BDW		(2 << 28)
9850 #define  SPLL_REF_LCPLL			(3 << 28)
9851 #define  SPLL_REF_MASK			(3 << 28)
9852 #define  SPLL_FREQ_810MHz		(0 << 26)
9853 #define  SPLL_FREQ_1350MHz		(1 << 26)
9854 #define  SPLL_FREQ_2700MHz		(2 << 26)
9855 #define  SPLL_FREQ_MASK			(3 << 26)
9856 
9857 /* WRPLL */
9858 #define _WRPLL_CTL1			0x46040
9859 #define _WRPLL_CTL2			0x46060
9860 #define WRPLL_CTL(pll)			_MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9861 #define  WRPLL_PLL_ENABLE		(1 << 31)
9862 #define  WRPLL_REF_BCLK			(0 << 28)
9863 #define  WRPLL_REF_PCH_SSC		(1 << 28)
9864 #define  WRPLL_REF_MUXED_SSC_BDW	(2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9865 #define  WRPLL_REF_SPECIAL_HSW		(2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
9866 #define  WRPLL_REF_LCPLL		(3 << 28)
9867 #define  WRPLL_REF_MASK			(3 << 28)
9868 /* WRPLL divider programming */
9869 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
9870 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
9871 #define  WRPLL_DIVIDER_POST(x)		((x) << 8)
9872 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
9873 #define  WRPLL_DIVIDER_POST_SHIFT	8
9874 #define  WRPLL_DIVIDER_FEEDBACK(x)	((x) << 16)
9875 #define  WRPLL_DIVIDER_FB_SHIFT		16
9876 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
9877 
9878 /* Port clock selection */
9879 #define _PORT_CLK_SEL_A			0x46100
9880 #define _PORT_CLK_SEL_B			0x46104
9881 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9882 #define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
9883 #define  PORT_CLK_SEL_LCPLL_1350	(1 << 29)
9884 #define  PORT_CLK_SEL_LCPLL_810		(2 << 29)
9885 #define  PORT_CLK_SEL_SPLL		(3 << 29)
9886 #define  PORT_CLK_SEL_WRPLL(pll)	(((pll) + 4) << 29)
9887 #define  PORT_CLK_SEL_WRPLL1		(4 << 29)
9888 #define  PORT_CLK_SEL_WRPLL2		(5 << 29)
9889 #define  PORT_CLK_SEL_NONE		(7 << 29)
9890 #define  PORT_CLK_SEL_MASK		(7 << 29)
9891 
9892 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9893 #define DDI_CLK_SEL(port)		PORT_CLK_SEL(port)
9894 #define  DDI_CLK_SEL_NONE		(0x0 << 28)
9895 #define  DDI_CLK_SEL_MG			(0x8 << 28)
9896 #define  DDI_CLK_SEL_TBT_162		(0xC << 28)
9897 #define  DDI_CLK_SEL_TBT_270		(0xD << 28)
9898 #define  DDI_CLK_SEL_TBT_540		(0xE << 28)
9899 #define  DDI_CLK_SEL_TBT_810		(0xF << 28)
9900 #define  DDI_CLK_SEL_MASK		(0xF << 28)
9901 
9902 /* Transcoder clock selection */
9903 #define _TRANS_CLK_SEL_A		0x46140
9904 #define _TRANS_CLK_SEL_B		0x46144
9905 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9906 /* For each transcoder, we need to select the corresponding port clock */
9907 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
9908 #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
9909 #define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
9910 #define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)
9911 
9912 
9913 #define CDCLK_FREQ			_MMIO(0x46200)
9914 
9915 #define _TRANSA_MSA_MISC		0x60410
9916 #define _TRANSB_MSA_MISC		0x61410
9917 #define _TRANSC_MSA_MISC		0x62410
9918 #define _TRANS_EDP_MSA_MISC		0x6f410
9919 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9920 /* See DP_MSA_MISC_* for the bit definitions */
9921 
9922 /* LCPLL Control */
9923 #define LCPLL_CTL			_MMIO(0x130040)
9924 #define  LCPLL_PLL_DISABLE		(1 << 31)
9925 #define  LCPLL_PLL_LOCK			(1 << 30)
9926 #define  LCPLL_REF_NON_SSC		(0 << 28)
9927 #define  LCPLL_REF_BCLK			(2 << 28)
9928 #define  LCPLL_REF_PCH_SSC		(3 << 28)
9929 #define  LCPLL_REF_MASK			(3 << 28)
9930 #define  LCPLL_CLK_FREQ_MASK		(3 << 26)
9931 #define  LCPLL_CLK_FREQ_450		(0 << 26)
9932 #define  LCPLL_CLK_FREQ_54O_BDW		(1 << 26)
9933 #define  LCPLL_CLK_FREQ_337_5_BDW	(2 << 26)
9934 #define  LCPLL_CLK_FREQ_675_BDW		(3 << 26)
9935 #define  LCPLL_CD_CLOCK_DISABLE		(1 << 25)
9936 #define  LCPLL_ROOT_CD_CLOCK_DISABLE	(1 << 24)
9937 #define  LCPLL_CD2X_CLOCK_DISABLE	(1 << 23)
9938 #define  LCPLL_POWER_DOWN_ALLOW		(1 << 22)
9939 #define  LCPLL_CD_SOURCE_FCLK		(1 << 21)
9940 #define  LCPLL_CD_SOURCE_FCLK_DONE	(1 << 19)
9941 
9942 /*
9943  * SKL Clocks
9944  */
9945 
9946 /* CDCLK_CTL */
9947 #define CDCLK_CTL			_MMIO(0x46000)
9948 #define  CDCLK_FREQ_SEL_MASK		(3 << 26)
9949 #define  CDCLK_FREQ_450_432		(0 << 26)
9950 #define  CDCLK_FREQ_540			(1 << 26)
9951 #define  CDCLK_FREQ_337_308		(2 << 26)
9952 #define  CDCLK_FREQ_675_617		(3 << 26)
9953 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)
9954 #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
9955 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)
9956 #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
9957 #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
9958 #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
9959 #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
9960 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
9961 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
9962 #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
9963 #define  TGL_CDCLK_CD2X_PIPE(pipe)	BXT_CDCLK_CD2X_PIPE(pipe)
9964 #define  TGL_CDCLK_CD2X_PIPE_NONE	ICL_CDCLK_CD2X_PIPE_NONE
9965 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
9966 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
9967 
9968 /* LCPLL_CTL */
9969 #define LCPLL1_CTL		_MMIO(0x46010)
9970 #define LCPLL2_CTL		_MMIO(0x46014)
9971 #define  LCPLL_PLL_ENABLE	(1 << 31)
9972 
9973 /* DPLL control1 */
9974 #define DPLL_CTRL1		_MMIO(0x6C058)
9975 #define  DPLL_CTRL1_HDMI_MODE(id)		(1 << ((id) * 6 + 5))
9976 #define  DPLL_CTRL1_SSC(id)			(1 << ((id) * 6 + 4))
9977 #define  DPLL_CTRL1_LINK_RATE_MASK(id)		(7 << ((id) * 6 + 1))
9978 #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)		((id) * 6 + 1)
9979 #define  DPLL_CTRL1_LINK_RATE(linkrate, id)	((linkrate) << ((id) * 6 + 1))
9980 #define  DPLL_CTRL1_OVERRIDE(id)		(1 << ((id) * 6))
9981 #define  DPLL_CTRL1_LINK_RATE_2700		0
9982 #define  DPLL_CTRL1_LINK_RATE_1350		1
9983 #define  DPLL_CTRL1_LINK_RATE_810		2
9984 #define  DPLL_CTRL1_LINK_RATE_1620		3
9985 #define  DPLL_CTRL1_LINK_RATE_1080		4
9986 #define  DPLL_CTRL1_LINK_RATE_2160		5
9987 
9988 /* DPLL control2 */
9989 #define DPLL_CTRL2				_MMIO(0x6C05C)
9990 #define  DPLL_CTRL2_DDI_CLK_OFF(port)		(1 << ((port) + 15))
9991 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)	(3 << ((port) * 3 + 1))
9992 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port) * 3 + 1)
9993 #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)	((clk) << ((port) * 3 + 1))
9994 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1 << ((port) * 3))
9995 
9996 /* DPLL Status */
9997 #define DPLL_STATUS	_MMIO(0x6C060)
9998 #define  DPLL_LOCK(id) (1 << ((id) * 8))
9999 
10000 /* DPLL cfg */
10001 #define _DPLL1_CFGCR1	0x6C040
10002 #define _DPLL2_CFGCR1	0x6C048
10003 #define _DPLL3_CFGCR1	0x6C050
10004 #define  DPLL_CFGCR1_FREQ_ENABLE	(1 << 31)
10005 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
10006 #define  DPLL_CFGCR1_DCO_FRACTION(x)	((x) << 9)
10007 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
10008 
10009 #define _DPLL1_CFGCR2	0x6C044
10010 #define _DPLL2_CFGCR2	0x6C04C
10011 #define _DPLL3_CFGCR2	0x6C054
10012 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
10013 #define  DPLL_CFGCR2_QDIV_RATIO(x)	((x) << 8)
10014 #define  DPLL_CFGCR2_QDIV_MODE(x)	((x) << 7)
10015 #define  DPLL_CFGCR2_KDIV_MASK		(3 << 5)
10016 #define  DPLL_CFGCR2_KDIV(x)		((x) << 5)
10017 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
10018 #define  DPLL_CFGCR2_KDIV_2 (1 << 5)
10019 #define  DPLL_CFGCR2_KDIV_3 (2 << 5)
10020 #define  DPLL_CFGCR2_KDIV_1 (3 << 5)
10021 #define  DPLL_CFGCR2_PDIV_MASK		(7 << 2)
10022 #define  DPLL_CFGCR2_PDIV(x)		((x) << 2)
10023 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
10024 #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
10025 #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
10026 #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
10027 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
10028 
10029 #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10030 #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10031 
10032 /*
10033  * CNL Clocks
10034  */
10035 #define DPCLKA_CFGCR0				_MMIO(0x6C200)
10036 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
10037 						      (port) + 10))
10038 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
10039 						(port) * 2)
10040 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10041 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10042 
10043 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
10044 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
10045 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
10046 						       (tc_port) + 12 : \
10047 						       (tc_port) - PORT_TC4 + 21))
10048 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
10049 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10050 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10051 
10052 /* CNL PLL */
10053 #define DPLL0_ENABLE		0x46010
10054 #define DPLL1_ENABLE		0x46014
10055 #define  PLL_ENABLE		(1 << 31)
10056 #define  PLL_LOCK		(1 << 30)
10057 #define  PLL_POWER_ENABLE	(1 << 27)
10058 #define  PLL_POWER_STATE	(1 << 26)
10059 #define CNL_DPLL_ENABLE(pll)	_MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
10060 
10061 #define TBT_PLL_ENABLE		_MMIO(0x46020)
10062 
10063 #define _MG_PLL1_ENABLE		0x46030
10064 #define _MG_PLL2_ENABLE		0x46034
10065 #define _MG_PLL3_ENABLE		0x46038
10066 #define _MG_PLL4_ENABLE		0x4603C
10067 /* Bits are the same as DPLL0_ENABLE */
10068 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
10069 					   _MG_PLL2_ENABLE)
10070 
10071 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
10072 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
10073 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
10074 #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
10075 #define   MG_REFCLKIN_CTL_OD_2_MUX(x)			((x) << 8)
10076 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
10077 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10078 					    _MG_REFCLKIN_CTL_PORT1, \
10079 					    _MG_REFCLKIN_CTL_PORT2)
10080 
10081 #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
10082 #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
10083 #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
10084 #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
10085 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)		((x) << 16)
10086 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
10087 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)		((x) << 8)
10088 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
10089 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10090 						   _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10091 						   _MG_CLKTOP2_CORECLKCTL1_PORT2)
10092 
10093 #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
10094 #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
10095 #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
10096 #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
10097 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)		((x) << 16)
10098 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
10099 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)
10100 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
10101 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
10102 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
10103 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)
10104 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)
10105 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)
10106 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)
10107 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT		8
10108 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
10109 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10110 						_MG_CLKTOP2_HSCLKCTL_PORT1, \
10111 						_MG_CLKTOP2_HSCLKCTL_PORT2)
10112 
10113 #define _MG_PLL_DIV0_PORT1				0x168A00
10114 #define _MG_PLL_DIV0_PORT2				0x169A00
10115 #define _MG_PLL_DIV0_PORT3				0x16AA00
10116 #define _MG_PLL_DIV0_PORT4				0x16BA00
10117 #define   MG_PLL_DIV0_FRACNEN_H				(1 << 30)
10118 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
10119 #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT			8
10120 #define   MG_PLL_DIV0_FBDIV_FRAC(x)			((x) << 8)
10121 #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
10122 #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
10123 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10124 					_MG_PLL_DIV0_PORT2)
10125 
10126 #define _MG_PLL_DIV1_PORT1				0x168A04
10127 #define _MG_PLL_DIV1_PORT2				0x169A04
10128 #define _MG_PLL_DIV1_PORT3				0x16AA04
10129 #define _MG_PLL_DIV1_PORT4				0x16BA04
10130 #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)			((x) << 16)
10131 #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
10132 #define   MG_PLL_DIV1_DITHER_DIV_2			(1 << 12)
10133 #define   MG_PLL_DIV1_DITHER_DIV_4			(2 << 12)
10134 #define   MG_PLL_DIV1_DITHER_DIV_8			(3 << 12)
10135 #define   MG_PLL_DIV1_NDIVRATIO(x)			((x) << 4)
10136 #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
10137 #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
10138 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10139 					_MG_PLL_DIV1_PORT2)
10140 
10141 #define _MG_PLL_LF_PORT1				0x168A08
10142 #define _MG_PLL_LF_PORT2				0x169A08
10143 #define _MG_PLL_LF_PORT3				0x16AA08
10144 #define _MG_PLL_LF_PORT4				0x16BA08
10145 #define   MG_PLL_LF_TDCTARGETCNT(x)			((x) << 24)
10146 #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
10147 #define   MG_PLL_LF_AFCCNTSEL_512			(1 << 20)
10148 #define   MG_PLL_LF_GAINCTRL(x)				((x) << 16)
10149 #define   MG_PLL_LF_INT_COEFF(x)			((x) << 8)
10150 #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
10151 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10152 				      _MG_PLL_LF_PORT2)
10153 
10154 #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
10155 #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
10156 #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
10157 #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
10158 #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32		(1 << 18)
10159 #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32		(1 << 16)
10160 #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)		((x) << 11)
10161 #define   MG_PLL_FRAC_LOCK_DCODITHEREN			(1 << 10)
10162 #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN		(1 << 8)
10163 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
10164 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10165 					     _MG_PLL_FRAC_LOCK_PORT1, \
10166 					     _MG_PLL_FRAC_LOCK_PORT2)
10167 
10168 #define _MG_PLL_SSC_PORT1				0x168A10
10169 #define _MG_PLL_SSC_PORT2				0x169A10
10170 #define _MG_PLL_SSC_PORT3				0x16AA10
10171 #define _MG_PLL_SSC_PORT4				0x16BA10
10172 #define   MG_PLL_SSC_EN					(1 << 28)
10173 #define   MG_PLL_SSC_TYPE(x)				((x) << 26)
10174 #define   MG_PLL_SSC_STEPLENGTH(x)			((x) << 16)
10175 #define   MG_PLL_SSC_STEPNUM(x)				((x) << 10)
10176 #define   MG_PLL_SSC_FLLEN				(1 << 9)
10177 #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
10178 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10179 				       _MG_PLL_SSC_PORT2)
10180 
10181 #define _MG_PLL_BIAS_PORT1				0x168A14
10182 #define _MG_PLL_BIAS_PORT2				0x169A14
10183 #define _MG_PLL_BIAS_PORT3				0x16AA14
10184 #define _MG_PLL_BIAS_PORT4				0x16BA14
10185 #define   MG_PLL_BIAS_BIAS_GB_SEL(x)			((x) << 30)
10186 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
10187 #define   MG_PLL_BIAS_INIT_DCOAMP(x)			((x) << 24)
10188 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
10189 #define   MG_PLL_BIAS_BIAS_BONUS(x)			((x) << 16)
10190 #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
10191 #define   MG_PLL_BIAS_BIASCAL_EN			(1 << 15)
10192 #define   MG_PLL_BIAS_CTRIM(x)				((x) << 8)
10193 #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
10194 #define   MG_PLL_BIAS_VREF_RDAC(x)			((x) << 5)
10195 #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
10196 #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
10197 #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
10198 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10199 					_MG_PLL_BIAS_PORT2)
10200 
10201 #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
10202 #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
10203 #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
10204 #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
10205 #define   MG_PLL_TDC_COLDST_IREFINT_EN			(1 << 27)
10206 #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)	((x) << 17)
10207 #define   MG_PLL_TDC_COLDST_COLDSTART			(1 << 16)
10208 #define   MG_PLL_TDC_TDCOVCCORR_EN			(1 << 2)
10209 #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
10210 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10211 						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10212 						   _MG_PLL_TDC_COLDST_BIAS_PORT2)
10213 
10214 #define _CNL_DPLL0_CFGCR0		0x6C000
10215 #define _CNL_DPLL1_CFGCR0		0x6C080
10216 #define  DPLL_CFGCR0_HDMI_MODE		(1 << 30)
10217 #define  DPLL_CFGCR0_SSC_ENABLE		(1 << 29)
10218 #define  DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
10219 #define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
10220 #define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
10221 #define  DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
10222 #define  DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
10223 #define  DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
10224 #define  DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
10225 #define  DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
10226 #define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
10227 #define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
10228 #define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
10229 #define  DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
10230 #define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
10231 #define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
10232 #define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
10233 
10234 #define _CNL_DPLL0_CFGCR1		0x6C004
10235 #define _CNL_DPLL1_CFGCR1		0x6C084
10236 #define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
10237 #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
10238 #define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
10239 #define  DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
10240 #define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
10241 #define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
10242 #define  DPLL_CFGCR1_KDIV_SHIFT		(6)
10243 #define  DPLL_CFGCR1_KDIV(x)		((x) << 6)
10244 #define  DPLL_CFGCR1_KDIV_1		(1 << 6)
10245 #define  DPLL_CFGCR1_KDIV_2		(2 << 6)
10246 #define  DPLL_CFGCR1_KDIV_3		(4 << 6)
10247 #define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
10248 #define  DPLL_CFGCR1_PDIV_SHIFT		(2)
10249 #define  DPLL_CFGCR1_PDIV(x)		((x) << 2)
10250 #define  DPLL_CFGCR1_PDIV_2		(1 << 2)
10251 #define  DPLL_CFGCR1_PDIV_3		(2 << 2)
10252 #define  DPLL_CFGCR1_PDIV_5		(4 << 2)
10253 #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
10254 #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
10255 #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
10256 #define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
10257 #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
10258 
10259 #define _ICL_DPLL0_CFGCR0		0x164000
10260 #define _ICL_DPLL1_CFGCR0		0x164080
10261 #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10262 						  _ICL_DPLL1_CFGCR0)
10263 
10264 #define _ICL_DPLL0_CFGCR1		0x164004
10265 #define _ICL_DPLL1_CFGCR1		0x164084
10266 #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
10267 						  _ICL_DPLL1_CFGCR1)
10268 
10269 #define _TGL_DPLL0_CFGCR0		0x164284
10270 #define _TGL_DPLL1_CFGCR0		0x16428C
10271 /* TODO: add DPLL4 */
10272 #define _TGL_TBTPLL_CFGCR0		0x16429C
10273 #define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10274 						  _TGL_DPLL1_CFGCR0, \
10275 						  _TGL_TBTPLL_CFGCR0)
10276 
10277 #define _TGL_DPLL0_CFGCR1		0x164288
10278 #define _TGL_DPLL1_CFGCR1		0x164290
10279 /* TODO: add DPLL4 */
10280 #define _TGL_TBTPLL_CFGCR1		0x1642A0
10281 #define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10282 						   _TGL_DPLL1_CFGCR1, \
10283 						   _TGL_TBTPLL_CFGCR1)
10284 
10285 #define _DKL_PHY1_BASE			0x168000
10286 #define _DKL_PHY2_BASE			0x169000
10287 #define _DKL_PHY3_BASE			0x16A000
10288 #define _DKL_PHY4_BASE			0x16B000
10289 #define _DKL_PHY5_BASE			0x16C000
10290 #define _DKL_PHY6_BASE			0x16D000
10291 
10292 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
10293 #define _DKL_PLL_DIV0			0x200
10294 #define   DKL_PLL_DIV0_INTEG_COEFF(x)	((x) << 16)
10295 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
10296 #define   DKL_PLL_DIV0_PROP_COEFF(x)	((x) << 12)
10297 #define   DKL_PLL_DIV0_PROP_COEFF_MASK	(0xF << 12)
10298 #define   DKL_PLL_DIV0_FBPREDIV_SHIFT   (8)
10299 #define   DKL_PLL_DIV0_FBPREDIV(x)	((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10300 #define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10301 #define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
10302 #define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
10303 #define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10304 						    _DKL_PHY2_BASE) + \
10305 						    _DKL_PLL_DIV0)
10306 
10307 #define _DKL_PLL_DIV1				0x204
10308 #define   DKL_PLL_DIV1_IREF_TRIM(x)		((x) << 16)
10309 #define   DKL_PLL_DIV1_IREF_TRIM_MASK		(0x1F << 16)
10310 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)	((x) << 0)
10311 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK	(0xFF << 0)
10312 #define DKL_PLL_DIV1(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10313 						    _DKL_PHY2_BASE) + \
10314 						    _DKL_PLL_DIV1)
10315 
10316 #define _DKL_PLL_SSC				0x210
10317 #define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)	((x) << 29)
10318 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK	(0x7 << 29)
10319 #define   DKL_PLL_SSC_STEP_LEN(x)		((x) << 16)
10320 #define   DKL_PLL_SSC_STEP_LEN_MASK		(0xFF << 16)
10321 #define   DKL_PLL_SSC_STEP_NUM(x)		((x) << 11)
10322 #define   DKL_PLL_SSC_STEP_NUM_MASK		(0x7 << 11)
10323 #define   DKL_PLL_SSC_EN			(1 << 9)
10324 #define DKL_PLL_SSC(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10325 						    _DKL_PHY2_BASE) + \
10326 						    _DKL_PLL_SSC)
10327 
10328 #define _DKL_PLL_BIAS			0x214
10329 #define   DKL_PLL_BIAS_FRAC_EN_H	(1 << 30)
10330 #define   DKL_PLL_BIAS_FBDIV_SHIFT	(8)
10331 #define   DKL_PLL_BIAS_FBDIV_FRAC(x)	((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
10332 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK	(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
10333 #define DKL_PLL_BIAS(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10334 						    _DKL_PHY2_BASE) + \
10335 						    _DKL_PLL_BIAS)
10336 
10337 #define _DKL_PLL_TDC_COLDST_BIAS		0x218
10338 #define   DKL_PLL_TDC_SSC_STEP_SIZE(x)		((x) << 8)
10339 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK	(0xFF << 8)
10340 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)		((x) << 0)
10341 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK	(0xFF << 0)
10342 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
10343 						     _DKL_PHY1_BASE, \
10344 						     _DKL_PHY2_BASE) + \
10345 						     _DKL_PLL_TDC_COLDST_BIAS)
10346 
10347 #define _DKL_REFCLKIN_CTL		0x12C
10348 /* Bits are the same as MG_REFCLKIN_CTL */
10349 #define DKL_REFCLKIN_CTL(tc_port)	_MMIO(_PORT(tc_port, \
10350 						    _DKL_PHY1_BASE, \
10351 						    _DKL_PHY2_BASE) + \
10352 					      _DKL_REFCLKIN_CTL)
10353 
10354 #define _DKL_CLKTOP2_HSCLKCTL		0xD4
10355 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */
10356 #define DKL_CLKTOP2_HSCLKCTL(tc_port)	_MMIO(_PORT(tc_port, \
10357 						    _DKL_PHY1_BASE, \
10358 						    _DKL_PHY2_BASE) + \
10359 					      _DKL_CLKTOP2_HSCLKCTL)
10360 
10361 #define _DKL_CLKTOP2_CORECLKCTL1		0xD8
10362 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
10363 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)	_MMIO(_PORT(tc_port, \
10364 							    _DKL_PHY1_BASE, \
10365 							    _DKL_PHY2_BASE) + \
10366 						      _DKL_CLKTOP2_CORECLKCTL1)
10367 
10368 #define _DKL_TX_DPCNTL0				0x2C0
10369 #define  DKL_TX_PRESHOOT_COEFF(x)			((x) << 13)
10370 #define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
10371 #define  DKL_TX_DE_EMPHASIS_COEFF(x)		((x) << 8)
10372 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK		(0x1f << 8)
10373 #define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
10374 #define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
10375 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
10376 						     _DKL_PHY1_BASE, \
10377 						     _DKL_PHY2_BASE) + \
10378 						     _DKL_TX_DPCNTL0)
10379 
10380 #define _DKL_TX_DPCNTL1				0x2C4
10381 /* Bits are the same as DKL_TX_DPCNTRL0 */
10382 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
10383 						     _DKL_PHY1_BASE, \
10384 						     _DKL_PHY2_BASE) + \
10385 						     _DKL_TX_DPCNTL1)
10386 
10387 #define _DKL_TX_DPCNTL2				0x2C8
10388 #define  DKL_TX_DP20BITMODE				(1 << 2)
10389 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
10390 						     _DKL_PHY1_BASE, \
10391 						     _DKL_PHY2_BASE) + \
10392 						     _DKL_TX_DPCNTL2)
10393 
10394 #define _DKL_TX_FW_CALIB				0x2F8
10395 #define  DKL_TX_CFG_DISABLE_WAIT_INIT			(1 << 7)
10396 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
10397 						     _DKL_PHY1_BASE, \
10398 						     _DKL_PHY2_BASE) + \
10399 						     _DKL_TX_FW_CALIB)
10400 
10401 #define _DKL_TX_PMD_LANE_SUS				0xD00
10402 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
10403 							  _DKL_PHY1_BASE, \
10404 							  _DKL_PHY2_BASE) + \
10405 							  _DKL_TX_PMD_LANE_SUS)
10406 
10407 #define _DKL_TX_DW17					0xDC4
10408 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
10409 						     _DKL_PHY1_BASE, \
10410 						     _DKL_PHY2_BASE) + \
10411 						     _DKL_TX_DW17)
10412 
10413 #define _DKL_TX_DW18					0xDC8
10414 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
10415 						     _DKL_PHY1_BASE, \
10416 						     _DKL_PHY2_BASE) + \
10417 						     _DKL_TX_DW18)
10418 
10419 #define _DKL_DP_MODE					0xA0
10420 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
10421 						     _DKL_PHY1_BASE, \
10422 						     _DKL_PHY2_BASE) + \
10423 						     _DKL_DP_MODE)
10424 
10425 #define _DKL_CMN_UC_DW27			0x36C
10426 #define  DKL_CMN_UC_DW27_UC_HEALTH		(0x1 << 15)
10427 #define DKL_CMN_UC_DW_27(tc_port)		_MMIO(_PORT(tc_port, \
10428 							    _DKL_PHY1_BASE, \
10429 							    _DKL_PHY2_BASE) + \
10430 							    _DKL_CMN_UC_DW27)
10431 
10432 /*
10433  * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
10434  * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
10435  * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
10436  * bits that point the 4KB window into the full PHY register space.
10437  */
10438 #define _HIP_INDEX_REG0			0x1010A0
10439 #define _HIP_INDEX_REG1			0x1010A4
10440 #define HIP_INDEX_REG(tc_port)		_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
10441 					      : _HIP_INDEX_REG1)
10442 #define _HIP_INDEX_SHIFT(tc_port)	(8 * ((tc_port) % 4))
10443 #define HIP_INDEX_VAL(tc_port, val)	((val) << _HIP_INDEX_SHIFT(tc_port))
10444 
10445 /* BXT display engine PLL */
10446 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
10447 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
10448 #define   BXT_DE_PLL_RATIO_MASK		0xff
10449 
10450 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
10451 #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
10452 #define   BXT_DE_PLL_LOCK		(1 << 30)
10453 #define   CNL_CDCLK_PLL_RATIO(x)	(x)
10454 #define   CNL_CDCLK_PLL_RATIO_MASK	0xff
10455 
10456 /* GEN9 DC */
10457 #define DC_STATE_EN			_MMIO(0x45504)
10458 #define  DC_STATE_DISABLE		0
10459 #define  DC_STATE_EN_DC3CO		REG_BIT(30)
10460 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
10461 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
10462 #define  DC_STATE_EN_DC9		(1 << 3)
10463 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
10464 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
10465 
10466 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
10467 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
10468 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
10469 
10470 #define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10471 #define  BXT_REQ_DATA_MASK			0x3F
10472 #define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT		12
10473 #define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)
10474 #define  BXT_MEMORY_FREQ_MULTIPLIER_HZ		133333333
10475 
10476 #define BXT_D_CR_DRP0_DUNIT8			0x1000
10477 #define BXT_D_CR_DRP0_DUNIT9			0x1200
10478 #define  BXT_D_CR_DRP0_DUNIT_START		8
10479 #define  BXT_D_CR_DRP0_DUNIT_END		11
10480 #define BXT_D_CR_DRP0_DUNIT(x)	_MMIO(MCHBAR_MIRROR_BASE_SNB + \
10481 				      _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10482 						 BXT_D_CR_DRP0_DUNIT9))
10483 #define  BXT_DRAM_RANK_MASK			0x3
10484 #define  BXT_DRAM_RANK_SINGLE			0x1
10485 #define  BXT_DRAM_RANK_DUAL			0x3
10486 #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
10487 #define  BXT_DRAM_WIDTH_SHIFT			4
10488 #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
10489 #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
10490 #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
10491 #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
10492 #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
10493 #define  BXT_DRAM_SIZE_SHIFT			6
10494 #define  BXT_DRAM_SIZE_4GBIT			(0x0 << 6)
10495 #define  BXT_DRAM_SIZE_6GBIT			(0x1 << 6)
10496 #define  BXT_DRAM_SIZE_8GBIT			(0x2 << 6)
10497 #define  BXT_DRAM_SIZE_12GBIT			(0x3 << 6)
10498 #define  BXT_DRAM_SIZE_16GBIT			(0x4 << 6)
10499 #define  BXT_DRAM_TYPE_MASK			(0x7 << 22)
10500 #define  BXT_DRAM_TYPE_SHIFT			22
10501 #define  BXT_DRAM_TYPE_DDR3			(0x0 << 22)
10502 #define  BXT_DRAM_TYPE_LPDDR3			(0x1 << 22)
10503 #define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)
10504 #define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)
10505 
10506 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
10507 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10508 #define  SKL_REQ_DATA_MASK			(0xF << 0)
10509 
10510 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10511 #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
10512 #define  SKL_DRAM_DDR_TYPE_DDR4			(0 << 0)
10513 #define  SKL_DRAM_DDR_TYPE_DDR3			(1 << 0)
10514 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
10515 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
10516 
10517 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10518 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10519 #define  SKL_DRAM_S_SHIFT			16
10520 #define  SKL_DRAM_SIZE_MASK			0x3F
10521 #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
10522 #define  SKL_DRAM_WIDTH_SHIFT			8
10523 #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
10524 #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
10525 #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
10526 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
10527 #define  SKL_DRAM_RANK_SHIFT			10
10528 #define  SKL_DRAM_RANK_1			(0x0 << 10)
10529 #define  SKL_DRAM_RANK_2			(0x1 << 10)
10530 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
10531 #define  CNL_DRAM_SIZE_MASK			0x7F
10532 #define  CNL_DRAM_WIDTH_MASK			(0x3 << 7)
10533 #define  CNL_DRAM_WIDTH_SHIFT			7
10534 #define  CNL_DRAM_WIDTH_X8			(0x0 << 7)
10535 #define  CNL_DRAM_WIDTH_X16			(0x1 << 7)
10536 #define  CNL_DRAM_WIDTH_X32			(0x2 << 7)
10537 #define  CNL_DRAM_RANK_MASK			(0x3 << 9)
10538 #define  CNL_DRAM_RANK_SHIFT			9
10539 #define  CNL_DRAM_RANK_1			(0x0 << 9)
10540 #define  CNL_DRAM_RANK_2			(0x1 << 9)
10541 #define  CNL_DRAM_RANK_3			(0x2 << 9)
10542 #define  CNL_DRAM_RANK_4			(0x3 << 9)
10543 
10544 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10545  * since on HSW we can't write to it using I915_WRITE. */
10546 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10547 #define D_COMP_BDW			_MMIO(0x138144)
10548 #define  D_COMP_RCOMP_IN_PROGRESS	(1 << 9)
10549 #define  D_COMP_COMP_FORCE		(1 << 8)
10550 #define  D_COMP_COMP_DISABLE		(1 << 0)
10551 
10552 /* Pipe WM_LINETIME - watermark line time */
10553 #define _WM_LINETIME_A		0x45270
10554 #define _WM_LINETIME_B		0x45274
10555 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
10556 #define  HSW_LINETIME_MASK	REG_GENMASK(8, 0)
10557 #define  HSW_LINETIME(x)	REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
10558 #define  HSW_IPS_LINETIME_MASK	REG_GENMASK(24, 16)
10559 #define  HSW_IPS_LINETIME(x)	REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
10560 
10561 /* SFUSE_STRAP */
10562 #define SFUSE_STRAP			_MMIO(0xc2014)
10563 #define  SFUSE_STRAP_FUSE_LOCK		(1 << 13)
10564 #define  SFUSE_STRAP_RAW_FREQUENCY	(1 << 8)
10565 #define  SFUSE_STRAP_DISPLAY_DISABLED	(1 << 7)
10566 #define  SFUSE_STRAP_CRT_DISABLED	(1 << 6)
10567 #define  SFUSE_STRAP_DDIF_DETECTED	(1 << 3)
10568 #define  SFUSE_STRAP_DDIB_DETECTED	(1 << 2)
10569 #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
10570 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
10571 
10572 #define WM_MISC				_MMIO(0x45260)
10573 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
10574 
10575 #define WM_DBG				_MMIO(0x45280)
10576 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
10577 #define  WM_DBG_DISALLOW_MAXFIFO	(1 << 1)
10578 #define  WM_DBG_DISALLOW_SPRITE		(1 << 2)
10579 
10580 /* pipe CSC */
10581 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
10582 #define _PIPE_A_CSC_COEFF_BY	0x49014
10583 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
10584 #define _PIPE_A_CSC_COEFF_BU	0x4901c
10585 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
10586 #define _PIPE_A_CSC_COEFF_BV	0x49024
10587 
10588 #define _PIPE_A_CSC_MODE	0x49028
10589 #define  ICL_CSC_ENABLE			(1 << 31) /* icl+ */
10590 #define  ICL_OUTPUT_CSC_ENABLE		(1 << 30) /* icl+ */
10591 #define  CSC_BLACK_SCREEN_OFFSET	(1 << 2) /* ilk/snb */
10592 #define  CSC_POSITION_BEFORE_GAMMA	(1 << 1) /* pre-glk */
10593 #define  CSC_MODE_YUV_TO_RGB		(1 << 0) /* ilk/snb */
10594 
10595 #define _PIPE_A_CSC_PREOFF_HI	0x49030
10596 #define _PIPE_A_CSC_PREOFF_ME	0x49034
10597 #define _PIPE_A_CSC_PREOFF_LO	0x49038
10598 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
10599 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
10600 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
10601 
10602 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
10603 #define _PIPE_B_CSC_COEFF_BY	0x49114
10604 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
10605 #define _PIPE_B_CSC_COEFF_BU	0x4911c
10606 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
10607 #define _PIPE_B_CSC_COEFF_BV	0x49124
10608 #define _PIPE_B_CSC_MODE	0x49128
10609 #define _PIPE_B_CSC_PREOFF_HI	0x49130
10610 #define _PIPE_B_CSC_PREOFF_ME	0x49134
10611 #define _PIPE_B_CSC_PREOFF_LO	0x49138
10612 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
10613 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
10614 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
10615 
10616 #define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
10617 #define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
10618 #define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
10619 #define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
10620 #define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
10621 #define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
10622 #define PIPE_CSC_MODE(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
10623 #define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
10624 #define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
10625 #define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
10626 #define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
10627 #define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
10628 #define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
10629 
10630 /* Pipe Output CSC */
10631 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
10632 #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
10633 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
10634 #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
10635 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
10636 #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
10637 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
10638 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
10639 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
10640 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
10641 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
10642 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
10643 
10644 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
10645 #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
10646 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
10647 #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
10648 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
10649 #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
10650 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
10651 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
10652 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
10653 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
10654 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
10655 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
10656 
10657 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe,\
10658 							   _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
10659 							   _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
10660 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe)		_MMIO_PIPE(pipe, \
10661 							   _PIPE_A_OUTPUT_CSC_COEFF_BY, \
10662 							   _PIPE_B_OUTPUT_CSC_COEFF_BY)
10663 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, \
10664 							   _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
10665 							   _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
10666 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe)		_MMIO_PIPE(pipe, \
10667 							   _PIPE_A_OUTPUT_CSC_COEFF_BU, \
10668 							   _PIPE_B_OUTPUT_CSC_COEFF_BU)
10669 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, \
10670 							   _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
10671 							   _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
10672 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe)		_MMIO_PIPE(pipe, \
10673 							   _PIPE_A_OUTPUT_CSC_COEFF_BV, \
10674 							   _PIPE_B_OUTPUT_CSC_COEFF_BV)
10675 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)		_MMIO_PIPE(pipe, \
10676 							   _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
10677 							   _PIPE_B_OUTPUT_CSC_PREOFF_HI)
10678 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)		_MMIO_PIPE(pipe, \
10679 							   _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
10680 							   _PIPE_B_OUTPUT_CSC_PREOFF_ME)
10681 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)		_MMIO_PIPE(pipe, \
10682 							   _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
10683 							   _PIPE_B_OUTPUT_CSC_PREOFF_LO)
10684 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, \
10685 							   _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
10686 							   _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
10687 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, \
10688 							   _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
10689 							   _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
10690 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, \
10691 							   _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
10692 							   _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
10693 
10694 /* pipe degamma/gamma LUTs on IVB+ */
10695 #define _PAL_PREC_INDEX_A	0x4A400
10696 #define _PAL_PREC_INDEX_B	0x4AC00
10697 #define _PAL_PREC_INDEX_C	0x4B400
10698 #define   PAL_PREC_10_12_BIT		(0 << 31)
10699 #define   PAL_PREC_SPLIT_MODE		(1 << 31)
10700 #define   PAL_PREC_AUTO_INCREMENT	(1 << 15)
10701 #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
10702 #define   PAL_PREC_INDEX_VALUE(x)	((x) << 0)
10703 #define _PAL_PREC_DATA_A	0x4A404
10704 #define _PAL_PREC_DATA_B	0x4AC04
10705 #define _PAL_PREC_DATA_C	0x4B404
10706 #define _PAL_PREC_GC_MAX_A	0x4A410
10707 #define _PAL_PREC_GC_MAX_B	0x4AC10
10708 #define _PAL_PREC_GC_MAX_C	0x4B410
10709 #define   PREC_PAL_DATA_RED_MASK	REG_GENMASK(29, 20)
10710 #define   PREC_PAL_DATA_GREEN_MASK	REG_GENMASK(19, 10)
10711 #define   PREC_PAL_DATA_BLUE_MASK	REG_GENMASK(9, 0)
10712 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
10713 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
10714 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
10715 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
10716 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
10717 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
10718 
10719 #define PREC_PAL_INDEX(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
10720 #define PREC_PAL_DATA(pipe)		_MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
10721 #define PREC_PAL_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
10722 #define PREC_PAL_EXT_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
10723 #define PREC_PAL_EXT2_GC_MAX(pipe, i)	_MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
10724 
10725 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
10726 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
10727 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
10728 #define   PRE_CSC_GAMC_AUTO_INCREMENT	(1 << 10)
10729 #define _PRE_CSC_GAMC_DATA_A	0x4A488
10730 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
10731 #define _PRE_CSC_GAMC_DATA_C	0x4B488
10732 
10733 #define PRE_CSC_GAMC_INDEX(pipe)	_MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
10734 #define PRE_CSC_GAMC_DATA(pipe)		_MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
10735 
10736 /* ICL Multi segmented gamma */
10737 #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
10738 #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
10739 #define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT		REG_BIT(15)
10740 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
10741 
10742 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
10743 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
10744 
10745 #define PREC_PAL_MULTI_SEG_INDEX(pipe)	_MMIO_PIPE(pipe, \
10746 					_PAL_PREC_MULTI_SEG_INDEX_A, \
10747 					_PAL_PREC_MULTI_SEG_INDEX_B)
10748 #define PREC_PAL_MULTI_SEG_DATA(pipe)	_MMIO_PIPE(pipe, \
10749 					_PAL_PREC_MULTI_SEG_DATA_A, \
10750 					_PAL_PREC_MULTI_SEG_DATA_B)
10751 
10752 /* pipe CSC & degamma/gamma LUTs on CHV */
10753 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
10754 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
10755 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
10756 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
10757 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
10758 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
10759 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
10760 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
10761 #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
10762 #define   CGM_PIPE_MODE_CSC	(1 << 1)
10763 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
10764 #define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)
10765 #define   CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
10766 #define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)
10767 
10768 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
10769 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
10770 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
10771 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
10772 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
10773 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
10774 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
10775 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
10776 
10777 #define CGM_PIPE_CSC_COEFF01(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
10778 #define CGM_PIPE_CSC_COEFF23(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
10779 #define CGM_PIPE_CSC_COEFF45(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
10780 #define CGM_PIPE_CSC_COEFF67(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
10781 #define CGM_PIPE_CSC_COEFF8(pipe)	_MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
10782 #define CGM_PIPE_DEGAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
10783 #define CGM_PIPE_GAMMA(pipe, i, w)	_MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
10784 #define CGM_PIPE_MODE(pipe)		_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
10785 
10786 /* MIPI DSI registers */
10787 
10788 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
10789 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
10790 
10791 /* Gen11 DSI */
10792 #define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
10793 						    dsi0, dsi1)
10794 
10795 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
10796 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
10797 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
10798 #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
10799 
10800 #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
10801 #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
10802 #define ICL_DSI_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
10803 							_ICL_DSI_ESC_CLK_DIV0, \
10804 							_ICL_DSI_ESC_CLK_DIV1)
10805 #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
10806 #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
10807 #define ICL_DPHY_ESC_CLK_DIV(port)	_MMIO_PORT((port),	\
10808 						_ICL_DPHY_ESC_CLK_DIV0, \
10809 						_ICL_DPHY_ESC_CLK_DIV1)
10810 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
10811 #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT	16
10812 #define  ICL_ESC_CLK_DIV_MASK			0x1ff
10813 #define  ICL_ESC_CLK_DIV_SHIFT			0
10814 #define DSI_MAX_ESC_CLK			20000		/* in KHz */
10815 
10816 #define _DSI_CMD_FRMCTL_0		0x6b034
10817 #define _DSI_CMD_FRMCTL_1		0x6b834
10818 #define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
10819 						   _DSI_CMD_FRMCTL_0,\
10820 						   _DSI_CMD_FRMCTL_1)
10821 #define   DSI_FRAME_UPDATE_REQUEST		(1 << 31)
10822 #define   DSI_PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
10823 #define   DSI_NULL_PACKET_ENABLE		(1 << 28)
10824 #define   DSI_FRAME_IN_PROGRESS			(1 << 0)
10825 
10826 #define _DSI_INTR_MASK_REG_0		0x6b070
10827 #define _DSI_INTR_MASK_REG_1		0x6b870
10828 #define DSI_INTR_MASK_REG(port)		_MMIO_PORT(port,	\
10829 						   _DSI_INTR_MASK_REG_0,\
10830 						   _DSI_INTR_MASK_REG_1)
10831 
10832 #define _DSI_INTR_IDENT_REG_0		0x6b074
10833 #define _DSI_INTR_IDENT_REG_1		0x6b874
10834 #define DSI_INTR_IDENT_REG(port)	_MMIO_PORT(port,	\
10835 						   _DSI_INTR_IDENT_REG_0,\
10836 						   _DSI_INTR_IDENT_REG_1)
10837 #define   DSI_TE_EVENT				(1 << 31)
10838 #define   DSI_RX_DATA_OR_BTA_TERMINATED		(1 << 30)
10839 #define   DSI_TX_DATA				(1 << 29)
10840 #define   DSI_ULPS_ENTRY_DONE			(1 << 28)
10841 #define   DSI_NON_TE_TRIGGER_RECEIVED		(1 << 27)
10842 #define   DSI_HOST_CHKSUM_ERROR			(1 << 26)
10843 #define   DSI_HOST_MULTI_ECC_ERROR		(1 << 25)
10844 #define   DSI_HOST_SINGL_ECC_ERROR		(1 << 24)
10845 #define   DSI_HOST_CONTENTION_DETECTED		(1 << 23)
10846 #define   DSI_HOST_FALSE_CONTROL_ERROR		(1 << 22)
10847 #define   DSI_HOST_TIMEOUT_ERROR		(1 << 21)
10848 #define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR	(1 << 20)
10849 #define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR	(1 << 19)
10850 #define   DSI_FRAME_UPDATE_DONE			(1 << 16)
10851 #define   DSI_PROTOCOL_VIOLATION_REPORTED	(1 << 15)
10852 #define   DSI_INVALID_TX_LENGTH			(1 << 13)
10853 #define   DSI_INVALID_VC			(1 << 12)
10854 #define   DSI_INVALID_DATA_TYPE			(1 << 11)
10855 #define   DSI_PERIPHERAL_CHKSUM_ERROR		(1 << 10)
10856 #define   DSI_PERIPHERAL_MULTI_ECC_ERROR	(1 << 9)
10857 #define   DSI_PERIPHERAL_SINGLE_ECC_ERROR	(1 << 8)
10858 #define   DSI_PERIPHERAL_CONTENTION_DETECTED	(1 << 7)
10859 #define   DSI_PERIPHERAL_FALSE_CTRL_ERROR	(1 << 6)
10860 #define   DSI_PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
10861 #define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR	(1 << 4)
10862 #define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR	(1 << 3)
10863 #define   DSI_EOT_SYNC_ERROR			(1 << 2)
10864 #define   DSI_SOT_SYNC_ERROR			(1 << 1)
10865 #define   DSI_SOT_ERROR				(1 << 0)
10866 
10867 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
10868 #define GEN4_TIMESTAMP		_MMIO(0x2358)
10869 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
10870 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
10871 
10872 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
10873 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
10874 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
10875 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT	12
10876 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
10877 
10878 #define _PIPE_FRMTMSTMP_A		0x70048
10879 #define PIPE_FRMTMSTMP(pipe)		\
10880 			_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
10881 
10882 /* BXT MIPI clock controls */
10883 #define BXT_MAX_VAR_OUTPUT_KHZ			39500
10884 
10885 #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
10886 #define  BXT_MIPI1_DIV_SHIFT			26
10887 #define  BXT_MIPI2_DIV_SHIFT			10
10888 #define  BXT_MIPI_DIV_SHIFT(port)		\
10889 			_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10890 					BXT_MIPI2_DIV_SHIFT)
10891 
10892 /* TX control divider to select actual TX clock output from (8x/var) */
10893 #define  BXT_MIPI1_TX_ESCLK_SHIFT		26
10894 #define  BXT_MIPI2_TX_ESCLK_SHIFT		10
10895 #define  BXT_MIPI_TX_ESCLK_SHIFT(port)		\
10896 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10897 					BXT_MIPI2_TX_ESCLK_SHIFT)
10898 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
10899 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
10900 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
10901 			_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10902 					BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10903 #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)	\
10904 		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10905 /* RX upper control divider to select actual RX clock output from 8x */
10906 #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT		21
10907 #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT		5
10908 #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)		\
10909 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10910 					BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10911 #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 21)
10912 #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK		(3 << 5)
10913 #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)	\
10914 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10915 					BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10916 #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)	\
10917 		(((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10918 /* 8/3X divider to select the actual 8/3X clock output from 8x */
10919 #define  BXT_MIPI1_8X_BY3_SHIFT                19
10920 #define  BXT_MIPI2_8X_BY3_SHIFT                3
10921 #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
10922 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10923 					BXT_MIPI2_8X_BY3_SHIFT)
10924 #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
10925 #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
10926 #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
10927 			_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10928 						BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10929 #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
10930 			(((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10931 /* RX lower control divider to select actual RX clock output from 8x */
10932 #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT		16
10933 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
10934 #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)		\
10935 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10936 					BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10937 #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 16)
10938 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
10939 #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)	\
10940 			_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10941 					BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10942 #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)	\
10943 		(((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10944 
10945 #define RX_DIVIDER_BIT_1_2                     0x3
10946 #define RX_DIVIDER_BIT_3_4                     0xC
10947 
10948 /* BXT MIPI mode configure */
10949 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
10950 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
10951 #define  BXT_MIPI_TRANS_HACTIVE(tc)	_MMIO_MIPI(tc, \
10952 		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10953 
10954 #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
10955 #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
10956 #define  BXT_MIPI_TRANS_VACTIVE(tc)	_MMIO_MIPI(tc, \
10957 		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10958 
10959 #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
10960 #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
10961 #define  BXT_MIPI_TRANS_VTOTAL(tc)	_MMIO_MIPI(tc, \
10962 		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10963 
10964 #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
10965 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
10966 #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10967 #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10968 #define  BXT_DSIC_16X_BY1		(0 << 10)
10969 #define  BXT_DSIC_16X_BY2		(1 << 10)
10970 #define  BXT_DSIC_16X_BY3		(2 << 10)
10971 #define  BXT_DSIC_16X_BY4		(3 << 10)
10972 #define  BXT_DSIC_16X_MASK		(3 << 10)
10973 #define  BXT_DSIA_16X_BY1		(0 << 8)
10974 #define  BXT_DSIA_16X_BY2		(1 << 8)
10975 #define  BXT_DSIA_16X_BY3		(2 << 8)
10976 #define  BXT_DSIA_16X_BY4		(3 << 8)
10977 #define  BXT_DSIA_16X_MASK		(3 << 8)
10978 #define  BXT_DSI_FREQ_SEL_SHIFT		8
10979 #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
10980 
10981 #define BXT_DSI_PLL_RATIO_MAX		0x7D
10982 #define BXT_DSI_PLL_RATIO_MIN		0x22
10983 #define GLK_DSI_PLL_RATIO_MAX		0x6F
10984 #define GLK_DSI_PLL_RATIO_MIN		0x22
10985 #define BXT_DSI_PLL_RATIO_MASK		0xFF
10986 #define BXT_REF_CLOCK_KHZ		19200
10987 
10988 #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
10989 #define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
10990 #define  BXT_DSI_PLL_LOCKED		(1 << 30)
10991 
10992 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
10993 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
10994 #define MIPI_PORT_CTRL(port)	_MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10995 
10996  /* BXT port control */
10997 #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
10998 #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
10999 #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
11000 
11001 /* ICL DSI MODE control */
11002 #define _ICL_DSI_IO_MODECTL_0				0x6B094
11003 #define _ICL_DSI_IO_MODECTL_1				0x6B894
11004 #define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
11005 						    _ICL_DSI_IO_MODECTL_0, \
11006 						    _ICL_DSI_IO_MODECTL_1)
11007 #define  COMBO_PHY_MODE_DSI				(1 << 0)
11008 
11009 /* Display Stream Splitter Control */
11010 #define DSS_CTL1				_MMIO(0x67400)
11011 #define  SPLITTER_ENABLE			(1 << 31)
11012 #define  JOINER_ENABLE				(1 << 30)
11013 #define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
11014 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
11015 #define  OVERLAP_PIXELS_MASK			(0xf << 16)
11016 #define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
11017 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11018 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11019 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
11020 
11021 #define DSS_CTL2				_MMIO(0x67404)
11022 #define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
11023 #define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
11024 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11025 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11026 
11027 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
11028 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
11029 #define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
11030 							   _ICL_PIPE_DSS_CTL1_PB, \
11031 							   _ICL_PIPE_DSS_CTL1_PC)
11032 #define  BIG_JOINER_ENABLE			(1 << 29)
11033 #define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
11034 #define  VGA_CENTERING_ENABLE			(1 << 27)
11035 
11036 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
11037 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
11038 #define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
11039 							   _ICL_PIPE_DSS_CTL2_PB, \
11040 							   _ICL_PIPE_DSS_CTL2_PC)
11041 
11042 #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
11043 #define  STAP_SELECT					(1 << 0)
11044 
11045 #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
11046 #define  HS_IO_CTRL_SELECT				(1 << 0)
11047 
11048 #define  DPI_ENABLE					(1 << 31) /* A + C */
11049 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
11050 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
11051 #define  DUAL_LINK_MODE_SHIFT				26
11052 #define  DUAL_LINK_MODE_MASK				(1 << 26)
11053 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
11054 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
11055 #define  DITHERING_ENABLE				(1 << 25) /* A + C */
11056 #define  FLOPPED_HSTX					(1 << 23)
11057 #define  DE_INVERT					(1 << 19) /* XXX */
11058 #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
11059 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
11060 #define  AFE_LATCHOUT					(1 << 17)
11061 #define  LP_OUTPUT_HOLD					(1 << 16)
11062 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
11063 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
11064 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
11065 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
11066 #define  CSB_SHIFT					9
11067 #define  CSB_MASK					(3 << 9)
11068 #define  CSB_20MHZ					(0 << 9)
11069 #define  CSB_10MHZ					(1 << 9)
11070 #define  CSB_40MHZ					(2 << 9)
11071 #define  BANDGAP_MASK					(1 << 8)
11072 #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
11073 #define  BANDGAP_LNC_CIRCUIT				(1 << 8)
11074 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
11075 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
11076 #define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
11077 #define  TEARING_EFFECT_SHIFT				2 /* A + C */
11078 #define  TEARING_EFFECT_MASK				(3 << 2)
11079 #define  TEARING_EFFECT_OFF				(0 << 2)
11080 #define  TEARING_EFFECT_DSI				(1 << 2)
11081 #define  TEARING_EFFECT_GPIO				(2 << 2)
11082 #define  LANE_CONFIGURATION_SHIFT			0
11083 #define  LANE_CONFIGURATION_MASK			(3 << 0)
11084 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
11085 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
11086 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
11087 
11088 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
11089 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
11090 #define MIPI_TEARING_CTRL(port)			_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
11091 #define  TEARING_EFFECT_DELAY_SHIFT			0
11092 #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
11093 
11094 /* XXX: all bits reserved */
11095 #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
11096 
11097 /* MIPI DSI Controller and D-PHY registers */
11098 
11099 #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
11100 #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
11101 #define MIPI_DEVICE_READY(port)		_MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
11102 #define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
11103 #define  ULPS_STATE_MASK				(3 << 1)
11104 #define  ULPS_STATE_ENTER				(2 << 1)
11105 #define  ULPS_STATE_EXIT				(1 << 1)
11106 #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
11107 #define  DEVICE_READY					(1 << 0)
11108 
11109 #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
11110 #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
11111 #define MIPI_INTR_STAT(port)		_MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
11112 #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
11113 #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
11114 #define MIPI_INTR_EN(port)		_MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
11115 #define  TEARING_EFFECT					(1 << 31)
11116 #define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
11117 #define  GEN_READ_DATA_AVAIL				(1 << 29)
11118 #define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
11119 #define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
11120 #define  RX_PROT_VIOLATION				(1 << 26)
11121 #define  RX_INVALID_TX_LENGTH				(1 << 25)
11122 #define  ACK_WITH_NO_ERROR				(1 << 24)
11123 #define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
11124 #define  LP_RX_TIMEOUT					(1 << 22)
11125 #define  HS_TX_TIMEOUT					(1 << 21)
11126 #define  DPI_FIFO_UNDERRUN				(1 << 20)
11127 #define  LOW_CONTENTION					(1 << 19)
11128 #define  HIGH_CONTENTION				(1 << 18)
11129 #define  TXDSI_VC_ID_INVALID				(1 << 17)
11130 #define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
11131 #define  TXCHECKSUM_ERROR				(1 << 15)
11132 #define  TXECC_MULTIBIT_ERROR				(1 << 14)
11133 #define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
11134 #define  TXFALSE_CONTROL_ERROR				(1 << 12)
11135 #define  RXDSI_VC_ID_INVALID				(1 << 11)
11136 #define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
11137 #define  RXCHECKSUM_ERROR				(1 << 9)
11138 #define  RXECC_MULTIBIT_ERROR				(1 << 8)
11139 #define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
11140 #define  RXFALSE_CONTROL_ERROR				(1 << 6)
11141 #define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
11142 #define  RX_LP_TX_SYNC_ERROR				(1 << 4)
11143 #define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
11144 #define  RXEOT_SYNC_ERROR				(1 << 2)
11145 #define  RXSOT_SYNC_ERROR				(1 << 1)
11146 #define  RXSOT_ERROR					(1 << 0)
11147 
11148 #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
11149 #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
11150 #define MIPI_DSI_FUNC_PRG(port)		_MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
11151 #define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
11152 #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
11153 #define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
11154 #define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
11155 #define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
11156 #define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
11157 #define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
11158 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
11159 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
11160 #define  VID_MODE_FORMAT_RGB565				(1 << 7)
11161 #define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
11162 #define  VID_MODE_FORMAT_RGB666				(3 << 7)
11163 #define  VID_MODE_FORMAT_RGB888				(4 << 7)
11164 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
11165 #define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
11166 #define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
11167 #define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
11168 #define  DATA_LANES_PRG_REG_SHIFT			0
11169 #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
11170 
11171 #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
11172 #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
11173 #define MIPI_HS_TX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
11174 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
11175 
11176 #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
11177 #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
11178 #define MIPI_LP_RX_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
11179 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
11180 
11181 #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
11182 #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
11183 #define MIPI_TURN_AROUND_TIMEOUT(port)	_MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
11184 #define  TURN_AROUND_TIMEOUT_MASK			0x3f
11185 
11186 #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
11187 #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
11188 #define MIPI_DEVICE_RESET_TIMER(port)	_MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
11189 #define  DEVICE_RESET_TIMER_MASK			0xffff
11190 
11191 #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
11192 #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
11193 #define MIPI_DPI_RESOLUTION(port)	_MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
11194 #define  VERTICAL_ADDRESS_SHIFT				16
11195 #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
11196 #define  HORIZONTAL_ADDRESS_SHIFT			0
11197 #define  HORIZONTAL_ADDRESS_MASK			0xffff
11198 
11199 #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
11200 #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
11201 #define MIPI_DBI_FIFO_THROTTLE(port)	_MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
11202 #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
11203 #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
11204 #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
11205 
11206 /* regs below are bits 15:0 */
11207 #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
11208 #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
11209 #define MIPI_HSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
11210 
11211 #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
11212 #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
11213 #define MIPI_HBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
11214 
11215 #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
11216 #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
11217 #define MIPI_HFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
11218 
11219 #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
11220 #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
11221 #define MIPI_HACTIVE_AREA_COUNT(port)	_MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
11222 
11223 #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
11224 #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
11225 #define MIPI_VSYNC_PADDING_COUNT(port)	_MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
11226 
11227 #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
11228 #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
11229 #define MIPI_VBP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
11230 
11231 #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
11232 #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
11233 #define MIPI_VFP_COUNT(port)		_MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
11234 
11235 #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
11236 #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
11237 #define MIPI_HIGH_LOW_SWITCH_COUNT(port)	_MMIO_MIPI(port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
11238 
11239 /* regs above are bits 15:0 */
11240 
11241 #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
11242 #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
11243 #define MIPI_DPI_CONTROL(port)		_MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
11244 #define  DPI_LP_MODE					(1 << 6)
11245 #define  BACKLIGHT_OFF					(1 << 5)
11246 #define  BACKLIGHT_ON					(1 << 4)
11247 #define  COLOR_MODE_OFF					(1 << 3)
11248 #define  COLOR_MODE_ON					(1 << 2)
11249 #define  TURN_ON					(1 << 1)
11250 #define  SHUTDOWN					(1 << 0)
11251 
11252 #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
11253 #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
11254 #define MIPI_DPI_DATA(port)		_MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
11255 #define  COMMAND_BYTE_SHIFT				0
11256 #define  COMMAND_BYTE_MASK				(0x3f << 0)
11257 
11258 #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
11259 #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
11260 #define MIPI_INIT_COUNT(port)		_MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
11261 #define  MASTER_INIT_TIMER_SHIFT			0
11262 #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
11263 
11264 #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
11265 #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
11266 #define MIPI_MAX_RETURN_PKT_SIZE(port)	_MMIO_MIPI(port, \
11267 			_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
11268 #define  MAX_RETURN_PKT_SIZE_SHIFT			0
11269 #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
11270 
11271 #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
11272 #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
11273 #define MIPI_VIDEO_MODE_FORMAT(port)	_MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
11274 #define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
11275 #define  DISABLE_VIDEO_BTA				(1 << 3)
11276 #define  IP_TG_CONFIG					(1 << 2)
11277 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
11278 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
11279 #define  VIDEO_MODE_BURST				(3 << 0)
11280 
11281 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
11282 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
11283 #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
11284 #define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
11285 #define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
11286 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
11287 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
11288 #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
11289 #define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
11290 #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
11291 #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
11292 #define  CLOCKSTOP					(1 << 1)
11293 #define  EOT_DISABLE					(1 << 0)
11294 
11295 #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
11296 #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
11297 #define MIPI_LP_BYTECLK(port)		_MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
11298 #define  LP_BYTECLK_SHIFT				0
11299 #define  LP_BYTECLK_MASK				(0xffff << 0)
11300 
11301 #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
11302 #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
11303 #define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
11304 
11305 #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
11306 #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
11307 #define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
11308 
11309 /* bits 31:0 */
11310 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
11311 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
11312 #define MIPI_LP_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
11313 
11314 /* bits 31:0 */
11315 #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
11316 #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
11317 #define MIPI_HS_GEN_DATA(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
11318 
11319 #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
11320 #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
11321 #define MIPI_LP_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
11322 #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
11323 #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
11324 #define MIPI_HS_GEN_CTRL(port)		_MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
11325 #define  LONG_PACKET_WORD_COUNT_SHIFT			8
11326 #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
11327 #define  SHORT_PACKET_PARAM_SHIFT			8
11328 #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
11329 #define  VIRTUAL_CHANNEL_SHIFT				6
11330 #define  VIRTUAL_CHANNEL_MASK				(3 << 6)
11331 #define  DATA_TYPE_SHIFT				0
11332 #define  DATA_TYPE_MASK					(0x3f << 0)
11333 /* data type values, see include/video/mipi_display.h */
11334 
11335 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
11336 #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
11337 #define MIPI_GEN_FIFO_STAT(port)	_MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
11338 #define  DPI_FIFO_EMPTY					(1 << 28)
11339 #define  DBI_FIFO_EMPTY					(1 << 27)
11340 #define  LP_CTRL_FIFO_EMPTY				(1 << 26)
11341 #define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
11342 #define  LP_CTRL_FIFO_FULL				(1 << 24)
11343 #define  HS_CTRL_FIFO_EMPTY				(1 << 18)
11344 #define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
11345 #define  HS_CTRL_FIFO_FULL				(1 << 16)
11346 #define  LP_DATA_FIFO_EMPTY				(1 << 10)
11347 #define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
11348 #define  LP_DATA_FIFO_FULL				(1 << 8)
11349 #define  HS_DATA_FIFO_EMPTY				(1 << 2)
11350 #define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
11351 #define  HS_DATA_FIFO_FULL				(1 << 0)
11352 
11353 #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
11354 #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
11355 #define MIPI_HS_LP_DBI_ENABLE(port)	_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
11356 #define  DBI_HS_LP_MODE_MASK				(1 << 0)
11357 #define  DBI_LP_MODE					(1 << 0)
11358 #define  DBI_HS_MODE					(0 << 0)
11359 
11360 #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
11361 #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
11362 #define MIPI_DPHY_PARAM(port)		_MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
11363 #define  EXIT_ZERO_COUNT_SHIFT				24
11364 #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
11365 #define  TRAIL_COUNT_SHIFT				16
11366 #define  TRAIL_COUNT_MASK				(0x1f << 16)
11367 #define  CLK_ZERO_COUNT_SHIFT				8
11368 #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
11369 #define  PREPARE_COUNT_SHIFT				0
11370 #define  PREPARE_COUNT_MASK				(0x3f << 0)
11371 
11372 #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
11373 #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
11374 #define ICL_DSI_T_INIT_MASTER(port)	_MMIO_PORT(port,	\
11375 						   _ICL_DSI_T_INIT_MASTER_0,\
11376 						   _ICL_DSI_T_INIT_MASTER_1)
11377 
11378 #define _DPHY_CLK_TIMING_PARAM_0	0x162180
11379 #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
11380 #define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11381 						   _DPHY_CLK_TIMING_PARAM_0,\
11382 						   _DPHY_CLK_TIMING_PARAM_1)
11383 #define _DSI_CLK_TIMING_PARAM_0		0x6b080
11384 #define _DSI_CLK_TIMING_PARAM_1		0x6b880
11385 #define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11386 						   _DSI_CLK_TIMING_PARAM_0,\
11387 						   _DSI_CLK_TIMING_PARAM_1)
11388 #define  CLK_PREPARE_OVERRIDE		(1 << 31)
11389 #define  CLK_PREPARE(x)		((x) << 28)
11390 #define  CLK_PREPARE_MASK		(0x7 << 28)
11391 #define  CLK_PREPARE_SHIFT		28
11392 #define  CLK_ZERO_OVERRIDE		(1 << 27)
11393 #define  CLK_ZERO(x)			((x) << 20)
11394 #define  CLK_ZERO_MASK			(0xf << 20)
11395 #define  CLK_ZERO_SHIFT		20
11396 #define  CLK_PRE_OVERRIDE		(1 << 19)
11397 #define  CLK_PRE(x)			((x) << 16)
11398 #define  CLK_PRE_MASK			(0x3 << 16)
11399 #define  CLK_PRE_SHIFT			16
11400 #define  CLK_POST_OVERRIDE		(1 << 15)
11401 #define  CLK_POST(x)			((x) << 8)
11402 #define  CLK_POST_MASK			(0x7 << 8)
11403 #define  CLK_POST_SHIFT		8
11404 #define  CLK_TRAIL_OVERRIDE		(1 << 7)
11405 #define  CLK_TRAIL(x)			((x) << 0)
11406 #define  CLK_TRAIL_MASK		(0xf << 0)
11407 #define  CLK_TRAIL_SHIFT		0
11408 
11409 #define _DPHY_DATA_TIMING_PARAM_0	0x162184
11410 #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
11411 #define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11412 						   _DPHY_DATA_TIMING_PARAM_0,\
11413 						   _DPHY_DATA_TIMING_PARAM_1)
11414 #define _DSI_DATA_TIMING_PARAM_0	0x6B084
11415 #define _DSI_DATA_TIMING_PARAM_1	0x6B884
11416 #define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11417 						   _DSI_DATA_TIMING_PARAM_0,\
11418 						   _DSI_DATA_TIMING_PARAM_1)
11419 #define  HS_PREPARE_OVERRIDE		(1 << 31)
11420 #define  HS_PREPARE(x)			((x) << 24)
11421 #define  HS_PREPARE_MASK		(0x7 << 24)
11422 #define  HS_PREPARE_SHIFT		24
11423 #define  HS_ZERO_OVERRIDE		(1 << 23)
11424 #define  HS_ZERO(x)			((x) << 16)
11425 #define  HS_ZERO_MASK			(0xf << 16)
11426 #define  HS_ZERO_SHIFT			16
11427 #define  HS_TRAIL_OVERRIDE		(1 << 15)
11428 #define  HS_TRAIL(x)			((x) << 8)
11429 #define  HS_TRAIL_MASK			(0x7 << 8)
11430 #define  HS_TRAIL_SHIFT		8
11431 #define  HS_EXIT_OVERRIDE		(1 << 7)
11432 #define  HS_EXIT(x)			((x) << 0)
11433 #define  HS_EXIT_MASK			(0x7 << 0)
11434 #define  HS_EXIT_SHIFT			0
11435 
11436 #define _DPHY_TA_TIMING_PARAM_0		0x162188
11437 #define _DPHY_TA_TIMING_PARAM_1		0x6c188
11438 #define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11439 						   _DPHY_TA_TIMING_PARAM_0,\
11440 						   _DPHY_TA_TIMING_PARAM_1)
11441 #define _DSI_TA_TIMING_PARAM_0		0x6b098
11442 #define _DSI_TA_TIMING_PARAM_1		0x6b898
11443 #define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
11444 						   _DSI_TA_TIMING_PARAM_0,\
11445 						   _DSI_TA_TIMING_PARAM_1)
11446 #define  TA_SURE_OVERRIDE		(1 << 31)
11447 #define  TA_SURE(x)			((x) << 16)
11448 #define  TA_SURE_MASK			(0x1f << 16)
11449 #define  TA_SURE_SHIFT			16
11450 #define  TA_GO_OVERRIDE		(1 << 15)
11451 #define  TA_GO(x)			((x) << 8)
11452 #define  TA_GO_MASK			(0xf << 8)
11453 #define  TA_GO_SHIFT			8
11454 #define  TA_GET_OVERRIDE		(1 << 7)
11455 #define  TA_GET(x)			((x) << 0)
11456 #define  TA_GET_MASK			(0xf << 0)
11457 #define  TA_GET_SHIFT			0
11458 
11459 /* DSI transcoder configuration */
11460 #define _DSI_TRANS_FUNC_CONF_0		0x6b030
11461 #define _DSI_TRANS_FUNC_CONF_1		0x6b830
11462 #define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
11463 						  _DSI_TRANS_FUNC_CONF_0,\
11464 						  _DSI_TRANS_FUNC_CONF_1)
11465 #define  OP_MODE_MASK			(0x3 << 28)
11466 #define  OP_MODE_SHIFT			28
11467 #define  CMD_MODE_NO_GATE		(0x0 << 28)
11468 #define  CMD_MODE_TE_GATE		(0x1 << 28)
11469 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
11470 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
11471 #define  TE_SOURCE_GPIO			(1 << 27)
11472 #define  LINK_READY			(1 << 20)
11473 #define  PIX_FMT_MASK			(0x3 << 16)
11474 #define  PIX_FMT_SHIFT			16
11475 #define  PIX_FMT_RGB565			(0x0 << 16)
11476 #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
11477 #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
11478 #define  PIX_FMT_RGB888			(0x3 << 16)
11479 #define  PIX_FMT_RGB101010		(0x4 << 16)
11480 #define  PIX_FMT_RGB121212		(0x5 << 16)
11481 #define  PIX_FMT_COMPRESSED		(0x6 << 16)
11482 #define  BGR_TRANSMISSION		(1 << 15)
11483 #define  PIX_VIRT_CHAN(x)		((x) << 12)
11484 #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
11485 #define  PIX_VIRT_CHAN_SHIFT		12
11486 #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
11487 #define  PIX_BUF_THRESHOLD_SHIFT	10
11488 #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
11489 #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
11490 #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
11491 #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
11492 #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
11493 #define  CONTINUOUS_CLK_SHIFT		8
11494 #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
11495 #define  CLK_HS_OR_LP			(0x2 << 8)
11496 #define  CLK_HS_CONTINUOUS		(0x3 << 8)
11497 #define  LINK_CALIBRATION_MASK		(0x3 << 4)
11498 #define  LINK_CALIBRATION_SHIFT		4
11499 #define  CALIBRATION_DISABLED		(0x0 << 4)
11500 #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
11501 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
11502 #define  BLANKING_PACKET_ENABLE		(1 << 2)
11503 #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
11504 #define  EOTP_DISABLED			(1 << 0)
11505 
11506 #define _DSI_CMD_RXCTL_0		0x6b0d4
11507 #define _DSI_CMD_RXCTL_1		0x6b8d4
11508 #define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
11509 						  _DSI_CMD_RXCTL_0,\
11510 						  _DSI_CMD_RXCTL_1)
11511 #define  READ_UNLOADS_DW		(1 << 16)
11512 #define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
11513 #define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
11514 #define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
11515 #define  RECEIVED_RESET_TRIGGER		(1 << 12)
11516 #define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
11517 #define  RECEIVED_CRC_WAS_LOST		(1 << 10)
11518 #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
11519 #define  NUMBER_RX_PLOAD_DW_SHIFT	0
11520 
11521 #define _DSI_CMD_TXCTL_0		0x6b0d0
11522 #define _DSI_CMD_TXCTL_1		0x6b8d0
11523 #define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
11524 						  _DSI_CMD_TXCTL_0,\
11525 						  _DSI_CMD_TXCTL_1)
11526 #define  KEEP_LINK_IN_HS		(1 << 24)
11527 #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
11528 #define  FREE_HEADER_CREDIT_SHIFT	0x8
11529 #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
11530 #define  FREE_PLOAD_CREDIT_SHIFT	0
11531 #define  MAX_HEADER_CREDIT		0x10
11532 #define  MAX_PLOAD_CREDIT		0x40
11533 
11534 #define _DSI_CMD_TXHDR_0		0x6b100
11535 #define _DSI_CMD_TXHDR_1		0x6b900
11536 #define DSI_CMD_TXHDR(tc)		_MMIO_DSI(tc,	\
11537 						  _DSI_CMD_TXHDR_0,\
11538 						  _DSI_CMD_TXHDR_1)
11539 #define  PAYLOAD_PRESENT		(1 << 31)
11540 #define  LP_DATA_TRANSFER		(1 << 30)
11541 #define  VBLANK_FENCE			(1 << 29)
11542 #define  PARAM_WC_MASK			(0xffff << 8)
11543 #define  PARAM_WC_LOWER_SHIFT		8
11544 #define  PARAM_WC_UPPER_SHIFT		16
11545 #define  VC_MASK			(0x3 << 6)
11546 #define  VC_SHIFT			6
11547 #define  DT_MASK			(0x3f << 0)
11548 #define  DT_SHIFT			0
11549 
11550 #define _DSI_CMD_TXPYLD_0		0x6b104
11551 #define _DSI_CMD_TXPYLD_1		0x6b904
11552 #define DSI_CMD_TXPYLD(tc)		_MMIO_DSI(tc,	\
11553 						  _DSI_CMD_TXPYLD_0,\
11554 						  _DSI_CMD_TXPYLD_1)
11555 
11556 #define _DSI_LP_MSG_0			0x6b0d8
11557 #define _DSI_LP_MSG_1			0x6b8d8
11558 #define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
11559 						  _DSI_LP_MSG_0,\
11560 						  _DSI_LP_MSG_1)
11561 #define  LPTX_IN_PROGRESS		(1 << 17)
11562 #define  LINK_IN_ULPS			(1 << 16)
11563 #define  LINK_ULPS_TYPE_LP11		(1 << 8)
11564 #define  LINK_ENTER_ULPS		(1 << 0)
11565 
11566 /* DSI timeout registers */
11567 #define _DSI_HSTX_TO_0			0x6b044
11568 #define _DSI_HSTX_TO_1			0x6b844
11569 #define DSI_HSTX_TO(tc)			_MMIO_DSI(tc,	\
11570 						  _DSI_HSTX_TO_0,\
11571 						  _DSI_HSTX_TO_1)
11572 #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
11573 #define  HSTX_TIMEOUT_VALUE_SHIFT	16
11574 #define  HSTX_TIMEOUT_VALUE(x)		((x) << 16)
11575 #define  HSTX_TIMED_OUT			(1 << 0)
11576 
11577 #define _DSI_LPRX_HOST_TO_0		0x6b048
11578 #define _DSI_LPRX_HOST_TO_1		0x6b848
11579 #define DSI_LPRX_HOST_TO(tc)		_MMIO_DSI(tc,	\
11580 						  _DSI_LPRX_HOST_TO_0,\
11581 						  _DSI_LPRX_HOST_TO_1)
11582 #define  LPRX_TIMED_OUT			(1 << 16)
11583 #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
11584 #define  LPRX_TIMEOUT_VALUE_SHIFT	0
11585 #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
11586 
11587 #define _DSI_PWAIT_TO_0			0x6b040
11588 #define _DSI_PWAIT_TO_1			0x6b840
11589 #define DSI_PWAIT_TO(tc)		_MMIO_DSI(tc,	\
11590 						  _DSI_PWAIT_TO_0,\
11591 						  _DSI_PWAIT_TO_1)
11592 #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
11593 #define  PRESET_TIMEOUT_VALUE_SHIFT	16
11594 #define  PRESET_TIMEOUT_VALUE(x)	((x) << 16)
11595 #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
11596 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
11597 #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
11598 
11599 #define _DSI_TA_TO_0			0x6b04c
11600 #define _DSI_TA_TO_1			0x6b84c
11601 #define DSI_TA_TO(tc)			_MMIO_DSI(tc,	\
11602 						  _DSI_TA_TO_0,\
11603 						  _DSI_TA_TO_1)
11604 #define  TA_TIMED_OUT			(1 << 16)
11605 #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
11606 #define  TA_TIMEOUT_VALUE_SHIFT		0
11607 #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
11608 
11609 /* bits 31:0 */
11610 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
11611 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
11612 #define MIPI_DBI_BW_CTRL(port)		_MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
11613 
11614 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
11615 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
11616 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)	_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
11617 #define  LP_HS_SSW_CNT_SHIFT				16
11618 #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
11619 #define  HS_LP_PWR_SW_CNT_SHIFT				0
11620 #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
11621 
11622 #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
11623 #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
11624 #define MIPI_STOP_STATE_STALL(port)	_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
11625 #define  STOP_STATE_STALL_COUNTER_SHIFT			0
11626 #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
11627 
11628 #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
11629 #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
11630 #define MIPI_INTR_STAT_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
11631 #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
11632 #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
11633 #define MIPI_INTR_EN_REG_1(port)	_MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
11634 #define  RX_CONTENTION_DETECTED				(1 << 0)
11635 
11636 /* XXX: only pipe A ?!? */
11637 #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
11638 #define  DBI_TYPEC_ENABLE				(1 << 31)
11639 #define  DBI_TYPEC_WIP					(1 << 30)
11640 #define  DBI_TYPEC_OPTION_SHIFT				28
11641 #define  DBI_TYPEC_OPTION_MASK				(3 << 28)
11642 #define  DBI_TYPEC_FREQ_SHIFT				24
11643 #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
11644 #define  DBI_TYPEC_OVERRIDE				(1 << 8)
11645 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
11646 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
11647 
11648 
11649 /* MIPI adapter registers */
11650 
11651 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
11652 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
11653 #define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
11654 #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
11655 #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
11656 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
11657 #define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
11658 #define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
11659 #define  READ_REQUEST_PRIORITY_SHIFT			3
11660 #define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
11661 #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
11662 #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
11663 #define  RGB_FLIP_TO_BGR				(1 << 2)
11664 
11665 #define  BXT_PIPE_SELECT_SHIFT				7
11666 #define  BXT_PIPE_SELECT_MASK				(7 << 7)
11667 #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
11668 #define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
11669 #define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
11670 #define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
11671 #define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
11672 #define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
11673 #define  GLK_LP_WAKE					(1 << 22)
11674 #define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
11675 #define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
11676 #define  GLK_FIREWALL_ENABLE				(1 << 16)
11677 #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
11678 #define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
11679 #define  BXT_DSC_ENABLE					(1 << 3)
11680 #define  BXT_RGB_FLIP					(1 << 2)
11681 #define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
11682 #define  GLK_MIPIIO_ENABLE				(1 << 0)
11683 
11684 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
11685 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
11686 #define MIPI_DATA_ADDRESS(port)		_MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
11687 #define  DATA_MEM_ADDRESS_SHIFT				5
11688 #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
11689 #define  DATA_VALID					(1 << 0)
11690 
11691 #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
11692 #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
11693 #define MIPI_DATA_LENGTH(port)		_MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
11694 #define  DATA_LENGTH_SHIFT				0
11695 #define  DATA_LENGTH_MASK				(0xfffff << 0)
11696 
11697 #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
11698 #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
11699 #define MIPI_COMMAND_ADDRESS(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
11700 #define  COMMAND_MEM_ADDRESS_SHIFT			5
11701 #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
11702 #define  AUTO_PWG_ENABLE				(1 << 2)
11703 #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
11704 #define  COMMAND_VALID					(1 << 0)
11705 
11706 #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
11707 #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
11708 #define MIPI_COMMAND_LENGTH(port)	_MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
11709 #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
11710 #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
11711 
11712 #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
11713 #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
11714 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
11715 
11716 #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
11717 #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
11718 #define MIPI_READ_DATA_VALID(port)	_MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
11719 #define  READ_DATA_VALID(n)				(1 << (n))
11720 
11721 /* MOCS (Memory Object Control State) registers */
11722 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
11723 
11724 #define __GEN9_RCS0_MOCS0	0xc800
11725 #define GEN9_GFX_MOCS(i)	_MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
11726 #define __GEN9_VCS0_MOCS0	0xc900
11727 #define GEN9_MFX0_MOCS(i)	_MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
11728 #define __GEN9_VCS1_MOCS0	0xca00
11729 #define GEN9_MFX1_MOCS(i)	_MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
11730 #define __GEN9_VECS0_MOCS0	0xcb00
11731 #define GEN9_VEBOX_MOCS(i)	_MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
11732 #define __GEN9_BCS0_MOCS0	0xcc00
11733 #define GEN9_BLT_MOCS(i)	_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
11734 #define __GEN11_VCS2_MOCS0	0x10000
11735 #define GEN11_MFX2_MOCS(i)	_MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
11736 
11737 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
11738 #define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
11739 #define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
11740 #define   PMFLUSHDONE_LNEBLK		(1 << 22)
11741 
11742 #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
11743 
11744 /* gamt regs */
11745 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
11746 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
11747 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
11748 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
11749 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
11750 
11751 #define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
11752 #define  MMCD_PCLA		(1 << 31)
11753 #define  MMCD_HOTSPOT_EN	(1 << 27)
11754 
11755 #define _ICL_PHY_MISC_A		0x64C00
11756 #define _ICL_PHY_MISC_B		0x64C04
11757 #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
11758 						 _ICL_PHY_MISC_B)
11759 #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
11760 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
11761 
11762 /* Icelake Display Stream Compression Registers */
11763 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
11764 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
11765 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
11766 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
11767 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
11768 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
11769 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11770 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
11771 							   _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
11772 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11773 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
11774 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
11775 #define  DSC_VBR_ENABLE			(1 << 19)
11776 #define  DSC_422_ENABLE			(1 << 18)
11777 #define  DSC_COLOR_SPACE_CONVERSION	(1 << 17)
11778 #define  DSC_BLOCK_PREDICTION		(1 << 16)
11779 #define  DSC_LINE_BUF_DEPTH_SHIFT	12
11780 #define  DSC_BPC_SHIFT			8
11781 #define  DSC_VER_MIN_SHIFT		4
11782 #define  DSC_VER_MAJ			(0x1 << 0)
11783 
11784 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
11785 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
11786 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
11787 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
11788 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
11789 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
11790 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11791 							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
11792 							   _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
11793 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11794 							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
11795 							   _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
11796 #define  DSC_BPP(bpp)				((bpp) << 0)
11797 
11798 #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
11799 #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
11800 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
11801 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
11802 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
11803 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
11804 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11805 							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
11806 							   _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
11807 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11808 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
11809 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
11810 #define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
11811 #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
11812 
11813 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
11814 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
11815 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
11816 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
11817 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
11818 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
11819 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11820 							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
11821 							   _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
11822 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11823 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
11824 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
11825 #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
11826 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
11827 
11828 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
11829 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
11830 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
11831 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
11832 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
11833 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
11834 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11835 							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
11836 							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
11837 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11838 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
11839 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
11840 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
11841 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
11842 
11843 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
11844 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
11845 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
11846 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
11847 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
11848 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
11849 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11850 							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
11851 							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
11852 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11853 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
11854 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
11855 #define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
11856 #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
11857 
11858 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
11859 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
11860 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
11861 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
11862 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
11863 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
11864 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11865 							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
11866 							   _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
11867 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11868 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
11869 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
11870 #define  DSC_FLATNESS_MAX_QP(max_qp)		((max_qp) << 24)
11871 #define  DSC_FLATNESS_MIN_QP(min_qp)		((min_qp) << 16)
11872 #define  DSC_FIRST_LINE_BPG_OFFSET(offset)	((offset) << 8)
11873 #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
11874 
11875 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
11876 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
11877 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
11878 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
11879 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
11880 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
11881 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11882 							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
11883 							    _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
11884 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11885 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
11886 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
11887 #define  DSC_NFL_BPG_OFFSET(bpg_offset)		((bpg_offset) << 16)
11888 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
11889 
11890 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
11891 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
11892 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
11893 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
11894 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
11895 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
11896 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11897 							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11898 							   _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11899 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11900 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11901 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11902 #define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
11903 #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
11904 
11905 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
11906 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
11907 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
11908 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
11909 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
11910 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
11911 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11912 							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11913 							   _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11914 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11915 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11916 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11917 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	((rc_edge_fact) << 16)
11918 #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
11919 
11920 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
11921 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
11922 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
11923 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
11924 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
11925 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
11926 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11927 							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11928 							   _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11929 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11930 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11931 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11932 #define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		((rc_tgt_off_low) << 20)
11933 #define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	((rc_tgt_off_high) << 16)
11934 #define  DSC_RC_QUANT_INC_LIMIT1(lim)			((lim) << 8)
11935 #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
11936 
11937 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
11938 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
11939 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
11940 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
11941 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
11942 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
11943 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11944 							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11945 							   _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11946 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11947 							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11948 							   _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11949 
11950 #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
11951 #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
11952 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
11953 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
11954 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
11955 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
11956 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11957 							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11958 							   _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11959 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11960 							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11961 							   _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11962 
11963 #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
11964 #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
11965 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
11966 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
11967 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
11968 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
11969 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11970 							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11971 							   _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11972 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11973 							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11974 							   _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11975 
11976 #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
11977 #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
11978 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
11979 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
11980 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
11981 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
11982 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11983 							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11984 							   _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11985 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11986 							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11987 							   _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11988 
11989 #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
11990 #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
11991 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
11992 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
11993 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
11994 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
11995 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11996 							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11997 							   _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11998 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
11999 							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
12000 							   _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
12001 
12002 #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
12003 #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
12004 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
12005 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
12006 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
12007 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
12008 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12009 							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
12010 							   _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
12011 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12012 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
12013 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
12014 #define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
12015 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
12016 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
12017 
12018 /* Icelake Rate Control Buffer Threshold Registers */
12019 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
12020 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
12021 #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
12022 #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
12023 #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
12024 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
12025 #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
12026 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
12027 #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
12028 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
12029 #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
12030 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
12031 #define ICL_DSC0_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12032 						_ICL_DSC0_RC_BUF_THRESH_0_PB, \
12033 						_ICL_DSC0_RC_BUF_THRESH_0_PC)
12034 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12035 						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
12036 						_ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
12037 #define ICL_DSC1_RC_BUF_THRESH_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12038 						_ICL_DSC1_RC_BUF_THRESH_0_PB, \
12039 						_ICL_DSC1_RC_BUF_THRESH_0_PC)
12040 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12041 						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
12042 						_ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
12043 
12044 #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
12045 #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
12046 #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
12047 #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
12048 #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
12049 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
12050 #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
12051 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
12052 #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
12053 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
12054 #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
12055 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
12056 #define ICL_DSC0_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12057 						_ICL_DSC0_RC_BUF_THRESH_1_PB, \
12058 						_ICL_DSC0_RC_BUF_THRESH_1_PC)
12059 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12060 						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
12061 						_ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
12062 #define ICL_DSC1_RC_BUF_THRESH_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
12063 						_ICL_DSC1_RC_BUF_THRESH_1_PB, \
12064 						_ICL_DSC1_RC_BUF_THRESH_1_PC)
12065 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
12066 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
12067 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
12068 
12069 #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
12070 #define   MODULAR_FIA_MASK			(1 << 4)
12071 #define   TC_LIVE_STATE_TBT(idx)		(1 << ((idx) * 8 + 6))
12072 #define   TC_LIVE_STATE_TC(idx)			(1 << ((idx) * 8 + 5))
12073 #define   DP_LANE_ASSIGNMENT_SHIFT(idx)		((idx) * 8)
12074 #define   DP_LANE_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 8))
12075 #define   DP_LANE_ASSIGNMENT(idx, x)		((x) << ((idx) * 8))
12076 
12077 #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
12078 #define   DP_PHY_MODE_STATUS_COMPLETED(idx)	(1 << (idx))
12079 
12080 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
12081 #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)	(1 << (idx))
12082 
12083 #define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
12084 #define   DP_PIN_ASSIGNMENT_SHIFT(idx)		((idx) * 4)
12085 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
12086 #define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
12087 
12088 /* This register controls the Display State Buffer (DSB) engines. */
12089 #define _DSBSL_INSTANCE_BASE		0x70B00
12090 #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
12091 					 (pipe) * 0x1000 + (id) * 0x100)
12092 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
12093 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
12094 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
12095 #define   DSB_ENABLE			(1 << 31)
12096 #define   DSB_STATUS			(1 << 0)
12097 
12098 #endif /* _I915_REG_H_ */
12099