1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include <linux/bitfield.h> 29 #include <linux/bits.h> 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 /** 120 * REG_BIT() - Prepare a u32 bit value 121 * @__n: 0-based bit number 122 * 123 * Local wrapper for BIT() to force u32, with compile time checks. 124 * 125 * @return: Value with bit @__n set. 126 */ 127 #define REG_BIT(__n) \ 128 ((u32)(BIT(__n) + \ 129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ 130 ((__n) < 0 || (__n) > 31)))) 131 132 /** 133 * REG_GENMASK() - Prepare a continuous u32 bitmask 134 * @__high: 0-based high bit 135 * @__low: 0-based low bit 136 * 137 * Local wrapper for GENMASK() to force u32, with compile time checks. 138 * 139 * @return: Continuous bitmask from @__high to @__low, inclusive. 140 */ 141 #define REG_GENMASK(__high, __low) \ 142 ((u32)(GENMASK(__high, __low) + \ 143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ 144 __is_constexpr(__low) && \ 145 ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) 146 147 /* 148 * Local integer constant expression version of is_power_of_2(). 149 */ 150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) 151 152 /** 153 * REG_FIELD_PREP() - Prepare a u32 bitfield value 154 * @__mask: shifted mask defining the field's length and position 155 * @__val: value to put in the field 156 * 157 * Local copy of FIELD_PREP() to generate an integer constant expression, force 158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). 159 * 160 * @return: @__val masked and shifted into the field defined by @__mask. 161 */ 162 #define REG_FIELD_PREP(__mask, __val) \ 163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ 166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 168 169 /** 170 * REG_FIELD_GET() - Extract a u32 bitfield value 171 * @__mask: shifted mask defining the field's length and position 172 * @__val: value to extract the bitfield value from 173 * 174 * Local wrapper for FIELD_GET() to force u32 and for consistency with 175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). 176 * 177 * @return: Masked and shifted value of the field defined by @__mask in @__val. 178 */ 179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) 180 181 typedef struct { 182 u32 reg; 183 } i915_reg_t; 184 185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 186 187 #define INVALID_MMIO_REG _MMIO(0) 188 189 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg) 190 { 191 return reg.reg; 192 } 193 194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 195 { 196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 197 } 198 199 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 200 { 201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 202 } 203 204 #define VLV_DISPLAY_BASE 0x180000 205 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 206 #define BXT_MIPI_BASE 0x60000 207 208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) 209 210 /* 211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 212 * numbers, pick the 0-based __index'th value. 213 * 214 * Always prefer this over _PICK() if the numbers are evenly spaced. 215 */ 216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 217 218 /* 219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 220 * 221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 222 */ 223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 224 225 /* 226 * Named helper wrappers around _PICK_EVEN() and _PICK(). 227 */ 228 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 229 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 230 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 231 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 232 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 233 234 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 235 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 236 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 237 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 238 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 239 240 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 241 242 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 243 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 244 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 245 #define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) 246 247 /* 248 * Device info offset array based helpers for groups of registers with unevenly 249 * spaced base offsets. 250 */ 251 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ 252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ 253 DISPLAY_MMIO_BASE(dev_priv)) 254 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ 255 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 256 DISPLAY_MMIO_BASE(dev_priv)) 257 #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) 258 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 259 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ 260 DISPLAY_MMIO_BASE(dev_priv)) 261 262 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 263 #define _MASKED_FIELD(mask, value) ({ \ 264 if (__builtin_constant_p(mask)) \ 265 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 266 if (__builtin_constant_p(value)) \ 267 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 268 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 269 BUILD_BUG_ON_MSG((value) & ~(mask), \ 270 "Incorrect value for mask"); \ 271 __MASKED_FIELD(mask, value); }) 272 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 273 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 274 275 /* PCI config space */ 276 277 #define MCHBAR_I915 0x44 278 #define MCHBAR_I965 0x48 279 #define MCHBAR_SIZE (4 * 4096) 280 281 #define DEVEN 0x54 282 #define DEVEN_MCHBAR_EN (1 << 28) 283 284 /* BSM in include/drm/i915_drm.h */ 285 286 #define HPLLCC 0xc0 /* 85x only */ 287 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 288 #define GC_CLOCK_133_200 (0 << 0) 289 #define GC_CLOCK_100_200 (1 << 0) 290 #define GC_CLOCK_100_133 (2 << 0) 291 #define GC_CLOCK_133_266 (3 << 0) 292 #define GC_CLOCK_133_200_2 (4 << 0) 293 #define GC_CLOCK_133_266_2 (5 << 0) 294 #define GC_CLOCK_166_266 (6 << 0) 295 #define GC_CLOCK_166_250 (7 << 0) 296 297 #define I915_GDRST 0xc0 /* PCI config register */ 298 #define GRDOM_FULL (0 << 2) 299 #define GRDOM_RENDER (1 << 2) 300 #define GRDOM_MEDIA (3 << 2) 301 #define GRDOM_MASK (3 << 2) 302 #define GRDOM_RESET_STATUS (1 << 1) 303 #define GRDOM_RESET_ENABLE (1 << 0) 304 305 /* BSpec only has register offset, PCI device and bit found empirically */ 306 #define I830_CLOCK_GATE 0xc8 /* device 0 */ 307 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 308 309 #define GCDGMBUS 0xcc 310 311 #define GCFGC2 0xda 312 #define GCFGC 0xf0 /* 915+ only */ 313 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 314 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 315 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 316 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 317 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 318 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 319 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 320 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 321 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 322 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 323 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 324 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 325 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 326 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 327 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 328 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 329 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 330 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 331 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 332 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 333 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 334 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 335 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 336 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 337 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 338 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 339 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 340 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 341 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 342 343 #define ASLE 0xe4 344 #define ASLS 0xfc 345 346 #define SWSCI 0xe8 347 #define SWSCI_SCISEL (1 << 15) 348 #define SWSCI_GSSCIE (1 << 0) 349 350 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 351 352 353 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 354 #define ILK_GRDOM_FULL (0 << 1) 355 #define ILK_GRDOM_RENDER (1 << 1) 356 #define ILK_GRDOM_MEDIA (3 << 1) 357 #define ILK_GRDOM_MASK (3 << 1) 358 #define ILK_GRDOM_RESET_ENABLE (1 << 0) 359 360 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 361 #define GEN6_MBC_SNPCR_SHIFT 21 362 #define GEN6_MBC_SNPCR_MASK (3 << 21) 363 #define GEN6_MBC_SNPCR_MAX (0 << 21) 364 #define GEN6_MBC_SNPCR_MED (1 << 21) 365 #define GEN6_MBC_SNPCR_LOW (2 << 21) 366 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ 367 368 #define VLV_G3DCTL _MMIO(0x9024) 369 #define VLV_GSCKGCTL _MMIO(0x9028) 370 371 #define GEN6_MBCTL _MMIO(0x0907c) 372 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 373 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 374 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 375 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 376 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 377 378 #define GEN6_GDRST _MMIO(0x941c) 379 #define GEN6_GRDOM_FULL (1 << 0) 380 #define GEN6_GRDOM_RENDER (1 << 1) 381 #define GEN6_GRDOM_MEDIA (1 << 2) 382 #define GEN6_GRDOM_BLT (1 << 3) 383 #define GEN6_GRDOM_VECS (1 << 4) 384 #define GEN9_GRDOM_GUC (1 << 5) 385 #define GEN8_GRDOM_MEDIA2 (1 << 7) 386 /* GEN11 changed all bit defs except for FULL & RENDER */ 387 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL 388 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER 389 #define GEN11_GRDOM_BLT (1 << 2) 390 #define GEN11_GRDOM_GUC (1 << 3) 391 #define GEN11_GRDOM_MEDIA (1 << 5) 392 #define GEN11_GRDOM_MEDIA2 (1 << 6) 393 #define GEN11_GRDOM_MEDIA3 (1 << 7) 394 #define GEN11_GRDOM_MEDIA4 (1 << 8) 395 #define GEN11_GRDOM_VECS (1 << 13) 396 #define GEN11_GRDOM_VECS2 (1 << 14) 397 #define GEN11_GRDOM_SFC0 (1 << 17) 398 #define GEN11_GRDOM_SFC1 (1 << 18) 399 400 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) 401 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) 402 403 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C) 404 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 405 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890) 406 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 407 #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 408 409 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C) 410 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 411 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018) 412 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 413 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) 414 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 415 416 #define GEN12_SFC_DONE(n) _MMIO(0x1cc00 + (n) * 0x100) 417 #define GEN12_SFC_DONE_MAX 4 418 419 #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 420 #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 421 #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 422 #define PP_DIR_DCLV_2G 0xffffffff 423 424 #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 425 #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 426 427 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 428 #define GEN8_RPCS_ENABLE (1 << 31) 429 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 430 #define GEN8_RPCS_S_CNT_SHIFT 15 431 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 432 #define GEN11_RPCS_S_CNT_SHIFT 12 433 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 434 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 435 #define GEN8_RPCS_SS_CNT_SHIFT 8 436 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 437 #define GEN8_RPCS_EU_MAX_SHIFT 4 438 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 439 #define GEN8_RPCS_EU_MIN_SHIFT 0 440 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 441 442 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) 443 /* HSW only */ 444 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 445 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 446 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 447 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 448 /* HSW+ */ 449 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 450 #define HSW_RCS_CONTEXT_ENABLE (1 << 7) 451 #define HSW_RCS_INHIBIT (1 << 8) 452 /* Gen8 */ 453 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 454 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 455 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 456 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 457 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 458 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 459 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 460 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 461 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 462 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 463 464 #define GAM_ECOCHK _MMIO(0x4090) 465 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) 466 #define ECOCHK_SNB_BIT (1 << 10) 467 #define ECOCHK_DIS_TLB (1 << 8) 468 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) 469 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) 470 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) 471 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) 472 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) 473 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) 474 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) 475 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) 476 477 #define GEN8_RC6_CTX_INFO _MMIO(0x8504) 478 479 #define GAC_ECO_BITS _MMIO(0x14090) 480 #define ECOBITS_SNB_BIT (1 << 13) 481 #define ECOBITS_PPGTT_CACHE64B (3 << 8) 482 #define ECOBITS_PPGTT_CACHE4B (0 << 8) 483 484 #define GAB_CTL _MMIO(0x24000) 485 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) 486 487 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 488 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 489 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 490 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 491 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 492 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 493 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 494 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 495 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 496 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 497 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 498 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 499 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 500 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 501 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 502 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 503 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 504 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 505 506 /* VGA stuff */ 507 508 #define VGA_ST01_MDA 0x3ba 509 #define VGA_ST01_CGA 0x3da 510 511 #define _VGA_MSR_WRITE _MMIO(0x3c2) 512 #define VGA_MSR_WRITE 0x3c2 513 #define VGA_MSR_READ 0x3cc 514 #define VGA_MSR_MEM_EN (1 << 1) 515 #define VGA_MSR_CGA_MODE (1 << 0) 516 517 #define VGA_SR_INDEX 0x3c4 518 #define SR01 1 519 #define VGA_SR_DATA 0x3c5 520 521 #define VGA_AR_INDEX 0x3c0 522 #define VGA_AR_VID_EN (1 << 5) 523 #define VGA_AR_DATA_WRITE 0x3c0 524 #define VGA_AR_DATA_READ 0x3c1 525 526 #define VGA_GR_INDEX 0x3ce 527 #define VGA_GR_DATA 0x3cf 528 /* GR05 */ 529 #define VGA_GR_MEM_READ_MODE_SHIFT 3 530 #define VGA_GR_MEM_READ_MODE_PLANE 1 531 /* GR06 */ 532 #define VGA_GR_MEM_MODE_MASK 0xc 533 #define VGA_GR_MEM_MODE_SHIFT 2 534 #define VGA_GR_MEM_A0000_AFFFF 0 535 #define VGA_GR_MEM_A0000_BFFFF 1 536 #define VGA_GR_MEM_B0000_B7FFF 2 537 #define VGA_GR_MEM_B0000_BFFFF 3 538 539 #define VGA_DACMASK 0x3c6 540 #define VGA_DACRX 0x3c7 541 #define VGA_DACWX 0x3c8 542 #define VGA_DACDATA 0x3c9 543 544 #define VGA_CR_INDEX_MDA 0x3b4 545 #define VGA_CR_DATA_MDA 0x3b5 546 #define VGA_CR_INDEX_CGA 0x3d4 547 #define VGA_CR_DATA_CGA 0x3d5 548 549 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 550 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 551 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 552 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 553 #define MI_PREDICATE_DATA _MMIO(0x2410) 554 #define MI_PREDICATE_RESULT _MMIO(0x2418) 555 #define MI_PREDICATE_RESULT_1 _MMIO(0x241c) 556 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 557 #define LOWER_SLICE_ENABLED (1 << 0) 558 #define LOWER_SLICE_DISABLED (0 << 0) 559 560 /* 561 * Registers used only by the command parser 562 */ 563 #define BCS_SWCTRL _MMIO(0x22200) 564 #define BCS_SRC_Y REG_BIT(0) 565 #define BCS_DST_Y REG_BIT(1) 566 567 /* There are 16 GPR registers */ 568 #define BCS_GPR(n) _MMIO(0x22600 + (n) * 8) 569 #define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4) 570 571 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 572 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 573 #define HS_INVOCATION_COUNT _MMIO(0x2300) 574 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 575 #define DS_INVOCATION_COUNT _MMIO(0x2308) 576 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 577 #define IA_VERTICES_COUNT _MMIO(0x2310) 578 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 579 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 580 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 581 #define VS_INVOCATION_COUNT _MMIO(0x2320) 582 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 583 #define GS_INVOCATION_COUNT _MMIO(0x2328) 584 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 585 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 586 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 587 #define CL_INVOCATION_COUNT _MMIO(0x2338) 588 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 589 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 590 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 591 #define PS_INVOCATION_COUNT _MMIO(0x2348) 592 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 593 #define PS_DEPTH_COUNT _MMIO(0x2350) 594 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 595 596 /* There are the 4 64-bit counter registers, one for each stream output */ 597 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 598 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 599 600 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 601 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 602 603 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 604 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 605 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 606 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 607 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 608 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 609 610 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 611 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 612 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 613 614 /* There are the 16 64-bit CS General Purpose Registers */ 615 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 616 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 617 618 #define GEN7_OACONTROL _MMIO(0x2360) 619 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 620 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 621 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 622 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) 623 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) 624 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) 625 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) 626 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) 627 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) 628 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) 629 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) 630 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) 631 #define GEN7_OACONTROL_FORMAT_SHIFT 2 632 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) 633 #define GEN7_OACONTROL_ENABLE (1 << 0) 634 635 #define GEN8_OACTXID _MMIO(0x2364) 636 637 #define GEN8_OA_DEBUG _MMIO(0x2B04) 638 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 639 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 640 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 641 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 642 643 #define GEN8_OACONTROL _MMIO(0x2B00) 644 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) 645 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) 646 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) 647 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) 648 #define GEN8_OA_REPORT_FORMAT_SHIFT 2 649 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) 650 #define GEN8_OA_COUNTER_ENABLE (1 << 0) 651 652 #define GEN8_OACTXCONTROL _MMIO(0x2360) 653 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 654 #define GEN8_OA_TIMER_PERIOD_SHIFT 2 655 #define GEN8_OA_TIMER_ENABLE (1 << 1) 656 #define GEN8_OA_COUNTER_RESUME (1 << 0) 657 658 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 659 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) 660 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) 661 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) 662 #define GEN7_OABUFFER_RESUME (1 << 0) 663 664 #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 665 #define GEN8_OABUFFER _MMIO(0x2b14) 666 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 667 668 #define GEN7_OASTATUS1 _MMIO(0x2364) 669 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 670 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) 671 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) 672 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) 673 674 #define GEN7_OASTATUS2 _MMIO(0x2368) 675 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 676 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 677 678 #define GEN8_OASTATUS _MMIO(0x2b08) 679 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) 680 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) 681 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) 682 #define GEN8_OASTATUS_REPORT_LOST (1 << 0) 683 684 #define GEN8_OAHEADPTR _MMIO(0x2B0C) 685 #define GEN8_OAHEADPTR_MASK 0xffffffc0 686 #define GEN8_OATAILPTR _MMIO(0x2B10) 687 #define GEN8_OATAILPTR_MASK 0xffffffc0 688 689 #define OABUFFER_SIZE_128K (0 << 3) 690 #define OABUFFER_SIZE_256K (1 << 3) 691 #define OABUFFER_SIZE_512K (2 << 3) 692 #define OABUFFER_SIZE_1M (3 << 3) 693 #define OABUFFER_SIZE_2M (4 << 3) 694 #define OABUFFER_SIZE_4M (5 << 3) 695 #define OABUFFER_SIZE_8M (6 << 3) 696 #define OABUFFER_SIZE_16M (7 << 3) 697 698 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) 699 700 /* Gen12 OAR unit */ 701 #define GEN12_OAR_OACONTROL _MMIO(0x2960) 702 #define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1 703 #define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0) 704 705 #define GEN12_OACTXCONTROL _MMIO(0x2360) 706 #define GEN12_OAR_OASTATUS _MMIO(0x2968) 707 708 /* Gen12 OAG unit */ 709 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00) 710 #define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0 711 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04) 712 #define GEN12_OAG_OATAILPTR_MASK 0xffffffc0 713 714 #define GEN12_OAG_OABUFFER _MMIO(0xdb08) 715 #define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7) 716 #define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3) 717 #define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */ 718 719 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28) 720 #define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2 721 #define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1) 722 #define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0) 723 724 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4) 725 #define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2 726 #define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0) 727 728 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8) 729 #define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 730 #define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 731 #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 732 #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 733 734 #define GEN12_OAG_OASTATUS _MMIO(0xdafc) 735 #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2) 736 #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1) 737 #define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) 738 739 /* 740 * Flexible, Aggregate EU Counter Registers. 741 * Note: these aren't contiguous 742 */ 743 #define EU_PERF_CNTL0 _MMIO(0xe458) 744 #define EU_PERF_CNTL1 _MMIO(0xe558) 745 #define EU_PERF_CNTL2 _MMIO(0xe658) 746 #define EU_PERF_CNTL3 _MMIO(0xe758) 747 #define EU_PERF_CNTL4 _MMIO(0xe45c) 748 #define EU_PERF_CNTL5 _MMIO(0xe55c) 749 #define EU_PERF_CNTL6 _MMIO(0xe65c) 750 751 /* 752 * OA Boolean state 753 */ 754 755 #define OASTARTTRIG1 _MMIO(0x2710) 756 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 757 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff 758 759 #define OASTARTTRIG2 _MMIO(0x2714) 760 #define OASTARTTRIG2_INVERT_A_0 (1 << 0) 761 #define OASTARTTRIG2_INVERT_A_1 (1 << 1) 762 #define OASTARTTRIG2_INVERT_A_2 (1 << 2) 763 #define OASTARTTRIG2_INVERT_A_3 (1 << 3) 764 #define OASTARTTRIG2_INVERT_A_4 (1 << 4) 765 #define OASTARTTRIG2_INVERT_A_5 (1 << 5) 766 #define OASTARTTRIG2_INVERT_A_6 (1 << 6) 767 #define OASTARTTRIG2_INVERT_A_7 (1 << 7) 768 #define OASTARTTRIG2_INVERT_A_8 (1 << 8) 769 #define OASTARTTRIG2_INVERT_A_9 (1 << 9) 770 #define OASTARTTRIG2_INVERT_A_10 (1 << 10) 771 #define OASTARTTRIG2_INVERT_A_11 (1 << 11) 772 #define OASTARTTRIG2_INVERT_A_12 (1 << 12) 773 #define OASTARTTRIG2_INVERT_A_13 (1 << 13) 774 #define OASTARTTRIG2_INVERT_A_14 (1 << 14) 775 #define OASTARTTRIG2_INVERT_A_15 (1 << 15) 776 #define OASTARTTRIG2_INVERT_B_0 (1 << 16) 777 #define OASTARTTRIG2_INVERT_B_1 (1 << 17) 778 #define OASTARTTRIG2_INVERT_B_2 (1 << 18) 779 #define OASTARTTRIG2_INVERT_B_3 (1 << 19) 780 #define OASTARTTRIG2_INVERT_C_0 (1 << 20) 781 #define OASTARTTRIG2_INVERT_C_1 (1 << 21) 782 #define OASTARTTRIG2_INVERT_D_0 (1 << 22) 783 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) 784 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) 785 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) 786 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) 787 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) 788 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) 789 790 #define OASTARTTRIG3 _MMIO(0x2718) 791 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf 792 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 793 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 794 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 795 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 796 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 797 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 798 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 799 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 800 801 #define OASTARTTRIG4 _MMIO(0x271c) 802 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf 803 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 804 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 805 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 806 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 807 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 808 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 809 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 810 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 811 812 #define OASTARTTRIG5 _MMIO(0x2720) 813 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 814 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff 815 816 #define OASTARTTRIG6 _MMIO(0x2724) 817 #define OASTARTTRIG6_INVERT_A_0 (1 << 0) 818 #define OASTARTTRIG6_INVERT_A_1 (1 << 1) 819 #define OASTARTTRIG6_INVERT_A_2 (1 << 2) 820 #define OASTARTTRIG6_INVERT_A_3 (1 << 3) 821 #define OASTARTTRIG6_INVERT_A_4 (1 << 4) 822 #define OASTARTTRIG6_INVERT_A_5 (1 << 5) 823 #define OASTARTTRIG6_INVERT_A_6 (1 << 6) 824 #define OASTARTTRIG6_INVERT_A_7 (1 << 7) 825 #define OASTARTTRIG6_INVERT_A_8 (1 << 8) 826 #define OASTARTTRIG6_INVERT_A_9 (1 << 9) 827 #define OASTARTTRIG6_INVERT_A_10 (1 << 10) 828 #define OASTARTTRIG6_INVERT_A_11 (1 << 11) 829 #define OASTARTTRIG6_INVERT_A_12 (1 << 12) 830 #define OASTARTTRIG6_INVERT_A_13 (1 << 13) 831 #define OASTARTTRIG6_INVERT_A_14 (1 << 14) 832 #define OASTARTTRIG6_INVERT_A_15 (1 << 15) 833 #define OASTARTTRIG6_INVERT_B_0 (1 << 16) 834 #define OASTARTTRIG6_INVERT_B_1 (1 << 17) 835 #define OASTARTTRIG6_INVERT_B_2 (1 << 18) 836 #define OASTARTTRIG6_INVERT_B_3 (1 << 19) 837 #define OASTARTTRIG6_INVERT_C_0 (1 << 20) 838 #define OASTARTTRIG6_INVERT_C_1 (1 << 21) 839 #define OASTARTTRIG6_INVERT_D_0 (1 << 22) 840 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) 841 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) 842 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) 843 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) 844 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) 845 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) 846 847 #define OASTARTTRIG7 _MMIO(0x2728) 848 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf 849 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 850 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 851 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 852 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 853 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 854 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 855 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 856 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 857 858 #define OASTARTTRIG8 _MMIO(0x272c) 859 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf 860 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 861 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 862 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 863 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 864 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 865 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 866 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 867 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 868 869 #define OAREPORTTRIG1 _MMIO(0x2740) 870 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff 871 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */ 872 873 #define OAREPORTTRIG2 _MMIO(0x2744) 874 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0) 875 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1) 876 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2) 877 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3) 878 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4) 879 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5) 880 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6) 881 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7) 882 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8) 883 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9) 884 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10) 885 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11) 886 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12) 887 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13) 888 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14) 889 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15) 890 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16) 891 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17) 892 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18) 893 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19) 894 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20) 895 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21) 896 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22) 897 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) 898 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) 899 900 #define OAREPORTTRIG3 _MMIO(0x2748) 901 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf 902 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 903 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 904 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 905 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 906 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 907 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 908 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 909 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 910 911 #define OAREPORTTRIG4 _MMIO(0x274c) 912 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf 913 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 914 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 915 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 916 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 917 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 918 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 919 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 920 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 921 922 #define OAREPORTTRIG5 _MMIO(0x2750) 923 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff 924 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */ 925 926 #define OAREPORTTRIG6 _MMIO(0x2754) 927 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0) 928 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1) 929 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2) 930 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3) 931 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4) 932 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5) 933 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6) 934 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7) 935 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8) 936 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9) 937 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10) 938 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11) 939 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12) 940 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13) 941 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14) 942 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15) 943 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16) 944 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17) 945 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18) 946 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19) 947 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20) 948 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21) 949 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22) 950 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) 951 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) 952 953 #define OAREPORTTRIG7 _MMIO(0x2758) 954 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf 955 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 956 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 957 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 958 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 959 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 960 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 961 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 962 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 963 964 #define OAREPORTTRIG8 _MMIO(0x275c) 965 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf 966 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 967 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 968 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 969 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 970 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 971 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 972 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 973 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 974 975 /* Same layout as OASTARTTRIGX */ 976 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900) 977 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904) 978 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908) 979 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c) 980 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910) 981 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914) 982 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918) 983 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c) 984 985 /* Same layout as OAREPORTTRIGX */ 986 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920) 987 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924) 988 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928) 989 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c) 990 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930) 991 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934) 992 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938) 993 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c) 994 995 /* CECX_0 */ 996 #define OACEC_COMPARE_LESS_OR_EQUAL 6 997 #define OACEC_COMPARE_NOT_EQUAL 5 998 #define OACEC_COMPARE_LESS_THAN 4 999 #define OACEC_COMPARE_GREATER_OR_EQUAL 3 1000 #define OACEC_COMPARE_EQUAL 2 1001 #define OACEC_COMPARE_GREATER_THAN 1 1002 #define OACEC_COMPARE_ANY_EQUAL 0 1003 1004 #define OACEC_COMPARE_VALUE_MASK 0xffff 1005 #define OACEC_COMPARE_VALUE_SHIFT 3 1006 1007 #define OACEC_SELECT_NOA (0 << 19) 1008 #define OACEC_SELECT_PREV (1 << 19) 1009 #define OACEC_SELECT_BOOLEAN (2 << 19) 1010 1011 /* 11-bit array 0: pass-through, 1: negated */ 1012 #define GEN12_OASCEC_NEGATE_MASK 0x7ff 1013 #define GEN12_OASCEC_NEGATE_SHIFT 21 1014 1015 /* CECX_1 */ 1016 #define OACEC_MASK_MASK 0xffff 1017 #define OACEC_CONSIDERATIONS_MASK 0xffff 1018 #define OACEC_CONSIDERATIONS_SHIFT 16 1019 1020 #define OACEC0_0 _MMIO(0x2770) 1021 #define OACEC0_1 _MMIO(0x2774) 1022 #define OACEC1_0 _MMIO(0x2778) 1023 #define OACEC1_1 _MMIO(0x277c) 1024 #define OACEC2_0 _MMIO(0x2780) 1025 #define OACEC2_1 _MMIO(0x2784) 1026 #define OACEC3_0 _MMIO(0x2788) 1027 #define OACEC3_1 _MMIO(0x278c) 1028 #define OACEC4_0 _MMIO(0x2790) 1029 #define OACEC4_1 _MMIO(0x2794) 1030 #define OACEC5_0 _MMIO(0x2798) 1031 #define OACEC5_1 _MMIO(0x279c) 1032 #define OACEC6_0 _MMIO(0x27a0) 1033 #define OACEC6_1 _MMIO(0x27a4) 1034 #define OACEC7_0 _MMIO(0x27a8) 1035 #define OACEC7_1 _MMIO(0x27ac) 1036 1037 /* Same layout as CECX_Y */ 1038 #define GEN12_OAG_CEC0_0 _MMIO(0xd940) 1039 #define GEN12_OAG_CEC0_1 _MMIO(0xd944) 1040 #define GEN12_OAG_CEC1_0 _MMIO(0xd948) 1041 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c) 1042 #define GEN12_OAG_CEC2_0 _MMIO(0xd950) 1043 #define GEN12_OAG_CEC2_1 _MMIO(0xd954) 1044 #define GEN12_OAG_CEC3_0 _MMIO(0xd958) 1045 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c) 1046 #define GEN12_OAG_CEC4_0 _MMIO(0xd960) 1047 #define GEN12_OAG_CEC4_1 _MMIO(0xd964) 1048 #define GEN12_OAG_CEC5_0 _MMIO(0xd968) 1049 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c) 1050 #define GEN12_OAG_CEC6_0 _MMIO(0xd970) 1051 #define GEN12_OAG_CEC6_1 _MMIO(0xd974) 1052 #define GEN12_OAG_CEC7_0 _MMIO(0xd978) 1053 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c) 1054 1055 /* Same layout as CECX_Y + negate 11-bit array */ 1056 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00) 1057 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04) 1058 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08) 1059 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c) 1060 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10) 1061 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14) 1062 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18) 1063 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c) 1064 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20) 1065 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24) 1066 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28) 1067 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c) 1068 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30) 1069 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34) 1070 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38) 1071 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c) 1072 1073 /* OA perf counters */ 1074 #define OA_PERFCNT1_LO _MMIO(0x91B8) 1075 #define OA_PERFCNT1_HI _MMIO(0x91BC) 1076 #define OA_PERFCNT2_LO _MMIO(0x91C0) 1077 #define OA_PERFCNT2_HI _MMIO(0x91C4) 1078 #define OA_PERFCNT3_LO _MMIO(0x91C8) 1079 #define OA_PERFCNT3_HI _MMIO(0x91CC) 1080 #define OA_PERFCNT4_LO _MMIO(0x91D8) 1081 #define OA_PERFCNT4_HI _MMIO(0x91DC) 1082 1083 #define OA_PERFMATRIX_LO _MMIO(0x91C8) 1084 #define OA_PERFMATRIX_HI _MMIO(0x91CC) 1085 1086 /* RPM unit config (Gen8+) */ 1087 #define RPM_CONFIG0 _MMIO(0x0D00) 1088 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 1089 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 1090 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 1091 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 1092 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 1093 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 1094 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 1095 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 1096 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 1097 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 1098 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 1099 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 1100 1101 #define RPM_CONFIG1 _MMIO(0x0D04) 1102 #define GEN10_GT_NOA_ENABLE (1 << 9) 1103 1104 /* GPM unit config (Gen9+) */ 1105 #define CTC_MODE _MMIO(0xA26C) 1106 #define CTC_SOURCE_PARAMETER_MASK 1 1107 #define CTC_SOURCE_CRYSTAL_CLOCK 0 1108 #define CTC_SOURCE_DIVIDE_LOGIC 1 1109 #define CTC_SHIFT_PARAMETER_SHIFT 1 1110 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 1111 1112 /* RCP unit config (Gen8+) */ 1113 #define RCP_CONFIG _MMIO(0x0D08) 1114 1115 /* NOA (HSW) */ 1116 #define HSW_MBVID2_NOA0 _MMIO(0x9E80) 1117 #define HSW_MBVID2_NOA1 _MMIO(0x9E84) 1118 #define HSW_MBVID2_NOA2 _MMIO(0x9E88) 1119 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C) 1120 #define HSW_MBVID2_NOA4 _MMIO(0x9E90) 1121 #define HSW_MBVID2_NOA5 _MMIO(0x9E94) 1122 #define HSW_MBVID2_NOA6 _MMIO(0x9E98) 1123 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C) 1124 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0) 1125 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4) 1126 1127 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) 1128 1129 /* NOA (Gen8+) */ 1130 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) 1131 1132 #define MICRO_BP0_0 _MMIO(0x9800) 1133 #define MICRO_BP0_2 _MMIO(0x9804) 1134 #define MICRO_BP0_1 _MMIO(0x9808) 1135 1136 #define MICRO_BP1_0 _MMIO(0x980C) 1137 #define MICRO_BP1_2 _MMIO(0x9810) 1138 #define MICRO_BP1_1 _MMIO(0x9814) 1139 1140 #define MICRO_BP2_0 _MMIO(0x9818) 1141 #define MICRO_BP2_2 _MMIO(0x981C) 1142 #define MICRO_BP2_1 _MMIO(0x9820) 1143 1144 #define MICRO_BP3_0 _MMIO(0x9824) 1145 #define MICRO_BP3_2 _MMIO(0x9828) 1146 #define MICRO_BP3_1 _MMIO(0x982C) 1147 1148 #define MICRO_BP_TRIGGER _MMIO(0x9830) 1149 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 1150 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 1151 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) 1152 1153 #define GEN12_OAA_DBG_REG _MMIO(0xdc44) 1154 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c) 1155 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40) 1156 1157 #define GDT_CHICKEN_BITS _MMIO(0x9840) 1158 #define GT_NOA_ENABLE 0x00000080 1159 1160 #define NOA_DATA _MMIO(0x986C) 1161 #define NOA_WRITE _MMIO(0x9888) 1162 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) 1163 1164 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 1165 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 1166 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 1167 1168 /* 1169 * Reset registers 1170 */ 1171 #define DEBUG_RESET_I830 _MMIO(0x6070) 1172 #define DEBUG_RESET_FULL (1 << 7) 1173 #define DEBUG_RESET_RENDER (1 << 8) 1174 #define DEBUG_RESET_DISPLAY (1 << 9) 1175 1176 /* 1177 * IOSF sideband 1178 */ 1179 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 1180 #define IOSF_DEVFN_SHIFT 24 1181 #define IOSF_OPCODE_SHIFT 16 1182 #define IOSF_PORT_SHIFT 8 1183 #define IOSF_BYTE_ENABLES_SHIFT 4 1184 #define IOSF_BAR_SHIFT 1 1185 #define IOSF_SB_BUSY (1 << 0) 1186 #define IOSF_PORT_BUNIT 0x03 1187 #define IOSF_PORT_PUNIT 0x04 1188 #define IOSF_PORT_NC 0x11 1189 #define IOSF_PORT_DPIO 0x12 1190 #define IOSF_PORT_GPIO_NC 0x13 1191 #define IOSF_PORT_CCK 0x14 1192 #define IOSF_PORT_DPIO_2 0x1a 1193 #define IOSF_PORT_FLISDSI 0x1b 1194 #define IOSF_PORT_GPIO_SC 0x48 1195 #define IOSF_PORT_GPIO_SUS 0xa8 1196 #define IOSF_PORT_CCU 0xa9 1197 #define CHV_IOSF_PORT_GPIO_N 0x13 1198 #define CHV_IOSF_PORT_GPIO_SE 0x48 1199 #define CHV_IOSF_PORT_GPIO_E 0xa8 1200 #define CHV_IOSF_PORT_GPIO_SW 0xb2 1201 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 1202 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 1203 1204 /* See configdb bunit SB addr map */ 1205 #define BUNIT_REG_BISOC 0x11 1206 1207 /* PUNIT_REG_*SSPM0 */ 1208 #define _SSPM0_SSC(val) ((val) << 0) 1209 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 1210 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 1211 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 1212 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 1213 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 1214 #define _SSPM0_SSS(val) ((val) << 24) 1215 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 1216 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 1217 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 1218 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 1219 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 1220 1221 /* PUNIT_REG_*SSPM1 */ 1222 #define SSPM1_FREQSTAT_SHIFT 24 1223 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 1224 #define SSPM1_FREQGUAR_SHIFT 8 1225 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 1226 #define SSPM1_FREQ_SHIFT 0 1227 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 1228 1229 #define PUNIT_REG_VEDSSPM0 0x32 1230 #define PUNIT_REG_VEDSSPM1 0x33 1231 1232 #define PUNIT_REG_DSPSSPM 0x36 1233 #define DSPFREQSTAT_SHIFT_CHV 24 1234 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 1235 #define DSPFREQGUAR_SHIFT_CHV 8 1236 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 1237 #define DSPFREQSTAT_SHIFT 30 1238 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 1239 #define DSPFREQGUAR_SHIFT 14 1240 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 1241 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 1242 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 1243 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 1244 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 1245 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 1246 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 1247 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 1248 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 1249 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 1250 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 1251 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 1252 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 1253 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 1254 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 1255 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 1256 1257 #define PUNIT_REG_ISPSSPM0 0x39 1258 #define PUNIT_REG_ISPSSPM1 0x3a 1259 1260 #define PUNIT_REG_PWRGT_CTRL 0x60 1261 #define PUNIT_REG_PWRGT_STATUS 0x61 1262 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 1263 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 1264 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 1265 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 1266 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 1267 1268 #define PUNIT_PWGT_IDX_RENDER 0 1269 #define PUNIT_PWGT_IDX_MEDIA 1 1270 #define PUNIT_PWGT_IDX_DISP2D 3 1271 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 1272 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 1273 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 1274 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 1275 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 1276 #define PUNIT_PWGT_IDX_DPIO_RX0 10 1277 #define PUNIT_PWGT_IDX_DPIO_RX1 11 1278 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12 1279 1280 #define PUNIT_REG_GPU_LFM 0xd3 1281 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 1282 #define PUNIT_REG_GPU_FREQ_STS 0xd8 1283 #define GPLLENABLE (1 << 4) 1284 #define GENFREQSTATUS (1 << 0) 1285 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 1286 #define PUNIT_REG_CZ_TIMESTAMP 0xce 1287 1288 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 1289 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 1290 1291 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 1292 #define FB_GFX_FREQ_FUSE_MASK 0xff 1293 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 1294 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 1295 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 1296 1297 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 1298 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 1299 1300 #define PUNIT_REG_DDR_SETUP2 0x139 1301 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 1302 #define FORCE_DDR_LOW_FREQ (1 << 1) 1303 #define FORCE_DDR_HIGH_FREQ (1 << 0) 1304 1305 #define PUNIT_GPU_STATUS_REG 0xdb 1306 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 1307 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 1308 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 1309 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 1310 1311 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 1312 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 1313 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 1314 1315 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 1316 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 1317 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 1318 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 1319 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 1320 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 1321 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 1322 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 1323 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 1324 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 1325 1326 #define VLV_TURBO_SOC_OVERRIDE 0x04 1327 #define VLV_OVERRIDE_EN 1 1328 #define VLV_SOC_TDP_EN (1 << 1) 1329 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 1330 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 1331 1332 /* vlv2 north clock has */ 1333 #define CCK_FUSE_REG 0x8 1334 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 1335 #define CCK_REG_DSI_PLL_FUSE 0x44 1336 #define CCK_REG_DSI_PLL_CONTROL 0x48 1337 #define DSI_PLL_VCO_EN (1 << 31) 1338 #define DSI_PLL_LDO_GATE (1 << 30) 1339 #define DSI_PLL_P1_POST_DIV_SHIFT 17 1340 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 1341 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 1342 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 1343 #define DSI_PLL_MUX_MASK (3 << 9) 1344 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 1345 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 1346 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 1347 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 1348 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 1349 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 1350 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 1351 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 1352 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 1353 #define DSI_PLL_LOCK (1 << 0) 1354 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 1355 #define DSI_PLL_LFSR (1 << 31) 1356 #define DSI_PLL_FRACTION_EN (1 << 30) 1357 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 1358 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 1359 #define DSI_PLL_USYNC_CNT_SHIFT 18 1360 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 1361 #define DSI_PLL_N1_DIV_SHIFT 16 1362 #define DSI_PLL_N1_DIV_MASK (3 << 16) 1363 #define DSI_PLL_M1_DIV_SHIFT 0 1364 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 1365 #define CCK_CZ_CLOCK_CONTROL 0x62 1366 #define CCK_GPLL_CLOCK_CONTROL 0x67 1367 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 1368 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 1369 #define CCK_TRUNK_FORCE_ON (1 << 17) 1370 #define CCK_TRUNK_FORCE_OFF (1 << 16) 1371 #define CCK_FREQUENCY_STATUS (0x1f << 8) 1372 #define CCK_FREQUENCY_STATUS_SHIFT 8 1373 #define CCK_FREQUENCY_VALUES (0x1f << 0) 1374 1375 /* DPIO registers */ 1376 #define DPIO_DEVFN 0 1377 1378 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 1379 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 1380 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 1381 #define DPIO_SFR_BYPASS (1 << 1) 1382 #define DPIO_CMNRST (1 << 0) 1383 1384 #define DPIO_PHY(pipe) ((pipe) >> 1) 1385 1386 /* 1387 * Per pipe/PLL DPIO regs 1388 */ 1389 #define _VLV_PLL_DW3_CH0 0x800c 1390 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 1391 #define DPIO_POST_DIV_DAC 0 1392 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 1393 #define DPIO_POST_DIV_LVDS1 2 1394 #define DPIO_POST_DIV_LVDS2 3 1395 #define DPIO_K_SHIFT (24) /* 4 bits */ 1396 #define DPIO_P1_SHIFT (21) /* 3 bits */ 1397 #define DPIO_P2_SHIFT (16) /* 5 bits */ 1398 #define DPIO_N_SHIFT (12) /* 4 bits */ 1399 #define DPIO_ENABLE_CALIBRATION (1 << 11) 1400 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 1401 #define DPIO_M2DIV_MASK 0xff 1402 #define _VLV_PLL_DW3_CH1 0x802c 1403 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 1404 1405 #define _VLV_PLL_DW5_CH0 0x8014 1406 #define DPIO_REFSEL_OVERRIDE 27 1407 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 1408 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 1409 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 1410 #define DPIO_PLL_REFCLK_SEL_MASK 3 1411 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 1412 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 1413 #define _VLV_PLL_DW5_CH1 0x8034 1414 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 1415 1416 #define _VLV_PLL_DW7_CH0 0x801c 1417 #define _VLV_PLL_DW7_CH1 0x803c 1418 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 1419 1420 #define _VLV_PLL_DW8_CH0 0x8040 1421 #define _VLV_PLL_DW8_CH1 0x8060 1422 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 1423 1424 #define VLV_PLL_DW9_BCAST 0xc044 1425 #define _VLV_PLL_DW9_CH0 0x8044 1426 #define _VLV_PLL_DW9_CH1 0x8064 1427 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 1428 1429 #define _VLV_PLL_DW10_CH0 0x8048 1430 #define _VLV_PLL_DW10_CH1 0x8068 1431 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 1432 1433 #define _VLV_PLL_DW11_CH0 0x804c 1434 #define _VLV_PLL_DW11_CH1 0x806c 1435 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 1436 1437 /* Spec for ref block start counts at DW10 */ 1438 #define VLV_REF_DW13 0x80ac 1439 1440 #define VLV_CMN_DW0 0x8100 1441 1442 /* 1443 * Per DDI channel DPIO regs 1444 */ 1445 1446 #define _VLV_PCS_DW0_CH0 0x8200 1447 #define _VLV_PCS_DW0_CH1 0x8400 1448 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 1449 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 1450 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 1451 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 1452 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1453 1454 #define _VLV_PCS01_DW0_CH0 0x200 1455 #define _VLV_PCS23_DW0_CH0 0x400 1456 #define _VLV_PCS01_DW0_CH1 0x2600 1457 #define _VLV_PCS23_DW0_CH1 0x2800 1458 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1459 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1460 1461 #define _VLV_PCS_DW1_CH0 0x8204 1462 #define _VLV_PCS_DW1_CH1 0x8404 1463 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 1464 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 1465 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 1466 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1467 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 1468 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1469 1470 #define _VLV_PCS01_DW1_CH0 0x204 1471 #define _VLV_PCS23_DW1_CH0 0x404 1472 #define _VLV_PCS01_DW1_CH1 0x2604 1473 #define _VLV_PCS23_DW1_CH1 0x2804 1474 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1475 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1476 1477 #define _VLV_PCS_DW8_CH0 0x8220 1478 #define _VLV_PCS_DW8_CH1 0x8420 1479 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1480 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1481 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1482 1483 #define _VLV_PCS01_DW8_CH0 0x0220 1484 #define _VLV_PCS23_DW8_CH0 0x0420 1485 #define _VLV_PCS01_DW8_CH1 0x2620 1486 #define _VLV_PCS23_DW8_CH1 0x2820 1487 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1488 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1489 1490 #define _VLV_PCS_DW9_CH0 0x8224 1491 #define _VLV_PCS_DW9_CH1 0x8424 1492 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 1493 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 1494 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 1495 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 1496 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 1497 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 1498 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1499 1500 #define _VLV_PCS01_DW9_CH0 0x224 1501 #define _VLV_PCS23_DW9_CH0 0x424 1502 #define _VLV_PCS01_DW9_CH1 0x2624 1503 #define _VLV_PCS23_DW9_CH1 0x2824 1504 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1505 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1506 1507 #define _CHV_PCS_DW10_CH0 0x8228 1508 #define _CHV_PCS_DW10_CH1 0x8428 1509 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 1510 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 1511 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 1512 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 1513 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 1514 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 1515 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 1516 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 1517 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1518 1519 #define _VLV_PCS01_DW10_CH0 0x0228 1520 #define _VLV_PCS23_DW10_CH0 0x0428 1521 #define _VLV_PCS01_DW10_CH1 0x2628 1522 #define _VLV_PCS23_DW10_CH1 0x2828 1523 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1524 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1525 1526 #define _VLV_PCS_DW11_CH0 0x822c 1527 #define _VLV_PCS_DW11_CH1 0x842c 1528 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 1529 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 1530 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 1531 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 1532 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1533 1534 #define _VLV_PCS01_DW11_CH0 0x022c 1535 #define _VLV_PCS23_DW11_CH0 0x042c 1536 #define _VLV_PCS01_DW11_CH1 0x262c 1537 #define _VLV_PCS23_DW11_CH1 0x282c 1538 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1539 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1540 1541 #define _VLV_PCS01_DW12_CH0 0x0230 1542 #define _VLV_PCS23_DW12_CH0 0x0430 1543 #define _VLV_PCS01_DW12_CH1 0x2630 1544 #define _VLV_PCS23_DW12_CH1 0x2830 1545 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1546 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1547 1548 #define _VLV_PCS_DW12_CH0 0x8230 1549 #define _VLV_PCS_DW12_CH1 0x8430 1550 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 1551 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 1552 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 1553 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 1554 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 1555 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1556 1557 #define _VLV_PCS_DW14_CH0 0x8238 1558 #define _VLV_PCS_DW14_CH1 0x8438 1559 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1560 1561 #define _VLV_PCS_DW23_CH0 0x825c 1562 #define _VLV_PCS_DW23_CH1 0x845c 1563 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1564 1565 #define _VLV_TX_DW2_CH0 0x8288 1566 #define _VLV_TX_DW2_CH1 0x8488 1567 #define DPIO_SWING_MARGIN000_SHIFT 16 1568 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1569 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1570 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1571 1572 #define _VLV_TX_DW3_CH0 0x828c 1573 #define _VLV_TX_DW3_CH1 0x848c 1574 /* The following bit for CHV phy */ 1575 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 1576 #define DPIO_SWING_MARGIN101_SHIFT 16 1577 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1578 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1579 1580 #define _VLV_TX_DW4_CH0 0x8290 1581 #define _VLV_TX_DW4_CH1 0x8490 1582 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1583 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1584 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1585 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1586 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1587 1588 #define _VLV_TX3_DW4_CH0 0x690 1589 #define _VLV_TX3_DW4_CH1 0x2a90 1590 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1591 1592 #define _VLV_TX_DW5_CH0 0x8294 1593 #define _VLV_TX_DW5_CH1 0x8494 1594 #define DPIO_TX_OCALINIT_EN (1 << 31) 1595 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1596 1597 #define _VLV_TX_DW11_CH0 0x82ac 1598 #define _VLV_TX_DW11_CH1 0x84ac 1599 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1600 1601 #define _VLV_TX_DW14_CH0 0x82b8 1602 #define _VLV_TX_DW14_CH1 0x84b8 1603 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1604 1605 /* CHV dpPhy registers */ 1606 #define _CHV_PLL_DW0_CH0 0x8000 1607 #define _CHV_PLL_DW0_CH1 0x8180 1608 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1609 1610 #define _CHV_PLL_DW1_CH0 0x8004 1611 #define _CHV_PLL_DW1_CH1 0x8184 1612 #define DPIO_CHV_N_DIV_SHIFT 8 1613 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1614 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1615 1616 #define _CHV_PLL_DW2_CH0 0x8008 1617 #define _CHV_PLL_DW2_CH1 0x8188 1618 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1619 1620 #define _CHV_PLL_DW3_CH0 0x800c 1621 #define _CHV_PLL_DW3_CH1 0x818c 1622 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1623 #define DPIO_CHV_FIRST_MOD (0 << 8) 1624 #define DPIO_CHV_SECOND_MOD (1 << 8) 1625 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1626 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1627 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1628 1629 #define _CHV_PLL_DW6_CH0 0x8018 1630 #define _CHV_PLL_DW6_CH1 0x8198 1631 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1632 #define DPIO_CHV_INT_COEFF_SHIFT 8 1633 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1634 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1635 1636 #define _CHV_PLL_DW8_CH0 0x8020 1637 #define _CHV_PLL_DW8_CH1 0x81A0 1638 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1639 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1640 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1641 1642 #define _CHV_PLL_DW9_CH0 0x8024 1643 #define _CHV_PLL_DW9_CH1 0x81A4 1644 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1645 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1646 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1647 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1648 1649 #define _CHV_CMN_DW0_CH0 0x8100 1650 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1651 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1652 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1653 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1654 1655 #define _CHV_CMN_DW5_CH0 0x8114 1656 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1657 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1658 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1659 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1660 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1661 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1662 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1663 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1664 1665 #define _CHV_CMN_DW13_CH0 0x8134 1666 #define _CHV_CMN_DW0_CH1 0x8080 1667 #define DPIO_CHV_S1_DIV_SHIFT 21 1668 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1669 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1670 #define DPIO_CHV_K_DIV_SHIFT 4 1671 #define DPIO_PLL_FREQLOCK (1 << 1) 1672 #define DPIO_PLL_LOCK (1 << 0) 1673 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1674 1675 #define _CHV_CMN_DW14_CH0 0x8138 1676 #define _CHV_CMN_DW1_CH1 0x8084 1677 #define DPIO_AFC_RECAL (1 << 14) 1678 #define DPIO_DCLKP_EN (1 << 13) 1679 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1680 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1681 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1682 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1683 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1684 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1685 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1686 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1687 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1688 1689 #define _CHV_CMN_DW19_CH0 0x814c 1690 #define _CHV_CMN_DW6_CH1 0x8098 1691 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1692 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1693 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1694 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1695 1696 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1697 1698 #define CHV_CMN_DW28 0x8170 1699 #define DPIO_CL1POWERDOWNEN (1 << 23) 1700 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1701 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1702 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1703 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1704 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1705 1706 #define CHV_CMN_DW30 0x8178 1707 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1708 #define DPIO_LRC_BYPASS (1 << 3) 1709 1710 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1711 (lane) * 0x200 + (offset)) 1712 1713 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1714 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1715 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1716 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1717 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1718 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1719 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1720 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1721 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1722 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1723 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1724 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1725 #define DPIO_FRC_LATENCY_SHFIT 8 1726 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1727 #define DPIO_UPAR_SHIFT 30 1728 1729 /* BXT PHY registers */ 1730 #define _BXT_PHY0_BASE 0x6C000 1731 #define _BXT_PHY1_BASE 0x162000 1732 #define _BXT_PHY2_BASE 0x163000 1733 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 1734 _BXT_PHY1_BASE, \ 1735 _BXT_PHY2_BASE) 1736 1737 #define _BXT_PHY(phy, reg) \ 1738 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 1739 1740 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1741 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 1742 (reg_ch1) - _BXT_PHY0_BASE)) 1743 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1744 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 1745 1746 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1747 #define MIPIO_RST_CTRL (1 << 2) 1748 1749 #define _BXT_PHY_CTL_DDI_A 0x64C00 1750 #define _BXT_PHY_CTL_DDI_B 0x64C10 1751 #define _BXT_PHY_CTL_DDI_C 0x64C20 1752 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1753 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1754 #define BXT_PHY_LANE_ENABLED (1 << 8) 1755 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1756 _BXT_PHY_CTL_DDI_B) 1757 1758 #define _PHY_CTL_FAMILY_EDP 0x64C80 1759 #define _PHY_CTL_FAMILY_DDI 0x64C90 1760 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 1761 #define COMMON_RESET_DIS (1 << 31) 1762 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 1763 _PHY_CTL_FAMILY_EDP, \ 1764 _PHY_CTL_FAMILY_DDI_C) 1765 1766 /* BXT PHY PLL registers */ 1767 #define _PORT_PLL_A 0x46074 1768 #define _PORT_PLL_B 0x46078 1769 #define _PORT_PLL_C 0x4607c 1770 #define PORT_PLL_ENABLE (1 << 31) 1771 #define PORT_PLL_LOCK (1 << 30) 1772 #define PORT_PLL_REF_SEL (1 << 27) 1773 #define PORT_PLL_POWER_ENABLE (1 << 26) 1774 #define PORT_PLL_POWER_STATE (1 << 25) 1775 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1776 1777 #define _PORT_PLL_EBB_0_A 0x162034 1778 #define _PORT_PLL_EBB_0_B 0x6C034 1779 #define _PORT_PLL_EBB_0_C 0x6C340 1780 #define PORT_PLL_P1_SHIFT 13 1781 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1782 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1783 #define PORT_PLL_P2_SHIFT 8 1784 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1785 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1786 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1787 _PORT_PLL_EBB_0_B, \ 1788 _PORT_PLL_EBB_0_C) 1789 1790 #define _PORT_PLL_EBB_4_A 0x162038 1791 #define _PORT_PLL_EBB_4_B 0x6C038 1792 #define _PORT_PLL_EBB_4_C 0x6C344 1793 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1794 #define PORT_PLL_RECALIBRATE (1 << 14) 1795 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1796 _PORT_PLL_EBB_4_B, \ 1797 _PORT_PLL_EBB_4_C) 1798 1799 #define _PORT_PLL_0_A 0x162100 1800 #define _PORT_PLL_0_B 0x6C100 1801 #define _PORT_PLL_0_C 0x6C380 1802 /* PORT_PLL_0_A */ 1803 #define PORT_PLL_M2_MASK 0xFF 1804 /* PORT_PLL_1_A */ 1805 #define PORT_PLL_N_SHIFT 8 1806 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1807 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1808 /* PORT_PLL_2_A */ 1809 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1810 /* PORT_PLL_3_A */ 1811 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1812 /* PORT_PLL_6_A */ 1813 #define PORT_PLL_PROP_COEFF_MASK 0xF 1814 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1815 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1816 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1817 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1818 /* PORT_PLL_8_A */ 1819 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1820 /* PORT_PLL_9_A */ 1821 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1822 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1823 /* PORT_PLL_10_A */ 1824 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) 1825 #define PORT_PLL_DCO_AMP_DEFAULT 15 1826 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1827 #define PORT_PLL_DCO_AMP(x) ((x) << 10) 1828 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 1829 _PORT_PLL_0_B, \ 1830 _PORT_PLL_0_C) 1831 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 1832 (idx) * 4) 1833 1834 /* BXT PHY common lane registers */ 1835 #define _PORT_CL1CM_DW0_A 0x162000 1836 #define _PORT_CL1CM_DW0_BC 0x6C000 1837 #define PHY_POWER_GOOD (1 << 16) 1838 #define PHY_RESERVED (1 << 7) 1839 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1840 1841 #define _PORT_CL1CM_DW9_A 0x162024 1842 #define _PORT_CL1CM_DW9_BC 0x6C024 1843 #define IREF0RC_OFFSET_SHIFT 8 1844 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1845 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 1846 1847 #define _PORT_CL1CM_DW10_A 0x162028 1848 #define _PORT_CL1CM_DW10_BC 0x6C028 1849 #define IREF1RC_OFFSET_SHIFT 8 1850 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1851 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1852 1853 #define _PORT_CL1CM_DW28_A 0x162070 1854 #define _PORT_CL1CM_DW28_BC 0x6C070 1855 #define OCL1_POWER_DOWN_EN (1 << 23) 1856 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1857 #define SUS_CLK_CONFIG 0x3 1858 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 1859 1860 #define _PORT_CL1CM_DW30_A 0x162078 1861 #define _PORT_CL1CM_DW30_BC 0x6C078 1862 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1863 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1864 1865 /* 1866 * CNL/ICL Port/COMBO-PHY Registers 1867 */ 1868 #define _ICL_COMBOPHY_A 0x162000 1869 #define _ICL_COMBOPHY_B 0x6C000 1870 #define _EHL_COMBOPHY_C 0x160000 1871 #define _RKL_COMBOPHY_D 0x161000 1872 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ 1873 _ICL_COMBOPHY_B, \ 1874 _EHL_COMBOPHY_C, \ 1875 _RKL_COMBOPHY_D) 1876 1877 /* CNL/ICL Port CL_DW registers */ 1878 #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 1879 4 * (dw)) 1880 1881 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1882 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) 1883 #define CL_POWER_DOWN_ENABLE (1 << 4) 1884 #define SUS_CLOCK_CONFIG (3 << 0) 1885 1886 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) 1887 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) 1888 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 1889 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) 1890 #define PWR_UP_ALL_LANES (0x0 << 4) 1891 #define PWR_DOWN_LN_3_2_1 (0xe << 4) 1892 #define PWR_DOWN_LN_3_2 (0xc << 4) 1893 #define PWR_DOWN_LN_3 (0x8 << 4) 1894 #define PWR_DOWN_LN_2_1_0 (0x7 << 4) 1895 #define PWR_DOWN_LN_1_0 (0x3 << 4) 1896 #define PWR_DOWN_LN_3_1 (0xa << 4) 1897 #define PWR_DOWN_LN_3_1_0 (0xb << 4) 1898 #define PWR_DOWN_LN_MASK (0xf << 4) 1899 #define PWR_DOWN_LN_SHIFT 4 1900 #define EDP4K2K_MODE_OVRD_EN (1 << 3) 1901 #define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) 1902 1903 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) 1904 #define ICL_LANE_ENABLE_AUX (1 << 0) 1905 1906 /* CNL/ICL Port COMP_DW registers */ 1907 #define _ICL_PORT_COMP 0x100 1908 #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 1909 _ICL_PORT_COMP + 4 * (dw)) 1910 1911 #define CNL_PORT_COMP_DW0 _MMIO(0x162100) 1912 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) 1913 #define COMP_INIT (1 << 31) 1914 1915 #define CNL_PORT_COMP_DW1 _MMIO(0x162104) 1916 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) 1917 1918 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 1919 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) 1920 #define PROCESS_INFO_DOT_0 (0 << 26) 1921 #define PROCESS_INFO_DOT_1 (1 << 26) 1922 #define PROCESS_INFO_DOT_4 (2 << 26) 1923 #define PROCESS_INFO_MASK (7 << 26) 1924 #define PROCESS_INFO_SHIFT 26 1925 #define VOLTAGE_INFO_0_85V (0 << 24) 1926 #define VOLTAGE_INFO_0_95V (1 << 24) 1927 #define VOLTAGE_INFO_1_05V (2 << 24) 1928 #define VOLTAGE_INFO_MASK (3 << 24) 1929 #define VOLTAGE_INFO_SHIFT 24 1930 1931 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) 1932 #define IREFGEN (1 << 24) 1933 1934 #define CNL_PORT_COMP_DW9 _MMIO(0x162124) 1935 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) 1936 1937 #define CNL_PORT_COMP_DW10 _MMIO(0x162128) 1938 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) 1939 1940 /* CNL/ICL Port PCS registers */ 1941 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1942 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1943 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1944 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 1945 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 1946 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 1947 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604 1948 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 1949 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 1950 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 1951 #define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \ 1952 _CNL_PORT_PCS_DW1_GRP_AE, \ 1953 _CNL_PORT_PCS_DW1_GRP_B, \ 1954 _CNL_PORT_PCS_DW1_GRP_C, \ 1955 _CNL_PORT_PCS_DW1_GRP_D, \ 1956 _CNL_PORT_PCS_DW1_GRP_AE, \ 1957 _CNL_PORT_PCS_DW1_GRP_F)) 1958 #define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ 1959 _CNL_PORT_PCS_DW1_LN0_AE, \ 1960 _CNL_PORT_PCS_DW1_LN0_B, \ 1961 _CNL_PORT_PCS_DW1_LN0_C, \ 1962 _CNL_PORT_PCS_DW1_LN0_D, \ 1963 _CNL_PORT_PCS_DW1_LN0_AE, \ 1964 _CNL_PORT_PCS_DW1_LN0_F)) 1965 1966 #define _ICL_PORT_PCS_AUX 0x300 1967 #define _ICL_PORT_PCS_GRP 0x600 1968 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) 1969 #define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ 1970 _ICL_PORT_PCS_AUX + 4 * (dw)) 1971 #define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ 1972 _ICL_PORT_PCS_GRP + 4 * (dw)) 1973 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ 1974 _ICL_PORT_PCS_LN(ln) + 4 * (dw)) 1975 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) 1976 #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) 1977 #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) 1978 #define DCC_MODE_SELECT_MASK (0x3 << 20) 1979 #define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) 1980 #define COMMON_KEEPER_EN (1 << 26) 1981 #define LATENCY_OPTIM_MASK (0x3 << 2) 1982 #define LATENCY_OPTIM_VAL(x) ((x) << 2) 1983 1984 /* CNL/ICL Port TX registers */ 1985 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 1986 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 1987 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 1988 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 1989 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 1990 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 1991 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 1992 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 1993 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 1994 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 1995 #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \ 1996 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1997 _CNL_PORT_TX_B_GRP_OFFSET, \ 1998 _CNL_PORT_TX_B_GRP_OFFSET, \ 1999 _CNL_PORT_TX_D_GRP_OFFSET, \ 2000 _CNL_PORT_TX_AE_GRP_OFFSET, \ 2001 _CNL_PORT_TX_F_GRP_OFFSET) + \ 2002 4 * (dw)) 2003 #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \ 2004 _CNL_PORT_TX_AE_LN0_OFFSET, \ 2005 _CNL_PORT_TX_B_LN0_OFFSET, \ 2006 _CNL_PORT_TX_B_LN0_OFFSET, \ 2007 _CNL_PORT_TX_D_LN0_OFFSET, \ 2008 _CNL_PORT_TX_AE_LN0_OFFSET, \ 2009 _CNL_PORT_TX_F_LN0_OFFSET) + \ 2010 4 * (dw)) 2011 2012 #define _ICL_PORT_TX_AUX 0x380 2013 #define _ICL_PORT_TX_GRP 0x680 2014 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) 2015 2016 #define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ 2017 _ICL_PORT_TX_AUX + 4 * (dw)) 2018 #define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ 2019 _ICL_PORT_TX_GRP + 4 * (dw)) 2020 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ 2021 _ICL_PORT_TX_LN(ln) + 4 * (dw)) 2022 2023 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) 2024 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) 2025 #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) 2026 #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) 2027 #define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) 2028 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) 2029 #define SWING_SEL_UPPER_MASK (1 << 15) 2030 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) 2031 #define SWING_SEL_LOWER_MASK (0x7 << 11) 2032 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8) 2033 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8) 2034 #define RCOMP_SCALAR(x) ((x) << 0) 2035 #define RCOMP_SCALAR_MASK (0xFF << 0) 2036 2037 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 2038 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 2039 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) 2040 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) 2041 #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ 2042 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 2043 _CNL_PORT_TX_DW4_LN0_AE))) 2044 #define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) 2045 #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) 2046 #define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) 2047 #define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) 2048 #define LOADGEN_SELECT (1 << 31) 2049 #define POST_CURSOR_1(x) ((x) << 12) 2050 #define POST_CURSOR_1_MASK (0x3F << 12) 2051 #define POST_CURSOR_2(x) ((x) << 6) 2052 #define POST_CURSOR_2_MASK (0x3F << 6) 2053 #define CURSOR_COEFF(x) ((x) << 0) 2054 #define CURSOR_COEFF_MASK (0x3F << 0) 2055 2056 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) 2057 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) 2058 #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) 2059 #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) 2060 #define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) 2061 #define TX_TRAINING_EN (1 << 31) 2062 #define TAP2_DISABLE (1 << 30) 2063 #define TAP3_DISABLE (1 << 29) 2064 #define SCALING_MODE_SEL(x) ((x) << 18) 2065 #define SCALING_MODE_SEL_MASK (0x7 << 18) 2066 #define RTERM_SELECT(x) ((x) << 3) 2067 #define RTERM_SELECT_MASK (0x7 << 3) 2068 2069 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) 2070 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) 2071 #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) 2072 #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) 2073 #define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) 2074 #define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) 2075 #define N_SCALAR(x) ((x) << 24) 2076 #define N_SCALAR_MASK (0x7F << 24) 2077 2078 #define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy)) 2079 #define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) 2080 #define ICL_PORT_TX_DW8_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy)) 2081 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) 2082 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) 2083 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) 2084 2085 #define _ICL_DPHY_CHKN_REG 0x194 2086 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) 2087 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) 2088 2089 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ 2090 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) 2091 2092 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C 2093 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C 2094 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C 2095 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C 2096 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C 2097 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C 2098 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C 2099 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C 2100 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ 2101 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ 2102 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ 2103 MG_TX_LINK_PARAMS_TX1LN1_PORT1) 2104 2105 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC 2106 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC 2107 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC 2108 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC 2109 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC 2110 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC 2111 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC 2112 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC 2113 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ 2114 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ 2115 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ 2116 MG_TX_LINK_PARAMS_TX2LN1_PORT1) 2117 #define CRI_USE_FS32 (1 << 5) 2118 2119 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C 2120 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C 2121 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C 2122 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C 2123 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C 2124 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C 2125 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C 2126 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C 2127 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ 2128 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ 2129 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ 2130 MG_TX_PISO_READLOAD_TX1LN1_PORT1) 2131 2132 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC 2133 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC 2134 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC 2135 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC 2136 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC 2137 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC 2138 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC 2139 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC 2140 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ 2141 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ 2142 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ 2143 MG_TX_PISO_READLOAD_TX2LN1_PORT1) 2144 #define CRI_CALCINIT (1 << 1) 2145 2146 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 2147 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 2148 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 2149 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 2150 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148 2151 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 2152 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 2153 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 2154 #define MG_TX1_SWINGCTRL(ln, tc_port) \ 2155 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ 2156 MG_TX_SWINGCTRL_TX1LN0_PORT2, \ 2157 MG_TX_SWINGCTRL_TX1LN1_PORT1) 2158 2159 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 2160 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 2161 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 2162 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 2163 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8 2164 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 2165 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 2166 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 2167 #define MG_TX2_SWINGCTRL(ln, tc_port) \ 2168 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ 2169 MG_TX_SWINGCTRL_TX2LN0_PORT2, \ 2170 MG_TX_SWINGCTRL_TX2LN1_PORT1) 2171 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) 2172 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) 2173 2174 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144 2175 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544 2176 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144 2177 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544 2178 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144 2179 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 2180 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 2181 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 2182 #define MG_TX1_DRVCTRL(ln, tc_port) \ 2183 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ 2184 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ 2185 MG_TX_DRVCTRL_TX1LN1_TXPORT1) 2186 2187 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 2188 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 2189 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 2190 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 2191 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4 2192 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 2193 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 2194 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 2195 #define MG_TX2_DRVCTRL(ln, tc_port) \ 2196 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ 2197 MG_TX_DRVCTRL_TX2LN0_PORT2, \ 2198 MG_TX_DRVCTRL_TX2LN1_PORT1) 2199 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) 2200 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) 2201 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) 2202 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) 2203 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) 2204 #define CRI_LOADGEN_SEL(x) ((x) << 12) 2205 #define CRI_LOADGEN_SEL_MASK (0x3 << 12) 2206 2207 #define MG_CLKHUB_LN0_PORT1 0x16839C 2208 #define MG_CLKHUB_LN1_PORT1 0x16879C 2209 #define MG_CLKHUB_LN0_PORT2 0x16939C 2210 #define MG_CLKHUB_LN1_PORT2 0x16979C 2211 #define MG_CLKHUB_LN0_PORT3 0x16A39C 2212 #define MG_CLKHUB_LN1_PORT3 0x16A79C 2213 #define MG_CLKHUB_LN0_PORT4 0x16B39C 2214 #define MG_CLKHUB_LN1_PORT4 0x16B79C 2215 #define MG_CLKHUB(ln, tc_port) \ 2216 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \ 2217 MG_CLKHUB_LN0_PORT2, \ 2218 MG_CLKHUB_LN1_PORT1) 2219 #define CFG_LOW_RATE_LKREN_EN (1 << 11) 2220 2221 #define MG_TX_DCC_TX1LN0_PORT1 0x168110 2222 #define MG_TX_DCC_TX1LN1_PORT1 0x168510 2223 #define MG_TX_DCC_TX1LN0_PORT2 0x169110 2224 #define MG_TX_DCC_TX1LN1_PORT2 0x169510 2225 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110 2226 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 2227 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 2228 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 2229 #define MG_TX1_DCC(ln, tc_port) \ 2230 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \ 2231 MG_TX_DCC_TX1LN0_PORT2, \ 2232 MG_TX_DCC_TX1LN1_PORT1) 2233 #define MG_TX_DCC_TX2LN0_PORT1 0x168090 2234 #define MG_TX_DCC_TX2LN1_PORT1 0x168490 2235 #define MG_TX_DCC_TX2LN0_PORT2 0x169090 2236 #define MG_TX_DCC_TX2LN1_PORT2 0x169490 2237 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090 2238 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 2239 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 2240 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 2241 #define MG_TX2_DCC(ln, tc_port) \ 2242 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \ 2243 MG_TX_DCC_TX2LN0_PORT2, \ 2244 MG_TX_DCC_TX2LN1_PORT1) 2245 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) 2246 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) 2247 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) 2248 2249 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 2250 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 2251 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 2252 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 2253 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0 2254 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 2255 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 2256 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 2257 #define MG_DP_MODE(ln, tc_port) \ 2258 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \ 2259 MG_DP_MODE_LN0_ACU_PORT2, \ 2260 MG_DP_MODE_LN1_ACU_PORT1) 2261 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) 2262 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) 2263 2264 /* The spec defines this only for BXT PHY0, but lets assume that this 2265 * would exist for PHY1 too if it had a second channel. 2266 */ 2267 #define _PORT_CL2CM_DW6_A 0x162358 2268 #define _PORT_CL2CM_DW6_BC 0x6C358 2269 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 2270 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 2271 2272 #define FIA1_BASE 0x163000 2273 #define FIA2_BASE 0x16E000 2274 #define FIA3_BASE 0x16F000 2275 #define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE) 2276 #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off)) 2277 2278 /* ICL PHY DFLEX registers */ 2279 #define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0) 2280 #define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx))) 2281 #define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx))) 2282 #define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx))) 2283 #define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx))) 2284 #define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx))) 2285 #define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx))) 2286 2287 /* BXT PHY Ref registers */ 2288 #define _PORT_REF_DW3_A 0x16218C 2289 #define _PORT_REF_DW3_BC 0x6C18C 2290 #define GRC_DONE (1 << 22) 2291 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 2292 2293 #define _PORT_REF_DW6_A 0x162198 2294 #define _PORT_REF_DW6_BC 0x6C198 2295 #define GRC_CODE_SHIFT 24 2296 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 2297 #define GRC_CODE_FAST_SHIFT 16 2298 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 2299 #define GRC_CODE_SLOW_SHIFT 8 2300 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 2301 #define GRC_CODE_NOM_MASK 0xFF 2302 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 2303 2304 #define _PORT_REF_DW8_A 0x1621A0 2305 #define _PORT_REF_DW8_BC 0x6C1A0 2306 #define GRC_DIS (1 << 15) 2307 #define GRC_RDY_OVRD (1 << 1) 2308 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 2309 2310 /* BXT PHY PCS registers */ 2311 #define _PORT_PCS_DW10_LN01_A 0x162428 2312 #define _PORT_PCS_DW10_LN01_B 0x6C428 2313 #define _PORT_PCS_DW10_LN01_C 0x6C828 2314 #define _PORT_PCS_DW10_GRP_A 0x162C28 2315 #define _PORT_PCS_DW10_GRP_B 0x6CC28 2316 #define _PORT_PCS_DW10_GRP_C 0x6CE28 2317 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2318 _PORT_PCS_DW10_LN01_B, \ 2319 _PORT_PCS_DW10_LN01_C) 2320 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2321 _PORT_PCS_DW10_GRP_B, \ 2322 _PORT_PCS_DW10_GRP_C) 2323 2324 #define TX2_SWING_CALC_INIT (1 << 31) 2325 #define TX1_SWING_CALC_INIT (1 << 30) 2326 2327 #define _PORT_PCS_DW12_LN01_A 0x162430 2328 #define _PORT_PCS_DW12_LN01_B 0x6C430 2329 #define _PORT_PCS_DW12_LN01_C 0x6C830 2330 #define _PORT_PCS_DW12_LN23_A 0x162630 2331 #define _PORT_PCS_DW12_LN23_B 0x6C630 2332 #define _PORT_PCS_DW12_LN23_C 0x6CA30 2333 #define _PORT_PCS_DW12_GRP_A 0x162c30 2334 #define _PORT_PCS_DW12_GRP_B 0x6CC30 2335 #define _PORT_PCS_DW12_GRP_C 0x6CE30 2336 #define LANESTAGGER_STRAP_OVRD (1 << 6) 2337 #define LANE_STAGGER_MASK 0x1F 2338 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2339 _PORT_PCS_DW12_LN01_B, \ 2340 _PORT_PCS_DW12_LN01_C) 2341 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2342 _PORT_PCS_DW12_LN23_B, \ 2343 _PORT_PCS_DW12_LN23_C) 2344 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2345 _PORT_PCS_DW12_GRP_B, \ 2346 _PORT_PCS_DW12_GRP_C) 2347 2348 /* BXT PHY TX registers */ 2349 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 2350 ((lane) & 1) * 0x80) 2351 2352 #define _PORT_TX_DW2_LN0_A 0x162508 2353 #define _PORT_TX_DW2_LN0_B 0x6C508 2354 #define _PORT_TX_DW2_LN0_C 0x6C908 2355 #define _PORT_TX_DW2_GRP_A 0x162D08 2356 #define _PORT_TX_DW2_GRP_B 0x6CD08 2357 #define _PORT_TX_DW2_GRP_C 0x6CF08 2358 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2359 _PORT_TX_DW2_LN0_B, \ 2360 _PORT_TX_DW2_LN0_C) 2361 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2362 _PORT_TX_DW2_GRP_B, \ 2363 _PORT_TX_DW2_GRP_C) 2364 #define MARGIN_000_SHIFT 16 2365 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 2366 #define UNIQ_TRANS_SCALE_SHIFT 8 2367 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 2368 2369 #define _PORT_TX_DW3_LN0_A 0x16250C 2370 #define _PORT_TX_DW3_LN0_B 0x6C50C 2371 #define _PORT_TX_DW3_LN0_C 0x6C90C 2372 #define _PORT_TX_DW3_GRP_A 0x162D0C 2373 #define _PORT_TX_DW3_GRP_B 0x6CD0C 2374 #define _PORT_TX_DW3_GRP_C 0x6CF0C 2375 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2376 _PORT_TX_DW3_LN0_B, \ 2377 _PORT_TX_DW3_LN0_C) 2378 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2379 _PORT_TX_DW3_GRP_B, \ 2380 _PORT_TX_DW3_GRP_C) 2381 #define SCALE_DCOMP_METHOD (1 << 26) 2382 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 2383 2384 #define _PORT_TX_DW4_LN0_A 0x162510 2385 #define _PORT_TX_DW4_LN0_B 0x6C510 2386 #define _PORT_TX_DW4_LN0_C 0x6C910 2387 #define _PORT_TX_DW4_GRP_A 0x162D10 2388 #define _PORT_TX_DW4_GRP_B 0x6CD10 2389 #define _PORT_TX_DW4_GRP_C 0x6CF10 2390 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2391 _PORT_TX_DW4_LN0_B, \ 2392 _PORT_TX_DW4_LN0_C) 2393 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2394 _PORT_TX_DW4_GRP_B, \ 2395 _PORT_TX_DW4_GRP_C) 2396 #define DEEMPH_SHIFT 24 2397 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 2398 2399 #define _PORT_TX_DW5_LN0_A 0x162514 2400 #define _PORT_TX_DW5_LN0_B 0x6C514 2401 #define _PORT_TX_DW5_LN0_C 0x6C914 2402 #define _PORT_TX_DW5_GRP_A 0x162D14 2403 #define _PORT_TX_DW5_GRP_B 0x6CD14 2404 #define _PORT_TX_DW5_GRP_C 0x6CF14 2405 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2406 _PORT_TX_DW5_LN0_B, \ 2407 _PORT_TX_DW5_LN0_C) 2408 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2409 _PORT_TX_DW5_GRP_B, \ 2410 _PORT_TX_DW5_GRP_C) 2411 #define DCC_DELAY_RANGE_1 (1 << 9) 2412 #define DCC_DELAY_RANGE_2 (1 << 8) 2413 2414 #define _PORT_TX_DW14_LN0_A 0x162538 2415 #define _PORT_TX_DW14_LN0_B 0x6C538 2416 #define _PORT_TX_DW14_LN0_C 0x6C938 2417 #define LATENCY_OPTIM_SHIFT 30 2418 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 2419 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 2420 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 2421 _PORT_TX_DW14_LN0_C) + \ 2422 _BXT_LANE_OFFSET(lane)) 2423 2424 /* UAIMI scratch pad register 1 */ 2425 #define UAIMI_SPR1 _MMIO(0x4F074) 2426 /* SKL VccIO mask */ 2427 #define SKL_VCCIO_MASK 0x1 2428 /* SKL balance leg register */ 2429 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 2430 /* I_boost values */ 2431 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 2432 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 2433 /* Balance leg disable bits */ 2434 #define BALANCE_LEG_DISABLE_SHIFT 23 2435 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 2436 2437 /* 2438 * Fence registers 2439 * [0-7] @ 0x2000 gen2,gen3 2440 * [8-15] @ 0x3000 945,g33,pnv 2441 * 2442 * [0-15] @ 0x3000 gen4,gen5 2443 * 2444 * [0-15] @ 0x100000 gen6,vlv,chv 2445 * [0-31] @ 0x100000 gen7+ 2446 */ 2447 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 2448 #define I830_FENCE_START_MASK 0x07f80000 2449 #define I830_FENCE_TILING_Y_SHIFT 12 2450 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 2451 #define I830_FENCE_PITCH_SHIFT 4 2452 #define I830_FENCE_REG_VALID (1 << 0) 2453 #define I915_FENCE_MAX_PITCH_VAL 4 2454 #define I830_FENCE_MAX_PITCH_VAL 6 2455 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 2456 2457 #define I915_FENCE_START_MASK 0x0ff00000 2458 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 2459 2460 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 2461 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 2462 #define I965_FENCE_PITCH_SHIFT 2 2463 #define I965_FENCE_TILING_Y_SHIFT 1 2464 #define I965_FENCE_REG_VALID (1 << 0) 2465 #define I965_FENCE_MAX_PITCH_VAL 0x0400 2466 2467 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 2468 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 2469 #define GEN6_FENCE_PITCH_SHIFT 32 2470 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 2471 2472 2473 /* control register for cpu gtt access */ 2474 #define TILECTL _MMIO(0x101000) 2475 #define TILECTL_SWZCTL (1 << 0) 2476 #define TILECTL_TLBPF (1 << 1) 2477 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 2478 #define TILECTL_BACKSNOOP_DIS (1 << 3) 2479 2480 /* 2481 * Instruction and interrupt control regs 2482 */ 2483 #define PGTBL_CTL _MMIO(0x02020) 2484 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 2485 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 2486 #define PGTBL_ER _MMIO(0x02024) 2487 #define PRB0_BASE (0x2030 - 0x30) 2488 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 2489 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 2490 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 2491 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 2492 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 2493 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 2494 #define RENDER_RING_BASE 0x02000 2495 #define BSD_RING_BASE 0x04000 2496 #define GEN6_BSD_RING_BASE 0x12000 2497 #define GEN8_BSD2_RING_BASE 0x1c000 2498 #define GEN11_BSD_RING_BASE 0x1c0000 2499 #define GEN11_BSD2_RING_BASE 0x1c4000 2500 #define GEN11_BSD3_RING_BASE 0x1d0000 2501 #define GEN11_BSD4_RING_BASE 0x1d4000 2502 #define VEBOX_RING_BASE 0x1a000 2503 #define GEN11_VEBOX_RING_BASE 0x1c8000 2504 #define GEN11_VEBOX2_RING_BASE 0x1d8000 2505 #define BLT_RING_BASE 0x22000 2506 #define RING_TAIL(base) _MMIO((base) + 0x30) 2507 #define RING_HEAD(base) _MMIO((base) + 0x34) 2508 #define RING_START(base) _MMIO((base) + 0x38) 2509 #define RING_CTL(base) _MMIO((base) + 0x3c) 2510 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 2511 #define RING_SYNC_0(base) _MMIO((base) + 0x40) 2512 #define RING_SYNC_1(base) _MMIO((base) + 0x44) 2513 #define RING_SYNC_2(base) _MMIO((base) + 0x48) 2514 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 2515 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 2516 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 2517 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 2518 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 2519 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 2520 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 2521 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 2522 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 2523 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 2524 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 2525 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 2526 #define GEN6_NOSYNC INVALID_MMIO_REG 2527 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 2528 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 2529 #define RING_HWS_PGA(base) _MMIO((base) + 0x80) 2530 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 2531 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 2532 #define RESET_CTL_CAT_ERROR REG_BIT(2) 2533 #define RESET_CTL_READY_TO_RESET REG_BIT(1) 2534 #define RESET_CTL_REQUEST_RESET REG_BIT(0) 2535 2536 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 2537 2538 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 2539 #define GTT_CACHE_EN_ALL 0xF0007FFF 2540 #define GEN7_WR_WATERMARK _MMIO(0x4028) 2541 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 2542 #define ARB_MODE _MMIO(0x4030) 2543 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 2544 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 2545 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 2546 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 2547 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 2548 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 2549 #define GEN7_LRA_LIMITS_REG_NUM 13 2550 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 2551 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 2552 2553 #define GAMTARBMODE _MMIO(0x04a08) 2554 #define ARB_MODE_BWGTLB_DISABLE (1 << 9) 2555 #define ARB_MODE_SWIZZLE_BDW (1 << 1) 2556 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 2557 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) 2558 #define GEN8_RING_FAULT_REG _MMIO(0x4094) 2559 #define GEN12_RING_FAULT_REG _MMIO(0xcec4) 2560 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 2561 #define RING_FAULT_GTTSEL_MASK (1 << 11) 2562 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 2563 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 2564 #define RING_FAULT_VALID (1 << 0) 2565 #define DONE_REG _MMIO(0x40b0) 2566 #define GEN12_GAM_DONE _MMIO(0xcf68) 2567 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 2568 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 2569 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) 2570 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) 2571 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 2572 #define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) 2573 #define GEN12_VD0_AUX_NV _MMIO(0x4218) 2574 #define GEN12_VD1_AUX_NV _MMIO(0x4228) 2575 #define GEN12_VD2_AUX_NV _MMIO(0x4298) 2576 #define GEN12_VD3_AUX_NV _MMIO(0x42A8) 2577 #define GEN12_VE0_AUX_NV _MMIO(0x4238) 2578 #define GEN12_VE1_AUX_NV _MMIO(0x42B8) 2579 #define AUX_INV REG_BIT(0) 2580 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 2581 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 2582 #define RING_ACTHD(base) _MMIO((base) + 0x74) 2583 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 2584 #define RING_NOPID(base) _MMIO((base) + 0x94) 2585 #define RING_IMR(base) _MMIO((base) + 0xa8) 2586 #define RING_HWSTAM(base) _MMIO((base) + 0x98) 2587 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 2588 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 2589 #define TAIL_ADDR 0x001FFFF8 2590 #define HEAD_WRAP_COUNT 0xFFE00000 2591 #define HEAD_WRAP_ONE 0x00200000 2592 #define HEAD_ADDR 0x001FFFFC 2593 #define RING_NR_PAGES 0x001FF000 2594 #define RING_REPORT_MASK 0x00000006 2595 #define RING_REPORT_64K 0x00000002 2596 #define RING_REPORT_128K 0x00000004 2597 #define RING_NO_REPORT 0x00000000 2598 #define RING_VALID_MASK 0x00000001 2599 #define RING_VALID 0x00000001 2600 #define RING_INVALID 0x00000000 2601 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 2602 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 2603 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 2604 2605 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ 2606 #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) 2607 #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) 2608 2609 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 2610 #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 2611 #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ 2612 #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) 2613 #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28) 2614 #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28) 2615 #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28) 2616 #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ 2617 #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) 2618 #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) 2619 #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) 2620 #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0) 2621 #define RING_FORCE_TO_NONPRIV_MASK_VALID \ 2622 (RING_FORCE_TO_NONPRIV_RANGE_MASK \ 2623 | RING_FORCE_TO_NONPRIV_ACCESS_MASK) 2624 #define RING_MAX_NONPRIV_SLOTS 12 2625 2626 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 2627 2628 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 2629 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) 2630 2631 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 2632 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 2633 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) 2634 2635 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2636 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 2637 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) 2638 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) 2639 2640 #if 0 2641 #define PRB0_TAIL _MMIO(0x2030) 2642 #define PRB0_HEAD _MMIO(0x2034) 2643 #define PRB0_START _MMIO(0x2038) 2644 #define PRB0_CTL _MMIO(0x203c) 2645 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 2646 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 2647 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 2648 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 2649 #endif 2650 #define IPEIR_I965 _MMIO(0x2064) 2651 #define IPEHR_I965 _MMIO(0x2068) 2652 #define GEN7_SC_INSTDONE _MMIO(0x7100) 2653 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) 2654 #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) 2655 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 2656 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 2657 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 2658 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 2659 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 2660 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 2661 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 2662 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) 2663 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) 2664 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) 2665 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) 2666 #define RING_IPEIR(base) _MMIO((base) + 0x64) 2667 #define RING_IPEHR(base) _MMIO((base) + 0x68) 2668 #define RING_EIR(base) _MMIO((base) + 0xb0) 2669 #define RING_EMR(base) _MMIO((base) + 0xb4) 2670 #define RING_ESR(base) _MMIO((base) + 0xb8) 2671 /* 2672 * On GEN4, only the render ring INSTDONE exists and has a different 2673 * layout than the GEN7+ version. 2674 * The GEN2 counterpart of this register is GEN2_INSTDONE. 2675 */ 2676 #define RING_INSTDONE(base) _MMIO((base) + 0x6c) 2677 #define RING_INSTPS(base) _MMIO((base) + 0x70) 2678 #define RING_DMA_FADD(base) _MMIO((base) + 0x78) 2679 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 2680 #define RING_INSTPM(base) _MMIO((base) + 0xc0) 2681 #define RING_MI_MODE(base) _MMIO((base) + 0x9c) 2682 #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) 2683 #define INSTPS _MMIO(0x2070) /* 965+ only */ 2684 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 2685 #define ACTHD_I965 _MMIO(0x2074) 2686 #define HWS_PGA _MMIO(0x2080) 2687 #define HWS_ADDRESS_MASK 0xfffff000 2688 #define HWS_START_ADDRESS_SHIFT 4 2689 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 2690 #define PWRCTX_EN (1 << 0) 2691 #define IPEIR(base) _MMIO((base) + 0x88) 2692 #define IPEHR(base) _MMIO((base) + 0x8c) 2693 #define GEN2_INSTDONE _MMIO(0x2090) 2694 #define NOPID _MMIO(0x2094) 2695 #define HWSTAM _MMIO(0x2098) 2696 #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 2697 #define RING_BBSTATE(base) _MMIO((base) + 0x110) 2698 #define RING_BB_PPGTT (1 << 5) 2699 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 2700 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 2701 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 2702 #define RING_BBADDR(base) _MMIO((base) + 0x140) 2703 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 2704 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 2705 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 2706 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 2707 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 2708 2709 #define ERROR_GEN6 _MMIO(0x40a0) 2710 #define GEN7_ERR_INT _MMIO(0x44040) 2711 #define ERR_INT_POISON (1 << 31) 2712 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 2713 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 2714 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 2715 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 2716 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 2717 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 2718 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 2719 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 2720 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 2721 2722 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 2723 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 2724 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) 2725 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) 2726 #define FAULT_VA_HIGH_BITS (0xf << 0) 2727 #define FAULT_GTT_SEL (1 << 4) 2728 2729 #define GEN12_AUX_ERR_DBG _MMIO(0x43f4) 2730 2731 #define FPGA_DBG _MMIO(0x42300) 2732 #define FPGA_DBG_RM_NOCLAIM (1 << 31) 2733 2734 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 2735 #define CLAIM_ER_CLR (1 << 31) 2736 #define CLAIM_ER_OVERFLOW (1 << 16) 2737 #define CLAIM_ER_CTR_MASK 0xffff 2738 2739 #define DERRMR _MMIO(0x44050) 2740 /* Note that HBLANK events are reserved on bdw+ */ 2741 #define DERRMR_PIPEA_SCANLINE (1 << 0) 2742 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 2743 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 2744 #define DERRMR_PIPEA_VBLANK (1 << 3) 2745 #define DERRMR_PIPEA_HBLANK (1 << 5) 2746 #define DERRMR_PIPEB_SCANLINE (1 << 8) 2747 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 2748 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 2749 #define DERRMR_PIPEB_VBLANK (1 << 11) 2750 #define DERRMR_PIPEB_HBLANK (1 << 13) 2751 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 2752 #define DERRMR_PIPEC_SCANLINE (1 << 14) 2753 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 2754 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 2755 #define DERRMR_PIPEC_VBLANK (1 << 21) 2756 #define DERRMR_PIPEC_HBLANK (1 << 22) 2757 2758 2759 /* GM45+ chicken bits -- debug workaround bits that may be required 2760 * for various sorts of correct behavior. The top 16 bits of each are 2761 * the enables for writing to the corresponding low bit. 2762 */ 2763 #define _3D_CHICKEN _MMIO(0x2084) 2764 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 2765 #define _3D_CHICKEN2 _MMIO(0x208c) 2766 2767 #define FF_SLICE_CHICKEN _MMIO(0x2088) 2768 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) 2769 2770 /* Disables pipelining of read flushes past the SF-WIZ interface. 2771 * Required on all Ironlake steppings according to the B-Spec, but the 2772 * particular danger of not doing so is not specified. 2773 */ 2774 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2775 #define _3D_CHICKEN3 _MMIO(0x2090) 2776 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) 2777 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2778 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 2779 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2780 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ 2781 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2782 2783 #define MI_MODE _MMIO(0x209c) 2784 # define VS_TIMER_DISPATCH (1 << 6) 2785 # define MI_FLUSH_ENABLE (1 << 12) 2786 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 2787 # define MODE_IDLE (1 << 9) 2788 # define STOP_RING (1 << 8) 2789 2790 #define GEN6_GT_MODE _MMIO(0x20d0) 2791 #define GEN7_GT_MODE _MMIO(0x7008) 2792 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 2793 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 2794 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 2795 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 2796 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 2797 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 2798 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 2799 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 2800 2801 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2802 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2803 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2804 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7) 2805 2806 /* WaClearTdlStateAckDirtyBits */ 2807 #define GEN8_STATE_ACK _MMIO(0x20F0) 2808 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 2809 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 2810 #define GEN9_STATE_ACK_TDL0 (1 << 12) 2811 #define GEN9_STATE_ACK_TDL1 (1 << 13) 2812 #define GEN9_STATE_ACK_TDL2 (1 << 14) 2813 #define GEN9_STATE_ACK_TDL3 (1 << 15) 2814 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 2815 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 2816 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 2817 2818 #define GFX_MODE _MMIO(0x2520) 2819 #define GFX_MODE_GEN7 _MMIO(0x229c) 2820 #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) 2821 #define GFX_RUN_LIST_ENABLE (1 << 15) 2822 #define GFX_INTERRUPT_STEERING (1 << 14) 2823 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 2824 #define GFX_SURFACE_FAULT_ENABLE (1 << 12) 2825 #define GFX_REPLAY_MODE (1 << 11) 2826 #define GFX_PSMI_GRANULARITY (1 << 10) 2827 #define GFX_PPGTT_ENABLE (1 << 9) 2828 #define GEN8_GFX_PPGTT_48B (1 << 7) 2829 2830 #define GFX_FORWARD_VBLANK_MASK (3 << 5) 2831 #define GFX_FORWARD_VBLANK_NEVER (0 << 5) 2832 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 2833 #define GFX_FORWARD_VBLANK_COND (2 << 5) 2834 2835 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 2836 2837 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 2838 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 2839 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 2840 #define SCPD_FBC_IGNORE_3D (1 << 6) 2841 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 2842 #define GEN2_IER _MMIO(0x20a0) 2843 #define GEN2_IIR _MMIO(0x20a4) 2844 #define GEN2_IMR _MMIO(0x20a8) 2845 #define GEN2_ISR _MMIO(0x20ac) 2846 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 2847 #define GINT_DIS (1 << 22) 2848 #define GCFG_DIS (1 << 8) 2849 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 2850 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 2851 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 2852 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 2853 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 2854 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 2855 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 2856 #define VLV_PCBR_ADDR_SHIFT 12 2857 2858 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 2859 #define EIR _MMIO(0x20b0) 2860 #define EMR _MMIO(0x20b4) 2861 #define ESR _MMIO(0x20b8) 2862 #define GM45_ERROR_PAGE_TABLE (1 << 5) 2863 #define GM45_ERROR_MEM_PRIV (1 << 4) 2864 #define I915_ERROR_PAGE_TABLE (1 << 4) 2865 #define GM45_ERROR_CP_PRIV (1 << 3) 2866 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 2867 #define I915_ERROR_INSTRUCTION (1 << 0) 2868 #define INSTPM _MMIO(0x20c0) 2869 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 2870 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 2871 will not assert AGPBUSY# and will only 2872 be delivered when out of C3. */ 2873 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 2874 #define INSTPM_TLB_INVALIDATE (1 << 9) 2875 #define INSTPM_SYNC_FLUSH (1 << 5) 2876 #define ACTHD(base) _MMIO((base) + 0xc8) 2877 #define MEM_MODE _MMIO(0x20cc) 2878 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 2879 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 2880 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 2881 #define FW_BLC _MMIO(0x20d8) 2882 #define FW_BLC2 _MMIO(0x20dc) 2883 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 2884 #define FW_BLC_SELF_EN_MASK (1 << 31) 2885 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 2886 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 2887 #define MM_BURST_LENGTH 0x00700000 2888 #define MM_FIFO_WATERMARK 0x0001F000 2889 #define LM_BURST_LENGTH 0x00000700 2890 #define LM_FIFO_WATERMARK 0x0000001F 2891 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 2892 2893 #define _MBUS_ABOX0_CTL 0x45038 2894 #define _MBUS_ABOX1_CTL 0x45048 2895 #define _MBUS_ABOX2_CTL 0x4504C 2896 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 2897 _MBUS_ABOX1_CTL, \ 2898 _MBUS_ABOX2_CTL)) 2899 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 2900 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 2901 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 2902 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 2903 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 2904 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 2905 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 2906 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 2907 2908 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 2909 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 2910 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 2911 _PIPEB_MBUS_DBOX_CTL) 2912 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) 2913 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) 2914 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) 2915 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8) 2916 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) 2917 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0) 2918 2919 #define MBUS_UBOX_CTL _MMIO(0x4503C) 2920 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 2921 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 2922 2923 #define HDPORT_STATE _MMIO(0x45050) 2924 #define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) 2925 #define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) 2926 #define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) 2927 #define HDPORT_ENABLED REG_BIT(0) 2928 2929 /* Make render/texture TLB fetches lower priorty than associated data 2930 * fetches. This is not turned on by default 2931 */ 2932 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 2933 2934 /* Isoch request wait on GTT enable (Display A/B/C streams). 2935 * Make isoch requests stall on the TLB update. May cause 2936 * display underruns (test mode only) 2937 */ 2938 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 2939 2940 /* Block grant count for isoch requests when block count is 2941 * set to a finite value. 2942 */ 2943 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 2944 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 2945 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 2946 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 2947 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 2948 2949 /* Enable render writes to complete in C2/C3/C4 power states. 2950 * If this isn't enabled, render writes are prevented in low 2951 * power states. That seems bad to me. 2952 */ 2953 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 2954 2955 /* This acknowledges an async flip immediately instead 2956 * of waiting for 2TLB fetches. 2957 */ 2958 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 2959 2960 /* Enables non-sequential data reads through arbiter 2961 */ 2962 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 2963 2964 /* Disable FSB snooping of cacheable write cycles from binner/render 2965 * command stream 2966 */ 2967 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 2968 2969 /* Arbiter time slice for non-isoch streams */ 2970 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 2971 #define MI_ARB_TIME_SLICE_1 (0 << 5) 2972 #define MI_ARB_TIME_SLICE_2 (1 << 5) 2973 #define MI_ARB_TIME_SLICE_4 (2 << 5) 2974 #define MI_ARB_TIME_SLICE_6 (3 << 5) 2975 #define MI_ARB_TIME_SLICE_8 (4 << 5) 2976 #define MI_ARB_TIME_SLICE_10 (5 << 5) 2977 #define MI_ARB_TIME_SLICE_14 (6 << 5) 2978 #define MI_ARB_TIME_SLICE_16 (7 << 5) 2979 2980 /* Low priority grace period page size */ 2981 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 2982 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 2983 2984 /* Disable display A/B trickle feed */ 2985 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 2986 2987 /* Set display plane priority */ 2988 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 2989 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 2990 2991 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 2992 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 2993 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 2994 2995 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 2996 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) 2997 #define CM0_IZ_OPT_DISABLE (1 << 6) 2998 #define CM0_ZR_OPT_DISABLE (1 << 5) 2999 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) 3000 #define CM0_DEPTH_EVICT_DISABLE (1 << 4) 3001 #define CM0_COLOR_EVICT_DISABLE (1 << 3) 3002 #define CM0_DEPTH_WRITE_DISABLE (1 << 1) 3003 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0) 3004 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 3005 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 3006 #define GFX_FLSH_CNTL_EN (1 << 0) 3007 #define ECOSKPD _MMIO(0x21d0) 3008 #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) 3009 #define ECO_GATING_CX_ONLY (1 << 3) 3010 #define ECO_FLIP_DONE (1 << 0) 3011 3012 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 3013 #define RC_OP_FLUSH_ENABLE (1 << 0) 3014 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 3015 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 3016 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) 3017 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) 3018 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) 3019 3020 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 3021 #define GEN6_BLITTER_LOCK_SHIFT 16 3022 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3) 3023 3024 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 3025 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 3026 #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 3027 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 3028 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10) 3029 3030 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 3031 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 3032 3033 #define GEN10_CACHE_MODE_SS _MMIO(0xe420) 3034 #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) 3035 3036 /* Fuse readout registers for GT */ 3037 #define HSW_PAVP_FUSE1 _MMIO(0x911C) 3038 #define HSW_F1_EU_DIS_SHIFT 16 3039 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT) 3040 #define HSW_F1_EU_DIS_10EUS 0 3041 #define HSW_F1_EU_DIS_8EUS 1 3042 #define HSW_F1_EU_DIS_6EUS 2 3043 3044 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 3045 #define CHV_FGT_DISABLE_SS0 (1 << 10) 3046 #define CHV_FGT_DISABLE_SS1 (1 << 11) 3047 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 3048 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 3049 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 3050 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 3051 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 3052 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 3053 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 3054 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 3055 3056 #define GEN8_FUSE2 _MMIO(0x9120) 3057 #define GEN8_F2_SS_DIS_SHIFT 21 3058 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 3059 #define GEN8_F2_S_ENA_SHIFT 25 3060 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 3061 3062 #define GEN9_F2_SS_DIS_SHIFT 20 3063 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 3064 3065 #define GEN10_F2_S_ENA_SHIFT 22 3066 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 3067 #define GEN10_F2_SS_DIS_SHIFT 18 3068 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 3069 3070 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) 3071 #define GEN10_L3BANK_PAIR_COUNT 4 3072 #define GEN10_L3BANK_MASK 0x0F 3073 3074 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 3075 #define GEN8_EU_DIS0_S0_MASK 0xffffff 3076 #define GEN8_EU_DIS0_S1_SHIFT 24 3077 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 3078 3079 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 3080 #define GEN8_EU_DIS1_S1_MASK 0xffff 3081 #define GEN8_EU_DIS1_S2_SHIFT 16 3082 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 3083 3084 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 3085 #define GEN8_EU_DIS2_S2_MASK 0xff 3086 3087 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 3088 3089 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 3090 #define GEN10_EU_DIS_SS_MASK 0xff 3091 3092 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 3093 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff 3094 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 3095 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 3096 3097 #define GEN11_EU_DISABLE _MMIO(0x9134) 3098 #define GEN11_EU_DIS_MASK 0xFF 3099 3100 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 3101 #define GEN11_GT_S_ENA_MASK 0xFF 3102 3103 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C) 3104 3105 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C) 3106 3107 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 3108 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 3109 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 3110 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 3111 #define GEN6_BSD_GO_INDICATOR (1 << 4) 3112 3113 /* On modern GEN architectures interrupt control consists of two sets 3114 * of registers. The first set pertains to the ring generating the 3115 * interrupt. The second control is for the functional block generating the 3116 * interrupt. These are PM, GT, DE, etc. 3117 * 3118 * Luckily *knocks on wood* all the ring interrupt bits match up with the 3119 * GT interrupt bits, so we don't need to duplicate the defines. 3120 * 3121 * These defines should cover us well from SNB->HSW with minor exceptions 3122 * it can also work on ILK. 3123 */ 3124 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 3125 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 3126 #define GT_BLT_USER_INTERRUPT (1 << 22) 3127 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 3128 #define GT_BSD_USER_INTERRUPT (1 << 12) 3129 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 3130 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 3131 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 3132 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 3133 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 3134 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 3135 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 3136 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 3137 #define GT_RENDER_USER_INTERRUPT (1 << 0) 3138 3139 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 3140 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 3141 3142 #define GT_PARITY_ERROR(dev_priv) \ 3143 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 3144 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 3145 3146 /* These are all the "old" interrupts */ 3147 #define ILK_BSD_USER_INTERRUPT (1 << 5) 3148 3149 #define I915_PM_INTERRUPT (1 << 31) 3150 #define I915_ISP_INTERRUPT (1 << 22) 3151 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 3152 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 3153 #define I915_MIPIC_INTERRUPT (1 << 19) 3154 #define I915_MIPIA_INTERRUPT (1 << 18) 3155 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 3156 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 3157 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 3158 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 3159 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 3160 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 3161 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 3162 #define I915_HWB_OOM_INTERRUPT (1 << 13) 3163 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 3164 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 3165 #define I915_MISC_INTERRUPT (1 << 11) 3166 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 3167 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 3168 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 3169 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 3170 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 3171 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 3172 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 3173 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 3174 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 3175 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 3176 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 3177 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 3178 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 3179 #define I915_DEBUG_INTERRUPT (1 << 2) 3180 #define I915_WINVALID_INTERRUPT (1 << 1) 3181 #define I915_USER_INTERRUPT (1 << 1) 3182 #define I915_ASLE_INTERRUPT (1 << 0) 3183 #define I915_BSD_USER_INTERRUPT (1 << 25) 3184 3185 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 3186 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 3187 3188 /* DisplayPort Audio w/ LPE */ 3189 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 3190 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 3191 3192 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 3193 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 3194 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 3195 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 3196 _VLV_AUD_PORT_EN_B_DBG, \ 3197 _VLV_AUD_PORT_EN_C_DBG, \ 3198 _VLV_AUD_PORT_EN_D_DBG) 3199 #define VLV_AMP_MUTE (1 << 1) 3200 3201 #define GEN6_BSD_RNCID _MMIO(0x12198) 3202 3203 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 3204 #define GEN7_FF_SCHED_MASK 0x0077070 3205 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 3206 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 3207 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 3208 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 3209 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 3210 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 3211 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 3212 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 3213 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 3214 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 3215 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 3216 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 3217 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 3218 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 3219 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 3220 3221 /* 3222 * Framebuffer compression (915+ only) 3223 */ 3224 3225 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 3226 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 3227 #define FBC_CONTROL _MMIO(0x3208) 3228 #define FBC_CTL_EN REG_BIT(31) 3229 #define FBC_CTL_PERIODIC REG_BIT(30) 3230 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 3231 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 3232 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 3233 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 3234 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */ 3235 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 3236 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 3237 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 3238 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 3239 #define FBC_COMMAND _MMIO(0x320c) 3240 #define FBC_CMD_COMPRESS (1 << 0) 3241 #define FBC_STATUS _MMIO(0x3210) 3242 #define FBC_STAT_COMPRESSING (1 << 31) 3243 #define FBC_STAT_COMPRESSED (1 << 30) 3244 #define FBC_STAT_MODIFIED (1 << 29) 3245 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 3246 #define FBC_CONTROL2 _MMIO(0x3214) 3247 #define FBC_CTL_FENCE_DBL (0 << 4) 3248 #define FBC_CTL_IDLE_IMM (0 << 2) 3249 #define FBC_CTL_IDLE_FULL (1 << 2) 3250 #define FBC_CTL_IDLE_LINE (2 << 2) 3251 #define FBC_CTL_IDLE_DEBUG (3 << 2) 3252 #define FBC_CTL_CPU_FENCE (1 << 1) 3253 #define FBC_CTL_PLANE(plane) ((plane) << 0) 3254 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 3255 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 3256 3257 #define FBC_LL_SIZE (1536) 3258 3259 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 3260 #define FBC_LLC_FULLY_OPEN (1 << 30) 3261 3262 /* Framebuffer compression for GM45+ */ 3263 #define DPFC_CB_BASE _MMIO(0x3200) 3264 #define DPFC_CONTROL _MMIO(0x3208) 3265 #define DPFC_CTL_EN (1 << 31) 3266 #define DPFC_CTL_PLANE(plane) ((plane) << 30) 3267 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29) 3268 #define DPFC_CTL_FENCE_EN (1 << 29) 3269 #define IVB_DPFC_CTL_FENCE_EN (1 << 28) 3270 #define DPFC_CTL_PERSISTENT_MODE (1 << 25) 3271 #define DPFC_SR_EN (1 << 10) 3272 #define DPFC_CTL_LIMIT_1X (0 << 6) 3273 #define DPFC_CTL_LIMIT_2X (1 << 6) 3274 #define DPFC_CTL_LIMIT_4X (2 << 6) 3275 #define DPFC_RECOMP_CTL _MMIO(0x320c) 3276 #define DPFC_RECOMP_STALL_EN (1 << 27) 3277 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 3278 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 3279 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 3280 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 3281 #define DPFC_STATUS _MMIO(0x3210) 3282 #define DPFC_INVAL_SEG_SHIFT (16) 3283 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 3284 #define DPFC_COMP_SEG_SHIFT (0) 3285 #define DPFC_COMP_SEG_MASK (0x000007ff) 3286 #define DPFC_STATUS2 _MMIO(0x3214) 3287 #define DPFC_FENCE_YOFF _MMIO(0x3218) 3288 #define DPFC_CHICKEN _MMIO(0x3224) 3289 #define DPFC_HT_MODIFY (1 << 31) 3290 3291 /* Framebuffer compression for Ironlake */ 3292 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 3293 #define ILK_DPFC_CONTROL _MMIO(0x43208) 3294 #define FBC_CTL_FALSE_COLOR (1 << 10) 3295 /* The bit 28-8 is reserved */ 3296 #define DPFC_RESERVED (0x1FFFFF00) 3297 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 3298 #define ILK_DPFC_STATUS _MMIO(0x43210) 3299 #define ILK_DPFC_COMP_SEG_MASK 0x7ff 3300 #define IVB_FBC_STATUS2 _MMIO(0x43214) 3301 #define IVB_FBC_COMP_SEG_MASK 0x7ff 3302 #define BDW_FBC_COMP_SEG_MASK 0xfff 3303 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 3304 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 3305 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) 3306 #define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14) 3307 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) 3308 #define ILK_FBC_RT_BASE _MMIO(0x2128) 3309 #define ILK_FBC_RT_VALID (1 << 0) 3310 #define SNB_FBC_FRONT_BUFFER (1 << 1) 3311 3312 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 3313 #define ILK_FBCQ_DIS (1 << 22) 3314 #define ILK_PABSTRETCH_DIS (1 << 21) 3315 3316 3317 /* 3318 * Framebuffer compression for Sandybridge 3319 * 3320 * The following two registers are of type GTTMMADR 3321 */ 3322 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 3323 #define SNB_CPU_FENCE_ENABLE (1 << 29) 3324 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 3325 3326 /* Framebuffer compression for Ivybridge */ 3327 #define IVB_FBC_RT_BASE _MMIO(0x7020) 3328 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 3329 3330 #define IPS_CTL _MMIO(0x43408) 3331 #define IPS_ENABLE (1 << 31) 3332 3333 #define MSG_FBC_REND_STATE _MMIO(0x50380) 3334 #define FBC_REND_NUKE (1 << 2) 3335 #define FBC_REND_CACHE_CLEAN (1 << 1) 3336 3337 /* 3338 * GPIO regs 3339 */ 3340 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 3341 4 * (gpio)) 3342 3343 # define GPIO_CLOCK_DIR_MASK (1 << 0) 3344 # define GPIO_CLOCK_DIR_IN (0 << 1) 3345 # define GPIO_CLOCK_DIR_OUT (1 << 1) 3346 # define GPIO_CLOCK_VAL_MASK (1 << 2) 3347 # define GPIO_CLOCK_VAL_OUT (1 << 3) 3348 # define GPIO_CLOCK_VAL_IN (1 << 4) 3349 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 3350 # define GPIO_DATA_DIR_MASK (1 << 8) 3351 # define GPIO_DATA_DIR_IN (0 << 9) 3352 # define GPIO_DATA_DIR_OUT (1 << 9) 3353 # define GPIO_DATA_VAL_MASK (1 << 10) 3354 # define GPIO_DATA_VAL_OUT (1 << 11) 3355 # define GPIO_DATA_VAL_IN (1 << 12) 3356 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 3357 3358 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 3359 #define GMBUS_AKSV_SELECT (1 << 11) 3360 #define GMBUS_RATE_100KHZ (0 << 8) 3361 #define GMBUS_RATE_50KHZ (1 << 8) 3362 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 3363 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 3364 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 3365 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 3366 3367 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 3368 #define GMBUS_SW_CLR_INT (1 << 31) 3369 #define GMBUS_SW_RDY (1 << 30) 3370 #define GMBUS_ENT (1 << 29) /* enable timeout */ 3371 #define GMBUS_CYCLE_NONE (0 << 25) 3372 #define GMBUS_CYCLE_WAIT (1 << 25) 3373 #define GMBUS_CYCLE_INDEX (2 << 25) 3374 #define GMBUS_CYCLE_STOP (4 << 25) 3375 #define GMBUS_BYTE_COUNT_SHIFT 16 3376 #define GMBUS_BYTE_COUNT_MAX 256U 3377 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 3378 #define GMBUS_SLAVE_INDEX_SHIFT 8 3379 #define GMBUS_SLAVE_ADDR_SHIFT 1 3380 #define GMBUS_SLAVE_READ (1 << 0) 3381 #define GMBUS_SLAVE_WRITE (0 << 0) 3382 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 3383 #define GMBUS_INUSE (1 << 15) 3384 #define GMBUS_HW_WAIT_PHASE (1 << 14) 3385 #define GMBUS_STALL_TIMEOUT (1 << 13) 3386 #define GMBUS_INT (1 << 12) 3387 #define GMBUS_HW_RDY (1 << 11) 3388 #define GMBUS_SATOER (1 << 10) 3389 #define GMBUS_ACTIVE (1 << 9) 3390 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 3391 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 3392 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 3393 #define GMBUS_NAK_EN (1 << 3) 3394 #define GMBUS_IDLE_EN (1 << 2) 3395 #define GMBUS_HW_WAIT_EN (1 << 1) 3396 #define GMBUS_HW_RDY_EN (1 << 0) 3397 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 3398 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 3399 3400 /* 3401 * Clock control & power management 3402 */ 3403 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 3404 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 3405 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 3406 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 3407 3408 #define VGA0 _MMIO(0x6000) 3409 #define VGA1 _MMIO(0x6004) 3410 #define VGA_PD _MMIO(0x6010) 3411 #define VGA0_PD_P2_DIV_4 (1 << 7) 3412 #define VGA0_PD_P1_DIV_2 (1 << 5) 3413 #define VGA0_PD_P1_SHIFT 0 3414 #define VGA0_PD_P1_MASK (0x1f << 0) 3415 #define VGA1_PD_P2_DIV_4 (1 << 15) 3416 #define VGA1_PD_P1_DIV_2 (1 << 13) 3417 #define VGA1_PD_P1_SHIFT 8 3418 #define VGA1_PD_P1_MASK (0x1f << 8) 3419 #define DPLL_VCO_ENABLE (1 << 31) 3420 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 3421 #define DPLL_DVO_2X_MODE (1 << 30) 3422 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 3423 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 3424 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 3425 #define DPLL_VGA_MODE_DIS (1 << 28) 3426 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 3427 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 3428 #define DPLL_MODE_MASK (3 << 26) 3429 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 3430 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 3431 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 3432 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 3433 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 3434 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 3435 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 3436 #define DPLL_LOCK_VLV (1 << 15) 3437 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 3438 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 3439 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 3440 #define DPLL_PORTC_READY_MASK (0xf << 4) 3441 #define DPLL_PORTB_READY_MASK (0xf) 3442 3443 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 3444 3445 /* Additional CHV pll/phy registers */ 3446 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 3447 #define DPLL_PORTD_READY_MASK (0xf) 3448 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 3449 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 3450 #define PHY_LDO_DELAY_0NS 0x0 3451 #define PHY_LDO_DELAY_200NS 0x1 3452 #define PHY_LDO_DELAY_600NS 0x2 3453 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 3454 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 3455 #define PHY_CH_SU_PSR 0x1 3456 #define PHY_CH_DEEP_PSR 0x7 3457 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 3458 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 3459 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 3460 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 3461 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 3462 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 3463 3464 /* 3465 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 3466 * this field (only one bit may be set). 3467 */ 3468 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 3469 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 3470 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 3471 /* i830, required in DVO non-gang */ 3472 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 3473 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 3474 #define PLL_REF_INPUT_DREFCLK (0 << 13) 3475 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 3476 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 3477 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 3478 #define PLL_REF_INPUT_MASK (3 << 13) 3479 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 3480 /* Ironlake */ 3481 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 3482 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 3483 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 3484 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 3485 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 3486 3487 /* 3488 * Parallel to Serial Load Pulse phase selection. 3489 * Selects the phase for the 10X DPLL clock for the PCIe 3490 * digital display port. The range is 4 to 13; 10 or more 3491 * is just a flip delay. The default is 6 3492 */ 3493 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 3494 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 3495 /* 3496 * SDVO multiplier for 945G/GM. Not used on 965. 3497 */ 3498 #define SDVO_MULTIPLIER_MASK 0x000000ff 3499 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 3500 #define SDVO_MULTIPLIER_SHIFT_VGA 0 3501 3502 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 3503 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 3504 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 3505 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 3506 3507 /* 3508 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 3509 * 3510 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 3511 */ 3512 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 3513 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 3514 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 3515 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 3516 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 3517 /* 3518 * SDVO/UDI pixel multiplier. 3519 * 3520 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 3521 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 3522 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 3523 * dummy bytes in the datastream at an increased clock rate, with both sides of 3524 * the link knowing how many bytes are fill. 3525 * 3526 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 3527 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 3528 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 3529 * through an SDVO command. 3530 * 3531 * This register field has values of multiplication factor minus 1, with 3532 * a maximum multiplier of 5 for SDVO. 3533 */ 3534 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 3535 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 3536 /* 3537 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 3538 * This best be set to the default value (3) or the CRT won't work. No, 3539 * I don't entirely understand what this does... 3540 */ 3541 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 3542 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 3543 3544 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 3545 3546 #define _FPA0 0x6040 3547 #define _FPA1 0x6044 3548 #define _FPB0 0x6048 3549 #define _FPB1 0x604c 3550 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 3551 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 3552 #define FP_N_DIV_MASK 0x003f0000 3553 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 3554 #define FP_N_DIV_SHIFT 16 3555 #define FP_M1_DIV_MASK 0x00003f00 3556 #define FP_M1_DIV_SHIFT 8 3557 #define FP_M2_DIV_MASK 0x0000003f 3558 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 3559 #define FP_M2_DIV_SHIFT 0 3560 #define DPLL_TEST _MMIO(0x606c) 3561 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 3562 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 3563 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 3564 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 3565 #define DPLLB_TEST_N_BYPASS (1 << 19) 3566 #define DPLLB_TEST_M_BYPASS (1 << 18) 3567 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 3568 #define DPLLA_TEST_N_BYPASS (1 << 3) 3569 #define DPLLA_TEST_M_BYPASS (1 << 2) 3570 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 3571 #define D_STATE _MMIO(0x6104) 3572 #define DSTATE_GFX_RESET_I830 (1 << 6) 3573 #define DSTATE_PLL_D3_OFF (1 << 3) 3574 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 3575 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 3576 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 3577 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 3578 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 3579 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 3580 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 3581 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 3582 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 3583 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 3584 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 3585 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 3586 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 3587 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 3588 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 3589 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 3590 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 3591 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 3592 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 3593 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 3594 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 3595 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 3596 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 3597 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 3598 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 3599 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3600 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 3601 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 3602 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 3603 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 3604 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 3605 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 3606 /* 3607 * This bit must be set on the 830 to prevent hangs when turning off the 3608 * overlay scaler. 3609 */ 3610 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 3611 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 3612 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 3613 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 3614 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 3615 3616 #define RENCLK_GATE_D1 _MMIO(0x6204) 3617 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 3618 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 3619 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 3620 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 3621 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 3622 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 3623 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 3624 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 3625 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 3626 /* This bit must be unset on 855,865 */ 3627 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 3628 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 3629 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 3630 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 3631 /* This bit must be set on 855,865. */ 3632 # define SV_CLOCK_GATE_DISABLE (1 << 0) 3633 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 3634 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 3635 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 3636 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 3637 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 3638 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 3639 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 3640 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 3641 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 3642 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 3643 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 3644 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 3645 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 3646 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 3647 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 3648 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 3649 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 3650 3651 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 3652 /* This bit must always be set on 965G/965GM */ 3653 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 3654 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 3655 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 3656 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 3657 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 3658 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 3659 /* This bit must always be set on 965G */ 3660 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 3661 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 3662 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 3663 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 3664 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 3665 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 3666 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 3667 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 3668 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 3669 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 3670 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 3671 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 3672 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 3673 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 3674 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 3675 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 3676 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 3677 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 3678 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 3679 3680 #define RENCLK_GATE_D2 _MMIO(0x6208) 3681 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 3682 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 3683 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 3684 3685 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 3686 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 3687 3688 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 3689 #define DEUC _MMIO(0x6214) /* CRL only */ 3690 3691 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 3692 #define FW_CSPWRDWNEN (1 << 15) 3693 3694 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 3695 3696 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 3697 #define CDCLK_FREQ_SHIFT 4 3698 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 3699 #define CZCLK_FREQ_MASK 0xf 3700 3701 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 3702 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 3703 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 3704 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 3705 #define PFI_CREDIT_RESEND (1 << 27) 3706 #define VGA_FAST_MODE_DISABLE (1 << 14) 3707 3708 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 3709 3710 /* 3711 * Palette regs 3712 */ 3713 #define _PALETTE_A 0xa000 3714 #define _PALETTE_B 0xa800 3715 #define _CHV_PALETTE_C 0xc000 3716 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 3717 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 3718 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 3719 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 3720 _PICK((pipe), _PALETTE_A, \ 3721 _PALETTE_B, _CHV_PALETTE_C) + \ 3722 (i) * 4) 3723 3724 /* MCH MMIO space */ 3725 3726 /* 3727 * MCHBAR mirror. 3728 * 3729 * This mirrors the MCHBAR MMIO space whose location is determined by 3730 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 3731 * every way. It is not accessible from the CP register read instructions. 3732 * 3733 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 3734 * just read. 3735 */ 3736 #define MCHBAR_MIRROR_BASE 0x10000 3737 3738 #define MCHBAR_MIRROR_BASE_SNB 0x140000 3739 3740 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 3741 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 3742 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 3743 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 3744 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0) 3745 3746 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 3747 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 3748 3749 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 3750 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 3751 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 3752 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 3753 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 3754 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 3755 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 3756 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 3757 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 3758 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 3759 3760 /* Pineview MCH register contains DDR3 setting */ 3761 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 3762 #define CSHRDDR3CTL_DDR3 (1 << 2) 3763 3764 /* 965 MCH register controlling DRAM channel configuration */ 3765 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 3766 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 3767 3768 /* snb MCH registers for reading the DRAM channel configuration */ 3769 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 3770 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 3771 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 3772 #define MAD_DIMM_ECC_MASK (0x3 << 24) 3773 #define MAD_DIMM_ECC_OFF (0x0 << 24) 3774 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 3775 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 3776 #define MAD_DIMM_ECC_ON (0x3 << 24) 3777 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 3778 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 3779 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 3780 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 3781 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 3782 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 3783 #define MAD_DIMM_A_SELECT (0x1 << 16) 3784 /* DIMM sizes are in multiples of 256mb. */ 3785 #define MAD_DIMM_B_SIZE_SHIFT 8 3786 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 3787 #define MAD_DIMM_A_SIZE_SHIFT 0 3788 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 3789 3790 /* snb MCH registers for priority tuning */ 3791 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 3792 #define MCH_SSKPD_WM0_MASK 0x3f 3793 #define MCH_SSKPD_WM0_VAL 0xc 3794 3795 /* Clocking configuration register */ 3796 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 3797 #define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ 3798 #define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */ 3799 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 3800 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 3801 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 3802 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 3803 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 3804 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 3805 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 3806 #define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */ 3807 #define CLKCFG_FSB_MASK (7 << 0) 3808 #define CLKCFG_MEM_533 (1 << 4) 3809 #define CLKCFG_MEM_667 (2 << 4) 3810 #define CLKCFG_MEM_800 (3 << 4) 3811 #define CLKCFG_MEM_MASK (7 << 4) 3812 3813 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 3814 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 3815 3816 #define TSC1 _MMIO(0x11001) 3817 #define TSE (1 << 0) 3818 #define TR1 _MMIO(0x11006) 3819 #define TSFS _MMIO(0x11020) 3820 #define TSFS_SLOPE_MASK 0x0000ff00 3821 #define TSFS_SLOPE_SHIFT 8 3822 #define TSFS_INTR_MASK 0x000000ff 3823 3824 #define CRSTANDVID _MMIO(0x11100) 3825 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 3826 #define PXVFREQ_PX_MASK 0x7f000000 3827 #define PXVFREQ_PX_SHIFT 24 3828 #define VIDFREQ_BASE _MMIO(0x11110) 3829 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 3830 #define VIDFREQ2 _MMIO(0x11114) 3831 #define VIDFREQ3 _MMIO(0x11118) 3832 #define VIDFREQ4 _MMIO(0x1111c) 3833 #define VIDFREQ_P0_MASK 0x1f000000 3834 #define VIDFREQ_P0_SHIFT 24 3835 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 3836 #define VIDFREQ_P0_CSCLK_SHIFT 20 3837 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 3838 #define VIDFREQ_P0_CRCLK_SHIFT 16 3839 #define VIDFREQ_P1_MASK 0x00001f00 3840 #define VIDFREQ_P1_SHIFT 8 3841 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 3842 #define VIDFREQ_P1_CSCLK_SHIFT 4 3843 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 3844 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 3845 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 3846 #define INTTOEXT_MAP3_SHIFT 24 3847 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 3848 #define INTTOEXT_MAP2_SHIFT 16 3849 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 3850 #define INTTOEXT_MAP1_SHIFT 8 3851 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 3852 #define INTTOEXT_MAP0_SHIFT 0 3853 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 3854 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 3855 #define MEMCTL_CMD_MASK 0xe000 3856 #define MEMCTL_CMD_SHIFT 13 3857 #define MEMCTL_CMD_RCLK_OFF 0 3858 #define MEMCTL_CMD_RCLK_ON 1 3859 #define MEMCTL_CMD_CHFREQ 2 3860 #define MEMCTL_CMD_CHVID 3 3861 #define MEMCTL_CMD_VMMOFF 4 3862 #define MEMCTL_CMD_VMMON 5 3863 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears 3864 when command complete */ 3865 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 3866 #define MEMCTL_FREQ_SHIFT 8 3867 #define MEMCTL_SFCAVM (1 << 7) 3868 #define MEMCTL_TGT_VID_MASK 0x007f 3869 #define MEMIHYST _MMIO(0x1117c) 3870 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 3871 #define MEMINT_RSEXIT_EN (1 << 8) 3872 #define MEMINT_CX_SUPR_EN (1 << 7) 3873 #define MEMINT_CONT_BUSY_EN (1 << 6) 3874 #define MEMINT_AVG_BUSY_EN (1 << 5) 3875 #define MEMINT_EVAL_CHG_EN (1 << 4) 3876 #define MEMINT_MON_IDLE_EN (1 << 3) 3877 #define MEMINT_UP_EVAL_EN (1 << 2) 3878 #define MEMINT_DOWN_EVAL_EN (1 << 1) 3879 #define MEMINT_SW_CMD_EN (1 << 0) 3880 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 3881 #define MEM_RSEXIT_MASK 0xc000 3882 #define MEM_RSEXIT_SHIFT 14 3883 #define MEM_CONT_BUSY_MASK 0x3000 3884 #define MEM_CONT_BUSY_SHIFT 12 3885 #define MEM_AVG_BUSY_MASK 0x0c00 3886 #define MEM_AVG_BUSY_SHIFT 10 3887 #define MEM_EVAL_CHG_MASK 0x0300 3888 #define MEM_EVAL_BUSY_SHIFT 8 3889 #define MEM_MON_IDLE_MASK 0x00c0 3890 #define MEM_MON_IDLE_SHIFT 6 3891 #define MEM_UP_EVAL_MASK 0x0030 3892 #define MEM_UP_EVAL_SHIFT 4 3893 #define MEM_DOWN_EVAL_MASK 0x000c 3894 #define MEM_DOWN_EVAL_SHIFT 2 3895 #define MEM_SW_CMD_MASK 0x0003 3896 #define MEM_INT_STEER_GFX 0 3897 #define MEM_INT_STEER_CMR 1 3898 #define MEM_INT_STEER_SMI 2 3899 #define MEM_INT_STEER_SCI 3 3900 #define MEMINTRSTS _MMIO(0x11184) 3901 #define MEMINT_RSEXIT (1 << 7) 3902 #define MEMINT_CONT_BUSY (1 << 6) 3903 #define MEMINT_AVG_BUSY (1 << 5) 3904 #define MEMINT_EVAL_CHG (1 << 4) 3905 #define MEMINT_MON_IDLE (1 << 3) 3906 #define MEMINT_UP_EVAL (1 << 2) 3907 #define MEMINT_DOWN_EVAL (1 << 1) 3908 #define MEMINT_SW_CMD (1 << 0) 3909 #define MEMMODECTL _MMIO(0x11190) 3910 #define MEMMODE_BOOST_EN (1 << 31) 3911 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 3912 #define MEMMODE_BOOST_FREQ_SHIFT 24 3913 #define MEMMODE_IDLE_MODE_MASK 0x00030000 3914 #define MEMMODE_IDLE_MODE_SHIFT 16 3915 #define MEMMODE_IDLE_MODE_EVAL 0 3916 #define MEMMODE_IDLE_MODE_CONT 1 3917 #define MEMMODE_HWIDLE_EN (1 << 15) 3918 #define MEMMODE_SWMODE_EN (1 << 14) 3919 #define MEMMODE_RCLK_GATE (1 << 13) 3920 #define MEMMODE_HW_UPDATE (1 << 12) 3921 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 3922 #define MEMMODE_FSTART_SHIFT 8 3923 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 3924 #define MEMMODE_FMAX_SHIFT 4 3925 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 3926 #define RCBMAXAVG _MMIO(0x1119c) 3927 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 3928 #define SWMEMCMD_RENDER_OFF (0 << 13) 3929 #define SWMEMCMD_RENDER_ON (1 << 13) 3930 #define SWMEMCMD_SWFREQ (2 << 13) 3931 #define SWMEMCMD_TARVID (3 << 13) 3932 #define SWMEMCMD_VRM_OFF (4 << 13) 3933 #define SWMEMCMD_VRM_ON (5 << 13) 3934 #define CMDSTS (1 << 12) 3935 #define SFCAVM (1 << 11) 3936 #define SWFREQ_MASK 0x0380 /* P0-7 */ 3937 #define SWFREQ_SHIFT 7 3938 #define TARVID_MASK 0x001f 3939 #define MEMSTAT_CTG _MMIO(0x111a0) 3940 #define RCBMINAVG _MMIO(0x111a0) 3941 #define RCUPEI _MMIO(0x111b0) 3942 #define RCDNEI _MMIO(0x111b4) 3943 #define RSTDBYCTL _MMIO(0x111b8) 3944 #define RS1EN (1 << 31) 3945 #define RS2EN (1 << 30) 3946 #define RS3EN (1 << 29) 3947 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ 3948 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ 3949 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ 3950 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ 3951 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ 3952 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ 3953 #define RSX_STATUS_MASK (7 << 20) 3954 #define RSX_STATUS_ON (0 << 20) 3955 #define RSX_STATUS_RC1 (1 << 20) 3956 #define RSX_STATUS_RC1E (2 << 20) 3957 #define RSX_STATUS_RS1 (3 << 20) 3958 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ 3959 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ 3960 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ 3961 #define RSX_STATUS_RSVD2 (7 << 20) 3962 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ 3963 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ 3964 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */ 3965 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ 3966 #define RS1CONTSAV_MASK (3 << 14) 3967 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ 3968 #define RS1CONTSAV_RSVD (1 << 14) 3969 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ 3970 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ 3971 #define NORMSLEXLAT_MASK (3 << 12) 3972 #define SLOW_RS123 (0 << 12) 3973 #define SLOW_RS23 (1 << 12) 3974 #define SLOW_RS3 (2 << 12) 3975 #define NORMAL_RS123 (3 << 12) 3976 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ 3977 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 3978 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ 3979 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ 3980 #define RS_CSTATE_MASK (3 << 4) 3981 #define RS_CSTATE_C367_RS1 (0 << 4) 3982 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) 3983 #define RS_CSTATE_RSVD (2 << 4) 3984 #define RS_CSTATE_C367_RS2 (3 << 4) 3985 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ 3986 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ 3987 #define VIDCTL _MMIO(0x111c0) 3988 #define VIDSTS _MMIO(0x111c8) 3989 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 3990 #define MEMSTAT_ILK _MMIO(0x111f8) 3991 #define MEMSTAT_VID_MASK 0x7f00 3992 #define MEMSTAT_VID_SHIFT 8 3993 #define MEMSTAT_PSTATE_MASK 0x00f8 3994 #define MEMSTAT_PSTATE_SHIFT 3 3995 #define MEMSTAT_MON_ACTV (1 << 2) 3996 #define MEMSTAT_SRC_CTL_MASK 0x0003 3997 #define MEMSTAT_SRC_CTL_CORE 0 3998 #define MEMSTAT_SRC_CTL_TRB 1 3999 #define MEMSTAT_SRC_CTL_THM 2 4000 #define MEMSTAT_SRC_CTL_STDBY 3 4001 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 4002 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 4003 #define PMMISC _MMIO(0x11214) 4004 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ 4005 #define SDEW _MMIO(0x1124c) 4006 #define CSIEW0 _MMIO(0x11250) 4007 #define CSIEW1 _MMIO(0x11254) 4008 #define CSIEW2 _MMIO(0x11258) 4009 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 4010 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 4011 #define MCHAFE _MMIO(0x112c0) 4012 #define CSIEC _MMIO(0x112e0) 4013 #define DMIEC _MMIO(0x112e4) 4014 #define DDREC _MMIO(0x112e8) 4015 #define PEG0EC _MMIO(0x112ec) 4016 #define PEG1EC _MMIO(0x112f0) 4017 #define GFXEC _MMIO(0x112f4) 4018 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 4019 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 4020 #define ECR _MMIO(0x11600) 4021 #define ECR_GPFE (1 << 31) 4022 #define ECR_IMONE (1 << 30) 4023 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 4024 #define OGW0 _MMIO(0x11608) 4025 #define OGW1 _MMIO(0x1160c) 4026 #define EG0 _MMIO(0x11610) 4027 #define EG1 _MMIO(0x11614) 4028 #define EG2 _MMIO(0x11618) 4029 #define EG3 _MMIO(0x1161c) 4030 #define EG4 _MMIO(0x11620) 4031 #define EG5 _MMIO(0x11624) 4032 #define EG6 _MMIO(0x11628) 4033 #define EG7 _MMIO(0x1162c) 4034 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 4035 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 4036 #define LCFUSE02 _MMIO(0x116c0) 4037 #define LCFUSE_HIV_MASK 0x000000ff 4038 #define CSIPLL0 _MMIO(0x12c10) 4039 #define DDRMPLL1 _MMIO(0X12c20) 4040 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 4041 4042 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 4043 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 4044 4045 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 4046 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 4047 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 4048 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 4049 #define BXT_RP_STATE_CAP _MMIO(0x138170) 4050 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 4051 4052 /* 4053 * Logical Context regs 4054 */ 4055 #define CCID(base) _MMIO((base) + 0x180) 4056 #define CCID_EN BIT(0) 4057 #define CCID_EXTENDED_STATE_RESTORE BIT(2) 4058 #define CCID_EXTENDED_STATE_SAVE BIT(3) 4059 /* 4060 * Notes on SNB/IVB/VLV context size: 4061 * - Power context is saved elsewhere (LLC or stolen) 4062 * - Ring/execlist context is saved on SNB, not on IVB 4063 * - Extended context size already includes render context size 4064 * - We always need to follow the extended context size. 4065 * SNB BSpec has comments indicating that we should use the 4066 * render context size instead if execlists are disabled, but 4067 * based on empirical testing that's just nonsense. 4068 * - Pipelined/VF state is saved on SNB/IVB respectively 4069 * - GT1 size just indicates how much of render context 4070 * doesn't need saving on GT1 4071 */ 4072 #define CXT_SIZE _MMIO(0x21a0) 4073 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 4074 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 4075 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 4076 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 4077 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 4078 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 4079 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 4080 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 4081 #define GEN7_CXT_SIZE _MMIO(0x21a8) 4082 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 4083 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 4084 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 4085 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 4086 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 4087 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 4088 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 4089 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 4090 4091 enum { 4092 INTEL_ADVANCED_CONTEXT = 0, 4093 INTEL_LEGACY_32B_CONTEXT, 4094 INTEL_ADVANCED_AD_CONTEXT, 4095 INTEL_LEGACY_64B_CONTEXT 4096 }; 4097 4098 enum { 4099 FAULT_AND_HANG = 0, 4100 FAULT_AND_HALT, /* Debug only */ 4101 FAULT_AND_STREAM, 4102 FAULT_AND_CONTINUE /* Unsupported */ 4103 }; 4104 4105 #define GEN8_CTX_VALID (1 << 0) 4106 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) 4107 #define GEN8_CTX_FORCE_RESTORE (1 << 2) 4108 #define GEN8_CTX_L3LLC_COHERENT (1 << 5) 4109 #define GEN8_CTX_PRIVILEGE (1 << 8) 4110 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 4111 4112 #define GEN8_CTX_ID_SHIFT 32 4113 #define GEN8_CTX_ID_WIDTH 21 4114 #define GEN11_SW_CTX_ID_SHIFT 37 4115 #define GEN11_SW_CTX_ID_WIDTH 11 4116 #define GEN11_ENGINE_CLASS_SHIFT 61 4117 #define GEN11_ENGINE_CLASS_WIDTH 3 4118 #define GEN11_ENGINE_INSTANCE_SHIFT 48 4119 #define GEN11_ENGINE_INSTANCE_WIDTH 6 4120 4121 #define CHV_CLK_CTL1 _MMIO(0x101100) 4122 #define VLV_CLK_CTL2 _MMIO(0x101104) 4123 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 4124 4125 /* 4126 * Overlay regs 4127 */ 4128 4129 #define OVADD _MMIO(0x30000) 4130 #define DOVSTA _MMIO(0x30008) 4131 #define OC_BUF (0x3 << 20) 4132 #define OGAMC5 _MMIO(0x30010) 4133 #define OGAMC4 _MMIO(0x30014) 4134 #define OGAMC3 _MMIO(0x30018) 4135 #define OGAMC2 _MMIO(0x3001c) 4136 #define OGAMC1 _MMIO(0x30020) 4137 #define OGAMC0 _MMIO(0x30024) 4138 4139 /* 4140 * GEN9 clock gating regs 4141 */ 4142 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 4143 #define DARBF_GATING_DIS (1 << 27) 4144 #define PWM2_GATING_DIS (1 << 14) 4145 #define PWM1_GATING_DIS (1 << 13) 4146 4147 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 4148 #define TGL_VRH_GATING_DIS REG_BIT(31) 4149 4150 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 4151 #define BXT_GMBUS_GATING_DIS (1 << 14) 4152 4153 #define _CLKGATE_DIS_PSL_A 0x46520 4154 #define _CLKGATE_DIS_PSL_B 0x46524 4155 #define _CLKGATE_DIS_PSL_C 0x46528 4156 #define DUPS1_GATING_DIS (1 << 15) 4157 #define DUPS2_GATING_DIS (1 << 19) 4158 #define DUPS3_GATING_DIS (1 << 23) 4159 #define DPF_GATING_DIS (1 << 10) 4160 #define DPF_RAM_GATING_DIS (1 << 9) 4161 #define DPFR_GATING_DIS (1 << 8) 4162 4163 #define CLKGATE_DIS_PSL(pipe) \ 4164 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 4165 4166 /* 4167 * GEN10 clock gating regs 4168 */ 4169 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 4170 #define SARBUNIT_CLKGATE_DIS (1 << 5) 4171 #define RCCUNIT_CLKGATE_DIS (1 << 7) 4172 #define MSCUNIT_CLKGATE_DIS (1 << 10) 4173 #define L3_CLKGATE_DIS REG_BIT(16) 4174 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 4175 4176 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) 4177 #define GWUNIT_CLKGATE_DIS (1 << 16) 4178 4179 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528) 4180 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 4181 4182 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 4183 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 4184 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 4185 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 4186 4187 #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) 4188 #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) 4189 #define PSDUNIT_CLKGATE_DIS REG_BIT(5) 4190 4191 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) 4192 #define CGPSF_CLKGATE_DIS (1 << 3) 4193 4194 /* 4195 * Display engine regs 4196 */ 4197 4198 /* Pipe A CRC regs */ 4199 #define _PIPE_CRC_CTL_A 0x60050 4200 #define PIPE_CRC_ENABLE (1 << 31) 4201 /* skl+ source selection */ 4202 #define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28) 4203 #define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28) 4204 #define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28) 4205 #define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28) 4206 #define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28) 4207 #define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28) 4208 #define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28) 4209 #define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28) 4210 /* ivb+ source selection */ 4211 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 4212 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 4213 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 4214 /* ilk+ source selection */ 4215 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 4216 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 4217 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 4218 /* embedded DP port on the north display block, reserved on ivb */ 4219 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 4220 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 4221 /* vlv source selection */ 4222 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 4223 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 4224 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 4225 /* with DP port the pipe source is invalid */ 4226 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 4227 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 4228 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 4229 /* gen3+ source selection */ 4230 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 4231 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 4232 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 4233 /* with DP/TV port the pipe source is invalid */ 4234 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 4235 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 4236 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 4237 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 4238 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 4239 /* gen2 doesn't have source selection bits */ 4240 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 4241 4242 #define _PIPE_CRC_RES_1_A_IVB 0x60064 4243 #define _PIPE_CRC_RES_2_A_IVB 0x60068 4244 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 4245 #define _PIPE_CRC_RES_4_A_IVB 0x60070 4246 #define _PIPE_CRC_RES_5_A_IVB 0x60074 4247 4248 #define _PIPE_CRC_RES_RED_A 0x60060 4249 #define _PIPE_CRC_RES_GREEN_A 0x60064 4250 #define _PIPE_CRC_RES_BLUE_A 0x60068 4251 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 4252 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 4253 4254 /* Pipe B CRC regs */ 4255 #define _PIPE_CRC_RES_1_B_IVB 0x61064 4256 #define _PIPE_CRC_RES_2_B_IVB 0x61068 4257 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 4258 #define _PIPE_CRC_RES_4_B_IVB 0x61070 4259 #define _PIPE_CRC_RES_5_B_IVB 0x61074 4260 4261 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 4262 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 4263 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 4264 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 4265 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 4266 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 4267 4268 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 4269 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 4270 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 4271 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 4272 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 4273 4274 /* Pipe A timing regs */ 4275 #define _HTOTAL_A 0x60000 4276 #define _HBLANK_A 0x60004 4277 #define _HSYNC_A 0x60008 4278 #define _VTOTAL_A 0x6000c 4279 #define _VBLANK_A 0x60010 4280 #define _VSYNC_A 0x60014 4281 #define _EXITLINE_A 0x60018 4282 #define _PIPEASRC 0x6001c 4283 #define _BCLRPAT_A 0x60020 4284 #define _VSYNCSHIFT_A 0x60028 4285 #define _PIPE_MULT_A 0x6002c 4286 4287 /* Pipe B timing regs */ 4288 #define _HTOTAL_B 0x61000 4289 #define _HBLANK_B 0x61004 4290 #define _HSYNC_B 0x61008 4291 #define _VTOTAL_B 0x6100c 4292 #define _VBLANK_B 0x61010 4293 #define _VSYNC_B 0x61014 4294 #define _PIPEBSRC 0x6101c 4295 #define _BCLRPAT_B 0x61020 4296 #define _VSYNCSHIFT_B 0x61028 4297 #define _PIPE_MULT_B 0x6102c 4298 4299 /* DSI 0 timing regs */ 4300 #define _HTOTAL_DSI0 0x6b000 4301 #define _HSYNC_DSI0 0x6b008 4302 #define _VTOTAL_DSI0 0x6b00c 4303 #define _VSYNC_DSI0 0x6b014 4304 #define _VSYNCSHIFT_DSI0 0x6b028 4305 4306 /* DSI 1 timing regs */ 4307 #define _HTOTAL_DSI1 0x6b800 4308 #define _HSYNC_DSI1 0x6b808 4309 #define _VTOTAL_DSI1 0x6b80c 4310 #define _VSYNC_DSI1 0x6b814 4311 #define _VSYNCSHIFT_DSI1 0x6b828 4312 4313 #define TRANSCODER_A_OFFSET 0x60000 4314 #define TRANSCODER_B_OFFSET 0x61000 4315 #define TRANSCODER_C_OFFSET 0x62000 4316 #define CHV_TRANSCODER_C_OFFSET 0x63000 4317 #define TRANSCODER_D_OFFSET 0x63000 4318 #define TRANSCODER_EDP_OFFSET 0x6f000 4319 #define TRANSCODER_DSI0_OFFSET 0x6b000 4320 #define TRANSCODER_DSI1_OFFSET 0x6b800 4321 4322 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 4323 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 4324 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 4325 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 4326 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 4327 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 4328 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 4329 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 4330 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 4331 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 4332 4333 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 4334 #define EXITLINE_ENABLE REG_BIT(31) 4335 #define EXITLINE_MASK REG_GENMASK(12, 0) 4336 #define EXITLINE_SHIFT 0 4337 4338 /* VRR registers */ 4339 #define _TRANS_VRR_CTL_A 0x60420 4340 #define _TRANS_VRR_CTL_B 0x61420 4341 #define _TRANS_VRR_CTL_C 0x62420 4342 #define _TRANS_VRR_CTL_D 0x63420 4343 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 4344 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 4345 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 4346 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 4347 #define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3) 4348 #define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0) 4349 4350 #define _TRANS_VRR_VMAX_A 0x60424 4351 #define _TRANS_VRR_VMAX_B 0x61424 4352 #define _TRANS_VRR_VMAX_C 0x62424 4353 #define _TRANS_VRR_VMAX_D 0x63424 4354 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 4355 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 4356 4357 #define _TRANS_VRR_VMIN_A 0x60434 4358 #define _TRANS_VRR_VMIN_B 0x61434 4359 #define _TRANS_VRR_VMIN_C 0x62434 4360 #define _TRANS_VRR_VMIN_D 0x63434 4361 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 4362 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 4363 4364 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 4365 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 4366 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 4367 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 4368 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 4369 _TRANS_VRR_VMAXSHIFT_A) 4370 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 4371 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 4372 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 4373 4374 #define _TRANS_VRR_STATUS_A 0x6042C 4375 #define _TRANS_VRR_STATUS_B 0x6142C 4376 #define _TRANS_VRR_STATUS_C 0x6242C 4377 #define _TRANS_VRR_STATUS_D 0x6342C 4378 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 4379 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 4380 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 4381 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 4382 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 4383 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 4384 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 4385 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 4386 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 4387 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 4388 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 4389 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 4390 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 4391 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 4392 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 4393 4394 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 4395 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 4396 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 4397 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 4398 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 4399 _TRANS_VRR_VTOTAL_PREV_A) 4400 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 4401 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 4402 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 4403 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 4404 4405 #define _TRANS_VRR_FLIPLINE_A 0x60438 4406 #define _TRANS_VRR_FLIPLINE_B 0x61438 4407 #define _TRANS_VRR_FLIPLINE_C 0x62438 4408 #define _TRANS_VRR_FLIPLINE_D 0x63438 4409 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 4410 _TRANS_VRR_FLIPLINE_A) 4411 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 4412 4413 #define _TRANS_VRR_STATUS2_A 0x6043C 4414 #define _TRANS_VRR_STATUS2_B 0x6143C 4415 #define _TRANS_VRR_STATUS2_C 0x6243C 4416 #define _TRANS_VRR_STATUS2_D 0x6343C 4417 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 4418 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 4419 4420 #define _TRANS_PUSH_A 0x60A70 4421 #define _TRANS_PUSH_B 0x61A70 4422 #define _TRANS_PUSH_C 0x62A70 4423 #define _TRANS_PUSH_D 0x63A70 4424 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 4425 #define TRANS_PUSH_EN REG_BIT(31) 4426 #define TRANS_PUSH_SEND REG_BIT(30) 4427 4428 /* 4429 * HSW+ eDP PSR registers 4430 * 4431 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 4432 * instance of it 4433 */ 4434 #define _HSW_EDP_PSR_BASE 0x64800 4435 #define _SRD_CTL_A 0x60800 4436 #define _SRD_CTL_EDP 0x6f800 4437 #define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust) 4438 #define EDP_PSR_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A)) 4439 #define EDP_PSR_ENABLE (1 << 31) 4440 #define BDW_PSR_SINGLE_FRAME (1 << 30) 4441 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 4442 #define EDP_PSR_LINK_STANDBY (1 << 27) 4443 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 4444 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 4445 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 4446 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 4447 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 4448 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 4449 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 4450 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 4451 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 4452 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 4453 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 4454 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 4455 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 4456 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 4457 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 4458 #define EDP_PSR_TP1_TIME_500us (0 << 4) 4459 #define EDP_PSR_TP1_TIME_100us (1 << 4) 4460 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 4461 #define EDP_PSR_TP1_TIME_0us (3 << 4) 4462 #define EDP_PSR_IDLE_FRAME_SHIFT 0 4463 4464 /* 4465 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 4466 * to transcoder and bits defined for each one as if using no shift (i.e. as if 4467 * it was for TRANSCODER_EDP) 4468 */ 4469 #define EDP_PSR_IMR _MMIO(0x64834) 4470 #define EDP_PSR_IIR _MMIO(0x64838) 4471 #define _PSR_IMR_A 0x60814 4472 #define _PSR_IIR_A 0x60818 4473 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 4474 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 4475 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 4476 0 : ((trans) - TRANSCODER_A + 1) * 8) 4477 #define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) 4478 #define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) 4479 #define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) 4480 #define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) 4481 4482 #define _SRD_AUX_CTL_A 0x60810 4483 #define _SRD_AUX_CTL_EDP 0x6f810 4484 #define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A)) 4485 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) 4486 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4487 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 4488 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11) 4489 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4490 4491 #define _SRD_AUX_DATA_A 0x60814 4492 #define _SRD_AUX_DATA_EDP 0x6f814 4493 #define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */ 4494 4495 #define _SRD_STATUS_A 0x60840 4496 #define _SRD_STATUS_EDP 0x6f840 4497 #define EDP_PSR_STATUS(tran) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A)) 4498 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 4499 #define EDP_PSR_STATUS_STATE_SHIFT 29 4500 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 4501 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 4502 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 4503 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 4504 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 4505 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 4506 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 4507 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 4508 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 4509 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 4510 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 4511 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 4512 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 4513 #define EDP_PSR_STATUS_COUNT_SHIFT 16 4514 #define EDP_PSR_STATUS_COUNT_MASK 0xf 4515 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 4516 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 4517 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 4518 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 4519 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 4520 #define EDP_PSR_STATUS_IDLE_MASK 0xf 4521 4522 #define _SRD_PERF_CNT_A 0x60844 4523 #define _SRD_PERF_CNT_EDP 0x6f844 4524 #define EDP_PSR_PERF_CNT(tran) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A)) 4525 #define EDP_PSR_PERF_CNT_MASK 0xffffff 4526 4527 /* PSR_MASK on SKL+ */ 4528 #define _SRD_DEBUG_A 0x60860 4529 #define _SRD_DEBUG_EDP 0x6f860 4530 #define EDP_PSR_DEBUG(tran) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A)) 4531 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 4532 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 4533 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 4534 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 4535 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 4536 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 4537 4538 #define _PSR2_CTL_A 0x60900 4539 #define _PSR2_CTL_EDP 0x6f900 4540 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 4541 #define EDP_PSR2_ENABLE (1 << 31) 4542 #define EDP_SU_TRACK_ENABLE (1 << 30) 4543 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 4544 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 4545 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ 4546 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ 4547 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 4548 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 4549 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 4550 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 4551 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 4552 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 4553 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) 4554 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 4555 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 4556 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 4557 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 4558 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 4559 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) 4560 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 4561 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 4562 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 4563 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 4564 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 4565 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 4566 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 4567 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 4568 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 4569 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 4570 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 4571 4572 #define _PSR_EVENT_TRANS_A 0x60848 4573 #define _PSR_EVENT_TRANS_B 0x61848 4574 #define _PSR_EVENT_TRANS_C 0x62848 4575 #define _PSR_EVENT_TRANS_D 0x63848 4576 #define _PSR_EVENT_TRANS_EDP 0x6f848 4577 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 4578 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 4579 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 4580 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 4581 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 4582 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 4583 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 4584 #define PSR_EVENT_MEMORY_UP (1 << 10) 4585 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 4586 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 4587 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 4588 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 4589 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 4590 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 4591 #define PSR_EVENT_VBI_ENABLE (1 << 2) 4592 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 4593 #define PSR_EVENT_PSR_DISABLE (1 << 0) 4594 4595 #define _PSR2_STATUS_A 0x60940 4596 #define _PSR2_STATUS_EDP 0x6f940 4597 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 4598 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) 4599 #define EDP_PSR2_STATUS_STATE_SHIFT 28 4600 4601 #define _PSR2_SU_STATUS_A 0x60914 4602 #define _PSR2_SU_STATUS_EDP 0x6f914 4603 #define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4) 4604 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 4605 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 4606 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 4607 #define PSR2_SU_STATUS_FRAMES 8 4608 4609 #define _PSR2_MAN_TRK_CTL_A 0x60910 4610 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 4611 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 4612 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 4613 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 4614 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 4615 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 4616 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 4617 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 4618 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 4619 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 4620 4621 /* VGA port control */ 4622 #define ADPA _MMIO(0x61100) 4623 #define PCH_ADPA _MMIO(0xe1100) 4624 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 4625 4626 #define ADPA_DAC_ENABLE (1 << 31) 4627 #define ADPA_DAC_DISABLE 0 4628 #define ADPA_PIPE_SEL_SHIFT 30 4629 #define ADPA_PIPE_SEL_MASK (1 << 30) 4630 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 4631 #define ADPA_PIPE_SEL_SHIFT_CPT 29 4632 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 4633 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4634 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 4635 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 4636 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 4637 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 4638 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 4639 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 4640 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 4641 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 4642 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 4643 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 4644 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 4645 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 4646 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 4647 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 4648 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 4649 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 4650 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 4651 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 4652 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 4653 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 4654 #define ADPA_SETS_HVPOLARITY 0 4655 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 4656 #define ADPA_VSYNC_CNTL_ENABLE 0 4657 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 4658 #define ADPA_HSYNC_CNTL_ENABLE 0 4659 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 4660 #define ADPA_VSYNC_ACTIVE_LOW 0 4661 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 4662 #define ADPA_HSYNC_ACTIVE_LOW 0 4663 #define ADPA_DPMS_MASK (~(3 << 10)) 4664 #define ADPA_DPMS_ON (0 << 10) 4665 #define ADPA_DPMS_SUSPEND (1 << 10) 4666 #define ADPA_DPMS_STANDBY (2 << 10) 4667 #define ADPA_DPMS_OFF (3 << 10) 4668 4669 4670 /* Hotplug control (945+ only) */ 4671 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 4672 #define PORTB_HOTPLUG_INT_EN (1 << 29) 4673 #define PORTC_HOTPLUG_INT_EN (1 << 28) 4674 #define PORTD_HOTPLUG_INT_EN (1 << 27) 4675 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 4676 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 4677 #define TV_HOTPLUG_INT_EN (1 << 18) 4678 #define CRT_HOTPLUG_INT_EN (1 << 9) 4679 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 4680 PORTC_HOTPLUG_INT_EN | \ 4681 PORTD_HOTPLUG_INT_EN | \ 4682 SDVOC_HOTPLUG_INT_EN | \ 4683 SDVOB_HOTPLUG_INT_EN | \ 4684 CRT_HOTPLUG_INT_EN) 4685 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 4686 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 4687 /* must use period 64 on GM45 according to docs */ 4688 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 4689 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 4690 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 4691 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 4692 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 4693 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 4694 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 4695 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 4696 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 4697 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 4698 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 4699 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 4700 4701 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 4702 /* 4703 * HDMI/DP bits are g4x+ 4704 * 4705 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 4706 * Please check the detailed lore in the commit message for for experimental 4707 * evidence. 4708 */ 4709 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 4710 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 4711 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 4712 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 4713 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 4714 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 4715 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 4716 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 4717 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 4718 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 4719 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 4720 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 4721 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 4722 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 4723 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 4724 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 4725 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 4726 /* CRT/TV common between gen3+ */ 4727 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 4728 #define TV_HOTPLUG_INT_STATUS (1 << 10) 4729 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 4730 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 4731 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 4732 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 4733 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 4734 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 4735 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 4736 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 4737 4738 /* SDVO is different across gen3/4 */ 4739 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 4740 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 4741 /* 4742 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 4743 * since reality corrobates that they're the same as on gen3. But keep these 4744 * bits here (and the comment!) to help any other lost wanderers back onto the 4745 * right tracks. 4746 */ 4747 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 4748 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 4749 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 4750 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 4751 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 4752 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 4753 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 4754 PORTB_HOTPLUG_INT_STATUS | \ 4755 PORTC_HOTPLUG_INT_STATUS | \ 4756 PORTD_HOTPLUG_INT_STATUS) 4757 4758 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 4759 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 4760 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 4761 PORTB_HOTPLUG_INT_STATUS | \ 4762 PORTC_HOTPLUG_INT_STATUS | \ 4763 PORTD_HOTPLUG_INT_STATUS) 4764 4765 /* SDVO and HDMI port control. 4766 * The same register may be used for SDVO or HDMI */ 4767 #define _GEN3_SDVOB 0x61140 4768 #define _GEN3_SDVOC 0x61160 4769 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 4770 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 4771 #define GEN4_HDMIB GEN3_SDVOB 4772 #define GEN4_HDMIC GEN3_SDVOC 4773 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 4774 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 4775 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 4776 #define PCH_SDVOB _MMIO(0xe1140) 4777 #define PCH_HDMIB PCH_SDVOB 4778 #define PCH_HDMIC _MMIO(0xe1150) 4779 #define PCH_HDMID _MMIO(0xe1160) 4780 4781 #define PORT_DFT_I9XX _MMIO(0x61150) 4782 #define DC_BALANCE_RESET (1 << 25) 4783 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 4784 #define DC_BALANCE_RESET_VLV (1 << 31) 4785 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 4786 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 4787 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 4788 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 4789 4790 /* Gen 3 SDVO bits: */ 4791 #define SDVO_ENABLE (1 << 31) 4792 #define SDVO_PIPE_SEL_SHIFT 30 4793 #define SDVO_PIPE_SEL_MASK (1 << 30) 4794 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 4795 #define SDVO_STALL_SELECT (1 << 29) 4796 #define SDVO_INTERRUPT_ENABLE (1 << 26) 4797 /* 4798 * 915G/GM SDVO pixel multiplier. 4799 * Programmed value is multiplier - 1, up to 5x. 4800 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 4801 */ 4802 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 4803 #define SDVO_PORT_MULTIPLY_SHIFT 23 4804 #define SDVO_PHASE_SELECT_MASK (15 << 19) 4805 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 4806 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 4807 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 4808 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 4809 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 4810 #define SDVO_DETECTED (1 << 2) 4811 /* Bits to be preserved when writing */ 4812 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 4813 SDVO_INTERRUPT_ENABLE) 4814 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 4815 4816 /* Gen 4 SDVO/HDMI bits: */ 4817 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 4818 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 4819 #define SDVO_ENCODING_SDVO (0 << 10) 4820 #define SDVO_ENCODING_HDMI (2 << 10) 4821 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 4822 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 4823 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 4824 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 4825 /* VSYNC/HSYNC bits new with 965, default is to be set */ 4826 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 4827 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 4828 4829 /* Gen 5 (IBX) SDVO/HDMI bits: */ 4830 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 4831 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 4832 4833 /* Gen 6 (CPT) SDVO/HDMI bits: */ 4834 #define SDVO_PIPE_SEL_SHIFT_CPT 29 4835 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 4836 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4837 4838 /* CHV SDVO/HDMI bits: */ 4839 #define SDVO_PIPE_SEL_SHIFT_CHV 24 4840 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 4841 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 4842 4843 4844 /* DVO port control */ 4845 #define _DVOA 0x61120 4846 #define DVOA _MMIO(_DVOA) 4847 #define _DVOB 0x61140 4848 #define DVOB _MMIO(_DVOB) 4849 #define _DVOC 0x61160 4850 #define DVOC _MMIO(_DVOC) 4851 #define DVO_ENABLE (1 << 31) 4852 #define DVO_PIPE_SEL_SHIFT 30 4853 #define DVO_PIPE_SEL_MASK (1 << 30) 4854 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 4855 #define DVO_PIPE_STALL_UNUSED (0 << 28) 4856 #define DVO_PIPE_STALL (1 << 28) 4857 #define DVO_PIPE_STALL_TV (2 << 28) 4858 #define DVO_PIPE_STALL_MASK (3 << 28) 4859 #define DVO_USE_VGA_SYNC (1 << 15) 4860 #define DVO_DATA_ORDER_I740 (0 << 14) 4861 #define DVO_DATA_ORDER_FP (1 << 14) 4862 #define DVO_VSYNC_DISABLE (1 << 11) 4863 #define DVO_HSYNC_DISABLE (1 << 10) 4864 #define DVO_VSYNC_TRISTATE (1 << 9) 4865 #define DVO_HSYNC_TRISTATE (1 << 8) 4866 #define DVO_BORDER_ENABLE (1 << 7) 4867 #define DVO_DATA_ORDER_GBRG (1 << 6) 4868 #define DVO_DATA_ORDER_RGGB (0 << 6) 4869 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 4870 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 4871 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 4872 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 4873 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 4874 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 4875 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 4876 #define DVO_PRESERVE_MASK (0x7 << 24) 4877 #define DVOA_SRCDIM _MMIO(0x61124) 4878 #define DVOB_SRCDIM _MMIO(0x61144) 4879 #define DVOC_SRCDIM _MMIO(0x61164) 4880 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 4881 #define DVO_SRCDIM_VERTICAL_SHIFT 0 4882 4883 /* LVDS port control */ 4884 #define LVDS _MMIO(0x61180) 4885 /* 4886 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 4887 * the DPLL semantics change when the LVDS is assigned to that pipe. 4888 */ 4889 #define LVDS_PORT_EN (1 << 31) 4890 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 4891 #define LVDS_PIPE_SEL_SHIFT 30 4892 #define LVDS_PIPE_SEL_MASK (1 << 30) 4893 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 4894 #define LVDS_PIPE_SEL_SHIFT_CPT 29 4895 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 4896 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4897 /* LVDS dithering flag on 965/g4x platform */ 4898 #define LVDS_ENABLE_DITHER (1 << 25) 4899 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 4900 #define LVDS_VSYNC_POLARITY (1 << 21) 4901 #define LVDS_HSYNC_POLARITY (1 << 20) 4902 4903 /* Enable border for unscaled (or aspect-scaled) display */ 4904 #define LVDS_BORDER_ENABLE (1 << 15) 4905 /* 4906 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 4907 * pixel. 4908 */ 4909 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 4910 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 4911 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 4912 /* 4913 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 4914 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 4915 * on. 4916 */ 4917 #define LVDS_A3_POWER_MASK (3 << 6) 4918 #define LVDS_A3_POWER_DOWN (0 << 6) 4919 #define LVDS_A3_POWER_UP (3 << 6) 4920 /* 4921 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 4922 * is set. 4923 */ 4924 #define LVDS_CLKB_POWER_MASK (3 << 4) 4925 #define LVDS_CLKB_POWER_DOWN (0 << 4) 4926 #define LVDS_CLKB_POWER_UP (3 << 4) 4927 /* 4928 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 4929 * setting for whether we are in dual-channel mode. The B3 pair will 4930 * additionally only be powered up when LVDS_A3_POWER_UP is set. 4931 */ 4932 #define LVDS_B0B3_POWER_MASK (3 << 2) 4933 #define LVDS_B0B3_POWER_DOWN (0 << 2) 4934 #define LVDS_B0B3_POWER_UP (3 << 2) 4935 4936 /* Video Data Island Packet control */ 4937 #define VIDEO_DIP_DATA _MMIO(0x61178) 4938 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 4939 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 4940 * of the infoframe structure specified by CEA-861. */ 4941 #define VIDEO_DIP_DATA_SIZE 32 4942 #define VIDEO_DIP_GMP_DATA_SIZE 36 4943 #define VIDEO_DIP_VSC_DATA_SIZE 36 4944 #define VIDEO_DIP_PPS_DATA_SIZE 132 4945 #define VIDEO_DIP_CTL _MMIO(0x61170) 4946 /* Pre HSW: */ 4947 #define VIDEO_DIP_ENABLE (1 << 31) 4948 #define VIDEO_DIP_PORT(port) ((port) << 29) 4949 #define VIDEO_DIP_PORT_MASK (3 << 29) 4950 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 4951 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 4952 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 4953 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 4954 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 4955 #define VIDEO_DIP_SELECT_AVI (0 << 19) 4956 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 4957 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 4958 #define VIDEO_DIP_SELECT_SPD (3 << 19) 4959 #define VIDEO_DIP_SELECT_MASK (3 << 19) 4960 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 4961 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 4962 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4963 #define VIDEO_DIP_FREQ_MASK (3 << 16) 4964 /* HSW and later: */ 4965 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 4966 #define PSR_VSC_BIT_7_SET (1 << 27) 4967 #define VSC_SELECT_MASK (0x3 << 25) 4968 #define VSC_SELECT_SHIFT 25 4969 #define VSC_DIP_HW_HEA_DATA (0 << 25) 4970 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 4971 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 4972 #define VSC_DIP_SW_HEA_DATA (3 << 25) 4973 #define VDIP_ENABLE_PPS (1 << 24) 4974 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4975 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4976 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4977 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 4978 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4979 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4980 4981 /* Panel power sequencing */ 4982 #define PPS_BASE 0x61200 4983 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4984 #define PCH_PPS_BASE 0xC7200 4985 4986 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 4987 PPS_BASE + (reg) + \ 4988 (pps_idx) * 0x100) 4989 4990 #define _PP_STATUS 0x61200 4991 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 4992 #define PP_ON REG_BIT(31) 4993 /* 4994 * Indicates that all dependencies of the panel are on: 4995 * 4996 * - PLL enabled 4997 * - pipe enabled 4998 * - LVDS/DVOB/DVOC on 4999 */ 5000 #define PP_READY REG_BIT(30) 5001 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 5002 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 5003 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 5004 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 5005 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 5006 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 5007 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 5008 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 5009 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 5010 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 5011 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 5012 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 5013 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 5014 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 5015 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 5016 5017 #define _PP_CONTROL 0x61204 5018 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 5019 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 5020 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 5021 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 5022 #define EDP_FORCE_VDD REG_BIT(3) 5023 #define EDP_BLC_ENABLE REG_BIT(2) 5024 #define PANEL_POWER_RESET REG_BIT(1) 5025 #define PANEL_POWER_ON REG_BIT(0) 5026 5027 #define _PP_ON_DELAYS 0x61208 5028 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 5029 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 5030 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 5031 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 5032 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 5033 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 5034 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 5035 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 5036 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 5037 5038 #define _PP_OFF_DELAYS 0x6120C 5039 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 5040 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 5041 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 5042 5043 #define _PP_DIVISOR 0x61210 5044 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 5045 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 5046 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 5047 5048 /* Panel fitting */ 5049 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 5050 #define PFIT_ENABLE (1 << 31) 5051 #define PFIT_PIPE_MASK (3 << 29) 5052 #define PFIT_PIPE_SHIFT 29 5053 #define PFIT_PIPE(pipe) ((pipe) << 29) 5054 #define VERT_INTERP_DISABLE (0 << 10) 5055 #define VERT_INTERP_BILINEAR (1 << 10) 5056 #define VERT_INTERP_MASK (3 << 10) 5057 #define VERT_AUTO_SCALE (1 << 9) 5058 #define HORIZ_INTERP_DISABLE (0 << 6) 5059 #define HORIZ_INTERP_BILINEAR (1 << 6) 5060 #define HORIZ_INTERP_MASK (3 << 6) 5061 #define HORIZ_AUTO_SCALE (1 << 5) 5062 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 5063 #define PFIT_FILTER_FUZZY (0 << 24) 5064 #define PFIT_SCALING_AUTO (0 << 26) 5065 #define PFIT_SCALING_PROGRAMMED (1 << 26) 5066 #define PFIT_SCALING_PILLAR (2 << 26) 5067 #define PFIT_SCALING_LETTER (3 << 26) 5068 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 5069 /* Pre-965 */ 5070 #define PFIT_VERT_SCALE_SHIFT 20 5071 #define PFIT_VERT_SCALE_MASK 0xfff00000 5072 #define PFIT_HORIZ_SCALE_SHIFT 4 5073 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 5074 /* 965+ */ 5075 #define PFIT_VERT_SCALE_SHIFT_965 16 5076 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 5077 #define PFIT_HORIZ_SCALE_SHIFT_965 0 5078 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 5079 5080 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 5081 5082 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 5083 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 5084 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 5085 _VLV_BLC_PWM_CTL2_B) 5086 5087 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 5088 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 5089 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 5090 _VLV_BLC_PWM_CTL_B) 5091 5092 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 5093 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 5094 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 5095 _VLV_BLC_HIST_CTL_B) 5096 5097 /* Backlight control */ 5098 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 5099 #define BLM_PWM_ENABLE (1 << 31) 5100 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 5101 #define BLM_PIPE_SELECT (1 << 29) 5102 #define BLM_PIPE_SELECT_IVB (3 << 29) 5103 #define BLM_PIPE_A (0 << 29) 5104 #define BLM_PIPE_B (1 << 29) 5105 #define BLM_PIPE_C (2 << 29) /* ivb + */ 5106 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 5107 #define BLM_TRANSCODER_B BLM_PIPE_B 5108 #define BLM_TRANSCODER_C BLM_PIPE_C 5109 #define BLM_TRANSCODER_EDP (3 << 29) 5110 #define BLM_PIPE(pipe) ((pipe) << 29) 5111 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 5112 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 5113 #define BLM_PHASE_IN_ENABLE (1 << 25) 5114 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 5115 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 5116 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 5117 #define BLM_PHASE_IN_COUNT_SHIFT (8) 5118 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 5119 #define BLM_PHASE_IN_INCR_SHIFT (0) 5120 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 5121 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 5122 /* 5123 * This is the most significant 15 bits of the number of backlight cycles in a 5124 * complete cycle of the modulated backlight control. 5125 * 5126 * The actual value is this field multiplied by two. 5127 */ 5128 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 5129 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 5130 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 5131 /* 5132 * This is the number of cycles out of the backlight modulation cycle for which 5133 * the backlight is on. 5134 * 5135 * This field must be no greater than the number of cycles in the complete 5136 * backlight modulation cycle. 5137 */ 5138 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 5139 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 5140 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 5141 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 5142 5143 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 5144 #define BLM_HISTOGRAM_ENABLE (1 << 31) 5145 5146 /* New registers for PCH-split platforms. Safe where new bits show up, the 5147 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 5148 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 5149 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 5150 5151 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 5152 5153 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 5154 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 5155 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 5156 #define BLM_PCH_PWM_ENABLE (1 << 31) 5157 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 5158 #define BLM_PCH_POLARITY (1 << 29) 5159 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 5160 5161 #define UTIL_PIN_CTL _MMIO(0x48400) 5162 #define UTIL_PIN_ENABLE (1 << 31) 5163 #define UTIL_PIN_PIPE_MASK (3 << 29) 5164 #define UTIL_PIN_PIPE(x) ((x) << 29) 5165 #define UTIL_PIN_MODE_MASK (0xf << 24) 5166 #define UTIL_PIN_MODE_DATA (0 << 24) 5167 #define UTIL_PIN_MODE_PWM (1 << 24) 5168 #define UTIL_PIN_MODE_VBLANK (4 << 24) 5169 #define UTIL_PIN_MODE_VSYNC (5 << 24) 5170 #define UTIL_PIN_MODE_EYE_LEVEL (8 << 24) 5171 #define UTIL_PIN_OUTPUT_DATA (1 << 23) 5172 #define UTIL_PIN_POLARITY (1 << 22) 5173 #define UTIL_PIN_DIRECTION_INPUT (1 << 19) 5174 #define UTIL_PIN_INPUT_DATA (1 << 16) 5175 5176 /* BXT backlight register definition. */ 5177 #define _BXT_BLC_PWM_CTL1 0xC8250 5178 #define BXT_BLC_PWM_ENABLE (1 << 31) 5179 #define BXT_BLC_PWM_POLARITY (1 << 29) 5180 #define _BXT_BLC_PWM_FREQ1 0xC8254 5181 #define _BXT_BLC_PWM_DUTY1 0xC8258 5182 5183 #define _BXT_BLC_PWM_CTL2 0xC8350 5184 #define _BXT_BLC_PWM_FREQ2 0xC8354 5185 #define _BXT_BLC_PWM_DUTY2 0xC8358 5186 5187 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 5188 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 5189 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 5190 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 5191 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 5192 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 5193 5194 #define PCH_GTC_CTL _MMIO(0xe7000) 5195 #define PCH_GTC_ENABLE (1 << 31) 5196 5197 /* TV port control */ 5198 #define TV_CTL _MMIO(0x68000) 5199 /* Enables the TV encoder */ 5200 # define TV_ENC_ENABLE (1 << 31) 5201 /* Sources the TV encoder input from pipe B instead of A. */ 5202 # define TV_ENC_PIPE_SEL_SHIFT 30 5203 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 5204 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 5205 /* Outputs composite video (DAC A only) */ 5206 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 5207 /* Outputs SVideo video (DAC B/C) */ 5208 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 5209 /* Outputs Component video (DAC A/B/C) */ 5210 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 5211 /* Outputs Composite and SVideo (DAC A/B/C) */ 5212 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 5213 # define TV_TRILEVEL_SYNC (1 << 21) 5214 /* Enables slow sync generation (945GM only) */ 5215 # define TV_SLOW_SYNC (1 << 20) 5216 /* Selects 4x oversampling for 480i and 576p */ 5217 # define TV_OVERSAMPLE_4X (0 << 18) 5218 /* Selects 2x oversampling for 720p and 1080i */ 5219 # define TV_OVERSAMPLE_2X (1 << 18) 5220 /* Selects no oversampling for 1080p */ 5221 # define TV_OVERSAMPLE_NONE (2 << 18) 5222 /* Selects 8x oversampling */ 5223 # define TV_OVERSAMPLE_8X (3 << 18) 5224 # define TV_OVERSAMPLE_MASK (3 << 18) 5225 /* Selects progressive mode rather than interlaced */ 5226 # define TV_PROGRESSIVE (1 << 17) 5227 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 5228 # define TV_PAL_BURST (1 << 16) 5229 /* Field for setting delay of Y compared to C */ 5230 # define TV_YC_SKEW_MASK (7 << 12) 5231 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 5232 # define TV_ENC_SDP_FIX (1 << 11) 5233 /* 5234 * Enables a fix for the 915GM only. 5235 * 5236 * Not sure what it does. 5237 */ 5238 # define TV_ENC_C0_FIX (1 << 10) 5239 /* Bits that must be preserved by software */ 5240 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 5241 # define TV_FUSE_STATE_MASK (3 << 4) 5242 /* Read-only state that reports all features enabled */ 5243 # define TV_FUSE_STATE_ENABLED (0 << 4) 5244 /* Read-only state that reports that Macrovision is disabled in hardware*/ 5245 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 5246 /* Read-only state that reports that TV-out is disabled in hardware. */ 5247 # define TV_FUSE_STATE_DISABLED (2 << 4) 5248 /* Normal operation */ 5249 # define TV_TEST_MODE_NORMAL (0 << 0) 5250 /* Encoder test pattern 1 - combo pattern */ 5251 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 5252 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 5253 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 5254 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 5255 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 5256 /* Encoder test pattern 4 - random noise */ 5257 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 5258 /* Encoder test pattern 5 - linear color ramps */ 5259 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 5260 /* 5261 * This test mode forces the DACs to 50% of full output. 5262 * 5263 * This is used for load detection in combination with TVDAC_SENSE_MASK 5264 */ 5265 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 5266 # define TV_TEST_MODE_MASK (7 << 0) 5267 5268 #define TV_DAC _MMIO(0x68004) 5269 # define TV_DAC_SAVE 0x00ffff00 5270 /* 5271 * Reports that DAC state change logic has reported change (RO). 5272 * 5273 * This gets cleared when TV_DAC_STATE_EN is cleared 5274 */ 5275 # define TVDAC_STATE_CHG (1 << 31) 5276 # define TVDAC_SENSE_MASK (7 << 28) 5277 /* Reports that DAC A voltage is above the detect threshold */ 5278 # define TVDAC_A_SENSE (1 << 30) 5279 /* Reports that DAC B voltage is above the detect threshold */ 5280 # define TVDAC_B_SENSE (1 << 29) 5281 /* Reports that DAC C voltage is above the detect threshold */ 5282 # define TVDAC_C_SENSE (1 << 28) 5283 /* 5284 * Enables DAC state detection logic, for load-based TV detection. 5285 * 5286 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 5287 * to off, for load detection to work. 5288 */ 5289 # define TVDAC_STATE_CHG_EN (1 << 27) 5290 /* Sets the DAC A sense value to high */ 5291 # define TVDAC_A_SENSE_CTL (1 << 26) 5292 /* Sets the DAC B sense value to high */ 5293 # define TVDAC_B_SENSE_CTL (1 << 25) 5294 /* Sets the DAC C sense value to high */ 5295 # define TVDAC_C_SENSE_CTL (1 << 24) 5296 /* Overrides the ENC_ENABLE and DAC voltage levels */ 5297 # define DAC_CTL_OVERRIDE (1 << 7) 5298 /* Sets the slew rate. Must be preserved in software */ 5299 # define ENC_TVDAC_SLEW_FAST (1 << 6) 5300 # define DAC_A_1_3_V (0 << 4) 5301 # define DAC_A_1_1_V (1 << 4) 5302 # define DAC_A_0_7_V (2 << 4) 5303 # define DAC_A_MASK (3 << 4) 5304 # define DAC_B_1_3_V (0 << 2) 5305 # define DAC_B_1_1_V (1 << 2) 5306 # define DAC_B_0_7_V (2 << 2) 5307 # define DAC_B_MASK (3 << 2) 5308 # define DAC_C_1_3_V (0 << 0) 5309 # define DAC_C_1_1_V (1 << 0) 5310 # define DAC_C_0_7_V (2 << 0) 5311 # define DAC_C_MASK (3 << 0) 5312 5313 /* 5314 * CSC coefficients are stored in a floating point format with 9 bits of 5315 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 5316 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 5317 * -1 (0x3) being the only legal negative value. 5318 */ 5319 #define TV_CSC_Y _MMIO(0x68010) 5320 # define TV_RY_MASK 0x07ff0000 5321 # define TV_RY_SHIFT 16 5322 # define TV_GY_MASK 0x00000fff 5323 # define TV_GY_SHIFT 0 5324 5325 #define TV_CSC_Y2 _MMIO(0x68014) 5326 # define TV_BY_MASK 0x07ff0000 5327 # define TV_BY_SHIFT 16 5328 /* 5329 * Y attenuation for component video. 5330 * 5331 * Stored in 1.9 fixed point. 5332 */ 5333 # define TV_AY_MASK 0x000003ff 5334 # define TV_AY_SHIFT 0 5335 5336 #define TV_CSC_U _MMIO(0x68018) 5337 # define TV_RU_MASK 0x07ff0000 5338 # define TV_RU_SHIFT 16 5339 # define TV_GU_MASK 0x000007ff 5340 # define TV_GU_SHIFT 0 5341 5342 #define TV_CSC_U2 _MMIO(0x6801c) 5343 # define TV_BU_MASK 0x07ff0000 5344 # define TV_BU_SHIFT 16 5345 /* 5346 * U attenuation for component video. 5347 * 5348 * Stored in 1.9 fixed point. 5349 */ 5350 # define TV_AU_MASK 0x000003ff 5351 # define TV_AU_SHIFT 0 5352 5353 #define TV_CSC_V _MMIO(0x68020) 5354 # define TV_RV_MASK 0x0fff0000 5355 # define TV_RV_SHIFT 16 5356 # define TV_GV_MASK 0x000007ff 5357 # define TV_GV_SHIFT 0 5358 5359 #define TV_CSC_V2 _MMIO(0x68024) 5360 # define TV_BV_MASK 0x07ff0000 5361 # define TV_BV_SHIFT 16 5362 /* 5363 * V attenuation for component video. 5364 * 5365 * Stored in 1.9 fixed point. 5366 */ 5367 # define TV_AV_MASK 0x000007ff 5368 # define TV_AV_SHIFT 0 5369 5370 #define TV_CLR_KNOBS _MMIO(0x68028) 5371 /* 2s-complement brightness adjustment */ 5372 # define TV_BRIGHTNESS_MASK 0xff000000 5373 # define TV_BRIGHTNESS_SHIFT 24 5374 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 5375 # define TV_CONTRAST_MASK 0x00ff0000 5376 # define TV_CONTRAST_SHIFT 16 5377 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 5378 # define TV_SATURATION_MASK 0x0000ff00 5379 # define TV_SATURATION_SHIFT 8 5380 /* Hue adjustment, as an integer phase angle in degrees */ 5381 # define TV_HUE_MASK 0x000000ff 5382 # define TV_HUE_SHIFT 0 5383 5384 #define TV_CLR_LEVEL _MMIO(0x6802c) 5385 /* Controls the DAC level for black */ 5386 # define TV_BLACK_LEVEL_MASK 0x01ff0000 5387 # define TV_BLACK_LEVEL_SHIFT 16 5388 /* Controls the DAC level for blanking */ 5389 # define TV_BLANK_LEVEL_MASK 0x000001ff 5390 # define TV_BLANK_LEVEL_SHIFT 0 5391 5392 #define TV_H_CTL_1 _MMIO(0x68030) 5393 /* Number of pixels in the hsync. */ 5394 # define TV_HSYNC_END_MASK 0x1fff0000 5395 # define TV_HSYNC_END_SHIFT 16 5396 /* Total number of pixels minus one in the line (display and blanking). */ 5397 # define TV_HTOTAL_MASK 0x00001fff 5398 # define TV_HTOTAL_SHIFT 0 5399 5400 #define TV_H_CTL_2 _MMIO(0x68034) 5401 /* Enables the colorburst (needed for non-component color) */ 5402 # define TV_BURST_ENA (1 << 31) 5403 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 5404 # define TV_HBURST_START_SHIFT 16 5405 # define TV_HBURST_START_MASK 0x1fff0000 5406 /* Length of the colorburst */ 5407 # define TV_HBURST_LEN_SHIFT 0 5408 # define TV_HBURST_LEN_MASK 0x0001fff 5409 5410 #define TV_H_CTL_3 _MMIO(0x68038) 5411 /* End of hblank, measured in pixels minus one from start of hsync */ 5412 # define TV_HBLANK_END_SHIFT 16 5413 # define TV_HBLANK_END_MASK 0x1fff0000 5414 /* Start of hblank, measured in pixels minus one from start of hsync */ 5415 # define TV_HBLANK_START_SHIFT 0 5416 # define TV_HBLANK_START_MASK 0x0001fff 5417 5418 #define TV_V_CTL_1 _MMIO(0x6803c) 5419 /* XXX */ 5420 # define TV_NBR_END_SHIFT 16 5421 # define TV_NBR_END_MASK 0x07ff0000 5422 /* XXX */ 5423 # define TV_VI_END_F1_SHIFT 8 5424 # define TV_VI_END_F1_MASK 0x00003f00 5425 /* XXX */ 5426 # define TV_VI_END_F2_SHIFT 0 5427 # define TV_VI_END_F2_MASK 0x0000003f 5428 5429 #define TV_V_CTL_2 _MMIO(0x68040) 5430 /* Length of vsync, in half lines */ 5431 # define TV_VSYNC_LEN_MASK 0x07ff0000 5432 # define TV_VSYNC_LEN_SHIFT 16 5433 /* Offset of the start of vsync in field 1, measured in one less than the 5434 * number of half lines. 5435 */ 5436 # define TV_VSYNC_START_F1_MASK 0x00007f00 5437 # define TV_VSYNC_START_F1_SHIFT 8 5438 /* 5439 * Offset of the start of vsync in field 2, measured in one less than the 5440 * number of half lines. 5441 */ 5442 # define TV_VSYNC_START_F2_MASK 0x0000007f 5443 # define TV_VSYNC_START_F2_SHIFT 0 5444 5445 #define TV_V_CTL_3 _MMIO(0x68044) 5446 /* Enables generation of the equalization signal */ 5447 # define TV_EQUAL_ENA (1 << 31) 5448 /* Length of vsync, in half lines */ 5449 # define TV_VEQ_LEN_MASK 0x007f0000 5450 # define TV_VEQ_LEN_SHIFT 16 5451 /* Offset of the start of equalization in field 1, measured in one less than 5452 * the number of half lines. 5453 */ 5454 # define TV_VEQ_START_F1_MASK 0x0007f00 5455 # define TV_VEQ_START_F1_SHIFT 8 5456 /* 5457 * Offset of the start of equalization in field 2, measured in one less than 5458 * the number of half lines. 5459 */ 5460 # define TV_VEQ_START_F2_MASK 0x000007f 5461 # define TV_VEQ_START_F2_SHIFT 0 5462 5463 #define TV_V_CTL_4 _MMIO(0x68048) 5464 /* 5465 * Offset to start of vertical colorburst, measured in one less than the 5466 * number of lines from vertical start. 5467 */ 5468 # define TV_VBURST_START_F1_MASK 0x003f0000 5469 # define TV_VBURST_START_F1_SHIFT 16 5470 /* 5471 * Offset to the end of vertical colorburst, measured in one less than the 5472 * number of lines from the start of NBR. 5473 */ 5474 # define TV_VBURST_END_F1_MASK 0x000000ff 5475 # define TV_VBURST_END_F1_SHIFT 0 5476 5477 #define TV_V_CTL_5 _MMIO(0x6804c) 5478 /* 5479 * Offset to start of vertical colorburst, measured in one less than the 5480 * number of lines from vertical start. 5481 */ 5482 # define TV_VBURST_START_F2_MASK 0x003f0000 5483 # define TV_VBURST_START_F2_SHIFT 16 5484 /* 5485 * Offset to the end of vertical colorburst, measured in one less than the 5486 * number of lines from the start of NBR. 5487 */ 5488 # define TV_VBURST_END_F2_MASK 0x000000ff 5489 # define TV_VBURST_END_F2_SHIFT 0 5490 5491 #define TV_V_CTL_6 _MMIO(0x68050) 5492 /* 5493 * Offset to start of vertical colorburst, measured in one less than the 5494 * number of lines from vertical start. 5495 */ 5496 # define TV_VBURST_START_F3_MASK 0x003f0000 5497 # define TV_VBURST_START_F3_SHIFT 16 5498 /* 5499 * Offset to the end of vertical colorburst, measured in one less than the 5500 * number of lines from the start of NBR. 5501 */ 5502 # define TV_VBURST_END_F3_MASK 0x000000ff 5503 # define TV_VBURST_END_F3_SHIFT 0 5504 5505 #define TV_V_CTL_7 _MMIO(0x68054) 5506 /* 5507 * Offset to start of vertical colorburst, measured in one less than the 5508 * number of lines from vertical start. 5509 */ 5510 # define TV_VBURST_START_F4_MASK 0x003f0000 5511 # define TV_VBURST_START_F4_SHIFT 16 5512 /* 5513 * Offset to the end of vertical colorburst, measured in one less than the 5514 * number of lines from the start of NBR. 5515 */ 5516 # define TV_VBURST_END_F4_MASK 0x000000ff 5517 # define TV_VBURST_END_F4_SHIFT 0 5518 5519 #define TV_SC_CTL_1 _MMIO(0x68060) 5520 /* Turns on the first subcarrier phase generation DDA */ 5521 # define TV_SC_DDA1_EN (1 << 31) 5522 /* Turns on the first subcarrier phase generation DDA */ 5523 # define TV_SC_DDA2_EN (1 << 30) 5524 /* Turns on the first subcarrier phase generation DDA */ 5525 # define TV_SC_DDA3_EN (1 << 29) 5526 /* Sets the subcarrier DDA to reset frequency every other field */ 5527 # define TV_SC_RESET_EVERY_2 (0 << 24) 5528 /* Sets the subcarrier DDA to reset frequency every fourth field */ 5529 # define TV_SC_RESET_EVERY_4 (1 << 24) 5530 /* Sets the subcarrier DDA to reset frequency every eighth field */ 5531 # define TV_SC_RESET_EVERY_8 (2 << 24) 5532 /* Sets the subcarrier DDA to never reset the frequency */ 5533 # define TV_SC_RESET_NEVER (3 << 24) 5534 /* Sets the peak amplitude of the colorburst.*/ 5535 # define TV_BURST_LEVEL_MASK 0x00ff0000 5536 # define TV_BURST_LEVEL_SHIFT 16 5537 /* Sets the increment of the first subcarrier phase generation DDA */ 5538 # define TV_SCDDA1_INC_MASK 0x00000fff 5539 # define TV_SCDDA1_INC_SHIFT 0 5540 5541 #define TV_SC_CTL_2 _MMIO(0x68064) 5542 /* Sets the rollover for the second subcarrier phase generation DDA */ 5543 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 5544 # define TV_SCDDA2_SIZE_SHIFT 16 5545 /* Sets the increent of the second subcarrier phase generation DDA */ 5546 # define TV_SCDDA2_INC_MASK 0x00007fff 5547 # define TV_SCDDA2_INC_SHIFT 0 5548 5549 #define TV_SC_CTL_3 _MMIO(0x68068) 5550 /* Sets the rollover for the third subcarrier phase generation DDA */ 5551 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 5552 # define TV_SCDDA3_SIZE_SHIFT 16 5553 /* Sets the increent of the third subcarrier phase generation DDA */ 5554 # define TV_SCDDA3_INC_MASK 0x00007fff 5555 # define TV_SCDDA3_INC_SHIFT 0 5556 5557 #define TV_WIN_POS _MMIO(0x68070) 5558 /* X coordinate of the display from the start of horizontal active */ 5559 # define TV_XPOS_MASK 0x1fff0000 5560 # define TV_XPOS_SHIFT 16 5561 /* Y coordinate of the display from the start of vertical active (NBR) */ 5562 # define TV_YPOS_MASK 0x00000fff 5563 # define TV_YPOS_SHIFT 0 5564 5565 #define TV_WIN_SIZE _MMIO(0x68074) 5566 /* Horizontal size of the display window, measured in pixels*/ 5567 # define TV_XSIZE_MASK 0x1fff0000 5568 # define TV_XSIZE_SHIFT 16 5569 /* 5570 * Vertical size of the display window, measured in pixels. 5571 * 5572 * Must be even for interlaced modes. 5573 */ 5574 # define TV_YSIZE_MASK 0x00000fff 5575 # define TV_YSIZE_SHIFT 0 5576 5577 #define TV_FILTER_CTL_1 _MMIO(0x68080) 5578 /* 5579 * Enables automatic scaling calculation. 5580 * 5581 * If set, the rest of the registers are ignored, and the calculated values can 5582 * be read back from the register. 5583 */ 5584 # define TV_AUTO_SCALE (1 << 31) 5585 /* 5586 * Disables the vertical filter. 5587 * 5588 * This is required on modes more than 1024 pixels wide */ 5589 # define TV_V_FILTER_BYPASS (1 << 29) 5590 /* Enables adaptive vertical filtering */ 5591 # define TV_VADAPT (1 << 28) 5592 # define TV_VADAPT_MODE_MASK (3 << 26) 5593 /* Selects the least adaptive vertical filtering mode */ 5594 # define TV_VADAPT_MODE_LEAST (0 << 26) 5595 /* Selects the moderately adaptive vertical filtering mode */ 5596 # define TV_VADAPT_MODE_MODERATE (1 << 26) 5597 /* Selects the most adaptive vertical filtering mode */ 5598 # define TV_VADAPT_MODE_MOST (3 << 26) 5599 /* 5600 * Sets the horizontal scaling factor. 5601 * 5602 * This should be the fractional part of the horizontal scaling factor divided 5603 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 5604 * 5605 * (src width - 1) / ((oversample * dest width) - 1) 5606 */ 5607 # define TV_HSCALE_FRAC_MASK 0x00003fff 5608 # define TV_HSCALE_FRAC_SHIFT 0 5609 5610 #define TV_FILTER_CTL_2 _MMIO(0x68084) 5611 /* 5612 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5613 * 5614 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 5615 */ 5616 # define TV_VSCALE_INT_MASK 0x00038000 5617 # define TV_VSCALE_INT_SHIFT 15 5618 /* 5619 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5620 * 5621 * \sa TV_VSCALE_INT_MASK 5622 */ 5623 # define TV_VSCALE_FRAC_MASK 0x00007fff 5624 # define TV_VSCALE_FRAC_SHIFT 0 5625 5626 #define TV_FILTER_CTL_3 _MMIO(0x68088) 5627 /* 5628 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5629 * 5630 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 5631 * 5632 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5633 */ 5634 # define TV_VSCALE_IP_INT_MASK 0x00038000 5635 # define TV_VSCALE_IP_INT_SHIFT 15 5636 /* 5637 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5638 * 5639 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5640 * 5641 * \sa TV_VSCALE_IP_INT_MASK 5642 */ 5643 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 5644 # define TV_VSCALE_IP_FRAC_SHIFT 0 5645 5646 #define TV_CC_CONTROL _MMIO(0x68090) 5647 # define TV_CC_ENABLE (1 << 31) 5648 /* 5649 * Specifies which field to send the CC data in. 5650 * 5651 * CC data is usually sent in field 0. 5652 */ 5653 # define TV_CC_FID_MASK (1 << 27) 5654 # define TV_CC_FID_SHIFT 27 5655 /* Sets the horizontal position of the CC data. Usually 135. */ 5656 # define TV_CC_HOFF_MASK 0x03ff0000 5657 # define TV_CC_HOFF_SHIFT 16 5658 /* Sets the vertical position of the CC data. Usually 21 */ 5659 # define TV_CC_LINE_MASK 0x0000003f 5660 # define TV_CC_LINE_SHIFT 0 5661 5662 #define TV_CC_DATA _MMIO(0x68094) 5663 # define TV_CC_RDY (1 << 31) 5664 /* Second word of CC data to be transmitted. */ 5665 # define TV_CC_DATA_2_MASK 0x007f0000 5666 # define TV_CC_DATA_2_SHIFT 16 5667 /* First word of CC data to be transmitted. */ 5668 # define TV_CC_DATA_1_MASK 0x0000007f 5669 # define TV_CC_DATA_1_SHIFT 0 5670 5671 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 5672 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 5673 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 5674 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 5675 5676 /* Display Port */ 5677 #define DP_A _MMIO(0x64000) /* eDP */ 5678 #define DP_B _MMIO(0x64100) 5679 #define DP_C _MMIO(0x64200) 5680 #define DP_D _MMIO(0x64300) 5681 5682 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 5683 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 5684 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 5685 5686 #define DP_PORT_EN (1 << 31) 5687 #define DP_PIPE_SEL_SHIFT 30 5688 #define DP_PIPE_SEL_MASK (1 << 30) 5689 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 5690 #define DP_PIPE_SEL_SHIFT_IVB 29 5691 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 5692 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5693 #define DP_PIPE_SEL_SHIFT_CHV 16 5694 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 5695 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 5696 5697 /* Link training mode - select a suitable mode for each stage */ 5698 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 5699 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 5700 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 5701 #define DP_LINK_TRAIN_OFF (3 << 28) 5702 #define DP_LINK_TRAIN_MASK (3 << 28) 5703 #define DP_LINK_TRAIN_SHIFT 28 5704 5705 /* CPT Link training mode */ 5706 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 5707 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 5708 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 5709 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 5710 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 5711 #define DP_LINK_TRAIN_SHIFT_CPT 8 5712 5713 /* Signal voltages. These are mostly controlled by the other end */ 5714 #define DP_VOLTAGE_0_4 (0 << 25) 5715 #define DP_VOLTAGE_0_6 (1 << 25) 5716 #define DP_VOLTAGE_0_8 (2 << 25) 5717 #define DP_VOLTAGE_1_2 (3 << 25) 5718 #define DP_VOLTAGE_MASK (7 << 25) 5719 #define DP_VOLTAGE_SHIFT 25 5720 5721 /* Signal pre-emphasis levels, like voltages, the other end tells us what 5722 * they want 5723 */ 5724 #define DP_PRE_EMPHASIS_0 (0 << 22) 5725 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 5726 #define DP_PRE_EMPHASIS_6 (2 << 22) 5727 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 5728 #define DP_PRE_EMPHASIS_MASK (7 << 22) 5729 #define DP_PRE_EMPHASIS_SHIFT 22 5730 5731 /* How many wires to use. I guess 3 was too hard */ 5732 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 5733 #define DP_PORT_WIDTH_MASK (7 << 19) 5734 #define DP_PORT_WIDTH_SHIFT 19 5735 5736 /* Mystic DPCD version 1.1 special mode */ 5737 #define DP_ENHANCED_FRAMING (1 << 18) 5738 5739 /* eDP */ 5740 #define DP_PLL_FREQ_270MHZ (0 << 16) 5741 #define DP_PLL_FREQ_162MHZ (1 << 16) 5742 #define DP_PLL_FREQ_MASK (3 << 16) 5743 5744 /* locked once port is enabled */ 5745 #define DP_PORT_REVERSAL (1 << 15) 5746 5747 /* eDP */ 5748 #define DP_PLL_ENABLE (1 << 14) 5749 5750 /* sends the clock on lane 15 of the PEG for debug */ 5751 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 5752 5753 #define DP_SCRAMBLING_DISABLE (1 << 12) 5754 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 5755 5756 /* limit RGB values to avoid confusing TVs */ 5757 #define DP_COLOR_RANGE_16_235 (1 << 8) 5758 5759 /* Turn on the audio link */ 5760 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 5761 5762 /* vs and hs sync polarity */ 5763 #define DP_SYNC_VS_HIGH (1 << 4) 5764 #define DP_SYNC_HS_HIGH (1 << 3) 5765 5766 /* A fantasy */ 5767 #define DP_DETECTED (1 << 2) 5768 5769 /* The aux channel provides a way to talk to the 5770 * signal sink for DDC etc. Max packet size supported 5771 * is 20 bytes in each direction, hence the 5 fixed 5772 * data registers 5773 */ 5774 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 5775 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 5776 5777 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 5778 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 5779 5780 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 5781 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5782 5783 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 5784 #define DP_AUX_CH_CTL_DONE (1 << 30) 5785 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 5786 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 5787 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 5788 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 5789 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 5790 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 5791 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 5792 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 5793 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 5794 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 5795 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 5796 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 5797 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 5798 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 5799 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 5800 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 5801 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 5802 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 5803 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 5804 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 5805 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 5806 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 5807 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 5808 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 5809 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 5810 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 5811 5812 /* 5813 * Computing GMCH M and N values for the Display Port link 5814 * 5815 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 5816 * 5817 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 5818 * 5819 * The GMCH value is used internally 5820 * 5821 * bytes_per_pixel is the number of bytes coming out of the plane, 5822 * which is after the LUTs, so we want the bytes for our color format. 5823 * For our current usage, this is always 3, one byte for R, G and B. 5824 */ 5825 #define _PIPEA_DATA_M_G4X 0x70050 5826 #define _PIPEB_DATA_M_G4X 0x71050 5827 5828 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 5829 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */ 5830 #define TU_SIZE_SHIFT 25 5831 #define TU_SIZE_MASK (0x3f << 25) 5832 5833 #define DATA_LINK_M_N_MASK (0xffffff) 5834 #define DATA_LINK_N_MAX (0x800000) 5835 5836 #define _PIPEA_DATA_N_G4X 0x70054 5837 #define _PIPEB_DATA_N_G4X 0x71054 5838 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 5839 5840 /* 5841 * Computing Link M and N values for the Display Port link 5842 * 5843 * Link M / N = pixel_clock / ls_clk 5844 * 5845 * (the DP spec calls pixel_clock the 'strm_clk') 5846 * 5847 * The Link value is transmitted in the Main Stream 5848 * Attributes and VB-ID. 5849 */ 5850 5851 #define _PIPEA_LINK_M_G4X 0x70060 5852 #define _PIPEB_LINK_M_G4X 0x71060 5853 #define PIPEA_DP_LINK_M_MASK (0xffffff) 5854 5855 #define _PIPEA_LINK_N_G4X 0x70064 5856 #define _PIPEB_LINK_N_G4X 0x71064 5857 #define PIPEA_DP_LINK_N_MASK (0xffffff) 5858 5859 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 5860 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 5861 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 5862 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 5863 5864 /* Display & cursor control */ 5865 5866 /* Pipe A */ 5867 #define _PIPEADSL 0x70000 5868 #define DSL_LINEMASK_GEN2 0x00000fff 5869 #define DSL_LINEMASK_GEN3 0x00001fff 5870 #define _PIPEACONF 0x70008 5871 #define PIPECONF_ENABLE (1 << 31) 5872 #define PIPECONF_DISABLE 0 5873 #define PIPECONF_DOUBLE_WIDE (1 << 30) 5874 #define I965_PIPECONF_ACTIVE (1 << 30) 5875 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ 5876 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */ 5877 #define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */ 5878 #define PIPECONF_SINGLE_WIDE 0 5879 #define PIPECONF_PIPE_UNLOCKED 0 5880 #define PIPECONF_PIPE_LOCKED (1 << 25) 5881 #define PIPECONF_FORCE_BORDER (1 << 25) 5882 #define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */ 5883 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */ 5884 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */ 5885 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */ 5886 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */ 5887 #define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */ 5888 #define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */ 5889 #define PIPECONF_GAMMA_MODE_SHIFT 24 5890 #define PIPECONF_INTERLACE_MASK (7 << 21) 5891 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 5892 /* Note that pre-gen3 does not support interlaced display directly. Panel 5893 * fitting must be disabled on pre-ilk for interlaced. */ 5894 #define PIPECONF_PROGRESSIVE (0 << 21) 5895 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 5896 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 5897 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 5898 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 5899 /* Ironlake and later have a complete new set of values for interlaced. PFIT 5900 * means panel fitter required, PF means progressive fetch, DBL means power 5901 * saving pixel doubling. */ 5902 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 5903 #define PIPECONF_INTERLACED_ILK (3 << 21) 5904 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 5905 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 5906 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 5907 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 5908 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16) 5909 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 5910 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 5911 #define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */ 5912 #define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */ 5913 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */ 5914 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */ 5915 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */ 5916 #define PIPECONF_BPC_MASK (0x7 << 5) 5917 #define PIPECONF_8BPC (0 << 5) 5918 #define PIPECONF_10BPC (1 << 5) 5919 #define PIPECONF_6BPC (2 << 5) 5920 #define PIPECONF_12BPC (3 << 5) 5921 #define PIPECONF_DITHER_EN (1 << 4) 5922 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 5923 #define PIPECONF_DITHER_TYPE_SP (0 << 2) 5924 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2) 5925 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2) 5926 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2) 5927 #define _PIPEASTAT 0x70024 5928 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 5929 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 5930 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 5931 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 5932 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 5933 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 5934 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 5935 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 5936 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 5937 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 5938 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 5939 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 5940 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 5941 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 5942 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 5943 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 5944 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 5945 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 5946 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 5947 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 5948 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 5949 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 5950 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 5951 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 5952 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 5953 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 5954 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 5955 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 5956 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 5957 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 5958 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 5959 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 5960 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 5961 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 5962 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 5963 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 5964 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 5965 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 5966 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 5967 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 5968 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 5969 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 5970 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 5971 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 5972 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 5973 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 5974 5975 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 5976 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 5977 5978 #define PIPE_A_OFFSET 0x70000 5979 #define PIPE_B_OFFSET 0x71000 5980 #define PIPE_C_OFFSET 0x72000 5981 #define PIPE_D_OFFSET 0x73000 5982 #define CHV_PIPE_C_OFFSET 0x74000 5983 /* 5984 * There's actually no pipe EDP. Some pipe registers have 5985 * simply shifted from the pipe to the transcoder, while 5986 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 5987 * to access such registers in transcoder EDP. 5988 */ 5989 #define PIPE_EDP_OFFSET 0x7f000 5990 5991 /* ICL DSI 0 and 1 */ 5992 #define PIPE_DSI0_OFFSET 0x7b000 5993 #define PIPE_DSI1_OFFSET 0x7b800 5994 5995 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 5996 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 5997 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 5998 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 5999 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 6000 6001 #define _PIPEAGCMAX 0x70010 6002 #define _PIPEBGCMAX 0x71010 6003 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 6004 6005 #define _PIPE_MISC_A 0x70030 6006 #define _PIPE_MISC_B 0x71030 6007 #define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */ 6008 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */ 6009 #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ 6010 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) 6011 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 6012 #define PIPEMISC_DITHER_BPC_MASK (7 << 5) 6013 #define PIPEMISC_DITHER_8_BPC (0 << 5) 6014 #define PIPEMISC_DITHER_10_BPC (1 << 5) 6015 #define PIPEMISC_DITHER_6_BPC (2 << 5) 6016 #define PIPEMISC_DITHER_12_BPC (3 << 5) 6017 #define PIPEMISC_DITHER_ENABLE (1 << 4) 6018 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2) 6019 #define PIPEMISC_DITHER_TYPE_SP (0 << 2) 6020 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 6021 6022 /* Skylake+ pipe bottom (background) color */ 6023 #define _SKL_BOTTOM_COLOR_A 0x70034 6024 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31) 6025 #define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30) 6026 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 6027 6028 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 6029 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) 6030 #define PIPEB_HLINE_INT_EN (1 << 28) 6031 #define PIPEB_VBLANK_INT_EN (1 << 27) 6032 #define SPRITED_FLIP_DONE_INT_EN (1 << 26) 6033 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25) 6034 #define PLANEB_FLIP_DONE_INT_EN (1 << 24) 6035 #define PIPE_PSR_INT_EN (1 << 22) 6036 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21) 6037 #define PIPEA_HLINE_INT_EN (1 << 20) 6038 #define PIPEA_VBLANK_INT_EN (1 << 19) 6039 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18) 6040 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17) 6041 #define PLANEA_FLIPDONE_INT_EN (1 << 16) 6042 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13) 6043 #define PIPEC_HLINE_INT_EN (1 << 12) 6044 #define PIPEC_VBLANK_INT_EN (1 << 11) 6045 #define SPRITEF_FLIPDONE_INT_EN (1 << 10) 6046 #define SPRITEE_FLIPDONE_INT_EN (1 << 9) 6047 #define PLANEC_FLIPDONE_INT_EN (1 << 8) 6048 6049 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 6050 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27) 6051 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26) 6052 #define PLANEC_INVALID_GTT_INT_EN (1 << 25) 6053 #define CURSORC_INVALID_GTT_INT_EN (1 << 24) 6054 #define CURSORB_INVALID_GTT_INT_EN (1 << 23) 6055 #define CURSORA_INVALID_GTT_INT_EN (1 << 22) 6056 #define SPRITED_INVALID_GTT_INT_EN (1 << 21) 6057 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20) 6058 #define PLANEB_INVALID_GTT_INT_EN (1 << 19) 6059 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18) 6060 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17) 6061 #define PLANEA_INVALID_GTT_INT_EN (1 << 16) 6062 #define DPINVGTT_EN_MASK 0xff0000 6063 #define DPINVGTT_EN_MASK_CHV 0xfff0000 6064 #define SPRITEF_INVALID_GTT_STATUS (1 << 11) 6065 #define SPRITEE_INVALID_GTT_STATUS (1 << 10) 6066 #define PLANEC_INVALID_GTT_STATUS (1 << 9) 6067 #define CURSORC_INVALID_GTT_STATUS (1 << 8) 6068 #define CURSORB_INVALID_GTT_STATUS (1 << 7) 6069 #define CURSORA_INVALID_GTT_STATUS (1 << 6) 6070 #define SPRITED_INVALID_GTT_STATUS (1 << 5) 6071 #define SPRITEC_INVALID_GTT_STATUS (1 << 4) 6072 #define PLANEB_INVALID_GTT_STATUS (1 << 3) 6073 #define SPRITEB_INVALID_GTT_STATUS (1 << 2) 6074 #define SPRITEA_INVALID_GTT_STATUS (1 << 1) 6075 #define PLANEA_INVALID_GTT_STATUS (1 << 0) 6076 #define DPINVGTT_STATUS_MASK 0xff 6077 #define DPINVGTT_STATUS_MASK_CHV 0xfff 6078 6079 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 6080 #define DSPARB_CSTART_MASK (0x7f << 7) 6081 #define DSPARB_CSTART_SHIFT 7 6082 #define DSPARB_BSTART_MASK (0x7f) 6083 #define DSPARB_BSTART_SHIFT 0 6084 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 6085 #define DSPARB_AEND_SHIFT 0 6086 #define DSPARB_SPRITEA_SHIFT_VLV 0 6087 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 6088 #define DSPARB_SPRITEB_SHIFT_VLV 8 6089 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 6090 #define DSPARB_SPRITEC_SHIFT_VLV 16 6091 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 6092 #define DSPARB_SPRITED_SHIFT_VLV 24 6093 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 6094 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 6095 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 6096 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 6097 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 6098 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 6099 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 6100 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 6101 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 6102 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 6103 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 6104 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 6105 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 6106 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 6107 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 6108 #define DSPARB_SPRITEE_SHIFT_VLV 0 6109 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 6110 #define DSPARB_SPRITEF_SHIFT_VLV 8 6111 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 6112 6113 /* pnv/gen4/g4x/vlv/chv */ 6114 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 6115 #define DSPFW_SR_SHIFT 23 6116 #define DSPFW_SR_MASK (0x1ff << 23) 6117 #define DSPFW_CURSORB_SHIFT 16 6118 #define DSPFW_CURSORB_MASK (0x3f << 16) 6119 #define DSPFW_PLANEB_SHIFT 8 6120 #define DSPFW_PLANEB_MASK (0x7f << 8) 6121 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 6122 #define DSPFW_PLANEA_SHIFT 0 6123 #define DSPFW_PLANEA_MASK (0x7f << 0) 6124 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 6125 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 6126 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 6127 #define DSPFW_FBC_SR_SHIFT 28 6128 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 6129 #define DSPFW_FBC_HPLL_SR_SHIFT 24 6130 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 6131 #define DSPFW_SPRITEB_SHIFT (16) 6132 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 6133 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 6134 #define DSPFW_CURSORA_SHIFT 8 6135 #define DSPFW_CURSORA_MASK (0x3f << 8) 6136 #define DSPFW_PLANEC_OLD_SHIFT 0 6137 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 6138 #define DSPFW_SPRITEA_SHIFT 0 6139 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 6140 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 6141 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 6142 #define DSPFW_HPLL_SR_EN (1 << 31) 6143 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 6144 #define DSPFW_CURSOR_SR_SHIFT 24 6145 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 6146 #define DSPFW_HPLL_CURSOR_SHIFT 16 6147 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 6148 #define DSPFW_HPLL_SR_SHIFT 0 6149 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 6150 6151 /* vlv/chv */ 6152 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 6153 #define DSPFW_SPRITEB_WM1_SHIFT 16 6154 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 6155 #define DSPFW_CURSORA_WM1_SHIFT 8 6156 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 6157 #define DSPFW_SPRITEA_WM1_SHIFT 0 6158 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 6159 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 6160 #define DSPFW_PLANEB_WM1_SHIFT 24 6161 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 6162 #define DSPFW_PLANEA_WM1_SHIFT 16 6163 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 6164 #define DSPFW_CURSORB_WM1_SHIFT 8 6165 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 6166 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 6167 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 6168 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 6169 #define DSPFW_SR_WM1_SHIFT 0 6170 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 6171 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 6172 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 6173 #define DSPFW_SPRITED_WM1_SHIFT 24 6174 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 6175 #define DSPFW_SPRITED_SHIFT 16 6176 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 6177 #define DSPFW_SPRITEC_WM1_SHIFT 8 6178 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 6179 #define DSPFW_SPRITEC_SHIFT 0 6180 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 6181 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 6182 #define DSPFW_SPRITEF_WM1_SHIFT 24 6183 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 6184 #define DSPFW_SPRITEF_SHIFT 16 6185 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 6186 #define DSPFW_SPRITEE_WM1_SHIFT 8 6187 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 6188 #define DSPFW_SPRITEE_SHIFT 0 6189 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 6190 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 6191 #define DSPFW_PLANEC_WM1_SHIFT 24 6192 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 6193 #define DSPFW_PLANEC_SHIFT 16 6194 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 6195 #define DSPFW_CURSORC_WM1_SHIFT 8 6196 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 6197 #define DSPFW_CURSORC_SHIFT 0 6198 #define DSPFW_CURSORC_MASK (0x3f << 0) 6199 6200 /* vlv/chv high order bits */ 6201 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 6202 #define DSPFW_SR_HI_SHIFT 24 6203 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 6204 #define DSPFW_SPRITEF_HI_SHIFT 23 6205 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 6206 #define DSPFW_SPRITEE_HI_SHIFT 22 6207 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 6208 #define DSPFW_PLANEC_HI_SHIFT 21 6209 #define DSPFW_PLANEC_HI_MASK (1 << 21) 6210 #define DSPFW_SPRITED_HI_SHIFT 20 6211 #define DSPFW_SPRITED_HI_MASK (1 << 20) 6212 #define DSPFW_SPRITEC_HI_SHIFT 16 6213 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 6214 #define DSPFW_PLANEB_HI_SHIFT 12 6215 #define DSPFW_PLANEB_HI_MASK (1 << 12) 6216 #define DSPFW_SPRITEB_HI_SHIFT 8 6217 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 6218 #define DSPFW_SPRITEA_HI_SHIFT 4 6219 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 6220 #define DSPFW_PLANEA_HI_SHIFT 0 6221 #define DSPFW_PLANEA_HI_MASK (1 << 0) 6222 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 6223 #define DSPFW_SR_WM1_HI_SHIFT 24 6224 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 6225 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 6226 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 6227 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 6228 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 6229 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 6230 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 6231 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 6232 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 6233 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 6234 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 6235 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 6236 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 6237 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 6238 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 6239 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 6240 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 6241 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 6242 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 6243 6244 /* drain latency register values*/ 6245 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 6246 #define DDL_CURSOR_SHIFT 24 6247 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 6248 #define DDL_PLANE_SHIFT 0 6249 #define DDL_PRECISION_HIGH (1 << 7) 6250 #define DDL_PRECISION_LOW (0 << 7) 6251 #define DRAIN_LATENCY_MASK 0x7f 6252 6253 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 6254 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 6255 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 6256 6257 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 6258 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 6259 6260 /* FIFO watermark sizes etc */ 6261 #define G4X_FIFO_LINE_SIZE 64 6262 #define I915_FIFO_LINE_SIZE 64 6263 #define I830_FIFO_LINE_SIZE 32 6264 6265 #define VALLEYVIEW_FIFO_SIZE 255 6266 #define G4X_FIFO_SIZE 127 6267 #define I965_FIFO_SIZE 512 6268 #define I945_FIFO_SIZE 127 6269 #define I915_FIFO_SIZE 95 6270 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 6271 #define I830_FIFO_SIZE 95 6272 6273 #define VALLEYVIEW_MAX_WM 0xff 6274 #define G4X_MAX_WM 0x3f 6275 #define I915_MAX_WM 0x3f 6276 6277 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 6278 #define PINEVIEW_FIFO_LINE_SIZE 64 6279 #define PINEVIEW_MAX_WM 0x1ff 6280 #define PINEVIEW_DFT_WM 0x3f 6281 #define PINEVIEW_DFT_HPLLOFF_WM 0 6282 #define PINEVIEW_GUARD_WM 10 6283 #define PINEVIEW_CURSOR_FIFO 64 6284 #define PINEVIEW_CURSOR_MAX_WM 0x3f 6285 #define PINEVIEW_CURSOR_DFT_WM 0 6286 #define PINEVIEW_CURSOR_GUARD_WM 5 6287 6288 #define VALLEYVIEW_CURSOR_MAX_WM 64 6289 #define I965_CURSOR_FIFO 64 6290 #define I965_CURSOR_MAX_WM 32 6291 #define I965_CURSOR_DFT_WM 8 6292 6293 /* Watermark register definitions for SKL */ 6294 #define _CUR_WM_A_0 0x70140 6295 #define _CUR_WM_B_0 0x71140 6296 #define _PLANE_WM_1_A_0 0x70240 6297 #define _PLANE_WM_1_B_0 0x71240 6298 #define _PLANE_WM_2_A_0 0x70340 6299 #define _PLANE_WM_2_B_0 0x71340 6300 #define _PLANE_WM_TRANS_1_A_0 0x70268 6301 #define _PLANE_WM_TRANS_1_B_0 0x71268 6302 #define _PLANE_WM_TRANS_2_A_0 0x70368 6303 #define _PLANE_WM_TRANS_2_B_0 0x71368 6304 #define _CUR_WM_TRANS_A_0 0x70168 6305 #define _CUR_WM_TRANS_B_0 0x71168 6306 #define PLANE_WM_EN (1 << 31) 6307 #define PLANE_WM_IGNORE_LINES (1 << 30) 6308 #define PLANE_WM_LINES_SHIFT 14 6309 #define PLANE_WM_LINES_MASK 0x1f 6310 #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */ 6311 6312 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 6313 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 6314 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 6315 6316 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 6317 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 6318 #define _PLANE_WM_BASE(pipe, plane) \ 6319 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 6320 #define PLANE_WM(pipe, plane, level) \ 6321 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 6322 #define _PLANE_WM_TRANS_1(pipe) \ 6323 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 6324 #define _PLANE_WM_TRANS_2(pipe) \ 6325 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 6326 #define PLANE_WM_TRANS(pipe, plane) \ 6327 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 6328 6329 /* define the Watermark register on Ironlake */ 6330 #define WM0_PIPEA_ILK _MMIO(0x45100) 6331 #define WM0_PIPE_PLANE_MASK (0xffff << 16) 6332 #define WM0_PIPE_PLANE_SHIFT 16 6333 #define WM0_PIPE_SPRITE_MASK (0xff << 8) 6334 #define WM0_PIPE_SPRITE_SHIFT 8 6335 #define WM0_PIPE_CURSOR_MASK (0xff) 6336 6337 #define WM0_PIPEB_ILK _MMIO(0x45104) 6338 #define WM0_PIPEC_IVB _MMIO(0x45200) 6339 #define WM1_LP_ILK _MMIO(0x45108) 6340 #define WM1_LP_SR_EN (1 << 31) 6341 #define WM1_LP_LATENCY_SHIFT 24 6342 #define WM1_LP_LATENCY_MASK (0x7f << 24) 6343 #define WM1_LP_FBC_MASK (0xf << 20) 6344 #define WM1_LP_FBC_SHIFT 20 6345 #define WM1_LP_FBC_SHIFT_BDW 19 6346 #define WM1_LP_SR_MASK (0x7ff << 8) 6347 #define WM1_LP_SR_SHIFT 8 6348 #define WM1_LP_CURSOR_MASK (0xff) 6349 #define WM2_LP_ILK _MMIO(0x4510c) 6350 #define WM2_LP_EN (1 << 31) 6351 #define WM3_LP_ILK _MMIO(0x45110) 6352 #define WM3_LP_EN (1 << 31) 6353 #define WM1S_LP_ILK _MMIO(0x45120) 6354 #define WM2S_LP_IVB _MMIO(0x45124) 6355 #define WM3S_LP_IVB _MMIO(0x45128) 6356 #define WM1S_LP_EN (1 << 31) 6357 6358 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 6359 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 6360 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 6361 6362 /* Memory latency timer register */ 6363 #define MLTR_ILK _MMIO(0x11222) 6364 #define MLTR_WM1_SHIFT 0 6365 #define MLTR_WM2_SHIFT 8 6366 /* the unit of memory self-refresh latency time is 0.5us */ 6367 #define ILK_SRLT_MASK 0x3f 6368 6369 6370 /* the address where we get all kinds of latency value */ 6371 #define SSKPD _MMIO(0x5d10) 6372 #define SSKPD_WM_MASK 0x3f 6373 #define SSKPD_WM0_SHIFT 0 6374 #define SSKPD_WM1_SHIFT 8 6375 #define SSKPD_WM2_SHIFT 16 6376 #define SSKPD_WM3_SHIFT 24 6377 6378 /* 6379 * The two pipe frame counter registers are not synchronized, so 6380 * reading a stable value is somewhat tricky. The following code 6381 * should work: 6382 * 6383 * do { 6384 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6385 * PIPE_FRAME_HIGH_SHIFT; 6386 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 6387 * PIPE_FRAME_LOW_SHIFT); 6388 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6389 * PIPE_FRAME_HIGH_SHIFT); 6390 * } while (high1 != high2); 6391 * frame = (high1 << 8) | low1; 6392 */ 6393 #define _PIPEAFRAMEHIGH 0x70040 6394 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 6395 #define PIPE_FRAME_HIGH_SHIFT 0 6396 #define _PIPEAFRAMEPIXEL 0x70044 6397 #define PIPE_FRAME_LOW_MASK 0xff000000 6398 #define PIPE_FRAME_LOW_SHIFT 24 6399 #define PIPE_PIXEL_MASK 0x00ffffff 6400 #define PIPE_PIXEL_SHIFT 0 6401 /* GM45+ just has to be different */ 6402 #define _PIPEA_FRMCOUNT_G4X 0x70040 6403 #define _PIPEA_FLIPCOUNT_G4X 0x70044 6404 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 6405 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 6406 6407 /* Cursor A & B regs */ 6408 #define _CURACNTR 0x70080 6409 /* Old style CUR*CNTR flags (desktop 8xx) */ 6410 #define CURSOR_ENABLE 0x80000000 6411 #define CURSOR_GAMMA_ENABLE 0x40000000 6412 #define CURSOR_STRIDE_SHIFT 28 6413 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 6414 #define CURSOR_FORMAT_SHIFT 24 6415 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 6416 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 6417 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 6418 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 6419 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 6420 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 6421 /* New style CUR*CNTR flags */ 6422 #define MCURSOR_MODE 0x27 6423 #define MCURSOR_MODE_DISABLE 0x00 6424 #define MCURSOR_MODE_128_32B_AX 0x02 6425 #define MCURSOR_MODE_256_32B_AX 0x03 6426 #define MCURSOR_MODE_64_32B_AX 0x07 6427 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX) 6428 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX) 6429 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX) 6430 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28) 6431 #define MCURSOR_PIPE_SELECT_SHIFT 28 6432 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) 6433 #define MCURSOR_GAMMA_ENABLE (1 << 26) 6434 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6435 #define MCURSOR_ROTATE_180 (1 << 15) 6436 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14) 6437 #define _CURABASE 0x70084 6438 #define _CURAPOS 0x70088 6439 #define CURSOR_POS_MASK 0x007FF 6440 #define CURSOR_POS_SIGN 0x8000 6441 #define CURSOR_X_SHIFT 0 6442 #define CURSOR_Y_SHIFT 16 6443 #define CURSIZE _MMIO(0x700a0) /* 845/865 */ 6444 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 6445 #define CUR_FBC_CTL_EN (1 << 31) 6446 #define _CURASURFLIVE 0x700ac /* g4x+ */ 6447 #define _CURBCNTR 0x700c0 6448 #define _CURBBASE 0x700c4 6449 #define _CURBPOS 0x700c8 6450 6451 #define _CURBCNTR_IVB 0x71080 6452 #define _CURBBASE_IVB 0x71084 6453 #define _CURBPOS_IVB 0x71088 6454 6455 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 6456 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 6457 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 6458 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 6459 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) 6460 6461 #define CURSOR_A_OFFSET 0x70080 6462 #define CURSOR_B_OFFSET 0x700c0 6463 #define CHV_CURSOR_C_OFFSET 0x700e0 6464 #define IVB_CURSOR_B_OFFSET 0x71080 6465 #define IVB_CURSOR_C_OFFSET 0x72080 6466 #define TGL_CURSOR_D_OFFSET 0x73080 6467 6468 /* Display A control */ 6469 #define _DSPACNTR 0x70180 6470 #define DISPLAY_PLANE_ENABLE (1 << 31) 6471 #define DISPLAY_PLANE_DISABLE 0 6472 #define DISPPLANE_GAMMA_ENABLE (1 << 30) 6473 #define DISPPLANE_GAMMA_DISABLE 0 6474 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 6475 #define DISPPLANE_YUV422 (0x0 << 26) 6476 #define DISPPLANE_8BPP (0x2 << 26) 6477 #define DISPPLANE_BGRA555 (0x3 << 26) 6478 #define DISPPLANE_BGRX555 (0x4 << 26) 6479 #define DISPPLANE_BGRX565 (0x5 << 26) 6480 #define DISPPLANE_BGRX888 (0x6 << 26) 6481 #define DISPPLANE_BGRA888 (0x7 << 26) 6482 #define DISPPLANE_RGBX101010 (0x8 << 26) 6483 #define DISPPLANE_RGBA101010 (0x9 << 26) 6484 #define DISPPLANE_BGRX101010 (0xa << 26) 6485 #define DISPPLANE_BGRA101010 (0xb << 26) 6486 #define DISPPLANE_RGBX161616 (0xc << 26) 6487 #define DISPPLANE_RGBX888 (0xe << 26) 6488 #define DISPPLANE_RGBA888 (0xf << 26) 6489 #define DISPPLANE_STEREO_ENABLE (1 << 25) 6490 #define DISPPLANE_STEREO_DISABLE 0 6491 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6492 #define DISPPLANE_SEL_PIPE_SHIFT 24 6493 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT) 6494 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT) 6495 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 6496 #define DISPPLANE_SRC_KEY_DISABLE 0 6497 #define DISPPLANE_LINE_DOUBLE (1 << 20) 6498 #define DISPPLANE_NO_LINE_DOUBLE 0 6499 #define DISPPLANE_STEREO_POLARITY_FIRST 0 6500 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 6501 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */ 6502 #define DISPPLANE_ROTATE_180 (1 << 15) 6503 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */ 6504 #define DISPPLANE_TILED (1 << 10) 6505 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */ 6506 #define _DSPAADDR 0x70184 6507 #define _DSPASTRIDE 0x70188 6508 #define _DSPAPOS 0x7018C /* reserved */ 6509 #define _DSPASIZE 0x70190 6510 #define _DSPASURF 0x7019C /* 965+ only */ 6511 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 6512 #define _DSPAOFFSET 0x701A4 /* HSW */ 6513 #define _DSPASURFLIVE 0x701AC 6514 #define _DSPAGAMC 0x701E0 6515 6516 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 6517 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 6518 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 6519 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 6520 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 6521 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 6522 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 6523 #define DSPLINOFF(plane) DSPADDR(plane) 6524 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 6525 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 6526 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 6527 6528 /* CHV pipe B blender and primary plane */ 6529 #define _CHV_BLEND_A 0x60a00 6530 #define CHV_BLEND_LEGACY (0 << 30) 6531 #define CHV_BLEND_ANDROID (1 << 30) 6532 #define CHV_BLEND_MPO (2 << 30) 6533 #define CHV_BLEND_MASK (3 << 30) 6534 #define _CHV_CANVAS_A 0x60a04 6535 #define _PRIMPOS_A 0x60a08 6536 #define _PRIMSIZE_A 0x60a0c 6537 #define _PRIMCNSTALPHA_A 0x60a10 6538 #define PRIM_CONST_ALPHA_ENABLE (1 << 31) 6539 6540 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 6541 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 6542 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 6543 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 6544 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 6545 6546 /* Display/Sprite base address macros */ 6547 #define DISP_BASEADDR_MASK (0xfffff000) 6548 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 6549 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 6550 6551 /* 6552 * VBIOS flags 6553 * gen2: 6554 * [00:06] alm,mgm 6555 * [10:16] all 6556 * [30:32] alm,mgm 6557 * gen3+: 6558 * [00:0f] all 6559 * [10:1f] all 6560 * [30:32] all 6561 */ 6562 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 6563 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 6564 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 6565 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 6566 6567 /* Pipe B */ 6568 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 6569 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 6570 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 6571 #define _PIPEBFRAMEHIGH 0x71040 6572 #define _PIPEBFRAMEPIXEL 0x71044 6573 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 6574 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 6575 6576 6577 /* Display B control */ 6578 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 6579 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 6580 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 6581 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 6582 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 6583 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 6584 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 6585 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 6586 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 6587 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 6588 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6589 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6590 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 6591 6592 /* ICL DSI 0 and 1 */ 6593 #define _PIPEDSI0CONF 0x7b008 6594 #define _PIPEDSI1CONF 0x7b808 6595 6596 /* Sprite A control */ 6597 #define _DVSACNTR 0x72180 6598 #define DVS_ENABLE (1 << 31) 6599 #define DVS_GAMMA_ENABLE (1 << 30) 6600 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27) 6601 #define DVS_PIXFORMAT_MASK (3 << 25) 6602 #define DVS_FORMAT_YUV422 (0 << 25) 6603 #define DVS_FORMAT_RGBX101010 (1 << 25) 6604 #define DVS_FORMAT_RGBX888 (2 << 25) 6605 #define DVS_FORMAT_RGBX161616 (3 << 25) 6606 #define DVS_PIPE_CSC_ENABLE (1 << 24) 6607 #define DVS_SOURCE_KEY (1 << 22) 6608 #define DVS_RGB_ORDER_XBGR (1 << 20) 6609 #define DVS_YUV_FORMAT_BT709 (1 << 18) 6610 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16) 6611 #define DVS_YUV_ORDER_YUYV (0 << 16) 6612 #define DVS_YUV_ORDER_UYVY (1 << 16) 6613 #define DVS_YUV_ORDER_YVYU (2 << 16) 6614 #define DVS_YUV_ORDER_VYUY (3 << 16) 6615 #define DVS_ROTATE_180 (1 << 15) 6616 #define DVS_DEST_KEY (1 << 2) 6617 #define DVS_TRICKLE_FEED_DISABLE (1 << 14) 6618 #define DVS_TILED (1 << 10) 6619 #define _DVSALINOFF 0x72184 6620 #define _DVSASTRIDE 0x72188 6621 #define _DVSAPOS 0x7218c 6622 #define _DVSASIZE 0x72190 6623 #define _DVSAKEYVAL 0x72194 6624 #define _DVSAKEYMSK 0x72198 6625 #define _DVSASURF 0x7219c 6626 #define _DVSAKEYMAXVAL 0x721a0 6627 #define _DVSATILEOFF 0x721a4 6628 #define _DVSASURFLIVE 0x721ac 6629 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 6630 #define _DVSASCALE 0x72204 6631 #define DVS_SCALE_ENABLE (1 << 31) 6632 #define DVS_FILTER_MASK (3 << 29) 6633 #define DVS_FILTER_MEDIUM (0 << 29) 6634 #define DVS_FILTER_ENHANCING (1 << 29) 6635 #define DVS_FILTER_SOFTENING (2 << 29) 6636 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6637 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27) 6638 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 6639 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 6640 6641 #define _DVSBCNTR 0x73180 6642 #define _DVSBLINOFF 0x73184 6643 #define _DVSBSTRIDE 0x73188 6644 #define _DVSBPOS 0x7318c 6645 #define _DVSBSIZE 0x73190 6646 #define _DVSBKEYVAL 0x73194 6647 #define _DVSBKEYMSK 0x73198 6648 #define _DVSBSURF 0x7319c 6649 #define _DVSBKEYMAXVAL 0x731a0 6650 #define _DVSBTILEOFF 0x731a4 6651 #define _DVSBSURFLIVE 0x731ac 6652 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 6653 #define _DVSBSCALE 0x73204 6654 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 6655 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 6656 6657 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 6658 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 6659 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 6660 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 6661 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 6662 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 6663 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 6664 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 6665 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 6666 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 6667 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 6668 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 6669 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 6670 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 6671 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 6672 6673 #define _SPRA_CTL 0x70280 6674 #define SPRITE_ENABLE (1 << 31) 6675 #define SPRITE_GAMMA_ENABLE (1 << 30) 6676 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6677 #define SPRITE_PIXFORMAT_MASK (7 << 25) 6678 #define SPRITE_FORMAT_YUV422 (0 << 25) 6679 #define SPRITE_FORMAT_RGBX101010 (1 << 25) 6680 #define SPRITE_FORMAT_RGBX888 (2 << 25) 6681 #define SPRITE_FORMAT_RGBX161616 (3 << 25) 6682 #define SPRITE_FORMAT_YUV444 (4 << 25) 6683 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */ 6684 #define SPRITE_PIPE_CSC_ENABLE (1 << 24) 6685 #define SPRITE_SOURCE_KEY (1 << 22) 6686 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */ 6687 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19) 6688 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */ 6689 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16) 6690 #define SPRITE_YUV_ORDER_YUYV (0 << 16) 6691 #define SPRITE_YUV_ORDER_UYVY (1 << 16) 6692 #define SPRITE_YUV_ORDER_YVYU (2 << 16) 6693 #define SPRITE_YUV_ORDER_VYUY (3 << 16) 6694 #define SPRITE_ROTATE_180 (1 << 15) 6695 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14) 6696 #define SPRITE_INT_GAMMA_DISABLE (1 << 13) 6697 #define SPRITE_TILED (1 << 10) 6698 #define SPRITE_DEST_KEY (1 << 2) 6699 #define _SPRA_LINOFF 0x70284 6700 #define _SPRA_STRIDE 0x70288 6701 #define _SPRA_POS 0x7028c 6702 #define _SPRA_SIZE 0x70290 6703 #define _SPRA_KEYVAL 0x70294 6704 #define _SPRA_KEYMSK 0x70298 6705 #define _SPRA_SURF 0x7029c 6706 #define _SPRA_KEYMAX 0x702a0 6707 #define _SPRA_TILEOFF 0x702a4 6708 #define _SPRA_OFFSET 0x702a4 6709 #define _SPRA_SURFLIVE 0x702ac 6710 #define _SPRA_SCALE 0x70304 6711 #define SPRITE_SCALE_ENABLE (1 << 31) 6712 #define SPRITE_FILTER_MASK (3 << 29) 6713 #define SPRITE_FILTER_MEDIUM (0 << 29) 6714 #define SPRITE_FILTER_ENHANCING (1 << 29) 6715 #define SPRITE_FILTER_SOFTENING (2 << 29) 6716 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6717 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27) 6718 #define _SPRA_GAMC 0x70400 6719 #define _SPRA_GAMC16 0x70440 6720 #define _SPRA_GAMC17 0x7044c 6721 6722 #define _SPRB_CTL 0x71280 6723 #define _SPRB_LINOFF 0x71284 6724 #define _SPRB_STRIDE 0x71288 6725 #define _SPRB_POS 0x7128c 6726 #define _SPRB_SIZE 0x71290 6727 #define _SPRB_KEYVAL 0x71294 6728 #define _SPRB_KEYMSK 0x71298 6729 #define _SPRB_SURF 0x7129c 6730 #define _SPRB_KEYMAX 0x712a0 6731 #define _SPRB_TILEOFF 0x712a4 6732 #define _SPRB_OFFSET 0x712a4 6733 #define _SPRB_SURFLIVE 0x712ac 6734 #define _SPRB_SCALE 0x71304 6735 #define _SPRB_GAMC 0x71400 6736 #define _SPRB_GAMC16 0x71440 6737 #define _SPRB_GAMC17 0x7144c 6738 6739 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 6740 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 6741 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 6742 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 6743 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 6744 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 6745 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 6746 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 6747 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 6748 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 6749 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 6750 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 6751 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 6752 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 6753 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 6754 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 6755 6756 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 6757 #define SP_ENABLE (1 << 31) 6758 #define SP_GAMMA_ENABLE (1 << 30) 6759 #define SP_PIXFORMAT_MASK (0xf << 26) 6760 #define SP_FORMAT_YUV422 (0x0 << 26) 6761 #define SP_FORMAT_8BPP (0x2 << 26) 6762 #define SP_FORMAT_BGR565 (0x5 << 26) 6763 #define SP_FORMAT_BGRX8888 (0x6 << 26) 6764 #define SP_FORMAT_BGRA8888 (0x7 << 26) 6765 #define SP_FORMAT_RGBX1010102 (0x8 << 26) 6766 #define SP_FORMAT_RGBA1010102 (0x9 << 26) 6767 #define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */ 6768 #define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */ 6769 #define SP_FORMAT_RGBX8888 (0xe << 26) 6770 #define SP_FORMAT_RGBA8888 (0xf << 26) 6771 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */ 6772 #define SP_SOURCE_KEY (1 << 22) 6773 #define SP_YUV_FORMAT_BT709 (1 << 18) 6774 #define SP_YUV_BYTE_ORDER_MASK (3 << 16) 6775 #define SP_YUV_ORDER_YUYV (0 << 16) 6776 #define SP_YUV_ORDER_UYVY (1 << 16) 6777 #define SP_YUV_ORDER_YVYU (2 << 16) 6778 #define SP_YUV_ORDER_VYUY (3 << 16) 6779 #define SP_ROTATE_180 (1 << 15) 6780 #define SP_TILED (1 << 10) 6781 #define SP_MIRROR (1 << 8) /* CHV pipe B */ 6782 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 6783 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 6784 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 6785 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 6786 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 6787 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 6788 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 6789 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 6790 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 6791 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 6792 #define SP_CONST_ALPHA_ENABLE (1 << 31) 6793 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 6794 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */ 6795 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */ 6796 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 6797 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */ 6798 #define SP_SH_COS(x) (x) /* u3.7 */ 6799 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 6800 6801 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 6802 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 6803 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 6804 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 6805 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 6806 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 6807 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 6808 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 6809 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 6810 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 6811 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 6812 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 6813 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 6814 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 6815 6816 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6817 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 6818 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6819 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 6820 6821 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 6822 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 6823 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 6824 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 6825 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 6826 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 6827 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 6828 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 6829 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 6830 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 6831 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 6832 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 6833 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 6834 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 6835 6836 /* 6837 * CHV pipe B sprite CSC 6838 * 6839 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 6840 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 6841 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 6842 */ 6843 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 6844 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 6845 6846 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 6847 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 6848 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 6849 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 6850 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 6851 6852 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 6853 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 6854 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 6855 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 6856 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 6857 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 6858 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 6859 6860 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 6861 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 6862 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 6863 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 6864 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 6865 6866 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 6867 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 6868 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 6869 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 6870 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 6871 6872 /* Skylake plane registers */ 6873 6874 #define _PLANE_CTL_1_A 0x70180 6875 #define _PLANE_CTL_2_A 0x70280 6876 #define _PLANE_CTL_3_A 0x70380 6877 #define PLANE_CTL_ENABLE (1 << 31) 6878 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */ 6879 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6880 /* 6881 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 6882 * expanded to include bit 23 as well. However, the shift-24 based values 6883 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 6884 */ 6885 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 6886 #define PLANE_CTL_FORMAT_YUV422 (0 << 24) 6887 #define PLANE_CTL_FORMAT_NV12 (1 << 24) 6888 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) 6889 #define PLANE_CTL_FORMAT_P010 (3 << 24) 6890 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) 6891 #define PLANE_CTL_FORMAT_P012 (5 << 24) 6892 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) 6893 #define PLANE_CTL_FORMAT_P016 (7 << 24) 6894 #define PLANE_CTL_FORMAT_XYUV (8 << 24) 6895 #define PLANE_CTL_FORMAT_INDEXED (12 << 24) 6896 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) 6897 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) 6898 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ 6899 #define PLANE_CTL_FORMAT_Y210 (1 << 23) 6900 #define PLANE_CTL_FORMAT_Y212 (3 << 23) 6901 #define PLANE_CTL_FORMAT_Y216 (5 << 23) 6902 #define PLANE_CTL_FORMAT_Y410 (7 << 23) 6903 #define PLANE_CTL_FORMAT_Y412 (9 << 23) 6904 #define PLANE_CTL_FORMAT_Y416 (0xb << 23) 6905 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 6906 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) 6907 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21) 6908 #define PLANE_CTL_ORDER_BGRX (0 << 20) 6909 #define PLANE_CTL_ORDER_RGBX (1 << 20) 6910 #define PLANE_CTL_YUV420_Y_PLANE (1 << 19) 6911 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) 6912 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6913 #define PLANE_CTL_YUV422_YUYV (0 << 16) 6914 #define PLANE_CTL_YUV422_UYVY (1 << 16) 6915 #define PLANE_CTL_YUV422_YVYU (2 << 16) 6916 #define PLANE_CTL_YUV422_VYUY (3 << 16) 6917 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15) 6918 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 6919 #define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */ 6920 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ 6921 #define PLANE_CTL_TILED_MASK (0x7 << 10) 6922 #define PLANE_CTL_TILED_LINEAR (0 << 10) 6923 #define PLANE_CTL_TILED_X (1 << 10) 6924 #define PLANE_CTL_TILED_Y (4 << 10) 6925 #define PLANE_CTL_TILED_YF (5 << 10) 6926 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) 6927 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ 6928 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ 6929 #define PLANE_CTL_ALPHA_DISABLE (0 << 4) 6930 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) 6931 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) 6932 #define PLANE_CTL_ROTATE_MASK 0x3 6933 #define PLANE_CTL_ROTATE_0 0x0 6934 #define PLANE_CTL_ROTATE_90 0x1 6935 #define PLANE_CTL_ROTATE_180 0x2 6936 #define PLANE_CTL_ROTATE_270 0x3 6937 #define _PLANE_STRIDE_1_A 0x70188 6938 #define _PLANE_STRIDE_2_A 0x70288 6939 #define _PLANE_STRIDE_3_A 0x70388 6940 #define _PLANE_POS_1_A 0x7018c 6941 #define _PLANE_POS_2_A 0x7028c 6942 #define _PLANE_POS_3_A 0x7038c 6943 #define _PLANE_SIZE_1_A 0x70190 6944 #define _PLANE_SIZE_2_A 0x70290 6945 #define _PLANE_SIZE_3_A 0x70390 6946 #define _PLANE_SURF_1_A 0x7019c 6947 #define _PLANE_SURF_2_A 0x7029c 6948 #define _PLANE_SURF_3_A 0x7039c 6949 #define _PLANE_OFFSET_1_A 0x701a4 6950 #define _PLANE_OFFSET_2_A 0x702a4 6951 #define _PLANE_OFFSET_3_A 0x703a4 6952 #define _PLANE_KEYVAL_1_A 0x70194 6953 #define _PLANE_KEYVAL_2_A 0x70294 6954 #define _PLANE_KEYMSK_1_A 0x70198 6955 #define _PLANE_KEYMSK_2_A 0x70298 6956 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 6957 #define _PLANE_KEYMAX_1_A 0x701a0 6958 #define _PLANE_KEYMAX_2_A 0x702a0 6959 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 6960 #define _PLANE_AUX_DIST_1_A 0x701c0 6961 #define _PLANE_AUX_DIST_2_A 0x702c0 6962 #define _PLANE_AUX_OFFSET_1_A 0x701c4 6963 #define _PLANE_AUX_OFFSET_2_A 0x702c4 6964 #define _PLANE_CUS_CTL_1_A 0x701c8 6965 #define _PLANE_CUS_CTL_2_A 0x702c8 6966 #define PLANE_CUS_ENABLE (1 << 31) 6967 #define PLANE_CUS_PLANE_4_RKL (0 << 30) 6968 #define PLANE_CUS_PLANE_5_RKL (1 << 30) 6969 #define PLANE_CUS_PLANE_6 (0 << 30) 6970 #define PLANE_CUS_PLANE_7 (1 << 30) 6971 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19) 6972 #define PLANE_CUS_HPHASE_0 (0 << 16) 6973 #define PLANE_CUS_HPHASE_0_25 (1 << 16) 6974 #define PLANE_CUS_HPHASE_0_5 (2 << 16) 6975 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15) 6976 #define PLANE_CUS_VPHASE_0 (0 << 12) 6977 #define PLANE_CUS_VPHASE_0_25 (1 << 12) 6978 #define PLANE_CUS_VPHASE_0_5 (2 << 12) 6979 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6980 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6981 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6982 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ 6983 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6984 #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ 6985 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ 6986 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) 6987 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17) 6988 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) 6989 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) 6990 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) 6991 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) 6992 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4) 6993 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4) 6994 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4) 6995 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4) 6996 #define _PLANE_BUF_CFG_1_A 0x7027c 6997 #define _PLANE_BUF_CFG_2_A 0x7037c 6998 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 6999 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 7000 7001 /* Input CSC Register Definitions */ 7002 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 7003 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 7004 7005 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 7006 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 7007 7008 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 7009 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 7010 _PLANE_INPUT_CSC_RY_GY_1_B) 7011 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 7012 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 7013 _PLANE_INPUT_CSC_RY_GY_2_B) 7014 7015 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 7016 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 7017 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 7018 7019 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 7020 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 7021 7022 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 7023 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 7024 7025 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 7026 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 7027 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 7028 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 7029 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 7030 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 7031 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 7032 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 7033 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 7034 7035 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 7036 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 7037 7038 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 7039 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 7040 7041 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 7042 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 7043 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 7044 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 7045 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 7046 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 7047 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 7048 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 7049 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 7050 7051 #define _PLANE_CTL_1_B 0x71180 7052 #define _PLANE_CTL_2_B 0x71280 7053 #define _PLANE_CTL_3_B 0x71380 7054 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 7055 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 7056 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 7057 #define PLANE_CTL(pipe, plane) \ 7058 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 7059 7060 #define _PLANE_STRIDE_1_B 0x71188 7061 #define _PLANE_STRIDE_2_B 0x71288 7062 #define _PLANE_STRIDE_3_B 0x71388 7063 #define _PLANE_STRIDE_1(pipe) \ 7064 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 7065 #define _PLANE_STRIDE_2(pipe) \ 7066 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 7067 #define _PLANE_STRIDE_3(pipe) \ 7068 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 7069 #define PLANE_STRIDE(pipe, plane) \ 7070 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 7071 7072 #define _PLANE_POS_1_B 0x7118c 7073 #define _PLANE_POS_2_B 0x7128c 7074 #define _PLANE_POS_3_B 0x7138c 7075 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 7076 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 7077 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 7078 #define PLANE_POS(pipe, plane) \ 7079 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 7080 7081 #define _PLANE_SIZE_1_B 0x71190 7082 #define _PLANE_SIZE_2_B 0x71290 7083 #define _PLANE_SIZE_3_B 0x71390 7084 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 7085 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 7086 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 7087 #define PLANE_SIZE(pipe, plane) \ 7088 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 7089 7090 #define _PLANE_SURF_1_B 0x7119c 7091 #define _PLANE_SURF_2_B 0x7129c 7092 #define _PLANE_SURF_3_B 0x7139c 7093 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 7094 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 7095 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 7096 #define PLANE_SURF(pipe, plane) \ 7097 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 7098 7099 #define _PLANE_OFFSET_1_B 0x711a4 7100 #define _PLANE_OFFSET_2_B 0x712a4 7101 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 7102 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 7103 #define PLANE_OFFSET(pipe, plane) \ 7104 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 7105 7106 #define _PLANE_KEYVAL_1_B 0x71194 7107 #define _PLANE_KEYVAL_2_B 0x71294 7108 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 7109 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 7110 #define PLANE_KEYVAL(pipe, plane) \ 7111 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 7112 7113 #define _PLANE_KEYMSK_1_B 0x71198 7114 #define _PLANE_KEYMSK_2_B 0x71298 7115 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 7116 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 7117 #define PLANE_KEYMSK(pipe, plane) \ 7118 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 7119 7120 #define _PLANE_KEYMAX_1_B 0x711a0 7121 #define _PLANE_KEYMAX_2_B 0x712a0 7122 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 7123 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 7124 #define PLANE_KEYMAX(pipe, plane) \ 7125 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 7126 7127 #define _PLANE_BUF_CFG_1_B 0x7127c 7128 #define _PLANE_BUF_CFG_2_B 0x7137c 7129 #define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */ 7130 #define DDB_ENTRY_END_SHIFT 16 7131 #define _PLANE_BUF_CFG_1(pipe) \ 7132 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 7133 #define _PLANE_BUF_CFG_2(pipe) \ 7134 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 7135 #define PLANE_BUF_CFG(pipe, plane) \ 7136 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 7137 7138 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 7139 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 7140 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 7141 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 7142 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 7143 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 7144 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 7145 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 7146 7147 #define _PLANE_AUX_DIST_1_B 0x711c0 7148 #define _PLANE_AUX_DIST_2_B 0x712c0 7149 #define _PLANE_AUX_DIST_1(pipe) \ 7150 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 7151 #define _PLANE_AUX_DIST_2(pipe) \ 7152 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 7153 #define PLANE_AUX_DIST(pipe, plane) \ 7154 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 7155 7156 #define _PLANE_AUX_OFFSET_1_B 0x711c4 7157 #define _PLANE_AUX_OFFSET_2_B 0x712c4 7158 #define _PLANE_AUX_OFFSET_1(pipe) \ 7159 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 7160 #define _PLANE_AUX_OFFSET_2(pipe) \ 7161 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 7162 #define PLANE_AUX_OFFSET(pipe, plane) \ 7163 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 7164 7165 #define _PLANE_CUS_CTL_1_B 0x711c8 7166 #define _PLANE_CUS_CTL_2_B 0x712c8 7167 #define _PLANE_CUS_CTL_1(pipe) \ 7168 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 7169 #define _PLANE_CUS_CTL_2(pipe) \ 7170 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 7171 #define PLANE_CUS_CTL(pipe, plane) \ 7172 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 7173 7174 #define _PLANE_COLOR_CTL_1_B 0x711CC 7175 #define _PLANE_COLOR_CTL_2_B 0x712CC 7176 #define _PLANE_COLOR_CTL_3_B 0x713CC 7177 #define _PLANE_COLOR_CTL_1(pipe) \ 7178 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 7179 #define _PLANE_COLOR_CTL_2(pipe) \ 7180 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 7181 #define PLANE_COLOR_CTL(pipe, plane) \ 7182 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 7183 7184 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 7185 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 7186 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 7187 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 7188 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 7189 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 7190 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 7191 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 7192 #define _SEL_FETCH_PLANE_BASE_1_B 0x70990 7193 7194 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 7195 _SEL_FETCH_PLANE_BASE_1_A, \ 7196 _SEL_FETCH_PLANE_BASE_2_A, \ 7197 _SEL_FETCH_PLANE_BASE_3_A, \ 7198 _SEL_FETCH_PLANE_BASE_4_A, \ 7199 _SEL_FETCH_PLANE_BASE_5_A, \ 7200 _SEL_FETCH_PLANE_BASE_6_A, \ 7201 _SEL_FETCH_PLANE_BASE_7_A, \ 7202 _SEL_FETCH_PLANE_BASE_CUR_A) 7203 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 7204 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 7205 _SEL_FETCH_PLANE_BASE_1_A + \ 7206 _SEL_FETCH_PLANE_BASE_A(plane)) 7207 7208 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 7209 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7210 _SEL_FETCH_PLANE_CTL_1_A - \ 7211 _SEL_FETCH_PLANE_BASE_1_A) 7212 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 7213 7214 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 7215 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7216 _SEL_FETCH_PLANE_POS_1_A - \ 7217 _SEL_FETCH_PLANE_BASE_1_A) 7218 7219 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 7220 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7221 _SEL_FETCH_PLANE_SIZE_1_A - \ 7222 _SEL_FETCH_PLANE_BASE_1_A) 7223 7224 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 7225 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7226 _SEL_FETCH_PLANE_OFFSET_1_A - \ 7227 _SEL_FETCH_PLANE_BASE_1_A) 7228 7229 /* SKL new cursor registers */ 7230 #define _CUR_BUF_CFG_A 0x7017c 7231 #define _CUR_BUF_CFG_B 0x7117c 7232 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 7233 7234 /* VBIOS regs */ 7235 #define VGACNTRL _MMIO(0x71400) 7236 # define VGA_DISP_DISABLE (1 << 31) 7237 # define VGA_2X_MODE (1 << 30) 7238 # define VGA_PIPE_B_SELECT (1 << 29) 7239 7240 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 7241 7242 /* Ironlake */ 7243 7244 #define CPU_VGACNTRL _MMIO(0x41000) 7245 7246 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 7247 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 7248 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 7249 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 7250 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 7251 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 7252 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 7253 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 7254 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 7255 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 7256 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 7257 7258 /* refresh rate hardware control */ 7259 #define RR_HW_CTL _MMIO(0x45300) 7260 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 7261 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 7262 7263 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 7264 #define FDI_PLL_FB_CLOCK_MASK 0xff 7265 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 7266 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 7267 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 7268 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 7269 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 7270 7271 #define PCH_3DCGDIS0 _MMIO(0x46020) 7272 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 7273 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 7274 7275 #define PCH_3DCGDIS1 _MMIO(0x46024) 7276 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 7277 7278 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 7279 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 7280 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 7281 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 7282 7283 7284 #define _PIPEA_DATA_M1 0x60030 7285 #define PIPE_DATA_M1_OFFSET 0 7286 #define _PIPEA_DATA_N1 0x60034 7287 #define PIPE_DATA_N1_OFFSET 0 7288 7289 #define _PIPEA_DATA_M2 0x60038 7290 #define PIPE_DATA_M2_OFFSET 0 7291 #define _PIPEA_DATA_N2 0x6003c 7292 #define PIPE_DATA_N2_OFFSET 0 7293 7294 #define _PIPEA_LINK_M1 0x60040 7295 #define PIPE_LINK_M1_OFFSET 0 7296 #define _PIPEA_LINK_N1 0x60044 7297 #define PIPE_LINK_N1_OFFSET 0 7298 7299 #define _PIPEA_LINK_M2 0x60048 7300 #define PIPE_LINK_M2_OFFSET 0 7301 #define _PIPEA_LINK_N2 0x6004c 7302 #define PIPE_LINK_N2_OFFSET 0 7303 7304 /* PIPEB timing regs are same start from 0x61000 */ 7305 7306 #define _PIPEB_DATA_M1 0x61030 7307 #define _PIPEB_DATA_N1 0x61034 7308 #define _PIPEB_DATA_M2 0x61038 7309 #define _PIPEB_DATA_N2 0x6103c 7310 #define _PIPEB_LINK_M1 0x61040 7311 #define _PIPEB_LINK_N1 0x61044 7312 #define _PIPEB_LINK_M2 0x61048 7313 #define _PIPEB_LINK_N2 0x6104c 7314 7315 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 7316 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 7317 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 7318 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 7319 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 7320 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 7321 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 7322 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 7323 7324 /* CPU panel fitter */ 7325 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 7326 #define _PFA_CTL_1 0x68080 7327 #define _PFB_CTL_1 0x68880 7328 #define PF_ENABLE (1 << 31) 7329 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 7330 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 7331 #define PF_FILTER_MASK (3 << 23) 7332 #define PF_FILTER_PROGRAMMED (0 << 23) 7333 #define PF_FILTER_MED_3x3 (1 << 23) 7334 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 7335 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 7336 #define _PFA_WIN_SZ 0x68074 7337 #define _PFB_WIN_SZ 0x68874 7338 #define _PFA_WIN_POS 0x68070 7339 #define _PFB_WIN_POS 0x68870 7340 #define _PFA_VSCALE 0x68084 7341 #define _PFB_VSCALE 0x68884 7342 #define _PFA_HSCALE 0x68090 7343 #define _PFB_HSCALE 0x68890 7344 7345 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 7346 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 7347 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 7348 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 7349 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 7350 7351 #define _PSA_CTL 0x68180 7352 #define _PSB_CTL 0x68980 7353 #define PS_ENABLE (1 << 31) 7354 #define _PSA_WIN_SZ 0x68174 7355 #define _PSB_WIN_SZ 0x68974 7356 #define _PSA_WIN_POS 0x68170 7357 #define _PSB_WIN_POS 0x68970 7358 7359 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 7360 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 7361 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 7362 7363 /* 7364 * Skylake scalers 7365 */ 7366 #define _PS_1A_CTRL 0x68180 7367 #define _PS_2A_CTRL 0x68280 7368 #define _PS_1B_CTRL 0x68980 7369 #define _PS_2B_CTRL 0x68A80 7370 #define _PS_1C_CTRL 0x69180 7371 #define PS_SCALER_EN (1 << 31) 7372 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 7373 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 7374 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 7375 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 7376 #define PS_SCALER_MODE_PLANAR (1 << 29) 7377 #define PS_SCALER_MODE_NORMAL (0 << 29) 7378 #define PS_PLANE_SEL_MASK (7 << 25) 7379 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 7380 #define PS_FILTER_MASK (3 << 23) 7381 #define PS_FILTER_MEDIUM (0 << 23) 7382 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 7383 #define PS_FILTER_BILINEAR (3 << 23) 7384 #define PS_VERT3TAP (1 << 21) 7385 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 7386 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 7387 #define PS_PWRUP_PROGRESS (1 << 17) 7388 #define PS_V_FILTER_BYPASS (1 << 8) 7389 #define PS_VADAPT_EN (1 << 7) 7390 #define PS_VADAPT_MODE_MASK (3 << 5) 7391 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 7392 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 7393 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 7394 #define PS_PLANE_Y_SEL_MASK (7 << 5) 7395 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 7396 7397 #define _PS_PWR_GATE_1A 0x68160 7398 #define _PS_PWR_GATE_2A 0x68260 7399 #define _PS_PWR_GATE_1B 0x68960 7400 #define _PS_PWR_GATE_2B 0x68A60 7401 #define _PS_PWR_GATE_1C 0x69160 7402 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 7403 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 7404 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 7405 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 7406 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 7407 #define PS_PWR_GATE_SLPEN_8 0 7408 #define PS_PWR_GATE_SLPEN_16 1 7409 #define PS_PWR_GATE_SLPEN_24 2 7410 #define PS_PWR_GATE_SLPEN_32 3 7411 7412 #define _PS_WIN_POS_1A 0x68170 7413 #define _PS_WIN_POS_2A 0x68270 7414 #define _PS_WIN_POS_1B 0x68970 7415 #define _PS_WIN_POS_2B 0x68A70 7416 #define _PS_WIN_POS_1C 0x69170 7417 7418 #define _PS_WIN_SZ_1A 0x68174 7419 #define _PS_WIN_SZ_2A 0x68274 7420 #define _PS_WIN_SZ_1B 0x68974 7421 #define _PS_WIN_SZ_2B 0x68A74 7422 #define _PS_WIN_SZ_1C 0x69174 7423 7424 #define _PS_VSCALE_1A 0x68184 7425 #define _PS_VSCALE_2A 0x68284 7426 #define _PS_VSCALE_1B 0x68984 7427 #define _PS_VSCALE_2B 0x68A84 7428 #define _PS_VSCALE_1C 0x69184 7429 7430 #define _PS_HSCALE_1A 0x68190 7431 #define _PS_HSCALE_2A 0x68290 7432 #define _PS_HSCALE_1B 0x68990 7433 #define _PS_HSCALE_2B 0x68A90 7434 #define _PS_HSCALE_1C 0x69190 7435 7436 #define _PS_VPHASE_1A 0x68188 7437 #define _PS_VPHASE_2A 0x68288 7438 #define _PS_VPHASE_1B 0x68988 7439 #define _PS_VPHASE_2B 0x68A88 7440 #define _PS_VPHASE_1C 0x69188 7441 #define PS_Y_PHASE(x) ((x) << 16) 7442 #define PS_UV_RGB_PHASE(x) ((x) << 0) 7443 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 7444 #define PS_PHASE_TRIP (1 << 0) 7445 7446 #define _PS_HPHASE_1A 0x68194 7447 #define _PS_HPHASE_2A 0x68294 7448 #define _PS_HPHASE_1B 0x68994 7449 #define _PS_HPHASE_2B 0x68A94 7450 #define _PS_HPHASE_1C 0x69194 7451 7452 #define _PS_ECC_STAT_1A 0x681D0 7453 #define _PS_ECC_STAT_2A 0x682D0 7454 #define _PS_ECC_STAT_1B 0x689D0 7455 #define _PS_ECC_STAT_2B 0x68AD0 7456 #define _PS_ECC_STAT_1C 0x691D0 7457 7458 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 7459 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 7460 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 7461 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 7462 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 7463 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 7464 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 7465 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 7466 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 7467 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 7468 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 7469 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 7470 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 7471 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7472 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 7473 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 7474 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7475 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 7476 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 7477 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7478 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 7479 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 7480 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7481 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 7482 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 7483 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 7484 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 7485 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 7486 7487 /* legacy palette */ 7488 #define _LGC_PALETTE_A 0x4a000 7489 #define _LGC_PALETTE_B 0x4a800 7490 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 7491 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 7492 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 7493 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 7494 7495 /* ilk/snb precision palette */ 7496 #define _PREC_PALETTE_A 0x4b000 7497 #define _PREC_PALETTE_B 0x4c000 7498 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 7499 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 7500 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 7501 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 7502 7503 #define _PREC_PIPEAGCMAX 0x4d000 7504 #define _PREC_PIPEBGCMAX 0x4d010 7505 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 7506 7507 #define _GAMMA_MODE_A 0x4a480 7508 #define _GAMMA_MODE_B 0x4ac80 7509 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 7510 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 7511 #define POST_CSC_GAMMA_ENABLE (1 << 30) 7512 #define GAMMA_MODE_MODE_MASK (3 << 0) 7513 #define GAMMA_MODE_MODE_8BIT (0 << 0) 7514 #define GAMMA_MODE_MODE_10BIT (1 << 0) 7515 #define GAMMA_MODE_MODE_12BIT (2 << 0) 7516 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 7517 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 7518 7519 /* DMC/CSR */ 7520 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 7521 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 7522 #define CSR_HTP_ADDR_SKL 0x00500034 7523 #define CSR_SSP_BASE _MMIO(0x8F074) 7524 #define CSR_HTP_SKL _MMIO(0x8F004) 7525 #define CSR_LAST_WRITE _MMIO(0x8F034) 7526 #define CSR_LAST_WRITE_VALUE 0xc003b400 7527 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 7528 #define CSR_MMIO_START_RANGE 0x80000 7529 #define CSR_MMIO_END_RANGE 0x8FFFF 7530 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 7531 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 7532 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 7533 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) 7534 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) 7535 7536 #define DMC_DEBUG3 _MMIO(0x101090) 7537 7538 /* Display Internal Timeout Register */ 7539 #define RM_TIMEOUT _MMIO(0x42060) 7540 #define MMIO_TIMEOUT_US(us) ((us) << 0) 7541 7542 /* interrupts */ 7543 #define DE_MASTER_IRQ_CONTROL (1 << 31) 7544 #define DE_SPRITEB_FLIP_DONE (1 << 29) 7545 #define DE_SPRITEA_FLIP_DONE (1 << 28) 7546 #define DE_PLANEB_FLIP_DONE (1 << 27) 7547 #define DE_PLANEA_FLIP_DONE (1 << 26) 7548 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 7549 #define DE_PCU_EVENT (1 << 25) 7550 #define DE_GTT_FAULT (1 << 24) 7551 #define DE_POISON (1 << 23) 7552 #define DE_PERFORM_COUNTER (1 << 22) 7553 #define DE_PCH_EVENT (1 << 21) 7554 #define DE_AUX_CHANNEL_A (1 << 20) 7555 #define DE_DP_A_HOTPLUG (1 << 19) 7556 #define DE_GSE (1 << 18) 7557 #define DE_PIPEB_VBLANK (1 << 15) 7558 #define DE_PIPEB_EVEN_FIELD (1 << 14) 7559 #define DE_PIPEB_ODD_FIELD (1 << 13) 7560 #define DE_PIPEB_LINE_COMPARE (1 << 12) 7561 #define DE_PIPEB_VSYNC (1 << 11) 7562 #define DE_PIPEB_CRC_DONE (1 << 10) 7563 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 7564 #define DE_PIPEA_VBLANK (1 << 7) 7565 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 7566 #define DE_PIPEA_EVEN_FIELD (1 << 6) 7567 #define DE_PIPEA_ODD_FIELD (1 << 5) 7568 #define DE_PIPEA_LINE_COMPARE (1 << 4) 7569 #define DE_PIPEA_VSYNC (1 << 3) 7570 #define DE_PIPEA_CRC_DONE (1 << 2) 7571 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 7572 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 7573 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 7574 7575 /* More Ivybridge lolz */ 7576 #define DE_ERR_INT_IVB (1 << 30) 7577 #define DE_GSE_IVB (1 << 29) 7578 #define DE_PCH_EVENT_IVB (1 << 28) 7579 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 7580 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 7581 #define DE_EDP_PSR_INT_HSW (1 << 19) 7582 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 7583 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 7584 #define DE_PIPEC_VBLANK_IVB (1 << 10) 7585 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 7586 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 7587 #define DE_PIPEB_VBLANK_IVB (1 << 5) 7588 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 7589 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 7590 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 7591 #define DE_PIPEA_VBLANK_IVB (1 << 0) 7592 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 7593 7594 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 7595 #define MASTER_INTERRUPT_ENABLE (1 << 31) 7596 7597 #define DEISR _MMIO(0x44000) 7598 #define DEIMR _MMIO(0x44004) 7599 #define DEIIR _MMIO(0x44008) 7600 #define DEIER _MMIO(0x4400c) 7601 7602 #define GTISR _MMIO(0x44010) 7603 #define GTIMR _MMIO(0x44014) 7604 #define GTIIR _MMIO(0x44018) 7605 #define GTIER _MMIO(0x4401c) 7606 7607 #define GEN8_MASTER_IRQ _MMIO(0x44200) 7608 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 7609 #define GEN8_PCU_IRQ (1 << 30) 7610 #define GEN8_DE_PCH_IRQ (1 << 23) 7611 #define GEN8_DE_MISC_IRQ (1 << 22) 7612 #define GEN8_DE_PORT_IRQ (1 << 20) 7613 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 7614 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 7615 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 7616 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 7617 #define GEN8_GT_VECS_IRQ (1 << 6) 7618 #define GEN8_GT_GUC_IRQ (1 << 5) 7619 #define GEN8_GT_PM_IRQ (1 << 4) 7620 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 7621 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 7622 #define GEN8_GT_BCS_IRQ (1 << 1) 7623 #define GEN8_GT_RCS_IRQ (1 << 0) 7624 7625 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 7626 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 7627 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 7628 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 7629 7630 #define GEN8_RCS_IRQ_SHIFT 0 7631 #define GEN8_BCS_IRQ_SHIFT 16 7632 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 7633 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 7634 #define GEN8_VECS_IRQ_SHIFT 0 7635 #define GEN8_WD_IRQ_SHIFT 16 7636 7637 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 7638 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 7639 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 7640 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 7641 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 7642 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 7643 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 7644 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 7645 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 7646 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 7647 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 7648 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 7649 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 7650 #define GEN8_PIPE_VSYNC (1 << 1) 7651 #define GEN8_PIPE_VBLANK (1 << 0) 7652 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 7653 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 7654 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 7655 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 7656 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 7657 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 7658 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 7659 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 7660 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 7661 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 7662 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 7663 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 7664 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 7665 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 7666 (GEN8_PIPE_CURSOR_FAULT | \ 7667 GEN8_PIPE_SPRITE_FAULT | \ 7668 GEN8_PIPE_PRIMARY_FAULT) 7669 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 7670 (GEN9_PIPE_CURSOR_FAULT | \ 7671 GEN9_PIPE_PLANE4_FAULT | \ 7672 GEN9_PIPE_PLANE3_FAULT | \ 7673 GEN9_PIPE_PLANE2_FAULT | \ 7674 GEN9_PIPE_PLANE1_FAULT) 7675 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 7676 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 7677 GEN11_PIPE_PLANE7_FAULT | \ 7678 GEN11_PIPE_PLANE6_FAULT | \ 7679 GEN11_PIPE_PLANE5_FAULT) 7680 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 7681 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 7682 GEN11_PIPE_PLANE5_FAULT) 7683 7684 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 7685 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 7686 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 7687 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 7688 #define DSI1_NON_TE (1 << 31) 7689 #define DSI0_NON_TE (1 << 30) 7690 #define ICL_AUX_CHANNEL_E (1 << 29) 7691 #define CNL_AUX_CHANNEL_F (1 << 28) 7692 #define GEN9_AUX_CHANNEL_D (1 << 27) 7693 #define GEN9_AUX_CHANNEL_C (1 << 26) 7694 #define GEN9_AUX_CHANNEL_B (1 << 25) 7695 #define DSI1_TE (1 << 24) 7696 #define DSI0_TE (1 << 23) 7697 #define BXT_DE_PORT_HP_DDIC (1 << 5) 7698 #define BXT_DE_PORT_HP_DDIB (1 << 4) 7699 #define BXT_DE_PORT_HP_DDIA (1 << 3) 7700 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 7701 BXT_DE_PORT_HP_DDIB | \ 7702 BXT_DE_PORT_HP_DDIC) 7703 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 7704 #define BXT_DE_PORT_GMBUS (1 << 1) 7705 #define GEN8_AUX_CHANNEL_A (1 << 0) 7706 #define TGL_DE_PORT_AUX_USBC6 (1 << 13) 7707 #define TGL_DE_PORT_AUX_USBC5 (1 << 12) 7708 #define TGL_DE_PORT_AUX_USBC4 (1 << 11) 7709 #define TGL_DE_PORT_AUX_USBC3 (1 << 10) 7710 #define TGL_DE_PORT_AUX_USBC2 (1 << 9) 7711 #define TGL_DE_PORT_AUX_USBC1 (1 << 8) 7712 #define TGL_DE_PORT_AUX_DDIC (1 << 2) 7713 #define TGL_DE_PORT_AUX_DDIB (1 << 1) 7714 #define TGL_DE_PORT_AUX_DDIA (1 << 0) 7715 7716 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 7717 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 7718 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 7719 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 7720 #define GEN8_DE_MISC_GSE (1 << 27) 7721 #define GEN8_DE_EDP_PSR (1 << 19) 7722 7723 #define GEN8_PCU_ISR _MMIO(0x444e0) 7724 #define GEN8_PCU_IMR _MMIO(0x444e4) 7725 #define GEN8_PCU_IIR _MMIO(0x444e8) 7726 #define GEN8_PCU_IER _MMIO(0x444ec) 7727 7728 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 7729 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 7730 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 7731 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 7732 #define GEN11_GU_MISC_GSE (1 << 27) 7733 7734 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 7735 #define GEN11_MASTER_IRQ (1 << 31) 7736 #define GEN11_PCU_IRQ (1 << 30) 7737 #define GEN11_GU_MISC_IRQ (1 << 29) 7738 #define GEN11_DISPLAY_IRQ (1 << 16) 7739 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 7740 #define GEN11_GT_DW1_IRQ (1 << 1) 7741 #define GEN11_GT_DW0_IRQ (1 << 0) 7742 7743 #define DG1_MSTR_UNIT_INTR _MMIO(0x190008) 7744 #define DG1_MSTR_IRQ REG_BIT(31) 7745 #define DG1_MSTR_UNIT(u) REG_BIT(u) 7746 7747 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 7748 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 7749 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 7750 #define GEN11_DE_PCH_IRQ (1 << 23) 7751 #define GEN11_DE_MISC_IRQ (1 << 22) 7752 #define GEN11_DE_HPD_IRQ (1 << 21) 7753 #define GEN11_DE_PORT_IRQ (1 << 20) 7754 #define GEN11_DE_PIPE_C (1 << 18) 7755 #define GEN11_DE_PIPE_B (1 << 17) 7756 #define GEN11_DE_PIPE_A (1 << 16) 7757 7758 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 7759 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 7760 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 7761 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 7762 #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) 7763 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \ 7764 GEN11_TC_HOTPLUG(PORT_TC5) | \ 7765 GEN11_TC_HOTPLUG(PORT_TC4) | \ 7766 GEN11_TC_HOTPLUG(PORT_TC3) | \ 7767 GEN11_TC_HOTPLUG(PORT_TC2) | \ 7768 GEN11_TC_HOTPLUG(PORT_TC1)) 7769 #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) 7770 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \ 7771 GEN11_TBT_HOTPLUG(PORT_TC5) | \ 7772 GEN11_TBT_HOTPLUG(PORT_TC4) | \ 7773 GEN11_TBT_HOTPLUG(PORT_TC3) | \ 7774 GEN11_TBT_HOTPLUG(PORT_TC2) | \ 7775 GEN11_TBT_HOTPLUG(PORT_TC1)) 7776 7777 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 7778 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 7779 #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) 7780 #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 7781 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 7782 #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) 7783 7784 #define GEN11_GT_INTR_DW0 _MMIO(0x190018) 7785 #define GEN11_CSME (31) 7786 #define GEN11_GUNIT (28) 7787 #define GEN11_GUC (25) 7788 #define GEN11_WDPERF (20) 7789 #define GEN11_KCR (19) 7790 #define GEN11_GTPM (16) 7791 #define GEN11_BCS (15) 7792 #define GEN11_RCS0 (0) 7793 7794 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c) 7795 #define GEN11_VECS(x) (31 - (x)) 7796 #define GEN11_VCS(x) (x) 7797 7798 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) 7799 7800 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) 7801 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) 7802 #define GEN11_INTR_DATA_VALID (1 << 31) 7803 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) 7804 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) 7805 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) 7806 /* irq instances for OTHER_CLASS */ 7807 #define OTHER_GUC_INSTANCE 0 7808 #define OTHER_GTPM_INSTANCE 1 7809 7810 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) 7811 7812 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070) 7813 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074) 7814 7815 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) 7816 7817 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) 7818 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) 7819 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) 7820 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) 7821 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) 7822 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) 7823 7824 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) 7825 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) 7826 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) 7827 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) 7828 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) 7829 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) 7830 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) 7831 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) 7832 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) 7833 7834 #define ENGINE1_MASK REG_GENMASK(31, 16) 7835 #define ENGINE0_MASK REG_GENMASK(15, 0) 7836 7837 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 7838 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 7839 #define ILK_ELPIN_409_SELECT (1 << 25) 7840 #define ILK_DPARB_GATE (1 << 22) 7841 #define ILK_VSDPFD_FULL (1 << 21) 7842 #define FUSE_STRAP _MMIO(0x42014) 7843 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 7844 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 7845 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 7846 #define IVB_PIPE_C_DISABLE (1 << 28) 7847 #define ILK_HDCP_DISABLE (1 << 25) 7848 #define ILK_eDP_A_DISABLE (1 << 24) 7849 #define HSW_CDCLK_LIMIT (1 << 24) 7850 #define ILK_DESKTOP (1 << 23) 7851 #define HSW_CPU_SSC_ENABLE (1 << 21) 7852 7853 #define FUSE_STRAP3 _MMIO(0x42020) 7854 #define HSW_REF_CLK_SELECT (1 << 1) 7855 7856 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 7857 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 7858 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 7859 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 7860 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 7861 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 7862 7863 #define IVB_CHICKEN3 _MMIO(0x4200c) 7864 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 7865 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 7866 7867 #define CHICKEN_PAR1_1 _MMIO(0x42080) 7868 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 7869 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 7870 #define DPA_MASK_VBLANK_SRD (1 << 15) 7871 #define FORCE_ARB_IDLE_PLANES (1 << 14) 7872 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 7873 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 7874 7875 #define CHICKEN_PAR2_1 _MMIO(0x42090) 7876 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 7877 7878 #define CHICKEN_MISC_2 _MMIO(0x42084) 7879 #define CNL_COMP_PWR_DOWN (1 << 23) 7880 #define GLK_CL2_PWR_DOWN (1 << 12) 7881 #define GLK_CL1_PWR_DOWN (1 << 11) 7882 #define GLK_CL0_PWR_DOWN (1 << 10) 7883 7884 #define CHICKEN_MISC_4 _MMIO(0x4208c) 7885 #define FBC_STRIDE_OVERRIDE (1 << 13) 7886 #define FBC_STRIDE_MASK 0x1FFF 7887 7888 #define _CHICKEN_PIPESL_1_A 0x420b0 7889 #define _CHICKEN_PIPESL_1_B 0x420b4 7890 #define HSW_FBCQ_DIS (1 << 22) 7891 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 7892 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 7893 7894 #define _CHICKEN_TRANS_A 0x420c0 7895 #define _CHICKEN_TRANS_B 0x420c4 7896 #define _CHICKEN_TRANS_C 0x420c8 7897 #define _CHICKEN_TRANS_EDP 0x420cc 7898 #define _CHICKEN_TRANS_D 0x420d8 7899 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 7900 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 7901 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 7902 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 7903 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 7904 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 7905 #define HSW_FRAME_START_DELAY_MASK (3 << 27) 7906 #define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 7907 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ 7908 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) 7909 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) 7910 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ 7911 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ 7912 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) 7913 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) 7914 7915 #define DISP_ARB_CTL _MMIO(0x45000) 7916 #define DISP_FBC_MEMORY_WAKE (1 << 31) 7917 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 7918 #define DISP_FBC_WM_DIS (1 << 15) 7919 #define DISP_ARB_CTL2 _MMIO(0x45004) 7920 #define DISP_DATA_PARTITION_5_6 (1 << 6) 7921 #define DISP_IPC_ENABLE (1 << 3) 7922 #define _DBUF_CTL_S1 0x45008 7923 #define _DBUF_CTL_S2 0x44FE8 7924 #define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2)) 7925 #define DBUF_POWER_REQUEST (1 << 31) 7926 #define DBUF_POWER_STATE (1 << 30) 7927 #define GEN7_MSG_CTL _MMIO(0x45010) 7928 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 7929 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 7930 7931 #define _BW_BUDDY0_CTL 0x45130 7932 #define _BW_BUDDY1_CTL 0x45140 7933 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 7934 _BW_BUDDY0_CTL, \ 7935 _BW_BUDDY1_CTL)) 7936 #define BW_BUDDY_DISABLE REG_BIT(31) 7937 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 7938 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 7939 7940 #define _BW_BUDDY0_PAGE_MASK 0x45134 7941 #define _BW_BUDDY1_PAGE_MASK 0x45144 7942 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 7943 _BW_BUDDY0_PAGE_MASK, \ 7944 _BW_BUDDY1_PAGE_MASK)) 7945 7946 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 7947 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 7948 7949 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 7950 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) 7951 #define CNL_DELAY_PMRSP (1 << 22) 7952 #define MASK_WAKEMEM (1 << 13) 7953 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) 7954 7955 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 7956 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 7957 #define DCPR_MASK_LPMODE REG_BIT(26) 7958 #define DCPR_SEND_RESP_IMM REG_BIT(25) 7959 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 7960 7961 #define SKL_DFSM _MMIO(0x51000) 7962 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 7963 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 7964 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 7965 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 7966 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 7967 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 7968 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 7969 #define ICL_DFSM_DMC_DISABLE (1 << 23) 7970 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 7971 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 7972 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 7973 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 7974 #define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 7975 7976 #define SKL_DSSM _MMIO(0x51004) 7977 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) 7978 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 7979 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 7980 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 7981 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 7982 7983 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 7984 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) 7985 7986 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 7987 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) 7988 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) 7989 7990 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 7991 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) 7992 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 7993 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11) 7994 7995 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 7996 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) 7997 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 7998 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 7999 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 8000 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 8001 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 8002 8003 /* GEN7 chicken */ 8004 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 8005 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) 8006 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) 8007 8008 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 8009 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) 8010 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) 8011 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) 8012 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) 8013 8014 #define GEN8_L3CNTLREG _MMIO(0x7034) 8015 #define GEN8_ERRDETBCTRL (1 << 9) 8016 8017 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) 8018 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) 8019 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) 8020 8021 #define HIZ_CHICKEN _MMIO(0x7018) 8022 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) 8023 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) 8024 8025 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 8026 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14) 8027 8028 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 8029 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 8030 8031 #define GEN7_SARCHKMD _MMIO(0xB000) 8032 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) 8033 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) 8034 8035 #define GEN7_L3SQCREG1 _MMIO(0xB010) 8036 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 8037 8038 #define GEN8_L3SQCREG1 _MMIO(0xB100) 8039 /* 8040 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 8041 * Using the formula in BSpec leads to a hang, while the formula here works 8042 * fine and matches the formulas for all other platforms. A BSpec change 8043 * request has been filed to clarify this. 8044 */ 8045 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 8046 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 8047 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 8048 8049 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 8050 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 8051 #define GEN7_L3AGDIS (1 << 19) 8052 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 8053 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 8054 8055 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 8056 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 8057 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114) 8058 #define GEN11_I2M_WRITE_DISABLE (1 << 28) 8059 8060 #define GEN7_L3SQCREG4 _MMIO(0xb034) 8061 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) 8062 8063 #define GEN11_SCRATCH2 _MMIO(0xb140) 8064 #define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19) 8065 8066 #define GEN8_L3SQCREG4 _MMIO(0xb118) 8067 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) 8068 #define GEN8_LQSC_RO_PERF_DIS (1 << 27) 8069 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) 8070 8071 /* GEN8 chicken */ 8072 #define HDC_CHICKEN0 _MMIO(0x7300) 8073 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) 8074 #define ICL_HDC_MODE _MMIO(0xE5F4) 8075 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) 8076 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) 8077 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) 8078 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) 8079 #define HDC_FORCE_NON_COHERENT (1 << 4) 8080 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) 8081 8082 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 8083 8084 /* GEN9 chicken */ 8085 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 8086 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 8087 8088 #define GEN9_WM_CHICKEN3 _MMIO(0x5588) 8089 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) 8090 8091 /* WaCatErrorRejectionIssue */ 8092 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 8093 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) 8094 8095 #define HSW_SCRATCH1 _MMIO(0xb038) 8096 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) 8097 8098 #define BDW_SCRATCH1 _MMIO(0xb11c) 8099 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) 8100 8101 /*GEN11 chicken */ 8102 #define _PIPEA_CHICKEN 0x70038 8103 #define _PIPEB_CHICKEN 0x71038 8104 #define _PIPEC_CHICKEN 0x72038 8105 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 8106 _PIPEB_CHICKEN) 8107 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) 8108 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) 8109 8110 #define FF_MODE2 _MMIO(0x6604) 8111 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 8112 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 8113 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 8114 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 8115 8116 /* PCH */ 8117 8118 #define PCH_DISPLAY_BASE 0xc0000u 8119 8120 /* south display engine interrupt: IBX */ 8121 #define SDE_AUDIO_POWER_D (1 << 27) 8122 #define SDE_AUDIO_POWER_C (1 << 26) 8123 #define SDE_AUDIO_POWER_B (1 << 25) 8124 #define SDE_AUDIO_POWER_SHIFT (25) 8125 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 8126 #define SDE_GMBUS (1 << 24) 8127 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 8128 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 8129 #define SDE_AUDIO_HDCP_MASK (3 << 22) 8130 #define SDE_AUDIO_TRANSB (1 << 21) 8131 #define SDE_AUDIO_TRANSA (1 << 20) 8132 #define SDE_AUDIO_TRANS_MASK (3 << 20) 8133 #define SDE_POISON (1 << 19) 8134 /* 18 reserved */ 8135 #define SDE_FDI_RXB (1 << 17) 8136 #define SDE_FDI_RXA (1 << 16) 8137 #define SDE_FDI_MASK (3 << 16) 8138 #define SDE_AUXD (1 << 15) 8139 #define SDE_AUXC (1 << 14) 8140 #define SDE_AUXB (1 << 13) 8141 #define SDE_AUX_MASK (7 << 13) 8142 /* 12 reserved */ 8143 #define SDE_CRT_HOTPLUG (1 << 11) 8144 #define SDE_PORTD_HOTPLUG (1 << 10) 8145 #define SDE_PORTC_HOTPLUG (1 << 9) 8146 #define SDE_PORTB_HOTPLUG (1 << 8) 8147 #define SDE_SDVOB_HOTPLUG (1 << 6) 8148 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 8149 SDE_SDVOB_HOTPLUG | \ 8150 SDE_PORTB_HOTPLUG | \ 8151 SDE_PORTC_HOTPLUG | \ 8152 SDE_PORTD_HOTPLUG) 8153 #define SDE_TRANSB_CRC_DONE (1 << 5) 8154 #define SDE_TRANSB_CRC_ERR (1 << 4) 8155 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 8156 #define SDE_TRANSA_CRC_DONE (1 << 2) 8157 #define SDE_TRANSA_CRC_ERR (1 << 1) 8158 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 8159 #define SDE_TRANS_MASK (0x3f) 8160 8161 /* south display engine interrupt: CPT - CNP */ 8162 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 8163 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 8164 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 8165 #define SDE_AUDIO_POWER_SHIFT_CPT 29 8166 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 8167 #define SDE_AUXD_CPT (1 << 27) 8168 #define SDE_AUXC_CPT (1 << 26) 8169 #define SDE_AUXB_CPT (1 << 25) 8170 #define SDE_AUX_MASK_CPT (7 << 25) 8171 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 8172 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 8173 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 8174 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 8175 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 8176 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 8177 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 8178 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 8179 SDE_SDVOB_HOTPLUG_CPT | \ 8180 SDE_PORTD_HOTPLUG_CPT | \ 8181 SDE_PORTC_HOTPLUG_CPT | \ 8182 SDE_PORTB_HOTPLUG_CPT) 8183 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 8184 SDE_PORTD_HOTPLUG_CPT | \ 8185 SDE_PORTC_HOTPLUG_CPT | \ 8186 SDE_PORTB_HOTPLUG_CPT | \ 8187 SDE_PORTA_HOTPLUG_SPT) 8188 #define SDE_GMBUS_CPT (1 << 17) 8189 #define SDE_ERROR_CPT (1 << 16) 8190 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 8191 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 8192 #define SDE_FDI_RXC_CPT (1 << 8) 8193 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 8194 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 8195 #define SDE_FDI_RXB_CPT (1 << 4) 8196 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 8197 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 8198 #define SDE_FDI_RXA_CPT (1 << 0) 8199 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 8200 SDE_AUDIO_CP_REQ_B_CPT | \ 8201 SDE_AUDIO_CP_REQ_A_CPT) 8202 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 8203 SDE_AUDIO_CP_CHG_B_CPT | \ 8204 SDE_AUDIO_CP_CHG_A_CPT) 8205 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 8206 SDE_FDI_RXB_CPT | \ 8207 SDE_FDI_RXA_CPT) 8208 8209 /* south display engine interrupt: ICP/TGP */ 8210 #define SDE_GMBUS_ICP (1 << 23) 8211 #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) 8212 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) 8213 #define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \ 8214 SDE_DDI_HOTPLUG_ICP(PORT_A)) 8215 #define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \ 8216 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ 8217 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ 8218 SDE_TC_HOTPLUG_ICP(PORT_TC1)) 8219 #define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \ 8220 SDE_DDI_HOTPLUG_ICP(PORT_B) | \ 8221 SDE_DDI_HOTPLUG_ICP(PORT_A)) 8222 #define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \ 8223 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \ 8224 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \ 8225 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ 8226 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ 8227 SDE_TC_HOTPLUG_ICP(PORT_TC1)) 8228 8229 #define SDEISR _MMIO(0xc4000) 8230 #define SDEIMR _MMIO(0xc4004) 8231 #define SDEIIR _MMIO(0xc4008) 8232 #define SDEIER _MMIO(0xc400c) 8233 8234 #define SERR_INT _MMIO(0xc4040) 8235 #define SERR_INT_POISON (1 << 31) 8236 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 8237 8238 /* digital port hotplug */ 8239 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 8240 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 8241 #define BXT_DDIA_HPD_INVERT (1 << 27) 8242 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 8243 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 8244 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 8245 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 8246 #define PORTD_HOTPLUG_ENABLE (1 << 20) 8247 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 8248 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 8249 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 8250 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 8251 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 8252 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 8253 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 8254 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 8255 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 8256 #define PORTC_HOTPLUG_ENABLE (1 << 12) 8257 #define BXT_DDIC_HPD_INVERT (1 << 11) 8258 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 8259 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 8260 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 8261 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 8262 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 8263 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 8264 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 8265 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 8266 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 8267 #define PORTB_HOTPLUG_ENABLE (1 << 4) 8268 #define BXT_DDIB_HPD_INVERT (1 << 3) 8269 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 8270 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 8271 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 8272 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 8273 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 8274 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 8275 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 8276 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 8277 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 8278 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 8279 BXT_DDIB_HPD_INVERT | \ 8280 BXT_DDIC_HPD_INVERT) 8281 8282 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 8283 #define PORTE_HOTPLUG_ENABLE (1 << 4) 8284 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 8285 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 8286 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 8287 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 8288 8289 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 8290 * functionality covered in PCH_PORT_HOTPLUG is split into 8291 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 8292 */ 8293 8294 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 8295 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port))) 8296 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port))) 8297 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port))) 8298 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port))) 8299 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port))) 8300 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port))) 8301 8302 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 8303 #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) 8304 8305 #define SHPD_FILTER_CNT _MMIO(0xc4038) 8306 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 8307 8308 /* Icelake DSC Rate Control Range Parameter Registers */ 8309 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 8310 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 8311 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 8312 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 8313 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 8314 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 8315 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 8316 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 8317 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 8318 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 8319 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 8320 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 8321 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8322 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 8323 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 8324 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8325 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 8326 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 8327 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8328 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 8329 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 8330 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8331 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 8332 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 8333 #define RC_BPG_OFFSET_SHIFT 10 8334 #define RC_MAX_QP_SHIFT 5 8335 #define RC_MIN_QP_SHIFT 0 8336 8337 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 8338 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 8339 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 8340 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 8341 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 8342 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 8343 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 8344 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 8345 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 8346 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 8347 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 8348 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 8349 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8350 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 8351 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 8352 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8353 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 8354 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 8355 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8356 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 8357 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 8358 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8359 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 8360 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 8361 8362 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 8363 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 8364 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 8365 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 8366 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 8367 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 8368 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 8369 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 8370 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 8371 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 8372 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 8373 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 8374 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8375 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 8376 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 8377 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8378 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 8379 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 8380 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8381 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 8382 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 8383 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8384 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 8385 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 8386 8387 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 8388 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 8389 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 8390 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 8391 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 8392 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 8393 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 8394 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 8395 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 8396 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 8397 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 8398 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 8399 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8400 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 8401 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 8402 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8403 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8404 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 8405 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8406 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 8407 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 8408 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8409 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8410 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 8411 8412 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 8413 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 8414 8415 #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ 8416 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) 8417 #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \ 8418 ICP_TC_HPD_ENABLE(PORT_TC3) | \ 8419 ICP_TC_HPD_ENABLE(PORT_TC2) | \ 8420 ICP_TC_HPD_ENABLE(PORT_TC1)) 8421 #define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ 8422 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ 8423 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) 8424 #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ 8425 ICP_TC_HPD_ENABLE(PORT_TC5) | \ 8426 ICP_TC_HPD_ENABLE_MASK) 8427 8428 #define _PCH_DPLL_A 0xc6014 8429 #define _PCH_DPLL_B 0xc6018 8430 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 8431 8432 #define _PCH_FPA0 0xc6040 8433 #define FP_CB_TUNE (0x3 << 22) 8434 #define _PCH_FPA1 0xc6044 8435 #define _PCH_FPB0 0xc6048 8436 #define _PCH_FPB1 0xc604c 8437 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 8438 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 8439 8440 #define PCH_DPLL_TEST _MMIO(0xc606c) 8441 8442 #define PCH_DREF_CONTROL _MMIO(0xC6200) 8443 #define DREF_CONTROL_MASK 0x7fc3 8444 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 8445 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 8446 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 8447 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 8448 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 8449 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 8450 #define DREF_SSC_SOURCE_MASK (3 << 11) 8451 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 8452 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 8453 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 8454 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 8455 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 8456 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 8457 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 8458 #define DREF_SSC4_DOWNSPREAD (0 << 6) 8459 #define DREF_SSC4_CENTERSPREAD (1 << 6) 8460 #define DREF_SSC1_DISABLE (0 << 1) 8461 #define DREF_SSC1_ENABLE (1 << 1) 8462 #define DREF_SSC4_DISABLE (0) 8463 #define DREF_SSC4_ENABLE (1) 8464 8465 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 8466 #define FDL_TP1_TIMER_SHIFT 12 8467 #define FDL_TP1_TIMER_MASK (3 << 12) 8468 #define FDL_TP2_TIMER_SHIFT 10 8469 #define FDL_TP2_TIMER_MASK (3 << 10) 8470 #define RAWCLK_FREQ_MASK 0x3ff 8471 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 8472 #define CNP_RAWCLK_DIV(div) ((div) << 16) 8473 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 8474 #define CNP_RAWCLK_DEN(den) ((den) << 26) 8475 #define ICP_RAWCLK_NUM(num) ((num) << 11) 8476 8477 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 8478 8479 #define PCH_SSC4_PARMS _MMIO(0xc6210) 8480 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 8481 8482 #define PCH_DPLL_SEL _MMIO(0xc7000) 8483 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 8484 #define TRANS_DPLLA_SEL(pipe) 0 8485 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 8486 8487 /* transcoder */ 8488 8489 #define _PCH_TRANS_HTOTAL_A 0xe0000 8490 #define TRANS_HTOTAL_SHIFT 16 8491 #define TRANS_HACTIVE_SHIFT 0 8492 #define _PCH_TRANS_HBLANK_A 0xe0004 8493 #define TRANS_HBLANK_END_SHIFT 16 8494 #define TRANS_HBLANK_START_SHIFT 0 8495 #define _PCH_TRANS_HSYNC_A 0xe0008 8496 #define TRANS_HSYNC_END_SHIFT 16 8497 #define TRANS_HSYNC_START_SHIFT 0 8498 #define _PCH_TRANS_VTOTAL_A 0xe000c 8499 #define TRANS_VTOTAL_SHIFT 16 8500 #define TRANS_VACTIVE_SHIFT 0 8501 #define _PCH_TRANS_VBLANK_A 0xe0010 8502 #define TRANS_VBLANK_END_SHIFT 16 8503 #define TRANS_VBLANK_START_SHIFT 0 8504 #define _PCH_TRANS_VSYNC_A 0xe0014 8505 #define TRANS_VSYNC_END_SHIFT 16 8506 #define TRANS_VSYNC_START_SHIFT 0 8507 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 8508 8509 #define _PCH_TRANSA_DATA_M1 0xe0030 8510 #define _PCH_TRANSA_DATA_N1 0xe0034 8511 #define _PCH_TRANSA_DATA_M2 0xe0038 8512 #define _PCH_TRANSA_DATA_N2 0xe003c 8513 #define _PCH_TRANSA_LINK_M1 0xe0040 8514 #define _PCH_TRANSA_LINK_N1 0xe0044 8515 #define _PCH_TRANSA_LINK_M2 0xe0048 8516 #define _PCH_TRANSA_LINK_N2 0xe004c 8517 8518 /* Per-transcoder DIP controls (PCH) */ 8519 #define _VIDEO_DIP_CTL_A 0xe0200 8520 #define _VIDEO_DIP_DATA_A 0xe0208 8521 #define _VIDEO_DIP_GCP_A 0xe0210 8522 #define GCP_COLOR_INDICATION (1 << 2) 8523 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 8524 #define GCP_AV_MUTE (1 << 0) 8525 8526 #define _VIDEO_DIP_CTL_B 0xe1200 8527 #define _VIDEO_DIP_DATA_B 0xe1208 8528 #define _VIDEO_DIP_GCP_B 0xe1210 8529 8530 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 8531 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 8532 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 8533 8534 /* Per-transcoder DIP controls (VLV) */ 8535 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 8536 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 8537 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 8538 8539 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 8540 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 8541 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 8542 8543 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 8544 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 8545 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 8546 8547 #define VLV_TVIDEO_DIP_CTL(pipe) \ 8548 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 8549 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 8550 #define VLV_TVIDEO_DIP_DATA(pipe) \ 8551 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 8552 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 8553 #define VLV_TVIDEO_DIP_GCP(pipe) \ 8554 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 8555 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 8556 8557 /* Haswell DIP controls */ 8558 8559 #define _HSW_VIDEO_DIP_CTL_A 0x60200 8560 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 8561 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 8562 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 8563 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 8564 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 8565 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 8566 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 8567 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 8568 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 8569 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 8570 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 8571 #define _HSW_VIDEO_DIP_GCP_A 0x60210 8572 8573 #define _HSW_VIDEO_DIP_CTL_B 0x61200 8574 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 8575 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 8576 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 8577 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 8578 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 8579 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 8580 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 8581 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 8582 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 8583 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 8584 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 8585 #define _HSW_VIDEO_DIP_GCP_B 0x61210 8586 8587 /* Icelake PPS_DATA and _ECC DIP Registers. 8588 * These are available for transcoders B,C and eDP. 8589 * Adding the _A so as to reuse the _MMIO_TRANS2 8590 * definition, with which it offsets to the right location. 8591 */ 8592 8593 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 8594 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 8595 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 8596 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 8597 8598 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 8599 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 8600 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 8601 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 8602 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 8603 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 8604 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 8605 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 8606 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 8607 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 8608 8609 #define _HSW_STEREO_3D_CTL_A 0x70020 8610 #define S3D_ENABLE (1 << 31) 8611 #define _HSW_STEREO_3D_CTL_B 0x71020 8612 8613 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 8614 8615 #define _PCH_TRANS_HTOTAL_B 0xe1000 8616 #define _PCH_TRANS_HBLANK_B 0xe1004 8617 #define _PCH_TRANS_HSYNC_B 0xe1008 8618 #define _PCH_TRANS_VTOTAL_B 0xe100c 8619 #define _PCH_TRANS_VBLANK_B 0xe1010 8620 #define _PCH_TRANS_VSYNC_B 0xe1014 8621 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 8622 8623 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 8624 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 8625 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 8626 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 8627 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 8628 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 8629 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 8630 8631 #define _PCH_TRANSB_DATA_M1 0xe1030 8632 #define _PCH_TRANSB_DATA_N1 0xe1034 8633 #define _PCH_TRANSB_DATA_M2 0xe1038 8634 #define _PCH_TRANSB_DATA_N2 0xe103c 8635 #define _PCH_TRANSB_LINK_M1 0xe1040 8636 #define _PCH_TRANSB_LINK_N1 0xe1044 8637 #define _PCH_TRANSB_LINK_M2 0xe1048 8638 #define _PCH_TRANSB_LINK_N2 0xe104c 8639 8640 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 8641 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 8642 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 8643 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 8644 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 8645 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 8646 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 8647 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 8648 8649 #define _PCH_TRANSACONF 0xf0008 8650 #define _PCH_TRANSBCONF 0xf1008 8651 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 8652 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 8653 #define TRANS_DISABLE (0 << 31) 8654 #define TRANS_ENABLE (1 << 31) 8655 #define TRANS_STATE_MASK (1 << 30) 8656 #define TRANS_STATE_DISABLE (0 << 30) 8657 #define TRANS_STATE_ENABLE (1 << 30) 8658 #define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */ 8659 #define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */ 8660 #define TRANS_INTERLACE_MASK (7 << 21) 8661 #define TRANS_PROGRESSIVE (0 << 21) 8662 #define TRANS_INTERLACED (3 << 21) 8663 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21) 8664 #define TRANS_8BPC (0 << 5) 8665 #define TRANS_10BPC (1 << 5) 8666 #define TRANS_6BPC (2 << 5) 8667 #define TRANS_12BPC (3 << 5) 8668 8669 #define _TRANSA_CHICKEN1 0xf0060 8670 #define _TRANSB_CHICKEN1 0xf1060 8671 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 8672 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 8673 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 8674 #define _TRANSA_CHICKEN2 0xf0064 8675 #define _TRANSB_CHICKEN2 0xf1064 8676 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 8677 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 8678 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 8679 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 8680 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 8681 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 8682 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 8683 8684 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 8685 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 8686 #define FDIA_PHASE_SYNC_SHIFT_EN 18 8687 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 8688 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 8689 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 8690 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 8691 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 8692 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 8693 #define SPT_PWM_GRANULARITY (1 << 0) 8694 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 8695 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 8696 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 8697 #define LPT_PWM_GRANULARITY (1 << 5) 8698 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 8699 8700 #define _FDI_RXA_CHICKEN 0xc200c 8701 #define _FDI_RXB_CHICKEN 0xc2010 8702 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 8703 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 8704 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 8705 8706 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 8707 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 8708 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 8709 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 8710 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 8711 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 8712 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 8713 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 8714 8715 /* CPU: FDI_TX */ 8716 #define _FDI_TXA_CTL 0x60100 8717 #define _FDI_TXB_CTL 0x61100 8718 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 8719 #define FDI_TX_DISABLE (0 << 31) 8720 #define FDI_TX_ENABLE (1 << 31) 8721 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 8722 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 8723 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 8724 #define FDI_LINK_TRAIN_NONE (3 << 28) 8725 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 8726 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 8727 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 8728 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 8729 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 8730 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 8731 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 8732 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 8733 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 8734 SNB has different settings. */ 8735 /* SNB A-stepping */ 8736 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8737 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8738 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8739 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8740 /* SNB B-stepping */ 8741 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 8742 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 8743 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 8744 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 8745 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 8746 #define FDI_DP_PORT_WIDTH_SHIFT 19 8747 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 8748 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 8749 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 8750 /* Ironlake: hardwired to 1 */ 8751 #define FDI_TX_PLL_ENABLE (1 << 14) 8752 8753 /* Ivybridge has different bits for lolz */ 8754 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 8755 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 8756 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 8757 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 8758 8759 /* both Tx and Rx */ 8760 #define FDI_COMPOSITE_SYNC (1 << 11) 8761 #define FDI_LINK_TRAIN_AUTO (1 << 10) 8762 #define FDI_SCRAMBLING_ENABLE (0 << 7) 8763 #define FDI_SCRAMBLING_DISABLE (1 << 7) 8764 8765 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 8766 #define _FDI_RXA_CTL 0xf000c 8767 #define _FDI_RXB_CTL 0xf100c 8768 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 8769 #define FDI_RX_ENABLE (1 << 31) 8770 /* train, dp width same as FDI_TX */ 8771 #define FDI_FS_ERRC_ENABLE (1 << 27) 8772 #define FDI_FE_ERRC_ENABLE (1 << 26) 8773 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 8774 #define FDI_8BPC (0 << 16) 8775 #define FDI_10BPC (1 << 16) 8776 #define FDI_6BPC (2 << 16) 8777 #define FDI_12BPC (3 << 16) 8778 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 8779 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 8780 #define FDI_RX_PLL_ENABLE (1 << 13) 8781 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 8782 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 8783 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 8784 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 8785 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 8786 #define FDI_PCDCLK (1 << 4) 8787 /* CPT */ 8788 #define FDI_AUTO_TRAINING (1 << 10) 8789 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 8790 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 8791 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 8792 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 8793 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 8794 8795 #define _FDI_RXA_MISC 0xf0010 8796 #define _FDI_RXB_MISC 0xf1010 8797 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 8798 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 8799 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 8800 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 8801 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 8802 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 8803 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 8804 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 8805 8806 #define _FDI_RXA_TUSIZE1 0xf0030 8807 #define _FDI_RXA_TUSIZE2 0xf0038 8808 #define _FDI_RXB_TUSIZE1 0xf1030 8809 #define _FDI_RXB_TUSIZE2 0xf1038 8810 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 8811 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 8812 8813 /* FDI_RX interrupt register format */ 8814 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 8815 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 8816 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 8817 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 8818 #define FDI_RX_FS_CODE_ERR (1 << 6) 8819 #define FDI_RX_FE_CODE_ERR (1 << 5) 8820 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 8821 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 8822 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 8823 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 8824 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 8825 8826 #define _FDI_RXA_IIR 0xf0014 8827 #define _FDI_RXA_IMR 0xf0018 8828 #define _FDI_RXB_IIR 0xf1014 8829 #define _FDI_RXB_IMR 0xf1018 8830 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 8831 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 8832 8833 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 8834 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 8835 8836 #define PCH_LVDS _MMIO(0xe1180) 8837 #define LVDS_DETECTED (1 << 1) 8838 8839 #define _PCH_DP_B 0xe4100 8840 #define PCH_DP_B _MMIO(_PCH_DP_B) 8841 #define _PCH_DPB_AUX_CH_CTL 0xe4110 8842 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 8843 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 8844 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 8845 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 8846 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 8847 8848 #define _PCH_DP_C 0xe4200 8849 #define PCH_DP_C _MMIO(_PCH_DP_C) 8850 #define _PCH_DPC_AUX_CH_CTL 0xe4210 8851 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 8852 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 8853 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 8854 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 8855 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 8856 8857 #define _PCH_DP_D 0xe4300 8858 #define PCH_DP_D _MMIO(_PCH_DP_D) 8859 #define _PCH_DPD_AUX_CH_CTL 0xe4310 8860 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 8861 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 8862 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 8863 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 8864 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 8865 8866 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 8867 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 8868 8869 /* CPT */ 8870 #define _TRANS_DP_CTL_A 0xe0300 8871 #define _TRANS_DP_CTL_B 0xe1300 8872 #define _TRANS_DP_CTL_C 0xe2300 8873 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 8874 #define TRANS_DP_OUTPUT_ENABLE (1 << 31) 8875 #define TRANS_DP_PORT_SEL_MASK (3 << 29) 8876 #define TRANS_DP_PORT_SEL_NONE (3 << 29) 8877 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29) 8878 #define TRANS_DP_AUDIO_ONLY (1 << 26) 8879 #define TRANS_DP_ENH_FRAMING (1 << 18) 8880 #define TRANS_DP_8BPC (0 << 9) 8881 #define TRANS_DP_10BPC (1 << 9) 8882 #define TRANS_DP_6BPC (2 << 9) 8883 #define TRANS_DP_12BPC (3 << 9) 8884 #define TRANS_DP_BPC_MASK (3 << 9) 8885 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4) 8886 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 8887 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3) 8888 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 8889 #define TRANS_DP_SYNC_MASK (3 << 3) 8890 8891 /* SNB eDP training params */ 8892 /* SNB A-stepping */ 8893 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8894 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8895 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8896 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8897 /* SNB B-stepping */ 8898 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 8899 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 8900 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 8901 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 8902 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 8903 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 8904 8905 /* IVB */ 8906 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 8907 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 8908 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 8909 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 8910 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 8911 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 8912 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 8913 8914 /* legacy values */ 8915 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 8916 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 8917 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 8918 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 8919 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 8920 8921 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 8922 8923 #define VLV_PMWGICZ _MMIO(0x1300a4) 8924 8925 #define RC6_LOCATION _MMIO(0xD40) 8926 #define RC6_CTX_IN_DRAM (1 << 0) 8927 #define RC6_CTX_BASE _MMIO(0xD48) 8928 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 8929 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 8930 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 8931 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 8932 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 8933 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 8934 #define IDLE_TIME_MASK 0xFFFFF 8935 #define FORCEWAKE _MMIO(0xA18C) 8936 #define FORCEWAKE_VLV _MMIO(0x1300b0) 8937 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 8938 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 8939 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 8940 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 8941 #define FORCEWAKE_ACK _MMIO(0x130090) 8942 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 8943 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 8944 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 8945 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 8946 8947 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 8948 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 8949 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 8950 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 8951 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 8952 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 8953 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 8954 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) 8955 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) 8956 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 8957 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 8958 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 8959 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) 8960 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) 8961 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 8962 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 8963 #define FORCEWAKE_KERNEL BIT(0) 8964 #define FORCEWAKE_USER BIT(1) 8965 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 8966 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 8967 #define ECOBUS _MMIO(0xa180) 8968 #define FORCEWAKE_MT_ENABLE (1 << 5) 8969 #define VLV_SPAREG2H _MMIO(0xA194) 8970 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) 8971 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 8972 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 8973 8974 #define POWERGATE_ENABLE _MMIO(0xa210) 8975 #define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3) 8976 #define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4) 8977 8978 #define GTFIFODBG _MMIO(0x120000) 8979 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 8980 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 8981 #define GT_FIFO_SBDROPERR (1 << 6) 8982 #define GT_FIFO_BLOBDROPERR (1 << 5) 8983 #define GT_FIFO_SB_READ_ABORTERR (1 << 4) 8984 #define GT_FIFO_DROPERR (1 << 3) 8985 #define GT_FIFO_OVFERR (1 << 2) 8986 #define GT_FIFO_IAWRERR (1 << 1) 8987 #define GT_FIFO_IARDERR (1 << 0) 8988 8989 #define GTFIFOCTL _MMIO(0x120008) 8990 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 8991 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 8992 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 8993 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 8994 8995 #define HSW_IDICR _MMIO(0x9008) 8996 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 8997 #define HSW_EDRAM_CAP _MMIO(0x120010) 8998 #define EDRAM_ENABLED 0x1 8999 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 9000 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 9001 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 9002 9003 #define GEN6_UCGCTL1 _MMIO(0x9400) 9004 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 9005 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 9006 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 9007 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 9008 9009 #define GEN6_UCGCTL2 _MMIO(0x9404) 9010 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 9011 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 9012 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 9013 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 9014 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 9015 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 9016 9017 #define GEN6_UCGCTL3 _MMIO(0x9408) 9018 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 9019 9020 #define GEN7_UCGCTL4 _MMIO(0x940c) 9021 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) 9022 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) 9023 9024 #define GEN6_RCGCTL1 _MMIO(0x9410) 9025 #define GEN6_RCGCTL2 _MMIO(0x9414) 9026 #define GEN6_RSTCTL _MMIO(0x9420) 9027 9028 #define GEN8_UCGCTL6 _MMIO(0x9430) 9029 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) 9030 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) 9031 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) 9032 9033 #define GEN6_GFXPAUSE _MMIO(0xA000) 9034 #define GEN6_RPNSWREQ _MMIO(0xA008) 9035 #define GEN6_TURBO_DISABLE (1 << 31) 9036 #define GEN6_FREQUENCY(x) ((x) << 25) 9037 #define HSW_FREQUENCY(x) ((x) << 24) 9038 #define GEN9_FREQUENCY(x) ((x) << 23) 9039 #define GEN6_OFFSET(x) ((x) << 19) 9040 #define GEN6_AGGRESSIVE_TURBO (0 << 15) 9041 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 9042 #define GEN6_RC_CONTROL _MMIO(0xA090) 9043 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) 9044 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) 9045 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18) 9046 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) 9047 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22) 9048 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) 9049 #define GEN7_RC_CTL_TO_MODE (1 << 28) 9050 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) 9051 #define GEN6_RC_CTL_HW_ENABLE (1 << 31) 9052 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 9053 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 9054 #define GEN6_RPSTAT1 _MMIO(0xA01C) 9055 #define GEN6_CAGF_SHIFT 8 9056 #define HSW_CAGF_SHIFT 7 9057 #define GEN9_CAGF_SHIFT 23 9058 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 9059 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 9060 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 9061 #define GEN6_RP_CONTROL _MMIO(0xA024) 9062 #define GEN6_RP_MEDIA_TURBO (1 << 11) 9063 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9) 9064 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) 9065 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) 9066 #define GEN6_RP_MEDIA_HW_MODE (1 << 9) 9067 #define GEN6_RP_MEDIA_SW_MODE (0 << 9) 9068 #define GEN6_RP_MEDIA_IS_GFX (1 << 8) 9069 #define GEN6_RP_ENABLE (1 << 7) 9070 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3) 9071 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3) 9072 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) 9073 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) 9074 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) 9075 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 9076 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 9077 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 9078 #define GEN6_RP_EI_MASK 0xffffff 9079 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 9080 #define GEN6_RP_CUR_UP _MMIO(0xA054) 9081 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 9082 #define GEN6_RP_PREV_UP _MMIO(0xA058) 9083 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 9084 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 9085 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 9086 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 9087 #define GEN6_RP_UP_EI _MMIO(0xA068) 9088 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 9089 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 9090 #define GEN6_RPDEUHWTC _MMIO(0xA080) 9091 #define GEN6_RPDEUC _MMIO(0xA084) 9092 #define GEN6_RPDEUCSW _MMIO(0xA088) 9093 #define GEN6_RC_STATE _MMIO(0xA094) 9094 #define RC_SW_TARGET_STATE_SHIFT 16 9095 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 9096 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 9097 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 9098 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 9099 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0) 9100 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 9101 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 9102 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 9103 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 9104 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 9105 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 9106 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 9107 #define VLV_RCEDATA _MMIO(0xA0BC) 9108 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 9109 #define GEN6_PMINTRMSK _MMIO(0xA168) 9110 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) 9111 #define ARAT_EXPIRED_INTRMSK (1 << 9) 9112 #define GEN8_MISC_CTRL0 _MMIO(0xA180) 9113 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 9114 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 9115 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 9116 #define GEN9_PG_ENABLE _MMIO(0xA210) 9117 #define GEN9_RENDER_PG_ENABLE REG_BIT(0) 9118 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1) 9119 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2) 9120 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 9121 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 9122 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 9123 9124 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 9125 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 9126 #define PIXEL_OVERLAP_CNT_SHIFT 30 9127 9128 #define GEN6_PMISR _MMIO(0x44020) 9129 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 9130 #define GEN6_PMIIR _MMIO(0x44028) 9131 #define GEN6_PMIER _MMIO(0x4402C) 9132 #define GEN6_PM_MBOX_EVENT (1 << 25) 9133 #define GEN6_PM_THERMAL_EVENT (1 << 24) 9134 9135 /* 9136 * For Gen11 these are in the upper word of the GPM_WGBOXPERF 9137 * registers. Shifting is handled on accessing the imr and ier. 9138 */ 9139 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) 9140 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5) 9141 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) 9142 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) 9143 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) 9144 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \ 9145 GEN6_PM_RP_UP_THRESHOLD | \ 9146 GEN6_PM_RP_DOWN_EI_EXPIRED | \ 9147 GEN6_PM_RP_DOWN_THRESHOLD | \ 9148 GEN6_PM_RP_DOWN_TIMEOUT) 9149 9150 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 9151 #define GEN7_GT_SCRATCH_REG_NUM 8 9152 9153 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 9154 #define VLV_GFX_CLK_STATUS_BIT (1 << 3) 9155 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) 9156 9157 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 9158 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 9159 #define VLV_COUNT_RANGE_HIGH (1 << 15) 9160 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5) 9161 #define VLV_RENDER_RC0_COUNT_EN (1 << 4) 9162 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) 9163 #define VLV_RENDER_RC6_COUNT_EN (1 << 0) 9164 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 9165 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 9166 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 9167 9168 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 9169 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 9170 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 9171 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 9172 9173 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 9174 #define GEN6_PCODE_READY (1 << 31) 9175 #define GEN6_PCODE_ERROR_MASK 0xFF 9176 #define GEN6_PCODE_SUCCESS 0x0 9177 #define GEN6_PCODE_ILLEGAL_CMD 0x1 9178 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 9179 #define GEN6_PCODE_TIMEOUT 0x3 9180 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 9181 #define GEN7_PCODE_TIMEOUT 0x2 9182 #define GEN7_PCODE_ILLEGAL_DATA 0x3 9183 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 9184 #define GEN11_PCODE_LOCKED 0x6 9185 #define GEN11_PCODE_REJECTED 0x11 9186 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 9187 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 9188 #define GEN6_PCODE_READ_RC6VIDS 0x5 9189 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 9190 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 9191 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 9192 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 9193 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 9194 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 9195 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 9196 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 9197 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 9198 #define SKL_PCODE_CDCLK_CONTROL 0x7 9199 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 9200 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 9201 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 9202 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 9203 #define GEN6_READ_OC_PARAMS 0xc 9204 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 9205 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 9206 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 9207 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 9208 #define ICL_PCODE_POINTS_RESTRICTED 0x0 9209 #define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1 9210 #define GEN6_PCODE_READ_D_COMP 0x10 9211 #define GEN6_PCODE_WRITE_D_COMP 0x11 9212 #define ICL_PCODE_EXIT_TCCOLD 0x12 9213 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 9214 #define DISPLAY_IPS_CONTROL 0x19 9215 #define TGL_PCODE_TCCOLD 0x26 9216 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 9217 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 9218 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 9219 /* See also IPS_CTL */ 9220 #define IPS_PCODE_CONTROL (1 << 30) 9221 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 9222 #define GEN9_PCODE_SAGV_CONTROL 0x21 9223 #define GEN9_SAGV_DISABLE 0x0 9224 #define GEN9_SAGV_IS_DISABLED 0x1 9225 #define GEN9_SAGV_ENABLE 0x3 9226 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 9227 #define GEN6_PCODE_DATA _MMIO(0x138128) 9228 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 9229 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 9230 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 9231 9232 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 9233 #define GEN6_CORE_CPD_STATE_MASK (7 << 4) 9234 #define GEN6_RCn_MASK 7 9235 #define GEN6_RC0 0 9236 #define GEN6_RC3 2 9237 #define GEN6_RC6 3 9238 #define GEN6_RC7 4 9239 9240 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 9241 #define GEN8_LSLICESTAT_MASK 0x7 9242 9243 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 9244 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 9245 #define CHV_SS_PG_ENABLE (1 << 1) 9246 #define CHV_EU08_PG_ENABLE (1 << 9) 9247 #define CHV_EU19_PG_ENABLE (1 << 17) 9248 #define CHV_EU210_PG_ENABLE (1 << 25) 9249 9250 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 9251 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 9252 #define CHV_EU311_PG_ENABLE (1 << 1) 9253 9254 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 9255 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 9256 ((slice) % 3) * 0x4) 9257 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 9258 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 9259 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 9260 9261 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 9262 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ 9263 ((slice) % 3) * 0x8) 9264 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 9265 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 9266 ((slice) % 3) * 0x8) 9267 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 9268 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 9269 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 9270 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 9271 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 9272 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 9273 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 9274 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 9275 9276 #define GEN7_MISCCPCTL _MMIO(0x9424) 9277 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) 9278 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) 9279 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) 9280 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) 9281 9282 #define GEN8_GARBCNTL _MMIO(0xB004) 9283 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7) 9284 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22) 9285 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0) 9286 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0) 9287 9288 #define GEN11_GLBLINVL _MMIO(0xB404) 9289 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) 9290 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) 9291 9292 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) 9293 #define DFR_DISABLE (1 << 9) 9294 9295 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80) 9296 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) 9297 #define GEN11_HASH_CTRL_BIT0 (1 << 0) 9298 #define GEN11_HASH_CTRL_BIT4 (1 << 12) 9299 9300 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C) 9301 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 9302 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 9303 9304 #define GEN10_SAMPLER_MODE _MMIO(0xE18C) 9305 #define ENABLE_SMALLPL REG_BIT(15) 9306 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 9307 9308 /* IVYBRIDGE DPF */ 9309 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 9310 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 9311 #define GEN7_PARITY_ERROR_VALID (1 << 13) 9312 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 9313 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 9314 #define GEN7_PARITY_ERROR_ROW(reg) \ 9315 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 9316 #define GEN7_PARITY_ERROR_BANK(reg) \ 9317 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 9318 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 9319 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 9320 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 9321 9322 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 9323 #define GEN7_L3LOG_SIZE 0x80 9324 9325 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 9326 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 9327 #define GEN7_MAX_PS_THREAD_DEP (8 << 12) 9328 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) 9329 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) 9330 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) 9331 9332 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 9333 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) 9334 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) 9335 9336 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 9337 #define FLOW_CONTROL_ENABLE (1 << 15) 9338 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8) 9339 #define STALL_DOP_GATING_DISABLE (1 << 5) 9340 #define THROTTLE_12_5 (7 << 2) 9341 #define DISABLE_EARLY_EOT (1 << 1) 9342 9343 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 9344 #define GEN12_DISABLE_EARLY_READ REG_BIT(14) 9345 #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 9346 9347 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 9348 #define DOP_CLOCK_GATING_DISABLE (1 << 0) 9349 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) 9350 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) 9351 9352 #define GEN9_ROW_CHICKEN4 _MMIO(0xe48c) 9353 #define GEN12_DISABLE_TDL_PUSH REG_BIT(9) 9354 #define GEN11_DIS_PICK_2ND_EU REG_BIT(7) 9355 9356 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 9357 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 9358 9359 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 9360 #define GEN8_ST_PO_DISABLE (1 << 13) 9361 9362 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 9363 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) 9364 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) 9365 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) 9366 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4) 9367 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) 9368 9369 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 9370 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8) 9371 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4) 9372 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) 9373 9374 /* Audio */ 9375 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 9376 #define INTEL_AUDIO_DEVCL 0x808629FB 9377 #define INTEL_AUDIO_DEVBLC 0x80862801 9378 #define INTEL_AUDIO_DEVCTG 0x80862802 9379 9380 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 9381 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 9382 #define G4X_ELDV_DEVCTG (1 << 14) 9383 #define G4X_ELD_ADDR_MASK (0xf << 5) 9384 #define G4X_ELD_ACK (1 << 4) 9385 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 9386 9387 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 9388 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 9389 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 9390 _IBX_HDMIW_HDMIEDID_B) 9391 #define _IBX_AUD_CNTL_ST_A 0xE20B4 9392 #define _IBX_AUD_CNTL_ST_B 0xE21B4 9393 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 9394 _IBX_AUD_CNTL_ST_B) 9395 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 9396 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 9397 #define IBX_ELD_ACK (1 << 4) 9398 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 9399 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 9400 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 9401 9402 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 9403 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 9404 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 9405 #define _CPT_AUD_CNTL_ST_A 0xE50B4 9406 #define _CPT_AUD_CNTL_ST_B 0xE51B4 9407 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 9408 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 9409 9410 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 9411 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 9412 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 9413 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 9414 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 9415 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 9416 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 9417 9418 /* These are the 4 32-bit write offset registers for each stream 9419 * output buffer. It determines the offset from the 9420 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 9421 */ 9422 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 9423 9424 #define _IBX_AUD_CONFIG_A 0xe2000 9425 #define _IBX_AUD_CONFIG_B 0xe2100 9426 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 9427 #define _CPT_AUD_CONFIG_A 0xe5000 9428 #define _CPT_AUD_CONFIG_B 0xe5100 9429 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 9430 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 9431 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 9432 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 9433 9434 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 9435 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 9436 #define AUD_CONFIG_UPPER_N_SHIFT 20 9437 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 9438 #define AUD_CONFIG_LOWER_N_SHIFT 4 9439 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 9440 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 9441 #define AUD_CONFIG_N(n) \ 9442 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 9443 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 9444 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 9445 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 9446 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 9447 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 9448 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 9449 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 9450 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 9451 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 9452 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 9453 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 9454 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 9455 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 9456 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) 9457 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) 9458 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) 9459 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) 9460 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 9461 9462 /* HSW Audio */ 9463 #define _HSW_AUD_CONFIG_A 0x65000 9464 #define _HSW_AUD_CONFIG_B 0x65100 9465 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 9466 9467 #define _HSW_AUD_MISC_CTRL_A 0x65010 9468 #define _HSW_AUD_MISC_CTRL_B 0x65110 9469 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 9470 9471 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 9472 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 9473 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 9474 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 9475 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 9476 #define AUD_CONFIG_M_MASK 0xfffff 9477 9478 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 9479 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 9480 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 9481 9482 /* Audio Digital Converter */ 9483 #define _HSW_AUD_DIG_CNVT_1 0x65080 9484 #define _HSW_AUD_DIG_CNVT_2 0x65180 9485 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 9486 #define DIP_PORT_SEL_MASK 0x3 9487 9488 #define _HSW_AUD_EDID_DATA_A 0x65050 9489 #define _HSW_AUD_EDID_DATA_B 0x65150 9490 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 9491 9492 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 9493 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 9494 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 9495 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 9496 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 9497 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 9498 9499 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 9500 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 9501 9502 #define AUD_FREQ_CNTRL _MMIO(0x65900) 9503 #define AUD_PIN_BUF_CTL _MMIO(0x48414) 9504 #define AUD_PIN_BUF_ENABLE REG_BIT(31) 9505 9506 /* Display Audio Config Reg */ 9507 #define AUD_CONFIG_BE _MMIO(0x65ef0) 9508 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) 9509 #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) 9510 #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) 9511 #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) 9512 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) 9513 #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) 9514 9515 #define HBLANK_START_COUNT_8 0 9516 #define HBLANK_START_COUNT_16 1 9517 #define HBLANK_START_COUNT_32 2 9518 #define HBLANK_START_COUNT_64 3 9519 #define HBLANK_START_COUNT_96 4 9520 #define HBLANK_START_COUNT_128 5 9521 9522 /* 9523 * HSW - ICL power wells 9524 * 9525 * Platforms have up to 3 power well control register sets, each set 9526 * controlling up to 16 power wells via a request/status HW flag tuple: 9527 * - main (HSW_PWR_WELL_CTL[1-4]) 9528 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 9529 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 9530 * Each control register set consists of up to 4 registers used by different 9531 * sources that can request a power well to be enabled: 9532 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 9533 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 9534 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 9535 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 9536 */ 9537 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 9538 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 9539 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 9540 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 9541 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 9542 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 9543 9544 /* HSW/BDW power well */ 9545 #define HSW_PW_CTL_IDX_GLOBAL 15 9546 9547 /* SKL/BXT/GLK/CNL power wells */ 9548 #define SKL_PW_CTL_IDX_PW_2 15 9549 #define SKL_PW_CTL_IDX_PW_1 14 9550 #define CNL_PW_CTL_IDX_AUX_F 12 9551 #define CNL_PW_CTL_IDX_AUX_D 11 9552 #define GLK_PW_CTL_IDX_AUX_C 10 9553 #define GLK_PW_CTL_IDX_AUX_B 9 9554 #define GLK_PW_CTL_IDX_AUX_A 8 9555 #define CNL_PW_CTL_IDX_DDI_F 6 9556 #define SKL_PW_CTL_IDX_DDI_D 4 9557 #define SKL_PW_CTL_IDX_DDI_C 3 9558 #define SKL_PW_CTL_IDX_DDI_B 2 9559 #define SKL_PW_CTL_IDX_DDI_A_E 1 9560 #define GLK_PW_CTL_IDX_DDI_A 1 9561 #define SKL_PW_CTL_IDX_MISC_IO 0 9562 9563 /* ICL/TGL - power wells */ 9564 #define TGL_PW_CTL_IDX_PW_5 4 9565 #define ICL_PW_CTL_IDX_PW_4 3 9566 #define ICL_PW_CTL_IDX_PW_3 2 9567 #define ICL_PW_CTL_IDX_PW_2 1 9568 #define ICL_PW_CTL_IDX_PW_1 0 9569 9570 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 9571 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 9572 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 9573 #define TGL_PW_CTL_IDX_AUX_TBT6 14 9574 #define TGL_PW_CTL_IDX_AUX_TBT5 13 9575 #define TGL_PW_CTL_IDX_AUX_TBT4 12 9576 #define ICL_PW_CTL_IDX_AUX_TBT4 11 9577 #define TGL_PW_CTL_IDX_AUX_TBT3 11 9578 #define ICL_PW_CTL_IDX_AUX_TBT3 10 9579 #define TGL_PW_CTL_IDX_AUX_TBT2 10 9580 #define ICL_PW_CTL_IDX_AUX_TBT2 9 9581 #define TGL_PW_CTL_IDX_AUX_TBT1 9 9582 #define ICL_PW_CTL_IDX_AUX_TBT1 8 9583 #define TGL_PW_CTL_IDX_AUX_TC6 8 9584 #define TGL_PW_CTL_IDX_AUX_TC5 7 9585 #define TGL_PW_CTL_IDX_AUX_TC4 6 9586 #define ICL_PW_CTL_IDX_AUX_F 5 9587 #define TGL_PW_CTL_IDX_AUX_TC3 5 9588 #define ICL_PW_CTL_IDX_AUX_E 4 9589 #define TGL_PW_CTL_IDX_AUX_TC2 4 9590 #define ICL_PW_CTL_IDX_AUX_D 3 9591 #define TGL_PW_CTL_IDX_AUX_TC1 3 9592 #define ICL_PW_CTL_IDX_AUX_C 2 9593 #define ICL_PW_CTL_IDX_AUX_B 1 9594 #define ICL_PW_CTL_IDX_AUX_A 0 9595 9596 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 9597 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 9598 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 9599 #define TGL_PW_CTL_IDX_DDI_TC6 8 9600 #define TGL_PW_CTL_IDX_DDI_TC5 7 9601 #define TGL_PW_CTL_IDX_DDI_TC4 6 9602 #define ICL_PW_CTL_IDX_DDI_F 5 9603 #define TGL_PW_CTL_IDX_DDI_TC3 5 9604 #define ICL_PW_CTL_IDX_DDI_E 4 9605 #define TGL_PW_CTL_IDX_DDI_TC2 4 9606 #define ICL_PW_CTL_IDX_DDI_D 3 9607 #define TGL_PW_CTL_IDX_DDI_TC1 3 9608 #define ICL_PW_CTL_IDX_DDI_C 2 9609 #define ICL_PW_CTL_IDX_DDI_B 1 9610 #define ICL_PW_CTL_IDX_DDI_A 0 9611 9612 /* HSW - power well misc debug registers */ 9613 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 9614 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 9615 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 9616 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 9617 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 9618 9619 /* SKL Fuse Status */ 9620 enum skl_power_gate { 9621 SKL_PG0, 9622 SKL_PG1, 9623 SKL_PG2, 9624 ICL_PG3, 9625 ICL_PG4, 9626 }; 9627 9628 #define SKL_FUSE_STATUS _MMIO(0x42000) 9629 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 9630 /* 9631 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9632 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 9633 */ 9634 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 9635 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 9636 /* 9637 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9638 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 9639 */ 9640 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 9641 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 9642 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 9643 9644 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B) 9645 #define _CNL_AUX_ANAOVRD1_B 0x162250 9646 #define _CNL_AUX_ANAOVRD1_C 0x162210 9647 #define _CNL_AUX_ANAOVRD1_D 0x1622D0 9648 #define _CNL_AUX_ANAOVRD1_F 0x162A90 9649 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ 9650 _CNL_AUX_ANAOVRD1_B, \ 9651 _CNL_AUX_ANAOVRD1_C, \ 9652 _CNL_AUX_ANAOVRD1_D, \ 9653 _CNL_AUX_ANAOVRD1_F)) 9654 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) 9655 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) 9656 9657 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 9658 #define _ICL_AUX_ANAOVRD1_A 0x162398 9659 #define _ICL_AUX_ANAOVRD1_B 0x6C398 9660 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 9661 _ICL_AUX_ANAOVRD1_A, \ 9662 _ICL_AUX_ANAOVRD1_B)) 9663 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 9664 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 9665 9666 /* HDCP Key Registers */ 9667 #define HDCP_KEY_CONF _MMIO(0x66c00) 9668 #define HDCP_AKSV_SEND_TRIGGER BIT(31) 9669 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 9670 #define HDCP_KEY_LOAD_TRIGGER BIT(8) 9671 #define HDCP_KEY_STATUS _MMIO(0x66c04) 9672 #define HDCP_FUSE_IN_PROGRESS BIT(7) 9673 #define HDCP_FUSE_ERROR BIT(6) 9674 #define HDCP_FUSE_DONE BIT(5) 9675 #define HDCP_KEY_LOAD_STATUS BIT(1) 9676 #define HDCP_KEY_LOAD_DONE BIT(0) 9677 #define HDCP_AKSV_LO _MMIO(0x66c10) 9678 #define HDCP_AKSV_HI _MMIO(0x66c14) 9679 9680 /* HDCP Repeater Registers */ 9681 #define HDCP_REP_CTL _MMIO(0x66d00) 9682 #define HDCP_TRANSA_REP_PRESENT BIT(31) 9683 #define HDCP_TRANSB_REP_PRESENT BIT(30) 9684 #define HDCP_TRANSC_REP_PRESENT BIT(29) 9685 #define HDCP_TRANSD_REP_PRESENT BIT(28) 9686 #define HDCP_DDIB_REP_PRESENT BIT(30) 9687 #define HDCP_DDIA_REP_PRESENT BIT(29) 9688 #define HDCP_DDIC_REP_PRESENT BIT(28) 9689 #define HDCP_DDID_REP_PRESENT BIT(27) 9690 #define HDCP_DDIF_REP_PRESENT BIT(26) 9691 #define HDCP_DDIE_REP_PRESENT BIT(25) 9692 #define HDCP_TRANSA_SHA1_M0 (1 << 20) 9693 #define HDCP_TRANSB_SHA1_M0 (2 << 20) 9694 #define HDCP_TRANSC_SHA1_M0 (3 << 20) 9695 #define HDCP_TRANSD_SHA1_M0 (4 << 20) 9696 #define HDCP_DDIB_SHA1_M0 (1 << 20) 9697 #define HDCP_DDIA_SHA1_M0 (2 << 20) 9698 #define HDCP_DDIC_SHA1_M0 (3 << 20) 9699 #define HDCP_DDID_SHA1_M0 (4 << 20) 9700 #define HDCP_DDIF_SHA1_M0 (5 << 20) 9701 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 9702 #define HDCP_SHA1_BUSY BIT(16) 9703 #define HDCP_SHA1_READY BIT(17) 9704 #define HDCP_SHA1_COMPLETE BIT(18) 9705 #define HDCP_SHA1_V_MATCH BIT(19) 9706 #define HDCP_SHA1_TEXT_32 (1 << 1) 9707 #define HDCP_SHA1_COMPLETE_HASH (2 << 1) 9708 #define HDCP_SHA1_TEXT_24 (4 << 1) 9709 #define HDCP_SHA1_TEXT_16 (5 << 1) 9710 #define HDCP_SHA1_TEXT_8 (6 << 1) 9711 #define HDCP_SHA1_TEXT_0 (7 << 1) 9712 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 9713 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 9714 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 9715 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 9716 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 9717 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 9718 #define HDCP_SHA_TEXT _MMIO(0x66d18) 9719 9720 /* HDCP Auth Registers */ 9721 #define _PORTA_HDCP_AUTHENC 0x66800 9722 #define _PORTB_HDCP_AUTHENC 0x66500 9723 #define _PORTC_HDCP_AUTHENC 0x66600 9724 #define _PORTD_HDCP_AUTHENC 0x66700 9725 #define _PORTE_HDCP_AUTHENC 0x66A00 9726 #define _PORTF_HDCP_AUTHENC 0x66900 9727 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 9728 _PORTA_HDCP_AUTHENC, \ 9729 _PORTB_HDCP_AUTHENC, \ 9730 _PORTC_HDCP_AUTHENC, \ 9731 _PORTD_HDCP_AUTHENC, \ 9732 _PORTE_HDCP_AUTHENC, \ 9733 _PORTF_HDCP_AUTHENC) + (x)) 9734 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 9735 #define _TRANSA_HDCP_CONF 0x66400 9736 #define _TRANSB_HDCP_CONF 0x66500 9737 #define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \ 9738 _TRANSB_HDCP_CONF) 9739 #define HDCP_CONF(dev_priv, trans, port) \ 9740 (INTEL_GEN(dev_priv) >= 12 ? \ 9741 TRANS_HDCP_CONF(trans) : \ 9742 PORT_HDCP_CONF(port)) 9743 9744 #define HDCP_CONF_CAPTURE_AN BIT(0) 9745 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 9746 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 9747 #define _TRANSA_HDCP_ANINIT 0x66404 9748 #define _TRANSB_HDCP_ANINIT 0x66504 9749 #define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \ 9750 _TRANSA_HDCP_ANINIT, \ 9751 _TRANSB_HDCP_ANINIT) 9752 #define HDCP_ANINIT(dev_priv, trans, port) \ 9753 (INTEL_GEN(dev_priv) >= 12 ? \ 9754 TRANS_HDCP_ANINIT(trans) : \ 9755 PORT_HDCP_ANINIT(port)) 9756 9757 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 9758 #define _TRANSA_HDCP_ANLO 0x66408 9759 #define _TRANSB_HDCP_ANLO 0x66508 9760 #define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \ 9761 _TRANSB_HDCP_ANLO) 9762 #define HDCP_ANLO(dev_priv, trans, port) \ 9763 (INTEL_GEN(dev_priv) >= 12 ? \ 9764 TRANS_HDCP_ANLO(trans) : \ 9765 PORT_HDCP_ANLO(port)) 9766 9767 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 9768 #define _TRANSA_HDCP_ANHI 0x6640C 9769 #define _TRANSB_HDCP_ANHI 0x6650C 9770 #define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \ 9771 _TRANSB_HDCP_ANHI) 9772 #define HDCP_ANHI(dev_priv, trans, port) \ 9773 (INTEL_GEN(dev_priv) >= 12 ? \ 9774 TRANS_HDCP_ANHI(trans) : \ 9775 PORT_HDCP_ANHI(port)) 9776 9777 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 9778 #define _TRANSA_HDCP_BKSVLO 0x66410 9779 #define _TRANSB_HDCP_BKSVLO 0x66510 9780 #define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \ 9781 _TRANSA_HDCP_BKSVLO, \ 9782 _TRANSB_HDCP_BKSVLO) 9783 #define HDCP_BKSVLO(dev_priv, trans, port) \ 9784 (INTEL_GEN(dev_priv) >= 12 ? \ 9785 TRANS_HDCP_BKSVLO(trans) : \ 9786 PORT_HDCP_BKSVLO(port)) 9787 9788 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 9789 #define _TRANSA_HDCP_BKSVHI 0x66414 9790 #define _TRANSB_HDCP_BKSVHI 0x66514 9791 #define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \ 9792 _TRANSA_HDCP_BKSVHI, \ 9793 _TRANSB_HDCP_BKSVHI) 9794 #define HDCP_BKSVHI(dev_priv, trans, port) \ 9795 (INTEL_GEN(dev_priv) >= 12 ? \ 9796 TRANS_HDCP_BKSVHI(trans) : \ 9797 PORT_HDCP_BKSVHI(port)) 9798 9799 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 9800 #define _TRANSA_HDCP_RPRIME 0x66418 9801 #define _TRANSB_HDCP_RPRIME 0x66518 9802 #define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \ 9803 _TRANSA_HDCP_RPRIME, \ 9804 _TRANSB_HDCP_RPRIME) 9805 #define HDCP_RPRIME(dev_priv, trans, port) \ 9806 (INTEL_GEN(dev_priv) >= 12 ? \ 9807 TRANS_HDCP_RPRIME(trans) : \ 9808 PORT_HDCP_RPRIME(port)) 9809 9810 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 9811 #define _TRANSA_HDCP_STATUS 0x6641C 9812 #define _TRANSB_HDCP_STATUS 0x6651C 9813 #define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \ 9814 _TRANSA_HDCP_STATUS, \ 9815 _TRANSB_HDCP_STATUS) 9816 #define HDCP_STATUS(dev_priv, trans, port) \ 9817 (INTEL_GEN(dev_priv) >= 12 ? \ 9818 TRANS_HDCP_STATUS(trans) : \ 9819 PORT_HDCP_STATUS(port)) 9820 9821 #define HDCP_STATUS_STREAM_A_ENC BIT(31) 9822 #define HDCP_STATUS_STREAM_B_ENC BIT(30) 9823 #define HDCP_STATUS_STREAM_C_ENC BIT(29) 9824 #define HDCP_STATUS_STREAM_D_ENC BIT(28) 9825 #define HDCP_STATUS_AUTH BIT(21) 9826 #define HDCP_STATUS_ENC BIT(20) 9827 #define HDCP_STATUS_RI_MATCH BIT(19) 9828 #define HDCP_STATUS_R0_READY BIT(18) 9829 #define HDCP_STATUS_AN_READY BIT(17) 9830 #define HDCP_STATUS_CIPHER BIT(16) 9831 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 9832 9833 /* HDCP2.2 Registers */ 9834 #define _PORTA_HDCP2_BASE 0x66800 9835 #define _PORTB_HDCP2_BASE 0x66500 9836 #define _PORTC_HDCP2_BASE 0x66600 9837 #define _PORTD_HDCP2_BASE 0x66700 9838 #define _PORTE_HDCP2_BASE 0x66A00 9839 #define _PORTF_HDCP2_BASE 0x66900 9840 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 9841 _PORTA_HDCP2_BASE, \ 9842 _PORTB_HDCP2_BASE, \ 9843 _PORTC_HDCP2_BASE, \ 9844 _PORTD_HDCP2_BASE, \ 9845 _PORTE_HDCP2_BASE, \ 9846 _PORTF_HDCP2_BASE) + (x)) 9847 #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) 9848 #define _TRANSA_HDCP2_AUTH 0x66498 9849 #define _TRANSB_HDCP2_AUTH 0x66598 9850 #define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \ 9851 _TRANSB_HDCP2_AUTH) 9852 #define AUTH_LINK_AUTHENTICATED BIT(31) 9853 #define AUTH_LINK_TYPE BIT(30) 9854 #define AUTH_FORCE_CLR_INPUTCTR BIT(19) 9855 #define AUTH_CLR_KEYS BIT(18) 9856 #define HDCP2_AUTH(dev_priv, trans, port) \ 9857 (INTEL_GEN(dev_priv) >= 12 ? \ 9858 TRANS_HDCP2_AUTH(trans) : \ 9859 PORT_HDCP2_AUTH(port)) 9860 9861 #define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0) 9862 #define _TRANSA_HDCP2_CTL 0x664B0 9863 #define _TRANSB_HDCP2_CTL 0x665B0 9864 #define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \ 9865 _TRANSB_HDCP2_CTL) 9866 #define CTL_LINK_ENCRYPTION_REQ BIT(31) 9867 #define HDCP2_CTL(dev_priv, trans, port) \ 9868 (INTEL_GEN(dev_priv) >= 12 ? \ 9869 TRANS_HDCP2_CTL(trans) : \ 9870 PORT_HDCP2_CTL(port)) 9871 9872 #define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4) 9873 #define _TRANSA_HDCP2_STATUS 0x664B4 9874 #define _TRANSB_HDCP2_STATUS 0x665B4 9875 #define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \ 9876 _TRANSA_HDCP2_STATUS, \ 9877 _TRANSB_HDCP2_STATUS) 9878 #define LINK_TYPE_STATUS BIT(22) 9879 #define LINK_AUTH_STATUS BIT(21) 9880 #define LINK_ENCRYPTION_STATUS BIT(20) 9881 #define HDCP2_STATUS(dev_priv, trans, port) \ 9882 (INTEL_GEN(dev_priv) >= 12 ? \ 9883 TRANS_HDCP2_STATUS(trans) : \ 9884 PORT_HDCP2_STATUS(port)) 9885 9886 /* Per-pipe DDI Function Control */ 9887 #define _TRANS_DDI_FUNC_CTL_A 0x60400 9888 #define _TRANS_DDI_FUNC_CTL_B 0x61400 9889 #define _TRANS_DDI_FUNC_CTL_C 0x62400 9890 #define _TRANS_DDI_FUNC_CTL_D 0x63400 9891 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 9892 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 9893 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 9894 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 9895 9896 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 9897 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 9898 #define TRANS_DDI_PORT_SHIFT 28 9899 #define TGL_TRANS_DDI_PORT_SHIFT 27 9900 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 9901 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 9902 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 9903 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 9904 #define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT) 9905 #define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1) 9906 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 9907 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 9908 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 9909 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 9910 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 9911 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24) 9912 #define TRANS_DDI_BPC_MASK (7 << 20) 9913 #define TRANS_DDI_BPC_8 (0 << 20) 9914 #define TRANS_DDI_BPC_10 (1 << 20) 9915 #define TRANS_DDI_BPC_6 (2 << 20) 9916 #define TRANS_DDI_BPC_12 (3 << 20) 9917 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */ 9918 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 9919 #define TRANS_DDI_PVSYNC (1 << 17) 9920 #define TRANS_DDI_PHSYNC (1 << 16) 9921 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */ 9922 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 9923 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 9924 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 9925 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 9926 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 9927 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 9928 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 9929 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 9930 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 9931 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 9932 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 9933 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 9934 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 9935 #define TRANS_DDI_BFI_ENABLE (1 << 4) 9936 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 9937 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 9938 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 9939 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 9940 | TRANS_DDI_HDMI_SCRAMBLING) 9941 9942 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 9943 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 9944 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 9945 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 9946 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 9947 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 9948 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 9949 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 9950 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 9951 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 9952 9953 /* DisplayPort Transport Control */ 9954 #define _DP_TP_CTL_A 0x64040 9955 #define _DP_TP_CTL_B 0x64140 9956 #define _TGL_DP_TP_CTL_A 0x60540 9957 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 9958 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 9959 #define DP_TP_CTL_ENABLE (1 << 31) 9960 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 9961 #define DP_TP_CTL_MODE_SST (0 << 27) 9962 #define DP_TP_CTL_MODE_MST (1 << 27) 9963 #define DP_TP_CTL_FORCE_ACT (1 << 25) 9964 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 9965 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 9966 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 9967 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 9968 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 9969 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 9970 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 9971 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 9972 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 9973 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 9974 9975 /* DisplayPort Transport Status */ 9976 #define _DP_TP_STATUS_A 0x64044 9977 #define _DP_TP_STATUS_B 0x64144 9978 #define _TGL_DP_TP_STATUS_A 0x60544 9979 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 9980 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 9981 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 9982 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 9983 #define DP_TP_STATUS_ACT_SENT (1 << 24) 9984 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 9985 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 9986 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 9987 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 9988 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 9989 9990 /* DDI Buffer Control */ 9991 #define _DDI_BUF_CTL_A 0x64000 9992 #define _DDI_BUF_CTL_B 0x64100 9993 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 9994 #define DDI_BUF_CTL_ENABLE (1 << 31) 9995 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 9996 #define DDI_BUF_EMP_MASK (0xf << 24) 9997 #define DDI_BUF_PORT_REVERSAL (1 << 16) 9998 #define DDI_BUF_IS_IDLE (1 << 7) 9999 #define DDI_A_4_LANES (1 << 4) 10000 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 10001 #define DDI_PORT_WIDTH_MASK (7 << 1) 10002 #define DDI_PORT_WIDTH_SHIFT 1 10003 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 10004 10005 /* DDI Buffer Translations */ 10006 #define _DDI_BUF_TRANS_A 0x64E00 10007 #define _DDI_BUF_TRANS_B 0x64E60 10008 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 10009 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 10010 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 10011 10012 /* DDI DP Compliance Control */ 10013 #define _DDI_DP_COMP_CTL_A 0x605F0 10014 #define _DDI_DP_COMP_CTL_B 0x615F0 10015 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 10016 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 10017 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 10018 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 10019 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 10020 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 10021 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 10022 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 10023 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 10024 10025 /* DDI DP Compliance Pattern */ 10026 #define _DDI_DP_COMP_PAT_A 0x605F4 10027 #define _DDI_DP_COMP_PAT_B 0x615F4 10028 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 10029 10030 /* Sideband Interface (SBI) is programmed indirectly, via 10031 * SBI_ADDR, which contains the register offset; and SBI_DATA, 10032 * which contains the payload */ 10033 #define SBI_ADDR _MMIO(0xC6000) 10034 #define SBI_DATA _MMIO(0xC6004) 10035 #define SBI_CTL_STAT _MMIO(0xC6008) 10036 #define SBI_CTL_DEST_ICLK (0x0 << 16) 10037 #define SBI_CTL_DEST_MPHY (0x1 << 16) 10038 #define SBI_CTL_OP_IORD (0x2 << 8) 10039 #define SBI_CTL_OP_IOWR (0x3 << 8) 10040 #define SBI_CTL_OP_CRRD (0x6 << 8) 10041 #define SBI_CTL_OP_CRWR (0x7 << 8) 10042 #define SBI_RESPONSE_FAIL (0x1 << 1) 10043 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 10044 #define SBI_BUSY (0x1 << 0) 10045 #define SBI_READY (0x0 << 0) 10046 10047 /* SBI offsets */ 10048 #define SBI_SSCDIVINTPHASE 0x0200 10049 #define SBI_SSCDIVINTPHASE6 0x0600 10050 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 10051 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 10052 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 10053 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 10054 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 10055 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 10056 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 10057 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 10058 #define SBI_SSCDITHPHASE 0x0204 10059 #define SBI_SSCCTL 0x020c 10060 #define SBI_SSCCTL6 0x060C 10061 #define SBI_SSCCTL_PATHALT (1 << 3) 10062 #define SBI_SSCCTL_DISABLE (1 << 0) 10063 #define SBI_SSCAUXDIV6 0x0610 10064 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 10065 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 10066 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 10067 #define SBI_DBUFF0 0x2a00 10068 #define SBI_GEN0 0x1f00 10069 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 10070 10071 /* LPT PIXCLK_GATE */ 10072 #define PIXCLK_GATE _MMIO(0xC6020) 10073 #define PIXCLK_GATE_UNGATE (1 << 0) 10074 #define PIXCLK_GATE_GATE (0 << 0) 10075 10076 /* SPLL */ 10077 #define SPLL_CTL _MMIO(0x46020) 10078 #define SPLL_PLL_ENABLE (1 << 31) 10079 #define SPLL_REF_BCLK (0 << 28) 10080 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 10081 #define SPLL_REF_NON_SSC_HSW (2 << 28) 10082 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 10083 #define SPLL_REF_LCPLL (3 << 28) 10084 #define SPLL_REF_MASK (3 << 28) 10085 #define SPLL_FREQ_810MHz (0 << 26) 10086 #define SPLL_FREQ_1350MHz (1 << 26) 10087 #define SPLL_FREQ_2700MHz (2 << 26) 10088 #define SPLL_FREQ_MASK (3 << 26) 10089 10090 /* WRPLL */ 10091 #define _WRPLL_CTL1 0x46040 10092 #define _WRPLL_CTL2 0x46060 10093 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 10094 #define WRPLL_PLL_ENABLE (1 << 31) 10095 #define WRPLL_REF_BCLK (0 << 28) 10096 #define WRPLL_REF_PCH_SSC (1 << 28) 10097 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 10098 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 10099 #define WRPLL_REF_LCPLL (3 << 28) 10100 #define WRPLL_REF_MASK (3 << 28) 10101 /* WRPLL divider programming */ 10102 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 10103 #define WRPLL_DIVIDER_REF_MASK (0xff) 10104 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 10105 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 10106 #define WRPLL_DIVIDER_POST_SHIFT 8 10107 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 10108 #define WRPLL_DIVIDER_FB_SHIFT 16 10109 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 10110 10111 /* Port clock selection */ 10112 #define _PORT_CLK_SEL_A 0x46100 10113 #define _PORT_CLK_SEL_B 0x46104 10114 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 10115 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29) 10116 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29) 10117 #define PORT_CLK_SEL_LCPLL_810 (2 << 29) 10118 #define PORT_CLK_SEL_SPLL (3 << 29) 10119 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) 10120 #define PORT_CLK_SEL_WRPLL1 (4 << 29) 10121 #define PORT_CLK_SEL_WRPLL2 (5 << 29) 10122 #define PORT_CLK_SEL_NONE (7 << 29) 10123 #define PORT_CLK_SEL_MASK (7 << 29) 10124 10125 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 10126 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 10127 #define DDI_CLK_SEL_NONE (0x0 << 28) 10128 #define DDI_CLK_SEL_MG (0x8 << 28) 10129 #define DDI_CLK_SEL_TBT_162 (0xC << 28) 10130 #define DDI_CLK_SEL_TBT_270 (0xD << 28) 10131 #define DDI_CLK_SEL_TBT_540 (0xE << 28) 10132 #define DDI_CLK_SEL_TBT_810 (0xF << 28) 10133 #define DDI_CLK_SEL_MASK (0xF << 28) 10134 10135 /* Transcoder clock selection */ 10136 #define _TRANS_CLK_SEL_A 0x46140 10137 #define _TRANS_CLK_SEL_B 0x46144 10138 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 10139 /* For each transcoder, we need to select the corresponding port clock */ 10140 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 10141 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 10142 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 10143 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 10144 10145 10146 #define CDCLK_FREQ _MMIO(0x46200) 10147 10148 #define _TRANSA_MSA_MISC 0x60410 10149 #define _TRANSB_MSA_MISC 0x61410 10150 #define _TRANSC_MSA_MISC 0x62410 10151 #define _TRANS_EDP_MSA_MISC 0x6f410 10152 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 10153 /* See DP_MSA_MISC_* for the bit definitions */ 10154 10155 /* LCPLL Control */ 10156 #define LCPLL_CTL _MMIO(0x130040) 10157 #define LCPLL_PLL_DISABLE (1 << 31) 10158 #define LCPLL_PLL_LOCK (1 << 30) 10159 #define LCPLL_REF_NON_SSC (0 << 28) 10160 #define LCPLL_REF_BCLK (2 << 28) 10161 #define LCPLL_REF_PCH_SSC (3 << 28) 10162 #define LCPLL_REF_MASK (3 << 28) 10163 #define LCPLL_CLK_FREQ_MASK (3 << 26) 10164 #define LCPLL_CLK_FREQ_450 (0 << 26) 10165 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 10166 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 10167 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 10168 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 10169 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 10170 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 10171 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 10172 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 10173 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 10174 10175 /* 10176 * SKL Clocks 10177 */ 10178 10179 /* CDCLK_CTL */ 10180 #define CDCLK_CTL _MMIO(0x46000) 10181 #define CDCLK_FREQ_SEL_MASK (3 << 26) 10182 #define CDCLK_FREQ_450_432 (0 << 26) 10183 #define CDCLK_FREQ_540 (1 << 26) 10184 #define CDCLK_FREQ_337_308 (2 << 26) 10185 #define CDCLK_FREQ_675_617 (3 << 26) 10186 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 10187 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 10188 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 10189 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 10190 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 10191 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 10192 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 10193 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 10194 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 10195 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 10196 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 10197 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 10198 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 10199 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 10200 10201 /* LCPLL_CTL */ 10202 #define LCPLL1_CTL _MMIO(0x46010) 10203 #define LCPLL2_CTL _MMIO(0x46014) 10204 #define LCPLL_PLL_ENABLE (1 << 31) 10205 10206 /* DPLL control1 */ 10207 #define DPLL_CTRL1 _MMIO(0x6C058) 10208 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 10209 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 10210 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 10211 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 10212 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 10213 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 10214 #define DPLL_CTRL1_LINK_RATE_2700 0 10215 #define DPLL_CTRL1_LINK_RATE_1350 1 10216 #define DPLL_CTRL1_LINK_RATE_810 2 10217 #define DPLL_CTRL1_LINK_RATE_1620 3 10218 #define DPLL_CTRL1_LINK_RATE_1080 4 10219 #define DPLL_CTRL1_LINK_RATE_2160 5 10220 10221 /* DPLL control2 */ 10222 #define DPLL_CTRL2 _MMIO(0x6C05C) 10223 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 10224 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 10225 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 10226 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 10227 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 10228 10229 /* DPLL Status */ 10230 #define DPLL_STATUS _MMIO(0x6C060) 10231 #define DPLL_LOCK(id) (1 << ((id) * 8)) 10232 10233 /* DPLL cfg */ 10234 #define _DPLL1_CFGCR1 0x6C040 10235 #define _DPLL2_CFGCR1 0x6C048 10236 #define _DPLL3_CFGCR1 0x6C050 10237 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 10238 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 10239 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 10240 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 10241 10242 #define _DPLL1_CFGCR2 0x6C044 10243 #define _DPLL2_CFGCR2 0x6C04C 10244 #define _DPLL3_CFGCR2 0x6C054 10245 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 10246 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 10247 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 10248 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 10249 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 10250 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 10251 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 10252 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 10253 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 10254 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 10255 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 10256 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 10257 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 10258 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 10259 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 10260 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 10261 10262 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 10263 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 10264 10265 /* 10266 * CNL Clocks 10267 */ 10268 #define DPCLKA_CFGCR0 _MMIO(0x6C200) 10269 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ 10270 (port) + 10)) 10271 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ 10272 (port) * 2) 10273 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 10274 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 10275 10276 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 10277 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) 10278 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 10279 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ 10280 (tc_port) + 12 : \ 10281 (tc_port) - PORT_TC4 + 21)) 10282 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 10283 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10284 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10285 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 10286 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 10287 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10288 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 10289 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10290 10291 /* CNL PLL */ 10292 #define DPLL0_ENABLE 0x46010 10293 #define DPLL1_ENABLE 0x46014 10294 #define PLL_ENABLE (1 << 31) 10295 #define PLL_LOCK (1 << 30) 10296 #define PLL_POWER_ENABLE (1 << 27) 10297 #define PLL_POWER_STATE (1 << 26) 10298 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) 10299 10300 #define TBT_PLL_ENABLE _MMIO(0x46020) 10301 10302 #define _MG_PLL1_ENABLE 0x46030 10303 #define _MG_PLL2_ENABLE 0x46034 10304 #define _MG_PLL3_ENABLE 0x46038 10305 #define _MG_PLL4_ENABLE 0x4603C 10306 /* Bits are the same as DPLL0_ENABLE */ 10307 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 10308 _MG_PLL2_ENABLE) 10309 10310 #define _MG_REFCLKIN_CTL_PORT1 0x16892C 10311 #define _MG_REFCLKIN_CTL_PORT2 0x16992C 10312 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C 10313 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C 10314 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) 10315 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) 10316 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ 10317 _MG_REFCLKIN_CTL_PORT1, \ 10318 _MG_REFCLKIN_CTL_PORT2) 10319 10320 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 10321 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 10322 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8 10323 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8 10324 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) 10325 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16) 10326 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) 10327 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8) 10328 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ 10329 _MG_CLKTOP2_CORECLKCTL1_PORT1, \ 10330 _MG_CLKTOP2_CORECLKCTL1_PORT2) 10331 10332 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 10333 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 10334 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 10335 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 10336 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) 10337 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) 10338 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) 10339 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) 10340 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) 10341 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) 10342 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) 10343 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) 10344 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) 10345 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) 10346 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 10347 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) 10348 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ 10349 _MG_CLKTOP2_HSCLKCTL_PORT1, \ 10350 _MG_CLKTOP2_HSCLKCTL_PORT2) 10351 10352 #define _MG_PLL_DIV0_PORT1 0x168A00 10353 #define _MG_PLL_DIV0_PORT2 0x169A00 10354 #define _MG_PLL_DIV0_PORT3 0x16AA00 10355 #define _MG_PLL_DIV0_PORT4 0x16BA00 10356 #define MG_PLL_DIV0_FRACNEN_H (1 << 30) 10357 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8) 10358 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 10359 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) 10360 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) 10361 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 10362 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ 10363 _MG_PLL_DIV0_PORT2) 10364 10365 #define _MG_PLL_DIV1_PORT1 0x168A04 10366 #define _MG_PLL_DIV1_PORT2 0x169A04 10367 #define _MG_PLL_DIV1_PORT3 0x16AA04 10368 #define _MG_PLL_DIV1_PORT4 0x16BA04 10369 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16) 10370 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12) 10371 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12) 10372 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) 10373 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) 10374 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) 10375 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) 10376 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) 10377 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ 10378 _MG_PLL_DIV1_PORT2) 10379 10380 #define _MG_PLL_LF_PORT1 0x168A08 10381 #define _MG_PLL_LF_PORT2 0x169A08 10382 #define _MG_PLL_LF_PORT3 0x16AA08 10383 #define _MG_PLL_LF_PORT4 0x16BA08 10384 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24) 10385 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20) 10386 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20) 10387 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16) 10388 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8) 10389 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0) 10390 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ 10391 _MG_PLL_LF_PORT2) 10392 10393 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C 10394 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C 10395 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C 10396 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C 10397 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18) 10398 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16) 10399 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11) 10400 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10) 10401 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8) 10402 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0) 10403 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ 10404 _MG_PLL_FRAC_LOCK_PORT1, \ 10405 _MG_PLL_FRAC_LOCK_PORT2) 10406 10407 #define _MG_PLL_SSC_PORT1 0x168A10 10408 #define _MG_PLL_SSC_PORT2 0x169A10 10409 #define _MG_PLL_SSC_PORT3 0x16AA10 10410 #define _MG_PLL_SSC_PORT4 0x16BA10 10411 #define MG_PLL_SSC_EN (1 << 28) 10412 #define MG_PLL_SSC_TYPE(x) ((x) << 26) 10413 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16) 10414 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10) 10415 #define MG_PLL_SSC_FLLEN (1 << 9) 10416 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0) 10417 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ 10418 _MG_PLL_SSC_PORT2) 10419 10420 #define _MG_PLL_BIAS_PORT1 0x168A14 10421 #define _MG_PLL_BIAS_PORT2 0x169A14 10422 #define _MG_PLL_BIAS_PORT3 0x16AA14 10423 #define _MG_PLL_BIAS_PORT4 0x16BA14 10424 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30) 10425 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30) 10426 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24) 10427 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24) 10428 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16) 10429 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16) 10430 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15) 10431 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8) 10432 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8) 10433 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5) 10434 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5) 10435 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0) 10436 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0) 10437 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ 10438 _MG_PLL_BIAS_PORT2) 10439 10440 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18 10441 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18 10442 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18 10443 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18 10444 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27) 10445 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17) 10446 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16) 10447 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2) 10448 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0) 10449 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \ 10450 _MG_PLL_TDC_COLDST_BIAS_PORT1, \ 10451 _MG_PLL_TDC_COLDST_BIAS_PORT2) 10452 10453 #define _CNL_DPLL0_CFGCR0 0x6C000 10454 #define _CNL_DPLL1_CFGCR0 0x6C080 10455 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 10456 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 10457 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 10458 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 10459 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 10460 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 10461 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 10462 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 10463 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 10464 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 10465 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 10466 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 10467 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 10468 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 10469 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 10470 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 10471 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) 10472 10473 #define _CNL_DPLL0_CFGCR1 0x6C004 10474 #define _CNL_DPLL1_CFGCR1 0x6C084 10475 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 10476 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 10477 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 10478 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 10479 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 10480 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 10481 #define DPLL_CFGCR1_KDIV_SHIFT (6) 10482 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 10483 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 10484 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 10485 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 10486 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 10487 #define DPLL_CFGCR1_PDIV_SHIFT (2) 10488 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 10489 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 10490 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 10491 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 10492 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 10493 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 10494 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 10495 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 10496 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) 10497 10498 #define _ICL_DPLL0_CFGCR0 0x164000 10499 #define _ICL_DPLL1_CFGCR0 0x164080 10500 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 10501 _ICL_DPLL1_CFGCR0) 10502 10503 #define _ICL_DPLL0_CFGCR1 0x164004 10504 #define _ICL_DPLL1_CFGCR1 0x164084 10505 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 10506 _ICL_DPLL1_CFGCR1) 10507 10508 #define _TGL_DPLL0_CFGCR0 0x164284 10509 #define _TGL_DPLL1_CFGCR0 0x16428C 10510 #define _TGL_TBTPLL_CFGCR0 0x16429C 10511 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 10512 _TGL_DPLL1_CFGCR0, \ 10513 _TGL_TBTPLL_CFGCR0) 10514 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 10515 _TGL_DPLL1_CFGCR0) 10516 10517 #define _TGL_DPLL0_CFGCR1 0x164288 10518 #define _TGL_DPLL1_CFGCR1 0x164290 10519 #define _TGL_TBTPLL_CFGCR1 0x1642A0 10520 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 10521 _TGL_DPLL1_CFGCR1, \ 10522 _TGL_TBTPLL_CFGCR1) 10523 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 10524 _TGL_DPLL1_CFGCR1) 10525 10526 #define _DKL_PHY1_BASE 0x168000 10527 #define _DKL_PHY2_BASE 0x169000 10528 #define _DKL_PHY3_BASE 0x16A000 10529 #define _DKL_PHY4_BASE 0x16B000 10530 #define _DKL_PHY5_BASE 0x16C000 10531 #define _DKL_PHY6_BASE 0x16D000 10532 10533 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ 10534 #define _DKL_PLL_DIV0 0x200 10535 #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) 10536 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) 10537 #define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) 10538 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) 10539 #define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) 10540 #define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) 10541 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) 10542 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 10543 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) 10544 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10545 _DKL_PHY2_BASE) + \ 10546 _DKL_PLL_DIV0) 10547 10548 #define _DKL_PLL_DIV1 0x204 10549 #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) 10550 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) 10551 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) 10552 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) 10553 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10554 _DKL_PHY2_BASE) + \ 10555 _DKL_PLL_DIV1) 10556 10557 #define _DKL_PLL_SSC 0x210 10558 #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) 10559 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) 10560 #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) 10561 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) 10562 #define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) 10563 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) 10564 #define DKL_PLL_SSC_EN (1 << 9) 10565 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10566 _DKL_PHY2_BASE) + \ 10567 _DKL_PLL_SSC) 10568 10569 #define _DKL_PLL_BIAS 0x214 10570 #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) 10571 #define DKL_PLL_BIAS_FBDIV_SHIFT (8) 10572 #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) 10573 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) 10574 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10575 _DKL_PHY2_BASE) + \ 10576 _DKL_PLL_BIAS) 10577 10578 #define _DKL_PLL_TDC_COLDST_BIAS 0x218 10579 #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) 10580 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) 10581 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) 10582 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) 10583 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ 10584 _DKL_PHY1_BASE, \ 10585 _DKL_PHY2_BASE) + \ 10586 _DKL_PLL_TDC_COLDST_BIAS) 10587 10588 #define _DKL_REFCLKIN_CTL 0x12C 10589 /* Bits are the same as MG_REFCLKIN_CTL */ 10590 #define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ 10591 _DKL_PHY1_BASE, \ 10592 _DKL_PHY2_BASE) + \ 10593 _DKL_REFCLKIN_CTL) 10594 10595 #define _DKL_CLKTOP2_HSCLKCTL 0xD4 10596 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ 10597 #define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ 10598 _DKL_PHY1_BASE, \ 10599 _DKL_PHY2_BASE) + \ 10600 _DKL_CLKTOP2_HSCLKCTL) 10601 10602 #define _DKL_CLKTOP2_CORECLKCTL1 0xD8 10603 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ 10604 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ 10605 _DKL_PHY1_BASE, \ 10606 _DKL_PHY2_BASE) + \ 10607 _DKL_CLKTOP2_CORECLKCTL1) 10608 10609 #define _DKL_TX_DPCNTL0 0x2C0 10610 #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) 10611 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) 10612 #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) 10613 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) 10614 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) 10615 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) 10616 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ 10617 _DKL_PHY1_BASE, \ 10618 _DKL_PHY2_BASE) + \ 10619 _DKL_TX_DPCNTL0) 10620 10621 #define _DKL_TX_DPCNTL1 0x2C4 10622 /* Bits are the same as DKL_TX_DPCNTRL0 */ 10623 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ 10624 _DKL_PHY1_BASE, \ 10625 _DKL_PHY2_BASE) + \ 10626 _DKL_TX_DPCNTL1) 10627 10628 #define _DKL_TX_DPCNTL2 0x2C8 10629 #define DKL_TX_DP20BITMODE (1 << 2) 10630 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ 10631 _DKL_PHY1_BASE, \ 10632 _DKL_PHY2_BASE) + \ 10633 _DKL_TX_DPCNTL2) 10634 10635 #define _DKL_TX_FW_CALIB 0x2F8 10636 #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) 10637 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ 10638 _DKL_PHY1_BASE, \ 10639 _DKL_PHY2_BASE) + \ 10640 _DKL_TX_FW_CALIB) 10641 10642 #define _DKL_TX_PMD_LANE_SUS 0xD00 10643 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ 10644 _DKL_PHY1_BASE, \ 10645 _DKL_PHY2_BASE) + \ 10646 _DKL_TX_PMD_LANE_SUS) 10647 10648 #define _DKL_TX_DW17 0xDC4 10649 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ 10650 _DKL_PHY1_BASE, \ 10651 _DKL_PHY2_BASE) + \ 10652 _DKL_TX_DW17) 10653 10654 #define _DKL_TX_DW18 0xDC8 10655 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ 10656 _DKL_PHY1_BASE, \ 10657 _DKL_PHY2_BASE) + \ 10658 _DKL_TX_DW18) 10659 10660 #define _DKL_DP_MODE 0xA0 10661 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ 10662 _DKL_PHY1_BASE, \ 10663 _DKL_PHY2_BASE) + \ 10664 _DKL_DP_MODE) 10665 10666 #define _DKL_CMN_UC_DW27 0x36C 10667 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) 10668 #define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ 10669 _DKL_PHY1_BASE, \ 10670 _DKL_PHY2_BASE) + \ 10671 _DKL_CMN_UC_DW27) 10672 10673 /* 10674 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than 10675 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 10676 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address 10677 * bits that point the 4KB window into the full PHY register space. 10678 */ 10679 #define _HIP_INDEX_REG0 0x1010A0 10680 #define _HIP_INDEX_REG1 0x1010A4 10681 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ 10682 : _HIP_INDEX_REG1) 10683 #define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) 10684 #define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) 10685 10686 /* BXT display engine PLL */ 10687 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 10688 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 10689 #define BXT_DE_PLL_RATIO_MASK 0xff 10690 10691 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 10692 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 10693 #define BXT_DE_PLL_LOCK (1 << 30) 10694 #define CNL_CDCLK_PLL_RATIO(x) (x) 10695 #define CNL_CDCLK_PLL_RATIO_MASK 0xff 10696 10697 /* GEN9 DC */ 10698 #define DC_STATE_EN _MMIO(0x45504) 10699 #define DC_STATE_DISABLE 0 10700 #define DC_STATE_EN_DC3CO REG_BIT(30) 10701 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 10702 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 10703 #define DC_STATE_EN_DC9 (1 << 3) 10704 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 10705 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 10706 10707 #define DC_STATE_DEBUG _MMIO(0x45520) 10708 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 10709 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 10710 10711 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) 10712 #define BXT_REQ_DATA_MASK 0x3F 10713 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12 10714 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12) 10715 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333 10716 10717 #define BXT_D_CR_DRP0_DUNIT8 0x1000 10718 #define BXT_D_CR_DRP0_DUNIT9 0x1200 10719 #define BXT_D_CR_DRP0_DUNIT_START 8 10720 #define BXT_D_CR_DRP0_DUNIT_END 11 10721 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ 10722 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\ 10723 BXT_D_CR_DRP0_DUNIT9)) 10724 #define BXT_DRAM_RANK_MASK 0x3 10725 #define BXT_DRAM_RANK_SINGLE 0x1 10726 #define BXT_DRAM_RANK_DUAL 0x3 10727 #define BXT_DRAM_WIDTH_MASK (0x3 << 4) 10728 #define BXT_DRAM_WIDTH_SHIFT 4 10729 #define BXT_DRAM_WIDTH_X8 (0x0 << 4) 10730 #define BXT_DRAM_WIDTH_X16 (0x1 << 4) 10731 #define BXT_DRAM_WIDTH_X32 (0x2 << 4) 10732 #define BXT_DRAM_WIDTH_X64 (0x3 << 4) 10733 #define BXT_DRAM_SIZE_MASK (0x7 << 6) 10734 #define BXT_DRAM_SIZE_SHIFT 6 10735 #define BXT_DRAM_SIZE_4GBIT (0x0 << 6) 10736 #define BXT_DRAM_SIZE_6GBIT (0x1 << 6) 10737 #define BXT_DRAM_SIZE_8GBIT (0x2 << 6) 10738 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6) 10739 #define BXT_DRAM_SIZE_16GBIT (0x4 << 6) 10740 #define BXT_DRAM_TYPE_MASK (0x7 << 22) 10741 #define BXT_DRAM_TYPE_SHIFT 22 10742 #define BXT_DRAM_TYPE_DDR3 (0x0 << 22) 10743 #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22) 10744 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) 10745 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22) 10746 10747 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666 10748 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) 10749 #define SKL_REQ_DATA_MASK (0xF << 0) 10750 10751 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) 10752 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) 10753 #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) 10754 #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) 10755 #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) 10756 #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) 10757 10758 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 10759 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 10760 #define SKL_DRAM_S_SHIFT 16 10761 #define SKL_DRAM_SIZE_MASK 0x3F 10762 #define SKL_DRAM_WIDTH_MASK (0x3 << 8) 10763 #define SKL_DRAM_WIDTH_SHIFT 8 10764 #define SKL_DRAM_WIDTH_X8 (0x0 << 8) 10765 #define SKL_DRAM_WIDTH_X16 (0x1 << 8) 10766 #define SKL_DRAM_WIDTH_X32 (0x2 << 8) 10767 #define SKL_DRAM_RANK_MASK (0x1 << 10) 10768 #define SKL_DRAM_RANK_SHIFT 10 10769 #define SKL_DRAM_RANK_1 (0x0 << 10) 10770 #define SKL_DRAM_RANK_2 (0x1 << 10) 10771 #define SKL_DRAM_RANK_MASK (0x1 << 10) 10772 #define CNL_DRAM_SIZE_MASK 0x7F 10773 #define CNL_DRAM_WIDTH_MASK (0x3 << 7) 10774 #define CNL_DRAM_WIDTH_SHIFT 7 10775 #define CNL_DRAM_WIDTH_X8 (0x0 << 7) 10776 #define CNL_DRAM_WIDTH_X16 (0x1 << 7) 10777 #define CNL_DRAM_WIDTH_X32 (0x2 << 7) 10778 #define CNL_DRAM_RANK_MASK (0x3 << 9) 10779 #define CNL_DRAM_RANK_SHIFT 9 10780 #define CNL_DRAM_RANK_1 (0x0 << 9) 10781 #define CNL_DRAM_RANK_2 (0x1 << 9) 10782 #define CNL_DRAM_RANK_3 (0x2 << 9) 10783 #define CNL_DRAM_RANK_4 (0x3 << 9) 10784 10785 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 10786 * since on HSW we can't write to it using I915_WRITE. */ 10787 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 10788 #define D_COMP_BDW _MMIO(0x138144) 10789 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9) 10790 #define D_COMP_COMP_FORCE (1 << 8) 10791 #define D_COMP_COMP_DISABLE (1 << 0) 10792 10793 /* Pipe WM_LINETIME - watermark line time */ 10794 #define _WM_LINETIME_A 0x45270 10795 #define _WM_LINETIME_B 0x45274 10796 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 10797 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 10798 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 10799 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 10800 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 10801 10802 /* SFUSE_STRAP */ 10803 #define SFUSE_STRAP _MMIO(0xc2014) 10804 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 10805 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 10806 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 10807 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 10808 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 10809 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 10810 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 10811 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 10812 10813 #define WM_MISC _MMIO(0x45260) 10814 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 10815 10816 #define WM_DBG _MMIO(0x45280) 10817 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 10818 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 10819 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 10820 10821 /* pipe CSC */ 10822 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 10823 #define _PIPE_A_CSC_COEFF_BY 0x49014 10824 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 10825 #define _PIPE_A_CSC_COEFF_BU 0x4901c 10826 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 10827 #define _PIPE_A_CSC_COEFF_BV 0x49024 10828 10829 #define _PIPE_A_CSC_MODE 0x49028 10830 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 10831 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 10832 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 10833 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 10834 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 10835 10836 #define _PIPE_A_CSC_PREOFF_HI 0x49030 10837 #define _PIPE_A_CSC_PREOFF_ME 0x49034 10838 #define _PIPE_A_CSC_PREOFF_LO 0x49038 10839 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 10840 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 10841 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 10842 10843 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 10844 #define _PIPE_B_CSC_COEFF_BY 0x49114 10845 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 10846 #define _PIPE_B_CSC_COEFF_BU 0x4911c 10847 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 10848 #define _PIPE_B_CSC_COEFF_BV 0x49124 10849 #define _PIPE_B_CSC_MODE 0x49128 10850 #define _PIPE_B_CSC_PREOFF_HI 0x49130 10851 #define _PIPE_B_CSC_PREOFF_ME 0x49134 10852 #define _PIPE_B_CSC_PREOFF_LO 0x49138 10853 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 10854 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 10855 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 10856 10857 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 10858 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 10859 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 10860 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 10861 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 10862 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 10863 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 10864 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 10865 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 10866 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 10867 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 10868 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 10869 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 10870 10871 /* Pipe Output CSC */ 10872 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 10873 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 10874 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 10875 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 10876 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 10877 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 10878 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 10879 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 10880 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 10881 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 10882 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 10883 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 10884 10885 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 10886 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 10887 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 10888 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 10889 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 10890 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 10891 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 10892 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 10893 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 10894 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 10895 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 10896 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 10897 10898 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 10899 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 10900 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 10901 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 10902 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 10903 _PIPE_B_OUTPUT_CSC_COEFF_BY) 10904 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 10905 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 10906 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 10907 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 10908 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 10909 _PIPE_B_OUTPUT_CSC_COEFF_BU) 10910 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 10911 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 10912 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 10913 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 10914 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 10915 _PIPE_B_OUTPUT_CSC_COEFF_BV) 10916 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10917 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 10918 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 10919 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10920 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 10921 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 10922 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10923 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 10924 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 10925 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10926 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 10927 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 10928 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10929 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 10930 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 10931 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10932 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 10933 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 10934 10935 /* pipe degamma/gamma LUTs on IVB+ */ 10936 #define _PAL_PREC_INDEX_A 0x4A400 10937 #define _PAL_PREC_INDEX_B 0x4AC00 10938 #define _PAL_PREC_INDEX_C 0x4B400 10939 #define PAL_PREC_10_12_BIT (0 << 31) 10940 #define PAL_PREC_SPLIT_MODE (1 << 31) 10941 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 10942 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 10943 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 10944 #define _PAL_PREC_DATA_A 0x4A404 10945 #define _PAL_PREC_DATA_B 0x4AC04 10946 #define _PAL_PREC_DATA_C 0x4B404 10947 #define _PAL_PREC_GC_MAX_A 0x4A410 10948 #define _PAL_PREC_GC_MAX_B 0x4AC10 10949 #define _PAL_PREC_GC_MAX_C 0x4B410 10950 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 10951 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 10952 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 10953 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 10954 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 10955 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 10956 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 10957 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 10958 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 10959 10960 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 10961 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 10962 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 10963 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 10964 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 10965 10966 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 10967 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 10968 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 10969 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 10970 #define _PRE_CSC_GAMC_DATA_A 0x4A488 10971 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 10972 #define _PRE_CSC_GAMC_DATA_C 0x4B488 10973 10974 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 10975 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 10976 10977 /* ICL Multi segmented gamma */ 10978 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 10979 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 10980 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 10981 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 10982 10983 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 10984 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 10985 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 10986 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 10987 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 10988 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 10989 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 10990 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 10991 10992 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 10993 _PAL_PREC_MULTI_SEG_INDEX_A, \ 10994 _PAL_PREC_MULTI_SEG_INDEX_B) 10995 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 10996 _PAL_PREC_MULTI_SEG_DATA_A, \ 10997 _PAL_PREC_MULTI_SEG_DATA_B) 10998 10999 /* pipe CSC & degamma/gamma LUTs on CHV */ 11000 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 11001 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 11002 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 11003 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 11004 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 11005 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 11006 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 11007 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 11008 #define CGM_PIPE_MODE_GAMMA (1 << 2) 11009 #define CGM_PIPE_MODE_CSC (1 << 1) 11010 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 11011 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 11012 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 11013 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 11014 11015 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 11016 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 11017 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 11018 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 11019 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 11020 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 11021 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 11022 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 11023 11024 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 11025 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 11026 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 11027 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 11028 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 11029 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 11030 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 11031 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 11032 11033 /* MIPI DSI registers */ 11034 11035 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 11036 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 11037 11038 /* Gen11 DSI */ 11039 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ 11040 dsi0, dsi1) 11041 11042 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 11043 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 11044 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 11045 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 11046 11047 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090 11048 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890 11049 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 11050 _ICL_DSI_ESC_CLK_DIV0, \ 11051 _ICL_DSI_ESC_CLK_DIV1) 11052 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190 11053 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 11054 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 11055 _ICL_DPHY_ESC_CLK_DIV0, \ 11056 _ICL_DPHY_ESC_CLK_DIV1) 11057 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) 11058 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 11059 #define ICL_ESC_CLK_DIV_MASK 0x1ff 11060 #define ICL_ESC_CLK_DIV_SHIFT 0 11061 #define DSI_MAX_ESC_CLK 20000 /* in KHz */ 11062 11063 #define _DSI_CMD_FRMCTL_0 0x6b034 11064 #define _DSI_CMD_FRMCTL_1 0x6b834 11065 #define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \ 11066 _DSI_CMD_FRMCTL_0,\ 11067 _DSI_CMD_FRMCTL_1) 11068 #define DSI_FRAME_UPDATE_REQUEST (1 << 31) 11069 #define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29) 11070 #define DSI_NULL_PACKET_ENABLE (1 << 28) 11071 #define DSI_FRAME_IN_PROGRESS (1 << 0) 11072 11073 #define _DSI_INTR_MASK_REG_0 0x6b070 11074 #define _DSI_INTR_MASK_REG_1 0x6b870 11075 #define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \ 11076 _DSI_INTR_MASK_REG_0,\ 11077 _DSI_INTR_MASK_REG_1) 11078 11079 #define _DSI_INTR_IDENT_REG_0 0x6b074 11080 #define _DSI_INTR_IDENT_REG_1 0x6b874 11081 #define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \ 11082 _DSI_INTR_IDENT_REG_0,\ 11083 _DSI_INTR_IDENT_REG_1) 11084 #define DSI_TE_EVENT (1 << 31) 11085 #define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30) 11086 #define DSI_TX_DATA (1 << 29) 11087 #define DSI_ULPS_ENTRY_DONE (1 << 28) 11088 #define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27) 11089 #define DSI_HOST_CHKSUM_ERROR (1 << 26) 11090 #define DSI_HOST_MULTI_ECC_ERROR (1 << 25) 11091 #define DSI_HOST_SINGL_ECC_ERROR (1 << 24) 11092 #define DSI_HOST_CONTENTION_DETECTED (1 << 23) 11093 #define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22) 11094 #define DSI_HOST_TIMEOUT_ERROR (1 << 21) 11095 #define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20) 11096 #define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19) 11097 #define DSI_FRAME_UPDATE_DONE (1 << 16) 11098 #define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15) 11099 #define DSI_INVALID_TX_LENGTH (1 << 13) 11100 #define DSI_INVALID_VC (1 << 12) 11101 #define DSI_INVALID_DATA_TYPE (1 << 11) 11102 #define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10) 11103 #define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9) 11104 #define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8) 11105 #define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7) 11106 #define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6) 11107 #define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5) 11108 #define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4) 11109 #define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3) 11110 #define DSI_EOT_SYNC_ERROR (1 << 2) 11111 #define DSI_SOT_SYNC_ERROR (1 << 1) 11112 #define DSI_SOT_ERROR (1 << 0) 11113 11114 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 11115 #define GEN4_TIMESTAMP _MMIO(0x2358) 11116 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 11117 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 11118 11119 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 11120 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 11121 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 11122 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 11123 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 11124 11125 #define _PIPE_FRMTMSTMP_A 0x70048 11126 #define PIPE_FRMTMSTMP(pipe) \ 11127 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 11128 11129 /* BXT MIPI clock controls */ 11130 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 11131 11132 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 11133 #define BXT_MIPI1_DIV_SHIFT 26 11134 #define BXT_MIPI2_DIV_SHIFT 10 11135 #define BXT_MIPI_DIV_SHIFT(port) \ 11136 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 11137 BXT_MIPI2_DIV_SHIFT) 11138 11139 /* TX control divider to select actual TX clock output from (8x/var) */ 11140 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 11141 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 11142 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 11143 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 11144 BXT_MIPI2_TX_ESCLK_SHIFT) 11145 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 11146 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 11147 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 11148 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 11149 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 11150 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 11151 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 11152 /* RX upper control divider to select actual RX clock output from 8x */ 11153 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 11154 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 11155 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 11156 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 11157 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 11158 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 11159 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 11160 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 11161 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 11162 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 11163 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 11164 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 11165 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 11166 #define BXT_MIPI1_8X_BY3_SHIFT 19 11167 #define BXT_MIPI2_8X_BY3_SHIFT 3 11168 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 11169 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 11170 BXT_MIPI2_8X_BY3_SHIFT) 11171 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 11172 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 11173 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 11174 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 11175 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 11176 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 11177 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 11178 /* RX lower control divider to select actual RX clock output from 8x */ 11179 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 11180 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 11181 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 11182 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 11183 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 11184 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 11185 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 11186 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 11187 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 11188 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 11189 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 11190 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 11191 11192 #define RX_DIVIDER_BIT_1_2 0x3 11193 #define RX_DIVIDER_BIT_3_4 0xC 11194 11195 /* BXT MIPI mode configure */ 11196 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 11197 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 11198 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 11199 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 11200 11201 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 11202 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 11203 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 11204 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 11205 11206 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 11207 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 11208 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 11209 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 11210 11211 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 11212 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 11213 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 11214 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 11215 #define BXT_DSIC_16X_BY1 (0 << 10) 11216 #define BXT_DSIC_16X_BY2 (1 << 10) 11217 #define BXT_DSIC_16X_BY3 (2 << 10) 11218 #define BXT_DSIC_16X_BY4 (3 << 10) 11219 #define BXT_DSIC_16X_MASK (3 << 10) 11220 #define BXT_DSIA_16X_BY1 (0 << 8) 11221 #define BXT_DSIA_16X_BY2 (1 << 8) 11222 #define BXT_DSIA_16X_BY3 (2 << 8) 11223 #define BXT_DSIA_16X_BY4 (3 << 8) 11224 #define BXT_DSIA_16X_MASK (3 << 8) 11225 #define BXT_DSI_FREQ_SEL_SHIFT 8 11226 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 11227 11228 #define BXT_DSI_PLL_RATIO_MAX 0x7D 11229 #define BXT_DSI_PLL_RATIO_MIN 0x22 11230 #define GLK_DSI_PLL_RATIO_MAX 0x6F 11231 #define GLK_DSI_PLL_RATIO_MIN 0x22 11232 #define BXT_DSI_PLL_RATIO_MASK 0xFF 11233 #define BXT_REF_CLOCK_KHZ 19200 11234 11235 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 11236 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 11237 #define BXT_DSI_PLL_LOCKED (1 << 30) 11238 11239 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 11240 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 11241 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 11242 11243 /* BXT port control */ 11244 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 11245 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 11246 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 11247 11248 /* ICL DSI MODE control */ 11249 #define _ICL_DSI_IO_MODECTL_0 0x6B094 11250 #define _ICL_DSI_IO_MODECTL_1 0x6B894 11251 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ 11252 _ICL_DSI_IO_MODECTL_0, \ 11253 _ICL_DSI_IO_MODECTL_1) 11254 #define COMBO_PHY_MODE_DSI (1 << 0) 11255 11256 /* Display Stream Splitter Control */ 11257 #define DSS_CTL1 _MMIO(0x67400) 11258 #define SPLITTER_ENABLE (1 << 31) 11259 #define JOINER_ENABLE (1 << 30) 11260 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 11261 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 11262 #define OVERLAP_PIXELS_MASK (0xf << 16) 11263 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 11264 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 11265 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 11266 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 11267 11268 #define DSS_CTL2 _MMIO(0x67404) 11269 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 11270 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 11271 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 11272 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 11273 11274 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 11275 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 11276 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11277 _ICL_PIPE_DSS_CTL1_PB, \ 11278 _ICL_PIPE_DSS_CTL1_PC) 11279 #define BIG_JOINER_ENABLE (1 << 29) 11280 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 11281 #define VGA_CENTERING_ENABLE (1 << 27) 11282 11283 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 11284 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 11285 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11286 _ICL_PIPE_DSS_CTL2_PB, \ 11287 _ICL_PIPE_DSS_CTL2_PC) 11288 11289 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 11290 #define STAP_SELECT (1 << 0) 11291 11292 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 11293 #define HS_IO_CTRL_SELECT (1 << 0) 11294 11295 #define DPI_ENABLE (1 << 31) /* A + C */ 11296 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 11297 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 11298 #define DUAL_LINK_MODE_SHIFT 26 11299 #define DUAL_LINK_MODE_MASK (1 << 26) 11300 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 11301 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 11302 #define DITHERING_ENABLE (1 << 25) /* A + C */ 11303 #define FLOPPED_HSTX (1 << 23) 11304 #define DE_INVERT (1 << 19) /* XXX */ 11305 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 11306 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 11307 #define AFE_LATCHOUT (1 << 17) 11308 #define LP_OUTPUT_HOLD (1 << 16) 11309 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 11310 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 11311 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 11312 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 11313 #define CSB_SHIFT 9 11314 #define CSB_MASK (3 << 9) 11315 #define CSB_20MHZ (0 << 9) 11316 #define CSB_10MHZ (1 << 9) 11317 #define CSB_40MHZ (2 << 9) 11318 #define BANDGAP_MASK (1 << 8) 11319 #define BANDGAP_PNW_CIRCUIT (0 << 8) 11320 #define BANDGAP_LNC_CIRCUIT (1 << 8) 11321 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 11322 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 11323 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 11324 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 11325 #define TEARING_EFFECT_MASK (3 << 2) 11326 #define TEARING_EFFECT_OFF (0 << 2) 11327 #define TEARING_EFFECT_DSI (1 << 2) 11328 #define TEARING_EFFECT_GPIO (2 << 2) 11329 #define LANE_CONFIGURATION_SHIFT 0 11330 #define LANE_CONFIGURATION_MASK (3 << 0) 11331 #define LANE_CONFIGURATION_4LANE (0 << 0) 11332 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 11333 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 11334 11335 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 11336 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 11337 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 11338 #define TEARING_EFFECT_DELAY_SHIFT 0 11339 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 11340 11341 /* XXX: all bits reserved */ 11342 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 11343 11344 /* MIPI DSI Controller and D-PHY registers */ 11345 11346 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 11347 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 11348 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 11349 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 11350 #define ULPS_STATE_MASK (3 << 1) 11351 #define ULPS_STATE_ENTER (2 << 1) 11352 #define ULPS_STATE_EXIT (1 << 1) 11353 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 11354 #define DEVICE_READY (1 << 0) 11355 11356 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 11357 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 11358 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 11359 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 11360 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 11361 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 11362 #define TEARING_EFFECT (1 << 31) 11363 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 11364 #define GEN_READ_DATA_AVAIL (1 << 29) 11365 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 11366 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 11367 #define RX_PROT_VIOLATION (1 << 26) 11368 #define RX_INVALID_TX_LENGTH (1 << 25) 11369 #define ACK_WITH_NO_ERROR (1 << 24) 11370 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 11371 #define LP_RX_TIMEOUT (1 << 22) 11372 #define HS_TX_TIMEOUT (1 << 21) 11373 #define DPI_FIFO_UNDERRUN (1 << 20) 11374 #define LOW_CONTENTION (1 << 19) 11375 #define HIGH_CONTENTION (1 << 18) 11376 #define TXDSI_VC_ID_INVALID (1 << 17) 11377 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 11378 #define TXCHECKSUM_ERROR (1 << 15) 11379 #define TXECC_MULTIBIT_ERROR (1 << 14) 11380 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 11381 #define TXFALSE_CONTROL_ERROR (1 << 12) 11382 #define RXDSI_VC_ID_INVALID (1 << 11) 11383 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 11384 #define RXCHECKSUM_ERROR (1 << 9) 11385 #define RXECC_MULTIBIT_ERROR (1 << 8) 11386 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 11387 #define RXFALSE_CONTROL_ERROR (1 << 6) 11388 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 11389 #define RX_LP_TX_SYNC_ERROR (1 << 4) 11390 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 11391 #define RXEOT_SYNC_ERROR (1 << 2) 11392 #define RXSOT_SYNC_ERROR (1 << 1) 11393 #define RXSOT_ERROR (1 << 0) 11394 11395 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 11396 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 11397 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 11398 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 11399 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 11400 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 11401 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 11402 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 11403 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 11404 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 11405 #define VID_MODE_FORMAT_MASK (0xf << 7) 11406 #define VID_MODE_NOT_SUPPORTED (0 << 7) 11407 #define VID_MODE_FORMAT_RGB565 (1 << 7) 11408 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 11409 #define VID_MODE_FORMAT_RGB666 (3 << 7) 11410 #define VID_MODE_FORMAT_RGB888 (4 << 7) 11411 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 11412 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 11413 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 11414 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 11415 #define DATA_LANES_PRG_REG_SHIFT 0 11416 #define DATA_LANES_PRG_REG_MASK (7 << 0) 11417 11418 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 11419 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 11420 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 11421 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 11422 11423 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 11424 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 11425 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 11426 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 11427 11428 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 11429 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 11430 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 11431 #define TURN_AROUND_TIMEOUT_MASK 0x3f 11432 11433 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 11434 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 11435 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 11436 #define DEVICE_RESET_TIMER_MASK 0xffff 11437 11438 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 11439 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 11440 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 11441 #define VERTICAL_ADDRESS_SHIFT 16 11442 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 11443 #define HORIZONTAL_ADDRESS_SHIFT 0 11444 #define HORIZONTAL_ADDRESS_MASK 0xffff 11445 11446 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 11447 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 11448 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 11449 #define DBI_FIFO_EMPTY_HALF (0 << 0) 11450 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 11451 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 11452 11453 /* regs below are bits 15:0 */ 11454 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 11455 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 11456 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 11457 11458 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 11459 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 11460 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 11461 11462 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 11463 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 11464 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 11465 11466 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 11467 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 11468 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 11469 11470 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 11471 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 11472 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 11473 11474 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 11475 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 11476 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 11477 11478 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 11479 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 11480 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 11481 11482 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 11483 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 11484 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 11485 11486 /* regs above are bits 15:0 */ 11487 11488 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 11489 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 11490 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 11491 #define DPI_LP_MODE (1 << 6) 11492 #define BACKLIGHT_OFF (1 << 5) 11493 #define BACKLIGHT_ON (1 << 4) 11494 #define COLOR_MODE_OFF (1 << 3) 11495 #define COLOR_MODE_ON (1 << 2) 11496 #define TURN_ON (1 << 1) 11497 #define SHUTDOWN (1 << 0) 11498 11499 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 11500 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 11501 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 11502 #define COMMAND_BYTE_SHIFT 0 11503 #define COMMAND_BYTE_MASK (0x3f << 0) 11504 11505 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 11506 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 11507 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 11508 #define MASTER_INIT_TIMER_SHIFT 0 11509 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 11510 11511 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 11512 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 11513 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 11514 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 11515 #define MAX_RETURN_PKT_SIZE_SHIFT 0 11516 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 11517 11518 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 11519 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 11520 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 11521 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 11522 #define DISABLE_VIDEO_BTA (1 << 3) 11523 #define IP_TG_CONFIG (1 << 2) 11524 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 11525 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 11526 #define VIDEO_MODE_BURST (3 << 0) 11527 11528 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 11529 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 11530 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 11531 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 11532 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 11533 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 11534 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 11535 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 11536 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 11537 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 11538 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 11539 #define CLOCKSTOP (1 << 1) 11540 #define EOT_DISABLE (1 << 0) 11541 11542 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 11543 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 11544 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 11545 #define LP_BYTECLK_SHIFT 0 11546 #define LP_BYTECLK_MASK (0xffff << 0) 11547 11548 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 11549 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 11550 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 11551 11552 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 11553 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 11554 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 11555 11556 /* bits 31:0 */ 11557 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 11558 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 11559 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 11560 11561 /* bits 31:0 */ 11562 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 11563 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 11564 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 11565 11566 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 11567 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 11568 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 11569 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 11570 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 11571 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 11572 #define LONG_PACKET_WORD_COUNT_SHIFT 8 11573 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 11574 #define SHORT_PACKET_PARAM_SHIFT 8 11575 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 11576 #define VIRTUAL_CHANNEL_SHIFT 6 11577 #define VIRTUAL_CHANNEL_MASK (3 << 6) 11578 #define DATA_TYPE_SHIFT 0 11579 #define DATA_TYPE_MASK (0x3f << 0) 11580 /* data type values, see include/video/mipi_display.h */ 11581 11582 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 11583 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 11584 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 11585 #define DPI_FIFO_EMPTY (1 << 28) 11586 #define DBI_FIFO_EMPTY (1 << 27) 11587 #define LP_CTRL_FIFO_EMPTY (1 << 26) 11588 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 11589 #define LP_CTRL_FIFO_FULL (1 << 24) 11590 #define HS_CTRL_FIFO_EMPTY (1 << 18) 11591 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 11592 #define HS_CTRL_FIFO_FULL (1 << 16) 11593 #define LP_DATA_FIFO_EMPTY (1 << 10) 11594 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 11595 #define LP_DATA_FIFO_FULL (1 << 8) 11596 #define HS_DATA_FIFO_EMPTY (1 << 2) 11597 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 11598 #define HS_DATA_FIFO_FULL (1 << 0) 11599 11600 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 11601 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 11602 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 11603 #define DBI_HS_LP_MODE_MASK (1 << 0) 11604 #define DBI_LP_MODE (1 << 0) 11605 #define DBI_HS_MODE (0 << 0) 11606 11607 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 11608 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 11609 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 11610 #define EXIT_ZERO_COUNT_SHIFT 24 11611 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 11612 #define TRAIL_COUNT_SHIFT 16 11613 #define TRAIL_COUNT_MASK (0x1f << 16) 11614 #define CLK_ZERO_COUNT_SHIFT 8 11615 #define CLK_ZERO_COUNT_MASK (0xff << 8) 11616 #define PREPARE_COUNT_SHIFT 0 11617 #define PREPARE_COUNT_MASK (0x3f << 0) 11618 11619 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088 11620 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888 11621 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ 11622 _ICL_DSI_T_INIT_MASTER_0,\ 11623 _ICL_DSI_T_INIT_MASTER_1) 11624 11625 #define _DPHY_CLK_TIMING_PARAM_0 0x162180 11626 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180 11627 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 11628 _DPHY_CLK_TIMING_PARAM_0,\ 11629 _DPHY_CLK_TIMING_PARAM_1) 11630 #define _DSI_CLK_TIMING_PARAM_0 0x6b080 11631 #define _DSI_CLK_TIMING_PARAM_1 0x6b880 11632 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 11633 _DSI_CLK_TIMING_PARAM_0,\ 11634 _DSI_CLK_TIMING_PARAM_1) 11635 #define CLK_PREPARE_OVERRIDE (1 << 31) 11636 #define CLK_PREPARE(x) ((x) << 28) 11637 #define CLK_PREPARE_MASK (0x7 << 28) 11638 #define CLK_PREPARE_SHIFT 28 11639 #define CLK_ZERO_OVERRIDE (1 << 27) 11640 #define CLK_ZERO(x) ((x) << 20) 11641 #define CLK_ZERO_MASK (0xf << 20) 11642 #define CLK_ZERO_SHIFT 20 11643 #define CLK_PRE_OVERRIDE (1 << 19) 11644 #define CLK_PRE(x) ((x) << 16) 11645 #define CLK_PRE_MASK (0x3 << 16) 11646 #define CLK_PRE_SHIFT 16 11647 #define CLK_POST_OVERRIDE (1 << 15) 11648 #define CLK_POST(x) ((x) << 8) 11649 #define CLK_POST_MASK (0x7 << 8) 11650 #define CLK_POST_SHIFT 8 11651 #define CLK_TRAIL_OVERRIDE (1 << 7) 11652 #define CLK_TRAIL(x) ((x) << 0) 11653 #define CLK_TRAIL_MASK (0xf << 0) 11654 #define CLK_TRAIL_SHIFT 0 11655 11656 #define _DPHY_DATA_TIMING_PARAM_0 0x162184 11657 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184 11658 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11659 _DPHY_DATA_TIMING_PARAM_0,\ 11660 _DPHY_DATA_TIMING_PARAM_1) 11661 #define _DSI_DATA_TIMING_PARAM_0 0x6B084 11662 #define _DSI_DATA_TIMING_PARAM_1 0x6B884 11663 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11664 _DSI_DATA_TIMING_PARAM_0,\ 11665 _DSI_DATA_TIMING_PARAM_1) 11666 #define HS_PREPARE_OVERRIDE (1 << 31) 11667 #define HS_PREPARE(x) ((x) << 24) 11668 #define HS_PREPARE_MASK (0x7 << 24) 11669 #define HS_PREPARE_SHIFT 24 11670 #define HS_ZERO_OVERRIDE (1 << 23) 11671 #define HS_ZERO(x) ((x) << 16) 11672 #define HS_ZERO_MASK (0xf << 16) 11673 #define HS_ZERO_SHIFT 16 11674 #define HS_TRAIL_OVERRIDE (1 << 15) 11675 #define HS_TRAIL(x) ((x) << 8) 11676 #define HS_TRAIL_MASK (0x7 << 8) 11677 #define HS_TRAIL_SHIFT 8 11678 #define HS_EXIT_OVERRIDE (1 << 7) 11679 #define HS_EXIT(x) ((x) << 0) 11680 #define HS_EXIT_MASK (0x7 << 0) 11681 #define HS_EXIT_SHIFT 0 11682 11683 #define _DPHY_TA_TIMING_PARAM_0 0x162188 11684 #define _DPHY_TA_TIMING_PARAM_1 0x6c188 11685 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11686 _DPHY_TA_TIMING_PARAM_0,\ 11687 _DPHY_TA_TIMING_PARAM_1) 11688 #define _DSI_TA_TIMING_PARAM_0 0x6b098 11689 #define _DSI_TA_TIMING_PARAM_1 0x6b898 11690 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11691 _DSI_TA_TIMING_PARAM_0,\ 11692 _DSI_TA_TIMING_PARAM_1) 11693 #define TA_SURE_OVERRIDE (1 << 31) 11694 #define TA_SURE(x) ((x) << 16) 11695 #define TA_SURE_MASK (0x1f << 16) 11696 #define TA_SURE_SHIFT 16 11697 #define TA_GO_OVERRIDE (1 << 15) 11698 #define TA_GO(x) ((x) << 8) 11699 #define TA_GO_MASK (0xf << 8) 11700 #define TA_GO_SHIFT 8 11701 #define TA_GET_OVERRIDE (1 << 7) 11702 #define TA_GET(x) ((x) << 0) 11703 #define TA_GET_MASK (0xf << 0) 11704 #define TA_GET_SHIFT 0 11705 11706 /* DSI transcoder configuration */ 11707 #define _DSI_TRANS_FUNC_CONF_0 0x6b030 11708 #define _DSI_TRANS_FUNC_CONF_1 0x6b830 11709 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ 11710 _DSI_TRANS_FUNC_CONF_0,\ 11711 _DSI_TRANS_FUNC_CONF_1) 11712 #define OP_MODE_MASK (0x3 << 28) 11713 #define OP_MODE_SHIFT 28 11714 #define CMD_MODE_NO_GATE (0x0 << 28) 11715 #define CMD_MODE_TE_GATE (0x1 << 28) 11716 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28) 11717 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28) 11718 #define TE_SOURCE_GPIO (1 << 27) 11719 #define LINK_READY (1 << 20) 11720 #define PIX_FMT_MASK (0x3 << 16) 11721 #define PIX_FMT_SHIFT 16 11722 #define PIX_FMT_RGB565 (0x0 << 16) 11723 #define PIX_FMT_RGB666_PACKED (0x1 << 16) 11724 #define PIX_FMT_RGB666_LOOSE (0x2 << 16) 11725 #define PIX_FMT_RGB888 (0x3 << 16) 11726 #define PIX_FMT_RGB101010 (0x4 << 16) 11727 #define PIX_FMT_RGB121212 (0x5 << 16) 11728 #define PIX_FMT_COMPRESSED (0x6 << 16) 11729 #define BGR_TRANSMISSION (1 << 15) 11730 #define PIX_VIRT_CHAN(x) ((x) << 12) 11731 #define PIX_VIRT_CHAN_MASK (0x3 << 12) 11732 #define PIX_VIRT_CHAN_SHIFT 12 11733 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10) 11734 #define PIX_BUF_THRESHOLD_SHIFT 10 11735 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) 11736 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) 11737 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) 11738 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10) 11739 #define CONTINUOUS_CLK_MASK (0x3 << 8) 11740 #define CONTINUOUS_CLK_SHIFT 8 11741 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) 11742 #define CLK_HS_OR_LP (0x2 << 8) 11743 #define CLK_HS_CONTINUOUS (0x3 << 8) 11744 #define LINK_CALIBRATION_MASK (0x3 << 4) 11745 #define LINK_CALIBRATION_SHIFT 4 11746 #define CALIBRATION_DISABLED (0x0 << 4) 11747 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) 11748 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) 11749 #define BLANKING_PACKET_ENABLE (1 << 2) 11750 #define S3D_ORIENTATION_LANDSCAPE (1 << 1) 11751 #define EOTP_DISABLED (1 << 0) 11752 11753 #define _DSI_CMD_RXCTL_0 0x6b0d4 11754 #define _DSI_CMD_RXCTL_1 0x6b8d4 11755 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \ 11756 _DSI_CMD_RXCTL_0,\ 11757 _DSI_CMD_RXCTL_1) 11758 #define READ_UNLOADS_DW (1 << 16) 11759 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15) 11760 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14) 11761 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13) 11762 #define RECEIVED_RESET_TRIGGER (1 << 12) 11763 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11) 11764 #define RECEIVED_CRC_WAS_LOST (1 << 10) 11765 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0) 11766 #define NUMBER_RX_PLOAD_DW_SHIFT 0 11767 11768 #define _DSI_CMD_TXCTL_0 0x6b0d0 11769 #define _DSI_CMD_TXCTL_1 0x6b8d0 11770 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \ 11771 _DSI_CMD_TXCTL_0,\ 11772 _DSI_CMD_TXCTL_1) 11773 #define KEEP_LINK_IN_HS (1 << 24) 11774 #define FREE_HEADER_CREDIT_MASK (0x1f << 8) 11775 #define FREE_HEADER_CREDIT_SHIFT 0x8 11776 #define FREE_PLOAD_CREDIT_MASK (0xff << 0) 11777 #define FREE_PLOAD_CREDIT_SHIFT 0 11778 #define MAX_HEADER_CREDIT 0x10 11779 #define MAX_PLOAD_CREDIT 0x40 11780 11781 #define _DSI_CMD_TXHDR_0 0x6b100 11782 #define _DSI_CMD_TXHDR_1 0x6b900 11783 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ 11784 _DSI_CMD_TXHDR_0,\ 11785 _DSI_CMD_TXHDR_1) 11786 #define PAYLOAD_PRESENT (1 << 31) 11787 #define LP_DATA_TRANSFER (1 << 30) 11788 #define VBLANK_FENCE (1 << 29) 11789 #define PARAM_WC_MASK (0xffff << 8) 11790 #define PARAM_WC_LOWER_SHIFT 8 11791 #define PARAM_WC_UPPER_SHIFT 16 11792 #define VC_MASK (0x3 << 6) 11793 #define VC_SHIFT 6 11794 #define DT_MASK (0x3f << 0) 11795 #define DT_SHIFT 0 11796 11797 #define _DSI_CMD_TXPYLD_0 0x6b104 11798 #define _DSI_CMD_TXPYLD_1 0x6b904 11799 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ 11800 _DSI_CMD_TXPYLD_0,\ 11801 _DSI_CMD_TXPYLD_1) 11802 11803 #define _DSI_LP_MSG_0 0x6b0d8 11804 #define _DSI_LP_MSG_1 0x6b8d8 11805 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ 11806 _DSI_LP_MSG_0,\ 11807 _DSI_LP_MSG_1) 11808 #define LPTX_IN_PROGRESS (1 << 17) 11809 #define LINK_IN_ULPS (1 << 16) 11810 #define LINK_ULPS_TYPE_LP11 (1 << 8) 11811 #define LINK_ENTER_ULPS (1 << 0) 11812 11813 /* DSI timeout registers */ 11814 #define _DSI_HSTX_TO_0 0x6b044 11815 #define _DSI_HSTX_TO_1 0x6b844 11816 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ 11817 _DSI_HSTX_TO_0,\ 11818 _DSI_HSTX_TO_1) 11819 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) 11820 #define HSTX_TIMEOUT_VALUE_SHIFT 16 11821 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16) 11822 #define HSTX_TIMED_OUT (1 << 0) 11823 11824 #define _DSI_LPRX_HOST_TO_0 0x6b048 11825 #define _DSI_LPRX_HOST_TO_1 0x6b848 11826 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ 11827 _DSI_LPRX_HOST_TO_0,\ 11828 _DSI_LPRX_HOST_TO_1) 11829 #define LPRX_TIMED_OUT (1 << 16) 11830 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) 11831 #define LPRX_TIMEOUT_VALUE_SHIFT 0 11832 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0) 11833 11834 #define _DSI_PWAIT_TO_0 0x6b040 11835 #define _DSI_PWAIT_TO_1 0x6b840 11836 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ 11837 _DSI_PWAIT_TO_0,\ 11838 _DSI_PWAIT_TO_1) 11839 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) 11840 #define PRESET_TIMEOUT_VALUE_SHIFT 16 11841 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16) 11842 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) 11843 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 11844 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) 11845 11846 #define _DSI_TA_TO_0 0x6b04c 11847 #define _DSI_TA_TO_1 0x6b84c 11848 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \ 11849 _DSI_TA_TO_0,\ 11850 _DSI_TA_TO_1) 11851 #define TA_TIMED_OUT (1 << 16) 11852 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0) 11853 #define TA_TIMEOUT_VALUE_SHIFT 0 11854 #define TA_TIMEOUT_VALUE(x) ((x) << 0) 11855 11856 /* bits 31:0 */ 11857 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 11858 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 11859 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 11860 11861 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 11862 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 11863 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 11864 #define LP_HS_SSW_CNT_SHIFT 16 11865 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 11866 #define HS_LP_PWR_SW_CNT_SHIFT 0 11867 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 11868 11869 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 11870 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 11871 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 11872 #define STOP_STATE_STALL_COUNTER_SHIFT 0 11873 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 11874 11875 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 11876 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 11877 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 11878 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 11879 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 11880 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 11881 #define RX_CONTENTION_DETECTED (1 << 0) 11882 11883 /* XXX: only pipe A ?!? */ 11884 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 11885 #define DBI_TYPEC_ENABLE (1 << 31) 11886 #define DBI_TYPEC_WIP (1 << 30) 11887 #define DBI_TYPEC_OPTION_SHIFT 28 11888 #define DBI_TYPEC_OPTION_MASK (3 << 28) 11889 #define DBI_TYPEC_FREQ_SHIFT 24 11890 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 11891 #define DBI_TYPEC_OVERRIDE (1 << 8) 11892 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 11893 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 11894 11895 11896 /* MIPI adapter registers */ 11897 11898 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 11899 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 11900 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 11901 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 11902 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 11903 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 11904 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 11905 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 11906 #define READ_REQUEST_PRIORITY_SHIFT 3 11907 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 11908 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 11909 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 11910 #define RGB_FLIP_TO_BGR (1 << 2) 11911 11912 #define BXT_PIPE_SELECT_SHIFT 7 11913 #define BXT_PIPE_SELECT_MASK (7 << 7) 11914 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 11915 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 11916 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 11917 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 11918 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 11919 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 11920 #define GLK_LP_WAKE (1 << 22) 11921 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 11922 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 11923 #define GLK_FIREWALL_ENABLE (1 << 16) 11924 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 11925 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 11926 #define BXT_DSC_ENABLE (1 << 3) 11927 #define BXT_RGB_FLIP (1 << 2) 11928 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 11929 #define GLK_MIPIIO_ENABLE (1 << 0) 11930 11931 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 11932 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 11933 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 11934 #define DATA_MEM_ADDRESS_SHIFT 5 11935 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 11936 #define DATA_VALID (1 << 0) 11937 11938 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 11939 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 11940 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 11941 #define DATA_LENGTH_SHIFT 0 11942 #define DATA_LENGTH_MASK (0xfffff << 0) 11943 11944 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 11945 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 11946 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 11947 #define COMMAND_MEM_ADDRESS_SHIFT 5 11948 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 11949 #define AUTO_PWG_ENABLE (1 << 2) 11950 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 11951 #define COMMAND_VALID (1 << 0) 11952 11953 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 11954 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 11955 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 11956 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 11957 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 11958 11959 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 11960 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 11961 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 11962 11963 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 11964 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 11965 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 11966 #define READ_DATA_VALID(n) (1 << (n)) 11967 11968 /* MOCS (Memory Object Control State) registers */ 11969 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 11970 11971 #define __GEN9_RCS0_MOCS0 0xc800 11972 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4) 11973 #define __GEN9_VCS0_MOCS0 0xc900 11974 #define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4) 11975 #define __GEN9_VCS1_MOCS0 0xca00 11976 #define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4) 11977 #define __GEN9_VECS0_MOCS0 0xcb00 11978 #define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4) 11979 #define __GEN9_BCS0_MOCS0 0xcc00 11980 #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4) 11981 #define __GEN11_VCS2_MOCS0 0x10000 11982 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4) 11983 11984 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) 11985 #define PMFLUSHDONE_LNICRSDROP (1 << 20) 11986 #define PMFLUSH_GAPL3UNBLOCK (1 << 21) 11987 #define PMFLUSHDONE_LNEBLK (1 << 22) 11988 11989 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ 11990 11991 /* gamt regs */ 11992 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 11993 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 11994 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 11995 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 11996 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 11997 11998 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 11999 #define MMCD_PCLA (1 << 31) 12000 #define MMCD_HOTSPOT_EN (1 << 27) 12001 12002 #define _ICL_PHY_MISC_A 0x64C00 12003 #define _ICL_PHY_MISC_B 0x64C04 12004 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \ 12005 _ICL_PHY_MISC_B) 12006 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 12007 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 12008 12009 /* Icelake Display Stream Compression Registers */ 12010 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 12011 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 12012 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 12013 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 12014 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 12015 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 12016 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12017 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 12018 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 12019 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12020 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 12021 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 12022 #define DSC_VBR_ENABLE (1 << 19) 12023 #define DSC_422_ENABLE (1 << 18) 12024 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 12025 #define DSC_BLOCK_PREDICTION (1 << 16) 12026 #define DSC_LINE_BUF_DEPTH_SHIFT 12 12027 #define DSC_BPC_SHIFT 8 12028 #define DSC_VER_MIN_SHIFT 4 12029 #define DSC_VER_MAJ (0x1 << 0) 12030 12031 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 12032 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 12033 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 12034 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 12035 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 12036 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 12037 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12038 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 12039 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 12040 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12041 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 12042 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 12043 #define DSC_BPP(bpp) ((bpp) << 0) 12044 12045 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 12046 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 12047 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 12048 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 12049 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 12050 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 12051 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12052 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 12053 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 12054 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12055 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 12056 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 12057 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 12058 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 12059 12060 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 12061 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 12062 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 12063 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 12064 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 12065 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 12066 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12067 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 12068 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 12069 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12070 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 12071 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 12072 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 12073 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 12074 12075 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 12076 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 12077 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 12078 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 12079 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 12080 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 12081 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12082 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 12083 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 12084 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12085 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 12086 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 12087 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 12088 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 12089 12090 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 12091 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 12092 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 12093 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 12094 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 12095 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 12096 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12097 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 12098 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 12099 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12100 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 12101 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 12102 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 12103 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 12104 12105 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 12106 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 12107 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 12108 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 12109 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 12110 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 12111 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12112 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 12113 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 12114 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12115 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 12116 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 12117 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 12118 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 12119 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 12120 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 12121 12122 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 12123 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 12124 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 12125 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 12126 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 12127 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 12128 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12129 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 12130 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 12131 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12132 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 12133 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 12134 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 12135 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 12136 12137 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 12138 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 12139 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 12140 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 12141 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 12142 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 12143 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12144 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 12145 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 12146 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12147 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 12148 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 12149 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 12150 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 12151 12152 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 12153 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 12154 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 12155 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 12156 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 12157 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 12158 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12159 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 12160 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 12161 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12162 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 12163 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 12164 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 12165 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 12166 12167 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 12168 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 12169 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 12170 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 12171 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 12172 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 12173 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12174 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 12175 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 12176 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12177 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 12178 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 12179 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 12180 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 12181 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 12182 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 12183 12184 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 12185 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 12186 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 12187 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 12188 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 12189 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 12190 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12191 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 12192 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 12193 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12194 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 12195 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 12196 12197 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 12198 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 12199 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 12200 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 12201 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 12202 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 12203 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12204 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 12205 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 12206 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12207 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 12208 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 12209 12210 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 12211 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 12212 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 12213 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 12214 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 12215 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 12216 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12217 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 12218 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 12219 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12220 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 12221 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 12222 12223 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 12224 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 12225 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 12226 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 12227 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 12228 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 12229 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12230 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 12231 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 12232 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12233 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 12234 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 12235 12236 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 12237 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 12238 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 12239 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 12240 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 12241 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 12242 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12243 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 12244 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 12245 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12246 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 12247 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 12248 12249 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 12250 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 12251 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 12252 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 12253 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 12254 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 12255 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12256 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 12257 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 12258 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12259 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 12260 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 12261 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 12262 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 12263 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 12264 12265 /* Icelake Rate Control Buffer Threshold Registers */ 12266 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 12267 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 12268 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 12269 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 12270 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 12271 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 12272 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 12273 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 12274 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 12275 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 12276 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 12277 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 12278 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12279 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 12280 _ICL_DSC0_RC_BUF_THRESH_0_PC) 12281 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12282 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 12283 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 12284 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12285 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 12286 _ICL_DSC1_RC_BUF_THRESH_0_PC) 12287 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12288 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 12289 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 12290 12291 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 12292 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 12293 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 12294 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 12295 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 12296 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 12297 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 12298 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 12299 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 12300 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 12301 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 12302 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 12303 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12304 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 12305 _ICL_DSC0_RC_BUF_THRESH_1_PC) 12306 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12307 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 12308 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 12309 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12310 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 12311 _ICL_DSC1_RC_BUF_THRESH_1_PC) 12312 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12313 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 12314 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 12315 12316 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 12317 #define MODULAR_FIA_MASK (1 << 4) 12318 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 12319 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 12320 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 12321 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 12322 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 12323 12324 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 12325 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 12326 12327 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 12328 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 12329 12330 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 12331 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 12332 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 12333 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 12334 12335 /* This register controls the Display State Buffer (DSB) engines. */ 12336 #define _DSBSL_INSTANCE_BASE 0x70B00 12337 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 12338 (pipe) * 0x1000 + (id) * 0x100) 12339 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 12340 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 12341 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 12342 #define DSB_ENABLE (1 << 31) 12343 #define DSB_STATUS (1 << 0) 12344 12345 #define TGL_ROOT_DEVICE_ID 0x9A00 12346 #define TGL_ROOT_DEVICE_MASK 0xFF00 12347 #define TGL_ROOT_DEVICE_SKU_MASK 0xF 12348 #define TGL_ROOT_DEVICE_SKU_ULX 0x2 12349 #define TGL_ROOT_DEVICE_SKU_ULT 0x4 12350 12351 #endif /* _I915_REG_H_ */ 12352