1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 /** 29 * DOC: The i915 register macro definition style guide 30 * 31 * Follow the style described here for new macros, and while changing existing 32 * macros. Do **not** mass change existing definitions just to update the style. 33 * 34 * Layout 35 * '''''' 36 * 37 * Keep helper macros near the top. For example, _PIPE() and friends. 38 * 39 * Prefix macros that generally should not be used outside of this file with 40 * underscore '_'. For example, _PIPE() and friends, single instances of 41 * registers that are defined solely for the use by function-like macros. 42 * 43 * Avoid using the underscore prefixed macros outside of this file. There are 44 * exceptions, but keep them to a minimum. 45 * 46 * There are two basic types of register definitions: Single registers and 47 * register groups. Register groups are registers which have two or more 48 * instances, for example one per pipe, port, transcoder, etc. Register groups 49 * should be defined using function-like macros. 50 * 51 * For single registers, define the register offset first, followed by register 52 * contents. 53 * 54 * For register groups, define the register instance offsets first, prefixed 55 * with underscore, followed by a function-like macro choosing the right 56 * instance based on the parameter, followed by register contents. 57 * 58 * Define the register contents (i.e. bit and bit field macros) from most 59 * significant to least significant bit. Indent the register content macros 60 * using two extra spaces between ``#define`` and the macro name. 61 * 62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field 63 * contents so that they are already shifted in place, and can be directly 64 * OR'd. For convenience, function-like macros may be used to define bit fields, 65 * but do note that the macros may be needed to read as well as write the 66 * register contents. 67 * 68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in 69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix 70 * to the name. 71 * 72 * Group the register and its contents together without blank lines, separate 73 * from other registers and their contents with one blank line. 74 * 75 * Indent macro values from macro names using TABs. Align values vertically. Use 76 * braces in macro values as needed to avoid unintended precedence after macro 77 * substitution. Use spaces in macro values according to kernel coding 78 * style. Use lower case in hexadecimal values. 79 * 80 * Naming 81 * '''''' 82 * 83 * Try to name registers according to the specs. If the register name changes in 84 * the specs from platform to another, stick to the original name. 85 * 86 * Try to re-use existing register macro definitions. Only add new macros for 87 * new register offsets, or when the register contents have changed enough to 88 * warrant a full redefinition. 89 * 90 * When a register macro changes for a new platform, prefix the new macro using 91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 92 * prefix signifies the start platform/generation using the register. 93 * 94 * When a bit (field) macro changes or gets added for a new platform, while 95 * retaining the existing register macro, add a platform acronym or generation 96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 97 * 98 * Examples 99 * '''''''' 100 * 101 * (Note that the values in the example are indented using spaces instead of 102 * TABs to avoid misalignment in generated documentation. Use TABs in the 103 * definitions.):: 104 * 105 * #define _FOO_A 0xf000 106 * #define _FOO_B 0xf001 107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 108 * #define FOO_ENABLE (1 << 31) 109 * #define FOO_MODE_MASK (0xf << 16) 110 * #define FOO_MODE_SHIFT 16 111 * #define FOO_MODE_BAR (0 << 16) 112 * #define FOO_MODE_BAZ (1 << 16) 113 * #define FOO_MODE_QUX_SNB (2 << 16) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 typedef struct { 120 uint32_t reg; 121 } i915_reg_t; 122 123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 124 125 #define INVALID_MMIO_REG _MMIO(0) 126 127 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) 128 { 129 return reg.reg; 130 } 131 132 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 133 { 134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 135 } 136 137 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 138 { 139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 140 } 141 142 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 143 144 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 146 #define _PLANE(plane, a, b) _PIPE(plane, a, b) 147 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) 148 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a))) 149 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 150 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 151 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 152 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 154 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) 155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 156 #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f)) 157 #define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \ 158 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) 159 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 160 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 161 162 #define _MASKED_FIELD(mask, value) ({ \ 163 if (__builtin_constant_p(mask)) \ 164 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 165 if (__builtin_constant_p(value)) \ 166 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 167 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 168 BUILD_BUG_ON_MSG((value) & ~(mask), \ 169 "Incorrect value for mask"); \ 170 (mask) << 16 | (value); }) 171 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 172 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 173 174 /* Engine ID */ 175 176 #define RCS_HW 0 177 #define VCS_HW 1 178 #define BCS_HW 2 179 #define VECS_HW 3 180 #define VCS2_HW 4 181 182 /* Engine class */ 183 184 #define RENDER_CLASS 0 185 #define VIDEO_DECODE_CLASS 1 186 #define VIDEO_ENHANCEMENT_CLASS 2 187 #define COPY_ENGINE_CLASS 3 188 #define OTHER_CLASS 4 189 190 /* PCI config space */ 191 192 #define MCHBAR_I915 0x44 193 #define MCHBAR_I965 0x48 194 #define MCHBAR_SIZE (4 * 4096) 195 196 #define DEVEN 0x54 197 #define DEVEN_MCHBAR_EN (1 << 28) 198 199 /* BSM in include/drm/i915_drm.h */ 200 201 #define HPLLCC 0xc0 /* 85x only */ 202 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 203 #define GC_CLOCK_133_200 (0 << 0) 204 #define GC_CLOCK_100_200 (1 << 0) 205 #define GC_CLOCK_100_133 (2 << 0) 206 #define GC_CLOCK_133_266 (3 << 0) 207 #define GC_CLOCK_133_200_2 (4 << 0) 208 #define GC_CLOCK_133_266_2 (5 << 0) 209 #define GC_CLOCK_166_266 (6 << 0) 210 #define GC_CLOCK_166_250 (7 << 0) 211 212 #define I915_GDRST 0xc0 /* PCI config register */ 213 #define GRDOM_FULL (0 << 2) 214 #define GRDOM_RENDER (1 << 2) 215 #define GRDOM_MEDIA (3 << 2) 216 #define GRDOM_MASK (3 << 2) 217 #define GRDOM_RESET_STATUS (1 << 1) 218 #define GRDOM_RESET_ENABLE (1 << 0) 219 220 /* BSpec only has register offset, PCI device and bit found empirically */ 221 #define I830_CLOCK_GATE 0xc8 /* device 0 */ 222 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 223 224 #define GCDGMBUS 0xcc 225 226 #define GCFGC2 0xda 227 #define GCFGC 0xf0 /* 915+ only */ 228 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 229 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 230 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 231 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 232 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 233 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 234 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 235 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 236 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 237 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 238 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 239 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 240 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 241 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 242 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 243 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 244 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 245 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 246 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 247 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 248 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 249 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 250 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 251 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 252 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 253 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 254 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 255 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 256 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 257 258 #define ASLE 0xe4 259 #define ASLS 0xfc 260 261 #define SWSCI 0xe8 262 #define SWSCI_SCISEL (1 << 15) 263 #define SWSCI_GSSCIE (1 << 0) 264 265 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 266 267 268 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 269 #define ILK_GRDOM_FULL (0<<1) 270 #define ILK_GRDOM_RENDER (1<<1) 271 #define ILK_GRDOM_MEDIA (3<<1) 272 #define ILK_GRDOM_MASK (3<<1) 273 #define ILK_GRDOM_RESET_ENABLE (1<<0) 274 275 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 276 #define GEN6_MBC_SNPCR_SHIFT 21 277 #define GEN6_MBC_SNPCR_MASK (3<<21) 278 #define GEN6_MBC_SNPCR_MAX (0<<21) 279 #define GEN6_MBC_SNPCR_MED (1<<21) 280 #define GEN6_MBC_SNPCR_LOW (2<<21) 281 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 282 283 #define VLV_G3DCTL _MMIO(0x9024) 284 #define VLV_GSCKGCTL _MMIO(0x9028) 285 286 #define GEN6_MBCTL _MMIO(0x0907c) 287 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 288 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 289 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 290 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 291 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 292 293 #define GEN6_GDRST _MMIO(0x941c) 294 #define GEN6_GRDOM_FULL (1 << 0) 295 #define GEN6_GRDOM_RENDER (1 << 1) 296 #define GEN6_GRDOM_MEDIA (1 << 2) 297 #define GEN6_GRDOM_BLT (1 << 3) 298 #define GEN6_GRDOM_VECS (1 << 4) 299 #define GEN9_GRDOM_GUC (1 << 5) 300 #define GEN8_GRDOM_MEDIA2 (1 << 7) 301 302 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228) 303 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518) 304 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220) 305 #define PP_DIR_DCLV_2G 0xffffffff 306 307 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4) 308 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8) 309 310 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 311 #define GEN8_RPCS_ENABLE (1 << 31) 312 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 313 #define GEN8_RPCS_S_CNT_SHIFT 15 314 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 315 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 316 #define GEN8_RPCS_SS_CNT_SHIFT 8 317 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 318 #define GEN8_RPCS_EU_MAX_SHIFT 4 319 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 320 #define GEN8_RPCS_EU_MIN_SHIFT 0 321 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 322 323 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) 324 /* HSW only */ 325 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 326 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 327 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 328 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 329 /* HSW+ */ 330 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 331 #define HSW_RCS_CONTEXT_ENABLE (1 << 7) 332 #define HSW_RCS_INHIBIT (1 << 8) 333 /* Gen8 */ 334 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 335 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 336 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 337 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 338 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 339 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 340 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 341 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 342 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 343 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 344 345 #define GAM_ECOCHK _MMIO(0x4090) 346 #define BDW_DISABLE_HDC_INVALIDATION (1<<25) 347 #define ECOCHK_SNB_BIT (1<<10) 348 #define ECOCHK_DIS_TLB (1<<8) 349 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 350 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 351 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 352 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 353 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 354 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 355 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 356 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 357 358 #define GEN8_CONFIG0 _MMIO(0xD00) 359 #define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1) 360 361 #define GAC_ECO_BITS _MMIO(0x14090) 362 #define ECOBITS_SNB_BIT (1<<13) 363 #define ECOBITS_PPGTT_CACHE64B (3<<8) 364 #define ECOBITS_PPGTT_CACHE4B (0<<8) 365 366 #define GAB_CTL _MMIO(0x24000) 367 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 368 369 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 370 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 371 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 372 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 373 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 374 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 375 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 376 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 377 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 378 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 379 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 380 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 381 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 382 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 383 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 384 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 385 386 /* VGA stuff */ 387 388 #define VGA_ST01_MDA 0x3ba 389 #define VGA_ST01_CGA 0x3da 390 391 #define _VGA_MSR_WRITE _MMIO(0x3c2) 392 #define VGA_MSR_WRITE 0x3c2 393 #define VGA_MSR_READ 0x3cc 394 #define VGA_MSR_MEM_EN (1<<1) 395 #define VGA_MSR_CGA_MODE (1<<0) 396 397 #define VGA_SR_INDEX 0x3c4 398 #define SR01 1 399 #define VGA_SR_DATA 0x3c5 400 401 #define VGA_AR_INDEX 0x3c0 402 #define VGA_AR_VID_EN (1<<5) 403 #define VGA_AR_DATA_WRITE 0x3c0 404 #define VGA_AR_DATA_READ 0x3c1 405 406 #define VGA_GR_INDEX 0x3ce 407 #define VGA_GR_DATA 0x3cf 408 /* GR05 */ 409 #define VGA_GR_MEM_READ_MODE_SHIFT 3 410 #define VGA_GR_MEM_READ_MODE_PLANE 1 411 /* GR06 */ 412 #define VGA_GR_MEM_MODE_MASK 0xc 413 #define VGA_GR_MEM_MODE_SHIFT 2 414 #define VGA_GR_MEM_A0000_AFFFF 0 415 #define VGA_GR_MEM_A0000_BFFFF 1 416 #define VGA_GR_MEM_B0000_B7FFF 2 417 #define VGA_GR_MEM_B0000_BFFFF 3 418 419 #define VGA_DACMASK 0x3c6 420 #define VGA_DACRX 0x3c7 421 #define VGA_DACWX 0x3c8 422 #define VGA_DACDATA 0x3c9 423 424 #define VGA_CR_INDEX_MDA 0x3b4 425 #define VGA_CR_DATA_MDA 0x3b5 426 #define VGA_CR_INDEX_CGA 0x3d4 427 #define VGA_CR_DATA_CGA 0x3d5 428 429 /* 430 * Instruction field definitions used by the command parser 431 */ 432 #define INSTR_CLIENT_SHIFT 29 433 #define INSTR_MI_CLIENT 0x0 434 #define INSTR_BC_CLIENT 0x2 435 #define INSTR_RC_CLIENT 0x3 436 #define INSTR_SUBCLIENT_SHIFT 27 437 #define INSTR_SUBCLIENT_MASK 0x18000000 438 #define INSTR_MEDIA_SUBCLIENT 0x2 439 #define INSTR_26_TO_24_MASK 0x7000000 440 #define INSTR_26_TO_24_SHIFT 24 441 442 /* 443 * Memory interface instructions used by the kernel 444 */ 445 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 446 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 447 #define MI_GLOBAL_GTT (1<<22) 448 449 #define MI_NOOP MI_INSTR(0, 0) 450 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 451 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 452 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 453 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 454 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 455 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 456 #define MI_FLUSH MI_INSTR(0x04, 0) 457 #define MI_READ_FLUSH (1 << 0) 458 #define MI_EXE_FLUSH (1 << 1) 459 #define MI_NO_WRITE_FLUSH (1 << 2) 460 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 461 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 462 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 463 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 464 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 465 #define MI_ARB_ENABLE (1<<0) 466 #define MI_ARB_DISABLE (0<<0) 467 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 468 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 469 #define MI_SUSPEND_FLUSH_EN (1<<0) 470 #define MI_SET_APPID MI_INSTR(0x0e, 0) 471 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 472 #define MI_OVERLAY_CONTINUE (0x0<<21) 473 #define MI_OVERLAY_ON (0x1<<21) 474 #define MI_OVERLAY_OFF (0x2<<21) 475 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 476 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 477 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 478 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 479 /* IVB has funny definitions for which plane to flip. */ 480 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 481 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 482 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 483 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 484 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 485 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 486 /* SKL ones */ 487 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 488 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 489 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 490 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 491 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 492 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 493 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 494 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 495 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 496 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 497 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 498 #define MI_SEMAPHORE_UPDATE (1<<21) 499 #define MI_SEMAPHORE_COMPARE (1<<20) 500 #define MI_SEMAPHORE_REGISTER (1<<18) 501 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 502 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 503 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 504 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 505 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 506 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 507 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 508 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 509 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 510 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 511 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 512 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 513 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 514 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 515 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 516 #define MI_MM_SPACE_GTT (1<<8) 517 #define MI_MM_SPACE_PHYSICAL (0<<8) 518 #define MI_SAVE_EXT_STATE_EN (1<<3) 519 #define MI_RESTORE_EXT_STATE_EN (1<<2) 520 #define MI_FORCE_RESTORE (1<<1) 521 #define MI_RESTORE_INHIBIT (1<<0) 522 #define HSW_MI_RS_SAVE_STATE_EN (1<<3) 523 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) 524 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 525 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 526 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 527 #define MI_SEMAPHORE_POLL (1<<15) 528 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 529 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 530 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) 531 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ 532 #define MI_USE_GGTT (1 << 22) /* g4x+ */ 533 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 534 #define MI_STORE_DWORD_INDEX_SHIFT 2 535 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 536 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 537 * simply ignores the register load under certain conditions. 538 * - One can actually load arbitrary many arbitrary registers: Simply issue x 539 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 540 */ 541 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 542 #define MI_LRI_FORCE_POSTED (1<<12) 543 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) 544 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) 545 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 546 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 547 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 548 #define MI_INVALIDATE_TLB (1<<18) 549 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 550 #define MI_FLUSH_DW_OP_MASK (3<<14) 551 #define MI_FLUSH_DW_NOTIFY (1<<8) 552 #define MI_INVALIDATE_BSD (1<<7) 553 #define MI_FLUSH_DW_USE_GTT (1<<2) 554 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 555 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) 556 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) 557 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 558 #define MI_BATCH_NON_SECURE (1) 559 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 560 #define MI_BATCH_NON_SECURE_I965 (1<<8) 561 #define MI_BATCH_PPGTT_HSW (1<<8) 562 #define MI_BATCH_NON_SECURE_HSW (1<<13) 563 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 564 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 565 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 566 #define MI_BATCH_RESOURCE_STREAMER (1<<10) 567 568 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 569 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 570 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 571 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 572 573 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 574 #define LOWER_SLICE_ENABLED (1<<0) 575 #define LOWER_SLICE_DISABLED (0<<0) 576 577 /* 578 * 3D instructions used by the kernel 579 */ 580 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 581 582 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) 583 #define GEN9_MEDIA_POOL_ENABLE (1 << 31) 584 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 585 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 586 #define SC_UPDATE_SCISSOR (0x1<<1) 587 #define SC_ENABLE_MASK (0x1<<0) 588 #define SC_ENABLE (0x1<<0) 589 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 590 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 591 #define SCI_YMIN_MASK (0xffff<<16) 592 #define SCI_XMIN_MASK (0xffff<<0) 593 #define SCI_YMAX_MASK (0xffff<<16) 594 #define SCI_XMAX_MASK (0xffff<<0) 595 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 596 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 597 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 598 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 599 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 600 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 601 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 602 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 603 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 604 605 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 606 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 607 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 608 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 609 #define BLT_WRITE_A (2<<20) 610 #define BLT_WRITE_RGB (1<<20) 611 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 612 #define BLT_DEPTH_8 (0<<24) 613 #define BLT_DEPTH_16_565 (1<<24) 614 #define BLT_DEPTH_16_1555 (2<<24) 615 #define BLT_DEPTH_32 (3<<24) 616 #define BLT_ROP_SRC_COPY (0xcc<<16) 617 #define BLT_ROP_COLOR_COPY (0xf0<<16) 618 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 619 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 620 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 621 #define ASYNC_FLIP (1<<22) 622 #define DISPLAY_PLANE_A (0<<20) 623 #define DISPLAY_PLANE_B (1<<20) 624 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) 625 #define PIPE_CONTROL_FLUSH_L3 (1<<27) 626 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 627 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 628 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 629 #define PIPE_CONTROL_CS_STALL (1<<20) 630 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 631 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 632 #define PIPE_CONTROL_QW_WRITE (1<<14) 633 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 634 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 635 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 636 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 637 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 638 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 639 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 640 #define PIPE_CONTROL_NOTIFY (1<<8) 641 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 642 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) 643 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 644 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 645 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 646 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 647 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 648 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 649 650 /* 651 * Commands used only by the command parser 652 */ 653 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 654 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 655 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 656 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 657 #define MI_PREDICATE MI_INSTR(0x0C, 0) 658 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 659 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 660 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 661 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 662 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 663 #define MI_CLFLUSH MI_INSTR(0x27, 0) 664 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 665 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 666 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 667 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 668 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 669 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 670 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 671 672 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 673 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 674 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 675 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 676 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 677 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 678 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 679 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 680 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 681 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 682 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 683 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 684 685 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 686 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 687 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 688 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 689 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 690 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 691 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 692 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 693 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 694 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 695 696 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 697 698 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 699 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 700 701 /* 702 * Registers used only by the command parser 703 */ 704 #define BCS_SWCTRL _MMIO(0x22200) 705 706 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 707 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 708 #define HS_INVOCATION_COUNT _MMIO(0x2300) 709 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 710 #define DS_INVOCATION_COUNT _MMIO(0x2308) 711 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 712 #define IA_VERTICES_COUNT _MMIO(0x2310) 713 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 714 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 715 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 716 #define VS_INVOCATION_COUNT _MMIO(0x2320) 717 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 718 #define GS_INVOCATION_COUNT _MMIO(0x2328) 719 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 720 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 721 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 722 #define CL_INVOCATION_COUNT _MMIO(0x2338) 723 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 724 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 725 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 726 #define PS_INVOCATION_COUNT _MMIO(0x2348) 727 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 728 #define PS_DEPTH_COUNT _MMIO(0x2350) 729 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 730 731 /* There are the 4 64-bit counter registers, one for each stream output */ 732 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 733 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 734 735 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 736 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 737 738 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 739 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 740 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 741 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 742 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 743 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 744 745 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 746 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 747 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 748 749 /* There are the 16 64-bit CS General Purpose Registers */ 750 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 751 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 752 753 #define GEN7_OACONTROL _MMIO(0x2360) 754 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 755 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 756 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 757 #define GEN7_OACONTROL_TIMER_ENABLE (1<<5) 758 #define GEN7_OACONTROL_FORMAT_A13 (0<<2) 759 #define GEN7_OACONTROL_FORMAT_A29 (1<<2) 760 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2) 761 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2) 762 #define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2) 763 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2) 764 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2) 765 #define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2) 766 #define GEN7_OACONTROL_FORMAT_SHIFT 2 767 #define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1) 768 #define GEN7_OACONTROL_ENABLE (1<<0) 769 770 #define GEN8_OACTXID _MMIO(0x2364) 771 772 #define GEN8_OA_DEBUG _MMIO(0x2B04) 773 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5) 774 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6) 775 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2) 776 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1) 777 778 #define GEN8_OACONTROL _MMIO(0x2B00) 779 #define GEN8_OA_REPORT_FORMAT_A12 (0<<2) 780 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2) 781 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2) 782 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2) 783 #define GEN8_OA_REPORT_FORMAT_SHIFT 2 784 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1) 785 #define GEN8_OA_COUNTER_ENABLE (1<<0) 786 787 #define GEN8_OACTXCONTROL _MMIO(0x2360) 788 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 789 #define GEN8_OA_TIMER_PERIOD_SHIFT 2 790 #define GEN8_OA_TIMER_ENABLE (1<<1) 791 #define GEN8_OA_COUNTER_RESUME (1<<0) 792 793 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 794 #define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3) 795 #define GEN7_OABUFFER_EDGE_TRIGGER (1<<2) 796 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1) 797 #define GEN7_OABUFFER_RESUME (1<<0) 798 799 #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 800 #define GEN8_OABUFFER _MMIO(0x2b14) 801 802 #define GEN7_OASTATUS1 _MMIO(0x2364) 803 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 804 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2) 805 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1) 806 #define GEN7_OASTATUS1_REPORT_LOST (1<<0) 807 808 #define GEN7_OASTATUS2 _MMIO(0x2368) 809 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 810 811 #define GEN8_OASTATUS _MMIO(0x2b08) 812 #define GEN8_OASTATUS_OVERRUN_STATUS (1<<3) 813 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2) 814 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1) 815 #define GEN8_OASTATUS_REPORT_LOST (1<<0) 816 817 #define GEN8_OAHEADPTR _MMIO(0x2B0C) 818 #define GEN8_OAHEADPTR_MASK 0xffffffc0 819 #define GEN8_OATAILPTR _MMIO(0x2B10) 820 #define GEN8_OATAILPTR_MASK 0xffffffc0 821 822 #define OABUFFER_SIZE_128K (0<<3) 823 #define OABUFFER_SIZE_256K (1<<3) 824 #define OABUFFER_SIZE_512K (2<<3) 825 #define OABUFFER_SIZE_1M (3<<3) 826 #define OABUFFER_SIZE_2M (4<<3) 827 #define OABUFFER_SIZE_4M (5<<3) 828 #define OABUFFER_SIZE_8M (6<<3) 829 #define OABUFFER_SIZE_16M (7<<3) 830 831 #define OA_MEM_SELECT_GGTT (1<<0) 832 833 /* 834 * Flexible, Aggregate EU Counter Registers. 835 * Note: these aren't contiguous 836 */ 837 #define EU_PERF_CNTL0 _MMIO(0xe458) 838 #define EU_PERF_CNTL1 _MMIO(0xe558) 839 #define EU_PERF_CNTL2 _MMIO(0xe658) 840 #define EU_PERF_CNTL3 _MMIO(0xe758) 841 #define EU_PERF_CNTL4 _MMIO(0xe45c) 842 #define EU_PERF_CNTL5 _MMIO(0xe55c) 843 #define EU_PERF_CNTL6 _MMIO(0xe65c) 844 845 /* 846 * OA Boolean state 847 */ 848 849 #define OASTARTTRIG1 _MMIO(0x2710) 850 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 851 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff 852 853 #define OASTARTTRIG2 _MMIO(0x2714) 854 #define OASTARTTRIG2_INVERT_A_0 (1<<0) 855 #define OASTARTTRIG2_INVERT_A_1 (1<<1) 856 #define OASTARTTRIG2_INVERT_A_2 (1<<2) 857 #define OASTARTTRIG2_INVERT_A_3 (1<<3) 858 #define OASTARTTRIG2_INVERT_A_4 (1<<4) 859 #define OASTARTTRIG2_INVERT_A_5 (1<<5) 860 #define OASTARTTRIG2_INVERT_A_6 (1<<6) 861 #define OASTARTTRIG2_INVERT_A_7 (1<<7) 862 #define OASTARTTRIG2_INVERT_A_8 (1<<8) 863 #define OASTARTTRIG2_INVERT_A_9 (1<<9) 864 #define OASTARTTRIG2_INVERT_A_10 (1<<10) 865 #define OASTARTTRIG2_INVERT_A_11 (1<<11) 866 #define OASTARTTRIG2_INVERT_A_12 (1<<12) 867 #define OASTARTTRIG2_INVERT_A_13 (1<<13) 868 #define OASTARTTRIG2_INVERT_A_14 (1<<14) 869 #define OASTARTTRIG2_INVERT_A_15 (1<<15) 870 #define OASTARTTRIG2_INVERT_B_0 (1<<16) 871 #define OASTARTTRIG2_INVERT_B_1 (1<<17) 872 #define OASTARTTRIG2_INVERT_B_2 (1<<18) 873 #define OASTARTTRIG2_INVERT_B_3 (1<<19) 874 #define OASTARTTRIG2_INVERT_C_0 (1<<20) 875 #define OASTARTTRIG2_INVERT_C_1 (1<<21) 876 #define OASTARTTRIG2_INVERT_D_0 (1<<22) 877 #define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23) 878 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24) 879 #define OASTARTTRIG2_EVENT_SELECT_0 (1<<28) 880 #define OASTARTTRIG2_EVENT_SELECT_1 (1<<29) 881 #define OASTARTTRIG2_EVENT_SELECT_2 (1<<30) 882 #define OASTARTTRIG2_EVENT_SELECT_3 (1<<31) 883 884 #define OASTARTTRIG3 _MMIO(0x2718) 885 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf 886 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 887 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 888 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 889 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 890 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 891 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 892 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 893 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 894 895 #define OASTARTTRIG4 _MMIO(0x271c) 896 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf 897 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 898 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 899 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 900 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 901 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 902 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 903 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 904 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 905 906 #define OASTARTTRIG5 _MMIO(0x2720) 907 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 908 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff 909 910 #define OASTARTTRIG6 _MMIO(0x2724) 911 #define OASTARTTRIG6_INVERT_A_0 (1<<0) 912 #define OASTARTTRIG6_INVERT_A_1 (1<<1) 913 #define OASTARTTRIG6_INVERT_A_2 (1<<2) 914 #define OASTARTTRIG6_INVERT_A_3 (1<<3) 915 #define OASTARTTRIG6_INVERT_A_4 (1<<4) 916 #define OASTARTTRIG6_INVERT_A_5 (1<<5) 917 #define OASTARTTRIG6_INVERT_A_6 (1<<6) 918 #define OASTARTTRIG6_INVERT_A_7 (1<<7) 919 #define OASTARTTRIG6_INVERT_A_8 (1<<8) 920 #define OASTARTTRIG6_INVERT_A_9 (1<<9) 921 #define OASTARTTRIG6_INVERT_A_10 (1<<10) 922 #define OASTARTTRIG6_INVERT_A_11 (1<<11) 923 #define OASTARTTRIG6_INVERT_A_12 (1<<12) 924 #define OASTARTTRIG6_INVERT_A_13 (1<<13) 925 #define OASTARTTRIG6_INVERT_A_14 (1<<14) 926 #define OASTARTTRIG6_INVERT_A_15 (1<<15) 927 #define OASTARTTRIG6_INVERT_B_0 (1<<16) 928 #define OASTARTTRIG6_INVERT_B_1 (1<<17) 929 #define OASTARTTRIG6_INVERT_B_2 (1<<18) 930 #define OASTARTTRIG6_INVERT_B_3 (1<<19) 931 #define OASTARTTRIG6_INVERT_C_0 (1<<20) 932 #define OASTARTTRIG6_INVERT_C_1 (1<<21) 933 #define OASTARTTRIG6_INVERT_D_0 (1<<22) 934 #define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23) 935 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24) 936 #define OASTARTTRIG6_EVENT_SELECT_4 (1<<28) 937 #define OASTARTTRIG6_EVENT_SELECT_5 (1<<29) 938 #define OASTARTTRIG6_EVENT_SELECT_6 (1<<30) 939 #define OASTARTTRIG6_EVENT_SELECT_7 (1<<31) 940 941 #define OASTARTTRIG7 _MMIO(0x2728) 942 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf 943 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 944 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 945 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 946 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 947 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 948 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 949 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 950 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 951 952 #define OASTARTTRIG8 _MMIO(0x272c) 953 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf 954 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 955 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 956 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 957 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 958 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 959 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 960 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 961 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 962 963 #define OAREPORTTRIG1 _MMIO(0x2740) 964 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff 965 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 966 967 #define OAREPORTTRIG2 _MMIO(0x2744) 968 #define OAREPORTTRIG2_INVERT_A_0 (1<<0) 969 #define OAREPORTTRIG2_INVERT_A_1 (1<<1) 970 #define OAREPORTTRIG2_INVERT_A_2 (1<<2) 971 #define OAREPORTTRIG2_INVERT_A_3 (1<<3) 972 #define OAREPORTTRIG2_INVERT_A_4 (1<<4) 973 #define OAREPORTTRIG2_INVERT_A_5 (1<<5) 974 #define OAREPORTTRIG2_INVERT_A_6 (1<<6) 975 #define OAREPORTTRIG2_INVERT_A_7 (1<<7) 976 #define OAREPORTTRIG2_INVERT_A_8 (1<<8) 977 #define OAREPORTTRIG2_INVERT_A_9 (1<<9) 978 #define OAREPORTTRIG2_INVERT_A_10 (1<<10) 979 #define OAREPORTTRIG2_INVERT_A_11 (1<<11) 980 #define OAREPORTTRIG2_INVERT_A_12 (1<<12) 981 #define OAREPORTTRIG2_INVERT_A_13 (1<<13) 982 #define OAREPORTTRIG2_INVERT_A_14 (1<<14) 983 #define OAREPORTTRIG2_INVERT_A_15 (1<<15) 984 #define OAREPORTTRIG2_INVERT_B_0 (1<<16) 985 #define OAREPORTTRIG2_INVERT_B_1 (1<<17) 986 #define OAREPORTTRIG2_INVERT_B_2 (1<<18) 987 #define OAREPORTTRIG2_INVERT_B_3 (1<<19) 988 #define OAREPORTTRIG2_INVERT_C_0 (1<<20) 989 #define OAREPORTTRIG2_INVERT_C_1 (1<<21) 990 #define OAREPORTTRIG2_INVERT_D_0 (1<<22) 991 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) 992 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) 993 994 #define OAREPORTTRIG3 _MMIO(0x2748) 995 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf 996 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 997 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 998 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 999 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 1000 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 1001 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 1002 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 1003 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 1004 1005 #define OAREPORTTRIG4 _MMIO(0x274c) 1006 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf 1007 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 1008 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 1009 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 1010 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 1011 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 1012 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 1013 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 1014 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 1015 1016 #define OAREPORTTRIG5 _MMIO(0x2750) 1017 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff 1018 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 1019 1020 #define OAREPORTTRIG6 _MMIO(0x2754) 1021 #define OAREPORTTRIG6_INVERT_A_0 (1<<0) 1022 #define OAREPORTTRIG6_INVERT_A_1 (1<<1) 1023 #define OAREPORTTRIG6_INVERT_A_2 (1<<2) 1024 #define OAREPORTTRIG6_INVERT_A_3 (1<<3) 1025 #define OAREPORTTRIG6_INVERT_A_4 (1<<4) 1026 #define OAREPORTTRIG6_INVERT_A_5 (1<<5) 1027 #define OAREPORTTRIG6_INVERT_A_6 (1<<6) 1028 #define OAREPORTTRIG6_INVERT_A_7 (1<<7) 1029 #define OAREPORTTRIG6_INVERT_A_8 (1<<8) 1030 #define OAREPORTTRIG6_INVERT_A_9 (1<<9) 1031 #define OAREPORTTRIG6_INVERT_A_10 (1<<10) 1032 #define OAREPORTTRIG6_INVERT_A_11 (1<<11) 1033 #define OAREPORTTRIG6_INVERT_A_12 (1<<12) 1034 #define OAREPORTTRIG6_INVERT_A_13 (1<<13) 1035 #define OAREPORTTRIG6_INVERT_A_14 (1<<14) 1036 #define OAREPORTTRIG6_INVERT_A_15 (1<<15) 1037 #define OAREPORTTRIG6_INVERT_B_0 (1<<16) 1038 #define OAREPORTTRIG6_INVERT_B_1 (1<<17) 1039 #define OAREPORTTRIG6_INVERT_B_2 (1<<18) 1040 #define OAREPORTTRIG6_INVERT_B_3 (1<<19) 1041 #define OAREPORTTRIG6_INVERT_C_0 (1<<20) 1042 #define OAREPORTTRIG6_INVERT_C_1 (1<<21) 1043 #define OAREPORTTRIG6_INVERT_D_0 (1<<22) 1044 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) 1045 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) 1046 1047 #define OAREPORTTRIG7 _MMIO(0x2758) 1048 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf 1049 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 1050 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 1051 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 1052 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 1053 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 1054 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 1055 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 1056 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 1057 1058 #define OAREPORTTRIG8 _MMIO(0x275c) 1059 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf 1060 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 1061 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 1062 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 1063 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 1064 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 1065 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 1066 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 1067 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 1068 1069 /* CECX_0 */ 1070 #define OACEC_COMPARE_LESS_OR_EQUAL 6 1071 #define OACEC_COMPARE_NOT_EQUAL 5 1072 #define OACEC_COMPARE_LESS_THAN 4 1073 #define OACEC_COMPARE_GREATER_OR_EQUAL 3 1074 #define OACEC_COMPARE_EQUAL 2 1075 #define OACEC_COMPARE_GREATER_THAN 1 1076 #define OACEC_COMPARE_ANY_EQUAL 0 1077 1078 #define OACEC_COMPARE_VALUE_MASK 0xffff 1079 #define OACEC_COMPARE_VALUE_SHIFT 3 1080 1081 #define OACEC_SELECT_NOA (0<<19) 1082 #define OACEC_SELECT_PREV (1<<19) 1083 #define OACEC_SELECT_BOOLEAN (2<<19) 1084 1085 /* CECX_1 */ 1086 #define OACEC_MASK_MASK 0xffff 1087 #define OACEC_CONSIDERATIONS_MASK 0xffff 1088 #define OACEC_CONSIDERATIONS_SHIFT 16 1089 1090 #define OACEC0_0 _MMIO(0x2770) 1091 #define OACEC0_1 _MMIO(0x2774) 1092 #define OACEC1_0 _MMIO(0x2778) 1093 #define OACEC1_1 _MMIO(0x277c) 1094 #define OACEC2_0 _MMIO(0x2780) 1095 #define OACEC2_1 _MMIO(0x2784) 1096 #define OACEC3_0 _MMIO(0x2788) 1097 #define OACEC3_1 _MMIO(0x278c) 1098 #define OACEC4_0 _MMIO(0x2790) 1099 #define OACEC4_1 _MMIO(0x2794) 1100 #define OACEC5_0 _MMIO(0x2798) 1101 #define OACEC5_1 _MMIO(0x279c) 1102 #define OACEC6_0 _MMIO(0x27a0) 1103 #define OACEC6_1 _MMIO(0x27a4) 1104 #define OACEC7_0 _MMIO(0x27a8) 1105 #define OACEC7_1 _MMIO(0x27ac) 1106 1107 /* OA perf counters */ 1108 #define OA_PERFCNT1_LO _MMIO(0x91B8) 1109 #define OA_PERFCNT1_HI _MMIO(0x91BC) 1110 #define OA_PERFCNT2_LO _MMIO(0x91C0) 1111 #define OA_PERFCNT2_HI _MMIO(0x91C4) 1112 1113 #define OA_PERFMATRIX_LO _MMIO(0x91C8) 1114 #define OA_PERFMATRIX_HI _MMIO(0x91CC) 1115 1116 /* RPM unit config (Gen8+) */ 1117 #define RPM_CONFIG0 _MMIO(0x0D00) 1118 #define RPM_CONFIG1 _MMIO(0x0D04) 1119 1120 /* RPC unit config (Gen8+) */ 1121 #define RPM_CONFIG _MMIO(0x0D08) 1122 1123 /* NOA (Gen8+) */ 1124 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) 1125 1126 #define MICRO_BP0_0 _MMIO(0x9800) 1127 #define MICRO_BP0_2 _MMIO(0x9804) 1128 #define MICRO_BP0_1 _MMIO(0x9808) 1129 1130 #define MICRO_BP1_0 _MMIO(0x980C) 1131 #define MICRO_BP1_2 _MMIO(0x9810) 1132 #define MICRO_BP1_1 _MMIO(0x9814) 1133 1134 #define MICRO_BP2_0 _MMIO(0x9818) 1135 #define MICRO_BP2_2 _MMIO(0x981C) 1136 #define MICRO_BP2_1 _MMIO(0x9820) 1137 1138 #define MICRO_BP3_0 _MMIO(0x9824) 1139 #define MICRO_BP3_2 _MMIO(0x9828) 1140 #define MICRO_BP3_1 _MMIO(0x982C) 1141 1142 #define MICRO_BP_TRIGGER _MMIO(0x9830) 1143 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 1144 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 1145 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) 1146 1147 #define GDT_CHICKEN_BITS _MMIO(0x9840) 1148 #define GT_NOA_ENABLE 0x00000080 1149 1150 #define NOA_DATA _MMIO(0x986C) 1151 #define NOA_WRITE _MMIO(0x9888) 1152 1153 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 1154 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 1155 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 1156 1157 /* 1158 * Reset registers 1159 */ 1160 #define DEBUG_RESET_I830 _MMIO(0x6070) 1161 #define DEBUG_RESET_FULL (1<<7) 1162 #define DEBUG_RESET_RENDER (1<<8) 1163 #define DEBUG_RESET_DISPLAY (1<<9) 1164 1165 /* 1166 * IOSF sideband 1167 */ 1168 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 1169 #define IOSF_DEVFN_SHIFT 24 1170 #define IOSF_OPCODE_SHIFT 16 1171 #define IOSF_PORT_SHIFT 8 1172 #define IOSF_BYTE_ENABLES_SHIFT 4 1173 #define IOSF_BAR_SHIFT 1 1174 #define IOSF_SB_BUSY (1<<0) 1175 #define IOSF_PORT_BUNIT 0x03 1176 #define IOSF_PORT_PUNIT 0x04 1177 #define IOSF_PORT_NC 0x11 1178 #define IOSF_PORT_DPIO 0x12 1179 #define IOSF_PORT_GPIO_NC 0x13 1180 #define IOSF_PORT_CCK 0x14 1181 #define IOSF_PORT_DPIO_2 0x1a 1182 #define IOSF_PORT_FLISDSI 0x1b 1183 #define IOSF_PORT_GPIO_SC 0x48 1184 #define IOSF_PORT_GPIO_SUS 0xa8 1185 #define IOSF_PORT_CCU 0xa9 1186 #define CHV_IOSF_PORT_GPIO_N 0x13 1187 #define CHV_IOSF_PORT_GPIO_SE 0x48 1188 #define CHV_IOSF_PORT_GPIO_E 0xa8 1189 #define CHV_IOSF_PORT_GPIO_SW 0xb2 1190 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 1191 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 1192 1193 /* See configdb bunit SB addr map */ 1194 #define BUNIT_REG_BISOC 0x11 1195 1196 #define PUNIT_REG_DSPFREQ 0x36 1197 #define DSPFREQSTAT_SHIFT_CHV 24 1198 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 1199 #define DSPFREQGUAR_SHIFT_CHV 8 1200 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 1201 #define DSPFREQSTAT_SHIFT 30 1202 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 1203 #define DSPFREQGUAR_SHIFT 14 1204 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 1205 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 1206 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 1207 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 1208 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 1209 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 1210 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 1211 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 1212 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 1213 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 1214 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 1215 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 1216 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 1217 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 1218 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 1219 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 1220 1221 /* 1222 * i915_power_well_id: 1223 * 1224 * Platform specific IDs used to look up power wells and - except for custom 1225 * power wells - to define request/status register flag bit positions. As such 1226 * the set of IDs on a given platform must be unique and except for custom 1227 * power wells their value must stay fixed. 1228 */ 1229 enum i915_power_well_id { 1230 /* 1231 * I830 1232 * - custom power well 1233 */ 1234 I830_DISP_PW_PIPES = 0, 1235 1236 /* 1237 * VLV/CHV 1238 * - PUNIT_REG_PWRGT_CTRL (bit: id*2), 1239 * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) 1240 */ 1241 PUNIT_POWER_WELL_RENDER = 0, 1242 PUNIT_POWER_WELL_MEDIA = 1, 1243 PUNIT_POWER_WELL_DISP2D = 3, 1244 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 1245 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 1246 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 1247 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 1248 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 1249 PUNIT_POWER_WELL_DPIO_RX0 = 10, 1250 PUNIT_POWER_WELL_DPIO_RX1 = 11, 1251 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 1252 /* - custom power well */ 1253 CHV_DISP_PW_PIPE_A, /* 13 */ 1254 1255 /* 1256 * HSW/BDW 1257 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) 1258 */ 1259 HSW_DISP_PW_GLOBAL = 15, 1260 1261 /* 1262 * GEN9+ 1263 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) 1264 */ 1265 SKL_DISP_PW_MISC_IO = 0, 1266 SKL_DISP_PW_DDI_A_E, 1267 GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, 1268 CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, 1269 SKL_DISP_PW_DDI_B, 1270 SKL_DISP_PW_DDI_C, 1271 SKL_DISP_PW_DDI_D, 1272 1273 GLK_DISP_PW_AUX_A = 8, 1274 GLK_DISP_PW_AUX_B, 1275 GLK_DISP_PW_AUX_C, 1276 CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A, 1277 CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B, 1278 CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C, 1279 CNL_DISP_PW_AUX_D, 1280 1281 SKL_DISP_PW_1 = 14, 1282 SKL_DISP_PW_2, 1283 1284 /* - custom power wells */ 1285 SKL_DISP_PW_DC_OFF, 1286 BXT_DPIO_CMN_A, 1287 BXT_DPIO_CMN_BC, 1288 GLK_DPIO_CMN_C, /* 19 */ 1289 1290 /* 1291 * Multiple platforms. 1292 * Must start following the highest ID of any platform. 1293 * - custom power wells 1294 */ 1295 I915_DISP_PW_ALWAYS_ON = 20, 1296 }; 1297 1298 #define PUNIT_REG_PWRGT_CTRL 0x60 1299 #define PUNIT_REG_PWRGT_STATUS 0x61 1300 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 1301 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 1302 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 1303 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 1304 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 1305 1306 #define PUNIT_REG_GPU_LFM 0xd3 1307 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 1308 #define PUNIT_REG_GPU_FREQ_STS 0xd8 1309 #define GPLLENABLE (1<<4) 1310 #define GENFREQSTATUS (1<<0) 1311 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 1312 #define PUNIT_REG_CZ_TIMESTAMP 0xce 1313 1314 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 1315 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 1316 1317 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 1318 #define FB_GFX_FREQ_FUSE_MASK 0xff 1319 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 1320 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 1321 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 1322 1323 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 1324 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 1325 1326 #define PUNIT_REG_DDR_SETUP2 0x139 1327 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 1328 #define FORCE_DDR_LOW_FREQ (1 << 1) 1329 #define FORCE_DDR_HIGH_FREQ (1 << 0) 1330 1331 #define PUNIT_GPU_STATUS_REG 0xdb 1332 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 1333 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 1334 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 1335 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 1336 1337 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 1338 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 1339 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 1340 1341 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 1342 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 1343 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 1344 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 1345 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 1346 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 1347 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 1348 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 1349 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 1350 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 1351 1352 #define VLV_TURBO_SOC_OVERRIDE 0x04 1353 #define VLV_OVERRIDE_EN 1 1354 #define VLV_SOC_TDP_EN (1 << 1) 1355 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 1356 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 1357 1358 /* vlv2 north clock has */ 1359 #define CCK_FUSE_REG 0x8 1360 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 1361 #define CCK_REG_DSI_PLL_FUSE 0x44 1362 #define CCK_REG_DSI_PLL_CONTROL 0x48 1363 #define DSI_PLL_VCO_EN (1 << 31) 1364 #define DSI_PLL_LDO_GATE (1 << 30) 1365 #define DSI_PLL_P1_POST_DIV_SHIFT 17 1366 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 1367 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 1368 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 1369 #define DSI_PLL_MUX_MASK (3 << 9) 1370 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 1371 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 1372 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 1373 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 1374 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 1375 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 1376 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 1377 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 1378 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 1379 #define DSI_PLL_LOCK (1 << 0) 1380 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 1381 #define DSI_PLL_LFSR (1 << 31) 1382 #define DSI_PLL_FRACTION_EN (1 << 30) 1383 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 1384 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 1385 #define DSI_PLL_USYNC_CNT_SHIFT 18 1386 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 1387 #define DSI_PLL_N1_DIV_SHIFT 16 1388 #define DSI_PLL_N1_DIV_MASK (3 << 16) 1389 #define DSI_PLL_M1_DIV_SHIFT 0 1390 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 1391 #define CCK_CZ_CLOCK_CONTROL 0x62 1392 #define CCK_GPLL_CLOCK_CONTROL 0x67 1393 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 1394 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 1395 #define CCK_TRUNK_FORCE_ON (1 << 17) 1396 #define CCK_TRUNK_FORCE_OFF (1 << 16) 1397 #define CCK_FREQUENCY_STATUS (0x1f << 8) 1398 #define CCK_FREQUENCY_STATUS_SHIFT 8 1399 #define CCK_FREQUENCY_VALUES (0x1f << 0) 1400 1401 /* DPIO registers */ 1402 #define DPIO_DEVFN 0 1403 1404 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 1405 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 1406 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 1407 #define DPIO_SFR_BYPASS (1<<1) 1408 #define DPIO_CMNRST (1<<0) 1409 1410 #define DPIO_PHY(pipe) ((pipe) >> 1) 1411 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 1412 1413 /* 1414 * Per pipe/PLL DPIO regs 1415 */ 1416 #define _VLV_PLL_DW3_CH0 0x800c 1417 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 1418 #define DPIO_POST_DIV_DAC 0 1419 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 1420 #define DPIO_POST_DIV_LVDS1 2 1421 #define DPIO_POST_DIV_LVDS2 3 1422 #define DPIO_K_SHIFT (24) /* 4 bits */ 1423 #define DPIO_P1_SHIFT (21) /* 3 bits */ 1424 #define DPIO_P2_SHIFT (16) /* 5 bits */ 1425 #define DPIO_N_SHIFT (12) /* 4 bits */ 1426 #define DPIO_ENABLE_CALIBRATION (1<<11) 1427 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 1428 #define DPIO_M2DIV_MASK 0xff 1429 #define _VLV_PLL_DW3_CH1 0x802c 1430 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 1431 1432 #define _VLV_PLL_DW5_CH0 0x8014 1433 #define DPIO_REFSEL_OVERRIDE 27 1434 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 1435 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 1436 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 1437 #define DPIO_PLL_REFCLK_SEL_MASK 3 1438 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 1439 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 1440 #define _VLV_PLL_DW5_CH1 0x8034 1441 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 1442 1443 #define _VLV_PLL_DW7_CH0 0x801c 1444 #define _VLV_PLL_DW7_CH1 0x803c 1445 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 1446 1447 #define _VLV_PLL_DW8_CH0 0x8040 1448 #define _VLV_PLL_DW8_CH1 0x8060 1449 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 1450 1451 #define VLV_PLL_DW9_BCAST 0xc044 1452 #define _VLV_PLL_DW9_CH0 0x8044 1453 #define _VLV_PLL_DW9_CH1 0x8064 1454 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 1455 1456 #define _VLV_PLL_DW10_CH0 0x8048 1457 #define _VLV_PLL_DW10_CH1 0x8068 1458 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 1459 1460 #define _VLV_PLL_DW11_CH0 0x804c 1461 #define _VLV_PLL_DW11_CH1 0x806c 1462 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 1463 1464 /* Spec for ref block start counts at DW10 */ 1465 #define VLV_REF_DW13 0x80ac 1466 1467 #define VLV_CMN_DW0 0x8100 1468 1469 /* 1470 * Per DDI channel DPIO regs 1471 */ 1472 1473 #define _VLV_PCS_DW0_CH0 0x8200 1474 #define _VLV_PCS_DW0_CH1 0x8400 1475 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 1476 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 1477 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) 1478 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) 1479 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1480 1481 #define _VLV_PCS01_DW0_CH0 0x200 1482 #define _VLV_PCS23_DW0_CH0 0x400 1483 #define _VLV_PCS01_DW0_CH1 0x2600 1484 #define _VLV_PCS23_DW0_CH1 0x2800 1485 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1486 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1487 1488 #define _VLV_PCS_DW1_CH0 0x8204 1489 #define _VLV_PCS_DW1_CH1 0x8404 1490 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 1491 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 1492 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 1493 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1494 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 1495 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1496 1497 #define _VLV_PCS01_DW1_CH0 0x204 1498 #define _VLV_PCS23_DW1_CH0 0x404 1499 #define _VLV_PCS01_DW1_CH1 0x2604 1500 #define _VLV_PCS23_DW1_CH1 0x2804 1501 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1502 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1503 1504 #define _VLV_PCS_DW8_CH0 0x8220 1505 #define _VLV_PCS_DW8_CH1 0x8420 1506 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1507 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1508 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1509 1510 #define _VLV_PCS01_DW8_CH0 0x0220 1511 #define _VLV_PCS23_DW8_CH0 0x0420 1512 #define _VLV_PCS01_DW8_CH1 0x2620 1513 #define _VLV_PCS23_DW8_CH1 0x2820 1514 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1515 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1516 1517 #define _VLV_PCS_DW9_CH0 0x8224 1518 #define _VLV_PCS_DW9_CH1 0x8424 1519 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) 1520 #define DPIO_PCS_TX2MARGIN_000 (0<<13) 1521 #define DPIO_PCS_TX2MARGIN_101 (1<<13) 1522 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) 1523 #define DPIO_PCS_TX1MARGIN_000 (0<<10) 1524 #define DPIO_PCS_TX1MARGIN_101 (1<<10) 1525 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1526 1527 #define _VLV_PCS01_DW9_CH0 0x224 1528 #define _VLV_PCS23_DW9_CH0 0x424 1529 #define _VLV_PCS01_DW9_CH1 0x2624 1530 #define _VLV_PCS23_DW9_CH1 0x2824 1531 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1532 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1533 1534 #define _CHV_PCS_DW10_CH0 0x8228 1535 #define _CHV_PCS_DW10_CH1 0x8428 1536 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 1537 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 1538 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) 1539 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) 1540 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) 1541 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) 1542 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) 1543 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) 1544 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1545 1546 #define _VLV_PCS01_DW10_CH0 0x0228 1547 #define _VLV_PCS23_DW10_CH0 0x0428 1548 #define _VLV_PCS01_DW10_CH1 0x2628 1549 #define _VLV_PCS23_DW10_CH1 0x2828 1550 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1551 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1552 1553 #define _VLV_PCS_DW11_CH0 0x822c 1554 #define _VLV_PCS_DW11_CH1 0x842c 1555 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) 1556 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) 1557 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) 1558 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) 1559 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1560 1561 #define _VLV_PCS01_DW11_CH0 0x022c 1562 #define _VLV_PCS23_DW11_CH0 0x042c 1563 #define _VLV_PCS01_DW11_CH1 0x262c 1564 #define _VLV_PCS23_DW11_CH1 0x282c 1565 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1566 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1567 1568 #define _VLV_PCS01_DW12_CH0 0x0230 1569 #define _VLV_PCS23_DW12_CH0 0x0430 1570 #define _VLV_PCS01_DW12_CH1 0x2630 1571 #define _VLV_PCS23_DW12_CH1 0x2830 1572 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1573 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1574 1575 #define _VLV_PCS_DW12_CH0 0x8230 1576 #define _VLV_PCS_DW12_CH1 0x8430 1577 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) 1578 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) 1579 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) 1580 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) 1581 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) 1582 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1583 1584 #define _VLV_PCS_DW14_CH0 0x8238 1585 #define _VLV_PCS_DW14_CH1 0x8438 1586 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1587 1588 #define _VLV_PCS_DW23_CH0 0x825c 1589 #define _VLV_PCS_DW23_CH1 0x845c 1590 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1591 1592 #define _VLV_TX_DW2_CH0 0x8288 1593 #define _VLV_TX_DW2_CH1 0x8488 1594 #define DPIO_SWING_MARGIN000_SHIFT 16 1595 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1596 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1597 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1598 1599 #define _VLV_TX_DW3_CH0 0x828c 1600 #define _VLV_TX_DW3_CH1 0x848c 1601 /* The following bit for CHV phy */ 1602 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 1603 #define DPIO_SWING_MARGIN101_SHIFT 16 1604 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1605 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1606 1607 #define _VLV_TX_DW4_CH0 0x8290 1608 #define _VLV_TX_DW4_CH1 0x8490 1609 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1610 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1611 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1612 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1613 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1614 1615 #define _VLV_TX3_DW4_CH0 0x690 1616 #define _VLV_TX3_DW4_CH1 0x2a90 1617 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1618 1619 #define _VLV_TX_DW5_CH0 0x8294 1620 #define _VLV_TX_DW5_CH1 0x8494 1621 #define DPIO_TX_OCALINIT_EN (1<<31) 1622 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1623 1624 #define _VLV_TX_DW11_CH0 0x82ac 1625 #define _VLV_TX_DW11_CH1 0x84ac 1626 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1627 1628 #define _VLV_TX_DW14_CH0 0x82b8 1629 #define _VLV_TX_DW14_CH1 0x84b8 1630 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1631 1632 /* CHV dpPhy registers */ 1633 #define _CHV_PLL_DW0_CH0 0x8000 1634 #define _CHV_PLL_DW0_CH1 0x8180 1635 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1636 1637 #define _CHV_PLL_DW1_CH0 0x8004 1638 #define _CHV_PLL_DW1_CH1 0x8184 1639 #define DPIO_CHV_N_DIV_SHIFT 8 1640 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1641 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1642 1643 #define _CHV_PLL_DW2_CH0 0x8008 1644 #define _CHV_PLL_DW2_CH1 0x8188 1645 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1646 1647 #define _CHV_PLL_DW3_CH0 0x800c 1648 #define _CHV_PLL_DW3_CH1 0x818c 1649 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1650 #define DPIO_CHV_FIRST_MOD (0 << 8) 1651 #define DPIO_CHV_SECOND_MOD (1 << 8) 1652 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1653 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1654 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1655 1656 #define _CHV_PLL_DW6_CH0 0x8018 1657 #define _CHV_PLL_DW6_CH1 0x8198 1658 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1659 #define DPIO_CHV_INT_COEFF_SHIFT 8 1660 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1661 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1662 1663 #define _CHV_PLL_DW8_CH0 0x8020 1664 #define _CHV_PLL_DW8_CH1 0x81A0 1665 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1666 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1667 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1668 1669 #define _CHV_PLL_DW9_CH0 0x8024 1670 #define _CHV_PLL_DW9_CH1 0x81A4 1671 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1672 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1673 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1674 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1675 1676 #define _CHV_CMN_DW0_CH0 0x8100 1677 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1678 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1679 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1680 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1681 1682 #define _CHV_CMN_DW5_CH0 0x8114 1683 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1684 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1685 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1686 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1687 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1688 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1689 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1690 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1691 1692 #define _CHV_CMN_DW13_CH0 0x8134 1693 #define _CHV_CMN_DW0_CH1 0x8080 1694 #define DPIO_CHV_S1_DIV_SHIFT 21 1695 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1696 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1697 #define DPIO_CHV_K_DIV_SHIFT 4 1698 #define DPIO_PLL_FREQLOCK (1 << 1) 1699 #define DPIO_PLL_LOCK (1 << 0) 1700 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1701 1702 #define _CHV_CMN_DW14_CH0 0x8138 1703 #define _CHV_CMN_DW1_CH1 0x8084 1704 #define DPIO_AFC_RECAL (1 << 14) 1705 #define DPIO_DCLKP_EN (1 << 13) 1706 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1707 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1708 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1709 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1710 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1711 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1712 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1713 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1714 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1715 1716 #define _CHV_CMN_DW19_CH0 0x814c 1717 #define _CHV_CMN_DW6_CH1 0x8098 1718 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1719 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1720 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1721 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1722 1723 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1724 1725 #define CHV_CMN_DW28 0x8170 1726 #define DPIO_CL1POWERDOWNEN (1 << 23) 1727 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1728 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1729 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1730 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1731 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1732 1733 #define CHV_CMN_DW30 0x8178 1734 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1735 #define DPIO_LRC_BYPASS (1 << 3) 1736 1737 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1738 (lane) * 0x200 + (offset)) 1739 1740 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1741 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1742 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1743 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1744 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1745 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1746 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1747 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1748 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1749 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1750 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1751 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1752 #define DPIO_FRC_LATENCY_SHFIT 8 1753 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1754 #define DPIO_UPAR_SHIFT 30 1755 1756 /* BXT PHY registers */ 1757 #define _BXT_PHY0_BASE 0x6C000 1758 #define _BXT_PHY1_BASE 0x162000 1759 #define _BXT_PHY2_BASE 0x163000 1760 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 1761 _BXT_PHY1_BASE, \ 1762 _BXT_PHY2_BASE) 1763 1764 #define _BXT_PHY(phy, reg) \ 1765 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 1766 1767 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1768 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 1769 (reg_ch1) - _BXT_PHY0_BASE)) 1770 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1771 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 1772 1773 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1774 #define MIPIO_RST_CTRL (1 << 2) 1775 1776 #define _BXT_PHY_CTL_DDI_A 0x64C00 1777 #define _BXT_PHY_CTL_DDI_B 0x64C10 1778 #define _BXT_PHY_CTL_DDI_C 0x64C20 1779 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1780 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1781 #define BXT_PHY_LANE_ENABLED (1 << 8) 1782 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1783 _BXT_PHY_CTL_DDI_B) 1784 1785 #define _PHY_CTL_FAMILY_EDP 0x64C80 1786 #define _PHY_CTL_FAMILY_DDI 0x64C90 1787 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 1788 #define COMMON_RESET_DIS (1 << 31) 1789 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 1790 _PHY_CTL_FAMILY_EDP, \ 1791 _PHY_CTL_FAMILY_DDI_C) 1792 1793 /* BXT PHY PLL registers */ 1794 #define _PORT_PLL_A 0x46074 1795 #define _PORT_PLL_B 0x46078 1796 #define _PORT_PLL_C 0x4607c 1797 #define PORT_PLL_ENABLE (1 << 31) 1798 #define PORT_PLL_LOCK (1 << 30) 1799 #define PORT_PLL_REF_SEL (1 << 27) 1800 #define PORT_PLL_POWER_ENABLE (1 << 26) 1801 #define PORT_PLL_POWER_STATE (1 << 25) 1802 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1803 1804 #define _PORT_PLL_EBB_0_A 0x162034 1805 #define _PORT_PLL_EBB_0_B 0x6C034 1806 #define _PORT_PLL_EBB_0_C 0x6C340 1807 #define PORT_PLL_P1_SHIFT 13 1808 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1809 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1810 #define PORT_PLL_P2_SHIFT 8 1811 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1812 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1813 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1814 _PORT_PLL_EBB_0_B, \ 1815 _PORT_PLL_EBB_0_C) 1816 1817 #define _PORT_PLL_EBB_4_A 0x162038 1818 #define _PORT_PLL_EBB_4_B 0x6C038 1819 #define _PORT_PLL_EBB_4_C 0x6C344 1820 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1821 #define PORT_PLL_RECALIBRATE (1 << 14) 1822 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1823 _PORT_PLL_EBB_4_B, \ 1824 _PORT_PLL_EBB_4_C) 1825 1826 #define _PORT_PLL_0_A 0x162100 1827 #define _PORT_PLL_0_B 0x6C100 1828 #define _PORT_PLL_0_C 0x6C380 1829 /* PORT_PLL_0_A */ 1830 #define PORT_PLL_M2_MASK 0xFF 1831 /* PORT_PLL_1_A */ 1832 #define PORT_PLL_N_SHIFT 8 1833 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1834 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1835 /* PORT_PLL_2_A */ 1836 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1837 /* PORT_PLL_3_A */ 1838 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1839 /* PORT_PLL_6_A */ 1840 #define PORT_PLL_PROP_COEFF_MASK 0xF 1841 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1842 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1843 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1844 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1845 /* PORT_PLL_8_A */ 1846 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1847 /* PORT_PLL_9_A */ 1848 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1849 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1850 /* PORT_PLL_10_A */ 1851 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) 1852 #define PORT_PLL_DCO_AMP_DEFAULT 15 1853 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1854 #define PORT_PLL_DCO_AMP(x) ((x)<<10) 1855 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 1856 _PORT_PLL_0_B, \ 1857 _PORT_PLL_0_C) 1858 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 1859 (idx) * 4) 1860 1861 /* BXT PHY common lane registers */ 1862 #define _PORT_CL1CM_DW0_A 0x162000 1863 #define _PORT_CL1CM_DW0_BC 0x6C000 1864 #define PHY_POWER_GOOD (1 << 16) 1865 #define PHY_RESERVED (1 << 7) 1866 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1867 1868 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1869 #define CL_POWER_DOWN_ENABLE (1 << 4) 1870 #define SUS_CLOCK_CONFIG (3 << 0) 1871 1872 #define _PORT_CL1CM_DW9_A 0x162024 1873 #define _PORT_CL1CM_DW9_BC 0x6C024 1874 #define IREF0RC_OFFSET_SHIFT 8 1875 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1876 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 1877 1878 #define _PORT_CL1CM_DW10_A 0x162028 1879 #define _PORT_CL1CM_DW10_BC 0x6C028 1880 #define IREF1RC_OFFSET_SHIFT 8 1881 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1882 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1883 1884 #define _PORT_CL1CM_DW28_A 0x162070 1885 #define _PORT_CL1CM_DW28_BC 0x6C070 1886 #define OCL1_POWER_DOWN_EN (1 << 23) 1887 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1888 #define SUS_CLK_CONFIG 0x3 1889 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 1890 1891 #define _PORT_CL1CM_DW30_A 0x162078 1892 #define _PORT_CL1CM_DW30_BC 0x6C078 1893 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1894 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1895 1896 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1897 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1898 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1899 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 1900 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 1901 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 1902 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604 1903 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 1904 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 1905 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 1906 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \ 1907 _CNL_PORT_PCS_DW1_GRP_AE, \ 1908 _CNL_PORT_PCS_DW1_GRP_B, \ 1909 _CNL_PORT_PCS_DW1_GRP_C, \ 1910 _CNL_PORT_PCS_DW1_GRP_D, \ 1911 _CNL_PORT_PCS_DW1_GRP_AE, \ 1912 _CNL_PORT_PCS_DW1_GRP_F) 1913 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \ 1914 _CNL_PORT_PCS_DW1_LN0_AE, \ 1915 _CNL_PORT_PCS_DW1_LN0_B, \ 1916 _CNL_PORT_PCS_DW1_LN0_C, \ 1917 _CNL_PORT_PCS_DW1_LN0_D, \ 1918 _CNL_PORT_PCS_DW1_LN0_AE, \ 1919 _CNL_PORT_PCS_DW1_LN0_F) 1920 #define COMMON_KEEPER_EN (1 << 26) 1921 1922 #define _CNL_PORT_TX_DW2_GRP_AE 0x162348 1923 #define _CNL_PORT_TX_DW2_GRP_B 0x1623C8 1924 #define _CNL_PORT_TX_DW2_GRP_C 0x162B48 1925 #define _CNL_PORT_TX_DW2_GRP_D 0x162BC8 1926 #define _CNL_PORT_TX_DW2_GRP_F 0x162A48 1927 #define _CNL_PORT_TX_DW2_LN0_AE 0x162448 1928 #define _CNL_PORT_TX_DW2_LN0_B 0x162648 1929 #define _CNL_PORT_TX_DW2_LN0_C 0x162C48 1930 #define _CNL_PORT_TX_DW2_LN0_D 0x162E48 1931 #define _CNL_PORT_TX_DW2_LN0_F 0x162A48 1932 #define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \ 1933 _CNL_PORT_TX_DW2_GRP_AE, \ 1934 _CNL_PORT_TX_DW2_GRP_B, \ 1935 _CNL_PORT_TX_DW2_GRP_C, \ 1936 _CNL_PORT_TX_DW2_GRP_D, \ 1937 _CNL_PORT_TX_DW2_GRP_AE, \ 1938 _CNL_PORT_TX_DW2_GRP_F) 1939 #define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \ 1940 _CNL_PORT_TX_DW2_LN0_AE, \ 1941 _CNL_PORT_TX_DW2_LN0_B, \ 1942 _CNL_PORT_TX_DW2_LN0_C, \ 1943 _CNL_PORT_TX_DW2_LN0_D, \ 1944 _CNL_PORT_TX_DW2_LN0_AE, \ 1945 _CNL_PORT_TX_DW2_LN0_F) 1946 #define SWING_SEL_UPPER(x) ((x >> 3) << 15) 1947 #define SWING_SEL_UPPER_MASK (1 << 15) 1948 #define SWING_SEL_LOWER(x) ((x & 0x7) << 11) 1949 #define SWING_SEL_LOWER_MASK (0x7 << 11) 1950 #define RCOMP_SCALAR(x) ((x) << 0) 1951 #define RCOMP_SCALAR_MASK (0xFF << 0) 1952 1953 #define _CNL_PORT_TX_DW4_GRP_AE 0x162350 1954 #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0 1955 #define _CNL_PORT_TX_DW4_GRP_C 0x162B50 1956 #define _CNL_PORT_TX_DW4_GRP_D 0x162BD0 1957 #define _CNL_PORT_TX_DW4_GRP_F 0x162A50 1958 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 1959 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 1960 #define _CNL_PORT_TX_DW4_LN0_B 0x162650 1961 #define _CNL_PORT_TX_DW4_LN0_C 0x162C50 1962 #define _CNL_PORT_TX_DW4_LN0_D 0x162E50 1963 #define _CNL_PORT_TX_DW4_LN0_F 0x162850 1964 #define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \ 1965 _CNL_PORT_TX_DW4_GRP_AE, \ 1966 _CNL_PORT_TX_DW4_GRP_B, \ 1967 _CNL_PORT_TX_DW4_GRP_C, \ 1968 _CNL_PORT_TX_DW4_GRP_D, \ 1969 _CNL_PORT_TX_DW4_GRP_AE, \ 1970 _CNL_PORT_TX_DW4_GRP_F) 1971 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \ 1972 _CNL_PORT_TX_DW4_LN0_AE, \ 1973 _CNL_PORT_TX_DW4_LN1_AE, \ 1974 _CNL_PORT_TX_DW4_LN0_B, \ 1975 _CNL_PORT_TX_DW4_LN0_C, \ 1976 _CNL_PORT_TX_DW4_LN0_D, \ 1977 _CNL_PORT_TX_DW4_LN0_AE, \ 1978 _CNL_PORT_TX_DW4_LN0_F) 1979 #define LOADGEN_SELECT (1 << 31) 1980 #define POST_CURSOR_1(x) ((x) << 12) 1981 #define POST_CURSOR_1_MASK (0x3F << 12) 1982 #define POST_CURSOR_2(x) ((x) << 6) 1983 #define POST_CURSOR_2_MASK (0x3F << 6) 1984 #define CURSOR_COEFF(x) ((x) << 0) 1985 #define CURSOR_COEFF_MASK (0x3F << 0) 1986 1987 #define _CNL_PORT_TX_DW5_GRP_AE 0x162354 1988 #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4 1989 #define _CNL_PORT_TX_DW5_GRP_C 0x162B54 1990 #define _CNL_PORT_TX_DW5_GRP_D 0x162BD4 1991 #define _CNL_PORT_TX_DW5_GRP_F 0x162A54 1992 #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 1993 #define _CNL_PORT_TX_DW5_LN0_B 0x162654 1994 #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 1995 #define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 1996 #define _CNL_PORT_TX_DW5_LN0_F 0x162854 1997 #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ 1998 _CNL_PORT_TX_DW5_GRP_AE, \ 1999 _CNL_PORT_TX_DW5_GRP_B, \ 2000 _CNL_PORT_TX_DW5_GRP_C, \ 2001 _CNL_PORT_TX_DW5_GRP_D, \ 2002 _CNL_PORT_TX_DW5_GRP_AE, \ 2003 _CNL_PORT_TX_DW5_GRP_F) 2004 #define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \ 2005 _CNL_PORT_TX_DW5_LN0_AE, \ 2006 _CNL_PORT_TX_DW5_LN0_B, \ 2007 _CNL_PORT_TX_DW5_LN0_C, \ 2008 _CNL_PORT_TX_DW5_LN0_D, \ 2009 _CNL_PORT_TX_DW5_LN0_AE, \ 2010 _CNL_PORT_TX_DW5_LN0_F) 2011 #define TX_TRAINING_EN (1 << 31) 2012 #define TAP3_DISABLE (1 << 29) 2013 #define SCALING_MODE_SEL(x) ((x) << 18) 2014 #define SCALING_MODE_SEL_MASK (0x7 << 18) 2015 #define RTERM_SELECT(x) ((x) << 3) 2016 #define RTERM_SELECT_MASK (0x7 << 3) 2017 2018 #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C 2019 #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC 2020 #define _CNL_PORT_TX_DW7_GRP_C 0x162B5C 2021 #define _CNL_PORT_TX_DW7_GRP_D 0x162BDC 2022 #define _CNL_PORT_TX_DW7_GRP_F 0x162A5C 2023 #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C 2024 #define _CNL_PORT_TX_DW7_LN0_B 0x16265C 2025 #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C 2026 #define _CNL_PORT_TX_DW7_LN0_D 0x162EDC 2027 #define _CNL_PORT_TX_DW7_LN0_F 0x16285C 2028 #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ 2029 _CNL_PORT_TX_DW7_GRP_AE, \ 2030 _CNL_PORT_TX_DW7_GRP_B, \ 2031 _CNL_PORT_TX_DW7_GRP_C, \ 2032 _CNL_PORT_TX_DW7_GRP_D, \ 2033 _CNL_PORT_TX_DW7_GRP_AE, \ 2034 _CNL_PORT_TX_DW7_GRP_F) 2035 #define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \ 2036 _CNL_PORT_TX_DW7_LN0_AE, \ 2037 _CNL_PORT_TX_DW7_LN0_B, \ 2038 _CNL_PORT_TX_DW7_LN0_C, \ 2039 _CNL_PORT_TX_DW7_LN0_D, \ 2040 _CNL_PORT_TX_DW7_LN0_AE, \ 2041 _CNL_PORT_TX_DW7_LN0_F) 2042 #define N_SCALAR(x) ((x) << 24) 2043 #define N_SCALAR_MASK (0x7F << 24) 2044 2045 /* The spec defines this only for BXT PHY0, but lets assume that this 2046 * would exist for PHY1 too if it had a second channel. 2047 */ 2048 #define _PORT_CL2CM_DW6_A 0x162358 2049 #define _PORT_CL2CM_DW6_BC 0x6C358 2050 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 2051 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 2052 2053 #define CNL_PORT_COMP_DW0 _MMIO(0x162100) 2054 #define COMP_INIT (1 << 31) 2055 #define CNL_PORT_COMP_DW1 _MMIO(0x162104) 2056 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 2057 #define PROCESS_INFO_DOT_0 (0 << 26) 2058 #define PROCESS_INFO_DOT_1 (1 << 26) 2059 #define PROCESS_INFO_DOT_4 (2 << 26) 2060 #define PROCESS_INFO_MASK (7 << 26) 2061 #define PROCESS_INFO_SHIFT 26 2062 #define VOLTAGE_INFO_0_85V (0 << 24) 2063 #define VOLTAGE_INFO_0_95V (1 << 24) 2064 #define VOLTAGE_INFO_1_05V (2 << 24) 2065 #define VOLTAGE_INFO_MASK (3 << 24) 2066 #define VOLTAGE_INFO_SHIFT 24 2067 #define CNL_PORT_COMP_DW9 _MMIO(0x162124) 2068 #define CNL_PORT_COMP_DW10 _MMIO(0x162128) 2069 2070 /* BXT PHY Ref registers */ 2071 #define _PORT_REF_DW3_A 0x16218C 2072 #define _PORT_REF_DW3_BC 0x6C18C 2073 #define GRC_DONE (1 << 22) 2074 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 2075 2076 #define _PORT_REF_DW6_A 0x162198 2077 #define _PORT_REF_DW6_BC 0x6C198 2078 #define GRC_CODE_SHIFT 24 2079 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 2080 #define GRC_CODE_FAST_SHIFT 16 2081 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 2082 #define GRC_CODE_SLOW_SHIFT 8 2083 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 2084 #define GRC_CODE_NOM_MASK 0xFF 2085 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 2086 2087 #define _PORT_REF_DW8_A 0x1621A0 2088 #define _PORT_REF_DW8_BC 0x6C1A0 2089 #define GRC_DIS (1 << 15) 2090 #define GRC_RDY_OVRD (1 << 1) 2091 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 2092 2093 /* BXT PHY PCS registers */ 2094 #define _PORT_PCS_DW10_LN01_A 0x162428 2095 #define _PORT_PCS_DW10_LN01_B 0x6C428 2096 #define _PORT_PCS_DW10_LN01_C 0x6C828 2097 #define _PORT_PCS_DW10_GRP_A 0x162C28 2098 #define _PORT_PCS_DW10_GRP_B 0x6CC28 2099 #define _PORT_PCS_DW10_GRP_C 0x6CE28 2100 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2101 _PORT_PCS_DW10_LN01_B, \ 2102 _PORT_PCS_DW10_LN01_C) 2103 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2104 _PORT_PCS_DW10_GRP_B, \ 2105 _PORT_PCS_DW10_GRP_C) 2106 2107 #define TX2_SWING_CALC_INIT (1 << 31) 2108 #define TX1_SWING_CALC_INIT (1 << 30) 2109 2110 #define _PORT_PCS_DW12_LN01_A 0x162430 2111 #define _PORT_PCS_DW12_LN01_B 0x6C430 2112 #define _PORT_PCS_DW12_LN01_C 0x6C830 2113 #define _PORT_PCS_DW12_LN23_A 0x162630 2114 #define _PORT_PCS_DW12_LN23_B 0x6C630 2115 #define _PORT_PCS_DW12_LN23_C 0x6CA30 2116 #define _PORT_PCS_DW12_GRP_A 0x162c30 2117 #define _PORT_PCS_DW12_GRP_B 0x6CC30 2118 #define _PORT_PCS_DW12_GRP_C 0x6CE30 2119 #define LANESTAGGER_STRAP_OVRD (1 << 6) 2120 #define LANE_STAGGER_MASK 0x1F 2121 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2122 _PORT_PCS_DW12_LN01_B, \ 2123 _PORT_PCS_DW12_LN01_C) 2124 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2125 _PORT_PCS_DW12_LN23_B, \ 2126 _PORT_PCS_DW12_LN23_C) 2127 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2128 _PORT_PCS_DW12_GRP_B, \ 2129 _PORT_PCS_DW12_GRP_C) 2130 2131 /* BXT PHY TX registers */ 2132 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 2133 ((lane) & 1) * 0x80) 2134 2135 #define _PORT_TX_DW2_LN0_A 0x162508 2136 #define _PORT_TX_DW2_LN0_B 0x6C508 2137 #define _PORT_TX_DW2_LN0_C 0x6C908 2138 #define _PORT_TX_DW2_GRP_A 0x162D08 2139 #define _PORT_TX_DW2_GRP_B 0x6CD08 2140 #define _PORT_TX_DW2_GRP_C 0x6CF08 2141 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2142 _PORT_TX_DW2_LN0_B, \ 2143 _PORT_TX_DW2_LN0_C) 2144 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2145 _PORT_TX_DW2_GRP_B, \ 2146 _PORT_TX_DW2_GRP_C) 2147 #define MARGIN_000_SHIFT 16 2148 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 2149 #define UNIQ_TRANS_SCALE_SHIFT 8 2150 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 2151 2152 #define _PORT_TX_DW3_LN0_A 0x16250C 2153 #define _PORT_TX_DW3_LN0_B 0x6C50C 2154 #define _PORT_TX_DW3_LN0_C 0x6C90C 2155 #define _PORT_TX_DW3_GRP_A 0x162D0C 2156 #define _PORT_TX_DW3_GRP_B 0x6CD0C 2157 #define _PORT_TX_DW3_GRP_C 0x6CF0C 2158 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2159 _PORT_TX_DW3_LN0_B, \ 2160 _PORT_TX_DW3_LN0_C) 2161 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2162 _PORT_TX_DW3_GRP_B, \ 2163 _PORT_TX_DW3_GRP_C) 2164 #define SCALE_DCOMP_METHOD (1 << 26) 2165 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 2166 2167 #define _PORT_TX_DW4_LN0_A 0x162510 2168 #define _PORT_TX_DW4_LN0_B 0x6C510 2169 #define _PORT_TX_DW4_LN0_C 0x6C910 2170 #define _PORT_TX_DW4_GRP_A 0x162D10 2171 #define _PORT_TX_DW4_GRP_B 0x6CD10 2172 #define _PORT_TX_DW4_GRP_C 0x6CF10 2173 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2174 _PORT_TX_DW4_LN0_B, \ 2175 _PORT_TX_DW4_LN0_C) 2176 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2177 _PORT_TX_DW4_GRP_B, \ 2178 _PORT_TX_DW4_GRP_C) 2179 #define DEEMPH_SHIFT 24 2180 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 2181 2182 #define _PORT_TX_DW5_LN0_A 0x162514 2183 #define _PORT_TX_DW5_LN0_B 0x6C514 2184 #define _PORT_TX_DW5_LN0_C 0x6C914 2185 #define _PORT_TX_DW5_GRP_A 0x162D14 2186 #define _PORT_TX_DW5_GRP_B 0x6CD14 2187 #define _PORT_TX_DW5_GRP_C 0x6CF14 2188 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2189 _PORT_TX_DW5_LN0_B, \ 2190 _PORT_TX_DW5_LN0_C) 2191 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2192 _PORT_TX_DW5_GRP_B, \ 2193 _PORT_TX_DW5_GRP_C) 2194 #define DCC_DELAY_RANGE_1 (1 << 9) 2195 #define DCC_DELAY_RANGE_2 (1 << 8) 2196 2197 #define _PORT_TX_DW14_LN0_A 0x162538 2198 #define _PORT_TX_DW14_LN0_B 0x6C538 2199 #define _PORT_TX_DW14_LN0_C 0x6C938 2200 #define LATENCY_OPTIM_SHIFT 30 2201 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 2202 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 2203 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 2204 _PORT_TX_DW14_LN0_C) + \ 2205 _BXT_LANE_OFFSET(lane)) 2206 2207 /* UAIMI scratch pad register 1 */ 2208 #define UAIMI_SPR1 _MMIO(0x4F074) 2209 /* SKL VccIO mask */ 2210 #define SKL_VCCIO_MASK 0x1 2211 /* SKL balance leg register */ 2212 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 2213 /* I_boost values */ 2214 #define BALANCE_LEG_SHIFT(port) (8+3*(port)) 2215 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) 2216 /* Balance leg disable bits */ 2217 #define BALANCE_LEG_DISABLE_SHIFT 23 2218 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 2219 2220 /* 2221 * Fence registers 2222 * [0-7] @ 0x2000 gen2,gen3 2223 * [8-15] @ 0x3000 945,g33,pnv 2224 * 2225 * [0-15] @ 0x3000 gen4,gen5 2226 * 2227 * [0-15] @ 0x100000 gen6,vlv,chv 2228 * [0-31] @ 0x100000 gen7+ 2229 */ 2230 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 2231 #define I830_FENCE_START_MASK 0x07f80000 2232 #define I830_FENCE_TILING_Y_SHIFT 12 2233 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 2234 #define I830_FENCE_PITCH_SHIFT 4 2235 #define I830_FENCE_REG_VALID (1<<0) 2236 #define I915_FENCE_MAX_PITCH_VAL 4 2237 #define I830_FENCE_MAX_PITCH_VAL 6 2238 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 2239 2240 #define I915_FENCE_START_MASK 0x0ff00000 2241 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 2242 2243 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 2244 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 2245 #define I965_FENCE_PITCH_SHIFT 2 2246 #define I965_FENCE_TILING_Y_SHIFT 1 2247 #define I965_FENCE_REG_VALID (1<<0) 2248 #define I965_FENCE_MAX_PITCH_VAL 0x0400 2249 2250 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 2251 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 2252 #define GEN6_FENCE_PITCH_SHIFT 32 2253 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 2254 2255 2256 /* control register for cpu gtt access */ 2257 #define TILECTL _MMIO(0x101000) 2258 #define TILECTL_SWZCTL (1 << 0) 2259 #define TILECTL_TLBPF (1 << 1) 2260 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 2261 #define TILECTL_BACKSNOOP_DIS (1 << 3) 2262 2263 /* 2264 * Instruction and interrupt control regs 2265 */ 2266 #define PGTBL_CTL _MMIO(0x02020) 2267 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 2268 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 2269 #define PGTBL_ER _MMIO(0x02024) 2270 #define PRB0_BASE (0x2030-0x30) 2271 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 2272 #define PRB2_BASE (0x2050-0x30) /* gen3 */ 2273 #define SRB0_BASE (0x2100-0x30) /* gen2 */ 2274 #define SRB1_BASE (0x2110-0x30) /* gen2 */ 2275 #define SRB2_BASE (0x2120-0x30) /* 830 */ 2276 #define SRB3_BASE (0x2130-0x30) /* 830 */ 2277 #define RENDER_RING_BASE 0x02000 2278 #define BSD_RING_BASE 0x04000 2279 #define GEN6_BSD_RING_BASE 0x12000 2280 #define GEN8_BSD2_RING_BASE 0x1c000 2281 #define VEBOX_RING_BASE 0x1a000 2282 #define BLT_RING_BASE 0x22000 2283 #define RING_TAIL(base) _MMIO((base)+0x30) 2284 #define RING_HEAD(base) _MMIO((base)+0x34) 2285 #define RING_START(base) _MMIO((base)+0x38) 2286 #define RING_CTL(base) _MMIO((base)+0x3c) 2287 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 2288 #define RING_SYNC_0(base) _MMIO((base)+0x40) 2289 #define RING_SYNC_1(base) _MMIO((base)+0x44) 2290 #define RING_SYNC_2(base) _MMIO((base)+0x48) 2291 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 2292 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 2293 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 2294 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 2295 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 2296 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 2297 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 2298 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 2299 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 2300 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 2301 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 2302 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 2303 #define GEN6_NOSYNC INVALID_MMIO_REG 2304 #define RING_PSMI_CTL(base) _MMIO((base)+0x50) 2305 #define RING_MAX_IDLE(base) _MMIO((base)+0x54) 2306 #define RING_HWS_PGA(base) _MMIO((base)+0x80) 2307 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080) 2308 #define RING_RESET_CTL(base) _MMIO((base)+0xd0) 2309 #define RESET_CTL_REQUEST_RESET (1 << 0) 2310 #define RESET_CTL_READY_TO_RESET (1 << 1) 2311 2312 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 2313 #define GTT_CACHE_EN_ALL 0xF0007FFF 2314 #define GEN7_WR_WATERMARK _MMIO(0x4028) 2315 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 2316 #define ARB_MODE _MMIO(0x4030) 2317 #define ARB_MODE_SWIZZLE_SNB (1<<4) 2318 #define ARB_MODE_SWIZZLE_IVB (1<<5) 2319 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 2320 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 2321 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 2322 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 2323 #define GEN7_LRA_LIMITS_REG_NUM 13 2324 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 2325 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 2326 2327 #define GAMTARBMODE _MMIO(0x04a08) 2328 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 2329 #define ARB_MODE_SWIZZLE_BDW (1<<1) 2330 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 2331 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id) 2332 #define RING_FAULT_GTTSEL_MASK (1<<11) 2333 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 2334 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 2335 #define RING_FAULT_VALID (1<<0) 2336 #define DONE_REG _MMIO(0x40b0) 2337 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 2338 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 2339 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index)*4) 2340 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 2341 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 2342 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 2343 #define RING_ACTHD(base) _MMIO((base)+0x74) 2344 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c) 2345 #define RING_NOPID(base) _MMIO((base)+0x94) 2346 #define RING_IMR(base) _MMIO((base)+0xa8) 2347 #define RING_HWSTAM(base) _MMIO((base)+0x98) 2348 #define RING_TIMESTAMP(base) _MMIO((base)+0x358) 2349 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4) 2350 #define TAIL_ADDR 0x001FFFF8 2351 #define HEAD_WRAP_COUNT 0xFFE00000 2352 #define HEAD_WRAP_ONE 0x00200000 2353 #define HEAD_ADDR 0x001FFFFC 2354 #define RING_NR_PAGES 0x001FF000 2355 #define RING_REPORT_MASK 0x00000006 2356 #define RING_REPORT_64K 0x00000002 2357 #define RING_REPORT_128K 0x00000004 2358 #define RING_NO_REPORT 0x00000000 2359 #define RING_VALID_MASK 0x00000001 2360 #define RING_VALID 0x00000001 2361 #define RING_INVALID 0x00000000 2362 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 2363 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 2364 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 2365 2366 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) 2367 #define RING_MAX_NONPRIV_SLOTS 12 2368 2369 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 2370 2371 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 2372 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18) 2373 2374 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 2375 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 2376 2377 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2378 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) 2379 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24) 2380 2381 #if 0 2382 #define PRB0_TAIL _MMIO(0x2030) 2383 #define PRB0_HEAD _MMIO(0x2034) 2384 #define PRB0_START _MMIO(0x2038) 2385 #define PRB0_CTL _MMIO(0x203c) 2386 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 2387 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 2388 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 2389 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 2390 #endif 2391 #define IPEIR_I965 _MMIO(0x2064) 2392 #define IPEHR_I965 _MMIO(0x2068) 2393 #define GEN7_SC_INSTDONE _MMIO(0x7100) 2394 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 2395 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 2396 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 2397 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 2398 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 2399 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 2400 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 2401 #define RING_IPEIR(base) _MMIO((base)+0x64) 2402 #define RING_IPEHR(base) _MMIO((base)+0x68) 2403 /* 2404 * On GEN4, only the render ring INSTDONE exists and has a different 2405 * layout than the GEN7+ version. 2406 * The GEN2 counterpart of this register is GEN2_INSTDONE. 2407 */ 2408 #define RING_INSTDONE(base) _MMIO((base)+0x6c) 2409 #define RING_INSTPS(base) _MMIO((base)+0x70) 2410 #define RING_DMA_FADD(base) _MMIO((base)+0x78) 2411 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */ 2412 #define RING_INSTPM(base) _MMIO((base)+0xc0) 2413 #define RING_MI_MODE(base) _MMIO((base)+0x9c) 2414 #define INSTPS _MMIO(0x2070) /* 965+ only */ 2415 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 2416 #define ACTHD_I965 _MMIO(0x2074) 2417 #define HWS_PGA _MMIO(0x2080) 2418 #define HWS_ADDRESS_MASK 0xfffff000 2419 #define HWS_START_ADDRESS_SHIFT 4 2420 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 2421 #define PWRCTX_EN (1<<0) 2422 #define IPEIR _MMIO(0x2088) 2423 #define IPEHR _MMIO(0x208c) 2424 #define GEN2_INSTDONE _MMIO(0x2090) 2425 #define NOPID _MMIO(0x2094) 2426 #define HWSTAM _MMIO(0x2098) 2427 #define DMA_FADD_I8XX _MMIO(0x20d0) 2428 #define RING_BBSTATE(base) _MMIO((base)+0x110) 2429 #define RING_BB_PPGTT (1 << 5) 2430 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */ 2431 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */ 2432 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */ 2433 #define RING_BBADDR(base) _MMIO((base)+0x140) 2434 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */ 2435 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */ 2436 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */ 2437 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */ 2438 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */ 2439 2440 #define ERROR_GEN6 _MMIO(0x40a0) 2441 #define GEN7_ERR_INT _MMIO(0x44040) 2442 #define ERR_INT_POISON (1<<31) 2443 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 2444 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 2445 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 2446 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 2447 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 2448 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 2449 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3)) 2450 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 2451 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 2452 2453 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 2454 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 2455 2456 #define FPGA_DBG _MMIO(0x42300) 2457 #define FPGA_DBG_RM_NOCLAIM (1<<31) 2458 2459 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 2460 #define CLAIM_ER_CLR (1 << 31) 2461 #define CLAIM_ER_OVERFLOW (1 << 16) 2462 #define CLAIM_ER_CTR_MASK 0xffff 2463 2464 #define DERRMR _MMIO(0x44050) 2465 /* Note that HBLANK events are reserved on bdw+ */ 2466 #define DERRMR_PIPEA_SCANLINE (1<<0) 2467 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 2468 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 2469 #define DERRMR_PIPEA_VBLANK (1<<3) 2470 #define DERRMR_PIPEA_HBLANK (1<<5) 2471 #define DERRMR_PIPEB_SCANLINE (1<<8) 2472 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 2473 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 2474 #define DERRMR_PIPEB_VBLANK (1<<11) 2475 #define DERRMR_PIPEB_HBLANK (1<<13) 2476 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 2477 #define DERRMR_PIPEC_SCANLINE (1<<14) 2478 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 2479 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 2480 #define DERRMR_PIPEC_VBLANK (1<<21) 2481 #define DERRMR_PIPEC_HBLANK (1<<22) 2482 2483 2484 /* GM45+ chicken bits -- debug workaround bits that may be required 2485 * for various sorts of correct behavior. The top 16 bits of each are 2486 * the enables for writing to the corresponding low bit. 2487 */ 2488 #define _3D_CHICKEN _MMIO(0x2084) 2489 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 2490 #define _3D_CHICKEN2 _MMIO(0x208c) 2491 /* Disables pipelining of read flushes past the SF-WIZ interface. 2492 * Required on all Ironlake steppings according to the B-Spec, but the 2493 * particular danger of not doing so is not specified. 2494 */ 2495 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2496 #define _3D_CHICKEN3 _MMIO(0x2090) 2497 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2498 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 2499 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2500 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 2501 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2502 2503 #define MI_MODE _MMIO(0x209c) 2504 # define VS_TIMER_DISPATCH (1 << 6) 2505 # define MI_FLUSH_ENABLE (1 << 12) 2506 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 2507 # define MODE_IDLE (1 << 9) 2508 # define STOP_RING (1 << 8) 2509 2510 #define GEN6_GT_MODE _MMIO(0x20d0) 2511 #define GEN7_GT_MODE _MMIO(0x7008) 2512 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 2513 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 2514 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 2515 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 2516 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 2517 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 2518 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 2519 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 2520 2521 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2522 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2523 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2524 2525 /* WaClearTdlStateAckDirtyBits */ 2526 #define GEN8_STATE_ACK _MMIO(0x20F0) 2527 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 2528 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 2529 #define GEN9_STATE_ACK_TDL0 (1 << 12) 2530 #define GEN9_STATE_ACK_TDL1 (1 << 13) 2531 #define GEN9_STATE_ACK_TDL2 (1 << 14) 2532 #define GEN9_STATE_ACK_TDL3 (1 << 15) 2533 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 2534 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 2535 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 2536 2537 #define GFX_MODE _MMIO(0x2520) 2538 #define GFX_MODE_GEN7 _MMIO(0x229c) 2539 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c) 2540 #define GFX_RUN_LIST_ENABLE (1<<15) 2541 #define GFX_INTERRUPT_STEERING (1<<14) 2542 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 2543 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 2544 #define GFX_REPLAY_MODE (1<<11) 2545 #define GFX_PSMI_GRANULARITY (1<<10) 2546 #define GFX_PPGTT_ENABLE (1<<9) 2547 #define GEN8_GFX_PPGTT_48B (1<<7) 2548 2549 #define GFX_FORWARD_VBLANK_MASK (3<<5) 2550 #define GFX_FORWARD_VBLANK_NEVER (0<<5) 2551 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5) 2552 #define GFX_FORWARD_VBLANK_COND (2<<5) 2553 2554 #define VLV_DISPLAY_BASE 0x180000 2555 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 2556 #define BXT_MIPI_BASE 0x60000 2557 2558 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 2559 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 2560 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 2561 #define IER _MMIO(0x20a0) 2562 #define IIR _MMIO(0x20a4) 2563 #define IMR _MMIO(0x20a8) 2564 #define ISR _MMIO(0x20ac) 2565 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 2566 #define GINT_DIS (1<<22) 2567 #define GCFG_DIS (1<<8) 2568 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 2569 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 2570 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 2571 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 2572 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 2573 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 2574 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 2575 #define VLV_PCBR_ADDR_SHIFT 12 2576 2577 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 2578 #define EIR _MMIO(0x20b0) 2579 #define EMR _MMIO(0x20b4) 2580 #define ESR _MMIO(0x20b8) 2581 #define GM45_ERROR_PAGE_TABLE (1<<5) 2582 #define GM45_ERROR_MEM_PRIV (1<<4) 2583 #define I915_ERROR_PAGE_TABLE (1<<4) 2584 #define GM45_ERROR_CP_PRIV (1<<3) 2585 #define I915_ERROR_MEMORY_REFRESH (1<<1) 2586 #define I915_ERROR_INSTRUCTION (1<<0) 2587 #define INSTPM _MMIO(0x20c0) 2588 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 2589 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 2590 will not assert AGPBUSY# and will only 2591 be delivered when out of C3. */ 2592 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 2593 #define INSTPM_TLB_INVALIDATE (1<<9) 2594 #define INSTPM_SYNC_FLUSH (1<<5) 2595 #define ACTHD _MMIO(0x20c8) 2596 #define MEM_MODE _MMIO(0x20cc) 2597 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 2598 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 2599 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 2600 #define FW_BLC _MMIO(0x20d8) 2601 #define FW_BLC2 _MMIO(0x20dc) 2602 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 2603 #define FW_BLC_SELF_EN_MASK (1<<31) 2604 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 2605 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 2606 #define MM_BURST_LENGTH 0x00700000 2607 #define MM_FIFO_WATERMARK 0x0001F000 2608 #define LM_BURST_LENGTH 0x00000700 2609 #define LM_FIFO_WATERMARK 0x0000001F 2610 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 2611 2612 /* Make render/texture TLB fetches lower priorty than associated data 2613 * fetches. This is not turned on by default 2614 */ 2615 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 2616 2617 /* Isoch request wait on GTT enable (Display A/B/C streams). 2618 * Make isoch requests stall on the TLB update. May cause 2619 * display underruns (test mode only) 2620 */ 2621 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 2622 2623 /* Block grant count for isoch requests when block count is 2624 * set to a finite value. 2625 */ 2626 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 2627 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 2628 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 2629 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 2630 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 2631 2632 /* Enable render writes to complete in C2/C3/C4 power states. 2633 * If this isn't enabled, render writes are prevented in low 2634 * power states. That seems bad to me. 2635 */ 2636 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 2637 2638 /* This acknowledges an async flip immediately instead 2639 * of waiting for 2TLB fetches. 2640 */ 2641 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 2642 2643 /* Enables non-sequential data reads through arbiter 2644 */ 2645 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 2646 2647 /* Disable FSB snooping of cacheable write cycles from binner/render 2648 * command stream 2649 */ 2650 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 2651 2652 /* Arbiter time slice for non-isoch streams */ 2653 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 2654 #define MI_ARB_TIME_SLICE_1 (0 << 5) 2655 #define MI_ARB_TIME_SLICE_2 (1 << 5) 2656 #define MI_ARB_TIME_SLICE_4 (2 << 5) 2657 #define MI_ARB_TIME_SLICE_6 (3 << 5) 2658 #define MI_ARB_TIME_SLICE_8 (4 << 5) 2659 #define MI_ARB_TIME_SLICE_10 (5 << 5) 2660 #define MI_ARB_TIME_SLICE_14 (6 << 5) 2661 #define MI_ARB_TIME_SLICE_16 (7 << 5) 2662 2663 /* Low priority grace period page size */ 2664 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 2665 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 2666 2667 /* Disable display A/B trickle feed */ 2668 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 2669 2670 /* Set display plane priority */ 2671 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 2672 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 2673 2674 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 2675 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 2676 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 2677 2678 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 2679 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 2680 #define CM0_IZ_OPT_DISABLE (1<<6) 2681 #define CM0_ZR_OPT_DISABLE (1<<5) 2682 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 2683 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 2684 #define CM0_COLOR_EVICT_DISABLE (1<<3) 2685 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 2686 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 2687 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 2688 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 2689 #define GFX_FLSH_CNTL_EN (1<<0) 2690 #define ECOSKPD _MMIO(0x21d0) 2691 #define ECO_GATING_CX_ONLY (1<<3) 2692 #define ECO_FLIP_DONE (1<<0) 2693 2694 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 2695 #define RC_OP_FLUSH_ENABLE (1<<0) 2696 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 2697 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 2698 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 2699 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 2700 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) 2701 2702 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 2703 #define GEN6_BLITTER_LOCK_SHIFT 16 2704 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 2705 2706 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 2707 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 2708 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 2709 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 2710 2711 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 2712 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 2713 2714 /* Fuse readout registers for GT */ 2715 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 2716 #define CHV_FGT_DISABLE_SS0 (1 << 10) 2717 #define CHV_FGT_DISABLE_SS1 (1 << 11) 2718 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 2719 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 2720 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 2721 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 2722 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 2723 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 2724 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 2725 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 2726 2727 #define GEN8_FUSE2 _MMIO(0x9120) 2728 #define GEN8_F2_SS_DIS_SHIFT 21 2729 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 2730 #define GEN8_F2_S_ENA_SHIFT 25 2731 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 2732 2733 #define GEN9_F2_SS_DIS_SHIFT 20 2734 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 2735 2736 #define GEN10_F2_S_ENA_SHIFT 22 2737 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 2738 #define GEN10_F2_SS_DIS_SHIFT 18 2739 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 2740 2741 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 2742 #define GEN8_EU_DIS0_S0_MASK 0xffffff 2743 #define GEN8_EU_DIS0_S1_SHIFT 24 2744 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 2745 2746 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 2747 #define GEN8_EU_DIS1_S1_MASK 0xffff 2748 #define GEN8_EU_DIS1_S2_SHIFT 16 2749 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 2750 2751 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 2752 #define GEN8_EU_DIS2_S2_MASK 0xff 2753 2754 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4) 2755 2756 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 2757 #define GEN10_EU_DIS_SS_MASK 0xff 2758 2759 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 2760 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 2761 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 2762 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 2763 #define GEN6_BSD_GO_INDICATOR (1 << 4) 2764 2765 /* On modern GEN architectures interrupt control consists of two sets 2766 * of registers. The first set pertains to the ring generating the 2767 * interrupt. The second control is for the functional block generating the 2768 * interrupt. These are PM, GT, DE, etc. 2769 * 2770 * Luckily *knocks on wood* all the ring interrupt bits match up with the 2771 * GT interrupt bits, so we don't need to duplicate the defines. 2772 * 2773 * These defines should cover us well from SNB->HSW with minor exceptions 2774 * it can also work on ILK. 2775 */ 2776 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 2777 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 2778 #define GT_BLT_USER_INTERRUPT (1 << 22) 2779 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 2780 #define GT_BSD_USER_INTERRUPT (1 << 12) 2781 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 2782 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 2783 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 2784 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 2785 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 2786 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 2787 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 2788 #define GT_RENDER_USER_INTERRUPT (1 << 0) 2789 2790 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 2791 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 2792 2793 #define GT_PARITY_ERROR(dev_priv) \ 2794 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 2795 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 2796 2797 /* These are all the "old" interrupts */ 2798 #define ILK_BSD_USER_INTERRUPT (1<<5) 2799 2800 #define I915_PM_INTERRUPT (1<<31) 2801 #define I915_ISP_INTERRUPT (1<<22) 2802 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 2803 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 2804 #define I915_MIPIC_INTERRUPT (1<<19) 2805 #define I915_MIPIA_INTERRUPT (1<<18) 2806 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 2807 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 2808 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 2809 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 2810 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 2811 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 2812 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 2813 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 2814 #define I915_HWB_OOM_INTERRUPT (1<<13) 2815 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 2816 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 2817 #define I915_MISC_INTERRUPT (1<<11) 2818 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 2819 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 2820 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 2821 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 2822 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 2823 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 2824 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 2825 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 2826 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 2827 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 2828 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 2829 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 2830 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 2831 #define I915_DEBUG_INTERRUPT (1<<2) 2832 #define I915_WINVALID_INTERRUPT (1<<1) 2833 #define I915_USER_INTERRUPT (1<<1) 2834 #define I915_ASLE_INTERRUPT (1<<0) 2835 #define I915_BSD_USER_INTERRUPT (1<<25) 2836 2837 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 2838 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 2839 2840 /* DisplayPort Audio w/ LPE */ 2841 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 2842 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 2843 2844 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 2845 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 2846 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 2847 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 2848 _VLV_AUD_PORT_EN_B_DBG, \ 2849 _VLV_AUD_PORT_EN_C_DBG, \ 2850 _VLV_AUD_PORT_EN_D_DBG) 2851 #define VLV_AMP_MUTE (1 << 1) 2852 2853 #define GEN6_BSD_RNCID _MMIO(0x12198) 2854 2855 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 2856 #define GEN7_FF_SCHED_MASK 0x0077070 2857 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 2858 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 2859 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 2860 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 2861 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 2862 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 2863 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 2864 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 2865 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 2866 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 2867 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 2868 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 2869 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 2870 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 2871 2872 /* 2873 * Framebuffer compression (915+ only) 2874 */ 2875 2876 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 2877 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 2878 #define FBC_CONTROL _MMIO(0x3208) 2879 #define FBC_CTL_EN (1<<31) 2880 #define FBC_CTL_PERIODIC (1<<30) 2881 #define FBC_CTL_INTERVAL_SHIFT (16) 2882 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 2883 #define FBC_CTL_C3_IDLE (1<<13) 2884 #define FBC_CTL_STRIDE_SHIFT (5) 2885 #define FBC_CTL_FENCENO_SHIFT (0) 2886 #define FBC_COMMAND _MMIO(0x320c) 2887 #define FBC_CMD_COMPRESS (1<<0) 2888 #define FBC_STATUS _MMIO(0x3210) 2889 #define FBC_STAT_COMPRESSING (1<<31) 2890 #define FBC_STAT_COMPRESSED (1<<30) 2891 #define FBC_STAT_MODIFIED (1<<29) 2892 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 2893 #define FBC_CONTROL2 _MMIO(0x3214) 2894 #define FBC_CTL_FENCE_DBL (0<<4) 2895 #define FBC_CTL_IDLE_IMM (0<<2) 2896 #define FBC_CTL_IDLE_FULL (1<<2) 2897 #define FBC_CTL_IDLE_LINE (2<<2) 2898 #define FBC_CTL_IDLE_DEBUG (3<<2) 2899 #define FBC_CTL_CPU_FENCE (1<<1) 2900 #define FBC_CTL_PLANE(plane) ((plane)<<0) 2901 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 2902 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 2903 2904 #define FBC_LL_SIZE (1536) 2905 2906 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 2907 #define FBC_LLC_FULLY_OPEN (1<<30) 2908 2909 /* Framebuffer compression for GM45+ */ 2910 #define DPFC_CB_BASE _MMIO(0x3200) 2911 #define DPFC_CONTROL _MMIO(0x3208) 2912 #define DPFC_CTL_EN (1<<31) 2913 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 2914 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 2915 #define DPFC_CTL_FENCE_EN (1<<29) 2916 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 2917 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 2918 #define DPFC_SR_EN (1<<10) 2919 #define DPFC_CTL_LIMIT_1X (0<<6) 2920 #define DPFC_CTL_LIMIT_2X (1<<6) 2921 #define DPFC_CTL_LIMIT_4X (2<<6) 2922 #define DPFC_RECOMP_CTL _MMIO(0x320c) 2923 #define DPFC_RECOMP_STALL_EN (1<<27) 2924 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 2925 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 2926 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 2927 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 2928 #define DPFC_STATUS _MMIO(0x3210) 2929 #define DPFC_INVAL_SEG_SHIFT (16) 2930 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 2931 #define DPFC_COMP_SEG_SHIFT (0) 2932 #define DPFC_COMP_SEG_MASK (0x000007ff) 2933 #define DPFC_STATUS2 _MMIO(0x3214) 2934 #define DPFC_FENCE_YOFF _MMIO(0x3218) 2935 #define DPFC_CHICKEN _MMIO(0x3224) 2936 #define DPFC_HT_MODIFY (1<<31) 2937 2938 /* Framebuffer compression for Ironlake */ 2939 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 2940 #define ILK_DPFC_CONTROL _MMIO(0x43208) 2941 #define FBC_CTL_FALSE_COLOR (1<<10) 2942 /* The bit 28-8 is reserved */ 2943 #define DPFC_RESERVED (0x1FFFFF00) 2944 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 2945 #define ILK_DPFC_STATUS _MMIO(0x43210) 2946 #define ILK_DPFC_COMP_SEG_MASK 0x7ff 2947 #define IVB_FBC_STATUS2 _MMIO(0x43214) 2948 #define IVB_FBC_COMP_SEG_MASK 0x7ff 2949 #define BDW_FBC_COMP_SEG_MASK 0xfff 2950 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 2951 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 2952 #define ILK_DPFC_DISABLE_DUMMY0 (1<<8) 2953 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23) 2954 #define ILK_FBC_RT_BASE _MMIO(0x2128) 2955 #define ILK_FBC_RT_VALID (1<<0) 2956 #define SNB_FBC_FRONT_BUFFER (1<<1) 2957 2958 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 2959 #define ILK_FBCQ_DIS (1<<22) 2960 #define ILK_PABSTRETCH_DIS (1<<21) 2961 2962 2963 /* 2964 * Framebuffer compression for Sandybridge 2965 * 2966 * The following two registers are of type GTTMMADR 2967 */ 2968 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 2969 #define SNB_CPU_FENCE_ENABLE (1<<29) 2970 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 2971 2972 /* Framebuffer compression for Ivybridge */ 2973 #define IVB_FBC_RT_BASE _MMIO(0x7020) 2974 2975 #define IPS_CTL _MMIO(0x43408) 2976 #define IPS_ENABLE (1 << 31) 2977 2978 #define MSG_FBC_REND_STATE _MMIO(0x50380) 2979 #define FBC_REND_NUKE (1<<2) 2980 #define FBC_REND_CACHE_CLEAN (1<<1) 2981 2982 /* 2983 * GPIO regs 2984 */ 2985 #define GPIOA _MMIO(0x5010) 2986 #define GPIOB _MMIO(0x5014) 2987 #define GPIOC _MMIO(0x5018) 2988 #define GPIOD _MMIO(0x501c) 2989 #define GPIOE _MMIO(0x5020) 2990 #define GPIOF _MMIO(0x5024) 2991 #define GPIOG _MMIO(0x5028) 2992 #define GPIOH _MMIO(0x502c) 2993 # define GPIO_CLOCK_DIR_MASK (1 << 0) 2994 # define GPIO_CLOCK_DIR_IN (0 << 1) 2995 # define GPIO_CLOCK_DIR_OUT (1 << 1) 2996 # define GPIO_CLOCK_VAL_MASK (1 << 2) 2997 # define GPIO_CLOCK_VAL_OUT (1 << 3) 2998 # define GPIO_CLOCK_VAL_IN (1 << 4) 2999 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 3000 # define GPIO_DATA_DIR_MASK (1 << 8) 3001 # define GPIO_DATA_DIR_IN (0 << 9) 3002 # define GPIO_DATA_DIR_OUT (1 << 9) 3003 # define GPIO_DATA_VAL_MASK (1 << 10) 3004 # define GPIO_DATA_VAL_OUT (1 << 11) 3005 # define GPIO_DATA_VAL_IN (1 << 12) 3006 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 3007 3008 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 3009 #define GMBUS_RATE_100KHZ (0<<8) 3010 #define GMBUS_RATE_50KHZ (1<<8) 3011 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 3012 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 3013 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 3014 #define GMBUS_PIN_DISABLED 0 3015 #define GMBUS_PIN_SSC 1 3016 #define GMBUS_PIN_VGADDC 2 3017 #define GMBUS_PIN_PANEL 3 3018 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 3019 #define GMBUS_PIN_DPC 4 /* HDMIC */ 3020 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 3021 #define GMBUS_PIN_DPD 6 /* HDMID */ 3022 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 3023 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ 3024 #define GMBUS_PIN_2_BXT 2 3025 #define GMBUS_PIN_3_BXT 3 3026 #define GMBUS_PIN_4_CNP 4 3027 #define GMBUS_NUM_PINS 7 /* including 0 */ 3028 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 3029 #define GMBUS_SW_CLR_INT (1<<31) 3030 #define GMBUS_SW_RDY (1<<30) 3031 #define GMBUS_ENT (1<<29) /* enable timeout */ 3032 #define GMBUS_CYCLE_NONE (0<<25) 3033 #define GMBUS_CYCLE_WAIT (1<<25) 3034 #define GMBUS_CYCLE_INDEX (2<<25) 3035 #define GMBUS_CYCLE_STOP (4<<25) 3036 #define GMBUS_BYTE_COUNT_SHIFT 16 3037 #define GMBUS_BYTE_COUNT_MAX 256U 3038 #define GMBUS_SLAVE_INDEX_SHIFT 8 3039 #define GMBUS_SLAVE_ADDR_SHIFT 1 3040 #define GMBUS_SLAVE_READ (1<<0) 3041 #define GMBUS_SLAVE_WRITE (0<<0) 3042 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 3043 #define GMBUS_INUSE (1<<15) 3044 #define GMBUS_HW_WAIT_PHASE (1<<14) 3045 #define GMBUS_STALL_TIMEOUT (1<<13) 3046 #define GMBUS_INT (1<<12) 3047 #define GMBUS_HW_RDY (1<<11) 3048 #define GMBUS_SATOER (1<<10) 3049 #define GMBUS_ACTIVE (1<<9) 3050 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 3051 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 3052 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 3053 #define GMBUS_NAK_EN (1<<3) 3054 #define GMBUS_IDLE_EN (1<<2) 3055 #define GMBUS_HW_WAIT_EN (1<<1) 3056 #define GMBUS_HW_RDY_EN (1<<0) 3057 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 3058 #define GMBUS_2BYTE_INDEX_EN (1<<31) 3059 3060 /* 3061 * Clock control & power management 3062 */ 3063 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 3064 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 3065 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 3066 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 3067 3068 #define VGA0 _MMIO(0x6000) 3069 #define VGA1 _MMIO(0x6004) 3070 #define VGA_PD _MMIO(0x6010) 3071 #define VGA0_PD_P2_DIV_4 (1 << 7) 3072 #define VGA0_PD_P1_DIV_2 (1 << 5) 3073 #define VGA0_PD_P1_SHIFT 0 3074 #define VGA0_PD_P1_MASK (0x1f << 0) 3075 #define VGA1_PD_P2_DIV_4 (1 << 15) 3076 #define VGA1_PD_P1_DIV_2 (1 << 13) 3077 #define VGA1_PD_P1_SHIFT 8 3078 #define VGA1_PD_P1_MASK (0x1f << 8) 3079 #define DPLL_VCO_ENABLE (1 << 31) 3080 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 3081 #define DPLL_DVO_2X_MODE (1 << 30) 3082 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 3083 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 3084 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 3085 #define DPLL_VGA_MODE_DIS (1 << 28) 3086 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 3087 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 3088 #define DPLL_MODE_MASK (3 << 26) 3089 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 3090 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 3091 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 3092 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 3093 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 3094 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 3095 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 3096 #define DPLL_LOCK_VLV (1<<15) 3097 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 3098 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) 3099 #define DPLL_SSC_REF_CLK_CHV (1<<13) 3100 #define DPLL_PORTC_READY_MASK (0xf << 4) 3101 #define DPLL_PORTB_READY_MASK (0xf) 3102 3103 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 3104 3105 /* Additional CHV pll/phy registers */ 3106 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 3107 #define DPLL_PORTD_READY_MASK (0xf) 3108 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 3109 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27)) 3110 #define PHY_LDO_DELAY_0NS 0x0 3111 #define PHY_LDO_DELAY_200NS 0x1 3112 #define PHY_LDO_DELAY_600NS 0x2 3113 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) 3114 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11)) 3115 #define PHY_CH_SU_PSR 0x1 3116 #define PHY_CH_DEEP_PSR 0x7 3117 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) 3118 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 3119 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 3120 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 3121 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch)))) 3122 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline)))) 3123 3124 /* 3125 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 3126 * this field (only one bit may be set). 3127 */ 3128 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 3129 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 3130 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 3131 /* i830, required in DVO non-gang */ 3132 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 3133 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 3134 #define PLL_REF_INPUT_DREFCLK (0 << 13) 3135 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 3136 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 3137 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 3138 #define PLL_REF_INPUT_MASK (3 << 13) 3139 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 3140 /* Ironlake */ 3141 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 3142 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 3143 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 3144 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 3145 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 3146 3147 /* 3148 * Parallel to Serial Load Pulse phase selection. 3149 * Selects the phase for the 10X DPLL clock for the PCIe 3150 * digital display port. The range is 4 to 13; 10 or more 3151 * is just a flip delay. The default is 6 3152 */ 3153 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 3154 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 3155 /* 3156 * SDVO multiplier for 945G/GM. Not used on 965. 3157 */ 3158 #define SDVO_MULTIPLIER_MASK 0x000000ff 3159 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 3160 #define SDVO_MULTIPLIER_SHIFT_VGA 0 3161 3162 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 3163 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 3164 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 3165 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 3166 3167 /* 3168 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 3169 * 3170 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 3171 */ 3172 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 3173 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 3174 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 3175 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 3176 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 3177 /* 3178 * SDVO/UDI pixel multiplier. 3179 * 3180 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 3181 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 3182 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 3183 * dummy bytes in the datastream at an increased clock rate, with both sides of 3184 * the link knowing how many bytes are fill. 3185 * 3186 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 3187 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 3188 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 3189 * through an SDVO command. 3190 * 3191 * This register field has values of multiplication factor minus 1, with 3192 * a maximum multiplier of 5 for SDVO. 3193 */ 3194 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 3195 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 3196 /* 3197 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 3198 * This best be set to the default value (3) or the CRT won't work. No, 3199 * I don't entirely understand what this does... 3200 */ 3201 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 3202 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 3203 3204 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 3205 3206 #define _FPA0 0x6040 3207 #define _FPA1 0x6044 3208 #define _FPB0 0x6048 3209 #define _FPB1 0x604c 3210 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 3211 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 3212 #define FP_N_DIV_MASK 0x003f0000 3213 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 3214 #define FP_N_DIV_SHIFT 16 3215 #define FP_M1_DIV_MASK 0x00003f00 3216 #define FP_M1_DIV_SHIFT 8 3217 #define FP_M2_DIV_MASK 0x0000003f 3218 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 3219 #define FP_M2_DIV_SHIFT 0 3220 #define DPLL_TEST _MMIO(0x606c) 3221 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 3222 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 3223 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 3224 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 3225 #define DPLLB_TEST_N_BYPASS (1 << 19) 3226 #define DPLLB_TEST_M_BYPASS (1 << 18) 3227 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 3228 #define DPLLA_TEST_N_BYPASS (1 << 3) 3229 #define DPLLA_TEST_M_BYPASS (1 << 2) 3230 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 3231 #define D_STATE _MMIO(0x6104) 3232 #define DSTATE_GFX_RESET_I830 (1<<6) 3233 #define DSTATE_PLL_D3_OFF (1<<3) 3234 #define DSTATE_GFX_CLOCK_GATING (1<<1) 3235 #define DSTATE_DOT_CLOCK_GATING (1<<0) 3236 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) 3237 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 3238 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 3239 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 3240 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 3241 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 3242 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 3243 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 3244 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 3245 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 3246 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 3247 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 3248 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 3249 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 3250 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 3251 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 3252 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 3253 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 3254 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 3255 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 3256 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 3257 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 3258 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3259 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 3260 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 3261 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 3262 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 3263 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 3264 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 3265 /* 3266 * This bit must be set on the 830 to prevent hangs when turning off the 3267 * overlay scaler. 3268 */ 3269 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 3270 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 3271 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 3272 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 3273 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 3274 3275 #define RENCLK_GATE_D1 _MMIO(0x6204) 3276 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 3277 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 3278 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 3279 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 3280 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 3281 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 3282 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 3283 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 3284 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 3285 /* This bit must be unset on 855,865 */ 3286 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 3287 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 3288 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 3289 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 3290 /* This bit must be set on 855,865. */ 3291 # define SV_CLOCK_GATE_DISABLE (1 << 0) 3292 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 3293 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 3294 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 3295 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 3296 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 3297 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 3298 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 3299 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 3300 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 3301 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 3302 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 3303 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 3304 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 3305 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 3306 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 3307 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 3308 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 3309 3310 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 3311 /* This bit must always be set on 965G/965GM */ 3312 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 3313 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 3314 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 3315 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 3316 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 3317 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 3318 /* This bit must always be set on 965G */ 3319 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 3320 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 3321 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 3322 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 3323 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 3324 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 3325 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 3326 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 3327 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 3328 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 3329 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 3330 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 3331 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 3332 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 3333 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 3334 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 3335 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 3336 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 3337 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 3338 3339 #define RENCLK_GATE_D2 _MMIO(0x6208) 3340 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 3341 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 3342 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 3343 3344 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 3345 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 3346 3347 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 3348 #define DEUC _MMIO(0x6214) /* CRL only */ 3349 3350 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 3351 #define FW_CSPWRDWNEN (1<<15) 3352 3353 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 3354 3355 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 3356 #define CDCLK_FREQ_SHIFT 4 3357 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 3358 #define CZCLK_FREQ_MASK 0xf 3359 3360 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 3361 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 3362 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 3363 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 3364 #define PFI_CREDIT_RESEND (1 << 27) 3365 #define VGA_FAST_MODE_DISABLE (1 << 14) 3366 3367 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 3368 3369 /* 3370 * Palette regs 3371 */ 3372 #define PALETTE_A_OFFSET 0xa000 3373 #define PALETTE_B_OFFSET 0xa800 3374 #define CHV_PALETTE_C_OFFSET 0xc000 3375 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ 3376 dev_priv->info.display_mmio_offset + (i) * 4) 3377 3378 /* MCH MMIO space */ 3379 3380 /* 3381 * MCHBAR mirror. 3382 * 3383 * This mirrors the MCHBAR MMIO space whose location is determined by 3384 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 3385 * every way. It is not accessible from the CP register read instructions. 3386 * 3387 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 3388 * just read. 3389 */ 3390 #define MCHBAR_MIRROR_BASE 0x10000 3391 3392 #define MCHBAR_MIRROR_BASE_SNB 0x140000 3393 3394 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 3395 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 3396 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 3397 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 3398 3399 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 3400 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 3401 3402 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 3403 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 3404 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 3405 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 3406 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 3407 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 3408 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 3409 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 3410 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 3411 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 3412 3413 /* Pineview MCH register contains DDR3 setting */ 3414 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 3415 #define CSHRDDR3CTL_DDR3 (1 << 2) 3416 3417 /* 965 MCH register controlling DRAM channel configuration */ 3418 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 3419 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 3420 3421 /* snb MCH registers for reading the DRAM channel configuration */ 3422 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 3423 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 3424 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 3425 #define MAD_DIMM_ECC_MASK (0x3 << 24) 3426 #define MAD_DIMM_ECC_OFF (0x0 << 24) 3427 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 3428 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 3429 #define MAD_DIMM_ECC_ON (0x3 << 24) 3430 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 3431 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 3432 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 3433 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 3434 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 3435 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 3436 #define MAD_DIMM_A_SELECT (0x1 << 16) 3437 /* DIMM sizes are in multiples of 256mb. */ 3438 #define MAD_DIMM_B_SIZE_SHIFT 8 3439 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 3440 #define MAD_DIMM_A_SIZE_SHIFT 0 3441 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 3442 3443 /* snb MCH registers for priority tuning */ 3444 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 3445 #define MCH_SSKPD_WM0_MASK 0x3f 3446 #define MCH_SSKPD_WM0_VAL 0xc 3447 3448 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) 3449 3450 /* Clocking configuration register */ 3451 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 3452 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 3453 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 3454 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 3455 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 3456 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 3457 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 3458 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 3459 /* 3460 * Note that on at least on ELK the below value is reported for both 3461 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet 3462 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. 3463 */ 3464 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 3465 #define CLKCFG_FSB_MASK (7 << 0) 3466 #define CLKCFG_MEM_533 (1 << 4) 3467 #define CLKCFG_MEM_667 (2 << 4) 3468 #define CLKCFG_MEM_800 (3 << 4) 3469 #define CLKCFG_MEM_MASK (7 << 4) 3470 3471 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 3472 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 3473 3474 #define TSC1 _MMIO(0x11001) 3475 #define TSE (1<<0) 3476 #define TR1 _MMIO(0x11006) 3477 #define TSFS _MMIO(0x11020) 3478 #define TSFS_SLOPE_MASK 0x0000ff00 3479 #define TSFS_SLOPE_SHIFT 8 3480 #define TSFS_INTR_MASK 0x000000ff 3481 3482 #define CRSTANDVID _MMIO(0x11100) 3483 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 3484 #define PXVFREQ_PX_MASK 0x7f000000 3485 #define PXVFREQ_PX_SHIFT 24 3486 #define VIDFREQ_BASE _MMIO(0x11110) 3487 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 3488 #define VIDFREQ2 _MMIO(0x11114) 3489 #define VIDFREQ3 _MMIO(0x11118) 3490 #define VIDFREQ4 _MMIO(0x1111c) 3491 #define VIDFREQ_P0_MASK 0x1f000000 3492 #define VIDFREQ_P0_SHIFT 24 3493 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 3494 #define VIDFREQ_P0_CSCLK_SHIFT 20 3495 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 3496 #define VIDFREQ_P0_CRCLK_SHIFT 16 3497 #define VIDFREQ_P1_MASK 0x00001f00 3498 #define VIDFREQ_P1_SHIFT 8 3499 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 3500 #define VIDFREQ_P1_CSCLK_SHIFT 4 3501 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 3502 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 3503 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 3504 #define INTTOEXT_MAP3_SHIFT 24 3505 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 3506 #define INTTOEXT_MAP2_SHIFT 16 3507 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 3508 #define INTTOEXT_MAP1_SHIFT 8 3509 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 3510 #define INTTOEXT_MAP0_SHIFT 0 3511 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 3512 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 3513 #define MEMCTL_CMD_MASK 0xe000 3514 #define MEMCTL_CMD_SHIFT 13 3515 #define MEMCTL_CMD_RCLK_OFF 0 3516 #define MEMCTL_CMD_RCLK_ON 1 3517 #define MEMCTL_CMD_CHFREQ 2 3518 #define MEMCTL_CMD_CHVID 3 3519 #define MEMCTL_CMD_VMMOFF 4 3520 #define MEMCTL_CMD_VMMON 5 3521 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 3522 when command complete */ 3523 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 3524 #define MEMCTL_FREQ_SHIFT 8 3525 #define MEMCTL_SFCAVM (1<<7) 3526 #define MEMCTL_TGT_VID_MASK 0x007f 3527 #define MEMIHYST _MMIO(0x1117c) 3528 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 3529 #define MEMINT_RSEXIT_EN (1<<8) 3530 #define MEMINT_CX_SUPR_EN (1<<7) 3531 #define MEMINT_CONT_BUSY_EN (1<<6) 3532 #define MEMINT_AVG_BUSY_EN (1<<5) 3533 #define MEMINT_EVAL_CHG_EN (1<<4) 3534 #define MEMINT_MON_IDLE_EN (1<<3) 3535 #define MEMINT_UP_EVAL_EN (1<<2) 3536 #define MEMINT_DOWN_EVAL_EN (1<<1) 3537 #define MEMINT_SW_CMD_EN (1<<0) 3538 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 3539 #define MEM_RSEXIT_MASK 0xc000 3540 #define MEM_RSEXIT_SHIFT 14 3541 #define MEM_CONT_BUSY_MASK 0x3000 3542 #define MEM_CONT_BUSY_SHIFT 12 3543 #define MEM_AVG_BUSY_MASK 0x0c00 3544 #define MEM_AVG_BUSY_SHIFT 10 3545 #define MEM_EVAL_CHG_MASK 0x0300 3546 #define MEM_EVAL_BUSY_SHIFT 8 3547 #define MEM_MON_IDLE_MASK 0x00c0 3548 #define MEM_MON_IDLE_SHIFT 6 3549 #define MEM_UP_EVAL_MASK 0x0030 3550 #define MEM_UP_EVAL_SHIFT 4 3551 #define MEM_DOWN_EVAL_MASK 0x000c 3552 #define MEM_DOWN_EVAL_SHIFT 2 3553 #define MEM_SW_CMD_MASK 0x0003 3554 #define MEM_INT_STEER_GFX 0 3555 #define MEM_INT_STEER_CMR 1 3556 #define MEM_INT_STEER_SMI 2 3557 #define MEM_INT_STEER_SCI 3 3558 #define MEMINTRSTS _MMIO(0x11184) 3559 #define MEMINT_RSEXIT (1<<7) 3560 #define MEMINT_CONT_BUSY (1<<6) 3561 #define MEMINT_AVG_BUSY (1<<5) 3562 #define MEMINT_EVAL_CHG (1<<4) 3563 #define MEMINT_MON_IDLE (1<<3) 3564 #define MEMINT_UP_EVAL (1<<2) 3565 #define MEMINT_DOWN_EVAL (1<<1) 3566 #define MEMINT_SW_CMD (1<<0) 3567 #define MEMMODECTL _MMIO(0x11190) 3568 #define MEMMODE_BOOST_EN (1<<31) 3569 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 3570 #define MEMMODE_BOOST_FREQ_SHIFT 24 3571 #define MEMMODE_IDLE_MODE_MASK 0x00030000 3572 #define MEMMODE_IDLE_MODE_SHIFT 16 3573 #define MEMMODE_IDLE_MODE_EVAL 0 3574 #define MEMMODE_IDLE_MODE_CONT 1 3575 #define MEMMODE_HWIDLE_EN (1<<15) 3576 #define MEMMODE_SWMODE_EN (1<<14) 3577 #define MEMMODE_RCLK_GATE (1<<13) 3578 #define MEMMODE_HW_UPDATE (1<<12) 3579 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 3580 #define MEMMODE_FSTART_SHIFT 8 3581 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 3582 #define MEMMODE_FMAX_SHIFT 4 3583 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 3584 #define RCBMAXAVG _MMIO(0x1119c) 3585 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 3586 #define SWMEMCMD_RENDER_OFF (0 << 13) 3587 #define SWMEMCMD_RENDER_ON (1 << 13) 3588 #define SWMEMCMD_SWFREQ (2 << 13) 3589 #define SWMEMCMD_TARVID (3 << 13) 3590 #define SWMEMCMD_VRM_OFF (4 << 13) 3591 #define SWMEMCMD_VRM_ON (5 << 13) 3592 #define CMDSTS (1<<12) 3593 #define SFCAVM (1<<11) 3594 #define SWFREQ_MASK 0x0380 /* P0-7 */ 3595 #define SWFREQ_SHIFT 7 3596 #define TARVID_MASK 0x001f 3597 #define MEMSTAT_CTG _MMIO(0x111a0) 3598 #define RCBMINAVG _MMIO(0x111a0) 3599 #define RCUPEI _MMIO(0x111b0) 3600 #define RCDNEI _MMIO(0x111b4) 3601 #define RSTDBYCTL _MMIO(0x111b8) 3602 #define RS1EN (1<<31) 3603 #define RS2EN (1<<30) 3604 #define RS3EN (1<<29) 3605 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 3606 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 3607 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 3608 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 3609 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 3610 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 3611 #define RSX_STATUS_MASK (7<<20) 3612 #define RSX_STATUS_ON (0<<20) 3613 #define RSX_STATUS_RC1 (1<<20) 3614 #define RSX_STATUS_RC1E (2<<20) 3615 #define RSX_STATUS_RS1 (3<<20) 3616 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 3617 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 3618 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 3619 #define RSX_STATUS_RSVD2 (7<<20) 3620 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 3621 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 3622 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 3623 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 3624 #define RS1CONTSAV_MASK (3<<14) 3625 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 3626 #define RS1CONTSAV_RSVD (1<<14) 3627 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 3628 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 3629 #define NORMSLEXLAT_MASK (3<<12) 3630 #define SLOW_RS123 (0<<12) 3631 #define SLOW_RS23 (1<<12) 3632 #define SLOW_RS3 (2<<12) 3633 #define NORMAL_RS123 (3<<12) 3634 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 3635 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 3636 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 3637 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 3638 #define RS_CSTATE_MASK (3<<4) 3639 #define RS_CSTATE_C367_RS1 (0<<4) 3640 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 3641 #define RS_CSTATE_RSVD (2<<4) 3642 #define RS_CSTATE_C367_RS2 (3<<4) 3643 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 3644 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 3645 #define VIDCTL _MMIO(0x111c0) 3646 #define VIDSTS _MMIO(0x111c8) 3647 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 3648 #define MEMSTAT_ILK _MMIO(0x111f8) 3649 #define MEMSTAT_VID_MASK 0x7f00 3650 #define MEMSTAT_VID_SHIFT 8 3651 #define MEMSTAT_PSTATE_MASK 0x00f8 3652 #define MEMSTAT_PSTATE_SHIFT 3 3653 #define MEMSTAT_MON_ACTV (1<<2) 3654 #define MEMSTAT_SRC_CTL_MASK 0x0003 3655 #define MEMSTAT_SRC_CTL_CORE 0 3656 #define MEMSTAT_SRC_CTL_TRB 1 3657 #define MEMSTAT_SRC_CTL_THM 2 3658 #define MEMSTAT_SRC_CTL_STDBY 3 3659 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 3660 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 3661 #define PMMISC _MMIO(0x11214) 3662 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 3663 #define SDEW _MMIO(0x1124c) 3664 #define CSIEW0 _MMIO(0x11250) 3665 #define CSIEW1 _MMIO(0x11254) 3666 #define CSIEW2 _MMIO(0x11258) 3667 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 3668 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 3669 #define MCHAFE _MMIO(0x112c0) 3670 #define CSIEC _MMIO(0x112e0) 3671 #define DMIEC _MMIO(0x112e4) 3672 #define DDREC _MMIO(0x112e8) 3673 #define PEG0EC _MMIO(0x112ec) 3674 #define PEG1EC _MMIO(0x112f0) 3675 #define GFXEC _MMIO(0x112f4) 3676 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 3677 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 3678 #define ECR _MMIO(0x11600) 3679 #define ECR_GPFE (1<<31) 3680 #define ECR_IMONE (1<<30) 3681 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 3682 #define OGW0 _MMIO(0x11608) 3683 #define OGW1 _MMIO(0x1160c) 3684 #define EG0 _MMIO(0x11610) 3685 #define EG1 _MMIO(0x11614) 3686 #define EG2 _MMIO(0x11618) 3687 #define EG3 _MMIO(0x1161c) 3688 #define EG4 _MMIO(0x11620) 3689 #define EG5 _MMIO(0x11624) 3690 #define EG6 _MMIO(0x11628) 3691 #define EG7 _MMIO(0x1162c) 3692 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 3693 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 3694 #define LCFUSE02 _MMIO(0x116c0) 3695 #define LCFUSE_HIV_MASK 0x000000ff 3696 #define CSIPLL0 _MMIO(0x12c10) 3697 #define DDRMPLL1 _MMIO(0X12c20) 3698 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 3699 3700 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 3701 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 3702 3703 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 3704 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 3705 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 3706 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 3707 #define BXT_RP_STATE_CAP _MMIO(0x138170) 3708 3709 /* 3710 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS 3711 * 8300) freezing up around GPU hangs. Looks as if even 3712 * scheduling/timer interrupts start misbehaving if the RPS 3713 * EI/thresholds are "bad", leading to a very sluggish or even 3714 * frozen machine. 3715 */ 3716 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) 3717 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 3718 #define INTERVAL_0_833_US(us) (((us) * 6) / 5) 3719 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ 3720 (IS_GEN9_LP(dev_priv) ? \ 3721 INTERVAL_0_833_US(us) : \ 3722 INTERVAL_1_33_US(us)) : \ 3723 INTERVAL_1_28_US(us)) 3724 3725 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) 3726 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) 3727 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) 3728 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ 3729 (IS_GEN9_LP(dev_priv) ? \ 3730 INTERVAL_0_833_TO_US(interval) : \ 3731 INTERVAL_1_33_TO_US(interval)) : \ 3732 INTERVAL_1_28_TO_US(interval)) 3733 3734 /* 3735 * Logical Context regs 3736 */ 3737 #define CCID _MMIO(0x2180) 3738 #define CCID_EN BIT(0) 3739 #define CCID_EXTENDED_STATE_RESTORE BIT(2) 3740 #define CCID_EXTENDED_STATE_SAVE BIT(3) 3741 /* 3742 * Notes on SNB/IVB/VLV context size: 3743 * - Power context is saved elsewhere (LLC or stolen) 3744 * - Ring/execlist context is saved on SNB, not on IVB 3745 * - Extended context size already includes render context size 3746 * - We always need to follow the extended context size. 3747 * SNB BSpec has comments indicating that we should use the 3748 * render context size instead if execlists are disabled, but 3749 * based on empirical testing that's just nonsense. 3750 * - Pipelined/VF state is saved on SNB/IVB respectively 3751 * - GT1 size just indicates how much of render context 3752 * doesn't need saving on GT1 3753 */ 3754 #define CXT_SIZE _MMIO(0x21a0) 3755 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 3756 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 3757 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 3758 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 3759 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 3760 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 3761 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 3762 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 3763 #define GEN7_CXT_SIZE _MMIO(0x21a8) 3764 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 3765 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 3766 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 3767 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 3768 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 3769 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 3770 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 3771 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 3772 3773 enum { 3774 INTEL_ADVANCED_CONTEXT = 0, 3775 INTEL_LEGACY_32B_CONTEXT, 3776 INTEL_ADVANCED_AD_CONTEXT, 3777 INTEL_LEGACY_64B_CONTEXT 3778 }; 3779 3780 enum { 3781 FAULT_AND_HANG = 0, 3782 FAULT_AND_HALT, /* Debug only */ 3783 FAULT_AND_STREAM, 3784 FAULT_AND_CONTINUE /* Unsupported */ 3785 }; 3786 3787 #define GEN8_CTX_VALID (1<<0) 3788 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) 3789 #define GEN8_CTX_FORCE_RESTORE (1<<2) 3790 #define GEN8_CTX_L3LLC_COHERENT (1<<5) 3791 #define GEN8_CTX_PRIVILEGE (1<<8) 3792 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 3793 3794 #define GEN8_CTX_ID_SHIFT 32 3795 #define GEN8_CTX_ID_WIDTH 21 3796 3797 #define CHV_CLK_CTL1 _MMIO(0x101100) 3798 #define VLV_CLK_CTL2 _MMIO(0x101104) 3799 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 3800 3801 /* 3802 * Overlay regs 3803 */ 3804 3805 #define OVADD _MMIO(0x30000) 3806 #define DOVSTA _MMIO(0x30008) 3807 #define OC_BUF (0x3<<20) 3808 #define OGAMC5 _MMIO(0x30010) 3809 #define OGAMC4 _MMIO(0x30014) 3810 #define OGAMC3 _MMIO(0x30018) 3811 #define OGAMC2 _MMIO(0x3001c) 3812 #define OGAMC1 _MMIO(0x30020) 3813 #define OGAMC0 _MMIO(0x30024) 3814 3815 /* 3816 * GEN9 clock gating regs 3817 */ 3818 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 3819 #define PWM2_GATING_DIS (1 << 14) 3820 #define PWM1_GATING_DIS (1 << 13) 3821 3822 #define _CLKGATE_DIS_PSL_A 0x46520 3823 #define _CLKGATE_DIS_PSL_B 0x46524 3824 #define _CLKGATE_DIS_PSL_C 0x46528 3825 #define DPF_GATING_DIS (1 << 10) 3826 #define DPF_RAM_GATING_DIS (1 << 9) 3827 #define DPFR_GATING_DIS (1 << 8) 3828 3829 #define CLKGATE_DIS_PSL(pipe) \ 3830 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 3831 3832 /* 3833 * GEN10 clock gating regs 3834 */ 3835 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 3836 #define SARBUNIT_CLKGATE_DIS (1 << 5) 3837 3838 /* 3839 * Display engine regs 3840 */ 3841 3842 /* Pipe A CRC regs */ 3843 #define _PIPE_CRC_CTL_A 0x60050 3844 #define PIPE_CRC_ENABLE (1 << 31) 3845 /* ivb+ source selection */ 3846 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 3847 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 3848 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 3849 /* ilk+ source selection */ 3850 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 3851 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 3852 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 3853 /* embedded DP port on the north display block, reserved on ivb */ 3854 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 3855 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 3856 /* vlv source selection */ 3857 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 3858 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 3859 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 3860 /* with DP port the pipe source is invalid */ 3861 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 3862 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 3863 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 3864 /* gen3+ source selection */ 3865 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 3866 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 3867 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 3868 /* with DP/TV port the pipe source is invalid */ 3869 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 3870 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 3871 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 3872 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 3873 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 3874 /* gen2 doesn't have source selection bits */ 3875 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 3876 3877 #define _PIPE_CRC_RES_1_A_IVB 0x60064 3878 #define _PIPE_CRC_RES_2_A_IVB 0x60068 3879 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 3880 #define _PIPE_CRC_RES_4_A_IVB 0x60070 3881 #define _PIPE_CRC_RES_5_A_IVB 0x60074 3882 3883 #define _PIPE_CRC_RES_RED_A 0x60060 3884 #define _PIPE_CRC_RES_GREEN_A 0x60064 3885 #define _PIPE_CRC_RES_BLUE_A 0x60068 3886 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 3887 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 3888 3889 /* Pipe B CRC regs */ 3890 #define _PIPE_CRC_RES_1_B_IVB 0x61064 3891 #define _PIPE_CRC_RES_2_B_IVB 0x61068 3892 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 3893 #define _PIPE_CRC_RES_4_B_IVB 0x61070 3894 #define _PIPE_CRC_RES_5_B_IVB 0x61074 3895 3896 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 3897 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 3898 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 3899 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 3900 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 3901 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 3902 3903 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 3904 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 3905 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 3906 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 3907 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 3908 3909 /* Pipe A timing regs */ 3910 #define _HTOTAL_A 0x60000 3911 #define _HBLANK_A 0x60004 3912 #define _HSYNC_A 0x60008 3913 #define _VTOTAL_A 0x6000c 3914 #define _VBLANK_A 0x60010 3915 #define _VSYNC_A 0x60014 3916 #define _PIPEASRC 0x6001c 3917 #define _BCLRPAT_A 0x60020 3918 #define _VSYNCSHIFT_A 0x60028 3919 #define _PIPE_MULT_A 0x6002c 3920 3921 /* Pipe B timing regs */ 3922 #define _HTOTAL_B 0x61000 3923 #define _HBLANK_B 0x61004 3924 #define _HSYNC_B 0x61008 3925 #define _VTOTAL_B 0x6100c 3926 #define _VBLANK_B 0x61010 3927 #define _VSYNC_B 0x61014 3928 #define _PIPEBSRC 0x6101c 3929 #define _BCLRPAT_B 0x61020 3930 #define _VSYNCSHIFT_B 0x61028 3931 #define _PIPE_MULT_B 0x6102c 3932 3933 #define TRANSCODER_A_OFFSET 0x60000 3934 #define TRANSCODER_B_OFFSET 0x61000 3935 #define TRANSCODER_C_OFFSET 0x62000 3936 #define CHV_TRANSCODER_C_OFFSET 0x63000 3937 #define TRANSCODER_EDP_OFFSET 0x6f000 3938 3939 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ 3940 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 3941 dev_priv->info.display_mmio_offset) 3942 3943 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 3944 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 3945 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 3946 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 3947 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 3948 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 3949 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 3950 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 3951 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 3952 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 3953 3954 /* VLV eDP PSR registers */ 3955 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) 3956 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) 3957 #define VLV_EDP_PSR_ENABLE (1<<0) 3958 #define VLV_EDP_PSR_RESET (1<<1) 3959 #define VLV_EDP_PSR_MODE_MASK (7<<2) 3960 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) 3961 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) 3962 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) 3963 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) 3964 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) 3965 #define VLV_EDP_PSR_DBL_FRAME (1<<10) 3966 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) 3967 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 3968 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB) 3969 3970 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) 3971 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) 3972 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) 3973 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) 3974 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) 3975 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB) 3976 3977 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) 3978 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) 3979 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) 3980 #define VLV_EDP_PSR_CURR_STATE_MASK 7 3981 #define VLV_EDP_PSR_DISABLED (0<<0) 3982 #define VLV_EDP_PSR_INACTIVE (1<<0) 3983 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) 3984 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) 3985 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) 3986 #define VLV_EDP_PSR_EXIT (5<<0) 3987 #define VLV_EDP_PSR_IN_TRANS (1<<7) 3988 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) 3989 3990 /* HSW+ eDP PSR registers */ 3991 #define HSW_EDP_PSR_BASE 0x64800 3992 #define BDW_EDP_PSR_BASE 0x6f800 3993 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) 3994 #define EDP_PSR_ENABLE (1<<31) 3995 #define BDW_PSR_SINGLE_FRAME (1<<30) 3996 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */ 3997 #define EDP_PSR_LINK_STANDBY (1<<27) 3998 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 3999 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 4000 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 4001 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 4002 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 4003 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 4004 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 4005 #define EDP_PSR_TP1_TP2_SEL (0<<11) 4006 #define EDP_PSR_TP1_TP3_SEL (1<<11) 4007 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 4008 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 4009 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 4010 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 4011 #define EDP_PSR_TP1_TIME_500us (0<<4) 4012 #define EDP_PSR_TP1_TIME_100us (1<<4) 4013 #define EDP_PSR_TP1_TIME_2500us (2<<4) 4014 #define EDP_PSR_TP1_TIME_0us (3<<4) 4015 #define EDP_PSR_IDLE_FRAME_SHIFT 0 4016 4017 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 4018 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ 4019 4020 #define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40) 4021 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 4022 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 4023 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 4024 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 4025 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 4026 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 4027 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 4028 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 4029 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 4030 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 4031 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 4032 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 4033 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 4034 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 4035 #define EDP_PSR_STATUS_COUNT_SHIFT 16 4036 #define EDP_PSR_STATUS_COUNT_MASK 0xf 4037 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 4038 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 4039 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 4040 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 4041 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 4042 #define EDP_PSR_STATUS_IDLE_MASK 0xf 4043 4044 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) 4045 #define EDP_PSR_PERF_CNT_MASK 0xffffff 4046 4047 #define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60) 4048 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28) 4049 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 4050 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 4051 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 4052 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16) 4053 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15) 4054 4055 #define EDP_PSR2_CTL _MMIO(0x6f900) 4056 #define EDP_PSR2_ENABLE (1<<31) 4057 #define EDP_SU_TRACK_ENABLE (1<<30) 4058 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) 4059 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) 4060 #define EDP_PSR2_TP2_TIME_500 (0<<8) 4061 #define EDP_PSR2_TP2_TIME_100 (1<<8) 4062 #define EDP_PSR2_TP2_TIME_2500 (2<<8) 4063 #define EDP_PSR2_TP2_TIME_50 (3<<8) 4064 #define EDP_PSR2_TP2_TIME_MASK (3<<8) 4065 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 4066 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) 4067 #define EDP_PSR2_IDLE_MASK 0xf 4068 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4) 4069 4070 #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) 4071 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) 4072 #define EDP_PSR2_STATUS_STATE_SHIFT 28 4073 4074 /* VGA port control */ 4075 #define ADPA _MMIO(0x61100) 4076 #define PCH_ADPA _MMIO(0xe1100) 4077 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 4078 4079 #define ADPA_DAC_ENABLE (1<<31) 4080 #define ADPA_DAC_DISABLE 0 4081 #define ADPA_PIPE_SELECT_MASK (1<<30) 4082 #define ADPA_PIPE_A_SELECT 0 4083 #define ADPA_PIPE_B_SELECT (1<<30) 4084 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 4085 /* CPT uses bits 29:30 for pch transcoder select */ 4086 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 4087 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 4088 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 4089 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 4090 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 4091 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 4092 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 4093 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 4094 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 4095 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 4096 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 4097 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 4098 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 4099 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 4100 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 4101 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 4102 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 4103 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 4104 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 4105 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 4106 #define ADPA_SETS_HVPOLARITY 0 4107 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 4108 #define ADPA_VSYNC_CNTL_ENABLE 0 4109 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 4110 #define ADPA_HSYNC_CNTL_ENABLE 0 4111 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 4112 #define ADPA_VSYNC_ACTIVE_LOW 0 4113 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 4114 #define ADPA_HSYNC_ACTIVE_LOW 0 4115 #define ADPA_DPMS_MASK (~(3<<10)) 4116 #define ADPA_DPMS_ON (0<<10) 4117 #define ADPA_DPMS_SUSPEND (1<<10) 4118 #define ADPA_DPMS_STANDBY (2<<10) 4119 #define ADPA_DPMS_OFF (3<<10) 4120 4121 4122 /* Hotplug control (945+ only) */ 4123 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) 4124 #define PORTB_HOTPLUG_INT_EN (1 << 29) 4125 #define PORTC_HOTPLUG_INT_EN (1 << 28) 4126 #define PORTD_HOTPLUG_INT_EN (1 << 27) 4127 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 4128 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 4129 #define TV_HOTPLUG_INT_EN (1 << 18) 4130 #define CRT_HOTPLUG_INT_EN (1 << 9) 4131 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 4132 PORTC_HOTPLUG_INT_EN | \ 4133 PORTD_HOTPLUG_INT_EN | \ 4134 SDVOC_HOTPLUG_INT_EN | \ 4135 SDVOB_HOTPLUG_INT_EN | \ 4136 CRT_HOTPLUG_INT_EN) 4137 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 4138 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 4139 /* must use period 64 on GM45 according to docs */ 4140 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 4141 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 4142 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 4143 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 4144 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 4145 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 4146 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 4147 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 4148 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 4149 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 4150 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 4151 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 4152 4153 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) 4154 /* 4155 * HDMI/DP bits are g4x+ 4156 * 4157 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 4158 * Please check the detailed lore in the commit message for for experimental 4159 * evidence. 4160 */ 4161 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 4162 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 4163 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 4164 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 4165 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 4166 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 4167 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 4168 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 4169 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 4170 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 4171 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 4172 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 4173 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 4174 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 4175 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 4176 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 4177 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 4178 /* CRT/TV common between gen3+ */ 4179 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 4180 #define TV_HOTPLUG_INT_STATUS (1 << 10) 4181 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 4182 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 4183 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 4184 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 4185 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 4186 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 4187 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 4188 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 4189 4190 /* SDVO is different across gen3/4 */ 4191 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 4192 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 4193 /* 4194 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 4195 * since reality corrobates that they're the same as on gen3. But keep these 4196 * bits here (and the comment!) to help any other lost wanderers back onto the 4197 * right tracks. 4198 */ 4199 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 4200 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 4201 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 4202 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 4203 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 4204 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 4205 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 4206 PORTB_HOTPLUG_INT_STATUS | \ 4207 PORTC_HOTPLUG_INT_STATUS | \ 4208 PORTD_HOTPLUG_INT_STATUS) 4209 4210 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 4211 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 4212 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 4213 PORTB_HOTPLUG_INT_STATUS | \ 4214 PORTC_HOTPLUG_INT_STATUS | \ 4215 PORTD_HOTPLUG_INT_STATUS) 4216 4217 /* SDVO and HDMI port control. 4218 * The same register may be used for SDVO or HDMI */ 4219 #define _GEN3_SDVOB 0x61140 4220 #define _GEN3_SDVOC 0x61160 4221 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 4222 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 4223 #define GEN4_HDMIB GEN3_SDVOB 4224 #define GEN4_HDMIC GEN3_SDVOC 4225 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 4226 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 4227 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 4228 #define PCH_SDVOB _MMIO(0xe1140) 4229 #define PCH_HDMIB PCH_SDVOB 4230 #define PCH_HDMIC _MMIO(0xe1150) 4231 #define PCH_HDMID _MMIO(0xe1160) 4232 4233 #define PORT_DFT_I9XX _MMIO(0x61150) 4234 #define DC_BALANCE_RESET (1 << 25) 4235 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) 4236 #define DC_BALANCE_RESET_VLV (1 << 31) 4237 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 4238 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 4239 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 4240 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 4241 4242 /* Gen 3 SDVO bits: */ 4243 #define SDVO_ENABLE (1 << 31) 4244 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 4245 #define SDVO_PIPE_SEL_MASK (1 << 30) 4246 #define SDVO_PIPE_B_SELECT (1 << 30) 4247 #define SDVO_STALL_SELECT (1 << 29) 4248 #define SDVO_INTERRUPT_ENABLE (1 << 26) 4249 /* 4250 * 915G/GM SDVO pixel multiplier. 4251 * Programmed value is multiplier - 1, up to 5x. 4252 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 4253 */ 4254 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 4255 #define SDVO_PORT_MULTIPLY_SHIFT 23 4256 #define SDVO_PHASE_SELECT_MASK (15 << 19) 4257 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 4258 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 4259 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 4260 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 4261 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 4262 #define SDVO_DETECTED (1 << 2) 4263 /* Bits to be preserved when writing */ 4264 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 4265 SDVO_INTERRUPT_ENABLE) 4266 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 4267 4268 /* Gen 4 SDVO/HDMI bits: */ 4269 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 4270 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 4271 #define SDVO_ENCODING_SDVO (0 << 10) 4272 #define SDVO_ENCODING_HDMI (2 << 10) 4273 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 4274 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 4275 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 4276 #define SDVO_AUDIO_ENABLE (1 << 6) 4277 /* VSYNC/HSYNC bits new with 965, default is to be set */ 4278 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 4279 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 4280 4281 /* Gen 5 (IBX) SDVO/HDMI bits: */ 4282 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 4283 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 4284 4285 /* Gen 6 (CPT) SDVO/HDMI bits: */ 4286 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4287 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 4288 4289 /* CHV SDVO/HDMI bits: */ 4290 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 4291 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 4292 4293 4294 /* DVO port control */ 4295 #define _DVOA 0x61120 4296 #define DVOA _MMIO(_DVOA) 4297 #define _DVOB 0x61140 4298 #define DVOB _MMIO(_DVOB) 4299 #define _DVOC 0x61160 4300 #define DVOC _MMIO(_DVOC) 4301 #define DVO_ENABLE (1 << 31) 4302 #define DVO_PIPE_B_SELECT (1 << 30) 4303 #define DVO_PIPE_STALL_UNUSED (0 << 28) 4304 #define DVO_PIPE_STALL (1 << 28) 4305 #define DVO_PIPE_STALL_TV (2 << 28) 4306 #define DVO_PIPE_STALL_MASK (3 << 28) 4307 #define DVO_USE_VGA_SYNC (1 << 15) 4308 #define DVO_DATA_ORDER_I740 (0 << 14) 4309 #define DVO_DATA_ORDER_FP (1 << 14) 4310 #define DVO_VSYNC_DISABLE (1 << 11) 4311 #define DVO_HSYNC_DISABLE (1 << 10) 4312 #define DVO_VSYNC_TRISTATE (1 << 9) 4313 #define DVO_HSYNC_TRISTATE (1 << 8) 4314 #define DVO_BORDER_ENABLE (1 << 7) 4315 #define DVO_DATA_ORDER_GBRG (1 << 6) 4316 #define DVO_DATA_ORDER_RGGB (0 << 6) 4317 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 4318 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 4319 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 4320 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 4321 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 4322 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 4323 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 4324 #define DVO_PRESERVE_MASK (0x7<<24) 4325 #define DVOA_SRCDIM _MMIO(0x61124) 4326 #define DVOB_SRCDIM _MMIO(0x61144) 4327 #define DVOC_SRCDIM _MMIO(0x61164) 4328 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 4329 #define DVO_SRCDIM_VERTICAL_SHIFT 0 4330 4331 /* LVDS port control */ 4332 #define LVDS _MMIO(0x61180) 4333 /* 4334 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 4335 * the DPLL semantics change when the LVDS is assigned to that pipe. 4336 */ 4337 #define LVDS_PORT_EN (1 << 31) 4338 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 4339 #define LVDS_PIPEB_SELECT (1 << 30) 4340 #define LVDS_PIPE_MASK (1 << 30) 4341 #define LVDS_PIPE(pipe) ((pipe) << 30) 4342 /* LVDS dithering flag on 965/g4x platform */ 4343 #define LVDS_ENABLE_DITHER (1 << 25) 4344 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 4345 #define LVDS_VSYNC_POLARITY (1 << 21) 4346 #define LVDS_HSYNC_POLARITY (1 << 20) 4347 4348 /* Enable border for unscaled (or aspect-scaled) display */ 4349 #define LVDS_BORDER_ENABLE (1 << 15) 4350 /* 4351 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 4352 * pixel. 4353 */ 4354 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 4355 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 4356 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 4357 /* 4358 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 4359 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 4360 * on. 4361 */ 4362 #define LVDS_A3_POWER_MASK (3 << 6) 4363 #define LVDS_A3_POWER_DOWN (0 << 6) 4364 #define LVDS_A3_POWER_UP (3 << 6) 4365 /* 4366 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 4367 * is set. 4368 */ 4369 #define LVDS_CLKB_POWER_MASK (3 << 4) 4370 #define LVDS_CLKB_POWER_DOWN (0 << 4) 4371 #define LVDS_CLKB_POWER_UP (3 << 4) 4372 /* 4373 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 4374 * setting for whether we are in dual-channel mode. The B3 pair will 4375 * additionally only be powered up when LVDS_A3_POWER_UP is set. 4376 */ 4377 #define LVDS_B0B3_POWER_MASK (3 << 2) 4378 #define LVDS_B0B3_POWER_DOWN (0 << 2) 4379 #define LVDS_B0B3_POWER_UP (3 << 2) 4380 4381 /* Video Data Island Packet control */ 4382 #define VIDEO_DIP_DATA _MMIO(0x61178) 4383 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 4384 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 4385 * of the infoframe structure specified by CEA-861. */ 4386 #define VIDEO_DIP_DATA_SIZE 32 4387 #define VIDEO_DIP_VSC_DATA_SIZE 36 4388 #define VIDEO_DIP_CTL _MMIO(0x61170) 4389 /* Pre HSW: */ 4390 #define VIDEO_DIP_ENABLE (1 << 31) 4391 #define VIDEO_DIP_PORT(port) ((port) << 29) 4392 #define VIDEO_DIP_PORT_MASK (3 << 29) 4393 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 4394 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 4395 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 4396 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 4397 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 4398 #define VIDEO_DIP_SELECT_AVI (0 << 19) 4399 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 4400 #define VIDEO_DIP_SELECT_SPD (3 << 19) 4401 #define VIDEO_DIP_SELECT_MASK (3 << 19) 4402 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 4403 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 4404 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4405 #define VIDEO_DIP_FREQ_MASK (3 << 16) 4406 /* HSW and later: */ 4407 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4408 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4409 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4410 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 4411 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4412 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4413 4414 /* Panel power sequencing */ 4415 #define PPS_BASE 0x61200 4416 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4417 #define PCH_PPS_BASE 0xC7200 4418 4419 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 4420 PPS_BASE + (reg) + \ 4421 (pps_idx) * 0x100) 4422 4423 #define _PP_STATUS 0x61200 4424 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 4425 #define PP_ON (1 << 31) 4426 /* 4427 * Indicates that all dependencies of the panel are on: 4428 * 4429 * - PLL enabled 4430 * - pipe enabled 4431 * - LVDS/DVOB/DVOC on 4432 */ 4433 #define PP_READY (1 << 30) 4434 #define PP_SEQUENCE_NONE (0 << 28) 4435 #define PP_SEQUENCE_POWER_UP (1 << 28) 4436 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 4437 #define PP_SEQUENCE_MASK (3 << 28) 4438 #define PP_SEQUENCE_SHIFT 28 4439 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 4440 #define PP_SEQUENCE_STATE_MASK 0x0000000f 4441 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 4442 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 4443 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 4444 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 4445 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 4446 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 4447 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 4448 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 4449 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 4450 4451 #define _PP_CONTROL 0x61204 4452 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 4453 #define PANEL_UNLOCK_REGS (0xabcd << 16) 4454 #define PANEL_UNLOCK_MASK (0xffff << 16) 4455 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0 4456 #define BXT_POWER_CYCLE_DELAY_SHIFT 4 4457 #define EDP_FORCE_VDD (1 << 3) 4458 #define EDP_BLC_ENABLE (1 << 2) 4459 #define PANEL_POWER_RESET (1 << 1) 4460 #define PANEL_POWER_OFF (0 << 0) 4461 #define PANEL_POWER_ON (1 << 0) 4462 4463 #define _PP_ON_DELAYS 0x61208 4464 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 4465 #define PANEL_PORT_SELECT_SHIFT 30 4466 #define PANEL_PORT_SELECT_MASK (3 << 30) 4467 #define PANEL_PORT_SELECT_LVDS (0 << 30) 4468 #define PANEL_PORT_SELECT_DPA (1 << 30) 4469 #define PANEL_PORT_SELECT_DPC (2 << 30) 4470 #define PANEL_PORT_SELECT_DPD (3 << 30) 4471 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 4472 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000 4473 #define PANEL_POWER_UP_DELAY_SHIFT 16 4474 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff 4475 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 4476 4477 #define _PP_OFF_DELAYS 0x6120C 4478 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 4479 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000 4480 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 4481 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff 4482 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 4483 4484 #define _PP_DIVISOR 0x61210 4485 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 4486 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00 4487 #define PP_REFERENCE_DIVIDER_SHIFT 8 4488 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f 4489 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 4490 4491 /* Panel fitting */ 4492 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) 4493 #define PFIT_ENABLE (1 << 31) 4494 #define PFIT_PIPE_MASK (3 << 29) 4495 #define PFIT_PIPE_SHIFT 29 4496 #define VERT_INTERP_DISABLE (0 << 10) 4497 #define VERT_INTERP_BILINEAR (1 << 10) 4498 #define VERT_INTERP_MASK (3 << 10) 4499 #define VERT_AUTO_SCALE (1 << 9) 4500 #define HORIZ_INTERP_DISABLE (0 << 6) 4501 #define HORIZ_INTERP_BILINEAR (1 << 6) 4502 #define HORIZ_INTERP_MASK (3 << 6) 4503 #define HORIZ_AUTO_SCALE (1 << 5) 4504 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 4505 #define PFIT_FILTER_FUZZY (0 << 24) 4506 #define PFIT_SCALING_AUTO (0 << 26) 4507 #define PFIT_SCALING_PROGRAMMED (1 << 26) 4508 #define PFIT_SCALING_PILLAR (2 << 26) 4509 #define PFIT_SCALING_LETTER (3 << 26) 4510 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) 4511 /* Pre-965 */ 4512 #define PFIT_VERT_SCALE_SHIFT 20 4513 #define PFIT_VERT_SCALE_MASK 0xfff00000 4514 #define PFIT_HORIZ_SCALE_SHIFT 4 4515 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 4516 /* 965+ */ 4517 #define PFIT_VERT_SCALE_SHIFT_965 16 4518 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 4519 #define PFIT_HORIZ_SCALE_SHIFT_965 0 4520 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 4521 4522 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) 4523 4524 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 4525 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 4526 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 4527 _VLV_BLC_PWM_CTL2_B) 4528 4529 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 4530 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 4531 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 4532 _VLV_BLC_PWM_CTL_B) 4533 4534 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 4535 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 4536 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 4537 _VLV_BLC_HIST_CTL_B) 4538 4539 /* Backlight control */ 4540 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 4541 #define BLM_PWM_ENABLE (1 << 31) 4542 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 4543 #define BLM_PIPE_SELECT (1 << 29) 4544 #define BLM_PIPE_SELECT_IVB (3 << 29) 4545 #define BLM_PIPE_A (0 << 29) 4546 #define BLM_PIPE_B (1 << 29) 4547 #define BLM_PIPE_C (2 << 29) /* ivb + */ 4548 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 4549 #define BLM_TRANSCODER_B BLM_PIPE_B 4550 #define BLM_TRANSCODER_C BLM_PIPE_C 4551 #define BLM_TRANSCODER_EDP (3 << 29) 4552 #define BLM_PIPE(pipe) ((pipe) << 29) 4553 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 4554 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 4555 #define BLM_PHASE_IN_ENABLE (1 << 25) 4556 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 4557 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 4558 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 4559 #define BLM_PHASE_IN_COUNT_SHIFT (8) 4560 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 4561 #define BLM_PHASE_IN_INCR_SHIFT (0) 4562 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 4563 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) 4564 /* 4565 * This is the most significant 15 bits of the number of backlight cycles in a 4566 * complete cycle of the modulated backlight control. 4567 * 4568 * The actual value is this field multiplied by two. 4569 */ 4570 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 4571 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 4572 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 4573 /* 4574 * This is the number of cycles out of the backlight modulation cycle for which 4575 * the backlight is on. 4576 * 4577 * This field must be no greater than the number of cycles in the complete 4578 * backlight modulation cycle. 4579 */ 4580 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 4581 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 4582 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 4583 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 4584 4585 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) 4586 #define BLM_HISTOGRAM_ENABLE (1 << 31) 4587 4588 /* New registers for PCH-split platforms. Safe where new bits show up, the 4589 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 4590 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 4591 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 4592 4593 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 4594 4595 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 4596 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 4597 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 4598 #define BLM_PCH_PWM_ENABLE (1 << 31) 4599 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 4600 #define BLM_PCH_POLARITY (1 << 29) 4601 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 4602 4603 #define UTIL_PIN_CTL _MMIO(0x48400) 4604 #define UTIL_PIN_ENABLE (1 << 31) 4605 4606 #define UTIL_PIN_PIPE(x) ((x) << 29) 4607 #define UTIL_PIN_PIPE_MASK (3 << 29) 4608 #define UTIL_PIN_MODE_PWM (1 << 24) 4609 #define UTIL_PIN_MODE_MASK (0xf << 24) 4610 #define UTIL_PIN_POLARITY (1 << 22) 4611 4612 /* BXT backlight register definition. */ 4613 #define _BXT_BLC_PWM_CTL1 0xC8250 4614 #define BXT_BLC_PWM_ENABLE (1 << 31) 4615 #define BXT_BLC_PWM_POLARITY (1 << 29) 4616 #define _BXT_BLC_PWM_FREQ1 0xC8254 4617 #define _BXT_BLC_PWM_DUTY1 0xC8258 4618 4619 #define _BXT_BLC_PWM_CTL2 0xC8350 4620 #define _BXT_BLC_PWM_FREQ2 0xC8354 4621 #define _BXT_BLC_PWM_DUTY2 0xC8358 4622 4623 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 4624 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 4625 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 4626 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 4627 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 4628 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 4629 4630 #define PCH_GTC_CTL _MMIO(0xe7000) 4631 #define PCH_GTC_ENABLE (1 << 31) 4632 4633 /* TV port control */ 4634 #define TV_CTL _MMIO(0x68000) 4635 /* Enables the TV encoder */ 4636 # define TV_ENC_ENABLE (1 << 31) 4637 /* Sources the TV encoder input from pipe B instead of A. */ 4638 # define TV_ENC_PIPEB_SELECT (1 << 30) 4639 /* Outputs composite video (DAC A only) */ 4640 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 4641 /* Outputs SVideo video (DAC B/C) */ 4642 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 4643 /* Outputs Component video (DAC A/B/C) */ 4644 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 4645 /* Outputs Composite and SVideo (DAC A/B/C) */ 4646 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 4647 # define TV_TRILEVEL_SYNC (1 << 21) 4648 /* Enables slow sync generation (945GM only) */ 4649 # define TV_SLOW_SYNC (1 << 20) 4650 /* Selects 4x oversampling for 480i and 576p */ 4651 # define TV_OVERSAMPLE_4X (0 << 18) 4652 /* Selects 2x oversampling for 720p and 1080i */ 4653 # define TV_OVERSAMPLE_2X (1 << 18) 4654 /* Selects no oversampling for 1080p */ 4655 # define TV_OVERSAMPLE_NONE (2 << 18) 4656 /* Selects 8x oversampling */ 4657 # define TV_OVERSAMPLE_8X (3 << 18) 4658 /* Selects progressive mode rather than interlaced */ 4659 # define TV_PROGRESSIVE (1 << 17) 4660 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 4661 # define TV_PAL_BURST (1 << 16) 4662 /* Field for setting delay of Y compared to C */ 4663 # define TV_YC_SKEW_MASK (7 << 12) 4664 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 4665 # define TV_ENC_SDP_FIX (1 << 11) 4666 /* 4667 * Enables a fix for the 915GM only. 4668 * 4669 * Not sure what it does. 4670 */ 4671 # define TV_ENC_C0_FIX (1 << 10) 4672 /* Bits that must be preserved by software */ 4673 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 4674 # define TV_FUSE_STATE_MASK (3 << 4) 4675 /* Read-only state that reports all features enabled */ 4676 # define TV_FUSE_STATE_ENABLED (0 << 4) 4677 /* Read-only state that reports that Macrovision is disabled in hardware*/ 4678 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 4679 /* Read-only state that reports that TV-out is disabled in hardware. */ 4680 # define TV_FUSE_STATE_DISABLED (2 << 4) 4681 /* Normal operation */ 4682 # define TV_TEST_MODE_NORMAL (0 << 0) 4683 /* Encoder test pattern 1 - combo pattern */ 4684 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 4685 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 4686 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 4687 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 4688 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 4689 /* Encoder test pattern 4 - random noise */ 4690 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 4691 /* Encoder test pattern 5 - linear color ramps */ 4692 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 4693 /* 4694 * This test mode forces the DACs to 50% of full output. 4695 * 4696 * This is used for load detection in combination with TVDAC_SENSE_MASK 4697 */ 4698 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 4699 # define TV_TEST_MODE_MASK (7 << 0) 4700 4701 #define TV_DAC _MMIO(0x68004) 4702 # define TV_DAC_SAVE 0x00ffff00 4703 /* 4704 * Reports that DAC state change logic has reported change (RO). 4705 * 4706 * This gets cleared when TV_DAC_STATE_EN is cleared 4707 */ 4708 # define TVDAC_STATE_CHG (1 << 31) 4709 # define TVDAC_SENSE_MASK (7 << 28) 4710 /* Reports that DAC A voltage is above the detect threshold */ 4711 # define TVDAC_A_SENSE (1 << 30) 4712 /* Reports that DAC B voltage is above the detect threshold */ 4713 # define TVDAC_B_SENSE (1 << 29) 4714 /* Reports that DAC C voltage is above the detect threshold */ 4715 # define TVDAC_C_SENSE (1 << 28) 4716 /* 4717 * Enables DAC state detection logic, for load-based TV detection. 4718 * 4719 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 4720 * to off, for load detection to work. 4721 */ 4722 # define TVDAC_STATE_CHG_EN (1 << 27) 4723 /* Sets the DAC A sense value to high */ 4724 # define TVDAC_A_SENSE_CTL (1 << 26) 4725 /* Sets the DAC B sense value to high */ 4726 # define TVDAC_B_SENSE_CTL (1 << 25) 4727 /* Sets the DAC C sense value to high */ 4728 # define TVDAC_C_SENSE_CTL (1 << 24) 4729 /* Overrides the ENC_ENABLE and DAC voltage levels */ 4730 # define DAC_CTL_OVERRIDE (1 << 7) 4731 /* Sets the slew rate. Must be preserved in software */ 4732 # define ENC_TVDAC_SLEW_FAST (1 << 6) 4733 # define DAC_A_1_3_V (0 << 4) 4734 # define DAC_A_1_1_V (1 << 4) 4735 # define DAC_A_0_7_V (2 << 4) 4736 # define DAC_A_MASK (3 << 4) 4737 # define DAC_B_1_3_V (0 << 2) 4738 # define DAC_B_1_1_V (1 << 2) 4739 # define DAC_B_0_7_V (2 << 2) 4740 # define DAC_B_MASK (3 << 2) 4741 # define DAC_C_1_3_V (0 << 0) 4742 # define DAC_C_1_1_V (1 << 0) 4743 # define DAC_C_0_7_V (2 << 0) 4744 # define DAC_C_MASK (3 << 0) 4745 4746 /* 4747 * CSC coefficients are stored in a floating point format with 9 bits of 4748 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 4749 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 4750 * -1 (0x3) being the only legal negative value. 4751 */ 4752 #define TV_CSC_Y _MMIO(0x68010) 4753 # define TV_RY_MASK 0x07ff0000 4754 # define TV_RY_SHIFT 16 4755 # define TV_GY_MASK 0x00000fff 4756 # define TV_GY_SHIFT 0 4757 4758 #define TV_CSC_Y2 _MMIO(0x68014) 4759 # define TV_BY_MASK 0x07ff0000 4760 # define TV_BY_SHIFT 16 4761 /* 4762 * Y attenuation for component video. 4763 * 4764 * Stored in 1.9 fixed point. 4765 */ 4766 # define TV_AY_MASK 0x000003ff 4767 # define TV_AY_SHIFT 0 4768 4769 #define TV_CSC_U _MMIO(0x68018) 4770 # define TV_RU_MASK 0x07ff0000 4771 # define TV_RU_SHIFT 16 4772 # define TV_GU_MASK 0x000007ff 4773 # define TV_GU_SHIFT 0 4774 4775 #define TV_CSC_U2 _MMIO(0x6801c) 4776 # define TV_BU_MASK 0x07ff0000 4777 # define TV_BU_SHIFT 16 4778 /* 4779 * U attenuation for component video. 4780 * 4781 * Stored in 1.9 fixed point. 4782 */ 4783 # define TV_AU_MASK 0x000003ff 4784 # define TV_AU_SHIFT 0 4785 4786 #define TV_CSC_V _MMIO(0x68020) 4787 # define TV_RV_MASK 0x0fff0000 4788 # define TV_RV_SHIFT 16 4789 # define TV_GV_MASK 0x000007ff 4790 # define TV_GV_SHIFT 0 4791 4792 #define TV_CSC_V2 _MMIO(0x68024) 4793 # define TV_BV_MASK 0x07ff0000 4794 # define TV_BV_SHIFT 16 4795 /* 4796 * V attenuation for component video. 4797 * 4798 * Stored in 1.9 fixed point. 4799 */ 4800 # define TV_AV_MASK 0x000007ff 4801 # define TV_AV_SHIFT 0 4802 4803 #define TV_CLR_KNOBS _MMIO(0x68028) 4804 /* 2s-complement brightness adjustment */ 4805 # define TV_BRIGHTNESS_MASK 0xff000000 4806 # define TV_BRIGHTNESS_SHIFT 24 4807 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 4808 # define TV_CONTRAST_MASK 0x00ff0000 4809 # define TV_CONTRAST_SHIFT 16 4810 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 4811 # define TV_SATURATION_MASK 0x0000ff00 4812 # define TV_SATURATION_SHIFT 8 4813 /* Hue adjustment, as an integer phase angle in degrees */ 4814 # define TV_HUE_MASK 0x000000ff 4815 # define TV_HUE_SHIFT 0 4816 4817 #define TV_CLR_LEVEL _MMIO(0x6802c) 4818 /* Controls the DAC level for black */ 4819 # define TV_BLACK_LEVEL_MASK 0x01ff0000 4820 # define TV_BLACK_LEVEL_SHIFT 16 4821 /* Controls the DAC level for blanking */ 4822 # define TV_BLANK_LEVEL_MASK 0x000001ff 4823 # define TV_BLANK_LEVEL_SHIFT 0 4824 4825 #define TV_H_CTL_1 _MMIO(0x68030) 4826 /* Number of pixels in the hsync. */ 4827 # define TV_HSYNC_END_MASK 0x1fff0000 4828 # define TV_HSYNC_END_SHIFT 16 4829 /* Total number of pixels minus one in the line (display and blanking). */ 4830 # define TV_HTOTAL_MASK 0x00001fff 4831 # define TV_HTOTAL_SHIFT 0 4832 4833 #define TV_H_CTL_2 _MMIO(0x68034) 4834 /* Enables the colorburst (needed for non-component color) */ 4835 # define TV_BURST_ENA (1 << 31) 4836 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 4837 # define TV_HBURST_START_SHIFT 16 4838 # define TV_HBURST_START_MASK 0x1fff0000 4839 /* Length of the colorburst */ 4840 # define TV_HBURST_LEN_SHIFT 0 4841 # define TV_HBURST_LEN_MASK 0x0001fff 4842 4843 #define TV_H_CTL_3 _MMIO(0x68038) 4844 /* End of hblank, measured in pixels minus one from start of hsync */ 4845 # define TV_HBLANK_END_SHIFT 16 4846 # define TV_HBLANK_END_MASK 0x1fff0000 4847 /* Start of hblank, measured in pixels minus one from start of hsync */ 4848 # define TV_HBLANK_START_SHIFT 0 4849 # define TV_HBLANK_START_MASK 0x0001fff 4850 4851 #define TV_V_CTL_1 _MMIO(0x6803c) 4852 /* XXX */ 4853 # define TV_NBR_END_SHIFT 16 4854 # define TV_NBR_END_MASK 0x07ff0000 4855 /* XXX */ 4856 # define TV_VI_END_F1_SHIFT 8 4857 # define TV_VI_END_F1_MASK 0x00003f00 4858 /* XXX */ 4859 # define TV_VI_END_F2_SHIFT 0 4860 # define TV_VI_END_F2_MASK 0x0000003f 4861 4862 #define TV_V_CTL_2 _MMIO(0x68040) 4863 /* Length of vsync, in half lines */ 4864 # define TV_VSYNC_LEN_MASK 0x07ff0000 4865 # define TV_VSYNC_LEN_SHIFT 16 4866 /* Offset of the start of vsync in field 1, measured in one less than the 4867 * number of half lines. 4868 */ 4869 # define TV_VSYNC_START_F1_MASK 0x00007f00 4870 # define TV_VSYNC_START_F1_SHIFT 8 4871 /* 4872 * Offset of the start of vsync in field 2, measured in one less than the 4873 * number of half lines. 4874 */ 4875 # define TV_VSYNC_START_F2_MASK 0x0000007f 4876 # define TV_VSYNC_START_F2_SHIFT 0 4877 4878 #define TV_V_CTL_3 _MMIO(0x68044) 4879 /* Enables generation of the equalization signal */ 4880 # define TV_EQUAL_ENA (1 << 31) 4881 /* Length of vsync, in half lines */ 4882 # define TV_VEQ_LEN_MASK 0x007f0000 4883 # define TV_VEQ_LEN_SHIFT 16 4884 /* Offset of the start of equalization in field 1, measured in one less than 4885 * the number of half lines. 4886 */ 4887 # define TV_VEQ_START_F1_MASK 0x0007f00 4888 # define TV_VEQ_START_F1_SHIFT 8 4889 /* 4890 * Offset of the start of equalization in field 2, measured in one less than 4891 * the number of half lines. 4892 */ 4893 # define TV_VEQ_START_F2_MASK 0x000007f 4894 # define TV_VEQ_START_F2_SHIFT 0 4895 4896 #define TV_V_CTL_4 _MMIO(0x68048) 4897 /* 4898 * Offset to start of vertical colorburst, measured in one less than the 4899 * number of lines from vertical start. 4900 */ 4901 # define TV_VBURST_START_F1_MASK 0x003f0000 4902 # define TV_VBURST_START_F1_SHIFT 16 4903 /* 4904 * Offset to the end of vertical colorburst, measured in one less than the 4905 * number of lines from the start of NBR. 4906 */ 4907 # define TV_VBURST_END_F1_MASK 0x000000ff 4908 # define TV_VBURST_END_F1_SHIFT 0 4909 4910 #define TV_V_CTL_5 _MMIO(0x6804c) 4911 /* 4912 * Offset to start of vertical colorburst, measured in one less than the 4913 * number of lines from vertical start. 4914 */ 4915 # define TV_VBURST_START_F2_MASK 0x003f0000 4916 # define TV_VBURST_START_F2_SHIFT 16 4917 /* 4918 * Offset to the end of vertical colorburst, measured in one less than the 4919 * number of lines from the start of NBR. 4920 */ 4921 # define TV_VBURST_END_F2_MASK 0x000000ff 4922 # define TV_VBURST_END_F2_SHIFT 0 4923 4924 #define TV_V_CTL_6 _MMIO(0x68050) 4925 /* 4926 * Offset to start of vertical colorburst, measured in one less than the 4927 * number of lines from vertical start. 4928 */ 4929 # define TV_VBURST_START_F3_MASK 0x003f0000 4930 # define TV_VBURST_START_F3_SHIFT 16 4931 /* 4932 * Offset to the end of vertical colorburst, measured in one less than the 4933 * number of lines from the start of NBR. 4934 */ 4935 # define TV_VBURST_END_F3_MASK 0x000000ff 4936 # define TV_VBURST_END_F3_SHIFT 0 4937 4938 #define TV_V_CTL_7 _MMIO(0x68054) 4939 /* 4940 * Offset to start of vertical colorburst, measured in one less than the 4941 * number of lines from vertical start. 4942 */ 4943 # define TV_VBURST_START_F4_MASK 0x003f0000 4944 # define TV_VBURST_START_F4_SHIFT 16 4945 /* 4946 * Offset to the end of vertical colorburst, measured in one less than the 4947 * number of lines from the start of NBR. 4948 */ 4949 # define TV_VBURST_END_F4_MASK 0x000000ff 4950 # define TV_VBURST_END_F4_SHIFT 0 4951 4952 #define TV_SC_CTL_1 _MMIO(0x68060) 4953 /* Turns on the first subcarrier phase generation DDA */ 4954 # define TV_SC_DDA1_EN (1 << 31) 4955 /* Turns on the first subcarrier phase generation DDA */ 4956 # define TV_SC_DDA2_EN (1 << 30) 4957 /* Turns on the first subcarrier phase generation DDA */ 4958 # define TV_SC_DDA3_EN (1 << 29) 4959 /* Sets the subcarrier DDA to reset frequency every other field */ 4960 # define TV_SC_RESET_EVERY_2 (0 << 24) 4961 /* Sets the subcarrier DDA to reset frequency every fourth field */ 4962 # define TV_SC_RESET_EVERY_4 (1 << 24) 4963 /* Sets the subcarrier DDA to reset frequency every eighth field */ 4964 # define TV_SC_RESET_EVERY_8 (2 << 24) 4965 /* Sets the subcarrier DDA to never reset the frequency */ 4966 # define TV_SC_RESET_NEVER (3 << 24) 4967 /* Sets the peak amplitude of the colorburst.*/ 4968 # define TV_BURST_LEVEL_MASK 0x00ff0000 4969 # define TV_BURST_LEVEL_SHIFT 16 4970 /* Sets the increment of the first subcarrier phase generation DDA */ 4971 # define TV_SCDDA1_INC_MASK 0x00000fff 4972 # define TV_SCDDA1_INC_SHIFT 0 4973 4974 #define TV_SC_CTL_2 _MMIO(0x68064) 4975 /* Sets the rollover for the second subcarrier phase generation DDA */ 4976 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 4977 # define TV_SCDDA2_SIZE_SHIFT 16 4978 /* Sets the increent of the second subcarrier phase generation DDA */ 4979 # define TV_SCDDA2_INC_MASK 0x00007fff 4980 # define TV_SCDDA2_INC_SHIFT 0 4981 4982 #define TV_SC_CTL_3 _MMIO(0x68068) 4983 /* Sets the rollover for the third subcarrier phase generation DDA */ 4984 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 4985 # define TV_SCDDA3_SIZE_SHIFT 16 4986 /* Sets the increent of the third subcarrier phase generation DDA */ 4987 # define TV_SCDDA3_INC_MASK 0x00007fff 4988 # define TV_SCDDA3_INC_SHIFT 0 4989 4990 #define TV_WIN_POS _MMIO(0x68070) 4991 /* X coordinate of the display from the start of horizontal active */ 4992 # define TV_XPOS_MASK 0x1fff0000 4993 # define TV_XPOS_SHIFT 16 4994 /* Y coordinate of the display from the start of vertical active (NBR) */ 4995 # define TV_YPOS_MASK 0x00000fff 4996 # define TV_YPOS_SHIFT 0 4997 4998 #define TV_WIN_SIZE _MMIO(0x68074) 4999 /* Horizontal size of the display window, measured in pixels*/ 5000 # define TV_XSIZE_MASK 0x1fff0000 5001 # define TV_XSIZE_SHIFT 16 5002 /* 5003 * Vertical size of the display window, measured in pixels. 5004 * 5005 * Must be even for interlaced modes. 5006 */ 5007 # define TV_YSIZE_MASK 0x00000fff 5008 # define TV_YSIZE_SHIFT 0 5009 5010 #define TV_FILTER_CTL_1 _MMIO(0x68080) 5011 /* 5012 * Enables automatic scaling calculation. 5013 * 5014 * If set, the rest of the registers are ignored, and the calculated values can 5015 * be read back from the register. 5016 */ 5017 # define TV_AUTO_SCALE (1 << 31) 5018 /* 5019 * Disables the vertical filter. 5020 * 5021 * This is required on modes more than 1024 pixels wide */ 5022 # define TV_V_FILTER_BYPASS (1 << 29) 5023 /* Enables adaptive vertical filtering */ 5024 # define TV_VADAPT (1 << 28) 5025 # define TV_VADAPT_MODE_MASK (3 << 26) 5026 /* Selects the least adaptive vertical filtering mode */ 5027 # define TV_VADAPT_MODE_LEAST (0 << 26) 5028 /* Selects the moderately adaptive vertical filtering mode */ 5029 # define TV_VADAPT_MODE_MODERATE (1 << 26) 5030 /* Selects the most adaptive vertical filtering mode */ 5031 # define TV_VADAPT_MODE_MOST (3 << 26) 5032 /* 5033 * Sets the horizontal scaling factor. 5034 * 5035 * This should be the fractional part of the horizontal scaling factor divided 5036 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 5037 * 5038 * (src width - 1) / ((oversample * dest width) - 1) 5039 */ 5040 # define TV_HSCALE_FRAC_MASK 0x00003fff 5041 # define TV_HSCALE_FRAC_SHIFT 0 5042 5043 #define TV_FILTER_CTL_2 _MMIO(0x68084) 5044 /* 5045 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5046 * 5047 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 5048 */ 5049 # define TV_VSCALE_INT_MASK 0x00038000 5050 # define TV_VSCALE_INT_SHIFT 15 5051 /* 5052 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5053 * 5054 * \sa TV_VSCALE_INT_MASK 5055 */ 5056 # define TV_VSCALE_FRAC_MASK 0x00007fff 5057 # define TV_VSCALE_FRAC_SHIFT 0 5058 5059 #define TV_FILTER_CTL_3 _MMIO(0x68088) 5060 /* 5061 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5062 * 5063 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 5064 * 5065 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5066 */ 5067 # define TV_VSCALE_IP_INT_MASK 0x00038000 5068 # define TV_VSCALE_IP_INT_SHIFT 15 5069 /* 5070 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5071 * 5072 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5073 * 5074 * \sa TV_VSCALE_IP_INT_MASK 5075 */ 5076 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 5077 # define TV_VSCALE_IP_FRAC_SHIFT 0 5078 5079 #define TV_CC_CONTROL _MMIO(0x68090) 5080 # define TV_CC_ENABLE (1 << 31) 5081 /* 5082 * Specifies which field to send the CC data in. 5083 * 5084 * CC data is usually sent in field 0. 5085 */ 5086 # define TV_CC_FID_MASK (1 << 27) 5087 # define TV_CC_FID_SHIFT 27 5088 /* Sets the horizontal position of the CC data. Usually 135. */ 5089 # define TV_CC_HOFF_MASK 0x03ff0000 5090 # define TV_CC_HOFF_SHIFT 16 5091 /* Sets the vertical position of the CC data. Usually 21 */ 5092 # define TV_CC_LINE_MASK 0x0000003f 5093 # define TV_CC_LINE_SHIFT 0 5094 5095 #define TV_CC_DATA _MMIO(0x68094) 5096 # define TV_CC_RDY (1 << 31) 5097 /* Second word of CC data to be transmitted. */ 5098 # define TV_CC_DATA_2_MASK 0x007f0000 5099 # define TV_CC_DATA_2_SHIFT 16 5100 /* First word of CC data to be transmitted. */ 5101 # define TV_CC_DATA_1_MASK 0x0000007f 5102 # define TV_CC_DATA_1_SHIFT 0 5103 5104 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 5105 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 5106 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 5107 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 5108 5109 /* Display Port */ 5110 #define DP_A _MMIO(0x64000) /* eDP */ 5111 #define DP_B _MMIO(0x64100) 5112 #define DP_C _MMIO(0x64200) 5113 #define DP_D _MMIO(0x64300) 5114 5115 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 5116 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 5117 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 5118 5119 #define DP_PORT_EN (1 << 31) 5120 #define DP_PIPEB_SELECT (1 << 30) 5121 #define DP_PIPE_MASK (1 << 30) 5122 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 5123 #define DP_PIPE_MASK_CHV (3 << 16) 5124 5125 /* Link training mode - select a suitable mode for each stage */ 5126 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 5127 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 5128 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 5129 #define DP_LINK_TRAIN_OFF (3 << 28) 5130 #define DP_LINK_TRAIN_MASK (3 << 28) 5131 #define DP_LINK_TRAIN_SHIFT 28 5132 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 5133 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 5134 5135 /* CPT Link training mode */ 5136 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 5137 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 5138 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 5139 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 5140 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 5141 #define DP_LINK_TRAIN_SHIFT_CPT 8 5142 5143 /* Signal voltages. These are mostly controlled by the other end */ 5144 #define DP_VOLTAGE_0_4 (0 << 25) 5145 #define DP_VOLTAGE_0_6 (1 << 25) 5146 #define DP_VOLTAGE_0_8 (2 << 25) 5147 #define DP_VOLTAGE_1_2 (3 << 25) 5148 #define DP_VOLTAGE_MASK (7 << 25) 5149 #define DP_VOLTAGE_SHIFT 25 5150 5151 /* Signal pre-emphasis levels, like voltages, the other end tells us what 5152 * they want 5153 */ 5154 #define DP_PRE_EMPHASIS_0 (0 << 22) 5155 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 5156 #define DP_PRE_EMPHASIS_6 (2 << 22) 5157 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 5158 #define DP_PRE_EMPHASIS_MASK (7 << 22) 5159 #define DP_PRE_EMPHASIS_SHIFT 22 5160 5161 /* How many wires to use. I guess 3 was too hard */ 5162 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 5163 #define DP_PORT_WIDTH_MASK (7 << 19) 5164 #define DP_PORT_WIDTH_SHIFT 19 5165 5166 /* Mystic DPCD version 1.1 special mode */ 5167 #define DP_ENHANCED_FRAMING (1 << 18) 5168 5169 /* eDP */ 5170 #define DP_PLL_FREQ_270MHZ (0 << 16) 5171 #define DP_PLL_FREQ_162MHZ (1 << 16) 5172 #define DP_PLL_FREQ_MASK (3 << 16) 5173 5174 /* locked once port is enabled */ 5175 #define DP_PORT_REVERSAL (1 << 15) 5176 5177 /* eDP */ 5178 #define DP_PLL_ENABLE (1 << 14) 5179 5180 /* sends the clock on lane 15 of the PEG for debug */ 5181 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 5182 5183 #define DP_SCRAMBLING_DISABLE (1 << 12) 5184 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 5185 5186 /* limit RGB values to avoid confusing TVs */ 5187 #define DP_COLOR_RANGE_16_235 (1 << 8) 5188 5189 /* Turn on the audio link */ 5190 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 5191 5192 /* vs and hs sync polarity */ 5193 #define DP_SYNC_VS_HIGH (1 << 4) 5194 #define DP_SYNC_HS_HIGH (1 << 3) 5195 5196 /* A fantasy */ 5197 #define DP_DETECTED (1 << 2) 5198 5199 /* The aux channel provides a way to talk to the 5200 * signal sink for DDC etc. Max packet size supported 5201 * is 20 bytes in each direction, hence the 5 fixed 5202 * data registers 5203 */ 5204 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) 5205 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) 5206 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) 5207 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) 5208 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) 5209 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) 5210 5211 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) 5212 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) 5213 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) 5214 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) 5215 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) 5216 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) 5217 5218 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) 5219 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) 5220 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) 5221 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) 5222 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) 5223 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) 5224 5225 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) 5226 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) 5227 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) 5228 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) 5229 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) 5230 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) 5231 5232 #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 5233 #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5234 5235 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 5236 #define DP_AUX_CH_CTL_DONE (1 << 30) 5237 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 5238 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 5239 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 5240 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 5241 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 5242 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 5243 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 5244 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 5245 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 5246 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 5247 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 5248 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 5249 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 5250 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 5251 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 5252 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 5253 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 5254 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 5255 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 5256 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 5257 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 5258 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 5259 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 5260 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 5261 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 5262 5263 /* 5264 * Computing GMCH M and N values for the Display Port link 5265 * 5266 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 5267 * 5268 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 5269 * 5270 * The GMCH value is used internally 5271 * 5272 * bytes_per_pixel is the number of bytes coming out of the plane, 5273 * which is after the LUTs, so we want the bytes for our color format. 5274 * For our current usage, this is always 3, one byte for R, G and B. 5275 */ 5276 #define _PIPEA_DATA_M_G4X 0x70050 5277 #define _PIPEB_DATA_M_G4X 0x71050 5278 5279 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 5280 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 5281 #define TU_SIZE_SHIFT 25 5282 #define TU_SIZE_MASK (0x3f << 25) 5283 5284 #define DATA_LINK_M_N_MASK (0xffffff) 5285 #define DATA_LINK_N_MAX (0x800000) 5286 5287 #define _PIPEA_DATA_N_G4X 0x70054 5288 #define _PIPEB_DATA_N_G4X 0x71054 5289 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 5290 5291 /* 5292 * Computing Link M and N values for the Display Port link 5293 * 5294 * Link M / N = pixel_clock / ls_clk 5295 * 5296 * (the DP spec calls pixel_clock the 'strm_clk') 5297 * 5298 * The Link value is transmitted in the Main Stream 5299 * Attributes and VB-ID. 5300 */ 5301 5302 #define _PIPEA_LINK_M_G4X 0x70060 5303 #define _PIPEB_LINK_M_G4X 0x71060 5304 #define PIPEA_DP_LINK_M_MASK (0xffffff) 5305 5306 #define _PIPEA_LINK_N_G4X 0x70064 5307 #define _PIPEB_LINK_N_G4X 0x71064 5308 #define PIPEA_DP_LINK_N_MASK (0xffffff) 5309 5310 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 5311 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 5312 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 5313 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 5314 5315 /* Display & cursor control */ 5316 5317 /* Pipe A */ 5318 #define _PIPEADSL 0x70000 5319 #define DSL_LINEMASK_GEN2 0x00000fff 5320 #define DSL_LINEMASK_GEN3 0x00001fff 5321 #define _PIPEACONF 0x70008 5322 #define PIPECONF_ENABLE (1<<31) 5323 #define PIPECONF_DISABLE 0 5324 #define PIPECONF_DOUBLE_WIDE (1<<30) 5325 #define I965_PIPECONF_ACTIVE (1<<30) 5326 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 5327 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 5328 #define PIPECONF_SINGLE_WIDE 0 5329 #define PIPECONF_PIPE_UNLOCKED 0 5330 #define PIPECONF_PIPE_LOCKED (1<<25) 5331 #define PIPECONF_PALETTE 0 5332 #define PIPECONF_GAMMA (1<<24) 5333 #define PIPECONF_FORCE_BORDER (1<<25) 5334 #define PIPECONF_INTERLACE_MASK (7 << 21) 5335 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 5336 /* Note that pre-gen3 does not support interlaced display directly. Panel 5337 * fitting must be disabled on pre-ilk for interlaced. */ 5338 #define PIPECONF_PROGRESSIVE (0 << 21) 5339 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 5340 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 5341 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 5342 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 5343 /* Ironlake and later have a complete new set of values for interlaced. PFIT 5344 * means panel fitter required, PF means progressive fetch, DBL means power 5345 * saving pixel doubling. */ 5346 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 5347 #define PIPECONF_INTERLACED_ILK (3 << 21) 5348 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 5349 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 5350 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 5351 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 5352 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 5353 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 5354 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 5355 #define PIPECONF_BPC_MASK (0x7 << 5) 5356 #define PIPECONF_8BPC (0<<5) 5357 #define PIPECONF_10BPC (1<<5) 5358 #define PIPECONF_6BPC (2<<5) 5359 #define PIPECONF_12BPC (3<<5) 5360 #define PIPECONF_DITHER_EN (1<<4) 5361 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 5362 #define PIPECONF_DITHER_TYPE_SP (0<<2) 5363 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 5364 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 5365 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 5366 #define _PIPEASTAT 0x70024 5367 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 5368 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 5369 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 5370 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 5371 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 5372 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 5373 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 5374 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 5375 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 5376 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 5377 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 5378 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 5379 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 5380 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 5381 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 5382 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 5383 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 5384 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 5385 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 5386 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 5387 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 5388 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 5389 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 5390 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 5391 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 5392 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 5393 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 5394 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 5395 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 5396 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 5397 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 5398 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 5399 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 5400 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 5401 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 5402 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 5403 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 5404 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 5405 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 5406 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 5407 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 5408 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 5409 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 5410 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 5411 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 5412 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 5413 5414 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 5415 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 5416 5417 #define PIPE_A_OFFSET 0x70000 5418 #define PIPE_B_OFFSET 0x71000 5419 #define PIPE_C_OFFSET 0x72000 5420 #define CHV_PIPE_C_OFFSET 0x74000 5421 /* 5422 * There's actually no pipe EDP. Some pipe registers have 5423 * simply shifted from the pipe to the transcoder, while 5424 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 5425 * to access such registers in transcoder EDP. 5426 */ 5427 #define PIPE_EDP_OFFSET 0x7f000 5428 5429 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ 5430 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 5431 dev_priv->info.display_mmio_offset) 5432 5433 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 5434 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 5435 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 5436 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 5437 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 5438 5439 #define _PIPE_MISC_A 0x70030 5440 #define _PIPE_MISC_B 0x71030 5441 #define PIPEMISC_YUV420_ENABLE (1<<27) 5442 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26) 5443 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11) 5444 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 5445 #define PIPEMISC_DITHER_8_BPC (0<<5) 5446 #define PIPEMISC_DITHER_10_BPC (1<<5) 5447 #define PIPEMISC_DITHER_6_BPC (2<<5) 5448 #define PIPEMISC_DITHER_12_BPC (3<<5) 5449 #define PIPEMISC_DITHER_ENABLE (1<<4) 5450 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 5451 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 5452 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 5453 5454 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 5455 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 5456 #define PIPEB_HLINE_INT_EN (1<<28) 5457 #define PIPEB_VBLANK_INT_EN (1<<27) 5458 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 5459 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 5460 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 5461 #define PIPE_PSR_INT_EN (1<<22) 5462 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 5463 #define PIPEA_HLINE_INT_EN (1<<20) 5464 #define PIPEA_VBLANK_INT_EN (1<<19) 5465 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 5466 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 5467 #define PLANEA_FLIPDONE_INT_EN (1<<16) 5468 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 5469 #define PIPEC_HLINE_INT_EN (1<<12) 5470 #define PIPEC_VBLANK_INT_EN (1<<11) 5471 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 5472 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 5473 #define PLANEC_FLIPDONE_INT_EN (1<<8) 5474 5475 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 5476 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 5477 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 5478 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 5479 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 5480 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 5481 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 5482 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 5483 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 5484 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 5485 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 5486 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 5487 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 5488 #define DPINVGTT_EN_MASK 0xff0000 5489 #define DPINVGTT_EN_MASK_CHV 0xfff0000 5490 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 5491 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 5492 #define PLANEC_INVALID_GTT_STATUS (1<<9) 5493 #define CURSORC_INVALID_GTT_STATUS (1<<8) 5494 #define CURSORB_INVALID_GTT_STATUS (1<<7) 5495 #define CURSORA_INVALID_GTT_STATUS (1<<6) 5496 #define SPRITED_INVALID_GTT_STATUS (1<<5) 5497 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 5498 #define PLANEB_INVALID_GTT_STATUS (1<<3) 5499 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 5500 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 5501 #define PLANEA_INVALID_GTT_STATUS (1<<0) 5502 #define DPINVGTT_STATUS_MASK 0xff 5503 #define DPINVGTT_STATUS_MASK_CHV 0xfff 5504 5505 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) 5506 #define DSPARB_CSTART_MASK (0x7f << 7) 5507 #define DSPARB_CSTART_SHIFT 7 5508 #define DSPARB_BSTART_MASK (0x7f) 5509 #define DSPARB_BSTART_SHIFT 0 5510 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 5511 #define DSPARB_AEND_SHIFT 0 5512 #define DSPARB_SPRITEA_SHIFT_VLV 0 5513 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 5514 #define DSPARB_SPRITEB_SHIFT_VLV 8 5515 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 5516 #define DSPARB_SPRITEC_SHIFT_VLV 16 5517 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 5518 #define DSPARB_SPRITED_SHIFT_VLV 24 5519 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 5520 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 5521 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 5522 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 5523 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 5524 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 5525 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 5526 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 5527 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 5528 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 5529 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 5530 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 5531 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 5532 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 5533 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 5534 #define DSPARB_SPRITEE_SHIFT_VLV 0 5535 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 5536 #define DSPARB_SPRITEF_SHIFT_VLV 8 5537 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 5538 5539 /* pnv/gen4/g4x/vlv/chv */ 5540 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) 5541 #define DSPFW_SR_SHIFT 23 5542 #define DSPFW_SR_MASK (0x1ff<<23) 5543 #define DSPFW_CURSORB_SHIFT 16 5544 #define DSPFW_CURSORB_MASK (0x3f<<16) 5545 #define DSPFW_PLANEB_SHIFT 8 5546 #define DSPFW_PLANEB_MASK (0x7f<<8) 5547 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 5548 #define DSPFW_PLANEA_SHIFT 0 5549 #define DSPFW_PLANEA_MASK (0x7f<<0) 5550 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 5551 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) 5552 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 5553 #define DSPFW_FBC_SR_SHIFT 28 5554 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 5555 #define DSPFW_FBC_HPLL_SR_SHIFT 24 5556 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 5557 #define DSPFW_SPRITEB_SHIFT (16) 5558 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 5559 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 5560 #define DSPFW_CURSORA_SHIFT 8 5561 #define DSPFW_CURSORA_MASK (0x3f<<8) 5562 #define DSPFW_PLANEC_OLD_SHIFT 0 5563 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ 5564 #define DSPFW_SPRITEA_SHIFT 0 5565 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 5566 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 5567 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) 5568 #define DSPFW_HPLL_SR_EN (1<<31) 5569 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 5570 #define DSPFW_CURSOR_SR_SHIFT 24 5571 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 5572 #define DSPFW_HPLL_CURSOR_SHIFT 16 5573 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 5574 #define DSPFW_HPLL_SR_SHIFT 0 5575 #define DSPFW_HPLL_SR_MASK (0x1ff<<0) 5576 5577 /* vlv/chv */ 5578 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 5579 #define DSPFW_SPRITEB_WM1_SHIFT 16 5580 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 5581 #define DSPFW_CURSORA_WM1_SHIFT 8 5582 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 5583 #define DSPFW_SPRITEA_WM1_SHIFT 0 5584 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 5585 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 5586 #define DSPFW_PLANEB_WM1_SHIFT 24 5587 #define DSPFW_PLANEB_WM1_MASK (0xff<<24) 5588 #define DSPFW_PLANEA_WM1_SHIFT 16 5589 #define DSPFW_PLANEA_WM1_MASK (0xff<<16) 5590 #define DSPFW_CURSORB_WM1_SHIFT 8 5591 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 5592 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 5593 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 5594 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 5595 #define DSPFW_SR_WM1_SHIFT 0 5596 #define DSPFW_SR_WM1_MASK (0x1ff<<0) 5597 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 5598 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 5599 #define DSPFW_SPRITED_WM1_SHIFT 24 5600 #define DSPFW_SPRITED_WM1_MASK (0xff<<24) 5601 #define DSPFW_SPRITED_SHIFT 16 5602 #define DSPFW_SPRITED_MASK_VLV (0xff<<16) 5603 #define DSPFW_SPRITEC_WM1_SHIFT 8 5604 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 5605 #define DSPFW_SPRITEC_SHIFT 0 5606 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) 5607 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 5608 #define DSPFW_SPRITEF_WM1_SHIFT 24 5609 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 5610 #define DSPFW_SPRITEF_SHIFT 16 5611 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) 5612 #define DSPFW_SPRITEE_WM1_SHIFT 8 5613 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 5614 #define DSPFW_SPRITEE_SHIFT 0 5615 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) 5616 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 5617 #define DSPFW_PLANEC_WM1_SHIFT 24 5618 #define DSPFW_PLANEC_WM1_MASK (0xff<<24) 5619 #define DSPFW_PLANEC_SHIFT 16 5620 #define DSPFW_PLANEC_MASK_VLV (0xff<<16) 5621 #define DSPFW_CURSORC_WM1_SHIFT 8 5622 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 5623 #define DSPFW_CURSORC_SHIFT 0 5624 #define DSPFW_CURSORC_MASK (0x3f<<0) 5625 5626 /* vlv/chv high order bits */ 5627 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 5628 #define DSPFW_SR_HI_SHIFT 24 5629 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 5630 #define DSPFW_SPRITEF_HI_SHIFT 23 5631 #define DSPFW_SPRITEF_HI_MASK (1<<23) 5632 #define DSPFW_SPRITEE_HI_SHIFT 22 5633 #define DSPFW_SPRITEE_HI_MASK (1<<22) 5634 #define DSPFW_PLANEC_HI_SHIFT 21 5635 #define DSPFW_PLANEC_HI_MASK (1<<21) 5636 #define DSPFW_SPRITED_HI_SHIFT 20 5637 #define DSPFW_SPRITED_HI_MASK (1<<20) 5638 #define DSPFW_SPRITEC_HI_SHIFT 16 5639 #define DSPFW_SPRITEC_HI_MASK (1<<16) 5640 #define DSPFW_PLANEB_HI_SHIFT 12 5641 #define DSPFW_PLANEB_HI_MASK (1<<12) 5642 #define DSPFW_SPRITEB_HI_SHIFT 8 5643 #define DSPFW_SPRITEB_HI_MASK (1<<8) 5644 #define DSPFW_SPRITEA_HI_SHIFT 4 5645 #define DSPFW_SPRITEA_HI_MASK (1<<4) 5646 #define DSPFW_PLANEA_HI_SHIFT 0 5647 #define DSPFW_PLANEA_HI_MASK (1<<0) 5648 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 5649 #define DSPFW_SR_WM1_HI_SHIFT 24 5650 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 5651 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 5652 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 5653 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 5654 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 5655 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 5656 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 5657 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 5658 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 5659 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 5660 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 5661 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 5662 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 5663 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 5664 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 5665 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 5666 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 5667 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 5668 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 5669 5670 /* drain latency register values*/ 5671 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 5672 #define DDL_CURSOR_SHIFT 24 5673 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 5674 #define DDL_PLANE_SHIFT 0 5675 #define DDL_PRECISION_HIGH (1<<7) 5676 #define DDL_PRECISION_LOW (0<<7) 5677 #define DRAIN_LATENCY_MASK 0x7f 5678 5679 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 5680 #define CBR_PND_DEADLINE_DISABLE (1<<31) 5681 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30) 5682 5683 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 5684 #define CBR_DPLLBMD_PIPE(pipe) (1<<(7+(pipe)*11)) /* pipes B and C */ 5685 5686 /* FIFO watermark sizes etc */ 5687 #define G4X_FIFO_LINE_SIZE 64 5688 #define I915_FIFO_LINE_SIZE 64 5689 #define I830_FIFO_LINE_SIZE 32 5690 5691 #define VALLEYVIEW_FIFO_SIZE 255 5692 #define G4X_FIFO_SIZE 127 5693 #define I965_FIFO_SIZE 512 5694 #define I945_FIFO_SIZE 127 5695 #define I915_FIFO_SIZE 95 5696 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 5697 #define I830_FIFO_SIZE 95 5698 5699 #define VALLEYVIEW_MAX_WM 0xff 5700 #define G4X_MAX_WM 0x3f 5701 #define I915_MAX_WM 0x3f 5702 5703 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 5704 #define PINEVIEW_FIFO_LINE_SIZE 64 5705 #define PINEVIEW_MAX_WM 0x1ff 5706 #define PINEVIEW_DFT_WM 0x3f 5707 #define PINEVIEW_DFT_HPLLOFF_WM 0 5708 #define PINEVIEW_GUARD_WM 10 5709 #define PINEVIEW_CURSOR_FIFO 64 5710 #define PINEVIEW_CURSOR_MAX_WM 0x3f 5711 #define PINEVIEW_CURSOR_DFT_WM 0 5712 #define PINEVIEW_CURSOR_GUARD_WM 5 5713 5714 #define VALLEYVIEW_CURSOR_MAX_WM 64 5715 #define I965_CURSOR_FIFO 64 5716 #define I965_CURSOR_MAX_WM 32 5717 #define I965_CURSOR_DFT_WM 8 5718 5719 /* Watermark register definitions for SKL */ 5720 #define _CUR_WM_A_0 0x70140 5721 #define _CUR_WM_B_0 0x71140 5722 #define _PLANE_WM_1_A_0 0x70240 5723 #define _PLANE_WM_1_B_0 0x71240 5724 #define _PLANE_WM_2_A_0 0x70340 5725 #define _PLANE_WM_2_B_0 0x71340 5726 #define _PLANE_WM_TRANS_1_A_0 0x70268 5727 #define _PLANE_WM_TRANS_1_B_0 0x71268 5728 #define _PLANE_WM_TRANS_2_A_0 0x70368 5729 #define _PLANE_WM_TRANS_2_B_0 0x71368 5730 #define _CUR_WM_TRANS_A_0 0x70168 5731 #define _CUR_WM_TRANS_B_0 0x71168 5732 #define PLANE_WM_EN (1 << 31) 5733 #define PLANE_WM_LINES_SHIFT 14 5734 #define PLANE_WM_LINES_MASK 0x1f 5735 #define PLANE_WM_BLOCKS_MASK 0x3ff 5736 5737 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 5738 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 5739 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 5740 5741 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 5742 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 5743 #define _PLANE_WM_BASE(pipe, plane) \ 5744 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 5745 #define PLANE_WM(pipe, plane, level) \ 5746 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 5747 #define _PLANE_WM_TRANS_1(pipe) \ 5748 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 5749 #define _PLANE_WM_TRANS_2(pipe) \ 5750 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 5751 #define PLANE_WM_TRANS(pipe, plane) \ 5752 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 5753 5754 /* define the Watermark register on Ironlake */ 5755 #define WM0_PIPEA_ILK _MMIO(0x45100) 5756 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 5757 #define WM0_PIPE_PLANE_SHIFT 16 5758 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 5759 #define WM0_PIPE_SPRITE_SHIFT 8 5760 #define WM0_PIPE_CURSOR_MASK (0xff) 5761 5762 #define WM0_PIPEB_ILK _MMIO(0x45104) 5763 #define WM0_PIPEC_IVB _MMIO(0x45200) 5764 #define WM1_LP_ILK _MMIO(0x45108) 5765 #define WM1_LP_SR_EN (1<<31) 5766 #define WM1_LP_LATENCY_SHIFT 24 5767 #define WM1_LP_LATENCY_MASK (0x7f<<24) 5768 #define WM1_LP_FBC_MASK (0xf<<20) 5769 #define WM1_LP_FBC_SHIFT 20 5770 #define WM1_LP_FBC_SHIFT_BDW 19 5771 #define WM1_LP_SR_MASK (0x7ff<<8) 5772 #define WM1_LP_SR_SHIFT 8 5773 #define WM1_LP_CURSOR_MASK (0xff) 5774 #define WM2_LP_ILK _MMIO(0x4510c) 5775 #define WM2_LP_EN (1<<31) 5776 #define WM3_LP_ILK _MMIO(0x45110) 5777 #define WM3_LP_EN (1<<31) 5778 #define WM1S_LP_ILK _MMIO(0x45120) 5779 #define WM2S_LP_IVB _MMIO(0x45124) 5780 #define WM3S_LP_IVB _MMIO(0x45128) 5781 #define WM1S_LP_EN (1<<31) 5782 5783 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 5784 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 5785 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 5786 5787 /* Memory latency timer register */ 5788 #define MLTR_ILK _MMIO(0x11222) 5789 #define MLTR_WM1_SHIFT 0 5790 #define MLTR_WM2_SHIFT 8 5791 /* the unit of memory self-refresh latency time is 0.5us */ 5792 #define ILK_SRLT_MASK 0x3f 5793 5794 5795 /* the address where we get all kinds of latency value */ 5796 #define SSKPD _MMIO(0x5d10) 5797 #define SSKPD_WM_MASK 0x3f 5798 #define SSKPD_WM0_SHIFT 0 5799 #define SSKPD_WM1_SHIFT 8 5800 #define SSKPD_WM2_SHIFT 16 5801 #define SSKPD_WM3_SHIFT 24 5802 5803 /* 5804 * The two pipe frame counter registers are not synchronized, so 5805 * reading a stable value is somewhat tricky. The following code 5806 * should work: 5807 * 5808 * do { 5809 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 5810 * PIPE_FRAME_HIGH_SHIFT; 5811 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 5812 * PIPE_FRAME_LOW_SHIFT); 5813 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 5814 * PIPE_FRAME_HIGH_SHIFT); 5815 * } while (high1 != high2); 5816 * frame = (high1 << 8) | low1; 5817 */ 5818 #define _PIPEAFRAMEHIGH 0x70040 5819 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 5820 #define PIPE_FRAME_HIGH_SHIFT 0 5821 #define _PIPEAFRAMEPIXEL 0x70044 5822 #define PIPE_FRAME_LOW_MASK 0xff000000 5823 #define PIPE_FRAME_LOW_SHIFT 24 5824 #define PIPE_PIXEL_MASK 0x00ffffff 5825 #define PIPE_PIXEL_SHIFT 0 5826 /* GM45+ just has to be different */ 5827 #define _PIPEA_FRMCOUNT_G4X 0x70040 5828 #define _PIPEA_FLIPCOUNT_G4X 0x70044 5829 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 5830 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 5831 5832 /* Cursor A & B regs */ 5833 #define _CURACNTR 0x70080 5834 /* Old style CUR*CNTR flags (desktop 8xx) */ 5835 #define CURSOR_ENABLE 0x80000000 5836 #define CURSOR_GAMMA_ENABLE 0x40000000 5837 #define CURSOR_STRIDE_SHIFT 28 5838 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 5839 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 5840 #define CURSOR_FORMAT_SHIFT 24 5841 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 5842 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 5843 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 5844 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 5845 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 5846 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 5847 /* New style CUR*CNTR flags */ 5848 #define CURSOR_MODE 0x27 5849 #define CURSOR_MODE_DISABLE 0x00 5850 #define CURSOR_MODE_128_32B_AX 0x02 5851 #define CURSOR_MODE_256_32B_AX 0x03 5852 #define CURSOR_MODE_64_32B_AX 0x07 5853 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 5854 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 5855 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 5856 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) 5857 #define MCURSOR_GAMMA_ENABLE (1 << 26) 5858 #define CURSOR_ROTATE_180 (1<<15) 5859 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 5860 #define _CURABASE 0x70084 5861 #define _CURAPOS 0x70088 5862 #define CURSOR_POS_MASK 0x007FF 5863 #define CURSOR_POS_SIGN 0x8000 5864 #define CURSOR_X_SHIFT 0 5865 #define CURSOR_Y_SHIFT 16 5866 #define CURSIZE _MMIO(0x700a0) /* 845/865 */ 5867 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 5868 #define CUR_FBC_CTL_EN (1 << 31) 5869 #define _CURBCNTR 0x700c0 5870 #define _CURBBASE 0x700c4 5871 #define _CURBPOS 0x700c8 5872 5873 #define _CURBCNTR_IVB 0x71080 5874 #define _CURBBASE_IVB 0x71084 5875 #define _CURBPOS_IVB 0x71088 5876 5877 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ 5878 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 5879 dev_priv->info.display_mmio_offset) 5880 5881 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 5882 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 5883 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 5884 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 5885 5886 #define CURSOR_A_OFFSET 0x70080 5887 #define CURSOR_B_OFFSET 0x700c0 5888 #define CHV_CURSOR_C_OFFSET 0x700e0 5889 #define IVB_CURSOR_B_OFFSET 0x71080 5890 #define IVB_CURSOR_C_OFFSET 0x72080 5891 5892 /* Display A control */ 5893 #define _DSPACNTR 0x70180 5894 #define DISPLAY_PLANE_ENABLE (1<<31) 5895 #define DISPLAY_PLANE_DISABLE 0 5896 #define DISPPLANE_GAMMA_ENABLE (1<<30) 5897 #define DISPPLANE_GAMMA_DISABLE 0 5898 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 5899 #define DISPPLANE_YUV422 (0x0<<26) 5900 #define DISPPLANE_8BPP (0x2<<26) 5901 #define DISPPLANE_BGRA555 (0x3<<26) 5902 #define DISPPLANE_BGRX555 (0x4<<26) 5903 #define DISPPLANE_BGRX565 (0x5<<26) 5904 #define DISPPLANE_BGRX888 (0x6<<26) 5905 #define DISPPLANE_BGRA888 (0x7<<26) 5906 #define DISPPLANE_RGBX101010 (0x8<<26) 5907 #define DISPPLANE_RGBA101010 (0x9<<26) 5908 #define DISPPLANE_BGRX101010 (0xa<<26) 5909 #define DISPPLANE_RGBX161616 (0xc<<26) 5910 #define DISPPLANE_RGBX888 (0xe<<26) 5911 #define DISPPLANE_RGBA888 (0xf<<26) 5912 #define DISPPLANE_STEREO_ENABLE (1<<25) 5913 #define DISPPLANE_STEREO_DISABLE 0 5914 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 5915 #define DISPPLANE_SEL_PIPE_SHIFT 24 5916 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 5917 #define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT) 5918 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 5919 #define DISPPLANE_SRC_KEY_DISABLE 0 5920 #define DISPPLANE_LINE_DOUBLE (1<<20) 5921 #define DISPPLANE_NO_LINE_DOUBLE 0 5922 #define DISPPLANE_STEREO_POLARITY_FIRST 0 5923 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 5924 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ 5925 #define DISPPLANE_ROTATE_180 (1<<15) 5926 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 5927 #define DISPPLANE_TILED (1<<10) 5928 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ 5929 #define _DSPAADDR 0x70184 5930 #define _DSPASTRIDE 0x70188 5931 #define _DSPAPOS 0x7018C /* reserved */ 5932 #define _DSPASIZE 0x70190 5933 #define _DSPASURF 0x7019C /* 965+ only */ 5934 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 5935 #define _DSPAOFFSET 0x701A4 /* HSW */ 5936 #define _DSPASURFLIVE 0x701AC 5937 5938 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 5939 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 5940 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 5941 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 5942 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 5943 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 5944 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 5945 #define DSPLINOFF(plane) DSPADDR(plane) 5946 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 5947 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 5948 5949 /* CHV pipe B blender and primary plane */ 5950 #define _CHV_BLEND_A 0x60a00 5951 #define CHV_BLEND_LEGACY (0<<30) 5952 #define CHV_BLEND_ANDROID (1<<30) 5953 #define CHV_BLEND_MPO (2<<30) 5954 #define CHV_BLEND_MASK (3<<30) 5955 #define _CHV_CANVAS_A 0x60a04 5956 #define _PRIMPOS_A 0x60a08 5957 #define _PRIMSIZE_A 0x60a0c 5958 #define _PRIMCNSTALPHA_A 0x60a10 5959 #define PRIM_CONST_ALPHA_ENABLE (1<<31) 5960 5961 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 5962 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 5963 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 5964 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 5965 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 5966 5967 /* Display/Sprite base address macros */ 5968 #define DISP_BASEADDR_MASK (0xfffff000) 5969 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 5970 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 5971 5972 /* 5973 * VBIOS flags 5974 * gen2: 5975 * [00:06] alm,mgm 5976 * [10:16] all 5977 * [30:32] alm,mgm 5978 * gen3+: 5979 * [00:0f] all 5980 * [10:1f] all 5981 * [30:32] all 5982 */ 5983 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) 5984 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) 5985 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) 5986 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 5987 5988 /* Pipe B */ 5989 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 5990 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 5991 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 5992 #define _PIPEBFRAMEHIGH 0x71040 5993 #define _PIPEBFRAMEPIXEL 0x71044 5994 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) 5995 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) 5996 5997 5998 /* Display B control */ 5999 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 6000 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 6001 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 6002 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 6003 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 6004 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 6005 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 6006 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 6007 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 6008 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 6009 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 6010 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 6011 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 6012 6013 /* Sprite A control */ 6014 #define _DVSACNTR 0x72180 6015 #define DVS_ENABLE (1<<31) 6016 #define DVS_GAMMA_ENABLE (1<<30) 6017 #define DVS_PIXFORMAT_MASK (3<<25) 6018 #define DVS_FORMAT_YUV422 (0<<25) 6019 #define DVS_FORMAT_RGBX101010 (1<<25) 6020 #define DVS_FORMAT_RGBX888 (2<<25) 6021 #define DVS_FORMAT_RGBX161616 (3<<25) 6022 #define DVS_PIPE_CSC_ENABLE (1<<24) 6023 #define DVS_SOURCE_KEY (1<<22) 6024 #define DVS_RGB_ORDER_XBGR (1<<20) 6025 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 6026 #define DVS_YUV_ORDER_YUYV (0<<16) 6027 #define DVS_YUV_ORDER_UYVY (1<<16) 6028 #define DVS_YUV_ORDER_YVYU (2<<16) 6029 #define DVS_YUV_ORDER_VYUY (3<<16) 6030 #define DVS_ROTATE_180 (1<<15) 6031 #define DVS_DEST_KEY (1<<2) 6032 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 6033 #define DVS_TILED (1<<10) 6034 #define _DVSALINOFF 0x72184 6035 #define _DVSASTRIDE 0x72188 6036 #define _DVSAPOS 0x7218c 6037 #define _DVSASIZE 0x72190 6038 #define _DVSAKEYVAL 0x72194 6039 #define _DVSAKEYMSK 0x72198 6040 #define _DVSASURF 0x7219c 6041 #define _DVSAKEYMAXVAL 0x721a0 6042 #define _DVSATILEOFF 0x721a4 6043 #define _DVSASURFLIVE 0x721ac 6044 #define _DVSASCALE 0x72204 6045 #define DVS_SCALE_ENABLE (1<<31) 6046 #define DVS_FILTER_MASK (3<<29) 6047 #define DVS_FILTER_MEDIUM (0<<29) 6048 #define DVS_FILTER_ENHANCING (1<<29) 6049 #define DVS_FILTER_SOFTENING (2<<29) 6050 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 6051 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 6052 #define _DVSAGAMC 0x72300 6053 6054 #define _DVSBCNTR 0x73180 6055 #define _DVSBLINOFF 0x73184 6056 #define _DVSBSTRIDE 0x73188 6057 #define _DVSBPOS 0x7318c 6058 #define _DVSBSIZE 0x73190 6059 #define _DVSBKEYVAL 0x73194 6060 #define _DVSBKEYMSK 0x73198 6061 #define _DVSBSURF 0x7319c 6062 #define _DVSBKEYMAXVAL 0x731a0 6063 #define _DVSBTILEOFF 0x731a4 6064 #define _DVSBSURFLIVE 0x731ac 6065 #define _DVSBSCALE 0x73204 6066 #define _DVSBGAMC 0x73300 6067 6068 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 6069 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 6070 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 6071 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 6072 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 6073 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 6074 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 6075 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 6076 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 6077 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 6078 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 6079 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 6080 6081 #define _SPRA_CTL 0x70280 6082 #define SPRITE_ENABLE (1<<31) 6083 #define SPRITE_GAMMA_ENABLE (1<<30) 6084 #define SPRITE_PIXFORMAT_MASK (7<<25) 6085 #define SPRITE_FORMAT_YUV422 (0<<25) 6086 #define SPRITE_FORMAT_RGBX101010 (1<<25) 6087 #define SPRITE_FORMAT_RGBX888 (2<<25) 6088 #define SPRITE_FORMAT_RGBX161616 (3<<25) 6089 #define SPRITE_FORMAT_YUV444 (4<<25) 6090 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 6091 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 6092 #define SPRITE_SOURCE_KEY (1<<22) 6093 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 6094 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 6095 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 6096 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 6097 #define SPRITE_YUV_ORDER_YUYV (0<<16) 6098 #define SPRITE_YUV_ORDER_UYVY (1<<16) 6099 #define SPRITE_YUV_ORDER_YVYU (2<<16) 6100 #define SPRITE_YUV_ORDER_VYUY (3<<16) 6101 #define SPRITE_ROTATE_180 (1<<15) 6102 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 6103 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 6104 #define SPRITE_TILED (1<<10) 6105 #define SPRITE_DEST_KEY (1<<2) 6106 #define _SPRA_LINOFF 0x70284 6107 #define _SPRA_STRIDE 0x70288 6108 #define _SPRA_POS 0x7028c 6109 #define _SPRA_SIZE 0x70290 6110 #define _SPRA_KEYVAL 0x70294 6111 #define _SPRA_KEYMSK 0x70298 6112 #define _SPRA_SURF 0x7029c 6113 #define _SPRA_KEYMAX 0x702a0 6114 #define _SPRA_TILEOFF 0x702a4 6115 #define _SPRA_OFFSET 0x702a4 6116 #define _SPRA_SURFLIVE 0x702ac 6117 #define _SPRA_SCALE 0x70304 6118 #define SPRITE_SCALE_ENABLE (1<<31) 6119 #define SPRITE_FILTER_MASK (3<<29) 6120 #define SPRITE_FILTER_MEDIUM (0<<29) 6121 #define SPRITE_FILTER_ENHANCING (1<<29) 6122 #define SPRITE_FILTER_SOFTENING (2<<29) 6123 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 6124 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 6125 #define _SPRA_GAMC 0x70400 6126 6127 #define _SPRB_CTL 0x71280 6128 #define _SPRB_LINOFF 0x71284 6129 #define _SPRB_STRIDE 0x71288 6130 #define _SPRB_POS 0x7128c 6131 #define _SPRB_SIZE 0x71290 6132 #define _SPRB_KEYVAL 0x71294 6133 #define _SPRB_KEYMSK 0x71298 6134 #define _SPRB_SURF 0x7129c 6135 #define _SPRB_KEYMAX 0x712a0 6136 #define _SPRB_TILEOFF 0x712a4 6137 #define _SPRB_OFFSET 0x712a4 6138 #define _SPRB_SURFLIVE 0x712ac 6139 #define _SPRB_SCALE 0x71304 6140 #define _SPRB_GAMC 0x71400 6141 6142 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 6143 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 6144 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 6145 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 6146 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 6147 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 6148 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 6149 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 6150 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 6151 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 6152 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 6153 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 6154 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 6155 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 6156 6157 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 6158 #define SP_ENABLE (1<<31) 6159 #define SP_GAMMA_ENABLE (1<<30) 6160 #define SP_PIXFORMAT_MASK (0xf<<26) 6161 #define SP_FORMAT_YUV422 (0<<26) 6162 #define SP_FORMAT_BGR565 (5<<26) 6163 #define SP_FORMAT_BGRX8888 (6<<26) 6164 #define SP_FORMAT_BGRA8888 (7<<26) 6165 #define SP_FORMAT_RGBX1010102 (8<<26) 6166 #define SP_FORMAT_RGBA1010102 (9<<26) 6167 #define SP_FORMAT_RGBX8888 (0xe<<26) 6168 #define SP_FORMAT_RGBA8888 (0xf<<26) 6169 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ 6170 #define SP_SOURCE_KEY (1<<22) 6171 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 6172 #define SP_YUV_ORDER_YUYV (0<<16) 6173 #define SP_YUV_ORDER_UYVY (1<<16) 6174 #define SP_YUV_ORDER_YVYU (2<<16) 6175 #define SP_YUV_ORDER_VYUY (3<<16) 6176 #define SP_ROTATE_180 (1<<15) 6177 #define SP_TILED (1<<10) 6178 #define SP_MIRROR (1<<8) /* CHV pipe B */ 6179 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 6180 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 6181 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 6182 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 6183 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 6184 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 6185 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 6186 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 6187 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 6188 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 6189 #define SP_CONST_ALPHA_ENABLE (1<<31) 6190 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 6191 6192 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 6193 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 6194 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 6195 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 6196 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 6197 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 6198 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 6199 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 6200 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 6201 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 6202 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 6203 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 6204 6205 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6206 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 6207 6208 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 6209 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 6210 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 6211 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 6212 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 6213 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 6214 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 6215 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 6216 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 6217 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 6218 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 6219 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) 6220 6221 /* 6222 * CHV pipe B sprite CSC 6223 * 6224 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 6225 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 6226 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 6227 */ 6228 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 6229 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 6230 6231 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 6232 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 6233 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 6234 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 6235 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 6236 6237 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 6238 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 6239 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 6240 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 6241 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 6242 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 6243 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 6244 6245 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 6246 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 6247 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 6248 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 6249 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 6250 6251 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 6252 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 6253 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 6254 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 6255 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 6256 6257 /* Skylake plane registers */ 6258 6259 #define _PLANE_CTL_1_A 0x70180 6260 #define _PLANE_CTL_2_A 0x70280 6261 #define _PLANE_CTL_3_A 0x70380 6262 #define PLANE_CTL_ENABLE (1 << 31) 6263 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) 6264 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 6265 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) 6266 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) 6267 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) 6268 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) 6269 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) 6270 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) 6271 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) 6272 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) 6273 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) 6274 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 6275 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) 6276 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) 6277 #define PLANE_CTL_ORDER_BGRX (0 << 20) 6278 #define PLANE_CTL_ORDER_RGBX (1 << 20) 6279 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6280 #define PLANE_CTL_YUV422_YUYV ( 0 << 16) 6281 #define PLANE_CTL_YUV422_UYVY ( 1 << 16) 6282 #define PLANE_CTL_YUV422_YVYU ( 2 << 16) 6283 #define PLANE_CTL_YUV422_VYUY ( 3 << 16) 6284 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) 6285 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 6286 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) 6287 #define PLANE_CTL_TILED_MASK (0x7 << 10) 6288 #define PLANE_CTL_TILED_LINEAR ( 0 << 10) 6289 #define PLANE_CTL_TILED_X ( 1 << 10) 6290 #define PLANE_CTL_TILED_Y ( 4 << 10) 6291 #define PLANE_CTL_TILED_YF ( 5 << 10) 6292 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) 6293 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) 6294 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) 6295 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) 6296 #define PLANE_CTL_ROTATE_MASK 0x3 6297 #define PLANE_CTL_ROTATE_0 0x0 6298 #define PLANE_CTL_ROTATE_90 0x1 6299 #define PLANE_CTL_ROTATE_180 0x2 6300 #define PLANE_CTL_ROTATE_270 0x3 6301 #define _PLANE_STRIDE_1_A 0x70188 6302 #define _PLANE_STRIDE_2_A 0x70288 6303 #define _PLANE_STRIDE_3_A 0x70388 6304 #define _PLANE_POS_1_A 0x7018c 6305 #define _PLANE_POS_2_A 0x7028c 6306 #define _PLANE_POS_3_A 0x7038c 6307 #define _PLANE_SIZE_1_A 0x70190 6308 #define _PLANE_SIZE_2_A 0x70290 6309 #define _PLANE_SIZE_3_A 0x70390 6310 #define _PLANE_SURF_1_A 0x7019c 6311 #define _PLANE_SURF_2_A 0x7029c 6312 #define _PLANE_SURF_3_A 0x7039c 6313 #define _PLANE_OFFSET_1_A 0x701a4 6314 #define _PLANE_OFFSET_2_A 0x702a4 6315 #define _PLANE_OFFSET_3_A 0x703a4 6316 #define _PLANE_KEYVAL_1_A 0x70194 6317 #define _PLANE_KEYVAL_2_A 0x70294 6318 #define _PLANE_KEYMSK_1_A 0x70198 6319 #define _PLANE_KEYMSK_2_A 0x70298 6320 #define _PLANE_KEYMAX_1_A 0x701a0 6321 #define _PLANE_KEYMAX_2_A 0x702a0 6322 #define _PLANE_AUX_DIST_1_A 0x701c0 6323 #define _PLANE_AUX_DIST_2_A 0x702c0 6324 #define _PLANE_AUX_OFFSET_1_A 0x701c4 6325 #define _PLANE_AUX_OFFSET_2_A 0x702c4 6326 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6327 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6328 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6329 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) 6330 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) 6331 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) 6332 #define _PLANE_BUF_CFG_1_A 0x7027c 6333 #define _PLANE_BUF_CFG_2_A 0x7037c 6334 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 6335 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 6336 6337 6338 #define _PLANE_CTL_1_B 0x71180 6339 #define _PLANE_CTL_2_B 0x71280 6340 #define _PLANE_CTL_3_B 0x71380 6341 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 6342 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 6343 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 6344 #define PLANE_CTL(pipe, plane) \ 6345 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 6346 6347 #define _PLANE_STRIDE_1_B 0x71188 6348 #define _PLANE_STRIDE_2_B 0x71288 6349 #define _PLANE_STRIDE_3_B 0x71388 6350 #define _PLANE_STRIDE_1(pipe) \ 6351 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 6352 #define _PLANE_STRIDE_2(pipe) \ 6353 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 6354 #define _PLANE_STRIDE_3(pipe) \ 6355 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 6356 #define PLANE_STRIDE(pipe, plane) \ 6357 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 6358 6359 #define _PLANE_POS_1_B 0x7118c 6360 #define _PLANE_POS_2_B 0x7128c 6361 #define _PLANE_POS_3_B 0x7138c 6362 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 6363 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 6364 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 6365 #define PLANE_POS(pipe, plane) \ 6366 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 6367 6368 #define _PLANE_SIZE_1_B 0x71190 6369 #define _PLANE_SIZE_2_B 0x71290 6370 #define _PLANE_SIZE_3_B 0x71390 6371 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 6372 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 6373 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 6374 #define PLANE_SIZE(pipe, plane) \ 6375 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 6376 6377 #define _PLANE_SURF_1_B 0x7119c 6378 #define _PLANE_SURF_2_B 0x7129c 6379 #define _PLANE_SURF_3_B 0x7139c 6380 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 6381 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 6382 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 6383 #define PLANE_SURF(pipe, plane) \ 6384 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 6385 6386 #define _PLANE_OFFSET_1_B 0x711a4 6387 #define _PLANE_OFFSET_2_B 0x712a4 6388 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 6389 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 6390 #define PLANE_OFFSET(pipe, plane) \ 6391 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 6392 6393 #define _PLANE_KEYVAL_1_B 0x71194 6394 #define _PLANE_KEYVAL_2_B 0x71294 6395 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 6396 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 6397 #define PLANE_KEYVAL(pipe, plane) \ 6398 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 6399 6400 #define _PLANE_KEYMSK_1_B 0x71198 6401 #define _PLANE_KEYMSK_2_B 0x71298 6402 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 6403 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 6404 #define PLANE_KEYMSK(pipe, plane) \ 6405 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 6406 6407 #define _PLANE_KEYMAX_1_B 0x711a0 6408 #define _PLANE_KEYMAX_2_B 0x712a0 6409 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 6410 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 6411 #define PLANE_KEYMAX(pipe, plane) \ 6412 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 6413 6414 #define _PLANE_BUF_CFG_1_B 0x7127c 6415 #define _PLANE_BUF_CFG_2_B 0x7137c 6416 #define _PLANE_BUF_CFG_1(pipe) \ 6417 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 6418 #define _PLANE_BUF_CFG_2(pipe) \ 6419 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 6420 #define PLANE_BUF_CFG(pipe, plane) \ 6421 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 6422 6423 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 6424 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 6425 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 6426 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 6427 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 6428 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 6429 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 6430 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 6431 6432 #define _PLANE_AUX_DIST_1_B 0x711c0 6433 #define _PLANE_AUX_DIST_2_B 0x712c0 6434 #define _PLANE_AUX_DIST_1(pipe) \ 6435 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 6436 #define _PLANE_AUX_DIST_2(pipe) \ 6437 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 6438 #define PLANE_AUX_DIST(pipe, plane) \ 6439 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 6440 6441 #define _PLANE_AUX_OFFSET_1_B 0x711c4 6442 #define _PLANE_AUX_OFFSET_2_B 0x712c4 6443 #define _PLANE_AUX_OFFSET_1(pipe) \ 6444 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 6445 #define _PLANE_AUX_OFFSET_2(pipe) \ 6446 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 6447 #define PLANE_AUX_OFFSET(pipe, plane) \ 6448 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 6449 6450 #define _PLANE_COLOR_CTL_1_B 0x711CC 6451 #define _PLANE_COLOR_CTL_2_B 0x712CC 6452 #define _PLANE_COLOR_CTL_3_B 0x713CC 6453 #define _PLANE_COLOR_CTL_1(pipe) \ 6454 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 6455 #define _PLANE_COLOR_CTL_2(pipe) \ 6456 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 6457 #define PLANE_COLOR_CTL(pipe, plane) \ 6458 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 6459 6460 #/* SKL new cursor registers */ 6461 #define _CUR_BUF_CFG_A 0x7017c 6462 #define _CUR_BUF_CFG_B 0x7117c 6463 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 6464 6465 /* VBIOS regs */ 6466 #define VGACNTRL _MMIO(0x71400) 6467 # define VGA_DISP_DISABLE (1 << 31) 6468 # define VGA_2X_MODE (1 << 30) 6469 # define VGA_PIPE_B_SELECT (1 << 29) 6470 6471 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 6472 6473 /* Ironlake */ 6474 6475 #define CPU_VGACNTRL _MMIO(0x41000) 6476 6477 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 6478 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 6479 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 6480 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 6481 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 6482 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 6483 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 6484 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 6485 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 6486 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 6487 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 6488 6489 /* refresh rate hardware control */ 6490 #define RR_HW_CTL _MMIO(0x45300) 6491 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 6492 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 6493 6494 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 6495 #define FDI_PLL_FB_CLOCK_MASK 0xff 6496 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 6497 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 6498 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 6499 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 6500 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 6501 6502 #define PCH_3DCGDIS0 _MMIO(0x46020) 6503 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 6504 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 6505 6506 #define PCH_3DCGDIS1 _MMIO(0x46024) 6507 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 6508 6509 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 6510 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 6511 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 6512 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 6513 6514 6515 #define _PIPEA_DATA_M1 0x60030 6516 #define PIPE_DATA_M1_OFFSET 0 6517 #define _PIPEA_DATA_N1 0x60034 6518 #define PIPE_DATA_N1_OFFSET 0 6519 6520 #define _PIPEA_DATA_M2 0x60038 6521 #define PIPE_DATA_M2_OFFSET 0 6522 #define _PIPEA_DATA_N2 0x6003c 6523 #define PIPE_DATA_N2_OFFSET 0 6524 6525 #define _PIPEA_LINK_M1 0x60040 6526 #define PIPE_LINK_M1_OFFSET 0 6527 #define _PIPEA_LINK_N1 0x60044 6528 #define PIPE_LINK_N1_OFFSET 0 6529 6530 #define _PIPEA_LINK_M2 0x60048 6531 #define PIPE_LINK_M2_OFFSET 0 6532 #define _PIPEA_LINK_N2 0x6004c 6533 #define PIPE_LINK_N2_OFFSET 0 6534 6535 /* PIPEB timing regs are same start from 0x61000 */ 6536 6537 #define _PIPEB_DATA_M1 0x61030 6538 #define _PIPEB_DATA_N1 0x61034 6539 #define _PIPEB_DATA_M2 0x61038 6540 #define _PIPEB_DATA_N2 0x6103c 6541 #define _PIPEB_LINK_M1 0x61040 6542 #define _PIPEB_LINK_N1 0x61044 6543 #define _PIPEB_LINK_M2 0x61048 6544 #define _PIPEB_LINK_N2 0x6104c 6545 6546 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 6547 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 6548 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 6549 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 6550 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 6551 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 6552 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 6553 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 6554 6555 /* CPU panel fitter */ 6556 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 6557 #define _PFA_CTL_1 0x68080 6558 #define _PFB_CTL_1 0x68880 6559 #define PF_ENABLE (1<<31) 6560 #define PF_PIPE_SEL_MASK_IVB (3<<29) 6561 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 6562 #define PF_FILTER_MASK (3<<23) 6563 #define PF_FILTER_PROGRAMMED (0<<23) 6564 #define PF_FILTER_MED_3x3 (1<<23) 6565 #define PF_FILTER_EDGE_ENHANCE (2<<23) 6566 #define PF_FILTER_EDGE_SOFTEN (3<<23) 6567 #define _PFA_WIN_SZ 0x68074 6568 #define _PFB_WIN_SZ 0x68874 6569 #define _PFA_WIN_POS 0x68070 6570 #define _PFB_WIN_POS 0x68870 6571 #define _PFA_VSCALE 0x68084 6572 #define _PFB_VSCALE 0x68884 6573 #define _PFA_HSCALE 0x68090 6574 #define _PFB_HSCALE 0x68890 6575 6576 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 6577 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 6578 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 6579 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 6580 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 6581 6582 #define _PSA_CTL 0x68180 6583 #define _PSB_CTL 0x68980 6584 #define PS_ENABLE (1<<31) 6585 #define _PSA_WIN_SZ 0x68174 6586 #define _PSB_WIN_SZ 0x68974 6587 #define _PSA_WIN_POS 0x68170 6588 #define _PSB_WIN_POS 0x68970 6589 6590 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 6591 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 6592 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 6593 6594 /* 6595 * Skylake scalers 6596 */ 6597 #define _PS_1A_CTRL 0x68180 6598 #define _PS_2A_CTRL 0x68280 6599 #define _PS_1B_CTRL 0x68980 6600 #define _PS_2B_CTRL 0x68A80 6601 #define _PS_1C_CTRL 0x69180 6602 #define PS_SCALER_EN (1 << 31) 6603 #define PS_SCALER_MODE_MASK (3 << 28) 6604 #define PS_SCALER_MODE_DYN (0 << 28) 6605 #define PS_SCALER_MODE_HQ (1 << 28) 6606 #define PS_PLANE_SEL_MASK (7 << 25) 6607 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 6608 #define PS_FILTER_MASK (3 << 23) 6609 #define PS_FILTER_MEDIUM (0 << 23) 6610 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 6611 #define PS_FILTER_BILINEAR (3 << 23) 6612 #define PS_VERT3TAP (1 << 21) 6613 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 6614 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 6615 #define PS_PWRUP_PROGRESS (1 << 17) 6616 #define PS_V_FILTER_BYPASS (1 << 8) 6617 #define PS_VADAPT_EN (1 << 7) 6618 #define PS_VADAPT_MODE_MASK (3 << 5) 6619 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 6620 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 6621 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 6622 6623 #define _PS_PWR_GATE_1A 0x68160 6624 #define _PS_PWR_GATE_2A 0x68260 6625 #define _PS_PWR_GATE_1B 0x68960 6626 #define _PS_PWR_GATE_2B 0x68A60 6627 #define _PS_PWR_GATE_1C 0x69160 6628 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 6629 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 6630 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 6631 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 6632 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 6633 #define PS_PWR_GATE_SLPEN_8 0 6634 #define PS_PWR_GATE_SLPEN_16 1 6635 #define PS_PWR_GATE_SLPEN_24 2 6636 #define PS_PWR_GATE_SLPEN_32 3 6637 6638 #define _PS_WIN_POS_1A 0x68170 6639 #define _PS_WIN_POS_2A 0x68270 6640 #define _PS_WIN_POS_1B 0x68970 6641 #define _PS_WIN_POS_2B 0x68A70 6642 #define _PS_WIN_POS_1C 0x69170 6643 6644 #define _PS_WIN_SZ_1A 0x68174 6645 #define _PS_WIN_SZ_2A 0x68274 6646 #define _PS_WIN_SZ_1B 0x68974 6647 #define _PS_WIN_SZ_2B 0x68A74 6648 #define _PS_WIN_SZ_1C 0x69174 6649 6650 #define _PS_VSCALE_1A 0x68184 6651 #define _PS_VSCALE_2A 0x68284 6652 #define _PS_VSCALE_1B 0x68984 6653 #define _PS_VSCALE_2B 0x68A84 6654 #define _PS_VSCALE_1C 0x69184 6655 6656 #define _PS_HSCALE_1A 0x68190 6657 #define _PS_HSCALE_2A 0x68290 6658 #define _PS_HSCALE_1B 0x68990 6659 #define _PS_HSCALE_2B 0x68A90 6660 #define _PS_HSCALE_1C 0x69190 6661 6662 #define _PS_VPHASE_1A 0x68188 6663 #define _PS_VPHASE_2A 0x68288 6664 #define _PS_VPHASE_1B 0x68988 6665 #define _PS_VPHASE_2B 0x68A88 6666 #define _PS_VPHASE_1C 0x69188 6667 6668 #define _PS_HPHASE_1A 0x68194 6669 #define _PS_HPHASE_2A 0x68294 6670 #define _PS_HPHASE_1B 0x68994 6671 #define _PS_HPHASE_2B 0x68A94 6672 #define _PS_HPHASE_1C 0x69194 6673 6674 #define _PS_ECC_STAT_1A 0x681D0 6675 #define _PS_ECC_STAT_2A 0x682D0 6676 #define _PS_ECC_STAT_1B 0x689D0 6677 #define _PS_ECC_STAT_2B 0x68AD0 6678 #define _PS_ECC_STAT_1C 0x691D0 6679 6680 #define _ID(id, a, b) ((a) + (id)*((b)-(a))) 6681 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 6682 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 6683 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 6684 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 6685 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 6686 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 6687 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 6688 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 6689 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 6690 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 6691 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 6692 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 6693 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 6694 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 6695 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 6696 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 6697 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 6698 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 6699 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 6700 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 6701 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 6702 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 6703 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 6704 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 6705 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 6706 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 6707 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 6708 6709 /* legacy palette */ 6710 #define _LGC_PALETTE_A 0x4a000 6711 #define _LGC_PALETTE_B 0x4a800 6712 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 6713 6714 #define _GAMMA_MODE_A 0x4a480 6715 #define _GAMMA_MODE_B 0x4ac80 6716 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 6717 #define GAMMA_MODE_MODE_MASK (3 << 0) 6718 #define GAMMA_MODE_MODE_8BIT (0 << 0) 6719 #define GAMMA_MODE_MODE_10BIT (1 << 0) 6720 #define GAMMA_MODE_MODE_12BIT (2 << 0) 6721 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 6722 6723 /* DMC/CSR */ 6724 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 6725 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 6726 #define CSR_HTP_ADDR_SKL 0x00500034 6727 #define CSR_SSP_BASE _MMIO(0x8F074) 6728 #define CSR_HTP_SKL _MMIO(0x8F004) 6729 #define CSR_LAST_WRITE _MMIO(0x8F034) 6730 #define CSR_LAST_WRITE_VALUE 0xc003b400 6731 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 6732 #define CSR_MMIO_START_RANGE 0x80000 6733 #define CSR_MMIO_END_RANGE 0x8FFFF 6734 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 6735 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 6736 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 6737 6738 /* interrupts */ 6739 #define DE_MASTER_IRQ_CONTROL (1 << 31) 6740 #define DE_SPRITEB_FLIP_DONE (1 << 29) 6741 #define DE_SPRITEA_FLIP_DONE (1 << 28) 6742 #define DE_PLANEB_FLIP_DONE (1 << 27) 6743 #define DE_PLANEA_FLIP_DONE (1 << 26) 6744 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 6745 #define DE_PCU_EVENT (1 << 25) 6746 #define DE_GTT_FAULT (1 << 24) 6747 #define DE_POISON (1 << 23) 6748 #define DE_PERFORM_COUNTER (1 << 22) 6749 #define DE_PCH_EVENT (1 << 21) 6750 #define DE_AUX_CHANNEL_A (1 << 20) 6751 #define DE_DP_A_HOTPLUG (1 << 19) 6752 #define DE_GSE (1 << 18) 6753 #define DE_PIPEB_VBLANK (1 << 15) 6754 #define DE_PIPEB_EVEN_FIELD (1 << 14) 6755 #define DE_PIPEB_ODD_FIELD (1 << 13) 6756 #define DE_PIPEB_LINE_COMPARE (1 << 12) 6757 #define DE_PIPEB_VSYNC (1 << 11) 6758 #define DE_PIPEB_CRC_DONE (1 << 10) 6759 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 6760 #define DE_PIPEA_VBLANK (1 << 7) 6761 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 6762 #define DE_PIPEA_EVEN_FIELD (1 << 6) 6763 #define DE_PIPEA_ODD_FIELD (1 << 5) 6764 #define DE_PIPEA_LINE_COMPARE (1 << 4) 6765 #define DE_PIPEA_VSYNC (1 << 3) 6766 #define DE_PIPEA_CRC_DONE (1 << 2) 6767 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 6768 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 6769 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 6770 6771 /* More Ivybridge lolz */ 6772 #define DE_ERR_INT_IVB (1<<30) 6773 #define DE_GSE_IVB (1<<29) 6774 #define DE_PCH_EVENT_IVB (1<<28) 6775 #define DE_DP_A_HOTPLUG_IVB (1<<27) 6776 #define DE_AUX_CHANNEL_A_IVB (1<<26) 6777 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 6778 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 6779 #define DE_PIPEC_VBLANK_IVB (1<<10) 6780 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 6781 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 6782 #define DE_PIPEB_VBLANK_IVB (1<<5) 6783 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 6784 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 6785 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 6786 #define DE_PIPEA_VBLANK_IVB (1<<0) 6787 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 6788 6789 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 6790 #define MASTER_INTERRUPT_ENABLE (1<<31) 6791 6792 #define DEISR _MMIO(0x44000) 6793 #define DEIMR _MMIO(0x44004) 6794 #define DEIIR _MMIO(0x44008) 6795 #define DEIER _MMIO(0x4400c) 6796 6797 #define GTISR _MMIO(0x44010) 6798 #define GTIMR _MMIO(0x44014) 6799 #define GTIIR _MMIO(0x44018) 6800 #define GTIER _MMIO(0x4401c) 6801 6802 #define GEN8_MASTER_IRQ _MMIO(0x44200) 6803 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 6804 #define GEN8_PCU_IRQ (1<<30) 6805 #define GEN8_DE_PCH_IRQ (1<<23) 6806 #define GEN8_DE_MISC_IRQ (1<<22) 6807 #define GEN8_DE_PORT_IRQ (1<<20) 6808 #define GEN8_DE_PIPE_C_IRQ (1<<18) 6809 #define GEN8_DE_PIPE_B_IRQ (1<<17) 6810 #define GEN8_DE_PIPE_A_IRQ (1<<16) 6811 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe))) 6812 #define GEN8_GT_VECS_IRQ (1<<6) 6813 #define GEN8_GT_GUC_IRQ (1<<5) 6814 #define GEN8_GT_PM_IRQ (1<<4) 6815 #define GEN8_GT_VCS2_IRQ (1<<3) 6816 #define GEN8_GT_VCS1_IRQ (1<<2) 6817 #define GEN8_GT_BCS_IRQ (1<<1) 6818 #define GEN8_GT_RCS_IRQ (1<<0) 6819 6820 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 6821 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 6822 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 6823 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 6824 6825 #define GEN9_GUC_TO_HOST_INT_EVENT (1<<31) 6826 #define GEN9_GUC_EXEC_ERROR_EVENT (1<<30) 6827 #define GEN9_GUC_DISPLAY_EVENT (1<<29) 6828 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28) 6829 #define GEN9_GUC_IOMMU_MSG_EVENT (1<<27) 6830 #define GEN9_GUC_DB_RING_EVENT (1<<26) 6831 #define GEN9_GUC_DMA_DONE_EVENT (1<<25) 6832 #define GEN9_GUC_FATAL_ERROR_EVENT (1<<24) 6833 #define GEN9_GUC_NOTIFICATION_EVENT (1<<23) 6834 6835 #define GEN8_RCS_IRQ_SHIFT 0 6836 #define GEN8_BCS_IRQ_SHIFT 16 6837 #define GEN8_VCS1_IRQ_SHIFT 0 6838 #define GEN8_VCS2_IRQ_SHIFT 16 6839 #define GEN8_VECS_IRQ_SHIFT 0 6840 #define GEN8_WD_IRQ_SHIFT 16 6841 6842 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 6843 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 6844 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 6845 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 6846 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 6847 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 6848 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 6849 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 6850 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 6851 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 6852 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 6853 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 6854 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 6855 #define GEN8_PIPE_VSYNC (1 << 1) 6856 #define GEN8_PIPE_VBLANK (1 << 0) 6857 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 6858 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 6859 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 6860 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 6861 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 6862 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 6863 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 6864 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 6865 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 6866 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 6867 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 6868 (GEN8_PIPE_CURSOR_FAULT | \ 6869 GEN8_PIPE_SPRITE_FAULT | \ 6870 GEN8_PIPE_PRIMARY_FAULT) 6871 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 6872 (GEN9_PIPE_CURSOR_FAULT | \ 6873 GEN9_PIPE_PLANE4_FAULT | \ 6874 GEN9_PIPE_PLANE3_FAULT | \ 6875 GEN9_PIPE_PLANE2_FAULT | \ 6876 GEN9_PIPE_PLANE1_FAULT) 6877 6878 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 6879 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 6880 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 6881 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 6882 #define GEN9_AUX_CHANNEL_D (1 << 27) 6883 #define GEN9_AUX_CHANNEL_C (1 << 26) 6884 #define GEN9_AUX_CHANNEL_B (1 << 25) 6885 #define BXT_DE_PORT_HP_DDIC (1 << 5) 6886 #define BXT_DE_PORT_HP_DDIB (1 << 4) 6887 #define BXT_DE_PORT_HP_DDIA (1 << 3) 6888 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 6889 BXT_DE_PORT_HP_DDIB | \ 6890 BXT_DE_PORT_HP_DDIC) 6891 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 6892 #define BXT_DE_PORT_GMBUS (1 << 1) 6893 #define GEN8_AUX_CHANNEL_A (1 << 0) 6894 6895 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 6896 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 6897 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 6898 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 6899 #define GEN8_DE_MISC_GSE (1 << 27) 6900 6901 #define GEN8_PCU_ISR _MMIO(0x444e0) 6902 #define GEN8_PCU_IMR _MMIO(0x444e4) 6903 #define GEN8_PCU_IIR _MMIO(0x444e8) 6904 #define GEN8_PCU_IER _MMIO(0x444ec) 6905 6906 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 6907 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 6908 #define ILK_ELPIN_409_SELECT (1 << 25) 6909 #define ILK_DPARB_GATE (1<<22) 6910 #define ILK_VSDPFD_FULL (1<<21) 6911 #define FUSE_STRAP _MMIO(0x42014) 6912 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 6913 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 6914 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 6915 #define IVB_PIPE_C_DISABLE (1 << 28) 6916 #define ILK_HDCP_DISABLE (1 << 25) 6917 #define ILK_eDP_A_DISABLE (1 << 24) 6918 #define HSW_CDCLK_LIMIT (1 << 24) 6919 #define ILK_DESKTOP (1 << 23) 6920 6921 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 6922 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 6923 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 6924 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 6925 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 6926 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 6927 6928 #define IVB_CHICKEN3 _MMIO(0x4200c) 6929 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 6930 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 6931 6932 #define CHICKEN_PAR1_1 _MMIO(0x42080) 6933 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 6934 #define DPA_MASK_VBLANK_SRD (1 << 15) 6935 #define FORCE_ARB_IDLE_PLANES (1 << 14) 6936 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 6937 6938 #define CHICKEN_PAR2_1 _MMIO(0x42090) 6939 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 6940 6941 #define CHICKEN_MISC_2 _MMIO(0x42084) 6942 #define CNL_COMP_PWR_DOWN (1 << 23) 6943 #define GLK_CL2_PWR_DOWN (1 << 12) 6944 #define GLK_CL1_PWR_DOWN (1 << 11) 6945 #define GLK_CL0_PWR_DOWN (1 << 10) 6946 6947 #define CHICKEN_MISC_4 _MMIO(0x4208c) 6948 #define FBC_STRIDE_OVERRIDE (1 << 13) 6949 #define FBC_STRIDE_MASK 0x1FFF 6950 6951 #define _CHICKEN_PIPESL_1_A 0x420b0 6952 #define _CHICKEN_PIPESL_1_B 0x420b4 6953 #define HSW_FBCQ_DIS (1 << 22) 6954 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 6955 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 6956 6957 #define CHICKEN_TRANS_A 0x420c0 6958 #define CHICKEN_TRANS_B 0x420c4 6959 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B) 6960 #define PSR2_VSC_ENABLE_PROG_HEADER (1<<12) 6961 #define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15) 6962 6963 #define DISP_ARB_CTL _MMIO(0x45000) 6964 #define DISP_FBC_MEMORY_WAKE (1<<31) 6965 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 6966 #define DISP_FBC_WM_DIS (1<<15) 6967 #define DISP_ARB_CTL2 _MMIO(0x45004) 6968 #define DISP_DATA_PARTITION_5_6 (1<<6) 6969 #define DISP_IPC_ENABLE (1<<3) 6970 #define DBUF_CTL _MMIO(0x45008) 6971 #define DBUF_POWER_REQUEST (1<<31) 6972 #define DBUF_POWER_STATE (1<<30) 6973 #define GEN7_MSG_CTL _MMIO(0x45010) 6974 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 6975 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 6976 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 6977 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 6978 6979 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 6980 #define MASK_WAKEMEM (1<<13) 6981 6982 #define SKL_DFSM _MMIO(0x51000) 6983 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 6984 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 6985 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 6986 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 6987 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 6988 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 6989 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 6990 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 6991 6992 #define SKL_DSSM _MMIO(0x51004) 6993 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) 6994 6995 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 6996 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) 6997 6998 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 6999 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) 7000 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10) 7001 7002 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 7003 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 7004 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 7005 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0) 7006 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 7007 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 7008 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 7009 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 7010 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 7011 7012 /* GEN7 chicken */ 7013 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 7014 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 7015 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) 7016 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 7017 # define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13) 7018 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12) 7019 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8) 7020 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 7021 7022 #define HIZ_CHICKEN _MMIO(0x7018) 7023 # define CHV_HZ_8X8_MODE_IN_1X (1<<15) 7024 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) 7025 7026 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 7027 #define DISABLE_PIXEL_MASK_CAMMING (1<<14) 7028 7029 #define GEN7_L3SQCREG1 _MMIO(0xB010) 7030 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 7031 7032 #define GEN8_L3SQCREG1 _MMIO(0xB100) 7033 /* 7034 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 7035 * Using the formula in BSpec leads to a hang, while the formula here works 7036 * fine and matches the formulas for all other platforms. A BSpec change 7037 * request has been filed to clarify this. 7038 */ 7039 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 7040 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 7041 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 7042 7043 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 7044 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 7045 #define GEN7_L3AGDIS (1<<19) 7046 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 7047 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 7048 7049 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 7050 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 7051 7052 #define GEN7_L3SQCREG4 _MMIO(0xb034) 7053 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 7054 7055 #define GEN8_L3SQCREG4 _MMIO(0xb118) 7056 #define GEN8_LQSC_RO_PERF_DIS (1<<27) 7057 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) 7058 7059 /* GEN8 chicken */ 7060 #define HDC_CHICKEN0 _MMIO(0x7300) 7061 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) 7062 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) 7063 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 7064 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 7065 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) 7066 #define HDC_FORCE_NON_COHERENT (1<<4) 7067 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) 7068 7069 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 7070 7071 /* GEN9 chicken */ 7072 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 7073 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 7074 7075 /* WaCatErrorRejectionIssue */ 7076 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 7077 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 7078 7079 #define HSW_SCRATCH1 _MMIO(0xb038) 7080 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 7081 7082 #define BDW_SCRATCH1 _MMIO(0xb11c) 7083 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) 7084 7085 /* PCH */ 7086 7087 /* south display engine interrupt: IBX */ 7088 #define SDE_AUDIO_POWER_D (1 << 27) 7089 #define SDE_AUDIO_POWER_C (1 << 26) 7090 #define SDE_AUDIO_POWER_B (1 << 25) 7091 #define SDE_AUDIO_POWER_SHIFT (25) 7092 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 7093 #define SDE_GMBUS (1 << 24) 7094 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 7095 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 7096 #define SDE_AUDIO_HDCP_MASK (3 << 22) 7097 #define SDE_AUDIO_TRANSB (1 << 21) 7098 #define SDE_AUDIO_TRANSA (1 << 20) 7099 #define SDE_AUDIO_TRANS_MASK (3 << 20) 7100 #define SDE_POISON (1 << 19) 7101 /* 18 reserved */ 7102 #define SDE_FDI_RXB (1 << 17) 7103 #define SDE_FDI_RXA (1 << 16) 7104 #define SDE_FDI_MASK (3 << 16) 7105 #define SDE_AUXD (1 << 15) 7106 #define SDE_AUXC (1 << 14) 7107 #define SDE_AUXB (1 << 13) 7108 #define SDE_AUX_MASK (7 << 13) 7109 /* 12 reserved */ 7110 #define SDE_CRT_HOTPLUG (1 << 11) 7111 #define SDE_PORTD_HOTPLUG (1 << 10) 7112 #define SDE_PORTC_HOTPLUG (1 << 9) 7113 #define SDE_PORTB_HOTPLUG (1 << 8) 7114 #define SDE_SDVOB_HOTPLUG (1 << 6) 7115 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 7116 SDE_SDVOB_HOTPLUG | \ 7117 SDE_PORTB_HOTPLUG | \ 7118 SDE_PORTC_HOTPLUG | \ 7119 SDE_PORTD_HOTPLUG) 7120 #define SDE_TRANSB_CRC_DONE (1 << 5) 7121 #define SDE_TRANSB_CRC_ERR (1 << 4) 7122 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 7123 #define SDE_TRANSA_CRC_DONE (1 << 2) 7124 #define SDE_TRANSA_CRC_ERR (1 << 1) 7125 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 7126 #define SDE_TRANS_MASK (0x3f) 7127 7128 /* south display engine interrupt: CPT/PPT */ 7129 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 7130 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 7131 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 7132 #define SDE_AUDIO_POWER_SHIFT_CPT 29 7133 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 7134 #define SDE_AUXD_CPT (1 << 27) 7135 #define SDE_AUXC_CPT (1 << 26) 7136 #define SDE_AUXB_CPT (1 << 25) 7137 #define SDE_AUX_MASK_CPT (7 << 25) 7138 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 7139 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 7140 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 7141 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 7142 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 7143 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 7144 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 7145 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 7146 SDE_SDVOB_HOTPLUG_CPT | \ 7147 SDE_PORTD_HOTPLUG_CPT | \ 7148 SDE_PORTC_HOTPLUG_CPT | \ 7149 SDE_PORTB_HOTPLUG_CPT) 7150 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 7151 SDE_PORTD_HOTPLUG_CPT | \ 7152 SDE_PORTC_HOTPLUG_CPT | \ 7153 SDE_PORTB_HOTPLUG_CPT | \ 7154 SDE_PORTA_HOTPLUG_SPT) 7155 #define SDE_GMBUS_CPT (1 << 17) 7156 #define SDE_ERROR_CPT (1 << 16) 7157 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 7158 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 7159 #define SDE_FDI_RXC_CPT (1 << 8) 7160 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 7161 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 7162 #define SDE_FDI_RXB_CPT (1 << 4) 7163 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 7164 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 7165 #define SDE_FDI_RXA_CPT (1 << 0) 7166 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 7167 SDE_AUDIO_CP_REQ_B_CPT | \ 7168 SDE_AUDIO_CP_REQ_A_CPT) 7169 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 7170 SDE_AUDIO_CP_CHG_B_CPT | \ 7171 SDE_AUDIO_CP_CHG_A_CPT) 7172 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 7173 SDE_FDI_RXB_CPT | \ 7174 SDE_FDI_RXA_CPT) 7175 7176 #define SDEISR _MMIO(0xc4000) 7177 #define SDEIMR _MMIO(0xc4004) 7178 #define SDEIIR _MMIO(0xc4008) 7179 #define SDEIER _MMIO(0xc400c) 7180 7181 #define SERR_INT _MMIO(0xc4040) 7182 #define SERR_INT_POISON (1<<31) 7183 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 7184 7185 /* digital port hotplug */ 7186 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 7187 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 7188 #define BXT_DDIA_HPD_INVERT (1 << 27) 7189 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 7190 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 7191 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 7192 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 7193 #define PORTD_HOTPLUG_ENABLE (1 << 20) 7194 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 7195 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 7196 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 7197 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 7198 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 7199 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 7200 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 7201 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 7202 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 7203 #define PORTC_HOTPLUG_ENABLE (1 << 12) 7204 #define BXT_DDIC_HPD_INVERT (1 << 11) 7205 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 7206 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 7207 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 7208 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 7209 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 7210 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 7211 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 7212 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 7213 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 7214 #define PORTB_HOTPLUG_ENABLE (1 << 4) 7215 #define BXT_DDIB_HPD_INVERT (1 << 3) 7216 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 7217 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 7218 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 7219 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 7220 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 7221 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 7222 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 7223 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 7224 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 7225 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 7226 BXT_DDIB_HPD_INVERT | \ 7227 BXT_DDIC_HPD_INVERT) 7228 7229 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 7230 #define PORTE_HOTPLUG_ENABLE (1 << 4) 7231 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 7232 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 7233 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 7234 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 7235 7236 #define PCH_GPIOA _MMIO(0xc5010) 7237 #define PCH_GPIOB _MMIO(0xc5014) 7238 #define PCH_GPIOC _MMIO(0xc5018) 7239 #define PCH_GPIOD _MMIO(0xc501c) 7240 #define PCH_GPIOE _MMIO(0xc5020) 7241 #define PCH_GPIOF _MMIO(0xc5024) 7242 7243 #define PCH_GMBUS0 _MMIO(0xc5100) 7244 #define PCH_GMBUS1 _MMIO(0xc5104) 7245 #define PCH_GMBUS2 _MMIO(0xc5108) 7246 #define PCH_GMBUS3 _MMIO(0xc510c) 7247 #define PCH_GMBUS4 _MMIO(0xc5110) 7248 #define PCH_GMBUS5 _MMIO(0xc5120) 7249 7250 #define _PCH_DPLL_A 0xc6014 7251 #define _PCH_DPLL_B 0xc6018 7252 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 7253 7254 #define _PCH_FPA0 0xc6040 7255 #define FP_CB_TUNE (0x3<<22) 7256 #define _PCH_FPA1 0xc6044 7257 #define _PCH_FPB0 0xc6048 7258 #define _PCH_FPB1 0xc604c 7259 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 7260 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 7261 7262 #define PCH_DPLL_TEST _MMIO(0xc606c) 7263 7264 #define PCH_DREF_CONTROL _MMIO(0xC6200) 7265 #define DREF_CONTROL_MASK 0x7fc3 7266 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 7267 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 7268 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 7269 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 7270 #define DREF_SSC_SOURCE_DISABLE (0<<11) 7271 #define DREF_SSC_SOURCE_ENABLE (2<<11) 7272 #define DREF_SSC_SOURCE_MASK (3<<11) 7273 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 7274 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 7275 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 7276 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 7277 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 7278 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 7279 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 7280 #define DREF_SSC4_DOWNSPREAD (0<<6) 7281 #define DREF_SSC4_CENTERSPREAD (1<<6) 7282 #define DREF_SSC1_DISABLE (0<<1) 7283 #define DREF_SSC1_ENABLE (1<<1) 7284 #define DREF_SSC4_DISABLE (0) 7285 #define DREF_SSC4_ENABLE (1) 7286 7287 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 7288 #define FDL_TP1_TIMER_SHIFT 12 7289 #define FDL_TP1_TIMER_MASK (3<<12) 7290 #define FDL_TP2_TIMER_SHIFT 10 7291 #define FDL_TP2_TIMER_MASK (3<<10) 7292 #define RAWCLK_FREQ_MASK 0x3ff 7293 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 7294 #define CNP_RAWCLK_DIV(div) ((div) << 16) 7295 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 7296 #define CNP_RAWCLK_FRAC(frac) ((frac) << 26) 7297 7298 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 7299 7300 #define PCH_SSC4_PARMS _MMIO(0xc6210) 7301 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 7302 7303 #define PCH_DPLL_SEL _MMIO(0xc7000) 7304 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 7305 #define TRANS_DPLLA_SEL(pipe) 0 7306 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 7307 7308 /* transcoder */ 7309 7310 #define _PCH_TRANS_HTOTAL_A 0xe0000 7311 #define TRANS_HTOTAL_SHIFT 16 7312 #define TRANS_HACTIVE_SHIFT 0 7313 #define _PCH_TRANS_HBLANK_A 0xe0004 7314 #define TRANS_HBLANK_END_SHIFT 16 7315 #define TRANS_HBLANK_START_SHIFT 0 7316 #define _PCH_TRANS_HSYNC_A 0xe0008 7317 #define TRANS_HSYNC_END_SHIFT 16 7318 #define TRANS_HSYNC_START_SHIFT 0 7319 #define _PCH_TRANS_VTOTAL_A 0xe000c 7320 #define TRANS_VTOTAL_SHIFT 16 7321 #define TRANS_VACTIVE_SHIFT 0 7322 #define _PCH_TRANS_VBLANK_A 0xe0010 7323 #define TRANS_VBLANK_END_SHIFT 16 7324 #define TRANS_VBLANK_START_SHIFT 0 7325 #define _PCH_TRANS_VSYNC_A 0xe0014 7326 #define TRANS_VSYNC_END_SHIFT 16 7327 #define TRANS_VSYNC_START_SHIFT 0 7328 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 7329 7330 #define _PCH_TRANSA_DATA_M1 0xe0030 7331 #define _PCH_TRANSA_DATA_N1 0xe0034 7332 #define _PCH_TRANSA_DATA_M2 0xe0038 7333 #define _PCH_TRANSA_DATA_N2 0xe003c 7334 #define _PCH_TRANSA_LINK_M1 0xe0040 7335 #define _PCH_TRANSA_LINK_N1 0xe0044 7336 #define _PCH_TRANSA_LINK_M2 0xe0048 7337 #define _PCH_TRANSA_LINK_N2 0xe004c 7338 7339 /* Per-transcoder DIP controls (PCH) */ 7340 #define _VIDEO_DIP_CTL_A 0xe0200 7341 #define _VIDEO_DIP_DATA_A 0xe0208 7342 #define _VIDEO_DIP_GCP_A 0xe0210 7343 #define GCP_COLOR_INDICATION (1 << 2) 7344 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 7345 #define GCP_AV_MUTE (1 << 0) 7346 7347 #define _VIDEO_DIP_CTL_B 0xe1200 7348 #define _VIDEO_DIP_DATA_B 0xe1208 7349 #define _VIDEO_DIP_GCP_B 0xe1210 7350 7351 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 7352 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 7353 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 7354 7355 /* Per-transcoder DIP controls (VLV) */ 7356 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 7357 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 7358 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 7359 7360 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 7361 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 7362 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 7363 7364 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 7365 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 7366 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 7367 7368 #define VLV_TVIDEO_DIP_CTL(pipe) \ 7369 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 7370 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 7371 #define VLV_TVIDEO_DIP_DATA(pipe) \ 7372 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 7373 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 7374 #define VLV_TVIDEO_DIP_GCP(pipe) \ 7375 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 7376 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 7377 7378 /* Haswell DIP controls */ 7379 7380 #define _HSW_VIDEO_DIP_CTL_A 0x60200 7381 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 7382 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 7383 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 7384 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 7385 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 7386 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 7387 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 7388 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 7389 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 7390 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 7391 #define _HSW_VIDEO_DIP_GCP_A 0x60210 7392 7393 #define _HSW_VIDEO_DIP_CTL_B 0x61200 7394 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 7395 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 7396 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 7397 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 7398 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 7399 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 7400 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 7401 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 7402 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 7403 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 7404 #define _HSW_VIDEO_DIP_GCP_B 0x61210 7405 7406 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 7407 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 7408 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 7409 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 7410 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 7411 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 7412 7413 #define _HSW_STEREO_3D_CTL_A 0x70020 7414 #define S3D_ENABLE (1<<31) 7415 #define _HSW_STEREO_3D_CTL_B 0x71020 7416 7417 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 7418 7419 #define _PCH_TRANS_HTOTAL_B 0xe1000 7420 #define _PCH_TRANS_HBLANK_B 0xe1004 7421 #define _PCH_TRANS_HSYNC_B 0xe1008 7422 #define _PCH_TRANS_VTOTAL_B 0xe100c 7423 #define _PCH_TRANS_VBLANK_B 0xe1010 7424 #define _PCH_TRANS_VSYNC_B 0xe1014 7425 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 7426 7427 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 7428 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 7429 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 7430 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 7431 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 7432 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 7433 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 7434 7435 #define _PCH_TRANSB_DATA_M1 0xe1030 7436 #define _PCH_TRANSB_DATA_N1 0xe1034 7437 #define _PCH_TRANSB_DATA_M2 0xe1038 7438 #define _PCH_TRANSB_DATA_N2 0xe103c 7439 #define _PCH_TRANSB_LINK_M1 0xe1040 7440 #define _PCH_TRANSB_LINK_N1 0xe1044 7441 #define _PCH_TRANSB_LINK_M2 0xe1048 7442 #define _PCH_TRANSB_LINK_N2 0xe104c 7443 7444 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 7445 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 7446 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 7447 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 7448 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 7449 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 7450 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 7451 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 7452 7453 #define _PCH_TRANSACONF 0xf0008 7454 #define _PCH_TRANSBCONF 0xf1008 7455 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 7456 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 7457 #define TRANS_DISABLE (0<<31) 7458 #define TRANS_ENABLE (1<<31) 7459 #define TRANS_STATE_MASK (1<<30) 7460 #define TRANS_STATE_DISABLE (0<<30) 7461 #define TRANS_STATE_ENABLE (1<<30) 7462 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 7463 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 7464 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 7465 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 7466 #define TRANS_INTERLACE_MASK (7<<21) 7467 #define TRANS_PROGRESSIVE (0<<21) 7468 #define TRANS_INTERLACED (3<<21) 7469 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 7470 #define TRANS_8BPC (0<<5) 7471 #define TRANS_10BPC (1<<5) 7472 #define TRANS_6BPC (2<<5) 7473 #define TRANS_12BPC (3<<5) 7474 7475 #define _TRANSA_CHICKEN1 0xf0060 7476 #define _TRANSB_CHICKEN1 0xf1060 7477 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 7478 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10) 7479 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 7480 #define _TRANSA_CHICKEN2 0xf0064 7481 #define _TRANSB_CHICKEN2 0xf1064 7482 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 7483 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 7484 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 7485 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 7486 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 7487 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 7488 7489 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 7490 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 7491 #define FDIA_PHASE_SYNC_SHIFT_EN 18 7492 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 7493 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 7494 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 7495 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 7496 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 7497 #define SPT_PWM_GRANULARITY (1<<0) 7498 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 7499 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 7500 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 7501 #define LPT_PWM_GRANULARITY (1<<5) 7502 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 7503 7504 #define _FDI_RXA_CHICKEN 0xc200c 7505 #define _FDI_RXB_CHICKEN 0xc2010 7506 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 7507 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 7508 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 7509 7510 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 7511 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 7512 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 7513 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 7514 #define CNP_PWM_CGE_GATING_DISABLE (1<<13) 7515 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 7516 7517 /* CPU: FDI_TX */ 7518 #define _FDI_TXA_CTL 0x60100 7519 #define _FDI_TXB_CTL 0x61100 7520 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 7521 #define FDI_TX_DISABLE (0<<31) 7522 #define FDI_TX_ENABLE (1<<31) 7523 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 7524 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 7525 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 7526 #define FDI_LINK_TRAIN_NONE (3<<28) 7527 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 7528 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 7529 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 7530 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 7531 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 7532 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 7533 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 7534 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 7535 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 7536 SNB has different settings. */ 7537 /* SNB A-stepping */ 7538 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 7539 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 7540 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 7541 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 7542 /* SNB B-stepping */ 7543 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 7544 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 7545 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 7546 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 7547 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 7548 #define FDI_DP_PORT_WIDTH_SHIFT 19 7549 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 7550 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 7551 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 7552 /* Ironlake: hardwired to 1 */ 7553 #define FDI_TX_PLL_ENABLE (1<<14) 7554 7555 /* Ivybridge has different bits for lolz */ 7556 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 7557 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 7558 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 7559 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 7560 7561 /* both Tx and Rx */ 7562 #define FDI_COMPOSITE_SYNC (1<<11) 7563 #define FDI_LINK_TRAIN_AUTO (1<<10) 7564 #define FDI_SCRAMBLING_ENABLE (0<<7) 7565 #define FDI_SCRAMBLING_DISABLE (1<<7) 7566 7567 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 7568 #define _FDI_RXA_CTL 0xf000c 7569 #define _FDI_RXB_CTL 0xf100c 7570 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 7571 #define FDI_RX_ENABLE (1<<31) 7572 /* train, dp width same as FDI_TX */ 7573 #define FDI_FS_ERRC_ENABLE (1<<27) 7574 #define FDI_FE_ERRC_ENABLE (1<<26) 7575 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 7576 #define FDI_8BPC (0<<16) 7577 #define FDI_10BPC (1<<16) 7578 #define FDI_6BPC (2<<16) 7579 #define FDI_12BPC (3<<16) 7580 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 7581 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 7582 #define FDI_RX_PLL_ENABLE (1<<13) 7583 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 7584 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 7585 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 7586 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 7587 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 7588 #define FDI_PCDCLK (1<<4) 7589 /* CPT */ 7590 #define FDI_AUTO_TRAINING (1<<10) 7591 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 7592 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 7593 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 7594 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 7595 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 7596 7597 #define _FDI_RXA_MISC 0xf0010 7598 #define _FDI_RXB_MISC 0xf1010 7599 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 7600 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 7601 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 7602 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 7603 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 7604 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 7605 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 7606 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 7607 7608 #define _FDI_RXA_TUSIZE1 0xf0030 7609 #define _FDI_RXA_TUSIZE2 0xf0038 7610 #define _FDI_RXB_TUSIZE1 0xf1030 7611 #define _FDI_RXB_TUSIZE2 0xf1038 7612 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 7613 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 7614 7615 /* FDI_RX interrupt register format */ 7616 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 7617 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 7618 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 7619 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 7620 #define FDI_RX_FS_CODE_ERR (1<<6) 7621 #define FDI_RX_FE_CODE_ERR (1<<5) 7622 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 7623 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 7624 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 7625 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 7626 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 7627 7628 #define _FDI_RXA_IIR 0xf0014 7629 #define _FDI_RXA_IMR 0xf0018 7630 #define _FDI_RXB_IIR 0xf1014 7631 #define _FDI_RXB_IMR 0xf1018 7632 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 7633 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 7634 7635 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 7636 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 7637 7638 #define PCH_LVDS _MMIO(0xe1180) 7639 #define LVDS_DETECTED (1 << 1) 7640 7641 #define _PCH_DP_B 0xe4100 7642 #define PCH_DP_B _MMIO(_PCH_DP_B) 7643 #define _PCH_DPB_AUX_CH_CTL 0xe4110 7644 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 7645 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 7646 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 7647 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 7648 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 7649 7650 #define _PCH_DP_C 0xe4200 7651 #define PCH_DP_C _MMIO(_PCH_DP_C) 7652 #define _PCH_DPC_AUX_CH_CTL 0xe4210 7653 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 7654 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 7655 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 7656 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 7657 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 7658 7659 #define _PCH_DP_D 0xe4300 7660 #define PCH_DP_D _MMIO(_PCH_DP_D) 7661 #define _PCH_DPD_AUX_CH_CTL 0xe4310 7662 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 7663 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 7664 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 7665 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 7666 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 7667 7668 #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 7669 #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 7670 7671 /* CPT */ 7672 #define PORT_TRANS_A_SEL_CPT 0 7673 #define PORT_TRANS_B_SEL_CPT (1<<29) 7674 #define PORT_TRANS_C_SEL_CPT (2<<29) 7675 #define PORT_TRANS_SEL_MASK (3<<29) 7676 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 7677 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 7678 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 7679 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 7680 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 7681 7682 #define _TRANS_DP_CTL_A 0xe0300 7683 #define _TRANS_DP_CTL_B 0xe1300 7684 #define _TRANS_DP_CTL_C 0xe2300 7685 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 7686 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 7687 #define TRANS_DP_PORT_SEL_B (0<<29) 7688 #define TRANS_DP_PORT_SEL_C (1<<29) 7689 #define TRANS_DP_PORT_SEL_D (2<<29) 7690 #define TRANS_DP_PORT_SEL_NONE (3<<29) 7691 #define TRANS_DP_PORT_SEL_MASK (3<<29) 7692 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) 7693 #define TRANS_DP_AUDIO_ONLY (1<<26) 7694 #define TRANS_DP_ENH_FRAMING (1<<18) 7695 #define TRANS_DP_8BPC (0<<9) 7696 #define TRANS_DP_10BPC (1<<9) 7697 #define TRANS_DP_6BPC (2<<9) 7698 #define TRANS_DP_12BPC (3<<9) 7699 #define TRANS_DP_BPC_MASK (3<<9) 7700 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 7701 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 7702 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 7703 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 7704 #define TRANS_DP_SYNC_MASK (3<<3) 7705 7706 /* SNB eDP training params */ 7707 /* SNB A-stepping */ 7708 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 7709 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 7710 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 7711 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 7712 /* SNB B-stepping */ 7713 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 7714 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 7715 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 7716 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 7717 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 7718 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 7719 7720 /* IVB */ 7721 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 7722 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 7723 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 7724 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 7725 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 7726 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 7727 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 7728 7729 /* legacy values */ 7730 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 7731 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 7732 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 7733 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 7734 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 7735 7736 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 7737 7738 #define VLV_PMWGICZ _MMIO(0x1300a4) 7739 7740 #define RC6_LOCATION _MMIO(0xD40) 7741 #define RC6_CTX_IN_DRAM (1 << 0) 7742 #define RC6_CTX_BASE _MMIO(0xD48) 7743 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 7744 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 7745 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 7746 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 7747 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 7748 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 7749 #define IDLE_TIME_MASK 0xFFFFF 7750 #define FORCEWAKE _MMIO(0xA18C) 7751 #define FORCEWAKE_VLV _MMIO(0x1300b0) 7752 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 7753 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 7754 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 7755 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 7756 #define FORCEWAKE_ACK _MMIO(0x130090) 7757 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 7758 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 7759 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 7760 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 7761 7762 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 7763 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 7764 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 7765 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 7766 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 7767 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 7768 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 7769 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 7770 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 7771 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 7772 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 7773 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 7774 #define FORCEWAKE_KERNEL 0x1 7775 #define FORCEWAKE_USER 0x2 7776 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 7777 #define ECOBUS _MMIO(0xa180) 7778 #define FORCEWAKE_MT_ENABLE (1<<5) 7779 #define VLV_SPAREG2H _MMIO(0xA194) 7780 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) 7781 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 7782 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 7783 7784 #define GTFIFODBG _MMIO(0x120000) 7785 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 7786 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 7787 #define GT_FIFO_SBDROPERR (1<<6) 7788 #define GT_FIFO_BLOBDROPERR (1<<5) 7789 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 7790 #define GT_FIFO_DROPERR (1<<3) 7791 #define GT_FIFO_OVFERR (1<<2) 7792 #define GT_FIFO_IAWRERR (1<<1) 7793 #define GT_FIFO_IARDERR (1<<0) 7794 7795 #define GTFIFOCTL _MMIO(0x120008) 7796 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 7797 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 7798 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 7799 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 7800 7801 #define HSW_IDICR _MMIO(0x9008) 7802 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 7803 #define HSW_EDRAM_CAP _MMIO(0x120010) 7804 #define EDRAM_ENABLED 0x1 7805 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 7806 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 7807 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 7808 7809 #define GEN6_UCGCTL1 _MMIO(0x9400) 7810 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 7811 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 7812 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 7813 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 7814 7815 #define GEN6_UCGCTL2 _MMIO(0x9404) 7816 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 7817 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 7818 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 7819 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 7820 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 7821 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 7822 7823 #define GEN6_UCGCTL3 _MMIO(0x9408) 7824 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 7825 7826 #define GEN7_UCGCTL4 _MMIO(0x940c) 7827 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 7828 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14) 7829 7830 #define GEN6_RCGCTL1 _MMIO(0x9410) 7831 #define GEN6_RCGCTL2 _MMIO(0x9414) 7832 #define GEN6_RSTCTL _MMIO(0x9420) 7833 7834 #define GEN8_UCGCTL6 _MMIO(0x9430) 7835 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) 7836 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 7837 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) 7838 7839 #define GEN6_GFXPAUSE _MMIO(0xA000) 7840 #define GEN6_RPNSWREQ _MMIO(0xA008) 7841 #define GEN6_TURBO_DISABLE (1<<31) 7842 #define GEN6_FREQUENCY(x) ((x)<<25) 7843 #define HSW_FREQUENCY(x) ((x)<<24) 7844 #define GEN9_FREQUENCY(x) ((x)<<23) 7845 #define GEN6_OFFSET(x) ((x)<<19) 7846 #define GEN6_AGGRESSIVE_TURBO (0<<15) 7847 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 7848 #define GEN6_RC_CONTROL _MMIO(0xA090) 7849 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 7850 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 7851 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 7852 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 7853 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 7854 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 7855 #define GEN7_RC_CTL_TO_MODE (1<<28) 7856 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 7857 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 7858 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 7859 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 7860 #define GEN6_RPSTAT1 _MMIO(0xA01C) 7861 #define GEN6_CAGF_SHIFT 8 7862 #define HSW_CAGF_SHIFT 7 7863 #define GEN9_CAGF_SHIFT 23 7864 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 7865 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 7866 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 7867 #define GEN6_RP_CONTROL _MMIO(0xA024) 7868 #define GEN6_RP_MEDIA_TURBO (1<<11) 7869 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 7870 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 7871 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 7872 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 7873 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 7874 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 7875 #define GEN6_RP_ENABLE (1<<7) 7876 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 7877 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 7878 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 7879 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 7880 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 7881 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 7882 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 7883 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 7884 #define GEN6_RP_EI_MASK 0xffffff 7885 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 7886 #define GEN6_RP_CUR_UP _MMIO(0xA054) 7887 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 7888 #define GEN6_RP_PREV_UP _MMIO(0xA058) 7889 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 7890 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 7891 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 7892 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 7893 #define GEN6_RP_UP_EI _MMIO(0xA068) 7894 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 7895 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 7896 #define GEN6_RPDEUHWTC _MMIO(0xA080) 7897 #define GEN6_RPDEUC _MMIO(0xA084) 7898 #define GEN6_RPDEUCSW _MMIO(0xA088) 7899 #define GEN6_RC_STATE _MMIO(0xA094) 7900 #define RC_SW_TARGET_STATE_SHIFT 16 7901 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 7902 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 7903 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 7904 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 7905 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 7906 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 7907 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 7908 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 7909 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 7910 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 7911 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 7912 #define VLV_RCEDATA _MMIO(0xA0BC) 7913 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 7914 #define GEN6_PMINTRMSK _MMIO(0xA168) 7915 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1<<31) 7916 #define ARAT_EXPIRED_INTRMSK (1<<9) 7917 #define GEN8_MISC_CTRL0 _MMIO(0xA180) 7918 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 7919 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 7920 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 7921 #define GEN9_PG_ENABLE _MMIO(0xA210) 7922 #define GEN9_RENDER_PG_ENABLE (1<<0) 7923 #define GEN9_MEDIA_PG_ENABLE (1<<1) 7924 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 7925 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 7926 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 7927 7928 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 7929 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 7930 #define PIXEL_OVERLAP_CNT_SHIFT 30 7931 7932 #define GEN6_PMISR _MMIO(0x44020) 7933 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 7934 #define GEN6_PMIIR _MMIO(0x44028) 7935 #define GEN6_PMIER _MMIO(0x4402C) 7936 #define GEN6_PM_MBOX_EVENT (1<<25) 7937 #define GEN6_PM_THERMAL_EVENT (1<<24) 7938 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 7939 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 7940 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 7941 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 7942 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 7943 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 7944 GEN6_PM_RP_DOWN_THRESHOLD | \ 7945 GEN6_PM_RP_DOWN_TIMEOUT) 7946 7947 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 7948 #define GEN7_GT_SCRATCH_REG_NUM 8 7949 7950 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 7951 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 7952 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 7953 7954 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 7955 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 7956 #define VLV_COUNT_RANGE_HIGH (1<<15) 7957 #define VLV_MEDIA_RC0_COUNT_EN (1<<5) 7958 #define VLV_RENDER_RC0_COUNT_EN (1<<4) 7959 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 7960 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 7961 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 7962 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 7963 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 7964 7965 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 7966 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 7967 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 7968 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 7969 7970 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 7971 #define GEN6_PCODE_READY (1<<31) 7972 #define GEN6_PCODE_ERROR_MASK 0xFF 7973 #define GEN6_PCODE_SUCCESS 0x0 7974 #define GEN6_PCODE_ILLEGAL_CMD 0x1 7975 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 7976 #define GEN6_PCODE_TIMEOUT 0x3 7977 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 7978 #define GEN7_PCODE_TIMEOUT 0x2 7979 #define GEN7_PCODE_ILLEGAL_DATA 0x3 7980 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 7981 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 7982 #define GEN6_PCODE_READ_RC6VIDS 0x5 7983 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 7984 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 7985 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 7986 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 7987 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 7988 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 7989 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 7990 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 7991 #define SKL_PCODE_CDCLK_CONTROL 0x7 7992 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 7993 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 7994 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 7995 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 7996 #define GEN6_READ_OC_PARAMS 0xc 7997 #define GEN6_PCODE_READ_D_COMP 0x10 7998 #define GEN6_PCODE_WRITE_D_COMP 0x11 7999 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 8000 #define DISPLAY_IPS_CONTROL 0x19 8001 /* See also IPS_CTL */ 8002 #define IPS_PCODE_CONTROL (1 << 30) 8003 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 8004 #define GEN9_PCODE_SAGV_CONTROL 0x21 8005 #define GEN9_SAGV_DISABLE 0x0 8006 #define GEN9_SAGV_IS_DISABLED 0x1 8007 #define GEN9_SAGV_ENABLE 0x3 8008 #define GEN6_PCODE_DATA _MMIO(0x138128) 8009 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 8010 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 8011 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 8012 8013 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 8014 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 8015 #define GEN6_RCn_MASK 7 8016 #define GEN6_RC0 0 8017 #define GEN6_RC3 2 8018 #define GEN6_RC6 3 8019 #define GEN6_RC7 4 8020 8021 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 8022 #define GEN8_LSLICESTAT_MASK 0x7 8023 8024 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 8025 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 8026 #define CHV_SS_PG_ENABLE (1<<1) 8027 #define CHV_EU08_PG_ENABLE (1<<9) 8028 #define CHV_EU19_PG_ENABLE (1<<17) 8029 #define CHV_EU210_PG_ENABLE (1<<25) 8030 8031 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 8032 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 8033 #define CHV_EU311_PG_ENABLE (1<<1) 8034 8035 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4) 8036 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 8037 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) 8038 8039 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8) 8040 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8) 8041 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 8042 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 8043 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 8044 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 8045 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 8046 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 8047 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 8048 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 8049 8050 #define GEN7_MISCCPCTL _MMIO(0x9424) 8051 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 8052 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2) 8053 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) 8054 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) 8055 8056 #define GEN8_GARBCNTL _MMIO(0xB004) 8057 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) 8058 8059 /* IVYBRIDGE DPF */ 8060 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 8061 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 8062 #define GEN7_PARITY_ERROR_VALID (1<<13) 8063 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 8064 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 8065 #define GEN7_PARITY_ERROR_ROW(reg) \ 8066 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 8067 #define GEN7_PARITY_ERROR_BANK(reg) \ 8068 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 8069 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 8070 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 8071 #define GEN7_L3CDERRST1_ENABLE (1<<7) 8072 8073 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 8074 #define GEN7_L3LOG_SIZE 0x80 8075 8076 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 8077 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 8078 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 8079 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 8080 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) 8081 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 8082 8083 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 8084 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) 8085 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) 8086 8087 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 8088 #define FLOW_CONTROL_ENABLE (1<<15) 8089 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 8090 #define STALL_DOP_GATING_DISABLE (1<<5) 8091 #define THROTTLE_12_5 (7<<2) 8092 8093 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 8094 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 8095 #define DOP_CLOCK_GATING_DISABLE (1<<0) 8096 #define PUSH_CONSTANT_DEREF_DISABLE (1<<8) 8097 8098 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 8099 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 8100 8101 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 8102 #define GEN8_ST_PO_DISABLE (1<<13) 8103 8104 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 8105 #define HSW_SAMPLE_C_PERFORMANCE (1<<9) 8106 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 8107 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 8108 #define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4) 8109 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 8110 8111 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 8112 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1<<8) 8113 #define GEN9_ENABLE_YV12_BUGFIX (1<<4) 8114 #define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2) 8115 8116 /* Audio */ 8117 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) 8118 #define INTEL_AUDIO_DEVCL 0x808629FB 8119 #define INTEL_AUDIO_DEVBLC 0x80862801 8120 #define INTEL_AUDIO_DEVCTG 0x80862802 8121 8122 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 8123 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 8124 #define G4X_ELDV_DEVCTG (1 << 14) 8125 #define G4X_ELD_ADDR_MASK (0xf << 5) 8126 #define G4X_ELD_ACK (1 << 4) 8127 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 8128 8129 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 8130 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 8131 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 8132 _IBX_HDMIW_HDMIEDID_B) 8133 #define _IBX_AUD_CNTL_ST_A 0xE20B4 8134 #define _IBX_AUD_CNTL_ST_B 0xE21B4 8135 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 8136 _IBX_AUD_CNTL_ST_B) 8137 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 8138 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 8139 #define IBX_ELD_ACK (1 << 4) 8140 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 8141 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 8142 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 8143 8144 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 8145 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 8146 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 8147 #define _CPT_AUD_CNTL_ST_A 0xE50B4 8148 #define _CPT_AUD_CNTL_ST_B 0xE51B4 8149 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 8150 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 8151 8152 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 8153 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 8154 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 8155 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 8156 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 8157 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 8158 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 8159 8160 /* These are the 4 32-bit write offset registers for each stream 8161 * output buffer. It determines the offset from the 8162 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 8163 */ 8164 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 8165 8166 #define _IBX_AUD_CONFIG_A 0xe2000 8167 #define _IBX_AUD_CONFIG_B 0xe2100 8168 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 8169 #define _CPT_AUD_CONFIG_A 0xe5000 8170 #define _CPT_AUD_CONFIG_B 0xe5100 8171 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 8172 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 8173 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 8174 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 8175 8176 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 8177 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 8178 #define AUD_CONFIG_UPPER_N_SHIFT 20 8179 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 8180 #define AUD_CONFIG_LOWER_N_SHIFT 4 8181 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 8182 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 8183 #define AUD_CONFIG_N(n) \ 8184 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 8185 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 8186 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 8187 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 8188 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 8189 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 8190 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 8191 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 8192 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 8193 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 8194 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 8195 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 8196 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 8197 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 8198 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 8199 8200 /* HSW Audio */ 8201 #define _HSW_AUD_CONFIG_A 0x65000 8202 #define _HSW_AUD_CONFIG_B 0x65100 8203 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 8204 8205 #define _HSW_AUD_MISC_CTRL_A 0x65010 8206 #define _HSW_AUD_MISC_CTRL_B 0x65110 8207 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 8208 8209 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 8210 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 8211 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 8212 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 8213 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 8214 #define AUD_CONFIG_M_MASK 0xfffff 8215 8216 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 8217 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 8218 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 8219 8220 /* Audio Digital Converter */ 8221 #define _HSW_AUD_DIG_CNVT_1 0x65080 8222 #define _HSW_AUD_DIG_CNVT_2 0x65180 8223 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 8224 #define DIP_PORT_SEL_MASK 0x3 8225 8226 #define _HSW_AUD_EDID_DATA_A 0x65050 8227 #define _HSW_AUD_EDID_DATA_B 0x65150 8228 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 8229 8230 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 8231 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 8232 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 8233 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 8234 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 8235 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 8236 8237 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 8238 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 8239 8240 /* HSW Power Wells */ 8241 #define _HSW_PWR_WELL_CTL1 0x45400 8242 #define _HSW_PWR_WELL_CTL2 0x45404 8243 #define _HSW_PWR_WELL_CTL3 0x45408 8244 #define _HSW_PWR_WELL_CTL4 0x4540C 8245 8246 /* 8247 * Each power well control register contains up to 16 (request, status) HW 8248 * flag tuples. The register index and HW flag shift is determined by the 8249 * power well ID (see i915_power_well_id). There are 4 possible sources of 8250 * power well requests each source having its own set of control registers: 8251 * BIOS, DRIVER, KVMR, DEBUG. 8252 */ 8253 #define _HSW_PW_REG_IDX(pw) ((pw) >> 4) 8254 #define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) 8255 /* TODO: Add all PWR_WELL_CTL registers below for new platforms */ 8256 #define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ 8257 _HSW_PWR_WELL_CTL1)) 8258 #define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ 8259 _HSW_PWR_WELL_CTL2)) 8260 #define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) 8261 #define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ 8262 _HSW_PWR_WELL_CTL4)) 8263 8264 #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) 8265 #define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) 8266 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 8267 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 8268 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 8269 #define HSW_PWR_WELL_FORCE_ON (1<<19) 8270 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 8271 8272 /* SKL Fuse Status */ 8273 enum skl_power_gate { 8274 SKL_PG0, 8275 SKL_PG1, 8276 SKL_PG2, 8277 }; 8278 8279 #define SKL_FUSE_STATUS _MMIO(0x42000) 8280 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) 8281 /* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ 8282 #define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) 8283 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 8284 8285 /* Per-pipe DDI Function Control */ 8286 #define _TRANS_DDI_FUNC_CTL_A 0x60400 8287 #define _TRANS_DDI_FUNC_CTL_B 0x61400 8288 #define _TRANS_DDI_FUNC_CTL_C 0x62400 8289 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 8290 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 8291 8292 #define TRANS_DDI_FUNC_ENABLE (1<<31) 8293 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 8294 #define TRANS_DDI_PORT_MASK (7<<28) 8295 #define TRANS_DDI_PORT_SHIFT 28 8296 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 8297 #define TRANS_DDI_PORT_NONE (0<<28) 8298 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 8299 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 8300 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 8301 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 8302 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 8303 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 8304 #define TRANS_DDI_BPC_MASK (7<<20) 8305 #define TRANS_DDI_BPC_8 (0<<20) 8306 #define TRANS_DDI_BPC_10 (1<<20) 8307 #define TRANS_DDI_BPC_6 (2<<20) 8308 #define TRANS_DDI_BPC_12 (3<<20) 8309 #define TRANS_DDI_PVSYNC (1<<17) 8310 #define TRANS_DDI_PHSYNC (1<<16) 8311 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 8312 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 8313 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 8314 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 8315 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 8316 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 8317 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) 8318 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) 8319 #define TRANS_DDI_BFI_ENABLE (1<<4) 8320 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4) 8321 #define TRANS_DDI_HDMI_SCRAMBLING (1<<0) 8322 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 8323 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 8324 | TRANS_DDI_HDMI_SCRAMBLING) 8325 8326 /* DisplayPort Transport Control */ 8327 #define _DP_TP_CTL_A 0x64040 8328 #define _DP_TP_CTL_B 0x64140 8329 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 8330 #define DP_TP_CTL_ENABLE (1<<31) 8331 #define DP_TP_CTL_MODE_SST (0<<27) 8332 #define DP_TP_CTL_MODE_MST (1<<27) 8333 #define DP_TP_CTL_FORCE_ACT (1<<25) 8334 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 8335 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 8336 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 8337 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 8338 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 8339 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 8340 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 8341 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 8342 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 8343 8344 /* DisplayPort Transport Status */ 8345 #define _DP_TP_STATUS_A 0x64044 8346 #define _DP_TP_STATUS_B 0x64144 8347 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 8348 #define DP_TP_STATUS_IDLE_DONE (1<<25) 8349 #define DP_TP_STATUS_ACT_SENT (1<<24) 8350 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 8351 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 8352 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 8353 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 8354 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 8355 8356 /* DDI Buffer Control */ 8357 #define _DDI_BUF_CTL_A 0x64000 8358 #define _DDI_BUF_CTL_B 0x64100 8359 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 8360 #define DDI_BUF_CTL_ENABLE (1<<31) 8361 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 8362 #define DDI_BUF_EMP_MASK (0xf<<24) 8363 #define DDI_BUF_PORT_REVERSAL (1<<16) 8364 #define DDI_BUF_IS_IDLE (1<<7) 8365 #define DDI_A_4_LANES (1<<4) 8366 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 8367 #define DDI_PORT_WIDTH_MASK (7 << 1) 8368 #define DDI_PORT_WIDTH_SHIFT 1 8369 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 8370 8371 /* DDI Buffer Translations */ 8372 #define _DDI_BUF_TRANS_A 0x64E00 8373 #define _DDI_BUF_TRANS_B 0x64E60 8374 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 8375 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 8376 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 8377 8378 /* Sideband Interface (SBI) is programmed indirectly, via 8379 * SBI_ADDR, which contains the register offset; and SBI_DATA, 8380 * which contains the payload */ 8381 #define SBI_ADDR _MMIO(0xC6000) 8382 #define SBI_DATA _MMIO(0xC6004) 8383 #define SBI_CTL_STAT _MMIO(0xC6008) 8384 #define SBI_CTL_DEST_ICLK (0x0<<16) 8385 #define SBI_CTL_DEST_MPHY (0x1<<16) 8386 #define SBI_CTL_OP_IORD (0x2<<8) 8387 #define SBI_CTL_OP_IOWR (0x3<<8) 8388 #define SBI_CTL_OP_CRRD (0x6<<8) 8389 #define SBI_CTL_OP_CRWR (0x7<<8) 8390 #define SBI_RESPONSE_FAIL (0x1<<1) 8391 #define SBI_RESPONSE_SUCCESS (0x0<<1) 8392 #define SBI_BUSY (0x1<<0) 8393 #define SBI_READY (0x0<<0) 8394 8395 /* SBI offsets */ 8396 #define SBI_SSCDIVINTPHASE 0x0200 8397 #define SBI_SSCDIVINTPHASE6 0x0600 8398 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 8399 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1) 8400 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 8401 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 8402 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8) 8403 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 8404 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 8405 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 8406 #define SBI_SSCDITHPHASE 0x0204 8407 #define SBI_SSCCTL 0x020c 8408 #define SBI_SSCCTL6 0x060C 8409 #define SBI_SSCCTL_PATHALT (1<<3) 8410 #define SBI_SSCCTL_DISABLE (1<<0) 8411 #define SBI_SSCAUXDIV6 0x0610 8412 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 8413 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4) 8414 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 8415 #define SBI_DBUFF0 0x2a00 8416 #define SBI_GEN0 0x1f00 8417 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 8418 8419 /* LPT PIXCLK_GATE */ 8420 #define PIXCLK_GATE _MMIO(0xC6020) 8421 #define PIXCLK_GATE_UNGATE (1<<0) 8422 #define PIXCLK_GATE_GATE (0<<0) 8423 8424 /* SPLL */ 8425 #define SPLL_CTL _MMIO(0x46020) 8426 #define SPLL_PLL_ENABLE (1<<31) 8427 #define SPLL_PLL_SSC (1<<28) 8428 #define SPLL_PLL_NON_SSC (2<<28) 8429 #define SPLL_PLL_LCPLL (3<<28) 8430 #define SPLL_PLL_REF_MASK (3<<28) 8431 #define SPLL_PLL_FREQ_810MHz (0<<26) 8432 #define SPLL_PLL_FREQ_1350MHz (1<<26) 8433 #define SPLL_PLL_FREQ_2700MHz (2<<26) 8434 #define SPLL_PLL_FREQ_MASK (3<<26) 8435 8436 /* WRPLL */ 8437 #define _WRPLL_CTL1 0x46040 8438 #define _WRPLL_CTL2 0x46060 8439 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 8440 #define WRPLL_PLL_ENABLE (1<<31) 8441 #define WRPLL_PLL_SSC (1<<28) 8442 #define WRPLL_PLL_NON_SSC (2<<28) 8443 #define WRPLL_PLL_LCPLL (3<<28) 8444 #define WRPLL_PLL_REF_MASK (3<<28) 8445 /* WRPLL divider programming */ 8446 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 8447 #define WRPLL_DIVIDER_REF_MASK (0xff) 8448 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 8449 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 8450 #define WRPLL_DIVIDER_POST_SHIFT 8 8451 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 8452 #define WRPLL_DIVIDER_FB_SHIFT 16 8453 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 8454 8455 /* Port clock selection */ 8456 #define _PORT_CLK_SEL_A 0x46100 8457 #define _PORT_CLK_SEL_B 0x46104 8458 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 8459 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 8460 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 8461 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 8462 #define PORT_CLK_SEL_SPLL (3<<29) 8463 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 8464 #define PORT_CLK_SEL_WRPLL1 (4<<29) 8465 #define PORT_CLK_SEL_WRPLL2 (5<<29) 8466 #define PORT_CLK_SEL_NONE (7<<29) 8467 #define PORT_CLK_SEL_MASK (7<<29) 8468 8469 /* Transcoder clock selection */ 8470 #define _TRANS_CLK_SEL_A 0x46140 8471 #define _TRANS_CLK_SEL_B 0x46144 8472 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 8473 /* For each transcoder, we need to select the corresponding port clock */ 8474 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 8475 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) 8476 8477 #define CDCLK_FREQ _MMIO(0x46200) 8478 8479 #define _TRANSA_MSA_MISC 0x60410 8480 #define _TRANSB_MSA_MISC 0x61410 8481 #define _TRANSC_MSA_MISC 0x62410 8482 #define _TRANS_EDP_MSA_MISC 0x6f410 8483 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 8484 8485 #define TRANS_MSA_SYNC_CLK (1<<0) 8486 #define TRANS_MSA_6_BPC (0<<5) 8487 #define TRANS_MSA_8_BPC (1<<5) 8488 #define TRANS_MSA_10_BPC (2<<5) 8489 #define TRANS_MSA_12_BPC (3<<5) 8490 #define TRANS_MSA_16_BPC (4<<5) 8491 8492 /* LCPLL Control */ 8493 #define LCPLL_CTL _MMIO(0x130040) 8494 #define LCPLL_PLL_DISABLE (1<<31) 8495 #define LCPLL_PLL_LOCK (1<<30) 8496 #define LCPLL_CLK_FREQ_MASK (3<<26) 8497 #define LCPLL_CLK_FREQ_450 (0<<26) 8498 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 8499 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 8500 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 8501 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 8502 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24) 8503 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 8504 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 8505 #define LCPLL_CD_SOURCE_FCLK (1<<21) 8506 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 8507 8508 /* 8509 * SKL Clocks 8510 */ 8511 8512 /* CDCLK_CTL */ 8513 #define CDCLK_CTL _MMIO(0x46000) 8514 #define CDCLK_FREQ_SEL_MASK (3<<26) 8515 #define CDCLK_FREQ_450_432 (0<<26) 8516 #define CDCLK_FREQ_540 (1<<26) 8517 #define CDCLK_FREQ_337_308 (2<<26) 8518 #define CDCLK_FREQ_675_617 (3<<26) 8519 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) 8520 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) 8521 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) 8522 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) 8523 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) 8524 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) 8525 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 8526 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) 8527 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 8528 8529 /* LCPLL_CTL */ 8530 #define LCPLL1_CTL _MMIO(0x46010) 8531 #define LCPLL2_CTL _MMIO(0x46014) 8532 #define LCPLL_PLL_ENABLE (1<<31) 8533 8534 /* DPLL control1 */ 8535 #define DPLL_CTRL1 _MMIO(0x6C058) 8536 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) 8537 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) 8538 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) 8539 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) 8540 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) 8541 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) 8542 #define DPLL_CTRL1_LINK_RATE_2700 0 8543 #define DPLL_CTRL1_LINK_RATE_1350 1 8544 #define DPLL_CTRL1_LINK_RATE_810 2 8545 #define DPLL_CTRL1_LINK_RATE_1620 3 8546 #define DPLL_CTRL1_LINK_RATE_1080 4 8547 #define DPLL_CTRL1_LINK_RATE_2160 5 8548 8549 /* DPLL control2 */ 8550 #define DPLL_CTRL2 _MMIO(0x6C05C) 8551 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15)) 8552 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) 8553 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) 8554 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1)) 8555 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) 8556 8557 /* DPLL Status */ 8558 #define DPLL_STATUS _MMIO(0x6C060) 8559 #define DPLL_LOCK(id) (1<<((id)*8)) 8560 8561 /* DPLL cfg */ 8562 #define _DPLL1_CFGCR1 0x6C040 8563 #define _DPLL2_CFGCR1 0x6C048 8564 #define _DPLL3_CFGCR1 0x6C050 8565 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) 8566 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) 8567 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9) 8568 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 8569 8570 #define _DPLL1_CFGCR2 0x6C044 8571 #define _DPLL2_CFGCR2 0x6C04C 8572 #define _DPLL3_CFGCR2 0x6C054 8573 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) 8574 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8) 8575 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7) 8576 #define DPLL_CFGCR2_KDIV_MASK (3<<5) 8577 #define DPLL_CFGCR2_KDIV(x) ((x)<<5) 8578 #define DPLL_CFGCR2_KDIV_5 (0<<5) 8579 #define DPLL_CFGCR2_KDIV_2 (1<<5) 8580 #define DPLL_CFGCR2_KDIV_3 (2<<5) 8581 #define DPLL_CFGCR2_KDIV_1 (3<<5) 8582 #define DPLL_CFGCR2_PDIV_MASK (7<<2) 8583 #define DPLL_CFGCR2_PDIV(x) ((x)<<2) 8584 #define DPLL_CFGCR2_PDIV_1 (0<<2) 8585 #define DPLL_CFGCR2_PDIV_2 (1<<2) 8586 #define DPLL_CFGCR2_PDIV_3 (2<<2) 8587 #define DPLL_CFGCR2_PDIV_7 (4<<2) 8588 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 8589 8590 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 8591 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 8592 8593 /* 8594 * CNL Clocks 8595 */ 8596 #define DPCLKA_CFGCR0 _MMIO(0x6C200) 8597 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10)) 8598 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2)) 8599 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2) 8600 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2)) 8601 8602 /* CNL PLL */ 8603 #define DPLL0_ENABLE 0x46010 8604 #define DPLL1_ENABLE 0x46014 8605 #define PLL_ENABLE (1 << 31) 8606 #define PLL_LOCK (1 << 30) 8607 #define PLL_POWER_ENABLE (1 << 27) 8608 #define PLL_POWER_STATE (1 << 26) 8609 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) 8610 8611 #define _CNL_DPLL0_CFGCR0 0x6C000 8612 #define _CNL_DPLL1_CFGCR0 0x6C080 8613 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 8614 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 8615 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 8616 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 8617 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 8618 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 8619 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 8620 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 8621 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 8622 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 8623 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 8624 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 8625 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 8626 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 8627 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 8628 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) 8629 8630 #define _CNL_DPLL0_CFGCR1 0x6C004 8631 #define _CNL_DPLL1_CFGCR1 0x6C084 8632 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 8633 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 8634 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 8635 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 8636 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 8637 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 8638 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 8639 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 8640 #define DPLL_CFGCR1_KDIV_4 (4 << 6) 8641 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 8642 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 8643 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 8644 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 8645 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 8646 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 8647 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 8648 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) 8649 8650 /* BXT display engine PLL */ 8651 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 8652 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 8653 #define BXT_DE_PLL_RATIO_MASK 0xff 8654 8655 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 8656 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 8657 #define BXT_DE_PLL_LOCK (1 << 30) 8658 #define CNL_CDCLK_PLL_RATIO(x) (x) 8659 #define CNL_CDCLK_PLL_RATIO_MASK 0xff 8660 8661 /* GEN9 DC */ 8662 #define DC_STATE_EN _MMIO(0x45504) 8663 #define DC_STATE_DISABLE 0 8664 #define DC_STATE_EN_UPTO_DC5 (1<<0) 8665 #define DC_STATE_EN_DC9 (1<<3) 8666 #define DC_STATE_EN_UPTO_DC6 (2<<0) 8667 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 8668 8669 #define DC_STATE_DEBUG _MMIO(0x45520) 8670 #define DC_STATE_DEBUG_MASK_CORES (1<<0) 8671 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) 8672 8673 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 8674 * since on HSW we can't write to it using I915_WRITE. */ 8675 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 8676 #define D_COMP_BDW _MMIO(0x138144) 8677 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 8678 #define D_COMP_COMP_FORCE (1<<8) 8679 #define D_COMP_COMP_DISABLE (1<<0) 8680 8681 /* Pipe WM_LINETIME - watermark line time */ 8682 #define _PIPE_WM_LINETIME_A 0x45270 8683 #define _PIPE_WM_LINETIME_B 0x45274 8684 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) 8685 #define PIPE_WM_LINETIME_MASK (0x1ff) 8686 #define PIPE_WM_LINETIME_TIME(x) ((x)) 8687 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 8688 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 8689 8690 /* SFUSE_STRAP */ 8691 #define SFUSE_STRAP _MMIO(0xc2014) 8692 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 8693 #define SFUSE_STRAP_RAW_FREQUENCY (1<<8) 8694 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 8695 #define SFUSE_STRAP_CRT_DISABLED (1<<6) 8696 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 8697 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 8698 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 8699 8700 #define WM_MISC _MMIO(0x45260) 8701 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 8702 8703 #define WM_DBG _MMIO(0x45280) 8704 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 8705 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 8706 #define WM_DBG_DISALLOW_SPRITE (1<<2) 8707 8708 /* pipe CSC */ 8709 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 8710 #define _PIPE_A_CSC_COEFF_BY 0x49014 8711 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 8712 #define _PIPE_A_CSC_COEFF_BU 0x4901c 8713 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 8714 #define _PIPE_A_CSC_COEFF_BV 0x49024 8715 #define _PIPE_A_CSC_MODE 0x49028 8716 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 8717 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 8718 #define CSC_MODE_YUV_TO_RGB (1 << 0) 8719 #define _PIPE_A_CSC_PREOFF_HI 0x49030 8720 #define _PIPE_A_CSC_PREOFF_ME 0x49034 8721 #define _PIPE_A_CSC_PREOFF_LO 0x49038 8722 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 8723 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 8724 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 8725 8726 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 8727 #define _PIPE_B_CSC_COEFF_BY 0x49114 8728 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 8729 #define _PIPE_B_CSC_COEFF_BU 0x4911c 8730 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 8731 #define _PIPE_B_CSC_COEFF_BV 0x49124 8732 #define _PIPE_B_CSC_MODE 0x49128 8733 #define _PIPE_B_CSC_PREOFF_HI 0x49130 8734 #define _PIPE_B_CSC_PREOFF_ME 0x49134 8735 #define _PIPE_B_CSC_PREOFF_LO 0x49138 8736 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 8737 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 8738 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 8739 8740 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 8741 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 8742 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 8743 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 8744 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 8745 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 8746 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 8747 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 8748 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 8749 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 8750 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 8751 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 8752 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 8753 8754 /* pipe degamma/gamma LUTs on IVB+ */ 8755 #define _PAL_PREC_INDEX_A 0x4A400 8756 #define _PAL_PREC_INDEX_B 0x4AC00 8757 #define _PAL_PREC_INDEX_C 0x4B400 8758 #define PAL_PREC_10_12_BIT (0 << 31) 8759 #define PAL_PREC_SPLIT_MODE (1 << 31) 8760 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 8761 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 8762 #define _PAL_PREC_DATA_A 0x4A404 8763 #define _PAL_PREC_DATA_B 0x4AC04 8764 #define _PAL_PREC_DATA_C 0x4B404 8765 #define _PAL_PREC_GC_MAX_A 0x4A410 8766 #define _PAL_PREC_GC_MAX_B 0x4AC10 8767 #define _PAL_PREC_GC_MAX_C 0x4B410 8768 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 8769 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 8770 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 8771 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 8772 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 8773 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 8774 8775 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 8776 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 8777 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 8778 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 8779 8780 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 8781 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 8782 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 8783 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 8784 #define _PRE_CSC_GAMC_DATA_A 0x4A488 8785 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 8786 #define _PRE_CSC_GAMC_DATA_C 0x4B488 8787 8788 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 8789 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 8790 8791 /* pipe CSC & degamma/gamma LUTs on CHV */ 8792 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 8793 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 8794 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 8795 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 8796 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 8797 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 8798 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 8799 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 8800 #define CGM_PIPE_MODE_GAMMA (1 << 2) 8801 #define CGM_PIPE_MODE_CSC (1 << 1) 8802 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 8803 8804 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 8805 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 8806 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 8807 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 8808 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 8809 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 8810 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 8811 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 8812 8813 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 8814 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 8815 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 8816 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 8817 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 8818 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 8819 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 8820 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 8821 8822 /* MIPI DSI registers */ 8823 8824 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 8825 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 8826 8827 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 8828 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 8829 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 8830 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 8831 8832 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 8833 #define GEN4_TIMESTAMP _MMIO(0x2358) 8834 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 8835 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 8836 8837 #define _PIPE_FRMTMSTMP_A 0x70048 8838 #define PIPE_FRMTMSTMP(pipe) \ 8839 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 8840 8841 /* BXT MIPI clock controls */ 8842 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 8843 8844 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 8845 #define BXT_MIPI1_DIV_SHIFT 26 8846 #define BXT_MIPI2_DIV_SHIFT 10 8847 #define BXT_MIPI_DIV_SHIFT(port) \ 8848 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 8849 BXT_MIPI2_DIV_SHIFT) 8850 8851 /* TX control divider to select actual TX clock output from (8x/var) */ 8852 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 8853 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 8854 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 8855 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 8856 BXT_MIPI2_TX_ESCLK_SHIFT) 8857 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 8858 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 8859 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 8860 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 8861 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 8862 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 8863 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 8864 /* RX upper control divider to select actual RX clock output from 8x */ 8865 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 8866 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 8867 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 8868 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 8869 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 8870 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 8871 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 8872 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 8873 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 8874 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 8875 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 8876 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 8877 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 8878 #define BXT_MIPI1_8X_BY3_SHIFT 19 8879 #define BXT_MIPI2_8X_BY3_SHIFT 3 8880 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 8881 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 8882 BXT_MIPI2_8X_BY3_SHIFT) 8883 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 8884 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 8885 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 8886 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 8887 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 8888 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 8889 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 8890 /* RX lower control divider to select actual RX clock output from 8x */ 8891 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 8892 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 8893 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 8894 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 8895 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 8896 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 8897 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 8898 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 8899 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 8900 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 8901 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 8902 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 8903 8904 #define RX_DIVIDER_BIT_1_2 0x3 8905 #define RX_DIVIDER_BIT_3_4 0xC 8906 8907 /* BXT MIPI mode configure */ 8908 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 8909 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 8910 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 8911 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 8912 8913 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 8914 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 8915 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 8916 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 8917 8918 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 8919 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 8920 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 8921 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 8922 8923 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 8924 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 8925 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 8926 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 8927 #define BXT_DSIC_16X_BY1 (0 << 10) 8928 #define BXT_DSIC_16X_BY2 (1 << 10) 8929 #define BXT_DSIC_16X_BY3 (2 << 10) 8930 #define BXT_DSIC_16X_BY4 (3 << 10) 8931 #define BXT_DSIC_16X_MASK (3 << 10) 8932 #define BXT_DSIA_16X_BY1 (0 << 8) 8933 #define BXT_DSIA_16X_BY2 (1 << 8) 8934 #define BXT_DSIA_16X_BY3 (2 << 8) 8935 #define BXT_DSIA_16X_BY4 (3 << 8) 8936 #define BXT_DSIA_16X_MASK (3 << 8) 8937 #define BXT_DSI_FREQ_SEL_SHIFT 8 8938 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 8939 8940 #define BXT_DSI_PLL_RATIO_MAX 0x7D 8941 #define BXT_DSI_PLL_RATIO_MIN 0x22 8942 #define GLK_DSI_PLL_RATIO_MAX 0x6F 8943 #define GLK_DSI_PLL_RATIO_MIN 0x22 8944 #define BXT_DSI_PLL_RATIO_MASK 0xFF 8945 #define BXT_REF_CLOCK_KHZ 19200 8946 8947 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 8948 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 8949 #define BXT_DSI_PLL_LOCKED (1 << 30) 8950 8951 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 8952 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 8953 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 8954 8955 /* BXT port control */ 8956 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 8957 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 8958 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 8959 8960 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 8961 #define STAP_SELECT (1 << 0) 8962 8963 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 8964 #define HS_IO_CTRL_SELECT (1 << 0) 8965 8966 #define DPI_ENABLE (1 << 31) /* A + C */ 8967 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 8968 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 8969 #define DUAL_LINK_MODE_SHIFT 26 8970 #define DUAL_LINK_MODE_MASK (1 << 26) 8971 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 8972 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 8973 #define DITHERING_ENABLE (1 << 25) /* A + C */ 8974 #define FLOPPED_HSTX (1 << 23) 8975 #define DE_INVERT (1 << 19) /* XXX */ 8976 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 8977 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 8978 #define AFE_LATCHOUT (1 << 17) 8979 #define LP_OUTPUT_HOLD (1 << 16) 8980 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 8981 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 8982 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 8983 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 8984 #define CSB_SHIFT 9 8985 #define CSB_MASK (3 << 9) 8986 #define CSB_20MHZ (0 << 9) 8987 #define CSB_10MHZ (1 << 9) 8988 #define CSB_40MHZ (2 << 9) 8989 #define BANDGAP_MASK (1 << 8) 8990 #define BANDGAP_PNW_CIRCUIT (0 << 8) 8991 #define BANDGAP_LNC_CIRCUIT (1 << 8) 8992 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 8993 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 8994 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 8995 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 8996 #define TEARING_EFFECT_MASK (3 << 2) 8997 #define TEARING_EFFECT_OFF (0 << 2) 8998 #define TEARING_EFFECT_DSI (1 << 2) 8999 #define TEARING_EFFECT_GPIO (2 << 2) 9000 #define LANE_CONFIGURATION_SHIFT 0 9001 #define LANE_CONFIGURATION_MASK (3 << 0) 9002 #define LANE_CONFIGURATION_4LANE (0 << 0) 9003 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 9004 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 9005 9006 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 9007 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 9008 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 9009 #define TEARING_EFFECT_DELAY_SHIFT 0 9010 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 9011 9012 /* XXX: all bits reserved */ 9013 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 9014 9015 /* MIPI DSI Controller and D-PHY registers */ 9016 9017 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 9018 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 9019 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 9020 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 9021 #define ULPS_STATE_MASK (3 << 1) 9022 #define ULPS_STATE_ENTER (2 << 1) 9023 #define ULPS_STATE_EXIT (1 << 1) 9024 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 9025 #define DEVICE_READY (1 << 0) 9026 9027 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 9028 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 9029 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 9030 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 9031 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 9032 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 9033 #define TEARING_EFFECT (1 << 31) 9034 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 9035 #define GEN_READ_DATA_AVAIL (1 << 29) 9036 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 9037 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 9038 #define RX_PROT_VIOLATION (1 << 26) 9039 #define RX_INVALID_TX_LENGTH (1 << 25) 9040 #define ACK_WITH_NO_ERROR (1 << 24) 9041 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 9042 #define LP_RX_TIMEOUT (1 << 22) 9043 #define HS_TX_TIMEOUT (1 << 21) 9044 #define DPI_FIFO_UNDERRUN (1 << 20) 9045 #define LOW_CONTENTION (1 << 19) 9046 #define HIGH_CONTENTION (1 << 18) 9047 #define TXDSI_VC_ID_INVALID (1 << 17) 9048 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 9049 #define TXCHECKSUM_ERROR (1 << 15) 9050 #define TXECC_MULTIBIT_ERROR (1 << 14) 9051 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 9052 #define TXFALSE_CONTROL_ERROR (1 << 12) 9053 #define RXDSI_VC_ID_INVALID (1 << 11) 9054 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 9055 #define RXCHECKSUM_ERROR (1 << 9) 9056 #define RXECC_MULTIBIT_ERROR (1 << 8) 9057 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 9058 #define RXFALSE_CONTROL_ERROR (1 << 6) 9059 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 9060 #define RX_LP_TX_SYNC_ERROR (1 << 4) 9061 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 9062 #define RXEOT_SYNC_ERROR (1 << 2) 9063 #define RXSOT_SYNC_ERROR (1 << 1) 9064 #define RXSOT_ERROR (1 << 0) 9065 9066 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 9067 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 9068 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 9069 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 9070 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 9071 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 9072 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 9073 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 9074 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 9075 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 9076 #define VID_MODE_FORMAT_MASK (0xf << 7) 9077 #define VID_MODE_NOT_SUPPORTED (0 << 7) 9078 #define VID_MODE_FORMAT_RGB565 (1 << 7) 9079 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 9080 #define VID_MODE_FORMAT_RGB666 (3 << 7) 9081 #define VID_MODE_FORMAT_RGB888 (4 << 7) 9082 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 9083 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 9084 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 9085 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 9086 #define DATA_LANES_PRG_REG_SHIFT 0 9087 #define DATA_LANES_PRG_REG_MASK (7 << 0) 9088 9089 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 9090 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 9091 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 9092 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 9093 9094 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 9095 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 9096 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 9097 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 9098 9099 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 9100 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 9101 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 9102 #define TURN_AROUND_TIMEOUT_MASK 0x3f 9103 9104 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 9105 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 9106 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 9107 #define DEVICE_RESET_TIMER_MASK 0xffff 9108 9109 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 9110 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 9111 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 9112 #define VERTICAL_ADDRESS_SHIFT 16 9113 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 9114 #define HORIZONTAL_ADDRESS_SHIFT 0 9115 #define HORIZONTAL_ADDRESS_MASK 0xffff 9116 9117 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 9118 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 9119 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 9120 #define DBI_FIFO_EMPTY_HALF (0 << 0) 9121 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 9122 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 9123 9124 /* regs below are bits 15:0 */ 9125 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 9126 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 9127 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 9128 9129 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 9130 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 9131 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 9132 9133 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 9134 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 9135 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 9136 9137 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 9138 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 9139 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 9140 9141 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 9142 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 9143 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 9144 9145 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 9146 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 9147 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 9148 9149 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 9150 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 9151 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 9152 9153 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 9154 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 9155 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 9156 9157 /* regs above are bits 15:0 */ 9158 9159 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 9160 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 9161 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 9162 #define DPI_LP_MODE (1 << 6) 9163 #define BACKLIGHT_OFF (1 << 5) 9164 #define BACKLIGHT_ON (1 << 4) 9165 #define COLOR_MODE_OFF (1 << 3) 9166 #define COLOR_MODE_ON (1 << 2) 9167 #define TURN_ON (1 << 1) 9168 #define SHUTDOWN (1 << 0) 9169 9170 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 9171 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 9172 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 9173 #define COMMAND_BYTE_SHIFT 0 9174 #define COMMAND_BYTE_MASK (0x3f << 0) 9175 9176 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 9177 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 9178 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 9179 #define MASTER_INIT_TIMER_SHIFT 0 9180 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 9181 9182 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 9183 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 9184 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 9185 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 9186 #define MAX_RETURN_PKT_SIZE_SHIFT 0 9187 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 9188 9189 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 9190 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 9191 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 9192 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 9193 #define DISABLE_VIDEO_BTA (1 << 3) 9194 #define IP_TG_CONFIG (1 << 2) 9195 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 9196 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 9197 #define VIDEO_MODE_BURST (3 << 0) 9198 9199 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 9200 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 9201 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 9202 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 9203 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 9204 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 9205 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 9206 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 9207 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 9208 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 9209 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 9210 #define CLOCKSTOP (1 << 1) 9211 #define EOT_DISABLE (1 << 0) 9212 9213 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 9214 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 9215 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 9216 #define LP_BYTECLK_SHIFT 0 9217 #define LP_BYTECLK_MASK (0xffff << 0) 9218 9219 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 9220 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 9221 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 9222 9223 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 9224 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 9225 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 9226 9227 /* bits 31:0 */ 9228 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 9229 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 9230 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 9231 9232 /* bits 31:0 */ 9233 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 9234 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 9235 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 9236 9237 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 9238 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 9239 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 9240 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 9241 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 9242 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 9243 #define LONG_PACKET_WORD_COUNT_SHIFT 8 9244 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 9245 #define SHORT_PACKET_PARAM_SHIFT 8 9246 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 9247 #define VIRTUAL_CHANNEL_SHIFT 6 9248 #define VIRTUAL_CHANNEL_MASK (3 << 6) 9249 #define DATA_TYPE_SHIFT 0 9250 #define DATA_TYPE_MASK (0x3f << 0) 9251 /* data type values, see include/video/mipi_display.h */ 9252 9253 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 9254 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 9255 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 9256 #define DPI_FIFO_EMPTY (1 << 28) 9257 #define DBI_FIFO_EMPTY (1 << 27) 9258 #define LP_CTRL_FIFO_EMPTY (1 << 26) 9259 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 9260 #define LP_CTRL_FIFO_FULL (1 << 24) 9261 #define HS_CTRL_FIFO_EMPTY (1 << 18) 9262 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 9263 #define HS_CTRL_FIFO_FULL (1 << 16) 9264 #define LP_DATA_FIFO_EMPTY (1 << 10) 9265 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 9266 #define LP_DATA_FIFO_FULL (1 << 8) 9267 #define HS_DATA_FIFO_EMPTY (1 << 2) 9268 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 9269 #define HS_DATA_FIFO_FULL (1 << 0) 9270 9271 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 9272 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 9273 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 9274 #define DBI_HS_LP_MODE_MASK (1 << 0) 9275 #define DBI_LP_MODE (1 << 0) 9276 #define DBI_HS_MODE (0 << 0) 9277 9278 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 9279 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 9280 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 9281 #define EXIT_ZERO_COUNT_SHIFT 24 9282 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 9283 #define TRAIL_COUNT_SHIFT 16 9284 #define TRAIL_COUNT_MASK (0x1f << 16) 9285 #define CLK_ZERO_COUNT_SHIFT 8 9286 #define CLK_ZERO_COUNT_MASK (0xff << 8) 9287 #define PREPARE_COUNT_SHIFT 0 9288 #define PREPARE_COUNT_MASK (0x3f << 0) 9289 9290 /* bits 31:0 */ 9291 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 9292 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 9293 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 9294 9295 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 9296 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 9297 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 9298 #define LP_HS_SSW_CNT_SHIFT 16 9299 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 9300 #define HS_LP_PWR_SW_CNT_SHIFT 0 9301 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 9302 9303 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 9304 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 9305 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 9306 #define STOP_STATE_STALL_COUNTER_SHIFT 0 9307 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 9308 9309 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 9310 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 9311 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 9312 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 9313 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 9314 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 9315 #define RX_CONTENTION_DETECTED (1 << 0) 9316 9317 /* XXX: only pipe A ?!? */ 9318 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 9319 #define DBI_TYPEC_ENABLE (1 << 31) 9320 #define DBI_TYPEC_WIP (1 << 30) 9321 #define DBI_TYPEC_OPTION_SHIFT 28 9322 #define DBI_TYPEC_OPTION_MASK (3 << 28) 9323 #define DBI_TYPEC_FREQ_SHIFT 24 9324 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 9325 #define DBI_TYPEC_OVERRIDE (1 << 8) 9326 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 9327 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 9328 9329 9330 /* MIPI adapter registers */ 9331 9332 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 9333 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 9334 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 9335 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 9336 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 9337 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 9338 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 9339 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 9340 #define READ_REQUEST_PRIORITY_SHIFT 3 9341 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 9342 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 9343 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 9344 #define RGB_FLIP_TO_BGR (1 << 2) 9345 9346 #define BXT_PIPE_SELECT_SHIFT 7 9347 #define BXT_PIPE_SELECT_MASK (7 << 7) 9348 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 9349 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 9350 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 9351 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 9352 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 9353 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 9354 #define GLK_LP_WAKE (1 << 22) 9355 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 9356 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 9357 #define GLK_FIREWALL_ENABLE (1 << 16) 9358 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 9359 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 9360 #define BXT_DSC_ENABLE (1 << 3) 9361 #define BXT_RGB_FLIP (1 << 2) 9362 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 9363 #define GLK_MIPIIO_ENABLE (1 << 0) 9364 9365 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 9366 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 9367 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 9368 #define DATA_MEM_ADDRESS_SHIFT 5 9369 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 9370 #define DATA_VALID (1 << 0) 9371 9372 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 9373 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 9374 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 9375 #define DATA_LENGTH_SHIFT 0 9376 #define DATA_LENGTH_MASK (0xfffff << 0) 9377 9378 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 9379 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 9380 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 9381 #define COMMAND_MEM_ADDRESS_SHIFT 5 9382 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 9383 #define AUTO_PWG_ENABLE (1 << 2) 9384 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 9385 #define COMMAND_VALID (1 << 0) 9386 9387 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 9388 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 9389 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 9390 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 9391 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 9392 9393 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 9394 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 9395 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 9396 9397 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 9398 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 9399 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 9400 #define READ_DATA_VALID(n) (1 << (n)) 9401 9402 /* For UMS only (deprecated): */ 9403 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 9404 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 9405 9406 /* MOCS (Memory Object Control State) registers */ 9407 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 9408 9409 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ 9410 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ 9411 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ 9412 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ 9413 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ 9414 9415 /* gamt regs */ 9416 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 9417 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 9418 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 9419 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 9420 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 9421 9422 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 9423 #define MMCD_PCLA (1 << 31) 9424 #define MMCD_HOTSPOT_EN (1 << 27) 9425 9426 #endif /* _I915_REG_H_ */ 9427