1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 30 /** 31 * DOC: The i915 register macro definition style guide 32 * 33 * Follow the style described here for new macros, and while changing existing 34 * macros. Do **not** mass change existing definitions just to update the style. 35 * 36 * File Layout 37 * ~~~~~~~~~~~ 38 * 39 * Keep helper macros near the top. For example, _PIPE() and friends. 40 * 41 * Prefix macros that generally should not be used outside of this file with 42 * underscore '_'. For example, _PIPE() and friends, single instances of 43 * registers that are defined solely for the use by function-like macros. 44 * 45 * Avoid using the underscore prefixed macros outside of this file. There are 46 * exceptions, but keep them to a minimum. 47 * 48 * There are two basic types of register definitions: Single registers and 49 * register groups. Register groups are registers which have two or more 50 * instances, for example one per pipe, port, transcoder, etc. Register groups 51 * should be defined using function-like macros. 52 * 53 * For single registers, define the register offset first, followed by register 54 * contents. 55 * 56 * For register groups, define the register instance offsets first, prefixed 57 * with underscore, followed by a function-like macro choosing the right 58 * instance based on the parameter, followed by register contents. 59 * 60 * Define the register contents (i.e. bit and bit field macros) from most 61 * significant to least significant bit. Indent the register content macros 62 * using two extra spaces between ``#define`` and the macro name. 63 * 64 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 65 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 66 * shifted in place, so they can be directly OR'd together. For convenience, 67 * function-like macros may be used to define bit fields, but do note that the 68 * macros may be needed to read as well as write the register contents. 69 * 70 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 71 * 72 * Group the register and its contents together without blank lines, separate 73 * from other registers and their contents with one blank line. 74 * 75 * Indent macro values from macro names using TABs. Align values vertically. Use 76 * braces in macro values as needed to avoid unintended precedence after macro 77 * substitution. Use spaces in macro values according to kernel coding 78 * style. Use lower case in hexadecimal values. 79 * 80 * Naming 81 * ~~~~~~ 82 * 83 * Try to name registers according to the specs. If the register name changes in 84 * the specs from platform to another, stick to the original name. 85 * 86 * Try to re-use existing register macro definitions. Only add new macros for 87 * new register offsets, or when the register contents have changed enough to 88 * warrant a full redefinition. 89 * 90 * When a register macro changes for a new platform, prefix the new macro using 91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 92 * prefix signifies the start platform/generation using the register. 93 * 94 * When a bit (field) macro changes or gets added for a new platform, while 95 * retaining the existing register macro, add a platform acronym or generation 96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 97 * 98 * Examples 99 * ~~~~~~~~ 100 * 101 * (Note that the values in the example are indented using spaces instead of 102 * TABs to avoid misalignment in generated documentation. Use TABs in the 103 * definitions.):: 104 * 105 * #define _FOO_A 0xf000 106 * #define _FOO_B 0xf001 107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 108 * #define FOO_ENABLE REG_BIT(31) 109 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 110 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 111 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 112 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 113 * 114 * #define BAR _MMIO(0xb000) 115 * #define GEN8_BAR _MMIO(0xb888) 116 */ 117 118 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset) 119 120 /* 121 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 122 * numbers, pick the 0-based __index'th value. 123 * 124 * Always prefer this over _PICK() if the numbers are evenly spaced. 125 */ 126 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 127 128 /* 129 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 130 * 131 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 132 */ 133 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 134 135 /* 136 * Named helper wrappers around _PICK_EVEN() and _PICK(). 137 */ 138 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 139 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 140 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 141 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 142 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 143 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 144 145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 146 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 147 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 148 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 149 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 150 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 151 152 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 153 154 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 155 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 156 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 157 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) 158 159 160 /* 161 * Device info offset array based helpers for groups of registers with unevenly 162 * spaced base offsets. 163 */ 164 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \ 165 INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \ 166 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 167 #define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \ 168 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \ 169 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 170 #define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \ 171 INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \ 172 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 173 174 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 175 #define _MASKED_FIELD(mask, value) ({ \ 176 if (__builtin_constant_p(mask)) \ 177 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 178 if (__builtin_constant_p(value)) \ 179 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 180 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 181 BUILD_BUG_ON_MSG((value) & ~(mask), \ 182 "Incorrect value for mask"); \ 183 __MASKED_FIELD(mask, value); }) 184 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 185 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 186 187 #define GU_CNTL _MMIO(0x101010) 188 #define LMEM_INIT REG_BIT(7) 189 190 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 191 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 192 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 193 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 194 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 195 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 196 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 197 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 198 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 199 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 200 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 201 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 202 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 203 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 204 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 205 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 206 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 207 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 208 209 #define _VGA_MSR_WRITE _MMIO(0x3c2) 210 211 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 212 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 213 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 214 215 /* 216 * Reset registers 217 */ 218 #define DEBUG_RESET_I830 _MMIO(0x6070) 219 #define DEBUG_RESET_FULL (1 << 7) 220 #define DEBUG_RESET_RENDER (1 << 8) 221 #define DEBUG_RESET_DISPLAY (1 << 9) 222 223 /* 224 * IOSF sideband 225 */ 226 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 227 #define IOSF_DEVFN_SHIFT 24 228 #define IOSF_OPCODE_SHIFT 16 229 #define IOSF_PORT_SHIFT 8 230 #define IOSF_BYTE_ENABLES_SHIFT 4 231 #define IOSF_BAR_SHIFT 1 232 #define IOSF_SB_BUSY (1 << 0) 233 #define IOSF_PORT_BUNIT 0x03 234 #define IOSF_PORT_PUNIT 0x04 235 #define IOSF_PORT_NC 0x11 236 #define IOSF_PORT_DPIO 0x12 237 #define IOSF_PORT_GPIO_NC 0x13 238 #define IOSF_PORT_CCK 0x14 239 #define IOSF_PORT_DPIO_2 0x1a 240 #define IOSF_PORT_FLISDSI 0x1b 241 #define IOSF_PORT_GPIO_SC 0x48 242 #define IOSF_PORT_GPIO_SUS 0xa8 243 #define IOSF_PORT_CCU 0xa9 244 #define CHV_IOSF_PORT_GPIO_N 0x13 245 #define CHV_IOSF_PORT_GPIO_SE 0x48 246 #define CHV_IOSF_PORT_GPIO_E 0xa8 247 #define CHV_IOSF_PORT_GPIO_SW 0xb2 248 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 249 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 250 251 /* DPIO registers */ 252 #define DPIO_DEVFN 0 253 254 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 255 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 256 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 257 #define DPIO_SFR_BYPASS (1 << 1) 258 #define DPIO_CMNRST (1 << 0) 259 260 #define DPIO_PHY(pipe) ((pipe) >> 1) 261 262 /* 263 * Per pipe/PLL DPIO regs 264 */ 265 #define _VLV_PLL_DW3_CH0 0x800c 266 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 267 #define DPIO_POST_DIV_DAC 0 268 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 269 #define DPIO_POST_DIV_LVDS1 2 270 #define DPIO_POST_DIV_LVDS2 3 271 #define DPIO_K_SHIFT (24) /* 4 bits */ 272 #define DPIO_P1_SHIFT (21) /* 3 bits */ 273 #define DPIO_P2_SHIFT (16) /* 5 bits */ 274 #define DPIO_N_SHIFT (12) /* 4 bits */ 275 #define DPIO_ENABLE_CALIBRATION (1 << 11) 276 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 277 #define DPIO_M2DIV_MASK 0xff 278 #define _VLV_PLL_DW3_CH1 0x802c 279 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 280 281 #define _VLV_PLL_DW5_CH0 0x8014 282 #define DPIO_REFSEL_OVERRIDE 27 283 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 284 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 285 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 286 #define DPIO_PLL_REFCLK_SEL_MASK 3 287 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 288 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 289 #define _VLV_PLL_DW5_CH1 0x8034 290 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 291 292 #define _VLV_PLL_DW7_CH0 0x801c 293 #define _VLV_PLL_DW7_CH1 0x803c 294 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 295 296 #define _VLV_PLL_DW8_CH0 0x8040 297 #define _VLV_PLL_DW8_CH1 0x8060 298 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 299 300 #define VLV_PLL_DW9_BCAST 0xc044 301 #define _VLV_PLL_DW9_CH0 0x8044 302 #define _VLV_PLL_DW9_CH1 0x8064 303 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 304 305 #define _VLV_PLL_DW10_CH0 0x8048 306 #define _VLV_PLL_DW10_CH1 0x8068 307 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 308 309 #define _VLV_PLL_DW11_CH0 0x804c 310 #define _VLV_PLL_DW11_CH1 0x806c 311 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 312 313 /* Spec for ref block start counts at DW10 */ 314 #define VLV_REF_DW13 0x80ac 315 316 #define VLV_CMN_DW0 0x8100 317 318 /* 319 * Per DDI channel DPIO regs 320 */ 321 322 #define _VLV_PCS_DW0_CH0 0x8200 323 #define _VLV_PCS_DW0_CH1 0x8400 324 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 325 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 326 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 327 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 328 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 329 330 #define _VLV_PCS01_DW0_CH0 0x200 331 #define _VLV_PCS23_DW0_CH0 0x400 332 #define _VLV_PCS01_DW0_CH1 0x2600 333 #define _VLV_PCS23_DW0_CH1 0x2800 334 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 335 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 336 337 #define _VLV_PCS_DW1_CH0 0x8204 338 #define _VLV_PCS_DW1_CH1 0x8404 339 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 340 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 341 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 342 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 343 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 344 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 345 346 #define _VLV_PCS01_DW1_CH0 0x204 347 #define _VLV_PCS23_DW1_CH0 0x404 348 #define _VLV_PCS01_DW1_CH1 0x2604 349 #define _VLV_PCS23_DW1_CH1 0x2804 350 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 351 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 352 353 #define _VLV_PCS_DW8_CH0 0x8220 354 #define _VLV_PCS_DW8_CH1 0x8420 355 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 356 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 357 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 358 359 #define _VLV_PCS01_DW8_CH0 0x0220 360 #define _VLV_PCS23_DW8_CH0 0x0420 361 #define _VLV_PCS01_DW8_CH1 0x2620 362 #define _VLV_PCS23_DW8_CH1 0x2820 363 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 364 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 365 366 #define _VLV_PCS_DW9_CH0 0x8224 367 #define _VLV_PCS_DW9_CH1 0x8424 368 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 369 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 370 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 371 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 372 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 373 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 374 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 375 376 #define _VLV_PCS01_DW9_CH0 0x224 377 #define _VLV_PCS23_DW9_CH0 0x424 378 #define _VLV_PCS01_DW9_CH1 0x2624 379 #define _VLV_PCS23_DW9_CH1 0x2824 380 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 381 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 382 383 #define _CHV_PCS_DW10_CH0 0x8228 384 #define _CHV_PCS_DW10_CH1 0x8428 385 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 386 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 387 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 388 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 389 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 390 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 391 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 392 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 393 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 394 395 #define _VLV_PCS01_DW10_CH0 0x0228 396 #define _VLV_PCS23_DW10_CH0 0x0428 397 #define _VLV_PCS01_DW10_CH1 0x2628 398 #define _VLV_PCS23_DW10_CH1 0x2828 399 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 400 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 401 402 #define _VLV_PCS_DW11_CH0 0x822c 403 #define _VLV_PCS_DW11_CH1 0x842c 404 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 405 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 406 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 407 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 408 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 409 410 #define _VLV_PCS01_DW11_CH0 0x022c 411 #define _VLV_PCS23_DW11_CH0 0x042c 412 #define _VLV_PCS01_DW11_CH1 0x262c 413 #define _VLV_PCS23_DW11_CH1 0x282c 414 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 415 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 416 417 #define _VLV_PCS01_DW12_CH0 0x0230 418 #define _VLV_PCS23_DW12_CH0 0x0430 419 #define _VLV_PCS01_DW12_CH1 0x2630 420 #define _VLV_PCS23_DW12_CH1 0x2830 421 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 422 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 423 424 #define _VLV_PCS_DW12_CH0 0x8230 425 #define _VLV_PCS_DW12_CH1 0x8430 426 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 427 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 428 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 429 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 430 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 431 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 432 433 #define _VLV_PCS_DW14_CH0 0x8238 434 #define _VLV_PCS_DW14_CH1 0x8438 435 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 436 437 #define _VLV_PCS_DW23_CH0 0x825c 438 #define _VLV_PCS_DW23_CH1 0x845c 439 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 440 441 #define _VLV_TX_DW2_CH0 0x8288 442 #define _VLV_TX_DW2_CH1 0x8488 443 #define DPIO_SWING_MARGIN000_SHIFT 16 444 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 445 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 446 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 447 448 #define _VLV_TX_DW3_CH0 0x828c 449 #define _VLV_TX_DW3_CH1 0x848c 450 /* The following bit for CHV phy */ 451 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 452 #define DPIO_SWING_MARGIN101_SHIFT 16 453 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 454 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 455 456 #define _VLV_TX_DW4_CH0 0x8290 457 #define _VLV_TX_DW4_CH1 0x8490 458 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 459 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 460 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 461 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 462 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 463 464 #define _VLV_TX3_DW4_CH0 0x690 465 #define _VLV_TX3_DW4_CH1 0x2a90 466 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 467 468 #define _VLV_TX_DW5_CH0 0x8294 469 #define _VLV_TX_DW5_CH1 0x8494 470 #define DPIO_TX_OCALINIT_EN (1 << 31) 471 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 472 473 #define _VLV_TX_DW11_CH0 0x82ac 474 #define _VLV_TX_DW11_CH1 0x84ac 475 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 476 477 #define _VLV_TX_DW14_CH0 0x82b8 478 #define _VLV_TX_DW14_CH1 0x84b8 479 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 480 481 /* CHV dpPhy registers */ 482 #define _CHV_PLL_DW0_CH0 0x8000 483 #define _CHV_PLL_DW0_CH1 0x8180 484 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 485 486 #define _CHV_PLL_DW1_CH0 0x8004 487 #define _CHV_PLL_DW1_CH1 0x8184 488 #define DPIO_CHV_N_DIV_SHIFT 8 489 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 490 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 491 492 #define _CHV_PLL_DW2_CH0 0x8008 493 #define _CHV_PLL_DW2_CH1 0x8188 494 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 495 496 #define _CHV_PLL_DW3_CH0 0x800c 497 #define _CHV_PLL_DW3_CH1 0x818c 498 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 499 #define DPIO_CHV_FIRST_MOD (0 << 8) 500 #define DPIO_CHV_SECOND_MOD (1 << 8) 501 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 502 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 503 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 504 505 #define _CHV_PLL_DW6_CH0 0x8018 506 #define _CHV_PLL_DW6_CH1 0x8198 507 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 508 #define DPIO_CHV_INT_COEFF_SHIFT 8 509 #define DPIO_CHV_PROP_COEFF_SHIFT 0 510 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 511 512 #define _CHV_PLL_DW8_CH0 0x8020 513 #define _CHV_PLL_DW8_CH1 0x81A0 514 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 515 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 516 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 517 518 #define _CHV_PLL_DW9_CH0 0x8024 519 #define _CHV_PLL_DW9_CH1 0x81A4 520 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 521 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 522 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 523 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 524 525 #define _CHV_CMN_DW0_CH0 0x8100 526 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 527 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 528 #define DPIO_ALLDL_POWERDOWN (1 << 1) 529 #define DPIO_ANYDL_POWERDOWN (1 << 0) 530 531 #define _CHV_CMN_DW5_CH0 0x8114 532 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 533 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 534 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 535 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 536 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 537 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 538 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 539 #define CHV_BUFLEFTENA1_MASK (3 << 22) 540 541 #define _CHV_CMN_DW13_CH0 0x8134 542 #define _CHV_CMN_DW0_CH1 0x8080 543 #define DPIO_CHV_S1_DIV_SHIFT 21 544 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 545 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 546 #define DPIO_CHV_K_DIV_SHIFT 4 547 #define DPIO_PLL_FREQLOCK (1 << 1) 548 #define DPIO_PLL_LOCK (1 << 0) 549 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 550 551 #define _CHV_CMN_DW14_CH0 0x8138 552 #define _CHV_CMN_DW1_CH1 0x8084 553 #define DPIO_AFC_RECAL (1 << 14) 554 #define DPIO_DCLKP_EN (1 << 13) 555 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 556 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 557 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 558 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 559 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 560 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 561 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 562 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 563 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 564 565 #define _CHV_CMN_DW19_CH0 0x814c 566 #define _CHV_CMN_DW6_CH1 0x8098 567 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 568 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 569 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 570 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 571 572 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 573 574 #define CHV_CMN_DW28 0x8170 575 #define DPIO_CL1POWERDOWNEN (1 << 23) 576 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 577 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 578 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 579 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 580 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 581 582 #define CHV_CMN_DW30 0x8178 583 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 584 #define DPIO_LRC_BYPASS (1 << 3) 585 586 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 587 (lane) * 0x200 + (offset)) 588 589 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 590 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 591 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 592 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 593 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 594 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 595 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 596 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 597 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 598 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 599 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 600 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 601 #define DPIO_FRC_LATENCY_SHFIT 8 602 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 603 #define DPIO_UPAR_SHIFT 30 604 605 /* BXT PHY registers */ 606 #define _BXT_PHY0_BASE 0x6C000 607 #define _BXT_PHY1_BASE 0x162000 608 #define _BXT_PHY2_BASE 0x163000 609 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 610 _BXT_PHY1_BASE, \ 611 _BXT_PHY2_BASE) 612 613 #define _BXT_PHY(phy, reg) \ 614 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 615 616 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 617 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 618 (reg_ch1) - _BXT_PHY0_BASE)) 619 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 620 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 621 622 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 623 #define MIPIO_RST_CTRL (1 << 2) 624 625 #define _BXT_PHY_CTL_DDI_A 0x64C00 626 #define _BXT_PHY_CTL_DDI_B 0x64C10 627 #define _BXT_PHY_CTL_DDI_C 0x64C20 628 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 629 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 630 #define BXT_PHY_LANE_ENABLED (1 << 8) 631 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 632 _BXT_PHY_CTL_DDI_B) 633 634 #define _PHY_CTL_FAMILY_EDP 0x64C80 635 #define _PHY_CTL_FAMILY_DDI 0x64C90 636 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 637 #define COMMON_RESET_DIS (1 << 31) 638 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 639 _PHY_CTL_FAMILY_EDP, \ 640 _PHY_CTL_FAMILY_DDI_C) 641 642 /* BXT PHY PLL registers */ 643 #define _PORT_PLL_A 0x46074 644 #define _PORT_PLL_B 0x46078 645 #define _PORT_PLL_C 0x4607c 646 #define PORT_PLL_ENABLE REG_BIT(31) 647 #define PORT_PLL_LOCK REG_BIT(30) 648 #define PORT_PLL_REF_SEL REG_BIT(27) 649 #define PORT_PLL_POWER_ENABLE REG_BIT(26) 650 #define PORT_PLL_POWER_STATE REG_BIT(25) 651 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 652 653 #define _PORT_PLL_EBB_0_A 0x162034 654 #define _PORT_PLL_EBB_0_B 0x6C034 655 #define _PORT_PLL_EBB_0_C 0x6C340 656 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) 657 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) 658 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) 659 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) 660 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 661 _PORT_PLL_EBB_0_B, \ 662 _PORT_PLL_EBB_0_C) 663 664 #define _PORT_PLL_EBB_4_A 0x162038 665 #define _PORT_PLL_EBB_4_B 0x6C038 666 #define _PORT_PLL_EBB_4_C 0x6C344 667 #define PORT_PLL_RECALIBRATE REG_BIT(14) 668 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) 669 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 670 _PORT_PLL_EBB_4_B, \ 671 _PORT_PLL_EBB_4_C) 672 673 #define _PORT_PLL_0_A 0x162100 674 #define _PORT_PLL_0_B 0x6C100 675 #define _PORT_PLL_0_C 0x6C380 676 /* PORT_PLL_0_A */ 677 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) 678 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) 679 /* PORT_PLL_1_A */ 680 #define PORT_PLL_N_MASK REG_GENMASK(11, 8) 681 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) 682 /* PORT_PLL_2_A */ 683 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) 684 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) 685 /* PORT_PLL_3_A */ 686 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) 687 /* PORT_PLL_6_A */ 688 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) 689 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) 690 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) 691 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) 692 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) 693 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) 694 /* PORT_PLL_8_A */ 695 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) 696 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) 697 /* PORT_PLL_9_A */ 698 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) 699 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) 700 /* PORT_PLL_10_A */ 701 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) 702 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) 703 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) 704 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 705 _PORT_PLL_0_B, \ 706 _PORT_PLL_0_C) 707 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 708 (idx) * 4) 709 710 /* BXT PHY common lane registers */ 711 #define _PORT_CL1CM_DW0_A 0x162000 712 #define _PORT_CL1CM_DW0_BC 0x6C000 713 #define PHY_POWER_GOOD (1 << 16) 714 #define PHY_RESERVED (1 << 7) 715 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 716 717 #define _PORT_CL1CM_DW9_A 0x162024 718 #define _PORT_CL1CM_DW9_BC 0x6C024 719 #define IREF0RC_OFFSET_SHIFT 8 720 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 721 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 722 723 #define _PORT_CL1CM_DW10_A 0x162028 724 #define _PORT_CL1CM_DW10_BC 0x6C028 725 #define IREF1RC_OFFSET_SHIFT 8 726 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 727 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 728 729 #define _PORT_CL1CM_DW28_A 0x162070 730 #define _PORT_CL1CM_DW28_BC 0x6C070 731 #define OCL1_POWER_DOWN_EN (1 << 23) 732 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 733 #define SUS_CLK_CONFIG 0x3 734 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 735 736 #define _PORT_CL1CM_DW30_A 0x162078 737 #define _PORT_CL1CM_DW30_BC 0x6C078 738 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 739 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 740 741 /* The spec defines this only for BXT PHY0, but lets assume that this 742 * would exist for PHY1 too if it had a second channel. 743 */ 744 #define _PORT_CL2CM_DW6_A 0x162358 745 #define _PORT_CL2CM_DW6_BC 0x6C358 746 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 747 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 748 749 /* BXT PHY Ref registers */ 750 #define _PORT_REF_DW3_A 0x16218C 751 #define _PORT_REF_DW3_BC 0x6C18C 752 #define GRC_DONE (1 << 22) 753 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 754 755 #define _PORT_REF_DW6_A 0x162198 756 #define _PORT_REF_DW6_BC 0x6C198 757 #define GRC_CODE_SHIFT 24 758 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 759 #define GRC_CODE_FAST_SHIFT 16 760 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 761 #define GRC_CODE_SLOW_SHIFT 8 762 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 763 #define GRC_CODE_NOM_MASK 0xFF 764 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 765 766 #define _PORT_REF_DW8_A 0x1621A0 767 #define _PORT_REF_DW8_BC 0x6C1A0 768 #define GRC_DIS (1 << 15) 769 #define GRC_RDY_OVRD (1 << 1) 770 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 771 772 /* BXT PHY PCS registers */ 773 #define _PORT_PCS_DW10_LN01_A 0x162428 774 #define _PORT_PCS_DW10_LN01_B 0x6C428 775 #define _PORT_PCS_DW10_LN01_C 0x6C828 776 #define _PORT_PCS_DW10_GRP_A 0x162C28 777 #define _PORT_PCS_DW10_GRP_B 0x6CC28 778 #define _PORT_PCS_DW10_GRP_C 0x6CE28 779 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 780 _PORT_PCS_DW10_LN01_B, \ 781 _PORT_PCS_DW10_LN01_C) 782 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 783 _PORT_PCS_DW10_GRP_B, \ 784 _PORT_PCS_DW10_GRP_C) 785 786 #define TX2_SWING_CALC_INIT (1 << 31) 787 #define TX1_SWING_CALC_INIT (1 << 30) 788 789 #define _PORT_PCS_DW12_LN01_A 0x162430 790 #define _PORT_PCS_DW12_LN01_B 0x6C430 791 #define _PORT_PCS_DW12_LN01_C 0x6C830 792 #define _PORT_PCS_DW12_LN23_A 0x162630 793 #define _PORT_PCS_DW12_LN23_B 0x6C630 794 #define _PORT_PCS_DW12_LN23_C 0x6CA30 795 #define _PORT_PCS_DW12_GRP_A 0x162c30 796 #define _PORT_PCS_DW12_GRP_B 0x6CC30 797 #define _PORT_PCS_DW12_GRP_C 0x6CE30 798 #define LANESTAGGER_STRAP_OVRD (1 << 6) 799 #define LANE_STAGGER_MASK 0x1F 800 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 801 _PORT_PCS_DW12_LN01_B, \ 802 _PORT_PCS_DW12_LN01_C) 803 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 804 _PORT_PCS_DW12_LN23_B, \ 805 _PORT_PCS_DW12_LN23_C) 806 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 807 _PORT_PCS_DW12_GRP_B, \ 808 _PORT_PCS_DW12_GRP_C) 809 810 /* BXT PHY TX registers */ 811 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 812 ((lane) & 1) * 0x80) 813 814 #define _PORT_TX_DW2_LN0_A 0x162508 815 #define _PORT_TX_DW2_LN0_B 0x6C508 816 #define _PORT_TX_DW2_LN0_C 0x6C908 817 #define _PORT_TX_DW2_GRP_A 0x162D08 818 #define _PORT_TX_DW2_GRP_B 0x6CD08 819 #define _PORT_TX_DW2_GRP_C 0x6CF08 820 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 821 _PORT_TX_DW2_LN0_B, \ 822 _PORT_TX_DW2_LN0_C) 823 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 824 _PORT_TX_DW2_GRP_B, \ 825 _PORT_TX_DW2_GRP_C) 826 #define MARGIN_000_SHIFT 16 827 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 828 #define UNIQ_TRANS_SCALE_SHIFT 8 829 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 830 831 #define _PORT_TX_DW3_LN0_A 0x16250C 832 #define _PORT_TX_DW3_LN0_B 0x6C50C 833 #define _PORT_TX_DW3_LN0_C 0x6C90C 834 #define _PORT_TX_DW3_GRP_A 0x162D0C 835 #define _PORT_TX_DW3_GRP_B 0x6CD0C 836 #define _PORT_TX_DW3_GRP_C 0x6CF0C 837 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 838 _PORT_TX_DW3_LN0_B, \ 839 _PORT_TX_DW3_LN0_C) 840 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 841 _PORT_TX_DW3_GRP_B, \ 842 _PORT_TX_DW3_GRP_C) 843 #define SCALE_DCOMP_METHOD (1 << 26) 844 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 845 846 #define _PORT_TX_DW4_LN0_A 0x162510 847 #define _PORT_TX_DW4_LN0_B 0x6C510 848 #define _PORT_TX_DW4_LN0_C 0x6C910 849 #define _PORT_TX_DW4_GRP_A 0x162D10 850 #define _PORT_TX_DW4_GRP_B 0x6CD10 851 #define _PORT_TX_DW4_GRP_C 0x6CF10 852 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 853 _PORT_TX_DW4_LN0_B, \ 854 _PORT_TX_DW4_LN0_C) 855 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 856 _PORT_TX_DW4_GRP_B, \ 857 _PORT_TX_DW4_GRP_C) 858 #define DEEMPH_SHIFT 24 859 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 860 861 #define _PORT_TX_DW5_LN0_A 0x162514 862 #define _PORT_TX_DW5_LN0_B 0x6C514 863 #define _PORT_TX_DW5_LN0_C 0x6C914 864 #define _PORT_TX_DW5_GRP_A 0x162D14 865 #define _PORT_TX_DW5_GRP_B 0x6CD14 866 #define _PORT_TX_DW5_GRP_C 0x6CF14 867 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 868 _PORT_TX_DW5_LN0_B, \ 869 _PORT_TX_DW5_LN0_C) 870 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 871 _PORT_TX_DW5_GRP_B, \ 872 _PORT_TX_DW5_GRP_C) 873 #define DCC_DELAY_RANGE_1 (1 << 9) 874 #define DCC_DELAY_RANGE_2 (1 << 8) 875 876 #define _PORT_TX_DW14_LN0_A 0x162538 877 #define _PORT_TX_DW14_LN0_B 0x6C538 878 #define _PORT_TX_DW14_LN0_C 0x6C938 879 #define LATENCY_OPTIM_SHIFT 30 880 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 881 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 882 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 883 _PORT_TX_DW14_LN0_C) + \ 884 _BXT_LANE_OFFSET(lane)) 885 886 /* UAIMI scratch pad register 1 */ 887 #define UAIMI_SPR1 _MMIO(0x4F074) 888 /* SKL VccIO mask */ 889 #define SKL_VCCIO_MASK 0x1 890 /* SKL balance leg register */ 891 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 892 /* I_boost values */ 893 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 894 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 895 /* Balance leg disable bits */ 896 #define BALANCE_LEG_DISABLE_SHIFT 23 897 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 898 899 /* 900 * Fence registers 901 * [0-7] @ 0x2000 gen2,gen3 902 * [8-15] @ 0x3000 945,g33,pnv 903 * 904 * [0-15] @ 0x3000 gen4,gen5 905 * 906 * [0-15] @ 0x100000 gen6,vlv,chv 907 * [0-31] @ 0x100000 gen7+ 908 */ 909 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 910 #define I830_FENCE_START_MASK 0x07f80000 911 #define I830_FENCE_TILING_Y_SHIFT 12 912 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 913 #define I830_FENCE_PITCH_SHIFT 4 914 #define I830_FENCE_REG_VALID (1 << 0) 915 #define I915_FENCE_MAX_PITCH_VAL 4 916 #define I830_FENCE_MAX_PITCH_VAL 6 917 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 918 919 #define I915_FENCE_START_MASK 0x0ff00000 920 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 921 922 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 923 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 924 #define I965_FENCE_PITCH_SHIFT 2 925 #define I965_FENCE_TILING_Y_SHIFT 1 926 #define I965_FENCE_REG_VALID (1 << 0) 927 #define I965_FENCE_MAX_PITCH_VAL 0x0400 928 929 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 930 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 931 #define GEN6_FENCE_PITCH_SHIFT 32 932 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 933 934 935 /* control register for cpu gtt access */ 936 #define TILECTL _MMIO(0x101000) 937 #define TILECTL_SWZCTL (1 << 0) 938 #define TILECTL_TLBPF (1 << 1) 939 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 940 #define TILECTL_BACKSNOOP_DIS (1 << 3) 941 942 /* 943 * Instruction and interrupt control regs 944 */ 945 #define PGTBL_CTL _MMIO(0x02020) 946 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 947 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 948 #define PGTBL_ER _MMIO(0x02024) 949 #define PRB0_BASE (0x2030 - 0x30) 950 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 951 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 952 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 953 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 954 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 955 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 956 #define RENDER_RING_BASE 0x02000 957 #define BSD_RING_BASE 0x04000 958 #define GEN6_BSD_RING_BASE 0x12000 959 #define GEN8_BSD2_RING_BASE 0x1c000 960 #define GEN11_BSD_RING_BASE 0x1c0000 961 #define GEN11_BSD2_RING_BASE 0x1c4000 962 #define GEN11_BSD3_RING_BASE 0x1d0000 963 #define GEN11_BSD4_RING_BASE 0x1d4000 964 #define XEHP_BSD5_RING_BASE 0x1e0000 965 #define XEHP_BSD6_RING_BASE 0x1e4000 966 #define XEHP_BSD7_RING_BASE 0x1f0000 967 #define XEHP_BSD8_RING_BASE 0x1f4000 968 #define VEBOX_RING_BASE 0x1a000 969 #define GEN11_VEBOX_RING_BASE 0x1c8000 970 #define GEN11_VEBOX2_RING_BASE 0x1d8000 971 #define XEHP_VEBOX3_RING_BASE 0x1e8000 972 #define XEHP_VEBOX4_RING_BASE 0x1f8000 973 #define GEN12_COMPUTE0_RING_BASE 0x1a000 974 #define GEN12_COMPUTE1_RING_BASE 0x1c000 975 #define GEN12_COMPUTE2_RING_BASE 0x1e000 976 #define GEN12_COMPUTE3_RING_BASE 0x26000 977 #define BLT_RING_BASE 0x22000 978 #define XEHPC_BCS1_RING_BASE 0x3e0000 979 #define XEHPC_BCS2_RING_BASE 0x3e2000 980 #define XEHPC_BCS3_RING_BASE 0x3e4000 981 #define XEHPC_BCS4_RING_BASE 0x3e6000 982 #define XEHPC_BCS5_RING_BASE 0x3e8000 983 #define XEHPC_BCS6_RING_BASE 0x3ea000 984 #define XEHPC_BCS7_RING_BASE 0x3ec000 985 #define XEHPC_BCS8_RING_BASE 0x3ee000 986 #define DG1_GSC_HECI1_BASE 0x00258000 987 #define DG1_GSC_HECI2_BASE 0x00259000 988 #define DG2_GSC_HECI1_BASE 0x00373000 989 #define DG2_GSC_HECI2_BASE 0x00374000 990 991 992 993 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 994 #define GTT_CACHE_EN_ALL 0xF0007FFF 995 #define GEN7_WR_WATERMARK _MMIO(0x4028) 996 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 997 #define ARB_MODE _MMIO(0x4030) 998 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 999 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 1000 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 1001 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 1002 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1003 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 1004 #define GEN7_LRA_LIMITS_REG_NUM 13 1005 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 1006 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 1007 1008 #define GEN7_ERR_INT _MMIO(0x44040) 1009 #define ERR_INT_POISON (1 << 31) 1010 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 1011 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 1012 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 1013 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 1014 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 1015 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 1016 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 1017 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 1018 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 1019 1020 #define FPGA_DBG _MMIO(0x42300) 1021 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 1022 1023 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1024 #define CLAIM_ER_CLR REG_BIT(31) 1025 #define CLAIM_ER_OVERFLOW REG_BIT(16) 1026 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 1027 1028 #define DERRMR _MMIO(0x44050) 1029 /* Note that HBLANK events are reserved on bdw+ */ 1030 #define DERRMR_PIPEA_SCANLINE (1 << 0) 1031 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 1032 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 1033 #define DERRMR_PIPEA_VBLANK (1 << 3) 1034 #define DERRMR_PIPEA_HBLANK (1 << 5) 1035 #define DERRMR_PIPEB_SCANLINE (1 << 8) 1036 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 1037 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 1038 #define DERRMR_PIPEB_VBLANK (1 << 11) 1039 #define DERRMR_PIPEB_HBLANK (1 << 13) 1040 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1041 #define DERRMR_PIPEC_SCANLINE (1 << 14) 1042 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 1043 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 1044 #define DERRMR_PIPEC_VBLANK (1 << 21) 1045 #define DERRMR_PIPEC_HBLANK (1 << 22) 1046 1047 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1048 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1049 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1050 #define SCPD_FBC_IGNORE_3D (1 << 6) 1051 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 1052 #define GEN2_IER _MMIO(0x20a0) 1053 #define GEN2_IIR _MMIO(0x20a4) 1054 #define GEN2_IMR _MMIO(0x20a8) 1055 #define GEN2_ISR _MMIO(0x20ac) 1056 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1057 #define GINT_DIS (1 << 22) 1058 #define GCFG_DIS (1 << 8) 1059 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1060 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1061 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1062 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1063 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1064 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1065 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1066 #define VLV_PCBR_ADDR_SHIFT 12 1067 1068 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1069 #define EIR _MMIO(0x20b0) 1070 #define EMR _MMIO(0x20b4) 1071 #define ESR _MMIO(0x20b8) 1072 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1073 #define GM45_ERROR_MEM_PRIV (1 << 4) 1074 #define I915_ERROR_PAGE_TABLE (1 << 4) 1075 #define GM45_ERROR_CP_PRIV (1 << 3) 1076 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1077 #define I915_ERROR_INSTRUCTION (1 << 0) 1078 #define INSTPM _MMIO(0x20c0) 1079 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1080 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1081 will not assert AGPBUSY# and will only 1082 be delivered when out of C3. */ 1083 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1084 #define INSTPM_TLB_INVALIDATE (1 << 9) 1085 #define INSTPM_SYNC_FLUSH (1 << 5) 1086 #define MEM_MODE _MMIO(0x20cc) 1087 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1088 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1089 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1090 #define FW_BLC _MMIO(0x20d8) 1091 #define FW_BLC2 _MMIO(0x20dc) 1092 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1093 #define FW_BLC_SELF_EN_MASK (1 << 31) 1094 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1095 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1096 #define MM_BURST_LENGTH 0x00700000 1097 #define MM_FIFO_WATERMARK 0x0001F000 1098 #define LM_BURST_LENGTH 0x00000700 1099 #define LM_FIFO_WATERMARK 0x0000001F 1100 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1101 1102 #define _MBUS_ABOX0_CTL 0x45038 1103 #define _MBUS_ABOX1_CTL 0x45048 1104 #define _MBUS_ABOX2_CTL 0x4504C 1105 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 1106 _MBUS_ABOX1_CTL, \ 1107 _MBUS_ABOX2_CTL)) 1108 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1109 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1110 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1111 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1112 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1113 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1114 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1115 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1116 1117 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 1118 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 1119 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 1120 _PIPEB_MBUS_DBOX_CTL) 1121 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 1122 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 1123 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 1124 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 1125 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 1126 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 1127 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 1128 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 1129 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 1130 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 1131 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 1132 1133 #define MBUS_UBOX_CTL _MMIO(0x4503C) 1134 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 1135 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 1136 1137 #define MBUS_CTL _MMIO(0x4438C) 1138 #define MBUS_JOIN REG_BIT(31) 1139 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 1140 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 1141 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 1142 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 1143 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 1144 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 1145 1146 #define HDPORT_STATE _MMIO(0x45050) 1147 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) 1148 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1) 1149 #define HDPORT_ENABLED REG_BIT(0) 1150 1151 /* Make render/texture TLB fetches lower priorty than associated data 1152 * fetches. This is not turned on by default 1153 */ 1154 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1155 1156 /* Isoch request wait on GTT enable (Display A/B/C streams). 1157 * Make isoch requests stall on the TLB update. May cause 1158 * display underruns (test mode only) 1159 */ 1160 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1161 1162 /* Block grant count for isoch requests when block count is 1163 * set to a finite value. 1164 */ 1165 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1166 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1167 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1168 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1169 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1170 1171 /* Enable render writes to complete in C2/C3/C4 power states. 1172 * If this isn't enabled, render writes are prevented in low 1173 * power states. That seems bad to me. 1174 */ 1175 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1176 1177 /* This acknowledges an async flip immediately instead 1178 * of waiting for 2TLB fetches. 1179 */ 1180 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1181 1182 /* Enables non-sequential data reads through arbiter 1183 */ 1184 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1185 1186 /* Disable FSB snooping of cacheable write cycles from binner/render 1187 * command stream 1188 */ 1189 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1190 1191 /* Arbiter time slice for non-isoch streams */ 1192 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1193 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1194 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1195 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1196 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1197 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1198 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1199 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1200 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1201 1202 /* Low priority grace period page size */ 1203 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1204 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1205 1206 /* Disable display A/B trickle feed */ 1207 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1208 1209 /* Set display plane priority */ 1210 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1211 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1212 1213 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1214 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1215 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1216 1217 /* On modern GEN architectures interrupt control consists of two sets 1218 * of registers. The first set pertains to the ring generating the 1219 * interrupt. The second control is for the functional block generating the 1220 * interrupt. These are PM, GT, DE, etc. 1221 * 1222 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1223 * GT interrupt bits, so we don't need to duplicate the defines. 1224 * 1225 * These defines should cover us well from SNB->HSW with minor exceptions 1226 * it can also work on ILK. 1227 */ 1228 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1229 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1230 #define GT_BLT_USER_INTERRUPT (1 << 22) 1231 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1232 #define GT_BSD_USER_INTERRUPT (1 << 12) 1233 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1234 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1235 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1236 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1237 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1238 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1239 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1240 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1241 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1242 1243 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1244 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1245 1246 #define GT_PARITY_ERROR(dev_priv) \ 1247 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1248 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1249 1250 /* These are all the "old" interrupts */ 1251 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1252 1253 #define I915_PM_INTERRUPT (1 << 31) 1254 #define I915_ISP_INTERRUPT (1 << 22) 1255 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1256 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1257 #define I915_MIPIC_INTERRUPT (1 << 19) 1258 #define I915_MIPIA_INTERRUPT (1 << 18) 1259 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1260 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1261 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1262 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1263 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1264 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1265 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1266 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1267 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1268 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1269 #define I915_MISC_INTERRUPT (1 << 11) 1270 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1271 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1272 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1273 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1274 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1275 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1276 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1277 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1278 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1279 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1280 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1281 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1282 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1283 #define I915_DEBUG_INTERRUPT (1 << 2) 1284 #define I915_WINVALID_INTERRUPT (1 << 1) 1285 #define I915_USER_INTERRUPT (1 << 1) 1286 #define I915_ASLE_INTERRUPT (1 << 0) 1287 #define I915_BSD_USER_INTERRUPT (1 << 25) 1288 1289 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1290 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1291 1292 /* DisplayPort Audio w/ LPE */ 1293 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1294 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1295 1296 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1297 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1298 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1299 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1300 _VLV_AUD_PORT_EN_B_DBG, \ 1301 _VLV_AUD_PORT_EN_C_DBG, \ 1302 _VLV_AUD_PORT_EN_D_DBG) 1303 #define VLV_AMP_MUTE (1 << 1) 1304 1305 #define GEN6_BSD_RNCID _MMIO(0x12198) 1306 1307 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1308 #define GEN7_FF_SCHED_MASK 0x0077070 1309 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1310 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1311 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1312 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1313 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1314 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1315 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1316 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1317 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1318 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1319 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1320 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1321 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1322 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1323 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1324 1325 /* 1326 * Framebuffer compression (915+ only) 1327 */ 1328 1329 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1330 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1331 #define FBC_CONTROL _MMIO(0x3208) 1332 #define FBC_CTL_EN REG_BIT(31) 1333 #define FBC_CTL_PERIODIC REG_BIT(30) 1334 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1335 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1336 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1337 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1338 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1339 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1340 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1341 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1342 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1343 #define FBC_COMMAND _MMIO(0x320c) 1344 #define FBC_CMD_COMPRESS REG_BIT(0) 1345 #define FBC_STATUS _MMIO(0x3210) 1346 #define FBC_STAT_COMPRESSING REG_BIT(31) 1347 #define FBC_STAT_COMPRESSED REG_BIT(30) 1348 #define FBC_STAT_MODIFIED REG_BIT(29) 1349 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1350 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1351 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1352 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1353 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1354 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1355 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1356 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1357 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1358 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1359 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1360 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1361 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1362 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1363 #define FBC_MOD_NUM_VALID REG_BIT(0) 1364 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1365 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1366 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1367 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1368 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1369 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1370 1371 #define FBC_LL_SIZE (1536) 1372 1373 /* Framebuffer compression for GM45+ */ 1374 #define DPFC_CB_BASE _MMIO(0x3200) 1375 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1376 #define DPFC_CONTROL _MMIO(0x3208) 1377 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1378 #define DPFC_CTL_EN REG_BIT(31) 1379 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1380 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1381 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1382 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1383 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1384 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1385 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1386 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1387 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1388 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1389 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1390 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1391 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1392 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1393 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1394 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1395 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1396 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1397 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1398 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1399 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1400 #define DPFC_STATUS _MMIO(0x3210) 1401 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1402 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1403 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1404 #define DPFC_STATUS2 _MMIO(0x3214) 1405 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1406 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1407 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1408 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1409 #define DPFC_CHICKEN _MMIO(0x3224) 1410 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1411 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1412 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1413 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1414 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1415 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1416 1417 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1418 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1419 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1420 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1421 1422 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1423 #define ILK_FBC_RT_VALID REG_BIT(0) 1424 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1425 1426 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1427 #define ILK_FBCQ_DIS (1 << 22) 1428 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1429 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1430 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1431 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1432 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1433 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1434 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1435 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1436 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1437 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1438 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1439 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1440 1441 1442 /* 1443 * Framebuffer compression for Sandybridge 1444 * 1445 * The following two registers are of type GTTMMADR 1446 */ 1447 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1448 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1449 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1450 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1451 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1452 1453 /* Framebuffer compression for Ivybridge */ 1454 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1455 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1456 1457 #define IPS_CTL _MMIO(0x43408) 1458 #define IPS_ENABLE (1 << 31) 1459 1460 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1461 #define FBC_REND_NUKE REG_BIT(2) 1462 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1463 1464 /* 1465 * GPIO regs 1466 */ 1467 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 1468 4 * (gpio)) 1469 1470 # define GPIO_CLOCK_DIR_MASK (1 << 0) 1471 # define GPIO_CLOCK_DIR_IN (0 << 1) 1472 # define GPIO_CLOCK_DIR_OUT (1 << 1) 1473 # define GPIO_CLOCK_VAL_MASK (1 << 2) 1474 # define GPIO_CLOCK_VAL_OUT (1 << 3) 1475 # define GPIO_CLOCK_VAL_IN (1 << 4) 1476 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1477 # define GPIO_DATA_DIR_MASK (1 << 8) 1478 # define GPIO_DATA_DIR_IN (0 << 9) 1479 # define GPIO_DATA_DIR_OUT (1 << 9) 1480 # define GPIO_DATA_VAL_MASK (1 << 10) 1481 # define GPIO_DATA_VAL_OUT (1 << 11) 1482 # define GPIO_DATA_VAL_IN (1 << 12) 1483 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1484 1485 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 1486 #define GMBUS_AKSV_SELECT (1 << 11) 1487 #define GMBUS_RATE_100KHZ (0 << 8) 1488 #define GMBUS_RATE_50KHZ (1 << 8) 1489 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 1490 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 1491 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 1492 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 1493 1494 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 1495 #define GMBUS_SW_CLR_INT (1 << 31) 1496 #define GMBUS_SW_RDY (1 << 30) 1497 #define GMBUS_ENT (1 << 29) /* enable timeout */ 1498 #define GMBUS_CYCLE_NONE (0 << 25) 1499 #define GMBUS_CYCLE_WAIT (1 << 25) 1500 #define GMBUS_CYCLE_INDEX (2 << 25) 1501 #define GMBUS_CYCLE_STOP (4 << 25) 1502 #define GMBUS_BYTE_COUNT_SHIFT 16 1503 #define GMBUS_BYTE_COUNT_MAX 256U 1504 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 1505 #define GMBUS_SLAVE_INDEX_SHIFT 8 1506 #define GMBUS_SLAVE_ADDR_SHIFT 1 1507 #define GMBUS_SLAVE_READ (1 << 0) 1508 #define GMBUS_SLAVE_WRITE (0 << 0) 1509 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 1510 #define GMBUS_INUSE (1 << 15) 1511 #define GMBUS_HW_WAIT_PHASE (1 << 14) 1512 #define GMBUS_STALL_TIMEOUT (1 << 13) 1513 #define GMBUS_INT (1 << 12) 1514 #define GMBUS_HW_RDY (1 << 11) 1515 #define GMBUS_SATOER (1 << 10) 1516 #define GMBUS_ACTIVE (1 << 9) 1517 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 1518 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 1519 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 1520 #define GMBUS_NAK_EN (1 << 3) 1521 #define GMBUS_IDLE_EN (1 << 2) 1522 #define GMBUS_HW_WAIT_EN (1 << 1) 1523 #define GMBUS_HW_RDY_EN (1 << 0) 1524 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 1525 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 1526 1527 /* 1528 * Clock control & power management 1529 */ 1530 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1531 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1532 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1533 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1534 1535 #define VGA0 _MMIO(0x6000) 1536 #define VGA1 _MMIO(0x6004) 1537 #define VGA_PD _MMIO(0x6010) 1538 #define VGA0_PD_P2_DIV_4 (1 << 7) 1539 #define VGA0_PD_P1_DIV_2 (1 << 5) 1540 #define VGA0_PD_P1_SHIFT 0 1541 #define VGA0_PD_P1_MASK (0x1f << 0) 1542 #define VGA1_PD_P2_DIV_4 (1 << 15) 1543 #define VGA1_PD_P1_DIV_2 (1 << 13) 1544 #define VGA1_PD_P1_SHIFT 8 1545 #define VGA1_PD_P1_MASK (0x1f << 8) 1546 #define DPLL_VCO_ENABLE (1 << 31) 1547 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1548 #define DPLL_DVO_2X_MODE (1 << 30) 1549 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1550 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1551 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1552 #define DPLL_VGA_MODE_DIS (1 << 28) 1553 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1554 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1555 #define DPLL_MODE_MASK (3 << 26) 1556 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1557 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1558 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1559 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1560 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1561 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1562 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1563 #define DPLL_LOCK_VLV (1 << 15) 1564 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1565 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1566 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1567 #define DPLL_PORTC_READY_MASK (0xf << 4) 1568 #define DPLL_PORTB_READY_MASK (0xf) 1569 1570 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1571 1572 /* Additional CHV pll/phy registers */ 1573 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1574 #define DPLL_PORTD_READY_MASK (0xf) 1575 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1576 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1577 #define PHY_LDO_DELAY_0NS 0x0 1578 #define PHY_LDO_DELAY_200NS 0x1 1579 #define PHY_LDO_DELAY_600NS 0x2 1580 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1581 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1582 #define PHY_CH_SU_PSR 0x1 1583 #define PHY_CH_DEEP_PSR 0x7 1584 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1585 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1586 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1587 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1588 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1589 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1590 1591 /* 1592 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1593 * this field (only one bit may be set). 1594 */ 1595 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1596 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1597 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1598 /* i830, required in DVO non-gang */ 1599 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1600 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1601 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1602 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1603 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1604 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1605 #define PLL_REF_INPUT_MASK (3 << 13) 1606 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1607 /* Ironlake */ 1608 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1609 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1610 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1611 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1612 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1613 1614 /* 1615 * Parallel to Serial Load Pulse phase selection. 1616 * Selects the phase for the 10X DPLL clock for the PCIe 1617 * digital display port. The range is 4 to 13; 10 or more 1618 * is just a flip delay. The default is 6 1619 */ 1620 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1621 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1622 /* 1623 * SDVO multiplier for 945G/GM. Not used on 965. 1624 */ 1625 #define SDVO_MULTIPLIER_MASK 0x000000ff 1626 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1627 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1628 1629 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1630 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1631 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1632 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1633 1634 /* 1635 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1636 * 1637 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1638 */ 1639 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1640 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1641 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1642 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1643 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1644 /* 1645 * SDVO/UDI pixel multiplier. 1646 * 1647 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1648 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1649 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1650 * dummy bytes in the datastream at an increased clock rate, with both sides of 1651 * the link knowing how many bytes are fill. 1652 * 1653 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1654 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1655 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1656 * through an SDVO command. 1657 * 1658 * This register field has values of multiplication factor minus 1, with 1659 * a maximum multiplier of 5 for SDVO. 1660 */ 1661 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1662 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1663 /* 1664 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1665 * This best be set to the default value (3) or the CRT won't work. No, 1666 * I don't entirely understand what this does... 1667 */ 1668 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1669 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1670 1671 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1672 1673 #define _FPA0 0x6040 1674 #define _FPA1 0x6044 1675 #define _FPB0 0x6048 1676 #define _FPB1 0x604c 1677 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1678 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1679 #define FP_N_DIV_MASK 0x003f0000 1680 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1681 #define FP_N_DIV_SHIFT 16 1682 #define FP_M1_DIV_MASK 0x00003f00 1683 #define FP_M1_DIV_SHIFT 8 1684 #define FP_M2_DIV_MASK 0x0000003f 1685 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1686 #define FP_M2_DIV_SHIFT 0 1687 #define DPLL_TEST _MMIO(0x606c) 1688 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1689 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1690 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1691 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1692 #define DPLLB_TEST_N_BYPASS (1 << 19) 1693 #define DPLLB_TEST_M_BYPASS (1 << 18) 1694 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1695 #define DPLLA_TEST_N_BYPASS (1 << 3) 1696 #define DPLLA_TEST_M_BYPASS (1 << 2) 1697 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1698 #define D_STATE _MMIO(0x6104) 1699 #define DSTATE_GFX_RESET_I830 (1 << 6) 1700 #define DSTATE_PLL_D3_OFF (1 << 3) 1701 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1702 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1703 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 1704 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1705 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1706 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1707 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1708 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1709 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1710 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1711 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1712 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1713 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1714 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1715 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1716 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1717 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1718 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1719 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1720 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1721 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1722 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1723 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1724 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1725 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1726 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1727 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1728 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1729 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1730 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1731 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1732 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1733 /* 1734 * This bit must be set on the 830 to prevent hangs when turning off the 1735 * overlay scaler. 1736 */ 1737 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1738 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1739 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1740 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1741 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1742 1743 #define RENCLK_GATE_D1 _MMIO(0x6204) 1744 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1745 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1746 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1747 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1748 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1749 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1750 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1751 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1752 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1753 /* This bit must be unset on 855,865 */ 1754 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1755 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1756 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1757 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1758 /* This bit must be set on 855,865. */ 1759 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1760 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1761 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1762 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1763 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1764 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1765 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1766 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1767 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1768 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1769 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1770 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1771 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1772 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1773 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1774 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1775 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1776 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1777 1778 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1779 /* This bit must always be set on 965G/965GM */ 1780 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1781 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1782 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1783 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1784 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1785 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1786 /* This bit must always be set on 965G */ 1787 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1788 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1789 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1790 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1791 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1792 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1793 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1794 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1795 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1796 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1797 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1798 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1799 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1800 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1801 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1802 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1803 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1804 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1805 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1806 1807 #define RENCLK_GATE_D2 _MMIO(0x6208) 1808 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1809 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1810 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1811 1812 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1813 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1814 1815 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1816 #define DEUC _MMIO(0x6214) /* CRL only */ 1817 1818 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1819 #define FW_CSPWRDWNEN (1 << 15) 1820 1821 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1822 1823 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1824 #define CDCLK_FREQ_SHIFT 4 1825 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1826 #define CZCLK_FREQ_MASK 0xf 1827 1828 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1829 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1830 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1831 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1832 #define PFI_CREDIT_RESEND (1 << 27) 1833 #define VGA_FAST_MODE_DISABLE (1 << 14) 1834 1835 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1836 1837 /* 1838 * Palette regs 1839 */ 1840 #define _PALETTE_A 0xa000 1841 #define _PALETTE_B 0xa800 1842 #define _CHV_PALETTE_C 0xc000 1843 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1844 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1845 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1846 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1847 _PICK((pipe), _PALETTE_A, \ 1848 _PALETTE_B, _CHV_PALETTE_C) + \ 1849 (i) * 4) 1850 1851 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1852 1853 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1854 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1855 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1856 #define PVC_RP_STATE_CAP _MMIO(0x281014) 1857 1858 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1859 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1860 #define PROCHOT_MASK REG_BIT(1) 1861 #define THERMAL_LIMIT_MASK REG_BIT(2) 1862 #define RATL_MASK REG_BIT(6) 1863 #define VR_THERMALERT_MASK REG_BIT(7) 1864 #define VR_TDC_MASK REG_BIT(8) 1865 #define POWER_LIMIT_4_MASK REG_BIT(9) 1866 #define POWER_LIMIT_1_MASK REG_BIT(11) 1867 #define POWER_LIMIT_2_MASK REG_BIT(12) 1868 1869 #define CHV_CLK_CTL1 _MMIO(0x101100) 1870 #define VLV_CLK_CTL2 _MMIO(0x101104) 1871 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1872 1873 /* 1874 * Overlay regs 1875 */ 1876 1877 #define OVADD _MMIO(0x30000) 1878 #define DOVSTA _MMIO(0x30008) 1879 #define OC_BUF (0x3 << 20) 1880 #define OGAMC5 _MMIO(0x30010) 1881 #define OGAMC4 _MMIO(0x30014) 1882 #define OGAMC3 _MMIO(0x30018) 1883 #define OGAMC2 _MMIO(0x3001c) 1884 #define OGAMC1 _MMIO(0x30020) 1885 #define OGAMC0 _MMIO(0x30024) 1886 1887 /* 1888 * GEN9 clock gating regs 1889 */ 1890 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1891 #define DARBF_GATING_DIS (1 << 27) 1892 #define PWM2_GATING_DIS (1 << 14) 1893 #define PWM1_GATING_DIS (1 << 13) 1894 1895 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1896 #define TGL_VRH_GATING_DIS REG_BIT(31) 1897 #define DPT_GATING_DIS REG_BIT(22) 1898 1899 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1900 #define BXT_GMBUS_GATING_DIS (1 << 14) 1901 1902 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1903 #define DPCE_GATING_DIS REG_BIT(17) 1904 1905 #define _CLKGATE_DIS_PSL_A 0x46520 1906 #define _CLKGATE_DIS_PSL_B 0x46524 1907 #define _CLKGATE_DIS_PSL_C 0x46528 1908 #define DUPS1_GATING_DIS (1 << 15) 1909 #define DUPS2_GATING_DIS (1 << 19) 1910 #define DUPS3_GATING_DIS (1 << 23) 1911 #define CURSOR_GATING_DIS REG_BIT(28) 1912 #define DPF_GATING_DIS (1 << 10) 1913 #define DPF_RAM_GATING_DIS (1 << 9) 1914 #define DPFR_GATING_DIS (1 << 8) 1915 1916 #define CLKGATE_DIS_PSL(pipe) \ 1917 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1918 1919 /* 1920 * Display engine regs 1921 */ 1922 1923 /* Pipe A CRC regs */ 1924 #define _PIPE_CRC_CTL_A 0x60050 1925 #define PIPE_CRC_ENABLE REG_BIT(31) 1926 /* skl+ source selection */ 1927 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1928 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1929 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1930 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1931 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1932 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1933 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1934 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1935 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1936 /* ivb+ source selection */ 1937 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1938 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1939 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1940 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1941 /* ilk+ source selection */ 1942 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1943 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1944 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1945 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1946 /* embedded DP port on the north display block */ 1947 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1948 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1949 /* vlv source selection */ 1950 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1951 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1952 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1953 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1954 /* with DP port the pipe source is invalid */ 1955 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1956 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1957 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1958 /* gen3+ source selection */ 1959 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1960 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1961 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1962 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1963 /* with DP/TV port the pipe source is invalid */ 1964 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1965 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1966 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1967 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1968 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1969 /* gen2 doesn't have source selection bits */ 1970 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1971 1972 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1973 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1974 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1975 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1976 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1977 1978 #define _PIPE_CRC_RES_RED_A 0x60060 1979 #define _PIPE_CRC_RES_GREEN_A 0x60064 1980 #define _PIPE_CRC_RES_BLUE_A 0x60068 1981 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1982 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1983 1984 /* Pipe B CRC regs */ 1985 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1986 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1987 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1988 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1989 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1990 1991 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1992 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1993 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1994 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1995 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1996 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1997 1998 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1999 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 2000 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 2001 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 2002 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 2003 2004 /* Pipe A timing regs */ 2005 #define _HTOTAL_A 0x60000 2006 #define _HBLANK_A 0x60004 2007 #define _HSYNC_A 0x60008 2008 #define _VTOTAL_A 0x6000c 2009 #define _VBLANK_A 0x60010 2010 #define _VSYNC_A 0x60014 2011 #define _EXITLINE_A 0x60018 2012 #define _PIPEASRC 0x6001c 2013 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 2014 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 2015 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 2016 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 2017 #define _BCLRPAT_A 0x60020 2018 #define _VSYNCSHIFT_A 0x60028 2019 #define _PIPE_MULT_A 0x6002c 2020 2021 /* Pipe B timing regs */ 2022 #define _HTOTAL_B 0x61000 2023 #define _HBLANK_B 0x61004 2024 #define _HSYNC_B 0x61008 2025 #define _VTOTAL_B 0x6100c 2026 #define _VBLANK_B 0x61010 2027 #define _VSYNC_B 0x61014 2028 #define _PIPEBSRC 0x6101c 2029 #define _BCLRPAT_B 0x61020 2030 #define _VSYNCSHIFT_B 0x61028 2031 #define _PIPE_MULT_B 0x6102c 2032 2033 /* DSI 0 timing regs */ 2034 #define _HTOTAL_DSI0 0x6b000 2035 #define _HSYNC_DSI0 0x6b008 2036 #define _VTOTAL_DSI0 0x6b00c 2037 #define _VSYNC_DSI0 0x6b014 2038 #define _VSYNCSHIFT_DSI0 0x6b028 2039 2040 /* DSI 1 timing regs */ 2041 #define _HTOTAL_DSI1 0x6b800 2042 #define _HSYNC_DSI1 0x6b808 2043 #define _VTOTAL_DSI1 0x6b80c 2044 #define _VSYNC_DSI1 0x6b814 2045 #define _VSYNCSHIFT_DSI1 0x6b828 2046 2047 #define TRANSCODER_A_OFFSET 0x60000 2048 #define TRANSCODER_B_OFFSET 0x61000 2049 #define TRANSCODER_C_OFFSET 0x62000 2050 #define CHV_TRANSCODER_C_OFFSET 0x63000 2051 #define TRANSCODER_D_OFFSET 0x63000 2052 #define TRANSCODER_EDP_OFFSET 0x6f000 2053 #define TRANSCODER_DSI0_OFFSET 0x6b000 2054 #define TRANSCODER_DSI1_OFFSET 0x6b800 2055 2056 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 2057 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 2058 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 2059 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 2060 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 2061 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 2062 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 2063 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 2064 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 2065 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 2066 2067 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 2068 #define EXITLINE_ENABLE REG_BIT(31) 2069 #define EXITLINE_MASK REG_GENMASK(12, 0) 2070 #define EXITLINE_SHIFT 0 2071 2072 /* VRR registers */ 2073 #define _TRANS_VRR_CTL_A 0x60420 2074 #define _TRANS_VRR_CTL_B 0x61420 2075 #define _TRANS_VRR_CTL_C 0x62420 2076 #define _TRANS_VRR_CTL_D 0x63420 2077 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 2078 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 2079 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 2080 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 2081 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 2082 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 2083 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 2084 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 2085 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 2086 2087 #define _TRANS_VRR_VMAX_A 0x60424 2088 #define _TRANS_VRR_VMAX_B 0x61424 2089 #define _TRANS_VRR_VMAX_C 0x62424 2090 #define _TRANS_VRR_VMAX_D 0x63424 2091 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 2092 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 2093 2094 #define _TRANS_VRR_VMIN_A 0x60434 2095 #define _TRANS_VRR_VMIN_B 0x61434 2096 #define _TRANS_VRR_VMIN_C 0x62434 2097 #define _TRANS_VRR_VMIN_D 0x63434 2098 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2099 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2100 2101 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2102 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2103 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2104 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2105 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2106 _TRANS_VRR_VMAXSHIFT_A) 2107 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2108 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2109 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2110 2111 #define _TRANS_VRR_STATUS_A 0x6042C 2112 #define _TRANS_VRR_STATUS_B 0x6142C 2113 #define _TRANS_VRR_STATUS_C 0x6242C 2114 #define _TRANS_VRR_STATUS_D 0x6342C 2115 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2116 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2117 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2118 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2119 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2120 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2121 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2122 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2123 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2124 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2125 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2126 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2127 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2128 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2129 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2130 2131 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2132 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2133 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2134 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2135 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2136 _TRANS_VRR_VTOTAL_PREV_A) 2137 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2138 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2139 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2140 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2141 2142 #define _TRANS_VRR_FLIPLINE_A 0x60438 2143 #define _TRANS_VRR_FLIPLINE_B 0x61438 2144 #define _TRANS_VRR_FLIPLINE_C 0x62438 2145 #define _TRANS_VRR_FLIPLINE_D 0x63438 2146 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2147 _TRANS_VRR_FLIPLINE_A) 2148 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2149 2150 #define _TRANS_VRR_STATUS2_A 0x6043C 2151 #define _TRANS_VRR_STATUS2_B 0x6143C 2152 #define _TRANS_VRR_STATUS2_C 0x6243C 2153 #define _TRANS_VRR_STATUS2_D 0x6343C 2154 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2155 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2156 2157 #define _TRANS_PUSH_A 0x60A70 2158 #define _TRANS_PUSH_B 0x61A70 2159 #define _TRANS_PUSH_C 0x62A70 2160 #define _TRANS_PUSH_D 0x63A70 2161 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2162 #define TRANS_PUSH_EN REG_BIT(31) 2163 #define TRANS_PUSH_SEND REG_BIT(30) 2164 2165 /* 2166 * HSW+ eDP PSR registers 2167 * 2168 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 2169 * instance of it 2170 */ 2171 #define _SRD_CTL_A 0x60800 2172 #define _SRD_CTL_EDP 0x6f800 2173 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 2174 #define EDP_PSR_ENABLE (1 << 31) 2175 #define BDW_PSR_SINGLE_FRAME (1 << 30) 2176 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 2177 #define EDP_PSR_LINK_STANDBY (1 << 27) 2178 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 2179 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 2180 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 2181 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 2182 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 2183 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2184 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 2185 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 2186 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 2187 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 2188 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 2189 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 2190 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 2191 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 2192 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 2193 #define EDP_PSR_TP1_TIME_500us (0 << 4) 2194 #define EDP_PSR_TP1_TIME_100us (1 << 4) 2195 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 2196 #define EDP_PSR_TP1_TIME_0us (3 << 4) 2197 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2198 2199 /* 2200 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 2201 * to transcoder and bits defined for each one as if using no shift (i.e. as if 2202 * it was for TRANSCODER_EDP) 2203 */ 2204 #define EDP_PSR_IMR _MMIO(0x64834) 2205 #define EDP_PSR_IIR _MMIO(0x64838) 2206 #define _PSR_IMR_A 0x60814 2207 #define _PSR_IIR_A 0x60818 2208 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 2209 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 2210 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 2211 0 : ((trans) - TRANSCODER_A + 1) * 8) 2212 #define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) 2213 #define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) 2214 #define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) 2215 #define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) 2216 2217 #define _SRD_AUX_DATA_A 0x60814 2218 #define _SRD_AUX_DATA_EDP 0x6f814 2219 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */ 2220 2221 #define _SRD_STATUS_A 0x60840 2222 #define _SRD_STATUS_EDP 0x6f840 2223 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 2224 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 2225 #define EDP_PSR_STATUS_STATE_SHIFT 29 2226 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 2227 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 2228 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 2229 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 2230 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 2231 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 2232 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 2233 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 2234 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 2235 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 2236 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 2237 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2238 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2239 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2240 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2241 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 2242 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 2243 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 2244 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 2245 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 2246 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2247 2248 #define _SRD_PERF_CNT_A 0x60844 2249 #define _SRD_PERF_CNT_EDP 0x6f844 2250 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 2251 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2252 2253 /* PSR_MASK on SKL+ */ 2254 #define _SRD_DEBUG_A 0x60860 2255 #define _SRD_DEBUG_EDP 0x6f860 2256 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 2257 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 2258 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 2259 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 2260 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 2261 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 2262 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 2263 2264 #define _PSR2_CTL_A 0x60900 2265 #define _PSR2_CTL_EDP 0x6f900 2266 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 2267 #define EDP_PSR2_ENABLE (1 << 31) 2268 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 2269 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 2270 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 2271 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 2272 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 2273 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 2274 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 2275 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 2276 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 2277 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 2278 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 2279 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 2280 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 2281 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 2282 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 2283 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 2284 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 2285 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 2286 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 2287 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 2288 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 2289 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 2290 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 2291 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 2292 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 2293 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 2294 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 2295 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 2296 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 2297 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 2298 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 2299 2300 #define _PSR_EVENT_TRANS_A 0x60848 2301 #define _PSR_EVENT_TRANS_B 0x61848 2302 #define _PSR_EVENT_TRANS_C 0x62848 2303 #define _PSR_EVENT_TRANS_D 0x63848 2304 #define _PSR_EVENT_TRANS_EDP 0x6f848 2305 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 2306 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 2307 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 2308 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 2309 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 2310 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 2311 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 2312 #define PSR_EVENT_MEMORY_UP (1 << 10) 2313 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 2314 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 2315 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 2316 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 2317 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 2318 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 2319 #define PSR_EVENT_VBI_ENABLE (1 << 2) 2320 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 2321 #define PSR_EVENT_PSR_DISABLE (1 << 0) 2322 2323 #define _PSR2_STATUS_A 0x60940 2324 #define _PSR2_STATUS_EDP 0x6f940 2325 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 2326 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 2327 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 2328 2329 #define _PSR2_SU_STATUS_A 0x60914 2330 #define _PSR2_SU_STATUS_EDP 0x6f914 2331 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 2332 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 2333 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 2334 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 2335 #define PSR2_SU_STATUS_FRAMES 8 2336 2337 #define _PSR2_MAN_TRK_CTL_A 0x60910 2338 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 2339 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 2340 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 2341 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 2342 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2343 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 2344 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2345 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 2346 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 2347 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 2348 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 2349 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2350 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 2351 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2352 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 2353 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 2354 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 2355 2356 /* Icelake DSC Rate Control Range Parameter Registers */ 2357 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 2358 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 2359 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 2360 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 2361 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 2362 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 2363 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 2364 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 2365 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 2366 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 2367 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 2368 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 2369 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2370 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 2371 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 2372 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2373 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2374 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 2375 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2376 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 2377 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 2378 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2379 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2380 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 2381 #define RC_BPG_OFFSET_SHIFT 10 2382 #define RC_MAX_QP_SHIFT 5 2383 #define RC_MIN_QP_SHIFT 0 2384 2385 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 2386 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 2387 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 2388 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 2389 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 2390 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 2391 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 2392 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 2393 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 2394 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 2395 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 2396 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 2397 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2398 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 2399 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 2400 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2401 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2402 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 2403 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2404 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 2405 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 2406 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2407 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2408 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 2409 2410 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 2411 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 2412 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 2413 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 2414 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 2415 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 2416 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 2417 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 2418 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 2419 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 2420 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 2421 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 2422 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2423 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 2424 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 2425 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2426 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2427 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 2428 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2429 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 2430 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 2431 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2432 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2433 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 2434 2435 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 2436 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 2437 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 2438 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 2439 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 2440 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 2441 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 2442 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 2443 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 2444 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 2445 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 2446 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 2447 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2448 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 2449 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 2450 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2451 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2452 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 2453 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2454 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 2455 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 2456 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2457 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2458 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 2459 2460 /* VGA port control */ 2461 #define ADPA _MMIO(0x61100) 2462 #define PCH_ADPA _MMIO(0xe1100) 2463 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2464 2465 #define ADPA_DAC_ENABLE (1 << 31) 2466 #define ADPA_DAC_DISABLE 0 2467 #define ADPA_PIPE_SEL_SHIFT 30 2468 #define ADPA_PIPE_SEL_MASK (1 << 30) 2469 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2470 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2471 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2472 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2473 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2474 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2475 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2476 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2477 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2478 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2479 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2480 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2481 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2482 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2483 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2484 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2485 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2486 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2487 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2488 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2489 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2490 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2491 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2492 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2493 #define ADPA_SETS_HVPOLARITY 0 2494 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2495 #define ADPA_VSYNC_CNTL_ENABLE 0 2496 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2497 #define ADPA_HSYNC_CNTL_ENABLE 0 2498 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2499 #define ADPA_VSYNC_ACTIVE_LOW 0 2500 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2501 #define ADPA_HSYNC_ACTIVE_LOW 0 2502 #define ADPA_DPMS_MASK (~(3 << 10)) 2503 #define ADPA_DPMS_ON (0 << 10) 2504 #define ADPA_DPMS_SUSPEND (1 << 10) 2505 #define ADPA_DPMS_STANDBY (2 << 10) 2506 #define ADPA_DPMS_OFF (3 << 10) 2507 2508 2509 /* Hotplug control (945+ only) */ 2510 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2511 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2512 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2513 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2514 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2515 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2516 #define TV_HOTPLUG_INT_EN (1 << 18) 2517 #define CRT_HOTPLUG_INT_EN (1 << 9) 2518 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2519 PORTC_HOTPLUG_INT_EN | \ 2520 PORTD_HOTPLUG_INT_EN | \ 2521 SDVOC_HOTPLUG_INT_EN | \ 2522 SDVOB_HOTPLUG_INT_EN | \ 2523 CRT_HOTPLUG_INT_EN) 2524 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2525 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2526 /* must use period 64 on GM45 according to docs */ 2527 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2528 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2529 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2530 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2531 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2532 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2533 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2534 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2535 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2536 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2537 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2538 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2539 2540 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2541 /* 2542 * HDMI/DP bits are g4x+ 2543 * 2544 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2545 * Please check the detailed lore in the commit message for for experimental 2546 * evidence. 2547 */ 2548 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 2549 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 2550 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 2551 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 2552 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 2553 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2554 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2555 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2556 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2557 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2558 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2559 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2560 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2561 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2562 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2563 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2564 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2565 /* CRT/TV common between gen3+ */ 2566 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2567 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2568 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2569 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2570 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2571 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2572 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2573 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2574 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2575 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2576 2577 /* SDVO is different across gen3/4 */ 2578 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2579 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2580 /* 2581 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2582 * since reality corrobates that they're the same as on gen3. But keep these 2583 * bits here (and the comment!) to help any other lost wanderers back onto the 2584 * right tracks. 2585 */ 2586 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2587 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2588 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2589 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2590 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2591 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2592 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2593 PORTB_HOTPLUG_INT_STATUS | \ 2594 PORTC_HOTPLUG_INT_STATUS | \ 2595 PORTD_HOTPLUG_INT_STATUS) 2596 2597 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2598 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2599 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2600 PORTB_HOTPLUG_INT_STATUS | \ 2601 PORTC_HOTPLUG_INT_STATUS | \ 2602 PORTD_HOTPLUG_INT_STATUS) 2603 2604 /* SDVO and HDMI port control. 2605 * The same register may be used for SDVO or HDMI */ 2606 #define _GEN3_SDVOB 0x61140 2607 #define _GEN3_SDVOC 0x61160 2608 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2609 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2610 #define GEN4_HDMIB GEN3_SDVOB 2611 #define GEN4_HDMIC GEN3_SDVOC 2612 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2613 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2614 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2615 #define PCH_SDVOB _MMIO(0xe1140) 2616 #define PCH_HDMIB PCH_SDVOB 2617 #define PCH_HDMIC _MMIO(0xe1150) 2618 #define PCH_HDMID _MMIO(0xe1160) 2619 2620 #define PORT_DFT_I9XX _MMIO(0x61150) 2621 #define DC_BALANCE_RESET (1 << 25) 2622 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2623 #define DC_BALANCE_RESET_VLV (1 << 31) 2624 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2625 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2626 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2627 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2628 2629 /* Gen 3 SDVO bits: */ 2630 #define SDVO_ENABLE (1 << 31) 2631 #define SDVO_PIPE_SEL_SHIFT 30 2632 #define SDVO_PIPE_SEL_MASK (1 << 30) 2633 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2634 #define SDVO_STALL_SELECT (1 << 29) 2635 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2636 /* 2637 * 915G/GM SDVO pixel multiplier. 2638 * Programmed value is multiplier - 1, up to 5x. 2639 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2640 */ 2641 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2642 #define SDVO_PORT_MULTIPLY_SHIFT 23 2643 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2644 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2645 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2646 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2647 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2648 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2649 #define SDVO_DETECTED (1 << 2) 2650 /* Bits to be preserved when writing */ 2651 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2652 SDVO_INTERRUPT_ENABLE) 2653 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2654 2655 /* Gen 4 SDVO/HDMI bits: */ 2656 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2657 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2658 #define SDVO_ENCODING_SDVO (0 << 10) 2659 #define SDVO_ENCODING_HDMI (2 << 10) 2660 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2661 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2662 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2663 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2664 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2665 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2666 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2667 2668 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2669 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2670 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2671 2672 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2673 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2674 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2675 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2676 2677 /* CHV SDVO/HDMI bits: */ 2678 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2679 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2680 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2681 2682 2683 /* DVO port control */ 2684 #define _DVOA 0x61120 2685 #define DVOA _MMIO(_DVOA) 2686 #define _DVOB 0x61140 2687 #define DVOB _MMIO(_DVOB) 2688 #define _DVOC 0x61160 2689 #define DVOC _MMIO(_DVOC) 2690 #define DVO_ENABLE (1 << 31) 2691 #define DVO_PIPE_SEL_SHIFT 30 2692 #define DVO_PIPE_SEL_MASK (1 << 30) 2693 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 2694 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2695 #define DVO_PIPE_STALL (1 << 28) 2696 #define DVO_PIPE_STALL_TV (2 << 28) 2697 #define DVO_PIPE_STALL_MASK (3 << 28) 2698 #define DVO_USE_VGA_SYNC (1 << 15) 2699 #define DVO_DATA_ORDER_I740 (0 << 14) 2700 #define DVO_DATA_ORDER_FP (1 << 14) 2701 #define DVO_VSYNC_DISABLE (1 << 11) 2702 #define DVO_HSYNC_DISABLE (1 << 10) 2703 #define DVO_VSYNC_TRISTATE (1 << 9) 2704 #define DVO_HSYNC_TRISTATE (1 << 8) 2705 #define DVO_BORDER_ENABLE (1 << 7) 2706 #define DVO_DATA_ORDER_GBRG (1 << 6) 2707 #define DVO_DATA_ORDER_RGGB (0 << 6) 2708 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2709 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2710 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2711 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2712 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2713 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2714 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2715 #define DVO_PRESERVE_MASK (0x7 << 24) 2716 #define DVOA_SRCDIM _MMIO(0x61124) 2717 #define DVOB_SRCDIM _MMIO(0x61144) 2718 #define DVOC_SRCDIM _MMIO(0x61164) 2719 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2720 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2721 2722 /* LVDS port control */ 2723 #define LVDS _MMIO(0x61180) 2724 /* 2725 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2726 * the DPLL semantics change when the LVDS is assigned to that pipe. 2727 */ 2728 #define LVDS_PORT_EN (1 << 31) 2729 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2730 #define LVDS_PIPE_SEL_SHIFT 30 2731 #define LVDS_PIPE_SEL_MASK (1 << 30) 2732 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 2733 #define LVDS_PIPE_SEL_SHIFT_CPT 29 2734 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 2735 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2736 /* LVDS dithering flag on 965/g4x platform */ 2737 #define LVDS_ENABLE_DITHER (1 << 25) 2738 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2739 #define LVDS_VSYNC_POLARITY (1 << 21) 2740 #define LVDS_HSYNC_POLARITY (1 << 20) 2741 2742 /* Enable border for unscaled (or aspect-scaled) display */ 2743 #define LVDS_BORDER_ENABLE (1 << 15) 2744 /* 2745 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2746 * pixel. 2747 */ 2748 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2749 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2750 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2751 /* 2752 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2753 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2754 * on. 2755 */ 2756 #define LVDS_A3_POWER_MASK (3 << 6) 2757 #define LVDS_A3_POWER_DOWN (0 << 6) 2758 #define LVDS_A3_POWER_UP (3 << 6) 2759 /* 2760 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2761 * is set. 2762 */ 2763 #define LVDS_CLKB_POWER_MASK (3 << 4) 2764 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2765 #define LVDS_CLKB_POWER_UP (3 << 4) 2766 /* 2767 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2768 * setting for whether we are in dual-channel mode. The B3 pair will 2769 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2770 */ 2771 #define LVDS_B0B3_POWER_MASK (3 << 2) 2772 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2773 #define LVDS_B0B3_POWER_UP (3 << 2) 2774 2775 /* Video Data Island Packet control */ 2776 #define VIDEO_DIP_DATA _MMIO(0x61178) 2777 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2778 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2779 * of the infoframe structure specified by CEA-861. */ 2780 #define VIDEO_DIP_DATA_SIZE 32 2781 #define VIDEO_DIP_GMP_DATA_SIZE 36 2782 #define VIDEO_DIP_VSC_DATA_SIZE 36 2783 #define VIDEO_DIP_PPS_DATA_SIZE 132 2784 #define VIDEO_DIP_CTL _MMIO(0x61170) 2785 /* Pre HSW: */ 2786 #define VIDEO_DIP_ENABLE (1 << 31) 2787 #define VIDEO_DIP_PORT(port) ((port) << 29) 2788 #define VIDEO_DIP_PORT_MASK (3 << 29) 2789 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2790 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2791 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2792 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2793 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2794 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2795 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2796 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2797 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2798 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2799 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2800 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2801 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2802 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2803 /* HSW and later: */ 2804 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2805 #define PSR_VSC_BIT_7_SET (1 << 27) 2806 #define VSC_SELECT_MASK (0x3 << 25) 2807 #define VSC_SELECT_SHIFT 25 2808 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2809 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2810 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2811 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2812 #define VDIP_ENABLE_PPS (1 << 24) 2813 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2814 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2815 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2816 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2817 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2818 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2819 2820 /* Panel power sequencing */ 2821 #define PPS_BASE 0x61200 2822 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 2823 #define PCH_PPS_BASE 0xC7200 2824 2825 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 2826 PPS_BASE + (reg) + \ 2827 (pps_idx) * 0x100) 2828 2829 #define _PP_STATUS 0x61200 2830 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 2831 #define PP_ON REG_BIT(31) 2832 /* 2833 * Indicates that all dependencies of the panel are on: 2834 * 2835 * - PLL enabled 2836 * - pipe enabled 2837 * - LVDS/DVOB/DVOC on 2838 */ 2839 #define PP_READY REG_BIT(30) 2840 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 2841 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 2842 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 2843 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 2844 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 2845 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 2846 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 2847 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 2848 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 2849 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 2850 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 2851 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 2852 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 2853 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 2854 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 2855 2856 #define _PP_CONTROL 0x61204 2857 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 2858 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 2859 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 2860 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 2861 #define EDP_FORCE_VDD REG_BIT(3) 2862 #define EDP_BLC_ENABLE REG_BIT(2) 2863 #define PANEL_POWER_RESET REG_BIT(1) 2864 #define PANEL_POWER_ON REG_BIT(0) 2865 2866 #define _PP_ON_DELAYS 0x61208 2867 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 2868 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 2869 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 2870 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 2871 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 2872 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 2873 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 2874 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 2875 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 2876 2877 #define _PP_OFF_DELAYS 0x6120C 2878 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 2879 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 2880 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 2881 2882 #define _PP_DIVISOR 0x61210 2883 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 2884 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 2885 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 2886 2887 /* Panel fitting */ 2888 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2889 #define PFIT_ENABLE (1 << 31) 2890 #define PFIT_PIPE_MASK (3 << 29) 2891 #define PFIT_PIPE_SHIFT 29 2892 #define PFIT_PIPE(pipe) ((pipe) << 29) 2893 #define VERT_INTERP_DISABLE (0 << 10) 2894 #define VERT_INTERP_BILINEAR (1 << 10) 2895 #define VERT_INTERP_MASK (3 << 10) 2896 #define VERT_AUTO_SCALE (1 << 9) 2897 #define HORIZ_INTERP_DISABLE (0 << 6) 2898 #define HORIZ_INTERP_BILINEAR (1 << 6) 2899 #define HORIZ_INTERP_MASK (3 << 6) 2900 #define HORIZ_AUTO_SCALE (1 << 5) 2901 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2902 #define PFIT_FILTER_FUZZY (0 << 24) 2903 #define PFIT_SCALING_AUTO (0 << 26) 2904 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2905 #define PFIT_SCALING_PILLAR (2 << 26) 2906 #define PFIT_SCALING_LETTER (3 << 26) 2907 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2908 /* Pre-965 */ 2909 #define PFIT_VERT_SCALE_SHIFT 20 2910 #define PFIT_VERT_SCALE_MASK 0xfff00000 2911 #define PFIT_HORIZ_SCALE_SHIFT 4 2912 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2913 /* 965+ */ 2914 #define PFIT_VERT_SCALE_SHIFT_965 16 2915 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2916 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2917 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2918 2919 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2920 2921 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 2922 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 2923 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 2924 _VLV_BLC_PWM_CTL2_B) 2925 2926 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 2927 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 2928 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 2929 _VLV_BLC_PWM_CTL_B) 2930 2931 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 2932 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 2933 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 2934 _VLV_BLC_HIST_CTL_B) 2935 2936 /* Backlight control */ 2937 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 2938 #define BLM_PWM_ENABLE (1 << 31) 2939 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 2940 #define BLM_PIPE_SELECT (1 << 29) 2941 #define BLM_PIPE_SELECT_IVB (3 << 29) 2942 #define BLM_PIPE_A (0 << 29) 2943 #define BLM_PIPE_B (1 << 29) 2944 #define BLM_PIPE_C (2 << 29) /* ivb + */ 2945 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 2946 #define BLM_TRANSCODER_B BLM_PIPE_B 2947 #define BLM_TRANSCODER_C BLM_PIPE_C 2948 #define BLM_TRANSCODER_EDP (3 << 29) 2949 #define BLM_PIPE(pipe) ((pipe) << 29) 2950 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 2951 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 2952 #define BLM_PHASE_IN_ENABLE (1 << 25) 2953 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 2954 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 2955 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 2956 #define BLM_PHASE_IN_COUNT_SHIFT (8) 2957 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 2958 #define BLM_PHASE_IN_INCR_SHIFT (0) 2959 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 2960 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 2961 /* 2962 * This is the most significant 15 bits of the number of backlight cycles in a 2963 * complete cycle of the modulated backlight control. 2964 * 2965 * The actual value is this field multiplied by two. 2966 */ 2967 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 2968 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 2969 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 2970 /* 2971 * This is the number of cycles out of the backlight modulation cycle for which 2972 * the backlight is on. 2973 * 2974 * This field must be no greater than the number of cycles in the complete 2975 * backlight modulation cycle. 2976 */ 2977 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 2978 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 2979 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 2980 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 2981 2982 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 2983 #define BLM_HISTOGRAM_ENABLE (1 << 31) 2984 2985 /* New registers for PCH-split platforms. Safe where new bits show up, the 2986 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 2987 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 2988 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 2989 2990 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 2991 2992 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 2993 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 2994 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 2995 #define BLM_PCH_PWM_ENABLE (1 << 31) 2996 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 2997 #define BLM_PCH_POLARITY (1 << 29) 2998 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 2999 3000 #define UTIL_PIN_CTL _MMIO(0x48400) 3001 #define UTIL_PIN_ENABLE (1 << 31) 3002 #define UTIL_PIN_PIPE_MASK (3 << 29) 3003 #define UTIL_PIN_PIPE(x) ((x) << 29) 3004 #define UTIL_PIN_MODE_MASK (0xf << 24) 3005 #define UTIL_PIN_MODE_DATA (0 << 24) 3006 #define UTIL_PIN_MODE_PWM (1 << 24) 3007 #define UTIL_PIN_MODE_VBLANK (4 << 24) 3008 #define UTIL_PIN_MODE_VSYNC (5 << 24) 3009 #define UTIL_PIN_MODE_EYE_LEVEL (8 << 24) 3010 #define UTIL_PIN_OUTPUT_DATA (1 << 23) 3011 #define UTIL_PIN_POLARITY (1 << 22) 3012 #define UTIL_PIN_DIRECTION_INPUT (1 << 19) 3013 #define UTIL_PIN_INPUT_DATA (1 << 16) 3014 3015 /* BXT backlight register definition. */ 3016 #define _BXT_BLC_PWM_CTL1 0xC8250 3017 #define BXT_BLC_PWM_ENABLE (1 << 31) 3018 #define BXT_BLC_PWM_POLARITY (1 << 29) 3019 #define _BXT_BLC_PWM_FREQ1 0xC8254 3020 #define _BXT_BLC_PWM_DUTY1 0xC8258 3021 3022 #define _BXT_BLC_PWM_CTL2 0xC8350 3023 #define _BXT_BLC_PWM_FREQ2 0xC8354 3024 #define _BXT_BLC_PWM_DUTY2 0xC8358 3025 3026 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 3027 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 3028 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 3029 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 3030 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 3031 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 3032 3033 #define PCH_GTC_CTL _MMIO(0xe7000) 3034 #define PCH_GTC_ENABLE (1 << 31) 3035 3036 /* TV port control */ 3037 #define TV_CTL _MMIO(0x68000) 3038 /* Enables the TV encoder */ 3039 # define TV_ENC_ENABLE (1 << 31) 3040 /* Sources the TV encoder input from pipe B instead of A. */ 3041 # define TV_ENC_PIPE_SEL_SHIFT 30 3042 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 3043 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 3044 /* Outputs composite video (DAC A only) */ 3045 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3046 /* Outputs SVideo video (DAC B/C) */ 3047 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3048 /* Outputs Component video (DAC A/B/C) */ 3049 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3050 /* Outputs Composite and SVideo (DAC A/B/C) */ 3051 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3052 # define TV_TRILEVEL_SYNC (1 << 21) 3053 /* Enables slow sync generation (945GM only) */ 3054 # define TV_SLOW_SYNC (1 << 20) 3055 /* Selects 4x oversampling for 480i and 576p */ 3056 # define TV_OVERSAMPLE_4X (0 << 18) 3057 /* Selects 2x oversampling for 720p and 1080i */ 3058 # define TV_OVERSAMPLE_2X (1 << 18) 3059 /* Selects no oversampling for 1080p */ 3060 # define TV_OVERSAMPLE_NONE (2 << 18) 3061 /* Selects 8x oversampling */ 3062 # define TV_OVERSAMPLE_8X (3 << 18) 3063 # define TV_OVERSAMPLE_MASK (3 << 18) 3064 /* Selects progressive mode rather than interlaced */ 3065 # define TV_PROGRESSIVE (1 << 17) 3066 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3067 # define TV_PAL_BURST (1 << 16) 3068 /* Field for setting delay of Y compared to C */ 3069 # define TV_YC_SKEW_MASK (7 << 12) 3070 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3071 # define TV_ENC_SDP_FIX (1 << 11) 3072 /* 3073 * Enables a fix for the 915GM only. 3074 * 3075 * Not sure what it does. 3076 */ 3077 # define TV_ENC_C0_FIX (1 << 10) 3078 /* Bits that must be preserved by software */ 3079 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3080 # define TV_FUSE_STATE_MASK (3 << 4) 3081 /* Read-only state that reports all features enabled */ 3082 # define TV_FUSE_STATE_ENABLED (0 << 4) 3083 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3084 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3085 /* Read-only state that reports that TV-out is disabled in hardware. */ 3086 # define TV_FUSE_STATE_DISABLED (2 << 4) 3087 /* Normal operation */ 3088 # define TV_TEST_MODE_NORMAL (0 << 0) 3089 /* Encoder test pattern 1 - combo pattern */ 3090 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3091 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3092 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3093 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3094 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3095 /* Encoder test pattern 4 - random noise */ 3096 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3097 /* Encoder test pattern 5 - linear color ramps */ 3098 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3099 /* 3100 * This test mode forces the DACs to 50% of full output. 3101 * 3102 * This is used for load detection in combination with TVDAC_SENSE_MASK 3103 */ 3104 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3105 # define TV_TEST_MODE_MASK (7 << 0) 3106 3107 #define TV_DAC _MMIO(0x68004) 3108 # define TV_DAC_SAVE 0x00ffff00 3109 /* 3110 * Reports that DAC state change logic has reported change (RO). 3111 * 3112 * This gets cleared when TV_DAC_STATE_EN is cleared 3113 */ 3114 # define TVDAC_STATE_CHG (1 << 31) 3115 # define TVDAC_SENSE_MASK (7 << 28) 3116 /* Reports that DAC A voltage is above the detect threshold */ 3117 # define TVDAC_A_SENSE (1 << 30) 3118 /* Reports that DAC B voltage is above the detect threshold */ 3119 # define TVDAC_B_SENSE (1 << 29) 3120 /* Reports that DAC C voltage is above the detect threshold */ 3121 # define TVDAC_C_SENSE (1 << 28) 3122 /* 3123 * Enables DAC state detection logic, for load-based TV detection. 3124 * 3125 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3126 * to off, for load detection to work. 3127 */ 3128 # define TVDAC_STATE_CHG_EN (1 << 27) 3129 /* Sets the DAC A sense value to high */ 3130 # define TVDAC_A_SENSE_CTL (1 << 26) 3131 /* Sets the DAC B sense value to high */ 3132 # define TVDAC_B_SENSE_CTL (1 << 25) 3133 /* Sets the DAC C sense value to high */ 3134 # define TVDAC_C_SENSE_CTL (1 << 24) 3135 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3136 # define DAC_CTL_OVERRIDE (1 << 7) 3137 /* Sets the slew rate. Must be preserved in software */ 3138 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3139 # define DAC_A_1_3_V (0 << 4) 3140 # define DAC_A_1_1_V (1 << 4) 3141 # define DAC_A_0_7_V (2 << 4) 3142 # define DAC_A_MASK (3 << 4) 3143 # define DAC_B_1_3_V (0 << 2) 3144 # define DAC_B_1_1_V (1 << 2) 3145 # define DAC_B_0_7_V (2 << 2) 3146 # define DAC_B_MASK (3 << 2) 3147 # define DAC_C_1_3_V (0 << 0) 3148 # define DAC_C_1_1_V (1 << 0) 3149 # define DAC_C_0_7_V (2 << 0) 3150 # define DAC_C_MASK (3 << 0) 3151 3152 /* 3153 * CSC coefficients are stored in a floating point format with 9 bits of 3154 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3155 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3156 * -1 (0x3) being the only legal negative value. 3157 */ 3158 #define TV_CSC_Y _MMIO(0x68010) 3159 # define TV_RY_MASK 0x07ff0000 3160 # define TV_RY_SHIFT 16 3161 # define TV_GY_MASK 0x00000fff 3162 # define TV_GY_SHIFT 0 3163 3164 #define TV_CSC_Y2 _MMIO(0x68014) 3165 # define TV_BY_MASK 0x07ff0000 3166 # define TV_BY_SHIFT 16 3167 /* 3168 * Y attenuation for component video. 3169 * 3170 * Stored in 1.9 fixed point. 3171 */ 3172 # define TV_AY_MASK 0x000003ff 3173 # define TV_AY_SHIFT 0 3174 3175 #define TV_CSC_U _MMIO(0x68018) 3176 # define TV_RU_MASK 0x07ff0000 3177 # define TV_RU_SHIFT 16 3178 # define TV_GU_MASK 0x000007ff 3179 # define TV_GU_SHIFT 0 3180 3181 #define TV_CSC_U2 _MMIO(0x6801c) 3182 # define TV_BU_MASK 0x07ff0000 3183 # define TV_BU_SHIFT 16 3184 /* 3185 * U attenuation for component video. 3186 * 3187 * Stored in 1.9 fixed point. 3188 */ 3189 # define TV_AU_MASK 0x000003ff 3190 # define TV_AU_SHIFT 0 3191 3192 #define TV_CSC_V _MMIO(0x68020) 3193 # define TV_RV_MASK 0x0fff0000 3194 # define TV_RV_SHIFT 16 3195 # define TV_GV_MASK 0x000007ff 3196 # define TV_GV_SHIFT 0 3197 3198 #define TV_CSC_V2 _MMIO(0x68024) 3199 # define TV_BV_MASK 0x07ff0000 3200 # define TV_BV_SHIFT 16 3201 /* 3202 * V attenuation for component video. 3203 * 3204 * Stored in 1.9 fixed point. 3205 */ 3206 # define TV_AV_MASK 0x000007ff 3207 # define TV_AV_SHIFT 0 3208 3209 #define TV_CLR_KNOBS _MMIO(0x68028) 3210 /* 2s-complement brightness adjustment */ 3211 # define TV_BRIGHTNESS_MASK 0xff000000 3212 # define TV_BRIGHTNESS_SHIFT 24 3213 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3214 # define TV_CONTRAST_MASK 0x00ff0000 3215 # define TV_CONTRAST_SHIFT 16 3216 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3217 # define TV_SATURATION_MASK 0x0000ff00 3218 # define TV_SATURATION_SHIFT 8 3219 /* Hue adjustment, as an integer phase angle in degrees */ 3220 # define TV_HUE_MASK 0x000000ff 3221 # define TV_HUE_SHIFT 0 3222 3223 #define TV_CLR_LEVEL _MMIO(0x6802c) 3224 /* Controls the DAC level for black */ 3225 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3226 # define TV_BLACK_LEVEL_SHIFT 16 3227 /* Controls the DAC level for blanking */ 3228 # define TV_BLANK_LEVEL_MASK 0x000001ff 3229 # define TV_BLANK_LEVEL_SHIFT 0 3230 3231 #define TV_H_CTL_1 _MMIO(0x68030) 3232 /* Number of pixels in the hsync. */ 3233 # define TV_HSYNC_END_MASK 0x1fff0000 3234 # define TV_HSYNC_END_SHIFT 16 3235 /* Total number of pixels minus one in the line (display and blanking). */ 3236 # define TV_HTOTAL_MASK 0x00001fff 3237 # define TV_HTOTAL_SHIFT 0 3238 3239 #define TV_H_CTL_2 _MMIO(0x68034) 3240 /* Enables the colorburst (needed for non-component color) */ 3241 # define TV_BURST_ENA (1 << 31) 3242 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3243 # define TV_HBURST_START_SHIFT 16 3244 # define TV_HBURST_START_MASK 0x1fff0000 3245 /* Length of the colorburst */ 3246 # define TV_HBURST_LEN_SHIFT 0 3247 # define TV_HBURST_LEN_MASK 0x0001fff 3248 3249 #define TV_H_CTL_3 _MMIO(0x68038) 3250 /* End of hblank, measured in pixels minus one from start of hsync */ 3251 # define TV_HBLANK_END_SHIFT 16 3252 # define TV_HBLANK_END_MASK 0x1fff0000 3253 /* Start of hblank, measured in pixels minus one from start of hsync */ 3254 # define TV_HBLANK_START_SHIFT 0 3255 # define TV_HBLANK_START_MASK 0x0001fff 3256 3257 #define TV_V_CTL_1 _MMIO(0x6803c) 3258 /* XXX */ 3259 # define TV_NBR_END_SHIFT 16 3260 # define TV_NBR_END_MASK 0x07ff0000 3261 /* XXX */ 3262 # define TV_VI_END_F1_SHIFT 8 3263 # define TV_VI_END_F1_MASK 0x00003f00 3264 /* XXX */ 3265 # define TV_VI_END_F2_SHIFT 0 3266 # define TV_VI_END_F2_MASK 0x0000003f 3267 3268 #define TV_V_CTL_2 _MMIO(0x68040) 3269 /* Length of vsync, in half lines */ 3270 # define TV_VSYNC_LEN_MASK 0x07ff0000 3271 # define TV_VSYNC_LEN_SHIFT 16 3272 /* Offset of the start of vsync in field 1, measured in one less than the 3273 * number of half lines. 3274 */ 3275 # define TV_VSYNC_START_F1_MASK 0x00007f00 3276 # define TV_VSYNC_START_F1_SHIFT 8 3277 /* 3278 * Offset of the start of vsync in field 2, measured in one less than the 3279 * number of half lines. 3280 */ 3281 # define TV_VSYNC_START_F2_MASK 0x0000007f 3282 # define TV_VSYNC_START_F2_SHIFT 0 3283 3284 #define TV_V_CTL_3 _MMIO(0x68044) 3285 /* Enables generation of the equalization signal */ 3286 # define TV_EQUAL_ENA (1 << 31) 3287 /* Length of vsync, in half lines */ 3288 # define TV_VEQ_LEN_MASK 0x007f0000 3289 # define TV_VEQ_LEN_SHIFT 16 3290 /* Offset of the start of equalization in field 1, measured in one less than 3291 * the number of half lines. 3292 */ 3293 # define TV_VEQ_START_F1_MASK 0x0007f00 3294 # define TV_VEQ_START_F1_SHIFT 8 3295 /* 3296 * Offset of the start of equalization in field 2, measured in one less than 3297 * the number of half lines. 3298 */ 3299 # define TV_VEQ_START_F2_MASK 0x000007f 3300 # define TV_VEQ_START_F2_SHIFT 0 3301 3302 #define TV_V_CTL_4 _MMIO(0x68048) 3303 /* 3304 * Offset to start of vertical colorburst, measured in one less than the 3305 * number of lines from vertical start. 3306 */ 3307 # define TV_VBURST_START_F1_MASK 0x003f0000 3308 # define TV_VBURST_START_F1_SHIFT 16 3309 /* 3310 * Offset to the end of vertical colorburst, measured in one less than the 3311 * number of lines from the start of NBR. 3312 */ 3313 # define TV_VBURST_END_F1_MASK 0x000000ff 3314 # define TV_VBURST_END_F1_SHIFT 0 3315 3316 #define TV_V_CTL_5 _MMIO(0x6804c) 3317 /* 3318 * Offset to start of vertical colorburst, measured in one less than the 3319 * number of lines from vertical start. 3320 */ 3321 # define TV_VBURST_START_F2_MASK 0x003f0000 3322 # define TV_VBURST_START_F2_SHIFT 16 3323 /* 3324 * Offset to the end of vertical colorburst, measured in one less than the 3325 * number of lines from the start of NBR. 3326 */ 3327 # define TV_VBURST_END_F2_MASK 0x000000ff 3328 # define TV_VBURST_END_F2_SHIFT 0 3329 3330 #define TV_V_CTL_6 _MMIO(0x68050) 3331 /* 3332 * Offset to start of vertical colorburst, measured in one less than the 3333 * number of lines from vertical start. 3334 */ 3335 # define TV_VBURST_START_F3_MASK 0x003f0000 3336 # define TV_VBURST_START_F3_SHIFT 16 3337 /* 3338 * Offset to the end of vertical colorburst, measured in one less than the 3339 * number of lines from the start of NBR. 3340 */ 3341 # define TV_VBURST_END_F3_MASK 0x000000ff 3342 # define TV_VBURST_END_F3_SHIFT 0 3343 3344 #define TV_V_CTL_7 _MMIO(0x68054) 3345 /* 3346 * Offset to start of vertical colorburst, measured in one less than the 3347 * number of lines from vertical start. 3348 */ 3349 # define TV_VBURST_START_F4_MASK 0x003f0000 3350 # define TV_VBURST_START_F4_SHIFT 16 3351 /* 3352 * Offset to the end of vertical colorburst, measured in one less than the 3353 * number of lines from the start of NBR. 3354 */ 3355 # define TV_VBURST_END_F4_MASK 0x000000ff 3356 # define TV_VBURST_END_F4_SHIFT 0 3357 3358 #define TV_SC_CTL_1 _MMIO(0x68060) 3359 /* Turns on the first subcarrier phase generation DDA */ 3360 # define TV_SC_DDA1_EN (1 << 31) 3361 /* Turns on the first subcarrier phase generation DDA */ 3362 # define TV_SC_DDA2_EN (1 << 30) 3363 /* Turns on the first subcarrier phase generation DDA */ 3364 # define TV_SC_DDA3_EN (1 << 29) 3365 /* Sets the subcarrier DDA to reset frequency every other field */ 3366 # define TV_SC_RESET_EVERY_2 (0 << 24) 3367 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3368 # define TV_SC_RESET_EVERY_4 (1 << 24) 3369 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3370 # define TV_SC_RESET_EVERY_8 (2 << 24) 3371 /* Sets the subcarrier DDA to never reset the frequency */ 3372 # define TV_SC_RESET_NEVER (3 << 24) 3373 /* Sets the peak amplitude of the colorburst.*/ 3374 # define TV_BURST_LEVEL_MASK 0x00ff0000 3375 # define TV_BURST_LEVEL_SHIFT 16 3376 /* Sets the increment of the first subcarrier phase generation DDA */ 3377 # define TV_SCDDA1_INC_MASK 0x00000fff 3378 # define TV_SCDDA1_INC_SHIFT 0 3379 3380 #define TV_SC_CTL_2 _MMIO(0x68064) 3381 /* Sets the rollover for the second subcarrier phase generation DDA */ 3382 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3383 # define TV_SCDDA2_SIZE_SHIFT 16 3384 /* Sets the increent of the second subcarrier phase generation DDA */ 3385 # define TV_SCDDA2_INC_MASK 0x00007fff 3386 # define TV_SCDDA2_INC_SHIFT 0 3387 3388 #define TV_SC_CTL_3 _MMIO(0x68068) 3389 /* Sets the rollover for the third subcarrier phase generation DDA */ 3390 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3391 # define TV_SCDDA3_SIZE_SHIFT 16 3392 /* Sets the increent of the third subcarrier phase generation DDA */ 3393 # define TV_SCDDA3_INC_MASK 0x00007fff 3394 # define TV_SCDDA3_INC_SHIFT 0 3395 3396 #define TV_WIN_POS _MMIO(0x68070) 3397 /* X coordinate of the display from the start of horizontal active */ 3398 # define TV_XPOS_MASK 0x1fff0000 3399 # define TV_XPOS_SHIFT 16 3400 /* Y coordinate of the display from the start of vertical active (NBR) */ 3401 # define TV_YPOS_MASK 0x00000fff 3402 # define TV_YPOS_SHIFT 0 3403 3404 #define TV_WIN_SIZE _MMIO(0x68074) 3405 /* Horizontal size of the display window, measured in pixels*/ 3406 # define TV_XSIZE_MASK 0x1fff0000 3407 # define TV_XSIZE_SHIFT 16 3408 /* 3409 * Vertical size of the display window, measured in pixels. 3410 * 3411 * Must be even for interlaced modes. 3412 */ 3413 # define TV_YSIZE_MASK 0x00000fff 3414 # define TV_YSIZE_SHIFT 0 3415 3416 #define TV_FILTER_CTL_1 _MMIO(0x68080) 3417 /* 3418 * Enables automatic scaling calculation. 3419 * 3420 * If set, the rest of the registers are ignored, and the calculated values can 3421 * be read back from the register. 3422 */ 3423 # define TV_AUTO_SCALE (1 << 31) 3424 /* 3425 * Disables the vertical filter. 3426 * 3427 * This is required on modes more than 1024 pixels wide */ 3428 # define TV_V_FILTER_BYPASS (1 << 29) 3429 /* Enables adaptive vertical filtering */ 3430 # define TV_VADAPT (1 << 28) 3431 # define TV_VADAPT_MODE_MASK (3 << 26) 3432 /* Selects the least adaptive vertical filtering mode */ 3433 # define TV_VADAPT_MODE_LEAST (0 << 26) 3434 /* Selects the moderately adaptive vertical filtering mode */ 3435 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3436 /* Selects the most adaptive vertical filtering mode */ 3437 # define TV_VADAPT_MODE_MOST (3 << 26) 3438 /* 3439 * Sets the horizontal scaling factor. 3440 * 3441 * This should be the fractional part of the horizontal scaling factor divided 3442 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3443 * 3444 * (src width - 1) / ((oversample * dest width) - 1) 3445 */ 3446 # define TV_HSCALE_FRAC_MASK 0x00003fff 3447 # define TV_HSCALE_FRAC_SHIFT 0 3448 3449 #define TV_FILTER_CTL_2 _MMIO(0x68084) 3450 /* 3451 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3452 * 3453 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3454 */ 3455 # define TV_VSCALE_INT_MASK 0x00038000 3456 # define TV_VSCALE_INT_SHIFT 15 3457 /* 3458 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3459 * 3460 * \sa TV_VSCALE_INT_MASK 3461 */ 3462 # define TV_VSCALE_FRAC_MASK 0x00007fff 3463 # define TV_VSCALE_FRAC_SHIFT 0 3464 3465 #define TV_FILTER_CTL_3 _MMIO(0x68088) 3466 /* 3467 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3468 * 3469 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3470 * 3471 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3472 */ 3473 # define TV_VSCALE_IP_INT_MASK 0x00038000 3474 # define TV_VSCALE_IP_INT_SHIFT 15 3475 /* 3476 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3477 * 3478 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3479 * 3480 * \sa TV_VSCALE_IP_INT_MASK 3481 */ 3482 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3483 # define TV_VSCALE_IP_FRAC_SHIFT 0 3484 3485 #define TV_CC_CONTROL _MMIO(0x68090) 3486 # define TV_CC_ENABLE (1 << 31) 3487 /* 3488 * Specifies which field to send the CC data in. 3489 * 3490 * CC data is usually sent in field 0. 3491 */ 3492 # define TV_CC_FID_MASK (1 << 27) 3493 # define TV_CC_FID_SHIFT 27 3494 /* Sets the horizontal position of the CC data. Usually 135. */ 3495 # define TV_CC_HOFF_MASK 0x03ff0000 3496 # define TV_CC_HOFF_SHIFT 16 3497 /* Sets the vertical position of the CC data. Usually 21 */ 3498 # define TV_CC_LINE_MASK 0x0000003f 3499 # define TV_CC_LINE_SHIFT 0 3500 3501 #define TV_CC_DATA _MMIO(0x68094) 3502 # define TV_CC_RDY (1 << 31) 3503 /* Second word of CC data to be transmitted. */ 3504 # define TV_CC_DATA_2_MASK 0x007f0000 3505 # define TV_CC_DATA_2_SHIFT 16 3506 /* First word of CC data to be transmitted. */ 3507 # define TV_CC_DATA_1_MASK 0x0000007f 3508 # define TV_CC_DATA_1_SHIFT 0 3509 3510 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 3511 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 3512 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 3513 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 3514 3515 /* Display Port */ 3516 #define DP_A _MMIO(0x64000) /* eDP */ 3517 #define DP_B _MMIO(0x64100) 3518 #define DP_C _MMIO(0x64200) 3519 #define DP_D _MMIO(0x64300) 3520 3521 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 3522 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 3523 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 3524 3525 #define DP_PORT_EN (1 << 31) 3526 #define DP_PIPE_SEL_SHIFT 30 3527 #define DP_PIPE_SEL_MASK (1 << 30) 3528 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 3529 #define DP_PIPE_SEL_SHIFT_IVB 29 3530 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 3531 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 3532 #define DP_PIPE_SEL_SHIFT_CHV 16 3533 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 3534 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 3535 3536 /* Link training mode - select a suitable mode for each stage */ 3537 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3538 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3539 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3540 #define DP_LINK_TRAIN_OFF (3 << 28) 3541 #define DP_LINK_TRAIN_MASK (3 << 28) 3542 #define DP_LINK_TRAIN_SHIFT 28 3543 3544 /* CPT Link training mode */ 3545 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3546 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3547 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3548 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3549 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3550 #define DP_LINK_TRAIN_SHIFT_CPT 8 3551 3552 /* Signal voltages. These are mostly controlled by the other end */ 3553 #define DP_VOLTAGE_0_4 (0 << 25) 3554 #define DP_VOLTAGE_0_6 (1 << 25) 3555 #define DP_VOLTAGE_0_8 (2 << 25) 3556 #define DP_VOLTAGE_1_2 (3 << 25) 3557 #define DP_VOLTAGE_MASK (7 << 25) 3558 #define DP_VOLTAGE_SHIFT 25 3559 3560 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3561 * they want 3562 */ 3563 #define DP_PRE_EMPHASIS_0 (0 << 22) 3564 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3565 #define DP_PRE_EMPHASIS_6 (2 << 22) 3566 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3567 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3568 #define DP_PRE_EMPHASIS_SHIFT 22 3569 3570 /* How many wires to use. I guess 3 was too hard */ 3571 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3572 #define DP_PORT_WIDTH_MASK (7 << 19) 3573 #define DP_PORT_WIDTH_SHIFT 19 3574 3575 /* Mystic DPCD version 1.1 special mode */ 3576 #define DP_ENHANCED_FRAMING (1 << 18) 3577 3578 /* eDP */ 3579 #define DP_PLL_FREQ_270MHZ (0 << 16) 3580 #define DP_PLL_FREQ_162MHZ (1 << 16) 3581 #define DP_PLL_FREQ_MASK (3 << 16) 3582 3583 /* locked once port is enabled */ 3584 #define DP_PORT_REVERSAL (1 << 15) 3585 3586 /* eDP */ 3587 #define DP_PLL_ENABLE (1 << 14) 3588 3589 /* sends the clock on lane 15 of the PEG for debug */ 3590 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3591 3592 #define DP_SCRAMBLING_DISABLE (1 << 12) 3593 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3594 3595 /* limit RGB values to avoid confusing TVs */ 3596 #define DP_COLOR_RANGE_16_235 (1 << 8) 3597 3598 /* Turn on the audio link */ 3599 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3600 3601 /* vs and hs sync polarity */ 3602 #define DP_SYNC_VS_HIGH (1 << 4) 3603 #define DP_SYNC_HS_HIGH (1 << 3) 3604 3605 /* A fantasy */ 3606 #define DP_DETECTED (1 << 2) 3607 3608 /* The aux channel provides a way to talk to the 3609 * signal sink for DDC etc. Max packet size supported 3610 * is 20 bytes in each direction, hence the 5 fixed 3611 * data registers 3612 */ 3613 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 3614 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 3615 3616 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 3617 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 3618 3619 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 3620 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 3621 3622 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3623 #define DP_AUX_CH_CTL_DONE (1 << 30) 3624 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3625 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3626 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3627 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3628 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3629 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 3630 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3631 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3632 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3633 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3634 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3635 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3636 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3637 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3638 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3639 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3640 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3641 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3642 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3643 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 3644 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 3645 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 3646 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 3647 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 3648 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 3649 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3650 3651 /* 3652 * Computing GMCH M and N values for the Display Port link 3653 * 3654 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3655 * 3656 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3657 * 3658 * The GMCH value is used internally 3659 * 3660 * bytes_per_pixel is the number of bytes coming out of the plane, 3661 * which is after the LUTs, so we want the bytes for our color format. 3662 * For our current usage, this is always 3, one byte for R, G and B. 3663 */ 3664 #define _PIPEA_DATA_M_G4X 0x70050 3665 #define _PIPEB_DATA_M_G4X 0x71050 3666 3667 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3668 #define TU_SIZE_MASK REG_GENMASK(30, 25) 3669 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 3670 3671 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 3672 #define DATA_LINK_N_MAX (0x800000) 3673 3674 #define _PIPEA_DATA_N_G4X 0x70054 3675 #define _PIPEB_DATA_N_G4X 0x71054 3676 3677 /* 3678 * Computing Link M and N values for the Display Port link 3679 * 3680 * Link M / N = pixel_clock / ls_clk 3681 * 3682 * (the DP spec calls pixel_clock the 'strm_clk') 3683 * 3684 * The Link value is transmitted in the Main Stream 3685 * Attributes and VB-ID. 3686 */ 3687 3688 #define _PIPEA_LINK_M_G4X 0x70060 3689 #define _PIPEB_LINK_M_G4X 0x71060 3690 #define _PIPEA_LINK_N_G4X 0x70064 3691 #define _PIPEB_LINK_N_G4X 0x71064 3692 3693 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3694 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3695 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3696 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3697 3698 /* Display & cursor control */ 3699 3700 /* Pipe A */ 3701 #define _PIPEADSL 0x70000 3702 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 3703 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 3704 #define _PIPEACONF 0x70008 3705 #define PIPECONF_ENABLE REG_BIT(31) 3706 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 3707 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 3708 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 3709 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 3710 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 3711 #define PIPECONF_PIPE_LOCKED REG_BIT(25) 3712 #define PIPECONF_FORCE_BORDER REG_BIT(25) 3713 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 3714 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 3715 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0) 3716 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1) 3717 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 3718 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 3719 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 3720 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 3721 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0) 3722 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ 3723 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ 3724 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6) 3725 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ 3726 /* 3727 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 3728 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 3729 */ 3730 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 3731 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 3732 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0) 3733 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1) 3734 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3) 3735 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 3736 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 3737 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 3738 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 3739 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x)) 3740 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16) 3741 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 3742 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13) 3743 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 3744 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 3745 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 3746 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 3747 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 3748 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 3749 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0) 3750 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1) 3751 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2) 3752 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3) 3753 #define PIPECONF_DITHER_EN REG_BIT(4) 3754 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3755 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0) 3756 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1) 3757 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2) 3758 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3) 3759 #define _PIPEASTAT 0x70024 3760 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 3761 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 3762 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 3763 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 3764 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 3765 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 3766 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 3767 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 3768 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 3769 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 3770 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 3771 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 3772 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 3773 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 3774 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 3775 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 3776 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 3777 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 3778 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 3779 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 3780 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 3781 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 3782 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 3783 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 3784 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 3785 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 3786 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 3787 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 3788 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 3789 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 3790 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 3791 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 3792 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 3793 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 3794 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 3795 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 3796 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 3797 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 3798 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 3799 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 3800 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 3801 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 3802 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 3803 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 3804 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 3805 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 3806 3807 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3808 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3809 3810 #define PIPE_A_OFFSET 0x70000 3811 #define PIPE_B_OFFSET 0x71000 3812 #define PIPE_C_OFFSET 0x72000 3813 #define PIPE_D_OFFSET 0x73000 3814 #define CHV_PIPE_C_OFFSET 0x74000 3815 /* 3816 * There's actually no pipe EDP. Some pipe registers have 3817 * simply shifted from the pipe to the transcoder, while 3818 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3819 * to access such registers in transcoder EDP. 3820 */ 3821 #define PIPE_EDP_OFFSET 0x7f000 3822 3823 /* ICL DSI 0 and 1 */ 3824 #define PIPE_DSI0_OFFSET 0x7b000 3825 #define PIPE_DSI1_OFFSET 0x7b800 3826 3827 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 3828 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 3829 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 3830 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 3831 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 3832 3833 #define _PIPEAGCMAX 0x70010 3834 #define _PIPEBGCMAX 0x71010 3835 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 3836 3837 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 3838 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 3839 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 3840 3841 #define _PIPE_MISC_A 0x70030 3842 #define _PIPE_MISC_B 0x71030 3843 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 3844 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 3845 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 3846 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 3847 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 3848 /* 3849 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 3850 * valid values of: 6, 8, 10 BPC. 3851 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 3852 * 6, 8, 10, 12 BPC. 3853 */ 3854 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5) 3855 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0) 3856 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1) 3857 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2) 3858 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */ 3859 #define PIPEMISC_DITHER_ENABLE REG_BIT(4) 3860 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3861 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0) 3862 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1) 3863 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2) 3864 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3) 3865 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 3866 3867 #define _PIPE_MISC2_A 0x7002C 3868 #define _PIPE_MISC2_B 0x7102C 3869 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 3870 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 3871 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 3872 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) 3873 3874 /* Skylake+ pipe bottom (background) color */ 3875 #define _SKL_BOTTOM_COLOR_A 0x70034 3876 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 3877 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 3878 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 3879 3880 #define _ICL_PIPE_A_STATUS 0x70058 3881 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 3882 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 3883 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 3884 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 3885 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 3886 3887 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 3888 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 3889 #define PIPEB_HLINE_INT_EN REG_BIT(28) 3890 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 3891 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 3892 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 3893 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 3894 #define PIPE_PSR_INT_EN REG_BIT(22) 3895 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 3896 #define PIPEA_HLINE_INT_EN REG_BIT(20) 3897 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 3898 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 3899 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 3900 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 3901 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 3902 #define PIPEC_HLINE_INT_EN REG_BIT(12) 3903 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 3904 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 3905 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 3906 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 3907 3908 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3909 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 3910 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 3911 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 3912 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 3913 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 3914 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 3915 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 3916 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 3917 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 3918 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 3919 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 3920 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 3921 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 3922 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 3923 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 3924 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 3925 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 3926 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 3927 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 3928 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 3929 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 3930 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 3931 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 3932 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 3933 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 3934 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 3935 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 3936 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 3937 3938 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 3939 #define DSPARB_CSTART_MASK (0x7f << 7) 3940 #define DSPARB_CSTART_SHIFT 7 3941 #define DSPARB_BSTART_MASK (0x7f) 3942 #define DSPARB_BSTART_SHIFT 0 3943 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3944 #define DSPARB_AEND_SHIFT 0 3945 #define DSPARB_SPRITEA_SHIFT_VLV 0 3946 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 3947 #define DSPARB_SPRITEB_SHIFT_VLV 8 3948 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 3949 #define DSPARB_SPRITEC_SHIFT_VLV 16 3950 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 3951 #define DSPARB_SPRITED_SHIFT_VLV 24 3952 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 3953 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 3954 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 3955 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 3956 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 3957 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 3958 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 3959 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 3960 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 3961 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 3962 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 3963 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 3964 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 3965 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 3966 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 3967 #define DSPARB_SPRITEE_SHIFT_VLV 0 3968 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 3969 #define DSPARB_SPRITEF_SHIFT_VLV 8 3970 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 3971 3972 /* pnv/gen4/g4x/vlv/chv */ 3973 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 3974 #define DSPFW_SR_SHIFT 23 3975 #define DSPFW_SR_MASK (0x1ff << 23) 3976 #define DSPFW_CURSORB_SHIFT 16 3977 #define DSPFW_CURSORB_MASK (0x3f << 16) 3978 #define DSPFW_PLANEB_SHIFT 8 3979 #define DSPFW_PLANEB_MASK (0x7f << 8) 3980 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 3981 #define DSPFW_PLANEA_SHIFT 0 3982 #define DSPFW_PLANEA_MASK (0x7f << 0) 3983 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3984 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 3985 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 3986 #define DSPFW_FBC_SR_SHIFT 28 3987 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 3988 #define DSPFW_FBC_HPLL_SR_SHIFT 24 3989 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 3990 #define DSPFW_SPRITEB_SHIFT (16) 3991 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 3992 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 3993 #define DSPFW_CURSORA_SHIFT 8 3994 #define DSPFW_CURSORA_MASK (0x3f << 8) 3995 #define DSPFW_PLANEC_OLD_SHIFT 0 3996 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 3997 #define DSPFW_SPRITEA_SHIFT 0 3998 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 3999 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 4000 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 4001 #define DSPFW_HPLL_SR_EN (1 << 31) 4002 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 4003 #define DSPFW_CURSOR_SR_SHIFT 24 4004 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 4005 #define DSPFW_HPLL_CURSOR_SHIFT 16 4006 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 4007 #define DSPFW_HPLL_SR_SHIFT 0 4008 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 4009 4010 /* vlv/chv */ 4011 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 4012 #define DSPFW_SPRITEB_WM1_SHIFT 16 4013 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 4014 #define DSPFW_CURSORA_WM1_SHIFT 8 4015 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 4016 #define DSPFW_SPRITEA_WM1_SHIFT 0 4017 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 4018 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 4019 #define DSPFW_PLANEB_WM1_SHIFT 24 4020 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 4021 #define DSPFW_PLANEA_WM1_SHIFT 16 4022 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 4023 #define DSPFW_CURSORB_WM1_SHIFT 8 4024 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 4025 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4026 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 4027 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 4028 #define DSPFW_SR_WM1_SHIFT 0 4029 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 4030 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 4031 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4032 #define DSPFW_SPRITED_WM1_SHIFT 24 4033 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 4034 #define DSPFW_SPRITED_SHIFT 16 4035 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 4036 #define DSPFW_SPRITEC_WM1_SHIFT 8 4037 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 4038 #define DSPFW_SPRITEC_SHIFT 0 4039 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 4040 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 4041 #define DSPFW_SPRITEF_WM1_SHIFT 24 4042 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 4043 #define DSPFW_SPRITEF_SHIFT 16 4044 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 4045 #define DSPFW_SPRITEE_WM1_SHIFT 8 4046 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 4047 #define DSPFW_SPRITEE_SHIFT 0 4048 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 4049 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4050 #define DSPFW_PLANEC_WM1_SHIFT 24 4051 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 4052 #define DSPFW_PLANEC_SHIFT 16 4053 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 4054 #define DSPFW_CURSORC_WM1_SHIFT 8 4055 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 4056 #define DSPFW_CURSORC_SHIFT 0 4057 #define DSPFW_CURSORC_MASK (0x3f << 0) 4058 4059 /* vlv/chv high order bits */ 4060 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 4061 #define DSPFW_SR_HI_SHIFT 24 4062 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 4063 #define DSPFW_SPRITEF_HI_SHIFT 23 4064 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 4065 #define DSPFW_SPRITEE_HI_SHIFT 22 4066 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 4067 #define DSPFW_PLANEC_HI_SHIFT 21 4068 #define DSPFW_PLANEC_HI_MASK (1 << 21) 4069 #define DSPFW_SPRITED_HI_SHIFT 20 4070 #define DSPFW_SPRITED_HI_MASK (1 << 20) 4071 #define DSPFW_SPRITEC_HI_SHIFT 16 4072 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 4073 #define DSPFW_PLANEB_HI_SHIFT 12 4074 #define DSPFW_PLANEB_HI_MASK (1 << 12) 4075 #define DSPFW_SPRITEB_HI_SHIFT 8 4076 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 4077 #define DSPFW_SPRITEA_HI_SHIFT 4 4078 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 4079 #define DSPFW_PLANEA_HI_SHIFT 0 4080 #define DSPFW_PLANEA_HI_MASK (1 << 0) 4081 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 4082 #define DSPFW_SR_WM1_HI_SHIFT 24 4083 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 4084 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4085 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 4086 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4087 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 4088 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4089 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 4090 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4091 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 4092 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4093 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 4094 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4095 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 4096 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4097 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 4098 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4099 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 4100 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4101 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 4102 4103 /* drain latency register values*/ 4104 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4105 #define DDL_CURSOR_SHIFT 24 4106 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 4107 #define DDL_PLANE_SHIFT 0 4108 #define DDL_PRECISION_HIGH (1 << 7) 4109 #define DDL_PRECISION_LOW (0 << 7) 4110 #define DRAIN_LATENCY_MASK 0x7f 4111 4112 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 4113 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 4114 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 4115 4116 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 4117 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 4118 4119 /* FIFO watermark sizes etc */ 4120 #define G4X_FIFO_LINE_SIZE 64 4121 #define I915_FIFO_LINE_SIZE 64 4122 #define I830_FIFO_LINE_SIZE 32 4123 4124 #define VALLEYVIEW_FIFO_SIZE 255 4125 #define G4X_FIFO_SIZE 127 4126 #define I965_FIFO_SIZE 512 4127 #define I945_FIFO_SIZE 127 4128 #define I915_FIFO_SIZE 95 4129 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4130 #define I830_FIFO_SIZE 95 4131 4132 #define VALLEYVIEW_MAX_WM 0xff 4133 #define G4X_MAX_WM 0x3f 4134 #define I915_MAX_WM 0x3f 4135 4136 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4137 #define PINEVIEW_FIFO_LINE_SIZE 64 4138 #define PINEVIEW_MAX_WM 0x1ff 4139 #define PINEVIEW_DFT_WM 0x3f 4140 #define PINEVIEW_DFT_HPLLOFF_WM 0 4141 #define PINEVIEW_GUARD_WM 10 4142 #define PINEVIEW_CURSOR_FIFO 64 4143 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4144 #define PINEVIEW_CURSOR_DFT_WM 0 4145 #define PINEVIEW_CURSOR_GUARD_WM 5 4146 4147 #define VALLEYVIEW_CURSOR_MAX_WM 64 4148 #define I965_CURSOR_FIFO 64 4149 #define I965_CURSOR_MAX_WM 32 4150 #define I965_CURSOR_DFT_WM 8 4151 4152 /* Watermark register definitions for SKL */ 4153 #define _CUR_WM_A_0 0x70140 4154 #define _CUR_WM_B_0 0x71140 4155 #define _CUR_WM_SAGV_A 0x70158 4156 #define _CUR_WM_SAGV_B 0x71158 4157 #define _CUR_WM_SAGV_TRANS_A 0x7015C 4158 #define _CUR_WM_SAGV_TRANS_B 0x7115C 4159 #define _CUR_WM_TRANS_A 0x70168 4160 #define _CUR_WM_TRANS_B 0x71168 4161 #define _PLANE_WM_1_A_0 0x70240 4162 #define _PLANE_WM_1_B_0 0x71240 4163 #define _PLANE_WM_2_A_0 0x70340 4164 #define _PLANE_WM_2_B_0 0x71340 4165 #define _PLANE_WM_SAGV_1_A 0x70258 4166 #define _PLANE_WM_SAGV_1_B 0x71258 4167 #define _PLANE_WM_SAGV_2_A 0x70358 4168 #define _PLANE_WM_SAGV_2_B 0x71358 4169 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 4170 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 4171 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 4172 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 4173 #define _PLANE_WM_TRANS_1_A 0x70268 4174 #define _PLANE_WM_TRANS_1_B 0x71268 4175 #define _PLANE_WM_TRANS_2_A 0x70368 4176 #define _PLANE_WM_TRANS_2_B 0x71368 4177 #define PLANE_WM_EN (1 << 31) 4178 #define PLANE_WM_IGNORE_LINES (1 << 30) 4179 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 4180 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 4181 4182 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4183 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4184 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 4185 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 4186 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 4187 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4188 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4189 #define _PLANE_WM_BASE(pipe, plane) \ 4190 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4191 #define PLANE_WM(pipe, plane, level) \ 4192 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4193 #define _PLANE_WM_SAGV_1(pipe) \ 4194 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 4195 #define _PLANE_WM_SAGV_2(pipe) \ 4196 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 4197 #define PLANE_WM_SAGV(pipe, plane) \ 4198 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 4199 #define _PLANE_WM_SAGV_TRANS_1(pipe) \ 4200 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 4201 #define _PLANE_WM_SAGV_TRANS_2(pipe) \ 4202 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 4203 #define PLANE_WM_SAGV_TRANS(pipe, plane) \ 4204 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 4205 #define _PLANE_WM_TRANS_1(pipe) \ 4206 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 4207 #define _PLANE_WM_TRANS_2(pipe) \ 4208 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 4209 #define PLANE_WM_TRANS(pipe, plane) \ 4210 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4211 4212 /* define the Watermark register on Ironlake */ 4213 #define _WM0_PIPEA_ILK 0x45100 4214 #define _WM0_PIPEB_ILK 0x45104 4215 #define _WM0_PIPEC_IVB 0x45200 4216 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 4217 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 4218 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 4219 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 4220 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 4221 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 4222 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 4223 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 4224 #define WM1_LP_ILK _MMIO(0x45108) 4225 #define WM2_LP_ILK _MMIO(0x4510c) 4226 #define WM3_LP_ILK _MMIO(0x45110) 4227 #define WM_LP_ENABLE REG_BIT(31) 4228 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 4229 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 4230 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 4231 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 4232 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 4233 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 4234 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 4235 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 4236 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 4237 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 4238 #define WM1S_LP_ILK _MMIO(0x45120) 4239 #define WM2S_LP_IVB _MMIO(0x45124) 4240 #define WM3S_LP_IVB _MMIO(0x45128) 4241 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 4242 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 4243 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 4244 4245 /* 4246 * The two pipe frame counter registers are not synchronized, so 4247 * reading a stable value is somewhat tricky. The following code 4248 * should work: 4249 * 4250 * do { 4251 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4252 * PIPE_FRAME_HIGH_SHIFT; 4253 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4254 * PIPE_FRAME_LOW_SHIFT); 4255 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4256 * PIPE_FRAME_HIGH_SHIFT); 4257 * } while (high1 != high2); 4258 * frame = (high1 << 8) | low1; 4259 */ 4260 #define _PIPEAFRAMEHIGH 0x70040 4261 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4262 #define PIPE_FRAME_HIGH_SHIFT 0 4263 #define _PIPEAFRAMEPIXEL 0x70044 4264 #define PIPE_FRAME_LOW_MASK 0xff000000 4265 #define PIPE_FRAME_LOW_SHIFT 24 4266 #define PIPE_PIXEL_MASK 0x00ffffff 4267 #define PIPE_PIXEL_SHIFT 0 4268 /* GM45+ just has to be different */ 4269 #define _PIPEA_FRMCOUNT_G4X 0x70040 4270 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4271 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4272 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4273 4274 /* Cursor A & B regs */ 4275 #define _CURACNTR 0x70080 4276 /* Old style CUR*CNTR flags (desktop 8xx) */ 4277 #define CURSOR_ENABLE REG_BIT(31) 4278 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 4279 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 4280 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 4281 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 4282 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 4283 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 4284 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 4285 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 4286 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 4287 /* New style CUR*CNTR flags */ 4288 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4289 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 4290 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 4291 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 4292 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 4293 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4294 #define MCURSOR_ROTATE_180 REG_BIT(15) 4295 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 4296 #define MCURSOR_MODE_MASK 0x27 4297 #define MCURSOR_MODE_DISABLE 0x00 4298 #define MCURSOR_MODE_128_32B_AX 0x02 4299 #define MCURSOR_MODE_256_32B_AX 0x03 4300 #define MCURSOR_MODE_64_32B_AX 0x07 4301 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 4302 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 4303 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 4304 #define _CURABASE 0x70084 4305 #define _CURAPOS 0x70088 4306 #define CURSOR_POS_Y_SIGN REG_BIT(31) 4307 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 4308 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 4309 #define CURSOR_POS_X_SIGN REG_BIT(15) 4310 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 4311 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 4312 #define _CURASIZE 0x700a0 /* 845/865 */ 4313 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 4314 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 4315 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 4316 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 4317 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 4318 #define CUR_FBC_EN REG_BIT(31) 4319 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 4320 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 4321 #define _CURASURFLIVE 0x700ac /* g4x+ */ 4322 #define _CURBCNTR 0x700c0 4323 #define _CURBBASE 0x700c4 4324 #define _CURBPOS 0x700c8 4325 4326 #define _CURBCNTR_IVB 0x71080 4327 #define _CURBBASE_IVB 0x71084 4328 #define _CURBPOS_IVB 0x71088 4329 4330 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) 4331 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) 4332 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) 4333 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) 4334 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) 4335 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) 4336 4337 #define CURSOR_A_OFFSET 0x70080 4338 #define CURSOR_B_OFFSET 0x700c0 4339 #define CHV_CURSOR_C_OFFSET 0x700e0 4340 #define IVB_CURSOR_B_OFFSET 0x71080 4341 #define IVB_CURSOR_C_OFFSET 0x72080 4342 #define TGL_CURSOR_D_OFFSET 0x73080 4343 4344 /* Display A control */ 4345 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 4346 #define _DSPACNTR 0x70180 4347 #define DISP_ENABLE REG_BIT(31) 4348 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 4349 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 4350 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 4351 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 4352 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 4353 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 4354 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 4355 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 4356 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 4357 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 4358 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 4359 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 4360 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 4361 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 4362 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 4363 #define DISP_STEREO_ENABLE REG_BIT(25) 4364 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4365 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 4366 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 4367 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 4368 #define DISP_LINE_DOUBLE REG_BIT(20) 4369 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 4370 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 4371 #define DISP_ROTATE_180 REG_BIT(15) 4372 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 4373 #define DISP_TILED REG_BIT(10) 4374 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 4375 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 4376 #define _DSPAADDR 0x70184 4377 #define _DSPASTRIDE 0x70188 4378 #define _DSPAPOS 0x7018C /* reserved */ 4379 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 4380 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4381 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4382 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4383 #define _DSPASIZE 0x70190 4384 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 4385 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4386 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4387 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 4388 #define _DSPASURF 0x7019C /* 965+ only */ 4389 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 4390 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4391 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4392 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 4393 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 4394 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 4395 #define _DSPAOFFSET 0x701A4 /* HSW */ 4396 #define _DSPASURFLIVE 0x701AC 4397 #define _DSPAGAMC 0x701E0 4398 4399 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 4400 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 4401 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 4402 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 4403 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 4404 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 4405 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 4406 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 4407 #define DSPLINOFF(plane) DSPADDR(plane) 4408 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 4409 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 4410 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 4411 4412 /* CHV pipe B blender and primary plane */ 4413 #define _CHV_BLEND_A 0x60a00 4414 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 4415 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 4416 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 4417 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 4418 #define _CHV_CANVAS_A 0x60a04 4419 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 4420 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 4421 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 4422 #define _PRIMPOS_A 0x60a08 4423 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 4424 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 4425 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 4426 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 4427 #define _PRIMSIZE_A 0x60a0c 4428 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 4429 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 4430 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 4431 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 4432 #define _PRIMCNSTALPHA_A 0x60a10 4433 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 4434 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4435 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 4436 4437 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 4438 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 4439 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 4440 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 4441 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 4442 4443 /* Display/Sprite base address macros */ 4444 #define DISP_BASEADDR_MASK (0xfffff000) 4445 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 4446 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 4447 4448 /* 4449 * VBIOS flags 4450 * gen2: 4451 * [00:06] alm,mgm 4452 * [10:16] all 4453 * [30:32] alm,mgm 4454 * gen3+: 4455 * [00:0f] all 4456 * [10:1f] all 4457 * [30:32] all 4458 */ 4459 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 4460 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 4461 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 4462 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 4463 4464 /* Pipe B */ 4465 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 4466 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 4467 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 4468 #define _PIPEBFRAMEHIGH 0x71040 4469 #define _PIPEBFRAMEPIXEL 0x71044 4470 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 4471 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 4472 4473 4474 /* Display B control */ 4475 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 4476 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 4477 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 4478 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 4479 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 4480 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 4481 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 4482 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 4483 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4484 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4485 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 4486 4487 /* ICL DSI 0 and 1 */ 4488 #define _PIPEDSI0CONF 0x7b008 4489 #define _PIPEDSI1CONF 0x7b808 4490 4491 /* Sprite A control */ 4492 #define _DVSACNTR 0x72180 4493 #define DVS_ENABLE REG_BIT(31) 4494 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 4495 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 4496 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 4497 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 4498 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 4499 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 4500 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 4501 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 4502 #define DVS_SOURCE_KEY REG_BIT(22) 4503 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 4504 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 4505 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 4506 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 4507 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 4508 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 4509 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 4510 #define DVS_ROTATE_180 REG_BIT(15) 4511 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 4512 #define DVS_TILED REG_BIT(10) 4513 #define DVS_DEST_KEY REG_BIT(2) 4514 #define _DVSALINOFF 0x72184 4515 #define _DVSASTRIDE 0x72188 4516 #define _DVSAPOS 0x7218c 4517 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 4518 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 4519 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 4520 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 4521 #define _DVSASIZE 0x72190 4522 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 4523 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 4524 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 4525 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 4526 #define _DVSAKEYVAL 0x72194 4527 #define _DVSAKEYMSK 0x72198 4528 #define _DVSASURF 0x7219c 4529 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 4530 #define _DVSAKEYMAXVAL 0x721a0 4531 #define _DVSATILEOFF 0x721a4 4532 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 4533 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 4534 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 4535 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 4536 #define _DVSASURFLIVE 0x721ac 4537 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 4538 #define _DVSASCALE 0x72204 4539 #define DVS_SCALE_ENABLE REG_BIT(31) 4540 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 4541 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 4542 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 4543 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 4544 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4545 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4546 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4547 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 4548 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4549 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 4550 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 4551 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 4552 4553 #define _DVSBCNTR 0x73180 4554 #define _DVSBLINOFF 0x73184 4555 #define _DVSBSTRIDE 0x73188 4556 #define _DVSBPOS 0x7318c 4557 #define _DVSBSIZE 0x73190 4558 #define _DVSBKEYVAL 0x73194 4559 #define _DVSBKEYMSK 0x73198 4560 #define _DVSBSURF 0x7319c 4561 #define _DVSBKEYMAXVAL 0x731a0 4562 #define _DVSBTILEOFF 0x731a4 4563 #define _DVSBSURFLIVE 0x731ac 4564 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 4565 #define _DVSBSCALE 0x73204 4566 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 4567 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 4568 4569 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4570 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4571 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4572 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 4573 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 4574 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4575 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4576 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4577 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4578 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4579 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4580 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4581 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 4582 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 4583 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 4584 4585 #define _SPRA_CTL 0x70280 4586 #define SPRITE_ENABLE REG_BIT(31) 4587 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 4588 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4589 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 4590 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 4591 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 4592 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 4593 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 4594 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 4595 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 4596 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 4597 #define SPRITE_SOURCE_KEY REG_BIT(22) 4598 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 4599 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 4600 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 4601 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 4602 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 4603 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 4604 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 4605 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 4606 #define SPRITE_ROTATE_180 REG_BIT(15) 4607 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 4608 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 4609 #define SPRITE_TILED REG_BIT(10) 4610 #define SPRITE_DEST_KEY REG_BIT(2) 4611 #define _SPRA_LINOFF 0x70284 4612 #define _SPRA_STRIDE 0x70288 4613 #define _SPRA_POS 0x7028c 4614 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 4615 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 4616 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 4617 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 4618 #define _SPRA_SIZE 0x70290 4619 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 4620 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 4621 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 4622 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 4623 #define _SPRA_KEYVAL 0x70294 4624 #define _SPRA_KEYMSK 0x70298 4625 #define _SPRA_SURF 0x7029c 4626 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 4627 #define _SPRA_KEYMAX 0x702a0 4628 #define _SPRA_TILEOFF 0x702a4 4629 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4630 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 4631 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 4632 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 4633 #define _SPRA_OFFSET 0x702a4 4634 #define _SPRA_SURFLIVE 0x702ac 4635 #define _SPRA_SCALE 0x70304 4636 #define SPRITE_SCALE_ENABLE REG_BIT(31) 4637 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 4638 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 4639 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 4640 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 4641 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4642 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4643 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4644 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 4645 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4646 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 4647 #define _SPRA_GAMC 0x70400 4648 #define _SPRA_GAMC16 0x70440 4649 #define _SPRA_GAMC17 0x7044c 4650 4651 #define _SPRB_CTL 0x71280 4652 #define _SPRB_LINOFF 0x71284 4653 #define _SPRB_STRIDE 0x71288 4654 #define _SPRB_POS 0x7128c 4655 #define _SPRB_SIZE 0x71290 4656 #define _SPRB_KEYVAL 0x71294 4657 #define _SPRB_KEYMSK 0x71298 4658 #define _SPRB_SURF 0x7129c 4659 #define _SPRB_KEYMAX 0x712a0 4660 #define _SPRB_TILEOFF 0x712a4 4661 #define _SPRB_OFFSET 0x712a4 4662 #define _SPRB_SURFLIVE 0x712ac 4663 #define _SPRB_SCALE 0x71304 4664 #define _SPRB_GAMC 0x71400 4665 #define _SPRB_GAMC16 0x71440 4666 #define _SPRB_GAMC17 0x7144c 4667 4668 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4669 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4670 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4671 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 4672 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4673 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4674 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4675 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4676 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4677 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4678 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4679 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4680 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 4681 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 4682 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 4683 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4684 4685 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4686 #define SP_ENABLE REG_BIT(31) 4687 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 4688 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 4689 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 4690 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 4691 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 4692 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 4693 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 4694 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 4695 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 4696 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 4697 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 4698 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 4699 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 4700 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 4701 #define SP_SOURCE_KEY REG_BIT(22) 4702 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 4703 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 4704 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 4705 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 4706 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 4707 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 4708 #define SP_ROTATE_180 REG_BIT(15) 4709 #define SP_TILED REG_BIT(10) 4710 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 4711 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4712 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4713 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4714 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 4715 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 4716 #define SP_POS_X_MASK REG_GENMASK(15, 0) 4717 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 4718 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4719 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 4720 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 4721 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 4722 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 4723 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4724 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4725 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4726 #define SP_ADDR_MASK REG_GENMASK(31, 12) 4727 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4728 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4729 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4730 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 4731 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 4732 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 4733 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4734 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 4735 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4736 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 4737 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 4738 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 4739 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 4740 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 4741 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 4742 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 4743 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 4744 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 4745 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 4746 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 4747 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 4748 4749 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4750 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4751 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4752 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4753 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4754 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4755 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4756 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4757 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4758 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4759 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4760 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 4761 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 4762 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 4763 4764 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4765 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 4766 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4767 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 4768 4769 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 4770 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 4771 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 4772 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 4773 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 4774 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 4775 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 4776 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 4777 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4778 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 4779 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 4780 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 4781 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 4782 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 4783 4784 /* 4785 * CHV pipe B sprite CSC 4786 * 4787 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4788 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4789 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4790 */ 4791 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 4792 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 4793 4794 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 4795 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 4796 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 4797 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 4798 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 4799 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 4800 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 4801 4802 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 4803 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 4804 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 4805 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 4806 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 4807 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 4808 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 4809 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 4810 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 4811 4812 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 4813 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 4814 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 4815 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 4816 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 4817 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 4818 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 4819 4820 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 4821 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 4822 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 4823 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 4824 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 4825 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 4826 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 4827 4828 /* Skylake plane registers */ 4829 4830 #define _PLANE_CTL_1_A 0x70180 4831 #define _PLANE_CTL_2_A 0x70280 4832 #define _PLANE_CTL_3_A 0x70380 4833 #define PLANE_CTL_ENABLE REG_BIT(31) 4834 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4835 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 4836 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 4837 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4838 /* 4839 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 4840 * expanded to include bit 23 as well. However, the shift-24 based values 4841 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 4842 */ 4843 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 4844 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 4845 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 4846 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 4847 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 4848 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 4849 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 4850 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 4851 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 4852 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 4853 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 4854 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 4855 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 4856 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 4857 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 4858 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 4859 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 4860 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 4861 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 4862 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 4863 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 4864 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 4865 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 4866 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 4867 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 4868 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 4869 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 4870 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 4871 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 4872 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 4873 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 4874 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 4875 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 4876 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 4877 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 4878 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 4879 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 4880 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 4881 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 4882 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4883 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4884 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 4885 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 4886 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 4887 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 4888 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 4889 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 4890 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 4891 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 4892 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 4893 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 4894 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 4895 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 4896 #define _PLANE_STRIDE_1_A 0x70188 4897 #define _PLANE_STRIDE_2_A 0x70288 4898 #define _PLANE_STRIDE_3_A 0x70388 4899 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 4900 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 4901 #define _PLANE_POS_1_A 0x7018c 4902 #define _PLANE_POS_2_A 0x7028c 4903 #define _PLANE_POS_3_A 0x7038c 4904 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 4905 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 4906 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 4907 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 4908 #define _PLANE_SIZE_1_A 0x70190 4909 #define _PLANE_SIZE_2_A 0x70290 4910 #define _PLANE_SIZE_3_A 0x70390 4911 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 4912 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 4913 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 4914 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 4915 #define _PLANE_SURF_1_A 0x7019c 4916 #define _PLANE_SURF_2_A 0x7029c 4917 #define _PLANE_SURF_3_A 0x7039c 4918 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 4919 #define PLANE_SURF_DECRYPT REG_BIT(2) 4920 #define _PLANE_OFFSET_1_A 0x701a4 4921 #define _PLANE_OFFSET_2_A 0x702a4 4922 #define _PLANE_OFFSET_3_A 0x703a4 4923 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4924 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 4925 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 4926 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 4927 #define _PLANE_KEYVAL_1_A 0x70194 4928 #define _PLANE_KEYVAL_2_A 0x70294 4929 #define _PLANE_KEYMSK_1_A 0x70198 4930 #define _PLANE_KEYMSK_2_A 0x70298 4931 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 4932 #define _PLANE_KEYMAX_1_A 0x701a0 4933 #define _PLANE_KEYMAX_2_A 0x702a0 4934 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 4935 #define _PLANE_CC_VAL_1_A 0x701b4 4936 #define _PLANE_CC_VAL_2_A 0x702b4 4937 #define _PLANE_AUX_DIST_1_A 0x701c0 4938 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 4939 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 4940 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 4941 #define _PLANE_AUX_DIST_2_A 0x702c0 4942 #define _PLANE_AUX_OFFSET_1_A 0x701c4 4943 #define _PLANE_AUX_OFFSET_2_A 0x702c4 4944 #define _PLANE_CUS_CTL_1_A 0x701c8 4945 #define _PLANE_CUS_CTL_2_A 0x702c8 4946 #define PLANE_CUS_ENABLE REG_BIT(31) 4947 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 4948 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4949 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4950 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4951 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4952 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 4953 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 4954 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 4955 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 4956 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 4957 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 4958 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 4959 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 4960 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 4961 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 4962 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 4963 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 4964 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 4965 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 4966 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4967 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 4968 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 4969 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 4970 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 4971 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 4972 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 4973 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 4974 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 4975 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 4976 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 4977 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 4978 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 4979 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 4980 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 4981 #define _PLANE_BUF_CFG_1_A 0x7027c 4982 #define _PLANE_BUF_CFG_2_A 0x7037c 4983 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 4984 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 4985 4986 #define _PLANE_CC_VAL_1_B 0x711b4 4987 #define _PLANE_CC_VAL_2_B 0x712b4 4988 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 4989 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 4990 #define PLANE_CC_VAL(pipe, plane, dw) \ 4991 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 4992 4993 /* Input CSC Register Definitions */ 4994 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 4995 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 4996 4997 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 4998 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 4999 5000 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 5001 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 5002 _PLANE_INPUT_CSC_RY_GY_1_B) 5003 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 5004 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 5005 _PLANE_INPUT_CSC_RY_GY_2_B) 5006 5007 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 5008 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 5009 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 5010 5011 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 5012 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 5013 5014 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 5015 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 5016 5017 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 5018 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 5019 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 5020 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 5021 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 5022 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 5023 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 5024 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 5025 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 5026 5027 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 5028 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 5029 5030 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 5031 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 5032 5033 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 5034 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 5035 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 5036 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 5037 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 5038 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 5039 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 5040 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 5041 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 5042 5043 #define _PLANE_CTL_1_B 0x71180 5044 #define _PLANE_CTL_2_B 0x71280 5045 #define _PLANE_CTL_3_B 0x71380 5046 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 5047 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 5048 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 5049 #define PLANE_CTL(pipe, plane) \ 5050 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 5051 5052 #define _PLANE_STRIDE_1_B 0x71188 5053 #define _PLANE_STRIDE_2_B 0x71288 5054 #define _PLANE_STRIDE_3_B 0x71388 5055 #define _PLANE_STRIDE_1(pipe) \ 5056 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 5057 #define _PLANE_STRIDE_2(pipe) \ 5058 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 5059 #define _PLANE_STRIDE_3(pipe) \ 5060 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 5061 #define PLANE_STRIDE(pipe, plane) \ 5062 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 5063 5064 #define _PLANE_POS_1_B 0x7118c 5065 #define _PLANE_POS_2_B 0x7128c 5066 #define _PLANE_POS_3_B 0x7138c 5067 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 5068 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 5069 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 5070 #define PLANE_POS(pipe, plane) \ 5071 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 5072 5073 #define _PLANE_SIZE_1_B 0x71190 5074 #define _PLANE_SIZE_2_B 0x71290 5075 #define _PLANE_SIZE_3_B 0x71390 5076 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 5077 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 5078 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 5079 #define PLANE_SIZE(pipe, plane) \ 5080 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 5081 5082 #define _PLANE_SURF_1_B 0x7119c 5083 #define _PLANE_SURF_2_B 0x7129c 5084 #define _PLANE_SURF_3_B 0x7139c 5085 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 5086 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 5087 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 5088 #define PLANE_SURF(pipe, plane) \ 5089 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 5090 5091 #define _PLANE_OFFSET_1_B 0x711a4 5092 #define _PLANE_OFFSET_2_B 0x712a4 5093 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 5094 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 5095 #define PLANE_OFFSET(pipe, plane) \ 5096 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 5097 5098 #define _PLANE_KEYVAL_1_B 0x71194 5099 #define _PLANE_KEYVAL_2_B 0x71294 5100 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 5101 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 5102 #define PLANE_KEYVAL(pipe, plane) \ 5103 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 5104 5105 #define _PLANE_KEYMSK_1_B 0x71198 5106 #define _PLANE_KEYMSK_2_B 0x71298 5107 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 5108 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 5109 #define PLANE_KEYMSK(pipe, plane) \ 5110 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5111 5112 #define _PLANE_KEYMAX_1_B 0x711a0 5113 #define _PLANE_KEYMAX_2_B 0x712a0 5114 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5115 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5116 #define PLANE_KEYMAX(pipe, plane) \ 5117 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5118 5119 #define _PLANE_BUF_CFG_1_B 0x7127c 5120 #define _PLANE_BUF_CFG_2_B 0x7137c 5121 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 5122 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 5123 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 5124 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 5125 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 5126 #define _PLANE_BUF_CFG_1(pipe) \ 5127 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5128 #define _PLANE_BUF_CFG_2(pipe) \ 5129 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5130 #define PLANE_BUF_CFG(pipe, plane) \ 5131 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5132 5133 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5134 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5135 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5136 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5137 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5138 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5139 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5140 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5141 5142 #define _PLANE_AUX_DIST_1_B 0x711c0 5143 #define _PLANE_AUX_DIST_2_B 0x712c0 5144 #define _PLANE_AUX_DIST_1(pipe) \ 5145 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 5146 #define _PLANE_AUX_DIST_2(pipe) \ 5147 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 5148 #define PLANE_AUX_DIST(pipe, plane) \ 5149 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 5150 5151 #define _PLANE_AUX_OFFSET_1_B 0x711c4 5152 #define _PLANE_AUX_OFFSET_2_B 0x712c4 5153 #define _PLANE_AUX_OFFSET_1(pipe) \ 5154 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 5155 #define _PLANE_AUX_OFFSET_2(pipe) \ 5156 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 5157 #define PLANE_AUX_OFFSET(pipe, plane) \ 5158 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 5159 5160 #define _PLANE_CUS_CTL_1_B 0x711c8 5161 #define _PLANE_CUS_CTL_2_B 0x712c8 5162 #define _PLANE_CUS_CTL_1(pipe) \ 5163 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 5164 #define _PLANE_CUS_CTL_2(pipe) \ 5165 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 5166 #define PLANE_CUS_CTL(pipe, plane) \ 5167 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 5168 5169 #define _PLANE_COLOR_CTL_1_B 0x711CC 5170 #define _PLANE_COLOR_CTL_2_B 0x712CC 5171 #define _PLANE_COLOR_CTL_3_B 0x713CC 5172 #define _PLANE_COLOR_CTL_1(pipe) \ 5173 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 5174 #define _PLANE_COLOR_CTL_2(pipe) \ 5175 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 5176 #define PLANE_COLOR_CTL(pipe, plane) \ 5177 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 5178 5179 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 5180 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 5181 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 5182 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 5183 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 5184 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 5185 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 5186 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 5187 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 5188 5189 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 5190 _SEL_FETCH_PLANE_BASE_1_A, \ 5191 _SEL_FETCH_PLANE_BASE_2_A, \ 5192 _SEL_FETCH_PLANE_BASE_3_A, \ 5193 _SEL_FETCH_PLANE_BASE_4_A, \ 5194 _SEL_FETCH_PLANE_BASE_5_A, \ 5195 _SEL_FETCH_PLANE_BASE_6_A, \ 5196 _SEL_FETCH_PLANE_BASE_7_A, \ 5197 _SEL_FETCH_PLANE_BASE_CUR_A) 5198 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 5199 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 5200 _SEL_FETCH_PLANE_BASE_1_A + \ 5201 _SEL_FETCH_PLANE_BASE_A(plane)) 5202 5203 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 5204 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5205 _SEL_FETCH_PLANE_CTL_1_A - \ 5206 _SEL_FETCH_PLANE_BASE_1_A) 5207 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 5208 5209 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 5210 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5211 _SEL_FETCH_PLANE_POS_1_A - \ 5212 _SEL_FETCH_PLANE_BASE_1_A) 5213 5214 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 5215 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5216 _SEL_FETCH_PLANE_SIZE_1_A - \ 5217 _SEL_FETCH_PLANE_BASE_1_A) 5218 5219 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 5220 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5221 _SEL_FETCH_PLANE_OFFSET_1_A - \ 5222 _SEL_FETCH_PLANE_BASE_1_A) 5223 5224 /* SKL new cursor registers */ 5225 #define _CUR_BUF_CFG_A 0x7017c 5226 #define _CUR_BUF_CFG_B 0x7117c 5227 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5228 5229 /* VBIOS regs */ 5230 #define VGACNTRL _MMIO(0x71400) 5231 # define VGA_DISP_DISABLE (1 << 31) 5232 # define VGA_2X_MODE (1 << 30) 5233 # define VGA_PIPE_B_SELECT (1 << 29) 5234 5235 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5236 5237 /* Ironlake */ 5238 5239 #define CPU_VGACNTRL _MMIO(0x41000) 5240 5241 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5242 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5243 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5244 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5245 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5246 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5247 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5248 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5249 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5250 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5251 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5252 5253 /* refresh rate hardware control */ 5254 #define RR_HW_CTL _MMIO(0x45300) 5255 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5256 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5257 5258 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5259 #define FDI_PLL_FB_CLOCK_MASK 0xff 5260 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5261 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5262 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5263 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5264 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5265 5266 #define PCH_3DCGDIS0 _MMIO(0x46020) 5267 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5268 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5269 5270 #define PCH_3DCGDIS1 _MMIO(0x46024) 5271 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5272 5273 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5274 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 5275 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5276 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5277 5278 5279 #define _PIPEA_DATA_M1 0x60030 5280 #define _PIPEA_DATA_N1 0x60034 5281 #define _PIPEA_DATA_M2 0x60038 5282 #define _PIPEA_DATA_N2 0x6003c 5283 #define _PIPEA_LINK_M1 0x60040 5284 #define _PIPEA_LINK_N1 0x60044 5285 #define _PIPEA_LINK_M2 0x60048 5286 #define _PIPEA_LINK_N2 0x6004c 5287 5288 /* PIPEB timing regs are same start from 0x61000 */ 5289 5290 #define _PIPEB_DATA_M1 0x61030 5291 #define _PIPEB_DATA_N1 0x61034 5292 #define _PIPEB_DATA_M2 0x61038 5293 #define _PIPEB_DATA_N2 0x6103c 5294 #define _PIPEB_LINK_M1 0x61040 5295 #define _PIPEB_LINK_N1 0x61044 5296 #define _PIPEB_LINK_M2 0x61048 5297 #define _PIPEB_LINK_N2 0x6104c 5298 5299 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5300 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5301 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5302 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5303 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5304 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5305 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5306 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5307 5308 /* CPU panel fitter */ 5309 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5310 #define _PFA_CTL_1 0x68080 5311 #define _PFB_CTL_1 0x68880 5312 #define PF_ENABLE (1 << 31) 5313 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 5314 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5315 #define PF_FILTER_MASK (3 << 23) 5316 #define PF_FILTER_PROGRAMMED (0 << 23) 5317 #define PF_FILTER_MED_3x3 (1 << 23) 5318 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 5319 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 5320 #define _PFA_WIN_SZ 0x68074 5321 #define _PFB_WIN_SZ 0x68874 5322 #define _PFA_WIN_POS 0x68070 5323 #define _PFB_WIN_POS 0x68870 5324 #define _PFA_VSCALE 0x68084 5325 #define _PFB_VSCALE 0x68884 5326 #define _PFA_HSCALE 0x68090 5327 #define _PFB_HSCALE 0x68890 5328 5329 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5330 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5331 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5332 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5333 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5334 5335 #define _PSA_CTL 0x68180 5336 #define _PSB_CTL 0x68980 5337 #define PS_ENABLE (1 << 31) 5338 #define _PSA_WIN_SZ 0x68174 5339 #define _PSB_WIN_SZ 0x68974 5340 #define _PSA_WIN_POS 0x68170 5341 #define _PSB_WIN_POS 0x68970 5342 5343 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5344 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5345 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5346 5347 /* 5348 * Skylake scalers 5349 */ 5350 #define _PS_1A_CTRL 0x68180 5351 #define _PS_2A_CTRL 0x68280 5352 #define _PS_1B_CTRL 0x68980 5353 #define _PS_2B_CTRL 0x68A80 5354 #define _PS_1C_CTRL 0x69180 5355 #define PS_SCALER_EN (1 << 31) 5356 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 5357 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 5358 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 5359 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 5360 #define PS_SCALER_MODE_PLANAR (1 << 29) 5361 #define PS_SCALER_MODE_NORMAL (0 << 29) 5362 #define PS_PLANE_SEL_MASK (7 << 25) 5363 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5364 #define PS_FILTER_MASK (3 << 23) 5365 #define PS_FILTER_MEDIUM (0 << 23) 5366 #define PS_FILTER_PROGRAMMED (1 << 23) 5367 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5368 #define PS_FILTER_BILINEAR (3 << 23) 5369 #define PS_VERT3TAP (1 << 21) 5370 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5371 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5372 #define PS_PWRUP_PROGRESS (1 << 17) 5373 #define PS_V_FILTER_BYPASS (1 << 8) 5374 #define PS_VADAPT_EN (1 << 7) 5375 #define PS_VADAPT_MODE_MASK (3 << 5) 5376 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5377 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5378 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5379 #define PS_PLANE_Y_SEL_MASK (7 << 5) 5380 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 5381 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 5382 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 5383 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 5384 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 5385 5386 #define _PS_PWR_GATE_1A 0x68160 5387 #define _PS_PWR_GATE_2A 0x68260 5388 #define _PS_PWR_GATE_1B 0x68960 5389 #define _PS_PWR_GATE_2B 0x68A60 5390 #define _PS_PWR_GATE_1C 0x69160 5391 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5392 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5393 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5394 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5395 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5396 #define PS_PWR_GATE_SLPEN_8 0 5397 #define PS_PWR_GATE_SLPEN_16 1 5398 #define PS_PWR_GATE_SLPEN_24 2 5399 #define PS_PWR_GATE_SLPEN_32 3 5400 5401 #define _PS_WIN_POS_1A 0x68170 5402 #define _PS_WIN_POS_2A 0x68270 5403 #define _PS_WIN_POS_1B 0x68970 5404 #define _PS_WIN_POS_2B 0x68A70 5405 #define _PS_WIN_POS_1C 0x69170 5406 5407 #define _PS_WIN_SZ_1A 0x68174 5408 #define _PS_WIN_SZ_2A 0x68274 5409 #define _PS_WIN_SZ_1B 0x68974 5410 #define _PS_WIN_SZ_2B 0x68A74 5411 #define _PS_WIN_SZ_1C 0x69174 5412 5413 #define _PS_VSCALE_1A 0x68184 5414 #define _PS_VSCALE_2A 0x68284 5415 #define _PS_VSCALE_1B 0x68984 5416 #define _PS_VSCALE_2B 0x68A84 5417 #define _PS_VSCALE_1C 0x69184 5418 5419 #define _PS_HSCALE_1A 0x68190 5420 #define _PS_HSCALE_2A 0x68290 5421 #define _PS_HSCALE_1B 0x68990 5422 #define _PS_HSCALE_2B 0x68A90 5423 #define _PS_HSCALE_1C 0x69190 5424 5425 #define _PS_VPHASE_1A 0x68188 5426 #define _PS_VPHASE_2A 0x68288 5427 #define _PS_VPHASE_1B 0x68988 5428 #define _PS_VPHASE_2B 0x68A88 5429 #define _PS_VPHASE_1C 0x69188 5430 #define PS_Y_PHASE(x) ((x) << 16) 5431 #define PS_UV_RGB_PHASE(x) ((x) << 0) 5432 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 5433 #define PS_PHASE_TRIP (1 << 0) 5434 5435 #define _PS_HPHASE_1A 0x68194 5436 #define _PS_HPHASE_2A 0x68294 5437 #define _PS_HPHASE_1B 0x68994 5438 #define _PS_HPHASE_2B 0x68A94 5439 #define _PS_HPHASE_1C 0x69194 5440 5441 #define _PS_ECC_STAT_1A 0x681D0 5442 #define _PS_ECC_STAT_2A 0x682D0 5443 #define _PS_ECC_STAT_1B 0x689D0 5444 #define _PS_ECC_STAT_2B 0x68AD0 5445 #define _PS_ECC_STAT_1C 0x691D0 5446 5447 #define _PS_COEF_SET0_INDEX_1A 0x68198 5448 #define _PS_COEF_SET0_INDEX_2A 0x68298 5449 #define _PS_COEF_SET0_INDEX_1B 0x68998 5450 #define _PS_COEF_SET0_INDEX_2B 0x68A98 5451 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 5452 5453 #define _PS_COEF_SET0_DATA_1A 0x6819C 5454 #define _PS_COEF_SET0_DATA_2A 0x6829C 5455 #define _PS_COEF_SET0_DATA_1B 0x6899C 5456 #define _PS_COEF_SET0_DATA_2B 0x68A9C 5457 5458 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 5459 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5460 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5461 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5462 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5463 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5464 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5465 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5466 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5467 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5468 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5469 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5470 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5471 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5472 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5473 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5474 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5475 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5476 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5477 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5478 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5479 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5480 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5481 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5482 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5483 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5484 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5485 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5486 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5487 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 5488 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 5489 5490 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5491 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 5492 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 5493 /* legacy palette */ 5494 #define _LGC_PALETTE_A 0x4a000 5495 #define _LGC_PALETTE_B 0x4a800 5496 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 5497 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 5498 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 5499 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5500 5501 /* ilk/snb precision palette */ 5502 #define _PREC_PALETTE_A 0x4b000 5503 #define _PREC_PALETTE_B 0x4c000 5504 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 5505 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 5506 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 5507 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 5508 5509 #define _PREC_PIPEAGCMAX 0x4d000 5510 #define _PREC_PIPEBGCMAX 0x4d010 5511 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 5512 5513 #define _GAMMA_MODE_A 0x4a480 5514 #define _GAMMA_MODE_B 0x4ac80 5515 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5516 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 5517 #define POST_CSC_GAMMA_ENABLE (1 << 30) 5518 #define GAMMA_MODE_MODE_MASK (3 << 0) 5519 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5520 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5521 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5522 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 5523 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 5524 5525 /* Display Internal Timeout Register */ 5526 #define RM_TIMEOUT _MMIO(0x42060) 5527 #define MMIO_TIMEOUT_US(us) ((us) << 0) 5528 5529 /* interrupts */ 5530 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5531 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5532 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5533 #define DE_PLANEB_FLIP_DONE (1 << 27) 5534 #define DE_PLANEA_FLIP_DONE (1 << 26) 5535 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5536 #define DE_PCU_EVENT (1 << 25) 5537 #define DE_GTT_FAULT (1 << 24) 5538 #define DE_POISON (1 << 23) 5539 #define DE_PERFORM_COUNTER (1 << 22) 5540 #define DE_PCH_EVENT (1 << 21) 5541 #define DE_AUX_CHANNEL_A (1 << 20) 5542 #define DE_DP_A_HOTPLUG (1 << 19) 5543 #define DE_GSE (1 << 18) 5544 #define DE_PIPEB_VBLANK (1 << 15) 5545 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5546 #define DE_PIPEB_ODD_FIELD (1 << 13) 5547 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5548 #define DE_PIPEB_VSYNC (1 << 11) 5549 #define DE_PIPEB_CRC_DONE (1 << 10) 5550 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5551 #define DE_PIPEA_VBLANK (1 << 7) 5552 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 5553 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5554 #define DE_PIPEA_ODD_FIELD (1 << 5) 5555 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5556 #define DE_PIPEA_VSYNC (1 << 3) 5557 #define DE_PIPEA_CRC_DONE (1 << 2) 5558 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 5559 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5560 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 5561 5562 /* More Ivybridge lolz */ 5563 #define DE_ERR_INT_IVB (1 << 30) 5564 #define DE_GSE_IVB (1 << 29) 5565 #define DE_PCH_EVENT_IVB (1 << 28) 5566 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 5567 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 5568 #define DE_EDP_PSR_INT_HSW (1 << 19) 5569 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 5570 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 5571 #define DE_PIPEC_VBLANK_IVB (1 << 10) 5572 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 5573 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 5574 #define DE_PIPEB_VBLANK_IVB (1 << 5) 5575 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 5576 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 5577 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 5578 #define DE_PIPEA_VBLANK_IVB (1 << 0) 5579 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5580 5581 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5582 #define MASTER_INTERRUPT_ENABLE (1 << 31) 5583 5584 #define DEISR _MMIO(0x44000) 5585 #define DEIMR _MMIO(0x44004) 5586 #define DEIIR _MMIO(0x44008) 5587 #define DEIER _MMIO(0x4400c) 5588 5589 #define GTISR _MMIO(0x44010) 5590 #define GTIMR _MMIO(0x44014) 5591 #define GTIIR _MMIO(0x44018) 5592 #define GTIER _MMIO(0x4401c) 5593 5594 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5595 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 5596 #define GEN8_PCU_IRQ (1 << 30) 5597 #define GEN8_DE_PCH_IRQ (1 << 23) 5598 #define GEN8_DE_MISC_IRQ (1 << 22) 5599 #define GEN8_DE_PORT_IRQ (1 << 20) 5600 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 5601 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 5602 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 5603 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 5604 #define GEN8_GT_VECS_IRQ (1 << 6) 5605 #define GEN8_GT_GUC_IRQ (1 << 5) 5606 #define GEN8_GT_PM_IRQ (1 << 4) 5607 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 5608 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 5609 #define GEN8_GT_BCS_IRQ (1 << 1) 5610 #define GEN8_GT_RCS_IRQ (1 << 0) 5611 5612 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 5613 5614 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5615 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5616 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5617 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5618 5619 #define GEN8_RCS_IRQ_SHIFT 0 5620 #define GEN8_BCS_IRQ_SHIFT 16 5621 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 5622 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 5623 #define GEN8_VECS_IRQ_SHIFT 0 5624 #define GEN8_WD_IRQ_SHIFT 16 5625 5626 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5627 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5628 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5629 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5630 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5631 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5632 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5633 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 5634 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 5635 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5636 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5637 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5638 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5639 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5640 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5641 #define GEN8_PIPE_VSYNC (1 << 1) 5642 #define GEN8_PIPE_VBLANK (1 << 0) 5643 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5644 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 5645 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 5646 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 5647 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5648 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5649 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5650 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5651 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5652 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5653 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5654 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5655 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5656 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5657 (GEN8_PIPE_CURSOR_FAULT | \ 5658 GEN8_PIPE_SPRITE_FAULT | \ 5659 GEN8_PIPE_PRIMARY_FAULT) 5660 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5661 (GEN9_PIPE_CURSOR_FAULT | \ 5662 GEN9_PIPE_PLANE4_FAULT | \ 5663 GEN9_PIPE_PLANE3_FAULT | \ 5664 GEN9_PIPE_PLANE2_FAULT | \ 5665 GEN9_PIPE_PLANE1_FAULT) 5666 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 5667 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5668 GEN11_PIPE_PLANE7_FAULT | \ 5669 GEN11_PIPE_PLANE6_FAULT | \ 5670 GEN11_PIPE_PLANE5_FAULT) 5671 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 5672 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5673 GEN11_PIPE_PLANE5_FAULT) 5674 5675 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 5676 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 5677 5678 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5679 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5680 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5681 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5682 #define DSI1_NON_TE (1 << 31) 5683 #define DSI0_NON_TE (1 << 30) 5684 #define ICL_AUX_CHANNEL_E (1 << 29) 5685 #define ICL_AUX_CHANNEL_F (1 << 28) 5686 #define GEN9_AUX_CHANNEL_D (1 << 27) 5687 #define GEN9_AUX_CHANNEL_C (1 << 26) 5688 #define GEN9_AUX_CHANNEL_B (1 << 25) 5689 #define DSI1_TE (1 << 24) 5690 #define DSI0_TE (1 << 23) 5691 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 5692 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 5693 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 5694 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 5695 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 5696 #define BXT_DE_PORT_GMBUS (1 << 1) 5697 #define GEN8_AUX_CHANNEL_A (1 << 0) 5698 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 5699 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 5700 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 5701 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 5702 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 5703 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 5704 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 5705 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 5706 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 5707 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 5708 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 5709 5710 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5711 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5712 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5713 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5714 #define GEN8_DE_MISC_GSE (1 << 27) 5715 #define GEN8_DE_EDP_PSR (1 << 19) 5716 5717 #define GEN8_PCU_ISR _MMIO(0x444e0) 5718 #define GEN8_PCU_IMR _MMIO(0x444e4) 5719 #define GEN8_PCU_IIR _MMIO(0x444e8) 5720 #define GEN8_PCU_IER _MMIO(0x444ec) 5721 5722 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 5723 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 5724 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 5725 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 5726 #define GEN11_GU_MISC_GSE (1 << 27) 5727 5728 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 5729 #define GEN11_MASTER_IRQ (1 << 31) 5730 #define GEN11_PCU_IRQ (1 << 30) 5731 #define GEN11_GU_MISC_IRQ (1 << 29) 5732 #define GEN11_DISPLAY_IRQ (1 << 16) 5733 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 5734 #define GEN11_GT_DW1_IRQ (1 << 1) 5735 #define GEN11_GT_DW0_IRQ (1 << 0) 5736 5737 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 5738 #define DG1_MSTR_IRQ REG_BIT(31) 5739 #define DG1_MSTR_TILE(t) REG_BIT(t) 5740 5741 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 5742 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 5743 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 5744 #define GEN11_DE_PCH_IRQ (1 << 23) 5745 #define GEN11_DE_MISC_IRQ (1 << 22) 5746 #define GEN11_DE_HPD_IRQ (1 << 21) 5747 #define GEN11_DE_PORT_IRQ (1 << 20) 5748 #define GEN11_DE_PIPE_C (1 << 18) 5749 #define GEN11_DE_PIPE_B (1 << 17) 5750 #define GEN11_DE_PIPE_A (1 << 16) 5751 5752 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 5753 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 5754 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 5755 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 5756 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 5757 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 5758 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 5759 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 5760 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 5761 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 5762 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 5763 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 5764 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 5765 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 5766 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 5767 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 5768 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 5769 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 5770 5771 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 5772 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 5773 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5774 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5775 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5776 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 5777 5778 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5779 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5780 #define ILK_ELPIN_409_SELECT (1 << 25) 5781 #define ILK_DPARB_GATE (1 << 22) 5782 #define ILK_VSDPFD_FULL (1 << 21) 5783 #define FUSE_STRAP _MMIO(0x42014) 5784 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5785 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5786 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5787 #define IVB_PIPE_C_DISABLE (1 << 28) 5788 #define ILK_HDCP_DISABLE (1 << 25) 5789 #define ILK_eDP_A_DISABLE (1 << 24) 5790 #define HSW_CDCLK_LIMIT (1 << 24) 5791 #define ILK_DESKTOP (1 << 23) 5792 #define HSW_CPU_SSC_ENABLE (1 << 21) 5793 5794 #define FUSE_STRAP3 _MMIO(0x42020) 5795 #define HSW_REF_CLK_SELECT (1 << 1) 5796 5797 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5798 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5799 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5800 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5801 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5802 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5803 5804 #define IVB_CHICKEN3 _MMIO(0x4200c) 5805 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5806 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5807 5808 #define CHICKEN_PAR1_1 _MMIO(0x42080) 5809 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 5810 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 5811 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 5812 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 5813 #define DPA_MASK_VBLANK_SRD (1 << 15) 5814 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5815 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 5816 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 5817 5818 #define CHICKEN_PAR2_1 _MMIO(0x42090) 5819 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 5820 5821 #define CHICKEN_MISC_2 _MMIO(0x42084) 5822 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 5823 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 5824 #define GLK_CL2_PWR_DOWN (1 << 12) 5825 #define GLK_CL1_PWR_DOWN (1 << 11) 5826 #define GLK_CL0_PWR_DOWN (1 << 10) 5827 5828 #define CHICKEN_MISC_4 _MMIO(0x4208c) 5829 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 5830 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 5831 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 5832 5833 #define _CHICKEN_PIPESL_1_A 0x420b0 5834 #define _CHICKEN_PIPESL_1_B 0x420b4 5835 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 5836 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 5837 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 5838 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 5839 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 5840 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 5841 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 5842 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 5843 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 5844 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 5845 #define HSW_FBCQ_DIS (1 << 22) 5846 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5847 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 5848 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 5849 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 5850 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 5851 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 5852 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5853 5854 #define _CHICKEN_TRANS_A 0x420c0 5855 #define _CHICKEN_TRANS_B 0x420c4 5856 #define _CHICKEN_TRANS_C 0x420c8 5857 #define _CHICKEN_TRANS_EDP 0x420cc 5858 #define _CHICKEN_TRANS_D 0x420d8 5859 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 5860 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 5861 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 5862 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 5863 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 5864 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 5865 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 5866 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 5867 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 5868 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 5869 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 5870 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 5871 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 5872 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 5873 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 5874 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 5875 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 5876 5877 #define DISP_ARB_CTL _MMIO(0x45000) 5878 #define DISP_FBC_MEMORY_WAKE (1 << 31) 5879 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 5880 #define DISP_FBC_WM_DIS (1 << 15) 5881 #define DISP_ARB_CTL2 _MMIO(0x45004) 5882 #define DISP_DATA_PARTITION_5_6 (1 << 6) 5883 #define DISP_IPC_ENABLE (1 << 3) 5884 5885 /* 5886 * The below are numbered starting from "S1" on gen11/gen12, but starting 5887 * with display 13, the bspec switches to a 0-based numbering scheme 5888 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 5889 * We'll just use the 0-based numbering here for all platforms since it's the 5890 * way things will be named by the hardware team going forward, plus it's more 5891 * consistent with how most of the rest of our registers are named. 5892 */ 5893 #define _DBUF_CTL_S0 0x45008 5894 #define _DBUF_CTL_S1 0x44FE8 5895 #define _DBUF_CTL_S2 0x44300 5896 #define _DBUF_CTL_S3 0x44304 5897 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 5898 _DBUF_CTL_S0, \ 5899 _DBUF_CTL_S1, \ 5900 _DBUF_CTL_S2, \ 5901 _DBUF_CTL_S3)) 5902 #define DBUF_POWER_REQUEST REG_BIT(31) 5903 #define DBUF_POWER_STATE REG_BIT(30) 5904 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 5905 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 5906 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 5907 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 5908 5909 #define GEN7_MSG_CTL _MMIO(0x45010) 5910 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 5911 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 5912 5913 #define _BW_BUDDY0_CTL 0x45130 5914 #define _BW_BUDDY1_CTL 0x45140 5915 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 5916 _BW_BUDDY0_CTL, \ 5917 _BW_BUDDY1_CTL)) 5918 #define BW_BUDDY_DISABLE REG_BIT(31) 5919 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 5920 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 5921 5922 #define _BW_BUDDY0_PAGE_MASK 0x45134 5923 #define _BW_BUDDY1_PAGE_MASK 0x45144 5924 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 5925 _BW_BUDDY0_PAGE_MASK, \ 5926 _BW_BUDDY1_PAGE_MASK)) 5927 5928 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 5929 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 5930 5931 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 5932 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 5933 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 5934 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 5935 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 5936 #define ICL_DELAY_PMRSP REG_BIT(22) 5937 #define DISABLE_FLR_SRC REG_BIT(15) 5938 #define MASK_WAKEMEM REG_BIT(13) 5939 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 5940 5941 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 5942 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 5943 #define DCPR_MASK_LPMODE REG_BIT(26) 5944 #define DCPR_SEND_RESP_IMM REG_BIT(25) 5945 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 5946 5947 #define SKL_DFSM _MMIO(0x51000) 5948 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 5949 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 5950 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 5951 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 5952 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 5953 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 5954 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 5955 #define ICL_DFSM_DMC_DISABLE (1 << 23) 5956 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 5957 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 5958 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 5959 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 5960 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 5961 5962 #define SKL_DSSM _MMIO(0x51004) 5963 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 5964 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 5965 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 5966 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 5967 5968 /*GEN11 chicken */ 5969 #define _PIPEA_CHICKEN 0x70038 5970 #define _PIPEB_CHICKEN 0x71038 5971 #define _PIPEC_CHICKEN 0x72038 5972 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 5973 _PIPEB_CHICKEN) 5974 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 5975 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 5976 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 5977 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 5978 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 5979 5980 /* PCH */ 5981 5982 #define PCH_DISPLAY_BASE 0xc0000u 5983 5984 /* south display engine interrupt: IBX */ 5985 #define SDE_AUDIO_POWER_D (1 << 27) 5986 #define SDE_AUDIO_POWER_C (1 << 26) 5987 #define SDE_AUDIO_POWER_B (1 << 25) 5988 #define SDE_AUDIO_POWER_SHIFT (25) 5989 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5990 #define SDE_GMBUS (1 << 24) 5991 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5992 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5993 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5994 #define SDE_AUDIO_TRANSB (1 << 21) 5995 #define SDE_AUDIO_TRANSA (1 << 20) 5996 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5997 #define SDE_POISON (1 << 19) 5998 /* 18 reserved */ 5999 #define SDE_FDI_RXB (1 << 17) 6000 #define SDE_FDI_RXA (1 << 16) 6001 #define SDE_FDI_MASK (3 << 16) 6002 #define SDE_AUXD (1 << 15) 6003 #define SDE_AUXC (1 << 14) 6004 #define SDE_AUXB (1 << 13) 6005 #define SDE_AUX_MASK (7 << 13) 6006 /* 12 reserved */ 6007 #define SDE_CRT_HOTPLUG (1 << 11) 6008 #define SDE_PORTD_HOTPLUG (1 << 10) 6009 #define SDE_PORTC_HOTPLUG (1 << 9) 6010 #define SDE_PORTB_HOTPLUG (1 << 8) 6011 #define SDE_SDVOB_HOTPLUG (1 << 6) 6012 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 6013 SDE_SDVOB_HOTPLUG | \ 6014 SDE_PORTB_HOTPLUG | \ 6015 SDE_PORTC_HOTPLUG | \ 6016 SDE_PORTD_HOTPLUG) 6017 #define SDE_TRANSB_CRC_DONE (1 << 5) 6018 #define SDE_TRANSB_CRC_ERR (1 << 4) 6019 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 6020 #define SDE_TRANSA_CRC_DONE (1 << 2) 6021 #define SDE_TRANSA_CRC_ERR (1 << 1) 6022 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 6023 #define SDE_TRANS_MASK (0x3f) 6024 6025 /* south display engine interrupt: CPT - CNP */ 6026 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 6027 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 6028 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 6029 #define SDE_AUDIO_POWER_SHIFT_CPT 29 6030 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 6031 #define SDE_AUXD_CPT (1 << 27) 6032 #define SDE_AUXC_CPT (1 << 26) 6033 #define SDE_AUXB_CPT (1 << 25) 6034 #define SDE_AUX_MASK_CPT (7 << 25) 6035 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 6036 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 6037 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 6038 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 6039 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 6040 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 6041 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 6042 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 6043 SDE_SDVOB_HOTPLUG_CPT | \ 6044 SDE_PORTD_HOTPLUG_CPT | \ 6045 SDE_PORTC_HOTPLUG_CPT | \ 6046 SDE_PORTB_HOTPLUG_CPT) 6047 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 6048 SDE_PORTD_HOTPLUG_CPT | \ 6049 SDE_PORTC_HOTPLUG_CPT | \ 6050 SDE_PORTB_HOTPLUG_CPT | \ 6051 SDE_PORTA_HOTPLUG_SPT) 6052 #define SDE_GMBUS_CPT (1 << 17) 6053 #define SDE_ERROR_CPT (1 << 16) 6054 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 6055 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 6056 #define SDE_FDI_RXC_CPT (1 << 8) 6057 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 6058 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 6059 #define SDE_FDI_RXB_CPT (1 << 4) 6060 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 6061 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 6062 #define SDE_FDI_RXA_CPT (1 << 0) 6063 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 6064 SDE_AUDIO_CP_REQ_B_CPT | \ 6065 SDE_AUDIO_CP_REQ_A_CPT) 6066 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 6067 SDE_AUDIO_CP_CHG_B_CPT | \ 6068 SDE_AUDIO_CP_CHG_A_CPT) 6069 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 6070 SDE_FDI_RXB_CPT | \ 6071 SDE_FDI_RXA_CPT) 6072 6073 /* south display engine interrupt: ICP/TGP */ 6074 #define SDE_GMBUS_ICP (1 << 23) 6075 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 6076 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 6077 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 6078 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 6079 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 6080 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 6081 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 6082 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 6083 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 6084 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 6085 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 6086 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 6087 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 6088 6089 #define SDEISR _MMIO(0xc4000) 6090 #define SDEIMR _MMIO(0xc4004) 6091 #define SDEIIR _MMIO(0xc4008) 6092 #define SDEIER _MMIO(0xc400c) 6093 6094 #define SERR_INT _MMIO(0xc4040) 6095 #define SERR_INT_POISON (1 << 31) 6096 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 6097 6098 /* digital port hotplug */ 6099 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6100 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6101 #define BXT_DDIA_HPD_INVERT (1 << 27) 6102 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6103 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6104 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6105 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6106 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6107 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6108 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6109 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6110 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6111 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6112 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6113 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6114 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6115 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6116 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6117 #define BXT_DDIC_HPD_INVERT (1 << 11) 6118 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6119 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6120 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6121 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6122 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6123 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6124 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6125 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6126 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6127 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6128 #define BXT_DDIB_HPD_INVERT (1 << 3) 6129 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6130 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6131 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6132 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6133 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6134 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6135 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6136 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6137 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6138 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6139 BXT_DDIB_HPD_INVERT | \ 6140 BXT_DDIC_HPD_INVERT) 6141 6142 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6143 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6144 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6145 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6146 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6147 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6148 6149 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 6150 * functionality covered in PCH_PORT_HOTPLUG is split into 6151 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 6152 */ 6153 6154 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 6155 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6156 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6157 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6158 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6159 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6160 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6161 6162 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 6163 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 6164 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 6165 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 6166 6167 #define SHPD_FILTER_CNT _MMIO(0xc4038) 6168 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 6169 6170 #define _PCH_DPLL_A 0xc6014 6171 #define _PCH_DPLL_B 0xc6018 6172 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6173 6174 #define _PCH_FPA0 0xc6040 6175 #define FP_CB_TUNE (0x3 << 22) 6176 #define _PCH_FPA1 0xc6044 6177 #define _PCH_FPB0 0xc6048 6178 #define _PCH_FPB1 0xc604c 6179 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 6180 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 6181 6182 #define PCH_DPLL_TEST _MMIO(0xc606c) 6183 6184 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6185 #define DREF_CONTROL_MASK 0x7fc3 6186 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 6187 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 6188 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 6189 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 6190 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 6191 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 6192 #define DREF_SSC_SOURCE_MASK (3 << 11) 6193 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 6194 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 6195 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 6196 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 6197 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 6198 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 6199 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 6200 #define DREF_SSC4_DOWNSPREAD (0 << 6) 6201 #define DREF_SSC4_CENTERSPREAD (1 << 6) 6202 #define DREF_SSC1_DISABLE (0 << 1) 6203 #define DREF_SSC1_ENABLE (1 << 1) 6204 #define DREF_SSC4_DISABLE (0) 6205 #define DREF_SSC4_ENABLE (1) 6206 6207 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6208 #define FDL_TP1_TIMER_SHIFT 12 6209 #define FDL_TP1_TIMER_MASK (3 << 12) 6210 #define FDL_TP2_TIMER_SHIFT 10 6211 #define FDL_TP2_TIMER_MASK (3 << 10) 6212 #define RAWCLK_FREQ_MASK 0x3ff 6213 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 6214 #define CNP_RAWCLK_DIV(div) ((div) << 16) 6215 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 6216 #define CNP_RAWCLK_DEN(den) ((den) << 26) 6217 #define ICP_RAWCLK_NUM(num) ((num) << 11) 6218 6219 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6220 6221 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6222 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6223 6224 #define PCH_DPLL_SEL _MMIO(0xc7000) 6225 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6226 #define TRANS_DPLLA_SEL(pipe) 0 6227 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6228 6229 /* transcoder */ 6230 6231 #define _PCH_TRANS_HTOTAL_A 0xe0000 6232 #define TRANS_HTOTAL_SHIFT 16 6233 #define TRANS_HACTIVE_SHIFT 0 6234 #define _PCH_TRANS_HBLANK_A 0xe0004 6235 #define TRANS_HBLANK_END_SHIFT 16 6236 #define TRANS_HBLANK_START_SHIFT 0 6237 #define _PCH_TRANS_HSYNC_A 0xe0008 6238 #define TRANS_HSYNC_END_SHIFT 16 6239 #define TRANS_HSYNC_START_SHIFT 0 6240 #define _PCH_TRANS_VTOTAL_A 0xe000c 6241 #define TRANS_VTOTAL_SHIFT 16 6242 #define TRANS_VACTIVE_SHIFT 0 6243 #define _PCH_TRANS_VBLANK_A 0xe0010 6244 #define TRANS_VBLANK_END_SHIFT 16 6245 #define TRANS_VBLANK_START_SHIFT 0 6246 #define _PCH_TRANS_VSYNC_A 0xe0014 6247 #define TRANS_VSYNC_END_SHIFT 16 6248 #define TRANS_VSYNC_START_SHIFT 0 6249 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6250 6251 #define _PCH_TRANSA_DATA_M1 0xe0030 6252 #define _PCH_TRANSA_DATA_N1 0xe0034 6253 #define _PCH_TRANSA_DATA_M2 0xe0038 6254 #define _PCH_TRANSA_DATA_N2 0xe003c 6255 #define _PCH_TRANSA_LINK_M1 0xe0040 6256 #define _PCH_TRANSA_LINK_N1 0xe0044 6257 #define _PCH_TRANSA_LINK_M2 0xe0048 6258 #define _PCH_TRANSA_LINK_N2 0xe004c 6259 6260 /* Per-transcoder DIP controls (PCH) */ 6261 #define _VIDEO_DIP_CTL_A 0xe0200 6262 #define _VIDEO_DIP_DATA_A 0xe0208 6263 #define _VIDEO_DIP_GCP_A 0xe0210 6264 #define GCP_COLOR_INDICATION (1 << 2) 6265 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6266 #define GCP_AV_MUTE (1 << 0) 6267 6268 #define _VIDEO_DIP_CTL_B 0xe1200 6269 #define _VIDEO_DIP_DATA_B 0xe1208 6270 #define _VIDEO_DIP_GCP_B 0xe1210 6271 6272 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6273 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6274 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6275 6276 /* Per-transcoder DIP controls (VLV) */ 6277 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6278 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6279 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6280 6281 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6282 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6283 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6284 6285 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6286 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6287 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6288 6289 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6290 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6291 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6292 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6293 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6294 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6295 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6296 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6297 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6298 6299 /* Haswell DIP controls */ 6300 6301 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6302 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6303 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6304 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6305 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6306 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6307 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 6308 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6309 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6310 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6311 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6312 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6313 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6314 6315 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6316 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6317 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6318 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6319 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6320 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6321 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 6322 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6323 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6324 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6325 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6326 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6327 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6328 6329 /* Icelake PPS_DATA and _ECC DIP Registers. 6330 * These are available for transcoders B,C and eDP. 6331 * Adding the _A so as to reuse the _MMIO_TRANS2 6332 * definition, with which it offsets to the right location. 6333 */ 6334 6335 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 6336 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 6337 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 6338 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 6339 6340 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6341 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6342 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6343 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6344 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6345 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 6346 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6347 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 6348 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 6349 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 6350 6351 #define _HSW_STEREO_3D_CTL_A 0x70020 6352 #define S3D_ENABLE (1 << 31) 6353 #define _HSW_STEREO_3D_CTL_B 0x71020 6354 6355 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6356 6357 #define _PCH_TRANS_HTOTAL_B 0xe1000 6358 #define _PCH_TRANS_HBLANK_B 0xe1004 6359 #define _PCH_TRANS_HSYNC_B 0xe1008 6360 #define _PCH_TRANS_VTOTAL_B 0xe100c 6361 #define _PCH_TRANS_VBLANK_B 0xe1010 6362 #define _PCH_TRANS_VSYNC_B 0xe1014 6363 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6364 6365 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6366 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6367 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6368 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6369 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6370 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6371 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6372 6373 #define _PCH_TRANSB_DATA_M1 0xe1030 6374 #define _PCH_TRANSB_DATA_N1 0xe1034 6375 #define _PCH_TRANSB_DATA_M2 0xe1038 6376 #define _PCH_TRANSB_DATA_N2 0xe103c 6377 #define _PCH_TRANSB_LINK_M1 0xe1040 6378 #define _PCH_TRANSB_LINK_N1 0xe1044 6379 #define _PCH_TRANSB_LINK_M2 0xe1048 6380 #define _PCH_TRANSB_LINK_N2 0xe104c 6381 6382 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6383 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6384 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6385 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6386 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6387 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6388 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6389 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6390 6391 #define _PCH_TRANSACONF 0xf0008 6392 #define _PCH_TRANSBCONF 0xf1008 6393 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6394 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6395 #define TRANS_ENABLE REG_BIT(31) 6396 #define TRANS_STATE_ENABLE REG_BIT(30) 6397 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 6398 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 6399 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 6400 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 6401 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 6402 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 6403 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 6404 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 6405 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 6406 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 6407 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 6408 #define _TRANSA_CHICKEN1 0xf0060 6409 #define _TRANSB_CHICKEN1 0xf1060 6410 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6411 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 6412 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 6413 #define _TRANSA_CHICKEN2 0xf0064 6414 #define _TRANSB_CHICKEN2 0xf1064 6415 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6416 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 6417 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 6418 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 6419 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 6420 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 6421 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 6422 6423 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6424 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6425 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6426 #define INVERT_DDID_HPD (1 << 18) 6427 #define INVERT_DDIC_HPD (1 << 17) 6428 #define INVERT_DDIB_HPD (1 << 16) 6429 #define INVERT_DDIA_HPD (1 << 15) 6430 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6431 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6432 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6433 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 6434 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 6435 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 6436 #define SPT_PWM_GRANULARITY (1 << 0) 6437 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6438 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 6439 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 6440 #define LPT_PWM_GRANULARITY (1 << 5) 6441 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 6442 6443 #define _FDI_RXA_CHICKEN 0xc200c 6444 #define _FDI_RXB_CHICKEN 0xc2010 6445 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 6446 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 6447 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6448 6449 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6450 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 6451 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 6452 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 6453 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 6454 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 6455 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 6456 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 6457 6458 /* CPU: FDI_TX */ 6459 #define _FDI_TXA_CTL 0x60100 6460 #define _FDI_TXB_CTL 0x61100 6461 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6462 #define FDI_TX_DISABLE (0 << 31) 6463 #define FDI_TX_ENABLE (1 << 31) 6464 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 6465 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 6466 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 6467 #define FDI_LINK_TRAIN_NONE (3 << 28) 6468 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 6469 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 6470 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 6471 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 6472 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 6473 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 6474 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 6475 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 6476 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6477 SNB has different settings. */ 6478 /* SNB A-stepping */ 6479 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6480 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6481 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6482 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6483 /* SNB B-stepping */ 6484 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 6485 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 6486 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 6487 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 6488 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 6489 #define FDI_DP_PORT_WIDTH_SHIFT 19 6490 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6491 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6492 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 6493 /* Ironlake: hardwired to 1 */ 6494 #define FDI_TX_PLL_ENABLE (1 << 14) 6495 6496 /* Ivybridge has different bits for lolz */ 6497 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 6498 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 6499 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 6500 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 6501 6502 /* both Tx and Rx */ 6503 #define FDI_COMPOSITE_SYNC (1 << 11) 6504 #define FDI_LINK_TRAIN_AUTO (1 << 10) 6505 #define FDI_SCRAMBLING_ENABLE (0 << 7) 6506 #define FDI_SCRAMBLING_DISABLE (1 << 7) 6507 6508 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6509 #define _FDI_RXA_CTL 0xf000c 6510 #define _FDI_RXB_CTL 0xf100c 6511 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6512 #define FDI_RX_ENABLE (1 << 31) 6513 /* train, dp width same as FDI_TX */ 6514 #define FDI_FS_ERRC_ENABLE (1 << 27) 6515 #define FDI_FE_ERRC_ENABLE (1 << 26) 6516 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 6517 #define FDI_8BPC (0 << 16) 6518 #define FDI_10BPC (1 << 16) 6519 #define FDI_6BPC (2 << 16) 6520 #define FDI_12BPC (3 << 16) 6521 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 6522 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 6523 #define FDI_RX_PLL_ENABLE (1 << 13) 6524 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 6525 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 6526 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 6527 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 6528 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 6529 #define FDI_PCDCLK (1 << 4) 6530 /* CPT */ 6531 #define FDI_AUTO_TRAINING (1 << 10) 6532 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 6533 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 6534 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 6535 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 6536 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 6537 6538 #define _FDI_RXA_MISC 0xf0010 6539 #define _FDI_RXB_MISC 0xf1010 6540 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 6541 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 6542 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 6543 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 6544 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 6545 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 6546 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 6547 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6548 6549 #define _FDI_RXA_TUSIZE1 0xf0030 6550 #define _FDI_RXA_TUSIZE2 0xf0038 6551 #define _FDI_RXB_TUSIZE1 0xf1030 6552 #define _FDI_RXB_TUSIZE2 0xf1038 6553 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6554 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6555 6556 /* FDI_RX interrupt register format */ 6557 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 6558 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 6559 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 6560 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 6561 #define FDI_RX_FS_CODE_ERR (1 << 6) 6562 #define FDI_RX_FE_CODE_ERR (1 << 5) 6563 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 6564 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 6565 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 6566 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 6567 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 6568 6569 #define _FDI_RXA_IIR 0xf0014 6570 #define _FDI_RXA_IMR 0xf0018 6571 #define _FDI_RXB_IIR 0xf1014 6572 #define _FDI_RXB_IMR 0xf1018 6573 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6574 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6575 6576 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6577 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6578 6579 #define PCH_LVDS _MMIO(0xe1180) 6580 #define LVDS_DETECTED (1 << 1) 6581 6582 #define _PCH_DP_B 0xe4100 6583 #define PCH_DP_B _MMIO(_PCH_DP_B) 6584 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6585 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6586 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6587 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6588 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6589 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6590 6591 #define _PCH_DP_C 0xe4200 6592 #define PCH_DP_C _MMIO(_PCH_DP_C) 6593 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6594 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6595 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6596 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6597 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6598 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6599 6600 #define _PCH_DP_D 0xe4300 6601 #define PCH_DP_D _MMIO(_PCH_DP_D) 6602 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6603 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6604 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6605 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6606 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6607 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6608 6609 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6610 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6611 6612 /* CPT */ 6613 #define _TRANS_DP_CTL_A 0xe0300 6614 #define _TRANS_DP_CTL_B 0xe1300 6615 #define _TRANS_DP_CTL_C 0xe2300 6616 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6617 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 6618 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 6619 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 6620 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 6621 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 6622 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 6623 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 6624 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 6625 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 6626 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 6627 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 6628 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 6629 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 6630 6631 #define _TRANS_DP2_CTL_A 0x600a0 6632 #define _TRANS_DP2_CTL_B 0x610a0 6633 #define _TRANS_DP2_CTL_C 0x620a0 6634 #define _TRANS_DP2_CTL_D 0x630a0 6635 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 6636 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 6637 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 6638 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 6639 6640 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 6641 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 6642 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 6643 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 6644 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 6645 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 6646 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 6647 6648 #define _TRANS_DP2_VFREQLOW_A 0x600a8 6649 #define _TRANS_DP2_VFREQLOW_B 0x610a8 6650 #define _TRANS_DP2_VFREQLOW_C 0x620a8 6651 #define _TRANS_DP2_VFREQLOW_D 0x630a8 6652 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 6653 6654 /* SNB eDP training params */ 6655 /* SNB A-stepping */ 6656 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6657 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6658 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6659 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6660 /* SNB B-stepping */ 6661 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 6662 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 6663 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 6664 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 6665 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 6666 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 6667 6668 /* IVB */ 6669 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 6670 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 6671 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 6672 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 6673 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 6674 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 6675 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 6676 6677 /* legacy values */ 6678 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 6679 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 6680 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 6681 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 6682 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 6683 6684 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 6685 6686 #define VLV_PMWGICZ _MMIO(0x1300a4) 6687 6688 #define HSW_EDRAM_CAP _MMIO(0x120010) 6689 #define EDRAM_ENABLED 0x1 6690 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6691 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6692 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6693 6694 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6695 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6696 #define PIXEL_OVERLAP_CNT_SHIFT 30 6697 6698 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 6699 #define GEN6_PCODE_READY (1 << 31) 6700 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 6701 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 6702 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 6703 #define GEN6_PCODE_ERROR_MASK 0xFF 6704 #define GEN6_PCODE_SUCCESS 0x0 6705 #define GEN6_PCODE_ILLEGAL_CMD 0x1 6706 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 6707 #define GEN6_PCODE_TIMEOUT 0x3 6708 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 6709 #define GEN7_PCODE_TIMEOUT 0x2 6710 #define GEN7_PCODE_ILLEGAL_DATA 0x3 6711 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 6712 #define GEN11_PCODE_LOCKED 0x6 6713 #define GEN11_PCODE_REJECTED 0x11 6714 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 6715 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6716 #define GEN6_PCODE_READ_RC6VIDS 0x5 6717 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6718 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6719 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 6720 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6721 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 6722 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 6723 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 6724 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 6725 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 6726 #define SKL_PCODE_CDCLK_CONTROL 0x7 6727 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6728 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6729 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6730 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6731 #define GEN6_READ_OC_PARAMS 0xc 6732 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 6733 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 6734 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 6735 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 6736 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 6737 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 6738 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 6739 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 6740 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 6741 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 6742 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 6743 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 6744 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 6745 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 6746 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 6747 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 6748 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 6749 #define GEN6_PCODE_READ_D_COMP 0x10 6750 #define GEN6_PCODE_WRITE_D_COMP 0x11 6751 #define ICL_PCODE_EXIT_TCCOLD 0x12 6752 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6753 #define DISPLAY_IPS_CONTROL 0x19 6754 #define TGL_PCODE_TCCOLD 0x26 6755 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 6756 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 6757 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 6758 /* See also IPS_CTL */ 6759 #define IPS_PCODE_CONTROL (1 << 30) 6760 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6761 #define GEN9_PCODE_SAGV_CONTROL 0x21 6762 #define GEN9_SAGV_DISABLE 0x0 6763 #define GEN9_SAGV_IS_DISABLED 0x1 6764 #define GEN9_SAGV_ENABLE 0x3 6765 #define DG1_PCODE_STATUS 0x7E 6766 #define DG1_UNCORE_GET_INIT_STATUS 0x0 6767 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 6768 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 6769 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ 6770 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 6771 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 6772 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 6773 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 6774 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 6775 #define PCODE_MBOX_DOMAIN_NONE 0x0 6776 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 6777 #define GEN6_PCODE_DATA _MMIO(0x138128) 6778 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6779 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6780 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 6781 6782 /* IVYBRIDGE DPF */ 6783 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 6784 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 6785 #define GEN7_PARITY_ERROR_VALID (1 << 13) 6786 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 6787 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 6788 #define GEN7_PARITY_ERROR_ROW(reg) \ 6789 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6790 #define GEN7_PARITY_ERROR_BANK(reg) \ 6791 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6792 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6793 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6794 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 6795 6796 /* These are the 4 32-bit write offset registers for each stream 6797 * output buffer. It determines the offset from the 6798 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6799 */ 6800 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 6801 6802 /* 6803 * HSW - ICL power wells 6804 * 6805 * Platforms have up to 3 power well control register sets, each set 6806 * controlling up to 16 power wells via a request/status HW flag tuple: 6807 * - main (HSW_PWR_WELL_CTL[1-4]) 6808 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 6809 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 6810 * Each control register set consists of up to 4 registers used by different 6811 * sources that can request a power well to be enabled: 6812 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 6813 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 6814 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 6815 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 6816 */ 6817 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 6818 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 6819 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 6820 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 6821 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 6822 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 6823 6824 /* HSW/BDW power well */ 6825 #define HSW_PW_CTL_IDX_GLOBAL 15 6826 6827 /* SKL/BXT/GLK power wells */ 6828 #define SKL_PW_CTL_IDX_PW_2 15 6829 #define SKL_PW_CTL_IDX_PW_1 14 6830 #define GLK_PW_CTL_IDX_AUX_C 10 6831 #define GLK_PW_CTL_IDX_AUX_B 9 6832 #define GLK_PW_CTL_IDX_AUX_A 8 6833 #define SKL_PW_CTL_IDX_DDI_D 4 6834 #define SKL_PW_CTL_IDX_DDI_C 3 6835 #define SKL_PW_CTL_IDX_DDI_B 2 6836 #define SKL_PW_CTL_IDX_DDI_A_E 1 6837 #define GLK_PW_CTL_IDX_DDI_A 1 6838 #define SKL_PW_CTL_IDX_MISC_IO 0 6839 6840 /* ICL/TGL - power wells */ 6841 #define TGL_PW_CTL_IDX_PW_5 4 6842 #define ICL_PW_CTL_IDX_PW_4 3 6843 #define ICL_PW_CTL_IDX_PW_3 2 6844 #define ICL_PW_CTL_IDX_PW_2 1 6845 #define ICL_PW_CTL_IDX_PW_1 0 6846 6847 /* XE_LPD - power wells */ 6848 #define XELPD_PW_CTL_IDX_PW_D 8 6849 #define XELPD_PW_CTL_IDX_PW_C 7 6850 #define XELPD_PW_CTL_IDX_PW_B 6 6851 #define XELPD_PW_CTL_IDX_PW_A 5 6852 6853 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 6854 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 6855 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 6856 #define TGL_PW_CTL_IDX_AUX_TBT6 14 6857 #define TGL_PW_CTL_IDX_AUX_TBT5 13 6858 #define TGL_PW_CTL_IDX_AUX_TBT4 12 6859 #define ICL_PW_CTL_IDX_AUX_TBT4 11 6860 #define TGL_PW_CTL_IDX_AUX_TBT3 11 6861 #define ICL_PW_CTL_IDX_AUX_TBT3 10 6862 #define TGL_PW_CTL_IDX_AUX_TBT2 10 6863 #define ICL_PW_CTL_IDX_AUX_TBT2 9 6864 #define TGL_PW_CTL_IDX_AUX_TBT1 9 6865 #define ICL_PW_CTL_IDX_AUX_TBT1 8 6866 #define TGL_PW_CTL_IDX_AUX_TC6 8 6867 #define XELPD_PW_CTL_IDX_AUX_E 8 6868 #define TGL_PW_CTL_IDX_AUX_TC5 7 6869 #define XELPD_PW_CTL_IDX_AUX_D 7 6870 #define TGL_PW_CTL_IDX_AUX_TC4 6 6871 #define ICL_PW_CTL_IDX_AUX_F 5 6872 #define TGL_PW_CTL_IDX_AUX_TC3 5 6873 #define ICL_PW_CTL_IDX_AUX_E 4 6874 #define TGL_PW_CTL_IDX_AUX_TC2 4 6875 #define ICL_PW_CTL_IDX_AUX_D 3 6876 #define TGL_PW_CTL_IDX_AUX_TC1 3 6877 #define ICL_PW_CTL_IDX_AUX_C 2 6878 #define ICL_PW_CTL_IDX_AUX_B 1 6879 #define ICL_PW_CTL_IDX_AUX_A 0 6880 6881 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 6882 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 6883 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 6884 #define XELPD_PW_CTL_IDX_DDI_E 8 6885 #define TGL_PW_CTL_IDX_DDI_TC6 8 6886 #define XELPD_PW_CTL_IDX_DDI_D 7 6887 #define TGL_PW_CTL_IDX_DDI_TC5 7 6888 #define TGL_PW_CTL_IDX_DDI_TC4 6 6889 #define ICL_PW_CTL_IDX_DDI_F 5 6890 #define TGL_PW_CTL_IDX_DDI_TC3 5 6891 #define ICL_PW_CTL_IDX_DDI_E 4 6892 #define TGL_PW_CTL_IDX_DDI_TC2 4 6893 #define ICL_PW_CTL_IDX_DDI_D 3 6894 #define TGL_PW_CTL_IDX_DDI_TC1 3 6895 #define ICL_PW_CTL_IDX_DDI_C 2 6896 #define ICL_PW_CTL_IDX_DDI_B 1 6897 #define ICL_PW_CTL_IDX_DDI_A 0 6898 6899 /* HSW - power well misc debug registers */ 6900 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 6901 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 6902 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 6903 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 6904 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 6905 6906 /* SKL Fuse Status */ 6907 enum skl_power_gate { 6908 SKL_PG0, 6909 SKL_PG1, 6910 SKL_PG2, 6911 ICL_PG3, 6912 ICL_PG4, 6913 }; 6914 6915 #define SKL_FUSE_STATUS _MMIO(0x42000) 6916 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 6917 /* 6918 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6919 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 6920 */ 6921 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 6922 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 6923 /* 6924 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6925 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 6926 */ 6927 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 6928 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 6929 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 6930 6931 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 6932 #define _ICL_AUX_ANAOVRD1_A 0x162398 6933 #define _ICL_AUX_ANAOVRD1_B 0x6C398 6934 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 6935 _ICL_AUX_ANAOVRD1_A, \ 6936 _ICL_AUX_ANAOVRD1_B)) 6937 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 6938 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 6939 6940 /* HDCP Key Registers */ 6941 #define HDCP_KEY_CONF _MMIO(0x66c00) 6942 #define HDCP_AKSV_SEND_TRIGGER BIT(31) 6943 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 6944 #define HDCP_KEY_LOAD_TRIGGER BIT(8) 6945 #define HDCP_KEY_STATUS _MMIO(0x66c04) 6946 #define HDCP_FUSE_IN_PROGRESS BIT(7) 6947 #define HDCP_FUSE_ERROR BIT(6) 6948 #define HDCP_FUSE_DONE BIT(5) 6949 #define HDCP_KEY_LOAD_STATUS BIT(1) 6950 #define HDCP_KEY_LOAD_DONE BIT(0) 6951 #define HDCP_AKSV_LO _MMIO(0x66c10) 6952 #define HDCP_AKSV_HI _MMIO(0x66c14) 6953 6954 /* HDCP Repeater Registers */ 6955 #define HDCP_REP_CTL _MMIO(0x66d00) 6956 #define HDCP_TRANSA_REP_PRESENT BIT(31) 6957 #define HDCP_TRANSB_REP_PRESENT BIT(30) 6958 #define HDCP_TRANSC_REP_PRESENT BIT(29) 6959 #define HDCP_TRANSD_REP_PRESENT BIT(28) 6960 #define HDCP_DDIB_REP_PRESENT BIT(30) 6961 #define HDCP_DDIA_REP_PRESENT BIT(29) 6962 #define HDCP_DDIC_REP_PRESENT BIT(28) 6963 #define HDCP_DDID_REP_PRESENT BIT(27) 6964 #define HDCP_DDIF_REP_PRESENT BIT(26) 6965 #define HDCP_DDIE_REP_PRESENT BIT(25) 6966 #define HDCP_TRANSA_SHA1_M0 (1 << 20) 6967 #define HDCP_TRANSB_SHA1_M0 (2 << 20) 6968 #define HDCP_TRANSC_SHA1_M0 (3 << 20) 6969 #define HDCP_TRANSD_SHA1_M0 (4 << 20) 6970 #define HDCP_DDIB_SHA1_M0 (1 << 20) 6971 #define HDCP_DDIA_SHA1_M0 (2 << 20) 6972 #define HDCP_DDIC_SHA1_M0 (3 << 20) 6973 #define HDCP_DDID_SHA1_M0 (4 << 20) 6974 #define HDCP_DDIF_SHA1_M0 (5 << 20) 6975 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 6976 #define HDCP_SHA1_BUSY BIT(16) 6977 #define HDCP_SHA1_READY BIT(17) 6978 #define HDCP_SHA1_COMPLETE BIT(18) 6979 #define HDCP_SHA1_V_MATCH BIT(19) 6980 #define HDCP_SHA1_TEXT_32 (1 << 1) 6981 #define HDCP_SHA1_COMPLETE_HASH (2 << 1) 6982 #define HDCP_SHA1_TEXT_24 (4 << 1) 6983 #define HDCP_SHA1_TEXT_16 (5 << 1) 6984 #define HDCP_SHA1_TEXT_8 (6 << 1) 6985 #define HDCP_SHA1_TEXT_0 (7 << 1) 6986 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 6987 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 6988 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 6989 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 6990 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 6991 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 6992 #define HDCP_SHA_TEXT _MMIO(0x66d18) 6993 6994 /* HDCP Auth Registers */ 6995 #define _PORTA_HDCP_AUTHENC 0x66800 6996 #define _PORTB_HDCP_AUTHENC 0x66500 6997 #define _PORTC_HDCP_AUTHENC 0x66600 6998 #define _PORTD_HDCP_AUTHENC 0x66700 6999 #define _PORTE_HDCP_AUTHENC 0x66A00 7000 #define _PORTF_HDCP_AUTHENC 0x66900 7001 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 7002 _PORTA_HDCP_AUTHENC, \ 7003 _PORTB_HDCP_AUTHENC, \ 7004 _PORTC_HDCP_AUTHENC, \ 7005 _PORTD_HDCP_AUTHENC, \ 7006 _PORTE_HDCP_AUTHENC, \ 7007 _PORTF_HDCP_AUTHENC) + (x)) 7008 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 7009 #define _TRANSA_HDCP_CONF 0x66400 7010 #define _TRANSB_HDCP_CONF 0x66500 7011 #define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \ 7012 _TRANSB_HDCP_CONF) 7013 #define HDCP_CONF(dev_priv, trans, port) \ 7014 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7015 TRANS_HDCP_CONF(trans) : \ 7016 PORT_HDCP_CONF(port)) 7017 7018 #define HDCP_CONF_CAPTURE_AN BIT(0) 7019 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 7020 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 7021 #define _TRANSA_HDCP_ANINIT 0x66404 7022 #define _TRANSB_HDCP_ANINIT 0x66504 7023 #define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \ 7024 _TRANSA_HDCP_ANINIT, \ 7025 _TRANSB_HDCP_ANINIT) 7026 #define HDCP_ANINIT(dev_priv, trans, port) \ 7027 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7028 TRANS_HDCP_ANINIT(trans) : \ 7029 PORT_HDCP_ANINIT(port)) 7030 7031 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 7032 #define _TRANSA_HDCP_ANLO 0x66408 7033 #define _TRANSB_HDCP_ANLO 0x66508 7034 #define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \ 7035 _TRANSB_HDCP_ANLO) 7036 #define HDCP_ANLO(dev_priv, trans, port) \ 7037 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7038 TRANS_HDCP_ANLO(trans) : \ 7039 PORT_HDCP_ANLO(port)) 7040 7041 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 7042 #define _TRANSA_HDCP_ANHI 0x6640C 7043 #define _TRANSB_HDCP_ANHI 0x6650C 7044 #define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \ 7045 _TRANSB_HDCP_ANHI) 7046 #define HDCP_ANHI(dev_priv, trans, port) \ 7047 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7048 TRANS_HDCP_ANHI(trans) : \ 7049 PORT_HDCP_ANHI(port)) 7050 7051 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 7052 #define _TRANSA_HDCP_BKSVLO 0x66410 7053 #define _TRANSB_HDCP_BKSVLO 0x66510 7054 #define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \ 7055 _TRANSA_HDCP_BKSVLO, \ 7056 _TRANSB_HDCP_BKSVLO) 7057 #define HDCP_BKSVLO(dev_priv, trans, port) \ 7058 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7059 TRANS_HDCP_BKSVLO(trans) : \ 7060 PORT_HDCP_BKSVLO(port)) 7061 7062 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 7063 #define _TRANSA_HDCP_BKSVHI 0x66414 7064 #define _TRANSB_HDCP_BKSVHI 0x66514 7065 #define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \ 7066 _TRANSA_HDCP_BKSVHI, \ 7067 _TRANSB_HDCP_BKSVHI) 7068 #define HDCP_BKSVHI(dev_priv, trans, port) \ 7069 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7070 TRANS_HDCP_BKSVHI(trans) : \ 7071 PORT_HDCP_BKSVHI(port)) 7072 7073 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 7074 #define _TRANSA_HDCP_RPRIME 0x66418 7075 #define _TRANSB_HDCP_RPRIME 0x66518 7076 #define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \ 7077 _TRANSA_HDCP_RPRIME, \ 7078 _TRANSB_HDCP_RPRIME) 7079 #define HDCP_RPRIME(dev_priv, trans, port) \ 7080 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7081 TRANS_HDCP_RPRIME(trans) : \ 7082 PORT_HDCP_RPRIME(port)) 7083 7084 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 7085 #define _TRANSA_HDCP_STATUS 0x6641C 7086 #define _TRANSB_HDCP_STATUS 0x6651C 7087 #define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \ 7088 _TRANSA_HDCP_STATUS, \ 7089 _TRANSB_HDCP_STATUS) 7090 #define HDCP_STATUS(dev_priv, trans, port) \ 7091 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7092 TRANS_HDCP_STATUS(trans) : \ 7093 PORT_HDCP_STATUS(port)) 7094 7095 #define HDCP_STATUS_STREAM_A_ENC BIT(31) 7096 #define HDCP_STATUS_STREAM_B_ENC BIT(30) 7097 #define HDCP_STATUS_STREAM_C_ENC BIT(29) 7098 #define HDCP_STATUS_STREAM_D_ENC BIT(28) 7099 #define HDCP_STATUS_AUTH BIT(21) 7100 #define HDCP_STATUS_ENC BIT(20) 7101 #define HDCP_STATUS_RI_MATCH BIT(19) 7102 #define HDCP_STATUS_R0_READY BIT(18) 7103 #define HDCP_STATUS_AN_READY BIT(17) 7104 #define HDCP_STATUS_CIPHER BIT(16) 7105 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 7106 7107 /* HDCP2.2 Registers */ 7108 #define _PORTA_HDCP2_BASE 0x66800 7109 #define _PORTB_HDCP2_BASE 0x66500 7110 #define _PORTC_HDCP2_BASE 0x66600 7111 #define _PORTD_HDCP2_BASE 0x66700 7112 #define _PORTE_HDCP2_BASE 0x66A00 7113 #define _PORTF_HDCP2_BASE 0x66900 7114 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 7115 _PORTA_HDCP2_BASE, \ 7116 _PORTB_HDCP2_BASE, \ 7117 _PORTC_HDCP2_BASE, \ 7118 _PORTD_HDCP2_BASE, \ 7119 _PORTE_HDCP2_BASE, \ 7120 _PORTF_HDCP2_BASE) + (x)) 7121 7122 #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) 7123 #define _TRANSA_HDCP2_AUTH 0x66498 7124 #define _TRANSB_HDCP2_AUTH 0x66598 7125 #define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \ 7126 _TRANSB_HDCP2_AUTH) 7127 #define AUTH_LINK_AUTHENTICATED BIT(31) 7128 #define AUTH_LINK_TYPE BIT(30) 7129 #define AUTH_FORCE_CLR_INPUTCTR BIT(19) 7130 #define AUTH_CLR_KEYS BIT(18) 7131 #define HDCP2_AUTH(dev_priv, trans, port) \ 7132 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7133 TRANS_HDCP2_AUTH(trans) : \ 7134 PORT_HDCP2_AUTH(port)) 7135 7136 #define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0) 7137 #define _TRANSA_HDCP2_CTL 0x664B0 7138 #define _TRANSB_HDCP2_CTL 0x665B0 7139 #define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \ 7140 _TRANSB_HDCP2_CTL) 7141 #define CTL_LINK_ENCRYPTION_REQ BIT(31) 7142 #define HDCP2_CTL(dev_priv, trans, port) \ 7143 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7144 TRANS_HDCP2_CTL(trans) : \ 7145 PORT_HDCP2_CTL(port)) 7146 7147 #define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4) 7148 #define _TRANSA_HDCP2_STATUS 0x664B4 7149 #define _TRANSB_HDCP2_STATUS 0x665B4 7150 #define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \ 7151 _TRANSA_HDCP2_STATUS, \ 7152 _TRANSB_HDCP2_STATUS) 7153 #define LINK_TYPE_STATUS BIT(22) 7154 #define LINK_AUTH_STATUS BIT(21) 7155 #define LINK_ENCRYPTION_STATUS BIT(20) 7156 #define HDCP2_STATUS(dev_priv, trans, port) \ 7157 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7158 TRANS_HDCP2_STATUS(trans) : \ 7159 PORT_HDCP2_STATUS(port)) 7160 7161 #define _PIPEA_HDCP2_STREAM_STATUS 0x668C0 7162 #define _PIPEB_HDCP2_STREAM_STATUS 0x665C0 7163 #define _PIPEC_HDCP2_STREAM_STATUS 0x666C0 7164 #define _PIPED_HDCP2_STREAM_STATUS 0x667C0 7165 #define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \ 7166 _PIPEA_HDCP2_STREAM_STATUS, \ 7167 _PIPEB_HDCP2_STREAM_STATUS, \ 7168 _PIPEC_HDCP2_STREAM_STATUS, \ 7169 _PIPED_HDCP2_STREAM_STATUS)) 7170 7171 #define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 7172 #define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 7173 #define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ 7174 _TRANSA_HDCP2_STREAM_STATUS, \ 7175 _TRANSB_HDCP2_STREAM_STATUS) 7176 #define STREAM_ENCRYPTION_STATUS BIT(31) 7177 #define STREAM_TYPE_STATUS BIT(30) 7178 #define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ 7179 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7180 TRANS_HDCP2_STREAM_STATUS(trans) : \ 7181 PIPE_HDCP2_STREAM_STATUS(pipe)) 7182 7183 #define _PORTA_HDCP2_AUTH_STREAM 0x66F00 7184 #define _PORTB_HDCP2_AUTH_STREAM 0x66F04 7185 #define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ 7186 _PORTA_HDCP2_AUTH_STREAM, \ 7187 _PORTB_HDCP2_AUTH_STREAM) 7188 #define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 7189 #define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 7190 #define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ 7191 _TRANSA_HDCP2_AUTH_STREAM, \ 7192 _TRANSB_HDCP2_AUTH_STREAM) 7193 #define AUTH_STREAM_TYPE BIT(31) 7194 #define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ 7195 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7196 TRANS_HDCP2_AUTH_STREAM(trans) : \ 7197 PORT_HDCP2_AUTH_STREAM(port)) 7198 7199 /* Per-pipe DDI Function Control */ 7200 #define _TRANS_DDI_FUNC_CTL_A 0x60400 7201 #define _TRANS_DDI_FUNC_CTL_B 0x61400 7202 #define _TRANS_DDI_FUNC_CTL_C 0x62400 7203 #define _TRANS_DDI_FUNC_CTL_D 0x63400 7204 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 7205 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 7206 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 7207 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 7208 7209 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 7210 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 7211 #define TRANS_DDI_PORT_SHIFT 28 7212 #define TGL_TRANS_DDI_PORT_SHIFT 27 7213 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 7214 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 7215 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 7216 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 7217 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 7218 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 7219 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 7220 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 7221 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 7222 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 7223 #define TRANS_DDI_BPC_MASK (7 << 20) 7224 #define TRANS_DDI_BPC_8 (0 << 20) 7225 #define TRANS_DDI_BPC_10 (1 << 20) 7226 #define TRANS_DDI_BPC_6 (2 << 20) 7227 #define TRANS_DDI_BPC_12 (3 << 20) 7228 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 7229 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 7230 #define TRANS_DDI_PVSYNC (1 << 17) 7231 #define TRANS_DDI_PHSYNC (1 << 16) 7232 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 7233 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 7234 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 7235 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 7236 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 7237 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 7238 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 7239 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 7240 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 7241 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 7242 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 7243 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 7244 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 7245 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 7246 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 7247 #define TRANS_DDI_BFI_ENABLE (1 << 4) 7248 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 7249 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 7250 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 7251 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 7252 | TRANS_DDI_HDMI_SCRAMBLING) 7253 7254 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 7255 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 7256 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 7257 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 7258 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 7259 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 7260 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 7261 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 7262 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 7263 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 7264 7265 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 7266 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 7267 7268 /* DisplayPort Transport Control */ 7269 #define _DP_TP_CTL_A 0x64040 7270 #define _DP_TP_CTL_B 0x64140 7271 #define _TGL_DP_TP_CTL_A 0x60540 7272 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 7273 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 7274 #define DP_TP_CTL_ENABLE (1 << 31) 7275 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 7276 #define DP_TP_CTL_MODE_SST (0 << 27) 7277 #define DP_TP_CTL_MODE_MST (1 << 27) 7278 #define DP_TP_CTL_FORCE_ACT (1 << 25) 7279 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 7280 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 7281 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 7282 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 7283 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 7284 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 7285 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 7286 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 7287 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 7288 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 7289 7290 /* DisplayPort Transport Status */ 7291 #define _DP_TP_STATUS_A 0x64044 7292 #define _DP_TP_STATUS_B 0x64144 7293 #define _TGL_DP_TP_STATUS_A 0x60544 7294 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 7295 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 7296 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 7297 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 7298 #define DP_TP_STATUS_ACT_SENT (1 << 24) 7299 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 7300 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 7301 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 7302 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 7303 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 7304 7305 /* DDI Buffer Control */ 7306 #define _DDI_BUF_CTL_A 0x64000 7307 #define _DDI_BUF_CTL_B 0x64100 7308 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 7309 #define DDI_BUF_CTL_ENABLE (1 << 31) 7310 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 7311 #define DDI_BUF_EMP_MASK (0xf << 24) 7312 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 7313 #define DDI_BUF_PORT_REVERSAL (1 << 16) 7314 #define DDI_BUF_IS_IDLE (1 << 7) 7315 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 7316 #define DDI_A_4_LANES (1 << 4) 7317 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 7318 #define DDI_PORT_WIDTH_MASK (7 << 1) 7319 #define DDI_PORT_WIDTH_SHIFT 1 7320 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 7321 7322 /* DDI Buffer Translations */ 7323 #define _DDI_BUF_TRANS_A 0x64E00 7324 #define _DDI_BUF_TRANS_B 0x64E60 7325 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 7326 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 7327 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 7328 7329 /* DDI DP Compliance Control */ 7330 #define _DDI_DP_COMP_CTL_A 0x605F0 7331 #define _DDI_DP_COMP_CTL_B 0x615F0 7332 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 7333 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 7334 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 7335 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 7336 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 7337 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 7338 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 7339 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 7340 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 7341 7342 /* DDI DP Compliance Pattern */ 7343 #define _DDI_DP_COMP_PAT_A 0x605F4 7344 #define _DDI_DP_COMP_PAT_B 0x615F4 7345 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 7346 7347 /* Sideband Interface (SBI) is programmed indirectly, via 7348 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7349 * which contains the payload */ 7350 #define SBI_ADDR _MMIO(0xC6000) 7351 #define SBI_DATA _MMIO(0xC6004) 7352 #define SBI_CTL_STAT _MMIO(0xC6008) 7353 #define SBI_CTL_DEST_ICLK (0x0 << 16) 7354 #define SBI_CTL_DEST_MPHY (0x1 << 16) 7355 #define SBI_CTL_OP_IORD (0x2 << 8) 7356 #define SBI_CTL_OP_IOWR (0x3 << 8) 7357 #define SBI_CTL_OP_CRRD (0x6 << 8) 7358 #define SBI_CTL_OP_CRWR (0x7 << 8) 7359 #define SBI_RESPONSE_FAIL (0x1 << 1) 7360 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 7361 #define SBI_BUSY (0x1 << 0) 7362 #define SBI_READY (0x0 << 0) 7363 7364 /* SBI offsets */ 7365 #define SBI_SSCDIVINTPHASE 0x0200 7366 #define SBI_SSCDIVINTPHASE6 0x0600 7367 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 7368 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 7369 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 7370 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 7371 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 7372 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 7373 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 7374 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 7375 #define SBI_SSCDITHPHASE 0x0204 7376 #define SBI_SSCCTL 0x020c 7377 #define SBI_SSCCTL6 0x060C 7378 #define SBI_SSCCTL_PATHALT (1 << 3) 7379 #define SBI_SSCCTL_DISABLE (1 << 0) 7380 #define SBI_SSCAUXDIV6 0x0610 7381 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7382 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 7383 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 7384 #define SBI_DBUFF0 0x2a00 7385 #define SBI_GEN0 0x1f00 7386 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 7387 7388 /* LPT PIXCLK_GATE */ 7389 #define PIXCLK_GATE _MMIO(0xC6020) 7390 #define PIXCLK_GATE_UNGATE (1 << 0) 7391 #define PIXCLK_GATE_GATE (0 << 0) 7392 7393 /* SPLL */ 7394 #define SPLL_CTL _MMIO(0x46020) 7395 #define SPLL_PLL_ENABLE (1 << 31) 7396 #define SPLL_REF_BCLK (0 << 28) 7397 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7398 #define SPLL_REF_NON_SSC_HSW (2 << 28) 7399 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 7400 #define SPLL_REF_LCPLL (3 << 28) 7401 #define SPLL_REF_MASK (3 << 28) 7402 #define SPLL_FREQ_810MHz (0 << 26) 7403 #define SPLL_FREQ_1350MHz (1 << 26) 7404 #define SPLL_FREQ_2700MHz (2 << 26) 7405 #define SPLL_FREQ_MASK (3 << 26) 7406 7407 /* WRPLL */ 7408 #define _WRPLL_CTL1 0x46040 7409 #define _WRPLL_CTL2 0x46060 7410 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7411 #define WRPLL_PLL_ENABLE (1 << 31) 7412 #define WRPLL_REF_BCLK (0 << 28) 7413 #define WRPLL_REF_PCH_SSC (1 << 28) 7414 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7415 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 7416 #define WRPLL_REF_LCPLL (3 << 28) 7417 #define WRPLL_REF_MASK (3 << 28) 7418 /* WRPLL divider programming */ 7419 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 7420 #define WRPLL_DIVIDER_REF_MASK (0xff) 7421 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 7422 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 7423 #define WRPLL_DIVIDER_POST_SHIFT 8 7424 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 7425 #define WRPLL_DIVIDER_FB_SHIFT 16 7426 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 7427 7428 /* Port clock selection */ 7429 #define _PORT_CLK_SEL_A 0x46100 7430 #define _PORT_CLK_SEL_B 0x46104 7431 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7432 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 7433 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 7434 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 7435 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 7436 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 7437 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 7438 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 7439 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 7440 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 7441 7442 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 7443 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 7444 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 7445 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 7446 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 7447 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 7448 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 7449 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 7450 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 7451 7452 /* Transcoder clock selection */ 7453 #define _TRANS_CLK_SEL_A 0x46140 7454 #define _TRANS_CLK_SEL_B 0x46144 7455 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7456 /* For each transcoder, we need to select the corresponding port clock */ 7457 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 7458 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 7459 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 7460 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 7461 7462 7463 #define CDCLK_FREQ _MMIO(0x46200) 7464 7465 #define _TRANSA_MSA_MISC 0x60410 7466 #define _TRANSB_MSA_MISC 0x61410 7467 #define _TRANSC_MSA_MISC 0x62410 7468 #define _TRANS_EDP_MSA_MISC 0x6f410 7469 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7470 /* See DP_MSA_MISC_* for the bit definitions */ 7471 7472 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 7473 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 7474 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 7475 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 7476 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 7477 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 7478 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 7479 7480 /* LCPLL Control */ 7481 #define LCPLL_CTL _MMIO(0x130040) 7482 #define LCPLL_PLL_DISABLE (1 << 31) 7483 #define LCPLL_PLL_LOCK (1 << 30) 7484 #define LCPLL_REF_NON_SSC (0 << 28) 7485 #define LCPLL_REF_BCLK (2 << 28) 7486 #define LCPLL_REF_PCH_SSC (3 << 28) 7487 #define LCPLL_REF_MASK (3 << 28) 7488 #define LCPLL_CLK_FREQ_MASK (3 << 26) 7489 #define LCPLL_CLK_FREQ_450 (0 << 26) 7490 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 7491 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 7492 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 7493 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 7494 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 7495 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 7496 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 7497 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 7498 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 7499 7500 /* 7501 * SKL Clocks 7502 */ 7503 7504 /* CDCLK_CTL */ 7505 #define CDCLK_CTL _MMIO(0x46000) 7506 #define CDCLK_FREQ_SEL_MASK (3 << 26) 7507 #define CDCLK_FREQ_450_432 (0 << 26) 7508 #define CDCLK_FREQ_540 (1 << 26) 7509 #define CDCLK_FREQ_337_308 (2 << 26) 7510 #define CDCLK_FREQ_675_617 (3 << 26) 7511 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 7512 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 7513 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 7514 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 7515 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 7516 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 7517 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 7518 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7519 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 7520 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 7521 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 7522 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 7523 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 7524 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7525 7526 /* CDCLK_SQUASH_CTL */ 7527 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 7528 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 7529 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 7530 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 7531 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 7532 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 7533 7534 /* LCPLL_CTL */ 7535 #define LCPLL1_CTL _MMIO(0x46010) 7536 #define LCPLL2_CTL _MMIO(0x46014) 7537 #define LCPLL_PLL_ENABLE (1 << 31) 7538 7539 /* DPLL control1 */ 7540 #define DPLL_CTRL1 _MMIO(0x6C058) 7541 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 7542 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 7543 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 7544 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 7545 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 7546 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 7547 #define DPLL_CTRL1_LINK_RATE_2700 0 7548 #define DPLL_CTRL1_LINK_RATE_1350 1 7549 #define DPLL_CTRL1_LINK_RATE_810 2 7550 #define DPLL_CTRL1_LINK_RATE_1620 3 7551 #define DPLL_CTRL1_LINK_RATE_1080 4 7552 #define DPLL_CTRL1_LINK_RATE_2160 5 7553 7554 /* DPLL control2 */ 7555 #define DPLL_CTRL2 _MMIO(0x6C05C) 7556 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 7557 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 7558 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 7559 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 7560 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 7561 7562 /* DPLL Status */ 7563 #define DPLL_STATUS _MMIO(0x6C060) 7564 #define DPLL_LOCK(id) (1 << ((id) * 8)) 7565 7566 /* DPLL cfg */ 7567 #define _DPLL1_CFGCR1 0x6C040 7568 #define _DPLL2_CFGCR1 0x6C048 7569 #define _DPLL3_CFGCR1 0x6C050 7570 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 7571 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 7572 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 7573 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7574 7575 #define _DPLL1_CFGCR2 0x6C044 7576 #define _DPLL2_CFGCR2 0x6C04C 7577 #define _DPLL3_CFGCR2 0x6C054 7578 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 7579 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 7580 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 7581 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 7582 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 7583 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 7584 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 7585 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 7586 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 7587 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 7588 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 7589 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 7590 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 7591 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 7592 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 7593 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 7594 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7595 7596 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7597 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7598 7599 /* ICL Clocks */ 7600 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 7601 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 7602 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 7603 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 7604 (tc_port) + 12 : \ 7605 (tc_port) - TC_PORT_4 + 21)) 7606 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 7607 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7608 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7609 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 7610 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 7611 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7612 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 7613 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7614 7615 /* 7616 * DG1 Clocks 7617 * First registers controls the first A and B, while the second register 7618 * controls the phy C and D. The bits on these registers are the 7619 * same, but refer to different phys 7620 */ 7621 #define _DG1_DPCLKA_CFGCR0 0x164280 7622 #define _DG1_DPCLKA1_CFGCR0 0x16C280 7623 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 7624 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 7625 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 7626 _DG1_DPCLKA_CFGCR0, \ 7627 _DG1_DPCLKA1_CFGCR0) 7628 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 7629 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 7630 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7631 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7632 7633 /* ADLS Clocks */ 7634 #define _ADLS_DPCLKA_CFGCR0 0x164280 7635 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 7636 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 7637 _ADLS_DPCLKA_CFGCR0, \ 7638 _ADLS_DPCLKA_CFGCR1) 7639 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 7640 /* ADLS DPCLKA_CFGCR0 DDI mask */ 7641 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 7642 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 7643 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 7644 /* ADLS DPCLKA_CFGCR1 DDI mask */ 7645 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 7646 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 7647 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 7648 ADLS_DPCLKA_DDIA_SEL_MASK, \ 7649 ADLS_DPCLKA_DDIB_SEL_MASK, \ 7650 ADLS_DPCLKA_DDII_SEL_MASK, \ 7651 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 7652 ADLS_DPCLKA_DDIK_SEL_MASK) 7653 7654 /* ICL PLL */ 7655 #define DPLL0_ENABLE 0x46010 7656 #define DPLL1_ENABLE 0x46014 7657 #define _ADLS_DPLL2_ENABLE 0x46018 7658 #define _ADLS_DPLL3_ENABLE 0x46030 7659 #define PLL_ENABLE (1 << 31) 7660 #define PLL_LOCK (1 << 30) 7661 #define PLL_POWER_ENABLE (1 << 27) 7662 #define PLL_POWER_STATE (1 << 26) 7663 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7664 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) 7665 7666 #define _DG2_PLL3_ENABLE 0x4601C 7667 7668 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7669 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) 7670 7671 #define TBT_PLL_ENABLE _MMIO(0x46020) 7672 7673 #define _MG_PLL1_ENABLE 0x46030 7674 #define _MG_PLL2_ENABLE 0x46034 7675 #define _MG_PLL3_ENABLE 0x46038 7676 #define _MG_PLL4_ENABLE 0x4603C 7677 /* Bits are the same as DPLL0_ENABLE */ 7678 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 7679 _MG_PLL2_ENABLE) 7680 7681 /* DG1 PLL */ 7682 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7683 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) 7684 7685 /* ADL-P Type C PLL */ 7686 #define PORTTC1_PLL_ENABLE 0x46038 7687 #define PORTTC2_PLL_ENABLE 0x46040 7688 7689 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 7690 PORTTC1_PLL_ENABLE, \ 7691 PORTTC2_PLL_ENABLE) 7692 7693 #define _ICL_DPLL0_CFGCR0 0x164000 7694 #define _ICL_DPLL1_CFGCR0 0x164080 7695 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 7696 _ICL_DPLL1_CFGCR0) 7697 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 7698 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 7699 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 7700 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 7701 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 7702 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 7703 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 7704 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 7705 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 7706 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 7707 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 7708 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 7709 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 7710 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 7711 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 7712 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 7713 7714 #define _ICL_DPLL0_CFGCR1 0x164004 7715 #define _ICL_DPLL1_CFGCR1 0x164084 7716 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 7717 _ICL_DPLL1_CFGCR1) 7718 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 7719 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 7720 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 7721 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 7722 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 7723 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 7724 #define DPLL_CFGCR1_KDIV_SHIFT (6) 7725 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 7726 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 7727 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 7728 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 7729 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 7730 #define DPLL_CFGCR1_PDIV_SHIFT (2) 7731 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 7732 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 7733 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 7734 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 7735 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 7736 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 7737 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 7738 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 7739 7740 #define _TGL_DPLL0_CFGCR0 0x164284 7741 #define _TGL_DPLL1_CFGCR0 0x16428C 7742 #define _TGL_TBTPLL_CFGCR0 0x16429C 7743 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7744 _TGL_DPLL1_CFGCR0, \ 7745 _TGL_TBTPLL_CFGCR0) 7746 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 7747 _TGL_DPLL1_CFGCR0) 7748 7749 #define _TGL_DPLL0_DIV0 0x164B00 7750 #define _TGL_DPLL1_DIV0 0x164C00 7751 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 7752 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7753 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 7754 7755 #define _TGL_DPLL0_CFGCR1 0x164288 7756 #define _TGL_DPLL1_CFGCR1 0x164290 7757 #define _TGL_TBTPLL_CFGCR1 0x1642A0 7758 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7759 _TGL_DPLL1_CFGCR1, \ 7760 _TGL_TBTPLL_CFGCR1) 7761 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 7762 _TGL_DPLL1_CFGCR1) 7763 7764 #define _DG1_DPLL2_CFGCR0 0x16C284 7765 #define _DG1_DPLL3_CFGCR0 0x16C28C 7766 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7767 _TGL_DPLL1_CFGCR0, \ 7768 _DG1_DPLL2_CFGCR0, \ 7769 _DG1_DPLL3_CFGCR0) 7770 7771 #define _DG1_DPLL2_CFGCR1 0x16C288 7772 #define _DG1_DPLL3_CFGCR1 0x16C290 7773 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7774 _TGL_DPLL1_CFGCR1, \ 7775 _DG1_DPLL2_CFGCR1, \ 7776 _DG1_DPLL3_CFGCR1) 7777 7778 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 7779 #define _ADLS_DPLL3_CFGCR0 0x1642C0 7780 #define _ADLS_DPLL4_CFGCR0 0x164294 7781 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7782 _TGL_DPLL1_CFGCR0, \ 7783 _ADLS_DPLL4_CFGCR0, \ 7784 _ADLS_DPLL3_CFGCR0) 7785 7786 #define _ADLS_DPLL3_CFGCR1 0x1642C4 7787 #define _ADLS_DPLL4_CFGCR1 0x164298 7788 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7789 _TGL_DPLL1_CFGCR1, \ 7790 _ADLS_DPLL4_CFGCR1, \ 7791 _ADLS_DPLL3_CFGCR1) 7792 7793 #define _DKL_PHY1_BASE 0x168000 7794 #define _DKL_PHY2_BASE 0x169000 7795 #define _DKL_PHY3_BASE 0x16A000 7796 #define _DKL_PHY4_BASE 0x16B000 7797 #define _DKL_PHY5_BASE 0x16C000 7798 #define _DKL_PHY6_BASE 0x16D000 7799 7800 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ 7801 #define _DKL_PCS_DW5 0x14 7802 #define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7803 _DKL_PHY2_BASE) + \ 7804 _DKL_PCS_DW5) 7805 #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) 7806 7807 #define _DKL_PLL_DIV0 0x200 7808 #define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7809 #define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) 7810 #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) 7811 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) 7812 #define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) 7813 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) 7814 #define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) 7815 #define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) 7816 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) 7817 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 7818 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) 7819 #define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ 7820 DKL_PLL_DIV0_PROP_COEFF_MASK | \ 7821 DKL_PLL_DIV0_FBPREDIV_MASK | \ 7822 DKL_PLL_DIV0_FBDIV_INT_MASK) 7823 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7824 _DKL_PHY2_BASE) + \ 7825 _DKL_PLL_DIV0) 7826 7827 #define _DKL_PLL_DIV1 0x204 7828 #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) 7829 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) 7830 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) 7831 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) 7832 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7833 _DKL_PHY2_BASE) + \ 7834 _DKL_PLL_DIV1) 7835 7836 #define _DKL_PLL_SSC 0x210 7837 #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) 7838 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) 7839 #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) 7840 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) 7841 #define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) 7842 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) 7843 #define DKL_PLL_SSC_EN (1 << 9) 7844 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7845 _DKL_PHY2_BASE) + \ 7846 _DKL_PLL_SSC) 7847 7848 #define _DKL_PLL_BIAS 0x214 7849 #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) 7850 #define DKL_PLL_BIAS_FBDIV_SHIFT (8) 7851 #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) 7852 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) 7853 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7854 _DKL_PHY2_BASE) + \ 7855 _DKL_PLL_BIAS) 7856 7857 #define _DKL_PLL_TDC_COLDST_BIAS 0x218 7858 #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) 7859 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) 7860 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) 7861 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) 7862 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ 7863 _DKL_PHY1_BASE, \ 7864 _DKL_PHY2_BASE) + \ 7865 _DKL_PLL_TDC_COLDST_BIAS) 7866 7867 #define _DKL_REFCLKIN_CTL 0x12C 7868 /* Bits are the same as MG_REFCLKIN_CTL */ 7869 #define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ 7870 _DKL_PHY1_BASE, \ 7871 _DKL_PHY2_BASE) + \ 7872 _DKL_REFCLKIN_CTL) 7873 7874 #define _DKL_CLKTOP2_HSCLKCTL 0xD4 7875 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ 7876 #define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ 7877 _DKL_PHY1_BASE, \ 7878 _DKL_PHY2_BASE) + \ 7879 _DKL_CLKTOP2_HSCLKCTL) 7880 7881 #define _DKL_CLKTOP2_CORECLKCTL1 0xD8 7882 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ 7883 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ 7884 _DKL_PHY1_BASE, \ 7885 _DKL_PHY2_BASE) + \ 7886 _DKL_CLKTOP2_CORECLKCTL1) 7887 7888 #define _DKL_TX_DPCNTL0 0x2C0 7889 #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) 7890 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) 7891 #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) 7892 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) 7893 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) 7894 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) 7895 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ 7896 _DKL_PHY1_BASE, \ 7897 _DKL_PHY2_BASE) + \ 7898 _DKL_TX_DPCNTL0) 7899 7900 #define _DKL_TX_DPCNTL1 0x2C4 7901 /* Bits are the same as DKL_TX_DPCNTRL0 */ 7902 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ 7903 _DKL_PHY1_BASE, \ 7904 _DKL_PHY2_BASE) + \ 7905 _DKL_TX_DPCNTL1) 7906 7907 #define _DKL_TX_DPCNTL2 0x2C8 7908 #define DKL_TX_DP20BITMODE REG_BIT(2) 7909 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) 7910 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) 7911 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) 7912 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) 7913 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ 7914 _DKL_PHY1_BASE, \ 7915 _DKL_PHY2_BASE) + \ 7916 _DKL_TX_DPCNTL2) 7917 7918 #define _DKL_TX_FW_CALIB 0x2F8 7919 #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) 7920 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ 7921 _DKL_PHY1_BASE, \ 7922 _DKL_PHY2_BASE) + \ 7923 _DKL_TX_FW_CALIB) 7924 7925 #define _DKL_TX_PMD_LANE_SUS 0xD00 7926 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ 7927 _DKL_PHY1_BASE, \ 7928 _DKL_PHY2_BASE) + \ 7929 _DKL_TX_PMD_LANE_SUS) 7930 7931 #define _DKL_TX_DW17 0xDC4 7932 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ 7933 _DKL_PHY1_BASE, \ 7934 _DKL_PHY2_BASE) + \ 7935 _DKL_TX_DW17) 7936 7937 #define _DKL_TX_DW18 0xDC8 7938 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ 7939 _DKL_PHY1_BASE, \ 7940 _DKL_PHY2_BASE) + \ 7941 _DKL_TX_DW18) 7942 7943 #define _DKL_DP_MODE 0xA0 7944 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ 7945 _DKL_PHY1_BASE, \ 7946 _DKL_PHY2_BASE) + \ 7947 _DKL_DP_MODE) 7948 7949 #define _DKL_CMN_UC_DW27 0x36C 7950 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) 7951 #define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ 7952 _DKL_PHY1_BASE, \ 7953 _DKL_PHY2_BASE) + \ 7954 _DKL_CMN_UC_DW27) 7955 7956 /* 7957 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than 7958 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 7959 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address 7960 * bits that point the 4KB window into the full PHY register space. 7961 */ 7962 #define _HIP_INDEX_REG0 0x1010A0 7963 #define _HIP_INDEX_REG1 0x1010A4 7964 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ 7965 : _HIP_INDEX_REG1) 7966 #define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) 7967 #define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) 7968 7969 /* BXT display engine PLL */ 7970 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 7971 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7972 #define BXT_DE_PLL_RATIO_MASK 0xff 7973 7974 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 7975 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7976 #define BXT_DE_PLL_LOCK (1 << 30) 7977 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 7978 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 7979 #define ICL_CDCLK_PLL_RATIO(x) (x) 7980 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 7981 7982 /* GEN9 DC */ 7983 #define DC_STATE_EN _MMIO(0x45504) 7984 #define DC_STATE_DISABLE 0 7985 #define DC_STATE_EN_DC3CO REG_BIT(30) 7986 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 7987 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 7988 #define DC_STATE_EN_DC9 (1 << 3) 7989 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 7990 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7991 7992 #define DC_STATE_DEBUG _MMIO(0x45520) 7993 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 7994 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 7995 7996 #define D_COMP_BDW _MMIO(0x138144) 7997 7998 /* Pipe WM_LINETIME - watermark line time */ 7999 #define _WM_LINETIME_A 0x45270 8000 #define _WM_LINETIME_B 0x45274 8001 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 8002 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 8003 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 8004 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 8005 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 8006 8007 /* SFUSE_STRAP */ 8008 #define SFUSE_STRAP _MMIO(0xc2014) 8009 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 8010 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 8011 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 8012 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 8013 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 8014 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 8015 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 8016 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 8017 8018 #define WM_MISC _MMIO(0x45260) 8019 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 8020 8021 #define WM_DBG _MMIO(0x45280) 8022 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 8023 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 8024 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 8025 8026 /* pipe CSC */ 8027 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 8028 #define _PIPE_A_CSC_COEFF_BY 0x49014 8029 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 8030 #define _PIPE_A_CSC_COEFF_BU 0x4901c 8031 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 8032 #define _PIPE_A_CSC_COEFF_BV 0x49024 8033 8034 #define _PIPE_A_CSC_MODE 0x49028 8035 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 8036 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 8037 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 8038 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 8039 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 8040 8041 #define _PIPE_A_CSC_PREOFF_HI 0x49030 8042 #define _PIPE_A_CSC_PREOFF_ME 0x49034 8043 #define _PIPE_A_CSC_PREOFF_LO 0x49038 8044 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 8045 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 8046 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 8047 8048 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 8049 #define _PIPE_B_CSC_COEFF_BY 0x49114 8050 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 8051 #define _PIPE_B_CSC_COEFF_BU 0x4911c 8052 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 8053 #define _PIPE_B_CSC_COEFF_BV 0x49124 8054 #define _PIPE_B_CSC_MODE 0x49128 8055 #define _PIPE_B_CSC_PREOFF_HI 0x49130 8056 #define _PIPE_B_CSC_PREOFF_ME 0x49134 8057 #define _PIPE_B_CSC_PREOFF_LO 0x49138 8058 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 8059 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 8060 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 8061 8062 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 8063 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 8064 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 8065 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 8066 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 8067 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 8068 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 8069 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 8070 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 8071 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 8072 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 8073 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 8074 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 8075 8076 /* Pipe Output CSC */ 8077 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 8078 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 8079 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 8080 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 8081 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 8082 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 8083 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 8084 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 8085 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 8086 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 8087 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 8088 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 8089 8090 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 8091 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 8092 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 8093 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 8094 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 8095 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 8096 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 8097 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 8098 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 8099 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 8100 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 8101 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 8102 8103 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 8104 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 8105 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 8106 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 8107 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 8108 _PIPE_B_OUTPUT_CSC_COEFF_BY) 8109 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 8110 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 8111 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 8112 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 8113 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 8114 _PIPE_B_OUTPUT_CSC_COEFF_BU) 8115 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 8116 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 8117 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 8118 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 8119 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 8120 _PIPE_B_OUTPUT_CSC_COEFF_BV) 8121 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 8122 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 8123 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 8124 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 8125 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 8126 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 8127 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 8128 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 8129 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 8130 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 8131 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 8132 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 8133 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 8134 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 8135 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 8136 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 8137 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 8138 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 8139 8140 /* pipe degamma/gamma LUTs on IVB+ */ 8141 #define _PAL_PREC_INDEX_A 0x4A400 8142 #define _PAL_PREC_INDEX_B 0x4AC00 8143 #define _PAL_PREC_INDEX_C 0x4B400 8144 #define PAL_PREC_10_12_BIT (0 << 31) 8145 #define PAL_PREC_SPLIT_MODE (1 << 31) 8146 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 8147 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 8148 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 8149 #define _PAL_PREC_DATA_A 0x4A404 8150 #define _PAL_PREC_DATA_B 0x4AC04 8151 #define _PAL_PREC_DATA_C 0x4B404 8152 #define _PAL_PREC_GC_MAX_A 0x4A410 8153 #define _PAL_PREC_GC_MAX_B 0x4AC10 8154 #define _PAL_PREC_GC_MAX_C 0x4B410 8155 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 8156 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 8157 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 8158 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 8159 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 8160 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 8161 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 8162 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 8163 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 8164 8165 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 8166 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 8167 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 8168 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 8169 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 8170 8171 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 8172 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 8173 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 8174 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 8175 #define _PRE_CSC_GAMC_DATA_A 0x4A488 8176 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 8177 #define _PRE_CSC_GAMC_DATA_C 0x4B488 8178 8179 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 8180 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 8181 8182 /* ICL Multi segmented gamma */ 8183 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 8184 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 8185 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 8186 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 8187 8188 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 8189 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 8190 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 8191 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 8192 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 8193 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 8194 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 8195 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 8196 8197 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 8198 _PAL_PREC_MULTI_SEG_INDEX_A, \ 8199 _PAL_PREC_MULTI_SEG_INDEX_B) 8200 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 8201 _PAL_PREC_MULTI_SEG_DATA_A, \ 8202 _PAL_PREC_MULTI_SEG_DATA_B) 8203 8204 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 8205 8206 /* Plane CSC Registers */ 8207 #define _PLANE_CSC_RY_GY_1_A 0x70210 8208 #define _PLANE_CSC_RY_GY_2_A 0x70310 8209 8210 #define _PLANE_CSC_RY_GY_1_B 0x71210 8211 #define _PLANE_CSC_RY_GY_2_B 0x71310 8212 8213 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 8214 _PLANE_CSC_RY_GY_1_B) 8215 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 8216 _PLANE_INPUT_CSC_RY_GY_2_B) 8217 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 8218 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 8219 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 8220 8221 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 8222 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 8223 8224 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 8225 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 8226 8227 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 8228 _PLANE_CSC_PREOFF_HI_1_B) 8229 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 8230 _PLANE_CSC_PREOFF_HI_2_B) 8231 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 8232 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 8233 (index) * 4) 8234 8235 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 8236 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 8237 8238 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 8239 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 8240 8241 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 8242 _PLANE_CSC_POSTOFF_HI_1_B) 8243 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 8244 _PLANE_CSC_POSTOFF_HI_2_B) 8245 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 8246 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 8247 (index) * 4) 8248 8249 /* pipe CSC & degamma/gamma LUTs on CHV */ 8250 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 8251 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 8252 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 8253 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 8254 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 8255 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 8256 #define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0) 8257 #define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16) 8258 #define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0) 8259 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 8260 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 8261 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 8262 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 8263 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 8264 #define CGM_PIPE_MODE_GAMMA (1 << 2) 8265 #define CGM_PIPE_MODE_CSC (1 << 1) 8266 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 8267 8268 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 8269 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 8270 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 8271 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 8272 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 8273 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 8274 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 8275 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 8276 8277 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 8278 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 8279 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 8280 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 8281 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 8282 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 8283 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 8284 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 8285 8286 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 8287 #define GEN4_TIMESTAMP _MMIO(0x2358) 8288 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 8289 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 8290 8291 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 8292 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 8293 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 8294 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 8295 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 8296 8297 #define _PIPE_FRMTMSTMP_A 0x70048 8298 #define PIPE_FRMTMSTMP(pipe) \ 8299 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 8300 8301 /* Display Stream Splitter Control */ 8302 #define DSS_CTL1 _MMIO(0x67400) 8303 #define SPLITTER_ENABLE (1 << 31) 8304 #define JOINER_ENABLE (1 << 30) 8305 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 8306 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 8307 #define OVERLAP_PIXELS_MASK (0xf << 16) 8308 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 8309 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 8310 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 8311 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 8312 8313 #define DSS_CTL2 _MMIO(0x67404) 8314 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 8315 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 8316 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 8317 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 8318 8319 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 8320 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 8321 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8322 _ICL_PIPE_DSS_CTL1_PB, \ 8323 _ICL_PIPE_DSS_CTL1_PC) 8324 #define BIG_JOINER_ENABLE (1 << 29) 8325 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 8326 #define VGA_CENTERING_ENABLE (1 << 27) 8327 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 8328 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 8329 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 8330 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 8331 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 8332 8333 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 8334 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 8335 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8336 _ICL_PIPE_DSS_CTL2_PB, \ 8337 _ICL_PIPE_DSS_CTL2_PC) 8338 8339 #define GEN12_GSMBASE _MMIO(0x108100) 8340 #define GEN12_DSMBASE _MMIO(0x1080C0) 8341 8342 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 8343 #define SGSI_SIDECLK_DIS REG_BIT(17) 8344 #define SGGI_DIS REG_BIT(15) 8345 #define SGR_DIS REG_BIT(13) 8346 8347 #define _ICL_PHY_MISC_A 0x64C00 8348 #define _ICL_PHY_MISC_B 0x64C04 8349 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 8350 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 8351 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 8352 ICL_PHY_MISC(port)) 8353 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 8354 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 8355 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 8356 8357 /* Icelake Display Stream Compression Registers */ 8358 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 8359 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 8360 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 8361 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 8362 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 8363 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 8364 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8365 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 8366 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 8367 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8368 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 8369 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 8370 #define DSC_VBR_ENABLE (1 << 19) 8371 #define DSC_422_ENABLE (1 << 18) 8372 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 8373 #define DSC_BLOCK_PREDICTION (1 << 16) 8374 #define DSC_LINE_BUF_DEPTH_SHIFT 12 8375 #define DSC_BPC_SHIFT 8 8376 #define DSC_VER_MIN_SHIFT 4 8377 #define DSC_VER_MAJ (0x1 << 0) 8378 8379 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 8380 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 8381 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 8382 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 8383 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 8384 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 8385 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8386 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 8387 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 8388 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8389 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 8390 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 8391 #define DSC_BPP(bpp) ((bpp) << 0) 8392 8393 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 8394 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 8395 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 8396 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 8397 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 8398 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 8399 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8400 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 8401 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 8402 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8403 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 8404 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 8405 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 8406 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 8407 8408 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 8409 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 8410 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 8411 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 8412 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 8413 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 8414 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8415 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 8416 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 8417 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8418 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 8419 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 8420 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 8421 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 8422 8423 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 8424 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 8425 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 8426 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 8427 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 8428 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 8429 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8430 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 8431 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 8432 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8433 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 8434 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 8435 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 8436 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 8437 8438 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 8439 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 8440 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 8441 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 8442 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 8443 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 8444 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8445 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 8446 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 8447 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8448 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 8449 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 8450 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 8451 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 8452 8453 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 8454 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 8455 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 8456 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 8457 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 8458 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 8459 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8460 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 8461 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 8462 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8463 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 8464 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 8465 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 8466 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 8467 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 8468 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 8469 8470 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 8471 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 8472 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 8473 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 8474 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 8475 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 8476 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8477 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 8478 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 8479 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8480 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 8481 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 8482 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 8483 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 8484 8485 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 8486 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 8487 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 8488 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 8489 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 8490 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 8491 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8492 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 8493 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 8494 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8495 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 8496 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 8497 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 8498 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 8499 8500 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 8501 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 8502 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 8503 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 8504 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 8505 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 8506 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8507 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 8508 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 8509 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8510 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 8511 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 8512 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 8513 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 8514 8515 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 8516 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 8517 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 8518 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 8519 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 8520 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 8521 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8522 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 8523 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 8524 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8525 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 8526 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 8527 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 8528 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 8529 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 8530 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 8531 8532 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 8533 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 8534 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 8535 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 8536 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 8537 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 8538 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8539 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 8540 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 8541 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8542 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 8543 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 8544 8545 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 8546 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 8547 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 8548 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 8549 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 8550 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 8551 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8552 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 8553 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 8554 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8555 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 8556 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 8557 8558 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 8559 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 8560 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 8561 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 8562 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 8563 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 8564 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8565 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 8566 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 8567 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8568 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 8569 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 8570 8571 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 8572 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 8573 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 8574 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 8575 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 8576 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 8577 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8578 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 8579 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 8580 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8581 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 8582 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 8583 8584 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 8585 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 8586 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 8587 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 8588 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 8589 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 8590 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8591 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 8592 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 8593 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8594 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 8595 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 8596 8597 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 8598 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 8599 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 8600 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 8601 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 8602 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 8603 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8604 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 8605 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 8606 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8607 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 8608 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 8609 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 8610 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 8611 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 8612 8613 /* Icelake Rate Control Buffer Threshold Registers */ 8614 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 8615 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 8616 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 8617 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 8618 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 8619 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 8620 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 8621 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 8622 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 8623 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 8624 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 8625 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 8626 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8627 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 8628 _ICL_DSC0_RC_BUF_THRESH_0_PC) 8629 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8630 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 8631 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 8632 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8633 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 8634 _ICL_DSC1_RC_BUF_THRESH_0_PC) 8635 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8636 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 8637 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 8638 8639 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 8640 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 8641 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 8642 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 8643 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 8644 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 8645 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 8646 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 8647 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 8648 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 8649 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 8650 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 8651 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8652 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 8653 _ICL_DSC0_RC_BUF_THRESH_1_PC) 8654 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8655 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 8656 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 8657 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8658 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 8659 _ICL_DSC1_RC_BUF_THRESH_1_PC) 8660 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8661 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 8662 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 8663 8664 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 8665 #define MODULAR_FIA_MASK (1 << 4) 8666 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 8667 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 8668 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 8669 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 8670 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 8671 8672 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 8673 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 8674 8675 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 8676 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 8677 8678 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 8679 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 8680 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 8681 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 8682 8683 #define _TCSS_DDI_STATUS_1 0x161500 8684 #define _TCSS_DDI_STATUS_2 0x161504 8685 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 8686 _TCSS_DDI_STATUS_1, \ 8687 _TCSS_DDI_STATUS_2)) 8688 #define TCSS_DDI_STATUS_READY REG_BIT(2) 8689 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 8690 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 8691 8692 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 8693 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 8694 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 8695 #define SPI_STATIC_REGIONS _MMIO(0x102090) 8696 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 8697 #define OROM_OFFSET _MMIO(0x1020c0) 8698 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 8699 8700 /* This register controls the Display State Buffer (DSB) engines. */ 8701 #define _DSBSL_INSTANCE_BASE 0x70B00 8702 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 8703 (pipe) * 0x1000 + (id) * 0x100) 8704 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 8705 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 8706 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 8707 #define DSB_ENABLE (1 << 31) 8708 #define DSB_STATUS (1 << 0) 8709 8710 #define CLKREQ_POLICY _MMIO(0x101038) 8711 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 8712 8713 #define CLKGATE_DIS_MISC _MMIO(0x46534) 8714 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 8715 8716 #define GEN12_CULLBIT1 _MMIO(0x6100) 8717 #define GEN12_CULLBIT2 _MMIO(0x7030) 8718 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) 8719 8720 #endif /* _I915_REG_H_ */ 8721