1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 typedef struct { 29 uint32_t reg; 30 } i915_reg_t; 31 32 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 33 34 #define INVALID_MMIO_REG _MMIO(0) 35 36 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) 37 { 38 return reg.reg; 39 } 40 41 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 42 { 43 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 44 } 45 46 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 47 { 48 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 49 } 50 51 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 52 53 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 54 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 55 #define _PLANE(plane, a, b) _PIPE(plane, a, b) 56 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) 57 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a))) 58 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 59 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 60 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 61 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 62 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 63 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) 64 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 65 #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f)) 66 #define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \ 67 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) 68 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 69 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 70 71 #define _MASKED_FIELD(mask, value) ({ \ 72 if (__builtin_constant_p(mask)) \ 73 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 74 if (__builtin_constant_p(value)) \ 75 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 76 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 77 BUILD_BUG_ON_MSG((value) & ~(mask), \ 78 "Incorrect value for mask"); \ 79 (mask) << 16 | (value); }) 80 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 81 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 82 83 /* Engine ID */ 84 85 #define RCS_HW 0 86 #define VCS_HW 1 87 #define BCS_HW 2 88 #define VECS_HW 3 89 #define VCS2_HW 4 90 91 /* Engine class */ 92 93 #define RENDER_CLASS 0 94 #define VIDEO_DECODE_CLASS 1 95 #define VIDEO_ENHANCEMENT_CLASS 2 96 #define COPY_ENGINE_CLASS 3 97 #define OTHER_CLASS 4 98 99 /* PCI config space */ 100 101 #define MCHBAR_I915 0x44 102 #define MCHBAR_I965 0x48 103 #define MCHBAR_SIZE (4 * 4096) 104 105 #define DEVEN 0x54 106 #define DEVEN_MCHBAR_EN (1 << 28) 107 108 /* BSM in include/drm/i915_drm.h */ 109 110 #define HPLLCC 0xc0 /* 85x only */ 111 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 112 #define GC_CLOCK_133_200 (0 << 0) 113 #define GC_CLOCK_100_200 (1 << 0) 114 #define GC_CLOCK_100_133 (2 << 0) 115 #define GC_CLOCK_133_266 (3 << 0) 116 #define GC_CLOCK_133_200_2 (4 << 0) 117 #define GC_CLOCK_133_266_2 (5 << 0) 118 #define GC_CLOCK_166_266 (6 << 0) 119 #define GC_CLOCK_166_250 (7 << 0) 120 121 #define I915_GDRST 0xc0 /* PCI config register */ 122 #define GRDOM_FULL (0 << 2) 123 #define GRDOM_RENDER (1 << 2) 124 #define GRDOM_MEDIA (3 << 2) 125 #define GRDOM_MASK (3 << 2) 126 #define GRDOM_RESET_STATUS (1 << 1) 127 #define GRDOM_RESET_ENABLE (1 << 0) 128 129 /* BSpec only has register offset, PCI device and bit found empirically */ 130 #define I830_CLOCK_GATE 0xc8 /* device 0 */ 131 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 132 133 #define GCDGMBUS 0xcc 134 135 #define GCFGC2 0xda 136 #define GCFGC 0xf0 /* 915+ only */ 137 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 138 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 139 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 140 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 141 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 142 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 143 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 144 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 145 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 146 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 147 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 148 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 149 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 150 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 151 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 152 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 153 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 154 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 155 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 156 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 157 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 158 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 159 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 160 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 161 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 162 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 163 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 164 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 165 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 166 167 #define ASLE 0xe4 168 #define ASLS 0xfc 169 170 #define SWSCI 0xe8 171 #define SWSCI_SCISEL (1 << 15) 172 #define SWSCI_GSSCIE (1 << 0) 173 174 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 175 176 177 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 178 #define ILK_GRDOM_FULL (0<<1) 179 #define ILK_GRDOM_RENDER (1<<1) 180 #define ILK_GRDOM_MEDIA (3<<1) 181 #define ILK_GRDOM_MASK (3<<1) 182 #define ILK_GRDOM_RESET_ENABLE (1<<0) 183 184 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 185 #define GEN6_MBC_SNPCR_SHIFT 21 186 #define GEN6_MBC_SNPCR_MASK (3<<21) 187 #define GEN6_MBC_SNPCR_MAX (0<<21) 188 #define GEN6_MBC_SNPCR_MED (1<<21) 189 #define GEN6_MBC_SNPCR_LOW (2<<21) 190 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 191 192 #define VLV_G3DCTL _MMIO(0x9024) 193 #define VLV_GSCKGCTL _MMIO(0x9028) 194 195 #define GEN6_MBCTL _MMIO(0x0907c) 196 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 197 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 198 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 199 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 200 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 201 202 #define GEN6_GDRST _MMIO(0x941c) 203 #define GEN6_GRDOM_FULL (1 << 0) 204 #define GEN6_GRDOM_RENDER (1 << 1) 205 #define GEN6_GRDOM_MEDIA (1 << 2) 206 #define GEN6_GRDOM_BLT (1 << 3) 207 #define GEN6_GRDOM_VECS (1 << 4) 208 #define GEN9_GRDOM_GUC (1 << 5) 209 #define GEN8_GRDOM_MEDIA2 (1 << 7) 210 211 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228) 212 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518) 213 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220) 214 #define PP_DIR_DCLV_2G 0xffffffff 215 216 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4) 217 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8) 218 219 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 220 #define GEN8_RPCS_ENABLE (1 << 31) 221 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 222 #define GEN8_RPCS_S_CNT_SHIFT 15 223 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 224 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 225 #define GEN8_RPCS_SS_CNT_SHIFT 8 226 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 227 #define GEN8_RPCS_EU_MAX_SHIFT 4 228 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 229 #define GEN8_RPCS_EU_MIN_SHIFT 0 230 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 231 232 #define GAM_ECOCHK _MMIO(0x4090) 233 #define BDW_DISABLE_HDC_INVALIDATION (1<<25) 234 #define ECOCHK_SNB_BIT (1<<10) 235 #define ECOCHK_DIS_TLB (1<<8) 236 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 237 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 238 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 239 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 240 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 241 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 242 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 243 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 244 245 #define GEN8_CONFIG0 _MMIO(0xD00) 246 #define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1) 247 248 #define GAC_ECO_BITS _MMIO(0x14090) 249 #define ECOBITS_SNB_BIT (1<<13) 250 #define ECOBITS_PPGTT_CACHE64B (3<<8) 251 #define ECOBITS_PPGTT_CACHE4B (0<<8) 252 253 #define GAB_CTL _MMIO(0x24000) 254 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 255 256 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 257 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 258 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 259 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 260 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 261 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 262 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 263 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 264 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 265 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 266 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 267 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 268 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 269 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 270 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 271 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 272 273 /* VGA stuff */ 274 275 #define VGA_ST01_MDA 0x3ba 276 #define VGA_ST01_CGA 0x3da 277 278 #define _VGA_MSR_WRITE _MMIO(0x3c2) 279 #define VGA_MSR_WRITE 0x3c2 280 #define VGA_MSR_READ 0x3cc 281 #define VGA_MSR_MEM_EN (1<<1) 282 #define VGA_MSR_CGA_MODE (1<<0) 283 284 #define VGA_SR_INDEX 0x3c4 285 #define SR01 1 286 #define VGA_SR_DATA 0x3c5 287 288 #define VGA_AR_INDEX 0x3c0 289 #define VGA_AR_VID_EN (1<<5) 290 #define VGA_AR_DATA_WRITE 0x3c0 291 #define VGA_AR_DATA_READ 0x3c1 292 293 #define VGA_GR_INDEX 0x3ce 294 #define VGA_GR_DATA 0x3cf 295 /* GR05 */ 296 #define VGA_GR_MEM_READ_MODE_SHIFT 3 297 #define VGA_GR_MEM_READ_MODE_PLANE 1 298 /* GR06 */ 299 #define VGA_GR_MEM_MODE_MASK 0xc 300 #define VGA_GR_MEM_MODE_SHIFT 2 301 #define VGA_GR_MEM_A0000_AFFFF 0 302 #define VGA_GR_MEM_A0000_BFFFF 1 303 #define VGA_GR_MEM_B0000_B7FFF 2 304 #define VGA_GR_MEM_B0000_BFFFF 3 305 306 #define VGA_DACMASK 0x3c6 307 #define VGA_DACRX 0x3c7 308 #define VGA_DACWX 0x3c8 309 #define VGA_DACDATA 0x3c9 310 311 #define VGA_CR_INDEX_MDA 0x3b4 312 #define VGA_CR_DATA_MDA 0x3b5 313 #define VGA_CR_INDEX_CGA 0x3d4 314 #define VGA_CR_DATA_CGA 0x3d5 315 316 /* 317 * Instruction field definitions used by the command parser 318 */ 319 #define INSTR_CLIENT_SHIFT 29 320 #define INSTR_MI_CLIENT 0x0 321 #define INSTR_BC_CLIENT 0x2 322 #define INSTR_RC_CLIENT 0x3 323 #define INSTR_SUBCLIENT_SHIFT 27 324 #define INSTR_SUBCLIENT_MASK 0x18000000 325 #define INSTR_MEDIA_SUBCLIENT 0x2 326 #define INSTR_26_TO_24_MASK 0x7000000 327 #define INSTR_26_TO_24_SHIFT 24 328 329 /* 330 * Memory interface instructions used by the kernel 331 */ 332 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 333 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 334 #define MI_GLOBAL_GTT (1<<22) 335 336 #define MI_NOOP MI_INSTR(0, 0) 337 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 338 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 339 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 340 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 341 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 342 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 343 #define MI_FLUSH MI_INSTR(0x04, 0) 344 #define MI_READ_FLUSH (1 << 0) 345 #define MI_EXE_FLUSH (1 << 1) 346 #define MI_NO_WRITE_FLUSH (1 << 2) 347 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 348 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 349 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 350 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 351 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 352 #define MI_ARB_ENABLE (1<<0) 353 #define MI_ARB_DISABLE (0<<0) 354 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 355 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 356 #define MI_SUSPEND_FLUSH_EN (1<<0) 357 #define MI_SET_APPID MI_INSTR(0x0e, 0) 358 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 359 #define MI_OVERLAY_CONTINUE (0x0<<21) 360 #define MI_OVERLAY_ON (0x1<<21) 361 #define MI_OVERLAY_OFF (0x2<<21) 362 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 363 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 364 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 365 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 366 /* IVB has funny definitions for which plane to flip. */ 367 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 368 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 369 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 370 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 371 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 372 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 373 /* SKL ones */ 374 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 375 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 376 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 377 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 378 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 379 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 380 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 381 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 382 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 383 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 384 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 385 #define MI_SEMAPHORE_UPDATE (1<<21) 386 #define MI_SEMAPHORE_COMPARE (1<<20) 387 #define MI_SEMAPHORE_REGISTER (1<<18) 388 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 389 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 390 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 391 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 392 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 393 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 394 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 395 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 396 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 397 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 398 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 399 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 400 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 401 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 402 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 403 #define MI_MM_SPACE_GTT (1<<8) 404 #define MI_MM_SPACE_PHYSICAL (0<<8) 405 #define MI_SAVE_EXT_STATE_EN (1<<3) 406 #define MI_RESTORE_EXT_STATE_EN (1<<2) 407 #define MI_FORCE_RESTORE (1<<1) 408 #define MI_RESTORE_INHIBIT (1<<0) 409 #define HSW_MI_RS_SAVE_STATE_EN (1<<3) 410 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) 411 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 412 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 413 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 414 #define MI_SEMAPHORE_POLL (1<<15) 415 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 416 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 417 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) 418 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ 419 #define MI_USE_GGTT (1 << 22) /* g4x+ */ 420 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 421 #define MI_STORE_DWORD_INDEX_SHIFT 2 422 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 423 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 424 * simply ignores the register load under certain conditions. 425 * - One can actually load arbitrary many arbitrary registers: Simply issue x 426 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 427 */ 428 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 429 #define MI_LRI_FORCE_POSTED (1<<12) 430 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) 431 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) 432 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 433 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 434 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 435 #define MI_INVALIDATE_TLB (1<<18) 436 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 437 #define MI_FLUSH_DW_OP_MASK (3<<14) 438 #define MI_FLUSH_DW_NOTIFY (1<<8) 439 #define MI_INVALIDATE_BSD (1<<7) 440 #define MI_FLUSH_DW_USE_GTT (1<<2) 441 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 442 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) 443 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) 444 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 445 #define MI_BATCH_NON_SECURE (1) 446 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 447 #define MI_BATCH_NON_SECURE_I965 (1<<8) 448 #define MI_BATCH_PPGTT_HSW (1<<8) 449 #define MI_BATCH_NON_SECURE_HSW (1<<13) 450 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 451 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 452 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 453 #define MI_BATCH_RESOURCE_STREAMER (1<<10) 454 455 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 456 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 457 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 458 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 459 460 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 461 #define LOWER_SLICE_ENABLED (1<<0) 462 #define LOWER_SLICE_DISABLED (0<<0) 463 464 /* 465 * 3D instructions used by the kernel 466 */ 467 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 468 469 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) 470 #define GEN9_MEDIA_POOL_ENABLE (1 << 31) 471 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 472 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 473 #define SC_UPDATE_SCISSOR (0x1<<1) 474 #define SC_ENABLE_MASK (0x1<<0) 475 #define SC_ENABLE (0x1<<0) 476 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 477 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 478 #define SCI_YMIN_MASK (0xffff<<16) 479 #define SCI_XMIN_MASK (0xffff<<0) 480 #define SCI_YMAX_MASK (0xffff<<16) 481 #define SCI_XMAX_MASK (0xffff<<0) 482 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 483 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 484 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 485 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 486 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 487 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 488 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 489 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 490 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 491 492 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 493 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 494 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 495 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 496 #define BLT_WRITE_A (2<<20) 497 #define BLT_WRITE_RGB (1<<20) 498 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 499 #define BLT_DEPTH_8 (0<<24) 500 #define BLT_DEPTH_16_565 (1<<24) 501 #define BLT_DEPTH_16_1555 (2<<24) 502 #define BLT_DEPTH_32 (3<<24) 503 #define BLT_ROP_SRC_COPY (0xcc<<16) 504 #define BLT_ROP_COLOR_COPY (0xf0<<16) 505 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 506 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 507 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 508 #define ASYNC_FLIP (1<<22) 509 #define DISPLAY_PLANE_A (0<<20) 510 #define DISPLAY_PLANE_B (1<<20) 511 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) 512 #define PIPE_CONTROL_FLUSH_L3 (1<<27) 513 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 514 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 515 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 516 #define PIPE_CONTROL_CS_STALL (1<<20) 517 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 518 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 519 #define PIPE_CONTROL_QW_WRITE (1<<14) 520 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 521 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 522 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 523 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 524 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 525 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 526 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 527 #define PIPE_CONTROL_NOTIFY (1<<8) 528 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 529 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) 530 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 531 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 532 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 533 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 534 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 535 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 536 537 /* 538 * Commands used only by the command parser 539 */ 540 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 541 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 542 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 543 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 544 #define MI_PREDICATE MI_INSTR(0x0C, 0) 545 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 546 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 547 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 548 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 549 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 550 #define MI_CLFLUSH MI_INSTR(0x27, 0) 551 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 552 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 553 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 554 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 555 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 556 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 557 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 558 559 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 560 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 561 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 562 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 563 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 564 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 565 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 566 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 567 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 568 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 569 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 570 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 571 572 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 573 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 574 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 575 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 576 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 577 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 578 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 579 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 580 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 581 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 582 583 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 584 585 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 586 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 587 588 /* 589 * Registers used only by the command parser 590 */ 591 #define BCS_SWCTRL _MMIO(0x22200) 592 593 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 594 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 595 #define HS_INVOCATION_COUNT _MMIO(0x2300) 596 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 597 #define DS_INVOCATION_COUNT _MMIO(0x2308) 598 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 599 #define IA_VERTICES_COUNT _MMIO(0x2310) 600 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 601 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 602 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 603 #define VS_INVOCATION_COUNT _MMIO(0x2320) 604 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 605 #define GS_INVOCATION_COUNT _MMIO(0x2328) 606 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 607 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 608 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 609 #define CL_INVOCATION_COUNT _MMIO(0x2338) 610 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 611 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 612 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 613 #define PS_INVOCATION_COUNT _MMIO(0x2348) 614 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 615 #define PS_DEPTH_COUNT _MMIO(0x2350) 616 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 617 618 /* There are the 4 64-bit counter registers, one for each stream output */ 619 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 620 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 621 622 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 623 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 624 625 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 626 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 627 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 628 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 629 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 630 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 631 632 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 633 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 634 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 635 636 /* There are the 16 64-bit CS General Purpose Registers */ 637 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 638 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 639 640 #define GEN7_OACONTROL _MMIO(0x2360) 641 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 642 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 643 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 644 #define GEN7_OACONTROL_TIMER_ENABLE (1<<5) 645 #define GEN7_OACONTROL_FORMAT_A13 (0<<2) 646 #define GEN7_OACONTROL_FORMAT_A29 (1<<2) 647 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2) 648 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2) 649 #define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2) 650 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2) 651 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2) 652 #define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2) 653 #define GEN7_OACONTROL_FORMAT_SHIFT 2 654 #define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1) 655 #define GEN7_OACONTROL_ENABLE (1<<0) 656 657 #define GEN8_OACTXID _MMIO(0x2364) 658 659 #define GEN8_OA_DEBUG _MMIO(0x2B04) 660 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5) 661 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6) 662 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2) 663 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1) 664 665 #define GEN8_OACONTROL _MMIO(0x2B00) 666 #define GEN8_OA_REPORT_FORMAT_A12 (0<<2) 667 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2) 668 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2) 669 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2) 670 #define GEN8_OA_REPORT_FORMAT_SHIFT 2 671 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1) 672 #define GEN8_OA_COUNTER_ENABLE (1<<0) 673 674 #define GEN8_OACTXCONTROL _MMIO(0x2360) 675 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 676 #define GEN8_OA_TIMER_PERIOD_SHIFT 2 677 #define GEN8_OA_TIMER_ENABLE (1<<1) 678 #define GEN8_OA_COUNTER_RESUME (1<<0) 679 680 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 681 #define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3) 682 #define GEN7_OABUFFER_EDGE_TRIGGER (1<<2) 683 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1) 684 #define GEN7_OABUFFER_RESUME (1<<0) 685 686 #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 687 #define GEN8_OABUFFER _MMIO(0x2b14) 688 689 #define GEN7_OASTATUS1 _MMIO(0x2364) 690 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 691 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2) 692 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1) 693 #define GEN7_OASTATUS1_REPORT_LOST (1<<0) 694 695 #define GEN7_OASTATUS2 _MMIO(0x2368) 696 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 697 698 #define GEN8_OASTATUS _MMIO(0x2b08) 699 #define GEN8_OASTATUS_OVERRUN_STATUS (1<<3) 700 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2) 701 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1) 702 #define GEN8_OASTATUS_REPORT_LOST (1<<0) 703 704 #define GEN8_OAHEADPTR _MMIO(0x2B0C) 705 #define GEN8_OAHEADPTR_MASK 0xffffffc0 706 #define GEN8_OATAILPTR _MMIO(0x2B10) 707 #define GEN8_OATAILPTR_MASK 0xffffffc0 708 709 #define OABUFFER_SIZE_128K (0<<3) 710 #define OABUFFER_SIZE_256K (1<<3) 711 #define OABUFFER_SIZE_512K (2<<3) 712 #define OABUFFER_SIZE_1M (3<<3) 713 #define OABUFFER_SIZE_2M (4<<3) 714 #define OABUFFER_SIZE_4M (5<<3) 715 #define OABUFFER_SIZE_8M (6<<3) 716 #define OABUFFER_SIZE_16M (7<<3) 717 718 #define OA_MEM_SELECT_GGTT (1<<0) 719 720 /* 721 * Flexible, Aggregate EU Counter Registers. 722 * Note: these aren't contiguous 723 */ 724 #define EU_PERF_CNTL0 _MMIO(0xe458) 725 #define EU_PERF_CNTL1 _MMIO(0xe558) 726 #define EU_PERF_CNTL2 _MMIO(0xe658) 727 #define EU_PERF_CNTL3 _MMIO(0xe758) 728 #define EU_PERF_CNTL4 _MMIO(0xe45c) 729 #define EU_PERF_CNTL5 _MMIO(0xe55c) 730 #define EU_PERF_CNTL6 _MMIO(0xe65c) 731 732 #define GDT_CHICKEN_BITS _MMIO(0x9840) 733 #define GT_NOA_ENABLE 0x00000080 734 735 /* 736 * OA Boolean state 737 */ 738 739 #define OAREPORTTRIG1 _MMIO(0x2740) 740 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff 741 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 742 743 #define OAREPORTTRIG2 _MMIO(0x2744) 744 #define OAREPORTTRIG2_INVERT_A_0 (1<<0) 745 #define OAREPORTTRIG2_INVERT_A_1 (1<<1) 746 #define OAREPORTTRIG2_INVERT_A_2 (1<<2) 747 #define OAREPORTTRIG2_INVERT_A_3 (1<<3) 748 #define OAREPORTTRIG2_INVERT_A_4 (1<<4) 749 #define OAREPORTTRIG2_INVERT_A_5 (1<<5) 750 #define OAREPORTTRIG2_INVERT_A_6 (1<<6) 751 #define OAREPORTTRIG2_INVERT_A_7 (1<<7) 752 #define OAREPORTTRIG2_INVERT_A_8 (1<<8) 753 #define OAREPORTTRIG2_INVERT_A_9 (1<<9) 754 #define OAREPORTTRIG2_INVERT_A_10 (1<<10) 755 #define OAREPORTTRIG2_INVERT_A_11 (1<<11) 756 #define OAREPORTTRIG2_INVERT_A_12 (1<<12) 757 #define OAREPORTTRIG2_INVERT_A_13 (1<<13) 758 #define OAREPORTTRIG2_INVERT_A_14 (1<<14) 759 #define OAREPORTTRIG2_INVERT_A_15 (1<<15) 760 #define OAREPORTTRIG2_INVERT_B_0 (1<<16) 761 #define OAREPORTTRIG2_INVERT_B_1 (1<<17) 762 #define OAREPORTTRIG2_INVERT_B_2 (1<<18) 763 #define OAREPORTTRIG2_INVERT_B_3 (1<<19) 764 #define OAREPORTTRIG2_INVERT_C_0 (1<<20) 765 #define OAREPORTTRIG2_INVERT_C_1 (1<<21) 766 #define OAREPORTTRIG2_INVERT_D_0 (1<<22) 767 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) 768 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) 769 770 #define OAREPORTTRIG3 _MMIO(0x2748) 771 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf 772 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 773 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 774 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 775 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 776 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 777 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 778 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 779 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 780 781 #define OAREPORTTRIG4 _MMIO(0x274c) 782 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf 783 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 784 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 785 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 786 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 787 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 788 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 789 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 790 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 791 792 #define OAREPORTTRIG5 _MMIO(0x2750) 793 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff 794 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ 795 796 #define OAREPORTTRIG6 _MMIO(0x2754) 797 #define OAREPORTTRIG6_INVERT_A_0 (1<<0) 798 #define OAREPORTTRIG6_INVERT_A_1 (1<<1) 799 #define OAREPORTTRIG6_INVERT_A_2 (1<<2) 800 #define OAREPORTTRIG6_INVERT_A_3 (1<<3) 801 #define OAREPORTTRIG6_INVERT_A_4 (1<<4) 802 #define OAREPORTTRIG6_INVERT_A_5 (1<<5) 803 #define OAREPORTTRIG6_INVERT_A_6 (1<<6) 804 #define OAREPORTTRIG6_INVERT_A_7 (1<<7) 805 #define OAREPORTTRIG6_INVERT_A_8 (1<<8) 806 #define OAREPORTTRIG6_INVERT_A_9 (1<<9) 807 #define OAREPORTTRIG6_INVERT_A_10 (1<<10) 808 #define OAREPORTTRIG6_INVERT_A_11 (1<<11) 809 #define OAREPORTTRIG6_INVERT_A_12 (1<<12) 810 #define OAREPORTTRIG6_INVERT_A_13 (1<<13) 811 #define OAREPORTTRIG6_INVERT_A_14 (1<<14) 812 #define OAREPORTTRIG6_INVERT_A_15 (1<<15) 813 #define OAREPORTTRIG6_INVERT_B_0 (1<<16) 814 #define OAREPORTTRIG6_INVERT_B_1 (1<<17) 815 #define OAREPORTTRIG6_INVERT_B_2 (1<<18) 816 #define OAREPORTTRIG6_INVERT_B_3 (1<<19) 817 #define OAREPORTTRIG6_INVERT_C_0 (1<<20) 818 #define OAREPORTTRIG6_INVERT_C_1 (1<<21) 819 #define OAREPORTTRIG6_INVERT_D_0 (1<<22) 820 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) 821 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) 822 823 #define OAREPORTTRIG7 _MMIO(0x2758) 824 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf 825 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 826 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 827 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 828 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 829 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 830 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 831 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 832 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 833 834 #define OAREPORTTRIG8 _MMIO(0x275c) 835 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf 836 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 837 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 838 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 839 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 840 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 841 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 842 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 843 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 844 845 #define OASTARTTRIG1 _MMIO(0x2710) 846 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 847 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff 848 849 #define OASTARTTRIG2 _MMIO(0x2714) 850 #define OASTARTTRIG2_INVERT_A_0 (1<<0) 851 #define OASTARTTRIG2_INVERT_A_1 (1<<1) 852 #define OASTARTTRIG2_INVERT_A_2 (1<<2) 853 #define OASTARTTRIG2_INVERT_A_3 (1<<3) 854 #define OASTARTTRIG2_INVERT_A_4 (1<<4) 855 #define OASTARTTRIG2_INVERT_A_5 (1<<5) 856 #define OASTARTTRIG2_INVERT_A_6 (1<<6) 857 #define OASTARTTRIG2_INVERT_A_7 (1<<7) 858 #define OASTARTTRIG2_INVERT_A_8 (1<<8) 859 #define OASTARTTRIG2_INVERT_A_9 (1<<9) 860 #define OASTARTTRIG2_INVERT_A_10 (1<<10) 861 #define OASTARTTRIG2_INVERT_A_11 (1<<11) 862 #define OASTARTTRIG2_INVERT_A_12 (1<<12) 863 #define OASTARTTRIG2_INVERT_A_13 (1<<13) 864 #define OASTARTTRIG2_INVERT_A_14 (1<<14) 865 #define OASTARTTRIG2_INVERT_A_15 (1<<15) 866 #define OASTARTTRIG2_INVERT_B_0 (1<<16) 867 #define OASTARTTRIG2_INVERT_B_1 (1<<17) 868 #define OASTARTTRIG2_INVERT_B_2 (1<<18) 869 #define OASTARTTRIG2_INVERT_B_3 (1<<19) 870 #define OASTARTTRIG2_INVERT_C_0 (1<<20) 871 #define OASTARTTRIG2_INVERT_C_1 (1<<21) 872 #define OASTARTTRIG2_INVERT_D_0 (1<<22) 873 #define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23) 874 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24) 875 #define OASTARTTRIG2_EVENT_SELECT_0 (1<<28) 876 #define OASTARTTRIG2_EVENT_SELECT_1 (1<<29) 877 #define OASTARTTRIG2_EVENT_SELECT_2 (1<<30) 878 #define OASTARTTRIG2_EVENT_SELECT_3 (1<<31) 879 880 #define OASTARTTRIG3 _MMIO(0x2718) 881 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf 882 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 883 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 884 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 885 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 886 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 887 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 888 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 889 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 890 891 #define OASTARTTRIG4 _MMIO(0x271c) 892 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf 893 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 894 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 895 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 896 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 897 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 898 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 899 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 900 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 901 902 #define OASTARTTRIG5 _MMIO(0x2720) 903 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 904 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff 905 906 #define OASTARTTRIG6 _MMIO(0x2724) 907 #define OASTARTTRIG6_INVERT_A_0 (1<<0) 908 #define OASTARTTRIG6_INVERT_A_1 (1<<1) 909 #define OASTARTTRIG6_INVERT_A_2 (1<<2) 910 #define OASTARTTRIG6_INVERT_A_3 (1<<3) 911 #define OASTARTTRIG6_INVERT_A_4 (1<<4) 912 #define OASTARTTRIG6_INVERT_A_5 (1<<5) 913 #define OASTARTTRIG6_INVERT_A_6 (1<<6) 914 #define OASTARTTRIG6_INVERT_A_7 (1<<7) 915 #define OASTARTTRIG6_INVERT_A_8 (1<<8) 916 #define OASTARTTRIG6_INVERT_A_9 (1<<9) 917 #define OASTARTTRIG6_INVERT_A_10 (1<<10) 918 #define OASTARTTRIG6_INVERT_A_11 (1<<11) 919 #define OASTARTTRIG6_INVERT_A_12 (1<<12) 920 #define OASTARTTRIG6_INVERT_A_13 (1<<13) 921 #define OASTARTTRIG6_INVERT_A_14 (1<<14) 922 #define OASTARTTRIG6_INVERT_A_15 (1<<15) 923 #define OASTARTTRIG6_INVERT_B_0 (1<<16) 924 #define OASTARTTRIG6_INVERT_B_1 (1<<17) 925 #define OASTARTTRIG6_INVERT_B_2 (1<<18) 926 #define OASTARTTRIG6_INVERT_B_3 (1<<19) 927 #define OASTARTTRIG6_INVERT_C_0 (1<<20) 928 #define OASTARTTRIG6_INVERT_C_1 (1<<21) 929 #define OASTARTTRIG6_INVERT_D_0 (1<<22) 930 #define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23) 931 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24) 932 #define OASTARTTRIG6_EVENT_SELECT_4 (1<<28) 933 #define OASTARTTRIG6_EVENT_SELECT_5 (1<<29) 934 #define OASTARTTRIG6_EVENT_SELECT_6 (1<<30) 935 #define OASTARTTRIG6_EVENT_SELECT_7 (1<<31) 936 937 #define OASTARTTRIG7 _MMIO(0x2728) 938 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf 939 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 940 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 941 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 942 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 943 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 944 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 945 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 946 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 947 948 #define OASTARTTRIG8 _MMIO(0x272c) 949 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf 950 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 951 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 952 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 953 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 954 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 955 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 956 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 957 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 958 959 /* CECX_0 */ 960 #define OACEC_COMPARE_LESS_OR_EQUAL 6 961 #define OACEC_COMPARE_NOT_EQUAL 5 962 #define OACEC_COMPARE_LESS_THAN 4 963 #define OACEC_COMPARE_GREATER_OR_EQUAL 3 964 #define OACEC_COMPARE_EQUAL 2 965 #define OACEC_COMPARE_GREATER_THAN 1 966 #define OACEC_COMPARE_ANY_EQUAL 0 967 968 #define OACEC_COMPARE_VALUE_MASK 0xffff 969 #define OACEC_COMPARE_VALUE_SHIFT 3 970 971 #define OACEC_SELECT_NOA (0<<19) 972 #define OACEC_SELECT_PREV (1<<19) 973 #define OACEC_SELECT_BOOLEAN (2<<19) 974 975 /* CECX_1 */ 976 #define OACEC_MASK_MASK 0xffff 977 #define OACEC_CONSIDERATIONS_MASK 0xffff 978 #define OACEC_CONSIDERATIONS_SHIFT 16 979 980 #define OACEC0_0 _MMIO(0x2770) 981 #define OACEC0_1 _MMIO(0x2774) 982 #define OACEC1_0 _MMIO(0x2778) 983 #define OACEC1_1 _MMIO(0x277c) 984 #define OACEC2_0 _MMIO(0x2780) 985 #define OACEC2_1 _MMIO(0x2784) 986 #define OACEC3_0 _MMIO(0x2788) 987 #define OACEC3_1 _MMIO(0x278c) 988 #define OACEC4_0 _MMIO(0x2790) 989 #define OACEC4_1 _MMIO(0x2794) 990 #define OACEC5_0 _MMIO(0x2798) 991 #define OACEC5_1 _MMIO(0x279c) 992 #define OACEC6_0 _MMIO(0x27a0) 993 #define OACEC6_1 _MMIO(0x27a4) 994 #define OACEC7_0 _MMIO(0x27a8) 995 #define OACEC7_1 _MMIO(0x27ac) 996 997 998 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 999 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 1000 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 1001 1002 /* 1003 * Reset registers 1004 */ 1005 #define DEBUG_RESET_I830 _MMIO(0x6070) 1006 #define DEBUG_RESET_FULL (1<<7) 1007 #define DEBUG_RESET_RENDER (1<<8) 1008 #define DEBUG_RESET_DISPLAY (1<<9) 1009 1010 /* 1011 * IOSF sideband 1012 */ 1013 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 1014 #define IOSF_DEVFN_SHIFT 24 1015 #define IOSF_OPCODE_SHIFT 16 1016 #define IOSF_PORT_SHIFT 8 1017 #define IOSF_BYTE_ENABLES_SHIFT 4 1018 #define IOSF_BAR_SHIFT 1 1019 #define IOSF_SB_BUSY (1<<0) 1020 #define IOSF_PORT_BUNIT 0x03 1021 #define IOSF_PORT_PUNIT 0x04 1022 #define IOSF_PORT_NC 0x11 1023 #define IOSF_PORT_DPIO 0x12 1024 #define IOSF_PORT_GPIO_NC 0x13 1025 #define IOSF_PORT_CCK 0x14 1026 #define IOSF_PORT_DPIO_2 0x1a 1027 #define IOSF_PORT_FLISDSI 0x1b 1028 #define IOSF_PORT_GPIO_SC 0x48 1029 #define IOSF_PORT_GPIO_SUS 0xa8 1030 #define IOSF_PORT_CCU 0xa9 1031 #define CHV_IOSF_PORT_GPIO_N 0x13 1032 #define CHV_IOSF_PORT_GPIO_SE 0x48 1033 #define CHV_IOSF_PORT_GPIO_E 0xa8 1034 #define CHV_IOSF_PORT_GPIO_SW 0xb2 1035 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 1036 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 1037 1038 /* See configdb bunit SB addr map */ 1039 #define BUNIT_REG_BISOC 0x11 1040 1041 #define PUNIT_REG_DSPFREQ 0x36 1042 #define DSPFREQSTAT_SHIFT_CHV 24 1043 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 1044 #define DSPFREQGUAR_SHIFT_CHV 8 1045 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 1046 #define DSPFREQSTAT_SHIFT 30 1047 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 1048 #define DSPFREQGUAR_SHIFT 14 1049 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 1050 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 1051 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 1052 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 1053 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 1054 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 1055 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 1056 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 1057 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 1058 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 1059 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 1060 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 1061 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 1062 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 1063 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 1064 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 1065 1066 /* See the PUNIT HAS v0.8 for the below bits */ 1067 enum punit_power_well { 1068 /* These numbers are fixed and must match the position of the pw bits */ 1069 PUNIT_POWER_WELL_RENDER = 0, 1070 PUNIT_POWER_WELL_MEDIA = 1, 1071 PUNIT_POWER_WELL_DISP2D = 3, 1072 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 1073 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 1074 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 1075 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 1076 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 1077 PUNIT_POWER_WELL_DPIO_RX0 = 10, 1078 PUNIT_POWER_WELL_DPIO_RX1 = 11, 1079 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 1080 1081 /* Not actual bit groups. Used as IDs for lookup_power_well() */ 1082 PUNIT_POWER_WELL_ALWAYS_ON, 1083 }; 1084 1085 enum skl_disp_power_wells { 1086 /* These numbers are fixed and must match the position of the pw bits */ 1087 SKL_DISP_PW_MISC_IO, 1088 SKL_DISP_PW_DDI_A_E, 1089 GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, 1090 CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, 1091 SKL_DISP_PW_DDI_B, 1092 SKL_DISP_PW_DDI_C, 1093 SKL_DISP_PW_DDI_D, 1094 1095 GLK_DISP_PW_AUX_A = 8, 1096 GLK_DISP_PW_AUX_B, 1097 GLK_DISP_PW_AUX_C, 1098 CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A, 1099 CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B, 1100 CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C, 1101 CNL_DISP_PW_AUX_D, 1102 1103 SKL_DISP_PW_1 = 14, 1104 SKL_DISP_PW_2, 1105 1106 /* Not actual bit groups. Used as IDs for lookup_power_well() */ 1107 SKL_DISP_PW_ALWAYS_ON, 1108 SKL_DISP_PW_DC_OFF, 1109 1110 BXT_DPIO_CMN_A, 1111 BXT_DPIO_CMN_BC, 1112 GLK_DPIO_CMN_C, 1113 }; 1114 1115 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) 1116 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) 1117 1118 #define PUNIT_REG_PWRGT_CTRL 0x60 1119 #define PUNIT_REG_PWRGT_STATUS 0x61 1120 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 1121 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 1122 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 1123 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 1124 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 1125 1126 #define PUNIT_REG_GPU_LFM 0xd3 1127 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 1128 #define PUNIT_REG_GPU_FREQ_STS 0xd8 1129 #define GPLLENABLE (1<<4) 1130 #define GENFREQSTATUS (1<<0) 1131 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 1132 #define PUNIT_REG_CZ_TIMESTAMP 0xce 1133 1134 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 1135 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 1136 1137 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 1138 #define FB_GFX_FREQ_FUSE_MASK 0xff 1139 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 1140 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 1141 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 1142 1143 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 1144 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 1145 1146 #define PUNIT_REG_DDR_SETUP2 0x139 1147 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 1148 #define FORCE_DDR_LOW_FREQ (1 << 1) 1149 #define FORCE_DDR_HIGH_FREQ (1 << 0) 1150 1151 #define PUNIT_GPU_STATUS_REG 0xdb 1152 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 1153 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 1154 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 1155 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 1156 1157 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 1158 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 1159 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 1160 1161 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 1162 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 1163 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 1164 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 1165 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 1166 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 1167 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 1168 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 1169 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 1170 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 1171 1172 #define VLV_TURBO_SOC_OVERRIDE 0x04 1173 #define VLV_OVERRIDE_EN 1 1174 #define VLV_SOC_TDP_EN (1 << 1) 1175 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 1176 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 1177 1178 /* vlv2 north clock has */ 1179 #define CCK_FUSE_REG 0x8 1180 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 1181 #define CCK_REG_DSI_PLL_FUSE 0x44 1182 #define CCK_REG_DSI_PLL_CONTROL 0x48 1183 #define DSI_PLL_VCO_EN (1 << 31) 1184 #define DSI_PLL_LDO_GATE (1 << 30) 1185 #define DSI_PLL_P1_POST_DIV_SHIFT 17 1186 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 1187 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 1188 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 1189 #define DSI_PLL_MUX_MASK (3 << 9) 1190 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 1191 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 1192 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 1193 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 1194 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 1195 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 1196 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 1197 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 1198 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 1199 #define DSI_PLL_LOCK (1 << 0) 1200 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 1201 #define DSI_PLL_LFSR (1 << 31) 1202 #define DSI_PLL_FRACTION_EN (1 << 30) 1203 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 1204 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 1205 #define DSI_PLL_USYNC_CNT_SHIFT 18 1206 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 1207 #define DSI_PLL_N1_DIV_SHIFT 16 1208 #define DSI_PLL_N1_DIV_MASK (3 << 16) 1209 #define DSI_PLL_M1_DIV_SHIFT 0 1210 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 1211 #define CCK_CZ_CLOCK_CONTROL 0x62 1212 #define CCK_GPLL_CLOCK_CONTROL 0x67 1213 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 1214 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 1215 #define CCK_TRUNK_FORCE_ON (1 << 17) 1216 #define CCK_TRUNK_FORCE_OFF (1 << 16) 1217 #define CCK_FREQUENCY_STATUS (0x1f << 8) 1218 #define CCK_FREQUENCY_STATUS_SHIFT 8 1219 #define CCK_FREQUENCY_VALUES (0x1f << 0) 1220 1221 /* DPIO registers */ 1222 #define DPIO_DEVFN 0 1223 1224 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 1225 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 1226 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 1227 #define DPIO_SFR_BYPASS (1<<1) 1228 #define DPIO_CMNRST (1<<0) 1229 1230 #define DPIO_PHY(pipe) ((pipe) >> 1) 1231 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 1232 1233 /* 1234 * Per pipe/PLL DPIO regs 1235 */ 1236 #define _VLV_PLL_DW3_CH0 0x800c 1237 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 1238 #define DPIO_POST_DIV_DAC 0 1239 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 1240 #define DPIO_POST_DIV_LVDS1 2 1241 #define DPIO_POST_DIV_LVDS2 3 1242 #define DPIO_K_SHIFT (24) /* 4 bits */ 1243 #define DPIO_P1_SHIFT (21) /* 3 bits */ 1244 #define DPIO_P2_SHIFT (16) /* 5 bits */ 1245 #define DPIO_N_SHIFT (12) /* 4 bits */ 1246 #define DPIO_ENABLE_CALIBRATION (1<<11) 1247 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 1248 #define DPIO_M2DIV_MASK 0xff 1249 #define _VLV_PLL_DW3_CH1 0x802c 1250 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 1251 1252 #define _VLV_PLL_DW5_CH0 0x8014 1253 #define DPIO_REFSEL_OVERRIDE 27 1254 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 1255 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 1256 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 1257 #define DPIO_PLL_REFCLK_SEL_MASK 3 1258 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 1259 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 1260 #define _VLV_PLL_DW5_CH1 0x8034 1261 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 1262 1263 #define _VLV_PLL_DW7_CH0 0x801c 1264 #define _VLV_PLL_DW7_CH1 0x803c 1265 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 1266 1267 #define _VLV_PLL_DW8_CH0 0x8040 1268 #define _VLV_PLL_DW8_CH1 0x8060 1269 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 1270 1271 #define VLV_PLL_DW9_BCAST 0xc044 1272 #define _VLV_PLL_DW9_CH0 0x8044 1273 #define _VLV_PLL_DW9_CH1 0x8064 1274 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 1275 1276 #define _VLV_PLL_DW10_CH0 0x8048 1277 #define _VLV_PLL_DW10_CH1 0x8068 1278 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 1279 1280 #define _VLV_PLL_DW11_CH0 0x804c 1281 #define _VLV_PLL_DW11_CH1 0x806c 1282 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 1283 1284 /* Spec for ref block start counts at DW10 */ 1285 #define VLV_REF_DW13 0x80ac 1286 1287 #define VLV_CMN_DW0 0x8100 1288 1289 /* 1290 * Per DDI channel DPIO regs 1291 */ 1292 1293 #define _VLV_PCS_DW0_CH0 0x8200 1294 #define _VLV_PCS_DW0_CH1 0x8400 1295 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 1296 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 1297 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) 1298 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) 1299 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1300 1301 #define _VLV_PCS01_DW0_CH0 0x200 1302 #define _VLV_PCS23_DW0_CH0 0x400 1303 #define _VLV_PCS01_DW0_CH1 0x2600 1304 #define _VLV_PCS23_DW0_CH1 0x2800 1305 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1306 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1307 1308 #define _VLV_PCS_DW1_CH0 0x8204 1309 #define _VLV_PCS_DW1_CH1 0x8404 1310 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 1311 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 1312 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 1313 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1314 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 1315 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1316 1317 #define _VLV_PCS01_DW1_CH0 0x204 1318 #define _VLV_PCS23_DW1_CH0 0x404 1319 #define _VLV_PCS01_DW1_CH1 0x2604 1320 #define _VLV_PCS23_DW1_CH1 0x2804 1321 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1322 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1323 1324 #define _VLV_PCS_DW8_CH0 0x8220 1325 #define _VLV_PCS_DW8_CH1 0x8420 1326 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1327 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1328 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1329 1330 #define _VLV_PCS01_DW8_CH0 0x0220 1331 #define _VLV_PCS23_DW8_CH0 0x0420 1332 #define _VLV_PCS01_DW8_CH1 0x2620 1333 #define _VLV_PCS23_DW8_CH1 0x2820 1334 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1335 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1336 1337 #define _VLV_PCS_DW9_CH0 0x8224 1338 #define _VLV_PCS_DW9_CH1 0x8424 1339 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) 1340 #define DPIO_PCS_TX2MARGIN_000 (0<<13) 1341 #define DPIO_PCS_TX2MARGIN_101 (1<<13) 1342 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) 1343 #define DPIO_PCS_TX1MARGIN_000 (0<<10) 1344 #define DPIO_PCS_TX1MARGIN_101 (1<<10) 1345 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1346 1347 #define _VLV_PCS01_DW9_CH0 0x224 1348 #define _VLV_PCS23_DW9_CH0 0x424 1349 #define _VLV_PCS01_DW9_CH1 0x2624 1350 #define _VLV_PCS23_DW9_CH1 0x2824 1351 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1352 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1353 1354 #define _CHV_PCS_DW10_CH0 0x8228 1355 #define _CHV_PCS_DW10_CH1 0x8428 1356 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 1357 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 1358 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) 1359 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) 1360 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) 1361 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) 1362 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) 1363 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) 1364 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1365 1366 #define _VLV_PCS01_DW10_CH0 0x0228 1367 #define _VLV_PCS23_DW10_CH0 0x0428 1368 #define _VLV_PCS01_DW10_CH1 0x2628 1369 #define _VLV_PCS23_DW10_CH1 0x2828 1370 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1371 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1372 1373 #define _VLV_PCS_DW11_CH0 0x822c 1374 #define _VLV_PCS_DW11_CH1 0x842c 1375 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) 1376 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) 1377 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) 1378 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) 1379 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1380 1381 #define _VLV_PCS01_DW11_CH0 0x022c 1382 #define _VLV_PCS23_DW11_CH0 0x042c 1383 #define _VLV_PCS01_DW11_CH1 0x262c 1384 #define _VLV_PCS23_DW11_CH1 0x282c 1385 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1386 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1387 1388 #define _VLV_PCS01_DW12_CH0 0x0230 1389 #define _VLV_PCS23_DW12_CH0 0x0430 1390 #define _VLV_PCS01_DW12_CH1 0x2630 1391 #define _VLV_PCS23_DW12_CH1 0x2830 1392 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1393 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1394 1395 #define _VLV_PCS_DW12_CH0 0x8230 1396 #define _VLV_PCS_DW12_CH1 0x8430 1397 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) 1398 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) 1399 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) 1400 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) 1401 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) 1402 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1403 1404 #define _VLV_PCS_DW14_CH0 0x8238 1405 #define _VLV_PCS_DW14_CH1 0x8438 1406 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1407 1408 #define _VLV_PCS_DW23_CH0 0x825c 1409 #define _VLV_PCS_DW23_CH1 0x845c 1410 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1411 1412 #define _VLV_TX_DW2_CH0 0x8288 1413 #define _VLV_TX_DW2_CH1 0x8488 1414 #define DPIO_SWING_MARGIN000_SHIFT 16 1415 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1416 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1417 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1418 1419 #define _VLV_TX_DW3_CH0 0x828c 1420 #define _VLV_TX_DW3_CH1 0x848c 1421 /* The following bit for CHV phy */ 1422 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 1423 #define DPIO_SWING_MARGIN101_SHIFT 16 1424 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1425 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1426 1427 #define _VLV_TX_DW4_CH0 0x8290 1428 #define _VLV_TX_DW4_CH1 0x8490 1429 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1430 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1431 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1432 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1433 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1434 1435 #define _VLV_TX3_DW4_CH0 0x690 1436 #define _VLV_TX3_DW4_CH1 0x2a90 1437 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1438 1439 #define _VLV_TX_DW5_CH0 0x8294 1440 #define _VLV_TX_DW5_CH1 0x8494 1441 #define DPIO_TX_OCALINIT_EN (1<<31) 1442 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1443 1444 #define _VLV_TX_DW11_CH0 0x82ac 1445 #define _VLV_TX_DW11_CH1 0x84ac 1446 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1447 1448 #define _VLV_TX_DW14_CH0 0x82b8 1449 #define _VLV_TX_DW14_CH1 0x84b8 1450 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1451 1452 /* CHV dpPhy registers */ 1453 #define _CHV_PLL_DW0_CH0 0x8000 1454 #define _CHV_PLL_DW0_CH1 0x8180 1455 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1456 1457 #define _CHV_PLL_DW1_CH0 0x8004 1458 #define _CHV_PLL_DW1_CH1 0x8184 1459 #define DPIO_CHV_N_DIV_SHIFT 8 1460 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1461 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1462 1463 #define _CHV_PLL_DW2_CH0 0x8008 1464 #define _CHV_PLL_DW2_CH1 0x8188 1465 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1466 1467 #define _CHV_PLL_DW3_CH0 0x800c 1468 #define _CHV_PLL_DW3_CH1 0x818c 1469 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1470 #define DPIO_CHV_FIRST_MOD (0 << 8) 1471 #define DPIO_CHV_SECOND_MOD (1 << 8) 1472 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1473 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1474 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1475 1476 #define _CHV_PLL_DW6_CH0 0x8018 1477 #define _CHV_PLL_DW6_CH1 0x8198 1478 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1479 #define DPIO_CHV_INT_COEFF_SHIFT 8 1480 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1481 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1482 1483 #define _CHV_PLL_DW8_CH0 0x8020 1484 #define _CHV_PLL_DW8_CH1 0x81A0 1485 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1486 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1487 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1488 1489 #define _CHV_PLL_DW9_CH0 0x8024 1490 #define _CHV_PLL_DW9_CH1 0x81A4 1491 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1492 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1493 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1494 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1495 1496 #define _CHV_CMN_DW0_CH0 0x8100 1497 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1498 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1499 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1500 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1501 1502 #define _CHV_CMN_DW5_CH0 0x8114 1503 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1504 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1505 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1506 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1507 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1508 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1509 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1510 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1511 1512 #define _CHV_CMN_DW13_CH0 0x8134 1513 #define _CHV_CMN_DW0_CH1 0x8080 1514 #define DPIO_CHV_S1_DIV_SHIFT 21 1515 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1516 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1517 #define DPIO_CHV_K_DIV_SHIFT 4 1518 #define DPIO_PLL_FREQLOCK (1 << 1) 1519 #define DPIO_PLL_LOCK (1 << 0) 1520 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1521 1522 #define _CHV_CMN_DW14_CH0 0x8138 1523 #define _CHV_CMN_DW1_CH1 0x8084 1524 #define DPIO_AFC_RECAL (1 << 14) 1525 #define DPIO_DCLKP_EN (1 << 13) 1526 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1527 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1528 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1529 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1530 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1531 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1532 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1533 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1534 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1535 1536 #define _CHV_CMN_DW19_CH0 0x814c 1537 #define _CHV_CMN_DW6_CH1 0x8098 1538 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1539 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1540 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1541 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1542 1543 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1544 1545 #define CHV_CMN_DW28 0x8170 1546 #define DPIO_CL1POWERDOWNEN (1 << 23) 1547 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1548 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1549 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1550 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1551 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1552 1553 #define CHV_CMN_DW30 0x8178 1554 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1555 #define DPIO_LRC_BYPASS (1 << 3) 1556 1557 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1558 (lane) * 0x200 + (offset)) 1559 1560 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1561 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1562 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1563 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1564 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1565 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1566 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1567 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1568 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1569 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1570 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1571 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1572 #define DPIO_FRC_LATENCY_SHFIT 8 1573 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1574 #define DPIO_UPAR_SHIFT 30 1575 1576 /* BXT PHY registers */ 1577 #define _BXT_PHY0_BASE 0x6C000 1578 #define _BXT_PHY1_BASE 0x162000 1579 #define _BXT_PHY2_BASE 0x163000 1580 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 1581 _BXT_PHY1_BASE, \ 1582 _BXT_PHY2_BASE) 1583 1584 #define _BXT_PHY(phy, reg) \ 1585 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 1586 1587 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1588 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 1589 (reg_ch1) - _BXT_PHY0_BASE)) 1590 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1591 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 1592 1593 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1594 #define MIPIO_RST_CTRL (1 << 2) 1595 1596 #define _BXT_PHY_CTL_DDI_A 0x64C00 1597 #define _BXT_PHY_CTL_DDI_B 0x64C10 1598 #define _BXT_PHY_CTL_DDI_C 0x64C20 1599 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1600 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1601 #define BXT_PHY_LANE_ENABLED (1 << 8) 1602 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1603 _BXT_PHY_CTL_DDI_B) 1604 1605 #define _PHY_CTL_FAMILY_EDP 0x64C80 1606 #define _PHY_CTL_FAMILY_DDI 0x64C90 1607 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 1608 #define COMMON_RESET_DIS (1 << 31) 1609 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 1610 _PHY_CTL_FAMILY_EDP, \ 1611 _PHY_CTL_FAMILY_DDI_C) 1612 1613 /* BXT PHY PLL registers */ 1614 #define _PORT_PLL_A 0x46074 1615 #define _PORT_PLL_B 0x46078 1616 #define _PORT_PLL_C 0x4607c 1617 #define PORT_PLL_ENABLE (1 << 31) 1618 #define PORT_PLL_LOCK (1 << 30) 1619 #define PORT_PLL_REF_SEL (1 << 27) 1620 #define PORT_PLL_POWER_ENABLE (1 << 26) 1621 #define PORT_PLL_POWER_STATE (1 << 25) 1622 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1623 1624 #define _PORT_PLL_EBB_0_A 0x162034 1625 #define _PORT_PLL_EBB_0_B 0x6C034 1626 #define _PORT_PLL_EBB_0_C 0x6C340 1627 #define PORT_PLL_P1_SHIFT 13 1628 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1629 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1630 #define PORT_PLL_P2_SHIFT 8 1631 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1632 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1633 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1634 _PORT_PLL_EBB_0_B, \ 1635 _PORT_PLL_EBB_0_C) 1636 1637 #define _PORT_PLL_EBB_4_A 0x162038 1638 #define _PORT_PLL_EBB_4_B 0x6C038 1639 #define _PORT_PLL_EBB_4_C 0x6C344 1640 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1641 #define PORT_PLL_RECALIBRATE (1 << 14) 1642 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1643 _PORT_PLL_EBB_4_B, \ 1644 _PORT_PLL_EBB_4_C) 1645 1646 #define _PORT_PLL_0_A 0x162100 1647 #define _PORT_PLL_0_B 0x6C100 1648 #define _PORT_PLL_0_C 0x6C380 1649 /* PORT_PLL_0_A */ 1650 #define PORT_PLL_M2_MASK 0xFF 1651 /* PORT_PLL_1_A */ 1652 #define PORT_PLL_N_SHIFT 8 1653 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1654 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1655 /* PORT_PLL_2_A */ 1656 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1657 /* PORT_PLL_3_A */ 1658 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1659 /* PORT_PLL_6_A */ 1660 #define PORT_PLL_PROP_COEFF_MASK 0xF 1661 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1662 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1663 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1664 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1665 /* PORT_PLL_8_A */ 1666 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1667 /* PORT_PLL_9_A */ 1668 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1669 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1670 /* PORT_PLL_10_A */ 1671 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) 1672 #define PORT_PLL_DCO_AMP_DEFAULT 15 1673 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1674 #define PORT_PLL_DCO_AMP(x) ((x)<<10) 1675 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 1676 _PORT_PLL_0_B, \ 1677 _PORT_PLL_0_C) 1678 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 1679 (idx) * 4) 1680 1681 /* BXT PHY common lane registers */ 1682 #define _PORT_CL1CM_DW0_A 0x162000 1683 #define _PORT_CL1CM_DW0_BC 0x6C000 1684 #define PHY_POWER_GOOD (1 << 16) 1685 #define PHY_RESERVED (1 << 7) 1686 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1687 1688 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1689 #define CL_POWER_DOWN_ENABLE (1 << 4) 1690 #define SUS_CLOCK_CONFIG (3 << 0) 1691 1692 #define _PORT_CL1CM_DW9_A 0x162024 1693 #define _PORT_CL1CM_DW9_BC 0x6C024 1694 #define IREF0RC_OFFSET_SHIFT 8 1695 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1696 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 1697 1698 #define _PORT_CL1CM_DW10_A 0x162028 1699 #define _PORT_CL1CM_DW10_BC 0x6C028 1700 #define IREF1RC_OFFSET_SHIFT 8 1701 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1702 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1703 1704 #define _PORT_CL1CM_DW28_A 0x162070 1705 #define _PORT_CL1CM_DW28_BC 0x6C070 1706 #define OCL1_POWER_DOWN_EN (1 << 23) 1707 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1708 #define SUS_CLK_CONFIG 0x3 1709 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 1710 1711 #define _PORT_CL1CM_DW30_A 0x162078 1712 #define _PORT_CL1CM_DW30_BC 0x6C078 1713 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1714 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1715 1716 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1717 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1718 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1719 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 1720 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 1721 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 1722 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604 1723 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 1724 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 1725 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 1726 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \ 1727 _CNL_PORT_PCS_DW1_GRP_AE, \ 1728 _CNL_PORT_PCS_DW1_GRP_B, \ 1729 _CNL_PORT_PCS_DW1_GRP_C, \ 1730 _CNL_PORT_PCS_DW1_GRP_D, \ 1731 _CNL_PORT_PCS_DW1_GRP_AE, \ 1732 _CNL_PORT_PCS_DW1_GRP_F) 1733 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \ 1734 _CNL_PORT_PCS_DW1_LN0_AE, \ 1735 _CNL_PORT_PCS_DW1_LN0_B, \ 1736 _CNL_PORT_PCS_DW1_LN0_C, \ 1737 _CNL_PORT_PCS_DW1_LN0_D, \ 1738 _CNL_PORT_PCS_DW1_LN0_AE, \ 1739 _CNL_PORT_PCS_DW1_LN0_F) 1740 #define COMMON_KEEPER_EN (1 << 26) 1741 1742 #define _CNL_PORT_TX_DW2_GRP_AE 0x162348 1743 #define _CNL_PORT_TX_DW2_GRP_B 0x1623C8 1744 #define _CNL_PORT_TX_DW2_GRP_C 0x162B48 1745 #define _CNL_PORT_TX_DW2_GRP_D 0x162BC8 1746 #define _CNL_PORT_TX_DW2_GRP_F 0x162A48 1747 #define _CNL_PORT_TX_DW2_LN0_AE 0x162448 1748 #define _CNL_PORT_TX_DW2_LN0_B 0x162648 1749 #define _CNL_PORT_TX_DW2_LN0_C 0x162C48 1750 #define _CNL_PORT_TX_DW2_LN0_D 0x162E48 1751 #define _CNL_PORT_TX_DW2_LN0_F 0x162A48 1752 #define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \ 1753 _CNL_PORT_TX_DW2_GRP_AE, \ 1754 _CNL_PORT_TX_DW2_GRP_B, \ 1755 _CNL_PORT_TX_DW2_GRP_C, \ 1756 _CNL_PORT_TX_DW2_GRP_D, \ 1757 _CNL_PORT_TX_DW2_GRP_AE, \ 1758 _CNL_PORT_TX_DW2_GRP_F) 1759 #define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \ 1760 _CNL_PORT_TX_DW2_LN0_AE, \ 1761 _CNL_PORT_TX_DW2_LN0_B, \ 1762 _CNL_PORT_TX_DW2_LN0_C, \ 1763 _CNL_PORT_TX_DW2_LN0_D, \ 1764 _CNL_PORT_TX_DW2_LN0_AE, \ 1765 _CNL_PORT_TX_DW2_LN0_F) 1766 #define SWING_SEL_UPPER(x) ((x >> 3) << 15) 1767 #define SWING_SEL_UPPER_MASK (1 << 15) 1768 #define SWING_SEL_LOWER(x) ((x & 0x7) << 11) 1769 #define SWING_SEL_LOWER_MASK (0x7 << 11) 1770 #define RCOMP_SCALAR(x) ((x) << 0) 1771 #define RCOMP_SCALAR_MASK (0xFF << 0) 1772 1773 #define _CNL_PORT_TX_DW4_GRP_AE 0x162350 1774 #define _CNL_PORT_TX_DW4_GRP_B 0x1623D0 1775 #define _CNL_PORT_TX_DW4_GRP_C 0x162B50 1776 #define _CNL_PORT_TX_DW4_GRP_D 0x162BD0 1777 #define _CNL_PORT_TX_DW4_GRP_F 0x162A50 1778 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 1779 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 1780 #define _CNL_PORT_TX_DW4_LN0_B 0x162650 1781 #define _CNL_PORT_TX_DW4_LN0_C 0x162C50 1782 #define _CNL_PORT_TX_DW4_LN0_D 0x162E50 1783 #define _CNL_PORT_TX_DW4_LN0_F 0x162850 1784 #define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \ 1785 _CNL_PORT_TX_DW4_GRP_AE, \ 1786 _CNL_PORT_TX_DW4_GRP_B, \ 1787 _CNL_PORT_TX_DW4_GRP_C, \ 1788 _CNL_PORT_TX_DW4_GRP_D, \ 1789 _CNL_PORT_TX_DW4_GRP_AE, \ 1790 _CNL_PORT_TX_DW4_GRP_F) 1791 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \ 1792 _CNL_PORT_TX_DW4_LN0_AE, \ 1793 _CNL_PORT_TX_DW4_LN1_AE, \ 1794 _CNL_PORT_TX_DW4_LN0_B, \ 1795 _CNL_PORT_TX_DW4_LN0_C, \ 1796 _CNL_PORT_TX_DW4_LN0_D, \ 1797 _CNL_PORT_TX_DW4_LN0_AE, \ 1798 _CNL_PORT_TX_DW4_LN0_F) 1799 #define LOADGEN_SELECT (1 << 31) 1800 #define POST_CURSOR_1(x) ((x) << 12) 1801 #define POST_CURSOR_1_MASK (0x3F << 12) 1802 #define POST_CURSOR_2(x) ((x) << 6) 1803 #define POST_CURSOR_2_MASK (0x3F << 6) 1804 #define CURSOR_COEFF(x) ((x) << 0) 1805 #define CURSOR_COEFF_MASK (0x3F << 0) 1806 1807 #define _CNL_PORT_TX_DW5_GRP_AE 0x162354 1808 #define _CNL_PORT_TX_DW5_GRP_B 0x1623D4 1809 #define _CNL_PORT_TX_DW5_GRP_C 0x162B54 1810 #define _CNL_PORT_TX_DW5_GRP_D 0x162BD4 1811 #define _CNL_PORT_TX_DW5_GRP_F 0x162A54 1812 #define _CNL_PORT_TX_DW5_LN0_AE 0x162454 1813 #define _CNL_PORT_TX_DW5_LN0_B 0x162654 1814 #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 1815 #define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 1816 #define _CNL_PORT_TX_DW5_LN0_F 0x162854 1817 #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ 1818 _CNL_PORT_TX_DW5_GRP_AE, \ 1819 _CNL_PORT_TX_DW5_GRP_B, \ 1820 _CNL_PORT_TX_DW5_GRP_C, \ 1821 _CNL_PORT_TX_DW5_GRP_D, \ 1822 _CNL_PORT_TX_DW5_GRP_AE, \ 1823 _CNL_PORT_TX_DW5_GRP_F) 1824 #define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \ 1825 _CNL_PORT_TX_DW5_LN0_AE, \ 1826 _CNL_PORT_TX_DW5_LN0_B, \ 1827 _CNL_PORT_TX_DW5_LN0_C, \ 1828 _CNL_PORT_TX_DW5_LN0_D, \ 1829 _CNL_PORT_TX_DW5_LN0_AE, \ 1830 _CNL_PORT_TX_DW5_LN0_F) 1831 #define TX_TRAINING_EN (1 << 31) 1832 #define TAP3_DISABLE (1 << 29) 1833 #define SCALING_MODE_SEL(x) ((x) << 18) 1834 #define SCALING_MODE_SEL_MASK (0x7 << 18) 1835 #define RTERM_SELECT(x) ((x) << 3) 1836 #define RTERM_SELECT_MASK (0x7 << 3) 1837 1838 #define _CNL_PORT_TX_DW7_GRP_AE 0x16235C 1839 #define _CNL_PORT_TX_DW7_GRP_B 0x1623DC 1840 #define _CNL_PORT_TX_DW7_GRP_C 0x162B5C 1841 #define _CNL_PORT_TX_DW7_GRP_D 0x162BDC 1842 #define _CNL_PORT_TX_DW7_GRP_F 0x162A5C 1843 #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C 1844 #define _CNL_PORT_TX_DW7_LN0_B 0x16265C 1845 #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C 1846 #define _CNL_PORT_TX_DW7_LN0_D 0x162EDC 1847 #define _CNL_PORT_TX_DW7_LN0_F 0x16285C 1848 #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ 1849 _CNL_PORT_TX_DW7_GRP_AE, \ 1850 _CNL_PORT_TX_DW7_GRP_B, \ 1851 _CNL_PORT_TX_DW7_GRP_C, \ 1852 _CNL_PORT_TX_DW7_GRP_D, \ 1853 _CNL_PORT_TX_DW7_GRP_AE, \ 1854 _CNL_PORT_TX_DW7_GRP_F) 1855 #define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \ 1856 _CNL_PORT_TX_DW7_LN0_AE, \ 1857 _CNL_PORT_TX_DW7_LN0_B, \ 1858 _CNL_PORT_TX_DW7_LN0_C, \ 1859 _CNL_PORT_TX_DW7_LN0_D, \ 1860 _CNL_PORT_TX_DW7_LN0_AE, \ 1861 _CNL_PORT_TX_DW7_LN0_F) 1862 #define N_SCALAR(x) ((x) << 24) 1863 #define N_SCALAR_MASK (0x7F << 24) 1864 1865 /* The spec defines this only for BXT PHY0, but lets assume that this 1866 * would exist for PHY1 too if it had a second channel. 1867 */ 1868 #define _PORT_CL2CM_DW6_A 0x162358 1869 #define _PORT_CL2CM_DW6_BC 0x6C358 1870 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 1871 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 1872 1873 #define CNL_PORT_COMP_DW0 _MMIO(0x162100) 1874 #define COMP_INIT (1 << 31) 1875 #define CNL_PORT_COMP_DW1 _MMIO(0x162104) 1876 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 1877 #define PROCESS_INFO_DOT_0 (0 << 26) 1878 #define PROCESS_INFO_DOT_1 (1 << 26) 1879 #define PROCESS_INFO_DOT_4 (2 << 26) 1880 #define PROCESS_INFO_MASK (7 << 26) 1881 #define PROCESS_INFO_SHIFT 26 1882 #define VOLTAGE_INFO_0_85V (0 << 24) 1883 #define VOLTAGE_INFO_0_95V (1 << 24) 1884 #define VOLTAGE_INFO_1_05V (2 << 24) 1885 #define VOLTAGE_INFO_MASK (3 << 24) 1886 #define VOLTAGE_INFO_SHIFT 24 1887 #define CNL_PORT_COMP_DW9 _MMIO(0x162124) 1888 #define CNL_PORT_COMP_DW10 _MMIO(0x162128) 1889 1890 /* BXT PHY Ref registers */ 1891 #define _PORT_REF_DW3_A 0x16218C 1892 #define _PORT_REF_DW3_BC 0x6C18C 1893 #define GRC_DONE (1 << 22) 1894 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 1895 1896 #define _PORT_REF_DW6_A 0x162198 1897 #define _PORT_REF_DW6_BC 0x6C198 1898 #define GRC_CODE_SHIFT 24 1899 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 1900 #define GRC_CODE_FAST_SHIFT 16 1901 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 1902 #define GRC_CODE_SLOW_SHIFT 8 1903 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 1904 #define GRC_CODE_NOM_MASK 0xFF 1905 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 1906 1907 #define _PORT_REF_DW8_A 0x1621A0 1908 #define _PORT_REF_DW8_BC 0x6C1A0 1909 #define GRC_DIS (1 << 15) 1910 #define GRC_RDY_OVRD (1 << 1) 1911 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 1912 1913 /* BXT PHY PCS registers */ 1914 #define _PORT_PCS_DW10_LN01_A 0x162428 1915 #define _PORT_PCS_DW10_LN01_B 0x6C428 1916 #define _PORT_PCS_DW10_LN01_C 0x6C828 1917 #define _PORT_PCS_DW10_GRP_A 0x162C28 1918 #define _PORT_PCS_DW10_GRP_B 0x6CC28 1919 #define _PORT_PCS_DW10_GRP_C 0x6CE28 1920 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1921 _PORT_PCS_DW10_LN01_B, \ 1922 _PORT_PCS_DW10_LN01_C) 1923 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1924 _PORT_PCS_DW10_GRP_B, \ 1925 _PORT_PCS_DW10_GRP_C) 1926 1927 #define TX2_SWING_CALC_INIT (1 << 31) 1928 #define TX1_SWING_CALC_INIT (1 << 30) 1929 1930 #define _PORT_PCS_DW12_LN01_A 0x162430 1931 #define _PORT_PCS_DW12_LN01_B 0x6C430 1932 #define _PORT_PCS_DW12_LN01_C 0x6C830 1933 #define _PORT_PCS_DW12_LN23_A 0x162630 1934 #define _PORT_PCS_DW12_LN23_B 0x6C630 1935 #define _PORT_PCS_DW12_LN23_C 0x6CA30 1936 #define _PORT_PCS_DW12_GRP_A 0x162c30 1937 #define _PORT_PCS_DW12_GRP_B 0x6CC30 1938 #define _PORT_PCS_DW12_GRP_C 0x6CE30 1939 #define LANESTAGGER_STRAP_OVRD (1 << 6) 1940 #define LANE_STAGGER_MASK 0x1F 1941 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1942 _PORT_PCS_DW12_LN01_B, \ 1943 _PORT_PCS_DW12_LN01_C) 1944 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1945 _PORT_PCS_DW12_LN23_B, \ 1946 _PORT_PCS_DW12_LN23_C) 1947 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1948 _PORT_PCS_DW12_GRP_B, \ 1949 _PORT_PCS_DW12_GRP_C) 1950 1951 /* BXT PHY TX registers */ 1952 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 1953 ((lane) & 1) * 0x80) 1954 1955 #define _PORT_TX_DW2_LN0_A 0x162508 1956 #define _PORT_TX_DW2_LN0_B 0x6C508 1957 #define _PORT_TX_DW2_LN0_C 0x6C908 1958 #define _PORT_TX_DW2_GRP_A 0x162D08 1959 #define _PORT_TX_DW2_GRP_B 0x6CD08 1960 #define _PORT_TX_DW2_GRP_C 0x6CF08 1961 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1962 _PORT_TX_DW2_LN0_B, \ 1963 _PORT_TX_DW2_LN0_C) 1964 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1965 _PORT_TX_DW2_GRP_B, \ 1966 _PORT_TX_DW2_GRP_C) 1967 #define MARGIN_000_SHIFT 16 1968 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 1969 #define UNIQ_TRANS_SCALE_SHIFT 8 1970 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 1971 1972 #define _PORT_TX_DW3_LN0_A 0x16250C 1973 #define _PORT_TX_DW3_LN0_B 0x6C50C 1974 #define _PORT_TX_DW3_LN0_C 0x6C90C 1975 #define _PORT_TX_DW3_GRP_A 0x162D0C 1976 #define _PORT_TX_DW3_GRP_B 0x6CD0C 1977 #define _PORT_TX_DW3_GRP_C 0x6CF0C 1978 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1979 _PORT_TX_DW3_LN0_B, \ 1980 _PORT_TX_DW3_LN0_C) 1981 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1982 _PORT_TX_DW3_GRP_B, \ 1983 _PORT_TX_DW3_GRP_C) 1984 #define SCALE_DCOMP_METHOD (1 << 26) 1985 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 1986 1987 #define _PORT_TX_DW4_LN0_A 0x162510 1988 #define _PORT_TX_DW4_LN0_B 0x6C510 1989 #define _PORT_TX_DW4_LN0_C 0x6C910 1990 #define _PORT_TX_DW4_GRP_A 0x162D10 1991 #define _PORT_TX_DW4_GRP_B 0x6CD10 1992 #define _PORT_TX_DW4_GRP_C 0x6CF10 1993 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1994 _PORT_TX_DW4_LN0_B, \ 1995 _PORT_TX_DW4_LN0_C) 1996 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1997 _PORT_TX_DW4_GRP_B, \ 1998 _PORT_TX_DW4_GRP_C) 1999 #define DEEMPH_SHIFT 24 2000 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 2001 2002 #define _PORT_TX_DW5_LN0_A 0x162514 2003 #define _PORT_TX_DW5_LN0_B 0x6C514 2004 #define _PORT_TX_DW5_LN0_C 0x6C914 2005 #define _PORT_TX_DW5_GRP_A 0x162D14 2006 #define _PORT_TX_DW5_GRP_B 0x6CD14 2007 #define _PORT_TX_DW5_GRP_C 0x6CF14 2008 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2009 _PORT_TX_DW5_LN0_B, \ 2010 _PORT_TX_DW5_LN0_C) 2011 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2012 _PORT_TX_DW5_GRP_B, \ 2013 _PORT_TX_DW5_GRP_C) 2014 #define DCC_DELAY_RANGE_1 (1 << 9) 2015 #define DCC_DELAY_RANGE_2 (1 << 8) 2016 2017 #define _PORT_TX_DW14_LN0_A 0x162538 2018 #define _PORT_TX_DW14_LN0_B 0x6C538 2019 #define _PORT_TX_DW14_LN0_C 0x6C938 2020 #define LATENCY_OPTIM_SHIFT 30 2021 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 2022 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 2023 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 2024 _PORT_TX_DW14_LN0_C) + \ 2025 _BXT_LANE_OFFSET(lane)) 2026 2027 /* UAIMI scratch pad register 1 */ 2028 #define UAIMI_SPR1 _MMIO(0x4F074) 2029 /* SKL VccIO mask */ 2030 #define SKL_VCCIO_MASK 0x1 2031 /* SKL balance leg register */ 2032 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 2033 /* I_boost values */ 2034 #define BALANCE_LEG_SHIFT(port) (8+3*(port)) 2035 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) 2036 /* Balance leg disable bits */ 2037 #define BALANCE_LEG_DISABLE_SHIFT 23 2038 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 2039 2040 /* 2041 * Fence registers 2042 * [0-7] @ 0x2000 gen2,gen3 2043 * [8-15] @ 0x3000 945,g33,pnv 2044 * 2045 * [0-15] @ 0x3000 gen4,gen5 2046 * 2047 * [0-15] @ 0x100000 gen6,vlv,chv 2048 * [0-31] @ 0x100000 gen7+ 2049 */ 2050 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 2051 #define I830_FENCE_START_MASK 0x07f80000 2052 #define I830_FENCE_TILING_Y_SHIFT 12 2053 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 2054 #define I830_FENCE_PITCH_SHIFT 4 2055 #define I830_FENCE_REG_VALID (1<<0) 2056 #define I915_FENCE_MAX_PITCH_VAL 4 2057 #define I830_FENCE_MAX_PITCH_VAL 6 2058 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 2059 2060 #define I915_FENCE_START_MASK 0x0ff00000 2061 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 2062 2063 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 2064 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 2065 #define I965_FENCE_PITCH_SHIFT 2 2066 #define I965_FENCE_TILING_Y_SHIFT 1 2067 #define I965_FENCE_REG_VALID (1<<0) 2068 #define I965_FENCE_MAX_PITCH_VAL 0x0400 2069 2070 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 2071 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 2072 #define GEN6_FENCE_PITCH_SHIFT 32 2073 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 2074 2075 2076 /* control register for cpu gtt access */ 2077 #define TILECTL _MMIO(0x101000) 2078 #define TILECTL_SWZCTL (1 << 0) 2079 #define TILECTL_TLBPF (1 << 1) 2080 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 2081 #define TILECTL_BACKSNOOP_DIS (1 << 3) 2082 2083 /* 2084 * Instruction and interrupt control regs 2085 */ 2086 #define PGTBL_CTL _MMIO(0x02020) 2087 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 2088 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 2089 #define PGTBL_ER _MMIO(0x02024) 2090 #define PRB0_BASE (0x2030-0x30) 2091 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 2092 #define PRB2_BASE (0x2050-0x30) /* gen3 */ 2093 #define SRB0_BASE (0x2100-0x30) /* gen2 */ 2094 #define SRB1_BASE (0x2110-0x30) /* gen2 */ 2095 #define SRB2_BASE (0x2120-0x30) /* 830 */ 2096 #define SRB3_BASE (0x2130-0x30) /* 830 */ 2097 #define RENDER_RING_BASE 0x02000 2098 #define BSD_RING_BASE 0x04000 2099 #define GEN6_BSD_RING_BASE 0x12000 2100 #define GEN8_BSD2_RING_BASE 0x1c000 2101 #define VEBOX_RING_BASE 0x1a000 2102 #define BLT_RING_BASE 0x22000 2103 #define RING_TAIL(base) _MMIO((base)+0x30) 2104 #define RING_HEAD(base) _MMIO((base)+0x34) 2105 #define RING_START(base) _MMIO((base)+0x38) 2106 #define RING_CTL(base) _MMIO((base)+0x3c) 2107 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 2108 #define RING_SYNC_0(base) _MMIO((base)+0x40) 2109 #define RING_SYNC_1(base) _MMIO((base)+0x44) 2110 #define RING_SYNC_2(base) _MMIO((base)+0x48) 2111 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 2112 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 2113 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 2114 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 2115 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 2116 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 2117 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 2118 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 2119 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 2120 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 2121 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 2122 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 2123 #define GEN6_NOSYNC INVALID_MMIO_REG 2124 #define RING_PSMI_CTL(base) _MMIO((base)+0x50) 2125 #define RING_MAX_IDLE(base) _MMIO((base)+0x54) 2126 #define RING_HWS_PGA(base) _MMIO((base)+0x80) 2127 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080) 2128 #define RING_RESET_CTL(base) _MMIO((base)+0xd0) 2129 #define RESET_CTL_REQUEST_RESET (1 << 0) 2130 #define RESET_CTL_READY_TO_RESET (1 << 1) 2131 2132 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 2133 #define GTT_CACHE_EN_ALL 0xF0007FFF 2134 #define GEN7_WR_WATERMARK _MMIO(0x4028) 2135 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 2136 #define ARB_MODE _MMIO(0x4030) 2137 #define ARB_MODE_SWIZZLE_SNB (1<<4) 2138 #define ARB_MODE_SWIZZLE_IVB (1<<5) 2139 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 2140 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 2141 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 2142 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 2143 #define GEN7_LRA_LIMITS_REG_NUM 13 2144 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 2145 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 2146 2147 #define GAMTARBMODE _MMIO(0x04a08) 2148 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 2149 #define ARB_MODE_SWIZZLE_BDW (1<<1) 2150 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 2151 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id) 2152 #define RING_FAULT_GTTSEL_MASK (1<<11) 2153 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 2154 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 2155 #define RING_FAULT_VALID (1<<0) 2156 #define DONE_REG _MMIO(0x40b0) 2157 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 2158 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 2159 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 2160 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 2161 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 2162 #define RING_ACTHD(base) _MMIO((base)+0x74) 2163 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c) 2164 #define RING_NOPID(base) _MMIO((base)+0x94) 2165 #define RING_IMR(base) _MMIO((base)+0xa8) 2166 #define RING_HWSTAM(base) _MMIO((base)+0x98) 2167 #define RING_TIMESTAMP(base) _MMIO((base)+0x358) 2168 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4) 2169 #define TAIL_ADDR 0x001FFFF8 2170 #define HEAD_WRAP_COUNT 0xFFE00000 2171 #define HEAD_WRAP_ONE 0x00200000 2172 #define HEAD_ADDR 0x001FFFFC 2173 #define RING_NR_PAGES 0x001FF000 2174 #define RING_REPORT_MASK 0x00000006 2175 #define RING_REPORT_64K 0x00000002 2176 #define RING_REPORT_128K 0x00000004 2177 #define RING_NO_REPORT 0x00000000 2178 #define RING_VALID_MASK 0x00000001 2179 #define RING_VALID 0x00000001 2180 #define RING_INVALID 0x00000000 2181 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 2182 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 2183 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 2184 2185 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) 2186 #define RING_MAX_NONPRIV_SLOTS 12 2187 2188 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 2189 2190 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 2191 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18) 2192 2193 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2194 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) 2195 2196 #if 0 2197 #define PRB0_TAIL _MMIO(0x2030) 2198 #define PRB0_HEAD _MMIO(0x2034) 2199 #define PRB0_START _MMIO(0x2038) 2200 #define PRB0_CTL _MMIO(0x203c) 2201 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 2202 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 2203 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 2204 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 2205 #endif 2206 #define IPEIR_I965 _MMIO(0x2064) 2207 #define IPEHR_I965 _MMIO(0x2068) 2208 #define GEN7_SC_INSTDONE _MMIO(0x7100) 2209 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 2210 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 2211 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 2212 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 2213 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 2214 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 2215 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 2216 #define RING_IPEIR(base) _MMIO((base)+0x64) 2217 #define RING_IPEHR(base) _MMIO((base)+0x68) 2218 /* 2219 * On GEN4, only the render ring INSTDONE exists and has a different 2220 * layout than the GEN7+ version. 2221 * The GEN2 counterpart of this register is GEN2_INSTDONE. 2222 */ 2223 #define RING_INSTDONE(base) _MMIO((base)+0x6c) 2224 #define RING_INSTPS(base) _MMIO((base)+0x70) 2225 #define RING_DMA_FADD(base) _MMIO((base)+0x78) 2226 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */ 2227 #define RING_INSTPM(base) _MMIO((base)+0xc0) 2228 #define RING_MI_MODE(base) _MMIO((base)+0x9c) 2229 #define INSTPS _MMIO(0x2070) /* 965+ only */ 2230 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 2231 #define ACTHD_I965 _MMIO(0x2074) 2232 #define HWS_PGA _MMIO(0x2080) 2233 #define HWS_ADDRESS_MASK 0xfffff000 2234 #define HWS_START_ADDRESS_SHIFT 4 2235 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 2236 #define PWRCTX_EN (1<<0) 2237 #define IPEIR _MMIO(0x2088) 2238 #define IPEHR _MMIO(0x208c) 2239 #define GEN2_INSTDONE _MMIO(0x2090) 2240 #define NOPID _MMIO(0x2094) 2241 #define HWSTAM _MMIO(0x2098) 2242 #define DMA_FADD_I8XX _MMIO(0x20d0) 2243 #define RING_BBSTATE(base) _MMIO((base)+0x110) 2244 #define RING_BB_PPGTT (1 << 5) 2245 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */ 2246 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */ 2247 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */ 2248 #define RING_BBADDR(base) _MMIO((base)+0x140) 2249 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */ 2250 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */ 2251 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */ 2252 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */ 2253 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */ 2254 2255 #define ERROR_GEN6 _MMIO(0x40a0) 2256 #define GEN7_ERR_INT _MMIO(0x44040) 2257 #define ERR_INT_POISON (1<<31) 2258 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 2259 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 2260 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 2261 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 2262 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 2263 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 2264 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3)) 2265 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 2266 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 2267 2268 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 2269 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 2270 2271 #define FPGA_DBG _MMIO(0x42300) 2272 #define FPGA_DBG_RM_NOCLAIM (1<<31) 2273 2274 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 2275 #define CLAIM_ER_CLR (1 << 31) 2276 #define CLAIM_ER_OVERFLOW (1 << 16) 2277 #define CLAIM_ER_CTR_MASK 0xffff 2278 2279 #define DERRMR _MMIO(0x44050) 2280 /* Note that HBLANK events are reserved on bdw+ */ 2281 #define DERRMR_PIPEA_SCANLINE (1<<0) 2282 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 2283 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 2284 #define DERRMR_PIPEA_VBLANK (1<<3) 2285 #define DERRMR_PIPEA_HBLANK (1<<5) 2286 #define DERRMR_PIPEB_SCANLINE (1<<8) 2287 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 2288 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 2289 #define DERRMR_PIPEB_VBLANK (1<<11) 2290 #define DERRMR_PIPEB_HBLANK (1<<13) 2291 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 2292 #define DERRMR_PIPEC_SCANLINE (1<<14) 2293 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 2294 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 2295 #define DERRMR_PIPEC_VBLANK (1<<21) 2296 #define DERRMR_PIPEC_HBLANK (1<<22) 2297 2298 2299 /* GM45+ chicken bits -- debug workaround bits that may be required 2300 * for various sorts of correct behavior. The top 16 bits of each are 2301 * the enables for writing to the corresponding low bit. 2302 */ 2303 #define _3D_CHICKEN _MMIO(0x2084) 2304 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 2305 #define _3D_CHICKEN2 _MMIO(0x208c) 2306 /* Disables pipelining of read flushes past the SF-WIZ interface. 2307 * Required on all Ironlake steppings according to the B-Spec, but the 2308 * particular danger of not doing so is not specified. 2309 */ 2310 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2311 #define _3D_CHICKEN3 _MMIO(0x2090) 2312 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2313 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2314 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 2315 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2316 2317 #define MI_MODE _MMIO(0x209c) 2318 # define VS_TIMER_DISPATCH (1 << 6) 2319 # define MI_FLUSH_ENABLE (1 << 12) 2320 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 2321 # define MODE_IDLE (1 << 9) 2322 # define STOP_RING (1 << 8) 2323 2324 #define GEN6_GT_MODE _MMIO(0x20d0) 2325 #define GEN7_GT_MODE _MMIO(0x7008) 2326 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 2327 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 2328 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 2329 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 2330 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 2331 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 2332 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 2333 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 2334 2335 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2336 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2337 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2338 2339 /* WaClearTdlStateAckDirtyBits */ 2340 #define GEN8_STATE_ACK _MMIO(0x20F0) 2341 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 2342 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 2343 #define GEN9_STATE_ACK_TDL0 (1 << 12) 2344 #define GEN9_STATE_ACK_TDL1 (1 << 13) 2345 #define GEN9_STATE_ACK_TDL2 (1 << 14) 2346 #define GEN9_STATE_ACK_TDL3 (1 << 15) 2347 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 2348 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 2349 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 2350 2351 #define GFX_MODE _MMIO(0x2520) 2352 #define GFX_MODE_GEN7 _MMIO(0x229c) 2353 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c) 2354 #define GFX_RUN_LIST_ENABLE (1<<15) 2355 #define GFX_INTERRUPT_STEERING (1<<14) 2356 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 2357 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 2358 #define GFX_REPLAY_MODE (1<<11) 2359 #define GFX_PSMI_GRANULARITY (1<<10) 2360 #define GFX_PPGTT_ENABLE (1<<9) 2361 #define GEN8_GFX_PPGTT_48B (1<<7) 2362 2363 #define GFX_FORWARD_VBLANK_MASK (3<<5) 2364 #define GFX_FORWARD_VBLANK_NEVER (0<<5) 2365 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5) 2366 #define GFX_FORWARD_VBLANK_COND (2<<5) 2367 2368 #define VLV_DISPLAY_BASE 0x180000 2369 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 2370 #define BXT_MIPI_BASE 0x60000 2371 2372 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 2373 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 2374 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 2375 #define IER _MMIO(0x20a0) 2376 #define IIR _MMIO(0x20a4) 2377 #define IMR _MMIO(0x20a8) 2378 #define ISR _MMIO(0x20ac) 2379 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 2380 #define GINT_DIS (1<<22) 2381 #define GCFG_DIS (1<<8) 2382 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 2383 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 2384 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 2385 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 2386 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 2387 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 2388 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 2389 #define VLV_PCBR_ADDR_SHIFT 12 2390 2391 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 2392 #define EIR _MMIO(0x20b0) 2393 #define EMR _MMIO(0x20b4) 2394 #define ESR _MMIO(0x20b8) 2395 #define GM45_ERROR_PAGE_TABLE (1<<5) 2396 #define GM45_ERROR_MEM_PRIV (1<<4) 2397 #define I915_ERROR_PAGE_TABLE (1<<4) 2398 #define GM45_ERROR_CP_PRIV (1<<3) 2399 #define I915_ERROR_MEMORY_REFRESH (1<<1) 2400 #define I915_ERROR_INSTRUCTION (1<<0) 2401 #define INSTPM _MMIO(0x20c0) 2402 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 2403 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 2404 will not assert AGPBUSY# and will only 2405 be delivered when out of C3. */ 2406 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 2407 #define INSTPM_TLB_INVALIDATE (1<<9) 2408 #define INSTPM_SYNC_FLUSH (1<<5) 2409 #define ACTHD _MMIO(0x20c8) 2410 #define MEM_MODE _MMIO(0x20cc) 2411 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 2412 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 2413 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 2414 #define FW_BLC _MMIO(0x20d8) 2415 #define FW_BLC2 _MMIO(0x20dc) 2416 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 2417 #define FW_BLC_SELF_EN_MASK (1<<31) 2418 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 2419 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 2420 #define MM_BURST_LENGTH 0x00700000 2421 #define MM_FIFO_WATERMARK 0x0001F000 2422 #define LM_BURST_LENGTH 0x00000700 2423 #define LM_FIFO_WATERMARK 0x0000001F 2424 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 2425 2426 /* Make render/texture TLB fetches lower priorty than associated data 2427 * fetches. This is not turned on by default 2428 */ 2429 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 2430 2431 /* Isoch request wait on GTT enable (Display A/B/C streams). 2432 * Make isoch requests stall on the TLB update. May cause 2433 * display underruns (test mode only) 2434 */ 2435 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 2436 2437 /* Block grant count for isoch requests when block count is 2438 * set to a finite value. 2439 */ 2440 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 2441 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 2442 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 2443 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 2444 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 2445 2446 /* Enable render writes to complete in C2/C3/C4 power states. 2447 * If this isn't enabled, render writes are prevented in low 2448 * power states. That seems bad to me. 2449 */ 2450 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 2451 2452 /* This acknowledges an async flip immediately instead 2453 * of waiting for 2TLB fetches. 2454 */ 2455 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 2456 2457 /* Enables non-sequential data reads through arbiter 2458 */ 2459 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 2460 2461 /* Disable FSB snooping of cacheable write cycles from binner/render 2462 * command stream 2463 */ 2464 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 2465 2466 /* Arbiter time slice for non-isoch streams */ 2467 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 2468 #define MI_ARB_TIME_SLICE_1 (0 << 5) 2469 #define MI_ARB_TIME_SLICE_2 (1 << 5) 2470 #define MI_ARB_TIME_SLICE_4 (2 << 5) 2471 #define MI_ARB_TIME_SLICE_6 (3 << 5) 2472 #define MI_ARB_TIME_SLICE_8 (4 << 5) 2473 #define MI_ARB_TIME_SLICE_10 (5 << 5) 2474 #define MI_ARB_TIME_SLICE_14 (6 << 5) 2475 #define MI_ARB_TIME_SLICE_16 (7 << 5) 2476 2477 /* Low priority grace period page size */ 2478 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 2479 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 2480 2481 /* Disable display A/B trickle feed */ 2482 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 2483 2484 /* Set display plane priority */ 2485 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 2486 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 2487 2488 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 2489 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 2490 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 2491 2492 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 2493 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 2494 #define CM0_IZ_OPT_DISABLE (1<<6) 2495 #define CM0_ZR_OPT_DISABLE (1<<5) 2496 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 2497 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 2498 #define CM0_COLOR_EVICT_DISABLE (1<<3) 2499 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 2500 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 2501 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 2502 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 2503 #define GFX_FLSH_CNTL_EN (1<<0) 2504 #define ECOSKPD _MMIO(0x21d0) 2505 #define ECO_GATING_CX_ONLY (1<<3) 2506 #define ECO_FLIP_DONE (1<<0) 2507 2508 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 2509 #define RC_OP_FLUSH_ENABLE (1<<0) 2510 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 2511 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 2512 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 2513 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 2514 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) 2515 2516 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 2517 #define GEN6_BLITTER_LOCK_SHIFT 16 2518 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 2519 2520 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 2521 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 2522 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 2523 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 2524 2525 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 2526 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 2527 2528 /* Fuse readout registers for GT */ 2529 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 2530 #define CHV_FGT_DISABLE_SS0 (1 << 10) 2531 #define CHV_FGT_DISABLE_SS1 (1 << 11) 2532 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 2533 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 2534 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 2535 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 2536 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 2537 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 2538 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 2539 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 2540 2541 #define GEN8_FUSE2 _MMIO(0x9120) 2542 #define GEN8_F2_SS_DIS_SHIFT 21 2543 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 2544 #define GEN8_F2_S_ENA_SHIFT 25 2545 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 2546 2547 #define GEN9_F2_SS_DIS_SHIFT 20 2548 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 2549 2550 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 2551 #define GEN8_EU_DIS0_S0_MASK 0xffffff 2552 #define GEN8_EU_DIS0_S1_SHIFT 24 2553 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 2554 2555 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 2556 #define GEN8_EU_DIS1_S1_MASK 0xffff 2557 #define GEN8_EU_DIS1_S2_SHIFT 16 2558 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 2559 2560 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 2561 #define GEN8_EU_DIS2_S2_MASK 0xff 2562 2563 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4) 2564 2565 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 2566 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 2567 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 2568 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 2569 #define GEN6_BSD_GO_INDICATOR (1 << 4) 2570 2571 /* On modern GEN architectures interrupt control consists of two sets 2572 * of registers. The first set pertains to the ring generating the 2573 * interrupt. The second control is for the functional block generating the 2574 * interrupt. These are PM, GT, DE, etc. 2575 * 2576 * Luckily *knocks on wood* all the ring interrupt bits match up with the 2577 * GT interrupt bits, so we don't need to duplicate the defines. 2578 * 2579 * These defines should cover us well from SNB->HSW with minor exceptions 2580 * it can also work on ILK. 2581 */ 2582 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 2583 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 2584 #define GT_BLT_USER_INTERRUPT (1 << 22) 2585 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 2586 #define GT_BSD_USER_INTERRUPT (1 << 12) 2587 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 2588 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 2589 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 2590 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 2591 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 2592 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 2593 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 2594 #define GT_RENDER_USER_INTERRUPT (1 << 0) 2595 2596 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 2597 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 2598 2599 #define GT_PARITY_ERROR(dev_priv) \ 2600 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 2601 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 2602 2603 /* These are all the "old" interrupts */ 2604 #define ILK_BSD_USER_INTERRUPT (1<<5) 2605 2606 #define I915_PM_INTERRUPT (1<<31) 2607 #define I915_ISP_INTERRUPT (1<<22) 2608 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 2609 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 2610 #define I915_MIPIC_INTERRUPT (1<<19) 2611 #define I915_MIPIA_INTERRUPT (1<<18) 2612 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 2613 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 2614 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 2615 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 2616 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 2617 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 2618 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 2619 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 2620 #define I915_HWB_OOM_INTERRUPT (1<<13) 2621 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 2622 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 2623 #define I915_MISC_INTERRUPT (1<<11) 2624 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 2625 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 2626 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 2627 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 2628 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 2629 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 2630 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 2631 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 2632 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 2633 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 2634 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 2635 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 2636 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 2637 #define I915_DEBUG_INTERRUPT (1<<2) 2638 #define I915_WINVALID_INTERRUPT (1<<1) 2639 #define I915_USER_INTERRUPT (1<<1) 2640 #define I915_ASLE_INTERRUPT (1<<0) 2641 #define I915_BSD_USER_INTERRUPT (1<<25) 2642 2643 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 2644 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 2645 2646 /* DisplayPort Audio w/ LPE */ 2647 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 2648 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 2649 2650 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 2651 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 2652 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 2653 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 2654 _VLV_AUD_PORT_EN_B_DBG, \ 2655 _VLV_AUD_PORT_EN_C_DBG, \ 2656 _VLV_AUD_PORT_EN_D_DBG) 2657 #define VLV_AMP_MUTE (1 << 1) 2658 2659 #define GEN6_BSD_RNCID _MMIO(0x12198) 2660 2661 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 2662 #define GEN7_FF_SCHED_MASK 0x0077070 2663 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 2664 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 2665 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 2666 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 2667 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 2668 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 2669 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 2670 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 2671 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 2672 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 2673 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 2674 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 2675 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 2676 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 2677 2678 /* 2679 * Framebuffer compression (915+ only) 2680 */ 2681 2682 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 2683 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 2684 #define FBC_CONTROL _MMIO(0x3208) 2685 #define FBC_CTL_EN (1<<31) 2686 #define FBC_CTL_PERIODIC (1<<30) 2687 #define FBC_CTL_INTERVAL_SHIFT (16) 2688 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 2689 #define FBC_CTL_C3_IDLE (1<<13) 2690 #define FBC_CTL_STRIDE_SHIFT (5) 2691 #define FBC_CTL_FENCENO_SHIFT (0) 2692 #define FBC_COMMAND _MMIO(0x320c) 2693 #define FBC_CMD_COMPRESS (1<<0) 2694 #define FBC_STATUS _MMIO(0x3210) 2695 #define FBC_STAT_COMPRESSING (1<<31) 2696 #define FBC_STAT_COMPRESSED (1<<30) 2697 #define FBC_STAT_MODIFIED (1<<29) 2698 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 2699 #define FBC_CONTROL2 _MMIO(0x3214) 2700 #define FBC_CTL_FENCE_DBL (0<<4) 2701 #define FBC_CTL_IDLE_IMM (0<<2) 2702 #define FBC_CTL_IDLE_FULL (1<<2) 2703 #define FBC_CTL_IDLE_LINE (2<<2) 2704 #define FBC_CTL_IDLE_DEBUG (3<<2) 2705 #define FBC_CTL_CPU_FENCE (1<<1) 2706 #define FBC_CTL_PLANE(plane) ((plane)<<0) 2707 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 2708 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 2709 2710 #define FBC_LL_SIZE (1536) 2711 2712 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 2713 #define FBC_LLC_FULLY_OPEN (1<<30) 2714 2715 /* Framebuffer compression for GM45+ */ 2716 #define DPFC_CB_BASE _MMIO(0x3200) 2717 #define DPFC_CONTROL _MMIO(0x3208) 2718 #define DPFC_CTL_EN (1<<31) 2719 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 2720 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 2721 #define DPFC_CTL_FENCE_EN (1<<29) 2722 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 2723 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 2724 #define DPFC_SR_EN (1<<10) 2725 #define DPFC_CTL_LIMIT_1X (0<<6) 2726 #define DPFC_CTL_LIMIT_2X (1<<6) 2727 #define DPFC_CTL_LIMIT_4X (2<<6) 2728 #define DPFC_RECOMP_CTL _MMIO(0x320c) 2729 #define DPFC_RECOMP_STALL_EN (1<<27) 2730 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 2731 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 2732 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 2733 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 2734 #define DPFC_STATUS _MMIO(0x3210) 2735 #define DPFC_INVAL_SEG_SHIFT (16) 2736 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 2737 #define DPFC_COMP_SEG_SHIFT (0) 2738 #define DPFC_COMP_SEG_MASK (0x000007ff) 2739 #define DPFC_STATUS2 _MMIO(0x3214) 2740 #define DPFC_FENCE_YOFF _MMIO(0x3218) 2741 #define DPFC_CHICKEN _MMIO(0x3224) 2742 #define DPFC_HT_MODIFY (1<<31) 2743 2744 /* Framebuffer compression for Ironlake */ 2745 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 2746 #define ILK_DPFC_CONTROL _MMIO(0x43208) 2747 #define FBC_CTL_FALSE_COLOR (1<<10) 2748 /* The bit 28-8 is reserved */ 2749 #define DPFC_RESERVED (0x1FFFFF00) 2750 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 2751 #define ILK_DPFC_STATUS _MMIO(0x43210) 2752 #define ILK_DPFC_COMP_SEG_MASK 0x7ff 2753 #define IVB_FBC_STATUS2 _MMIO(0x43214) 2754 #define IVB_FBC_COMP_SEG_MASK 0x7ff 2755 #define BDW_FBC_COMP_SEG_MASK 0xfff 2756 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 2757 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 2758 #define ILK_DPFC_DISABLE_DUMMY0 (1<<8) 2759 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23) 2760 #define ILK_FBC_RT_BASE _MMIO(0x2128) 2761 #define ILK_FBC_RT_VALID (1<<0) 2762 #define SNB_FBC_FRONT_BUFFER (1<<1) 2763 2764 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 2765 #define ILK_FBCQ_DIS (1<<22) 2766 #define ILK_PABSTRETCH_DIS (1<<21) 2767 2768 2769 /* 2770 * Framebuffer compression for Sandybridge 2771 * 2772 * The following two registers are of type GTTMMADR 2773 */ 2774 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 2775 #define SNB_CPU_FENCE_ENABLE (1<<29) 2776 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 2777 2778 /* Framebuffer compression for Ivybridge */ 2779 #define IVB_FBC_RT_BASE _MMIO(0x7020) 2780 2781 #define IPS_CTL _MMIO(0x43408) 2782 #define IPS_ENABLE (1 << 31) 2783 2784 #define MSG_FBC_REND_STATE _MMIO(0x50380) 2785 #define FBC_REND_NUKE (1<<2) 2786 #define FBC_REND_CACHE_CLEAN (1<<1) 2787 2788 /* 2789 * GPIO regs 2790 */ 2791 #define GPIOA _MMIO(0x5010) 2792 #define GPIOB _MMIO(0x5014) 2793 #define GPIOC _MMIO(0x5018) 2794 #define GPIOD _MMIO(0x501c) 2795 #define GPIOE _MMIO(0x5020) 2796 #define GPIOF _MMIO(0x5024) 2797 #define GPIOG _MMIO(0x5028) 2798 #define GPIOH _MMIO(0x502c) 2799 # define GPIO_CLOCK_DIR_MASK (1 << 0) 2800 # define GPIO_CLOCK_DIR_IN (0 << 1) 2801 # define GPIO_CLOCK_DIR_OUT (1 << 1) 2802 # define GPIO_CLOCK_VAL_MASK (1 << 2) 2803 # define GPIO_CLOCK_VAL_OUT (1 << 3) 2804 # define GPIO_CLOCK_VAL_IN (1 << 4) 2805 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 2806 # define GPIO_DATA_DIR_MASK (1 << 8) 2807 # define GPIO_DATA_DIR_IN (0 << 9) 2808 # define GPIO_DATA_DIR_OUT (1 << 9) 2809 # define GPIO_DATA_VAL_MASK (1 << 10) 2810 # define GPIO_DATA_VAL_OUT (1 << 11) 2811 # define GPIO_DATA_VAL_IN (1 << 12) 2812 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 2813 2814 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 2815 #define GMBUS_RATE_100KHZ (0<<8) 2816 #define GMBUS_RATE_50KHZ (1<<8) 2817 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 2818 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 2819 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 2820 #define GMBUS_PIN_DISABLED 0 2821 #define GMBUS_PIN_SSC 1 2822 #define GMBUS_PIN_VGADDC 2 2823 #define GMBUS_PIN_PANEL 3 2824 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 2825 #define GMBUS_PIN_DPC 4 /* HDMIC */ 2826 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 2827 #define GMBUS_PIN_DPD 6 /* HDMID */ 2828 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 2829 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */ 2830 #define GMBUS_PIN_2_BXT 2 2831 #define GMBUS_PIN_3_BXT 3 2832 #define GMBUS_PIN_4_CNP 4 2833 #define GMBUS_NUM_PINS 7 /* including 0 */ 2834 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 2835 #define GMBUS_SW_CLR_INT (1<<31) 2836 #define GMBUS_SW_RDY (1<<30) 2837 #define GMBUS_ENT (1<<29) /* enable timeout */ 2838 #define GMBUS_CYCLE_NONE (0<<25) 2839 #define GMBUS_CYCLE_WAIT (1<<25) 2840 #define GMBUS_CYCLE_INDEX (2<<25) 2841 #define GMBUS_CYCLE_STOP (4<<25) 2842 #define GMBUS_BYTE_COUNT_SHIFT 16 2843 #define GMBUS_BYTE_COUNT_MAX 256U 2844 #define GMBUS_SLAVE_INDEX_SHIFT 8 2845 #define GMBUS_SLAVE_ADDR_SHIFT 1 2846 #define GMBUS_SLAVE_READ (1<<0) 2847 #define GMBUS_SLAVE_WRITE (0<<0) 2848 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 2849 #define GMBUS_INUSE (1<<15) 2850 #define GMBUS_HW_WAIT_PHASE (1<<14) 2851 #define GMBUS_STALL_TIMEOUT (1<<13) 2852 #define GMBUS_INT (1<<12) 2853 #define GMBUS_HW_RDY (1<<11) 2854 #define GMBUS_SATOER (1<<10) 2855 #define GMBUS_ACTIVE (1<<9) 2856 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 2857 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 2858 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 2859 #define GMBUS_NAK_EN (1<<3) 2860 #define GMBUS_IDLE_EN (1<<2) 2861 #define GMBUS_HW_WAIT_EN (1<<1) 2862 #define GMBUS_HW_RDY_EN (1<<0) 2863 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 2864 #define GMBUS_2BYTE_INDEX_EN (1<<31) 2865 2866 /* 2867 * Clock control & power management 2868 */ 2869 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 2870 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 2871 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 2872 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 2873 2874 #define VGA0 _MMIO(0x6000) 2875 #define VGA1 _MMIO(0x6004) 2876 #define VGA_PD _MMIO(0x6010) 2877 #define VGA0_PD_P2_DIV_4 (1 << 7) 2878 #define VGA0_PD_P1_DIV_2 (1 << 5) 2879 #define VGA0_PD_P1_SHIFT 0 2880 #define VGA0_PD_P1_MASK (0x1f << 0) 2881 #define VGA1_PD_P2_DIV_4 (1 << 15) 2882 #define VGA1_PD_P1_DIV_2 (1 << 13) 2883 #define VGA1_PD_P1_SHIFT 8 2884 #define VGA1_PD_P1_MASK (0x1f << 8) 2885 #define DPLL_VCO_ENABLE (1 << 31) 2886 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 2887 #define DPLL_DVO_2X_MODE (1 << 30) 2888 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 2889 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 2890 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 2891 #define DPLL_VGA_MODE_DIS (1 << 28) 2892 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 2893 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 2894 #define DPLL_MODE_MASK (3 << 26) 2895 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 2896 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 2897 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 2898 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 2899 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 2900 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 2901 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 2902 #define DPLL_LOCK_VLV (1<<15) 2903 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 2904 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) 2905 #define DPLL_SSC_REF_CLK_CHV (1<<13) 2906 #define DPLL_PORTC_READY_MASK (0xf << 4) 2907 #define DPLL_PORTB_READY_MASK (0xf) 2908 2909 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 2910 2911 /* Additional CHV pll/phy registers */ 2912 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 2913 #define DPLL_PORTD_READY_MASK (0xf) 2914 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 2915 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27)) 2916 #define PHY_LDO_DELAY_0NS 0x0 2917 #define PHY_LDO_DELAY_200NS 0x1 2918 #define PHY_LDO_DELAY_600NS 0x2 2919 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) 2920 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11)) 2921 #define PHY_CH_SU_PSR 0x1 2922 #define PHY_CH_DEEP_PSR 0x7 2923 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) 2924 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 2925 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 2926 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 2927 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch)))) 2928 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline)))) 2929 2930 /* 2931 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 2932 * this field (only one bit may be set). 2933 */ 2934 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 2935 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 2936 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 2937 /* i830, required in DVO non-gang */ 2938 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 2939 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 2940 #define PLL_REF_INPUT_DREFCLK (0 << 13) 2941 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 2942 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 2943 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 2944 #define PLL_REF_INPUT_MASK (3 << 13) 2945 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 2946 /* Ironlake */ 2947 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 2948 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 2949 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 2950 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 2951 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 2952 2953 /* 2954 * Parallel to Serial Load Pulse phase selection. 2955 * Selects the phase for the 10X DPLL clock for the PCIe 2956 * digital display port. The range is 4 to 13; 10 or more 2957 * is just a flip delay. The default is 6 2958 */ 2959 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 2960 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 2961 /* 2962 * SDVO multiplier for 945G/GM. Not used on 965. 2963 */ 2964 #define SDVO_MULTIPLIER_MASK 0x000000ff 2965 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 2966 #define SDVO_MULTIPLIER_SHIFT_VGA 0 2967 2968 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 2969 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 2970 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 2971 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 2972 2973 /* 2974 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 2975 * 2976 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 2977 */ 2978 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 2979 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 2980 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 2981 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 2982 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 2983 /* 2984 * SDVO/UDI pixel multiplier. 2985 * 2986 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 2987 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 2988 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 2989 * dummy bytes in the datastream at an increased clock rate, with both sides of 2990 * the link knowing how many bytes are fill. 2991 * 2992 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 2993 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 2994 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 2995 * through an SDVO command. 2996 * 2997 * This register field has values of multiplication factor minus 1, with 2998 * a maximum multiplier of 5 for SDVO. 2999 */ 3000 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 3001 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 3002 /* 3003 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 3004 * This best be set to the default value (3) or the CRT won't work. No, 3005 * I don't entirely understand what this does... 3006 */ 3007 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 3008 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 3009 3010 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 3011 3012 #define _FPA0 0x6040 3013 #define _FPA1 0x6044 3014 #define _FPB0 0x6048 3015 #define _FPB1 0x604c 3016 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 3017 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 3018 #define FP_N_DIV_MASK 0x003f0000 3019 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 3020 #define FP_N_DIV_SHIFT 16 3021 #define FP_M1_DIV_MASK 0x00003f00 3022 #define FP_M1_DIV_SHIFT 8 3023 #define FP_M2_DIV_MASK 0x0000003f 3024 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 3025 #define FP_M2_DIV_SHIFT 0 3026 #define DPLL_TEST _MMIO(0x606c) 3027 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 3028 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 3029 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 3030 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 3031 #define DPLLB_TEST_N_BYPASS (1 << 19) 3032 #define DPLLB_TEST_M_BYPASS (1 << 18) 3033 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 3034 #define DPLLA_TEST_N_BYPASS (1 << 3) 3035 #define DPLLA_TEST_M_BYPASS (1 << 2) 3036 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 3037 #define D_STATE _MMIO(0x6104) 3038 #define DSTATE_GFX_RESET_I830 (1<<6) 3039 #define DSTATE_PLL_D3_OFF (1<<3) 3040 #define DSTATE_GFX_CLOCK_GATING (1<<1) 3041 #define DSTATE_DOT_CLOCK_GATING (1<<0) 3042 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) 3043 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 3044 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 3045 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 3046 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 3047 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 3048 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 3049 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 3050 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 3051 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 3052 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 3053 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 3054 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 3055 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 3056 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 3057 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 3058 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 3059 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 3060 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 3061 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 3062 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 3063 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 3064 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3065 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 3066 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 3067 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 3068 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 3069 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 3070 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 3071 /* 3072 * This bit must be set on the 830 to prevent hangs when turning off the 3073 * overlay scaler. 3074 */ 3075 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 3076 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 3077 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 3078 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 3079 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 3080 3081 #define RENCLK_GATE_D1 _MMIO(0x6204) 3082 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 3083 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 3084 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 3085 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 3086 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 3087 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 3088 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 3089 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 3090 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 3091 /* This bit must be unset on 855,865 */ 3092 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 3093 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 3094 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 3095 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 3096 /* This bit must be set on 855,865. */ 3097 # define SV_CLOCK_GATE_DISABLE (1 << 0) 3098 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 3099 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 3100 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 3101 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 3102 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 3103 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 3104 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 3105 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 3106 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 3107 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 3108 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 3109 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 3110 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 3111 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 3112 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 3113 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 3114 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 3115 3116 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 3117 /* This bit must always be set on 965G/965GM */ 3118 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 3119 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 3120 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 3121 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 3122 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 3123 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 3124 /* This bit must always be set on 965G */ 3125 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 3126 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 3127 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 3128 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 3129 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 3130 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 3131 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 3132 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 3133 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 3134 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 3135 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 3136 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 3137 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 3138 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 3139 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 3140 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 3141 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 3142 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 3143 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 3144 3145 #define RENCLK_GATE_D2 _MMIO(0x6208) 3146 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 3147 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 3148 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 3149 3150 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 3151 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 3152 3153 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 3154 #define DEUC _MMIO(0x6214) /* CRL only */ 3155 3156 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 3157 #define FW_CSPWRDWNEN (1<<15) 3158 3159 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 3160 3161 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 3162 #define CDCLK_FREQ_SHIFT 4 3163 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 3164 #define CZCLK_FREQ_MASK 0xf 3165 3166 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 3167 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 3168 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 3169 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 3170 #define PFI_CREDIT_RESEND (1 << 27) 3171 #define VGA_FAST_MODE_DISABLE (1 << 14) 3172 3173 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 3174 3175 /* 3176 * Palette regs 3177 */ 3178 #define PALETTE_A_OFFSET 0xa000 3179 #define PALETTE_B_OFFSET 0xa800 3180 #define CHV_PALETTE_C_OFFSET 0xc000 3181 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ 3182 dev_priv->info.display_mmio_offset + (i) * 4) 3183 3184 /* MCH MMIO space */ 3185 3186 /* 3187 * MCHBAR mirror. 3188 * 3189 * This mirrors the MCHBAR MMIO space whose location is determined by 3190 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 3191 * every way. It is not accessible from the CP register read instructions. 3192 * 3193 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 3194 * just read. 3195 */ 3196 #define MCHBAR_MIRROR_BASE 0x10000 3197 3198 #define MCHBAR_MIRROR_BASE_SNB 0x140000 3199 3200 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 3201 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 3202 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 3203 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 3204 3205 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 3206 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 3207 3208 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 3209 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 3210 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 3211 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 3212 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 3213 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 3214 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 3215 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 3216 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 3217 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 3218 3219 /* Pineview MCH register contains DDR3 setting */ 3220 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 3221 #define CSHRDDR3CTL_DDR3 (1 << 2) 3222 3223 /* 965 MCH register controlling DRAM channel configuration */ 3224 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 3225 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 3226 3227 /* snb MCH registers for reading the DRAM channel configuration */ 3228 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 3229 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 3230 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 3231 #define MAD_DIMM_ECC_MASK (0x3 << 24) 3232 #define MAD_DIMM_ECC_OFF (0x0 << 24) 3233 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 3234 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 3235 #define MAD_DIMM_ECC_ON (0x3 << 24) 3236 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 3237 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 3238 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 3239 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 3240 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 3241 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 3242 #define MAD_DIMM_A_SELECT (0x1 << 16) 3243 /* DIMM sizes are in multiples of 256mb. */ 3244 #define MAD_DIMM_B_SIZE_SHIFT 8 3245 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 3246 #define MAD_DIMM_A_SIZE_SHIFT 0 3247 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 3248 3249 /* snb MCH registers for priority tuning */ 3250 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 3251 #define MCH_SSKPD_WM0_MASK 0x3f 3252 #define MCH_SSKPD_WM0_VAL 0xc 3253 3254 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) 3255 3256 /* Clocking configuration register */ 3257 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 3258 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 3259 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 3260 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 3261 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 3262 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 3263 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 3264 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 3265 /* 3266 * Note that on at least on ELK the below value is reported for both 3267 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet 3268 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz. 3269 */ 3270 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 3271 #define CLKCFG_FSB_MASK (7 << 0) 3272 #define CLKCFG_MEM_533 (1 << 4) 3273 #define CLKCFG_MEM_667 (2 << 4) 3274 #define CLKCFG_MEM_800 (3 << 4) 3275 #define CLKCFG_MEM_MASK (7 << 4) 3276 3277 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 3278 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 3279 3280 #define TSC1 _MMIO(0x11001) 3281 #define TSE (1<<0) 3282 #define TR1 _MMIO(0x11006) 3283 #define TSFS _MMIO(0x11020) 3284 #define TSFS_SLOPE_MASK 0x0000ff00 3285 #define TSFS_SLOPE_SHIFT 8 3286 #define TSFS_INTR_MASK 0x000000ff 3287 3288 #define CRSTANDVID _MMIO(0x11100) 3289 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 3290 #define PXVFREQ_PX_MASK 0x7f000000 3291 #define PXVFREQ_PX_SHIFT 24 3292 #define VIDFREQ_BASE _MMIO(0x11110) 3293 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 3294 #define VIDFREQ2 _MMIO(0x11114) 3295 #define VIDFREQ3 _MMIO(0x11118) 3296 #define VIDFREQ4 _MMIO(0x1111c) 3297 #define VIDFREQ_P0_MASK 0x1f000000 3298 #define VIDFREQ_P0_SHIFT 24 3299 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 3300 #define VIDFREQ_P0_CSCLK_SHIFT 20 3301 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 3302 #define VIDFREQ_P0_CRCLK_SHIFT 16 3303 #define VIDFREQ_P1_MASK 0x00001f00 3304 #define VIDFREQ_P1_SHIFT 8 3305 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 3306 #define VIDFREQ_P1_CSCLK_SHIFT 4 3307 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 3308 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 3309 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 3310 #define INTTOEXT_MAP3_SHIFT 24 3311 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 3312 #define INTTOEXT_MAP2_SHIFT 16 3313 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 3314 #define INTTOEXT_MAP1_SHIFT 8 3315 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 3316 #define INTTOEXT_MAP0_SHIFT 0 3317 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 3318 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 3319 #define MEMCTL_CMD_MASK 0xe000 3320 #define MEMCTL_CMD_SHIFT 13 3321 #define MEMCTL_CMD_RCLK_OFF 0 3322 #define MEMCTL_CMD_RCLK_ON 1 3323 #define MEMCTL_CMD_CHFREQ 2 3324 #define MEMCTL_CMD_CHVID 3 3325 #define MEMCTL_CMD_VMMOFF 4 3326 #define MEMCTL_CMD_VMMON 5 3327 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 3328 when command complete */ 3329 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 3330 #define MEMCTL_FREQ_SHIFT 8 3331 #define MEMCTL_SFCAVM (1<<7) 3332 #define MEMCTL_TGT_VID_MASK 0x007f 3333 #define MEMIHYST _MMIO(0x1117c) 3334 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 3335 #define MEMINT_RSEXIT_EN (1<<8) 3336 #define MEMINT_CX_SUPR_EN (1<<7) 3337 #define MEMINT_CONT_BUSY_EN (1<<6) 3338 #define MEMINT_AVG_BUSY_EN (1<<5) 3339 #define MEMINT_EVAL_CHG_EN (1<<4) 3340 #define MEMINT_MON_IDLE_EN (1<<3) 3341 #define MEMINT_UP_EVAL_EN (1<<2) 3342 #define MEMINT_DOWN_EVAL_EN (1<<1) 3343 #define MEMINT_SW_CMD_EN (1<<0) 3344 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 3345 #define MEM_RSEXIT_MASK 0xc000 3346 #define MEM_RSEXIT_SHIFT 14 3347 #define MEM_CONT_BUSY_MASK 0x3000 3348 #define MEM_CONT_BUSY_SHIFT 12 3349 #define MEM_AVG_BUSY_MASK 0x0c00 3350 #define MEM_AVG_BUSY_SHIFT 10 3351 #define MEM_EVAL_CHG_MASK 0x0300 3352 #define MEM_EVAL_BUSY_SHIFT 8 3353 #define MEM_MON_IDLE_MASK 0x00c0 3354 #define MEM_MON_IDLE_SHIFT 6 3355 #define MEM_UP_EVAL_MASK 0x0030 3356 #define MEM_UP_EVAL_SHIFT 4 3357 #define MEM_DOWN_EVAL_MASK 0x000c 3358 #define MEM_DOWN_EVAL_SHIFT 2 3359 #define MEM_SW_CMD_MASK 0x0003 3360 #define MEM_INT_STEER_GFX 0 3361 #define MEM_INT_STEER_CMR 1 3362 #define MEM_INT_STEER_SMI 2 3363 #define MEM_INT_STEER_SCI 3 3364 #define MEMINTRSTS _MMIO(0x11184) 3365 #define MEMINT_RSEXIT (1<<7) 3366 #define MEMINT_CONT_BUSY (1<<6) 3367 #define MEMINT_AVG_BUSY (1<<5) 3368 #define MEMINT_EVAL_CHG (1<<4) 3369 #define MEMINT_MON_IDLE (1<<3) 3370 #define MEMINT_UP_EVAL (1<<2) 3371 #define MEMINT_DOWN_EVAL (1<<1) 3372 #define MEMINT_SW_CMD (1<<0) 3373 #define MEMMODECTL _MMIO(0x11190) 3374 #define MEMMODE_BOOST_EN (1<<31) 3375 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 3376 #define MEMMODE_BOOST_FREQ_SHIFT 24 3377 #define MEMMODE_IDLE_MODE_MASK 0x00030000 3378 #define MEMMODE_IDLE_MODE_SHIFT 16 3379 #define MEMMODE_IDLE_MODE_EVAL 0 3380 #define MEMMODE_IDLE_MODE_CONT 1 3381 #define MEMMODE_HWIDLE_EN (1<<15) 3382 #define MEMMODE_SWMODE_EN (1<<14) 3383 #define MEMMODE_RCLK_GATE (1<<13) 3384 #define MEMMODE_HW_UPDATE (1<<12) 3385 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 3386 #define MEMMODE_FSTART_SHIFT 8 3387 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 3388 #define MEMMODE_FMAX_SHIFT 4 3389 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 3390 #define RCBMAXAVG _MMIO(0x1119c) 3391 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 3392 #define SWMEMCMD_RENDER_OFF (0 << 13) 3393 #define SWMEMCMD_RENDER_ON (1 << 13) 3394 #define SWMEMCMD_SWFREQ (2 << 13) 3395 #define SWMEMCMD_TARVID (3 << 13) 3396 #define SWMEMCMD_VRM_OFF (4 << 13) 3397 #define SWMEMCMD_VRM_ON (5 << 13) 3398 #define CMDSTS (1<<12) 3399 #define SFCAVM (1<<11) 3400 #define SWFREQ_MASK 0x0380 /* P0-7 */ 3401 #define SWFREQ_SHIFT 7 3402 #define TARVID_MASK 0x001f 3403 #define MEMSTAT_CTG _MMIO(0x111a0) 3404 #define RCBMINAVG _MMIO(0x111a0) 3405 #define RCUPEI _MMIO(0x111b0) 3406 #define RCDNEI _MMIO(0x111b4) 3407 #define RSTDBYCTL _MMIO(0x111b8) 3408 #define RS1EN (1<<31) 3409 #define RS2EN (1<<30) 3410 #define RS3EN (1<<29) 3411 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 3412 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 3413 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 3414 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 3415 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 3416 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 3417 #define RSX_STATUS_MASK (7<<20) 3418 #define RSX_STATUS_ON (0<<20) 3419 #define RSX_STATUS_RC1 (1<<20) 3420 #define RSX_STATUS_RC1E (2<<20) 3421 #define RSX_STATUS_RS1 (3<<20) 3422 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 3423 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 3424 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 3425 #define RSX_STATUS_RSVD2 (7<<20) 3426 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 3427 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 3428 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 3429 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 3430 #define RS1CONTSAV_MASK (3<<14) 3431 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 3432 #define RS1CONTSAV_RSVD (1<<14) 3433 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 3434 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 3435 #define NORMSLEXLAT_MASK (3<<12) 3436 #define SLOW_RS123 (0<<12) 3437 #define SLOW_RS23 (1<<12) 3438 #define SLOW_RS3 (2<<12) 3439 #define NORMAL_RS123 (3<<12) 3440 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 3441 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 3442 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 3443 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 3444 #define RS_CSTATE_MASK (3<<4) 3445 #define RS_CSTATE_C367_RS1 (0<<4) 3446 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 3447 #define RS_CSTATE_RSVD (2<<4) 3448 #define RS_CSTATE_C367_RS2 (3<<4) 3449 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 3450 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 3451 #define VIDCTL _MMIO(0x111c0) 3452 #define VIDSTS _MMIO(0x111c8) 3453 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 3454 #define MEMSTAT_ILK _MMIO(0x111f8) 3455 #define MEMSTAT_VID_MASK 0x7f00 3456 #define MEMSTAT_VID_SHIFT 8 3457 #define MEMSTAT_PSTATE_MASK 0x00f8 3458 #define MEMSTAT_PSTATE_SHIFT 3 3459 #define MEMSTAT_MON_ACTV (1<<2) 3460 #define MEMSTAT_SRC_CTL_MASK 0x0003 3461 #define MEMSTAT_SRC_CTL_CORE 0 3462 #define MEMSTAT_SRC_CTL_TRB 1 3463 #define MEMSTAT_SRC_CTL_THM 2 3464 #define MEMSTAT_SRC_CTL_STDBY 3 3465 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 3466 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 3467 #define PMMISC _MMIO(0x11214) 3468 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 3469 #define SDEW _MMIO(0x1124c) 3470 #define CSIEW0 _MMIO(0x11250) 3471 #define CSIEW1 _MMIO(0x11254) 3472 #define CSIEW2 _MMIO(0x11258) 3473 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 3474 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 3475 #define MCHAFE _MMIO(0x112c0) 3476 #define CSIEC _MMIO(0x112e0) 3477 #define DMIEC _MMIO(0x112e4) 3478 #define DDREC _MMIO(0x112e8) 3479 #define PEG0EC _MMIO(0x112ec) 3480 #define PEG1EC _MMIO(0x112f0) 3481 #define GFXEC _MMIO(0x112f4) 3482 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 3483 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 3484 #define ECR _MMIO(0x11600) 3485 #define ECR_GPFE (1<<31) 3486 #define ECR_IMONE (1<<30) 3487 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 3488 #define OGW0 _MMIO(0x11608) 3489 #define OGW1 _MMIO(0x1160c) 3490 #define EG0 _MMIO(0x11610) 3491 #define EG1 _MMIO(0x11614) 3492 #define EG2 _MMIO(0x11618) 3493 #define EG3 _MMIO(0x1161c) 3494 #define EG4 _MMIO(0x11620) 3495 #define EG5 _MMIO(0x11624) 3496 #define EG6 _MMIO(0x11628) 3497 #define EG7 _MMIO(0x1162c) 3498 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 3499 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 3500 #define LCFUSE02 _MMIO(0x116c0) 3501 #define LCFUSE_HIV_MASK 0x000000ff 3502 #define CSIPLL0 _MMIO(0x12c10) 3503 #define DDRMPLL1 _MMIO(0X12c20) 3504 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 3505 3506 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 3507 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 3508 3509 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 3510 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 3511 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 3512 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 3513 #define BXT_RP_STATE_CAP _MMIO(0x138170) 3514 3515 /* 3516 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS 3517 * 8300) freezing up around GPU hangs. Looks as if even 3518 * scheduling/timer interrupts start misbehaving if the RPS 3519 * EI/thresholds are "bad", leading to a very sluggish or even 3520 * frozen machine. 3521 */ 3522 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) 3523 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 3524 #define INTERVAL_0_833_US(us) (((us) * 6) / 5) 3525 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ 3526 (IS_GEN9_LP(dev_priv) ? \ 3527 INTERVAL_0_833_US(us) : \ 3528 INTERVAL_1_33_US(us)) : \ 3529 INTERVAL_1_28_US(us)) 3530 3531 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) 3532 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) 3533 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) 3534 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \ 3535 (IS_GEN9_LP(dev_priv) ? \ 3536 INTERVAL_0_833_TO_US(interval) : \ 3537 INTERVAL_1_33_TO_US(interval)) : \ 3538 INTERVAL_1_28_TO_US(interval)) 3539 3540 /* 3541 * Logical Context regs 3542 */ 3543 #define CCID _MMIO(0x2180) 3544 #define CCID_EN BIT(0) 3545 #define CCID_EXTENDED_STATE_RESTORE BIT(2) 3546 #define CCID_EXTENDED_STATE_SAVE BIT(3) 3547 /* 3548 * Notes on SNB/IVB/VLV context size: 3549 * - Power context is saved elsewhere (LLC or stolen) 3550 * - Ring/execlist context is saved on SNB, not on IVB 3551 * - Extended context size already includes render context size 3552 * - We always need to follow the extended context size. 3553 * SNB BSpec has comments indicating that we should use the 3554 * render context size instead if execlists are disabled, but 3555 * based on empirical testing that's just nonsense. 3556 * - Pipelined/VF state is saved on SNB/IVB respectively 3557 * - GT1 size just indicates how much of render context 3558 * doesn't need saving on GT1 3559 */ 3560 #define CXT_SIZE _MMIO(0x21a0) 3561 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 3562 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 3563 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 3564 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 3565 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 3566 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 3567 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 3568 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 3569 #define GEN7_CXT_SIZE _MMIO(0x21a8) 3570 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 3571 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 3572 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 3573 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 3574 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 3575 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 3576 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 3577 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 3578 3579 enum { 3580 INTEL_ADVANCED_CONTEXT = 0, 3581 INTEL_LEGACY_32B_CONTEXT, 3582 INTEL_ADVANCED_AD_CONTEXT, 3583 INTEL_LEGACY_64B_CONTEXT 3584 }; 3585 3586 enum { 3587 FAULT_AND_HANG = 0, 3588 FAULT_AND_HALT, /* Debug only */ 3589 FAULT_AND_STREAM, 3590 FAULT_AND_CONTINUE /* Unsupported */ 3591 }; 3592 3593 #define GEN8_CTX_VALID (1<<0) 3594 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) 3595 #define GEN8_CTX_FORCE_RESTORE (1<<2) 3596 #define GEN8_CTX_L3LLC_COHERENT (1<<5) 3597 #define GEN8_CTX_PRIVILEGE (1<<8) 3598 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 3599 3600 #define GEN8_CTX_ID_SHIFT 32 3601 #define GEN8_CTX_ID_WIDTH 21 3602 3603 #define CHV_CLK_CTL1 _MMIO(0x101100) 3604 #define VLV_CLK_CTL2 _MMIO(0x101104) 3605 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 3606 3607 /* 3608 * Overlay regs 3609 */ 3610 3611 #define OVADD _MMIO(0x30000) 3612 #define DOVSTA _MMIO(0x30008) 3613 #define OC_BUF (0x3<<20) 3614 #define OGAMC5 _MMIO(0x30010) 3615 #define OGAMC4 _MMIO(0x30014) 3616 #define OGAMC3 _MMIO(0x30018) 3617 #define OGAMC2 _MMIO(0x3001c) 3618 #define OGAMC1 _MMIO(0x30020) 3619 #define OGAMC0 _MMIO(0x30024) 3620 3621 /* 3622 * GEN9 clock gating regs 3623 */ 3624 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 3625 #define PWM2_GATING_DIS (1 << 14) 3626 #define PWM1_GATING_DIS (1 << 13) 3627 3628 /* 3629 * Display engine regs 3630 */ 3631 3632 /* Pipe A CRC regs */ 3633 #define _PIPE_CRC_CTL_A 0x60050 3634 #define PIPE_CRC_ENABLE (1 << 31) 3635 /* ivb+ source selection */ 3636 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 3637 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 3638 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 3639 /* ilk+ source selection */ 3640 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 3641 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 3642 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 3643 /* embedded DP port on the north display block, reserved on ivb */ 3644 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 3645 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 3646 /* vlv source selection */ 3647 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 3648 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 3649 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 3650 /* with DP port the pipe source is invalid */ 3651 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 3652 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 3653 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 3654 /* gen3+ source selection */ 3655 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 3656 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 3657 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 3658 /* with DP/TV port the pipe source is invalid */ 3659 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 3660 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 3661 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 3662 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 3663 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 3664 /* gen2 doesn't have source selection bits */ 3665 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 3666 3667 #define _PIPE_CRC_RES_1_A_IVB 0x60064 3668 #define _PIPE_CRC_RES_2_A_IVB 0x60068 3669 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 3670 #define _PIPE_CRC_RES_4_A_IVB 0x60070 3671 #define _PIPE_CRC_RES_5_A_IVB 0x60074 3672 3673 #define _PIPE_CRC_RES_RED_A 0x60060 3674 #define _PIPE_CRC_RES_GREEN_A 0x60064 3675 #define _PIPE_CRC_RES_BLUE_A 0x60068 3676 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 3677 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 3678 3679 /* Pipe B CRC regs */ 3680 #define _PIPE_CRC_RES_1_B_IVB 0x61064 3681 #define _PIPE_CRC_RES_2_B_IVB 0x61068 3682 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 3683 #define _PIPE_CRC_RES_4_B_IVB 0x61070 3684 #define _PIPE_CRC_RES_5_B_IVB 0x61074 3685 3686 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 3687 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 3688 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 3689 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 3690 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 3691 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 3692 3693 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 3694 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 3695 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 3696 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 3697 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 3698 3699 /* Pipe A timing regs */ 3700 #define _HTOTAL_A 0x60000 3701 #define _HBLANK_A 0x60004 3702 #define _HSYNC_A 0x60008 3703 #define _VTOTAL_A 0x6000c 3704 #define _VBLANK_A 0x60010 3705 #define _VSYNC_A 0x60014 3706 #define _PIPEASRC 0x6001c 3707 #define _BCLRPAT_A 0x60020 3708 #define _VSYNCSHIFT_A 0x60028 3709 #define _PIPE_MULT_A 0x6002c 3710 3711 /* Pipe B timing regs */ 3712 #define _HTOTAL_B 0x61000 3713 #define _HBLANK_B 0x61004 3714 #define _HSYNC_B 0x61008 3715 #define _VTOTAL_B 0x6100c 3716 #define _VBLANK_B 0x61010 3717 #define _VSYNC_B 0x61014 3718 #define _PIPEBSRC 0x6101c 3719 #define _BCLRPAT_B 0x61020 3720 #define _VSYNCSHIFT_B 0x61028 3721 #define _PIPE_MULT_B 0x6102c 3722 3723 #define TRANSCODER_A_OFFSET 0x60000 3724 #define TRANSCODER_B_OFFSET 0x61000 3725 #define TRANSCODER_C_OFFSET 0x62000 3726 #define CHV_TRANSCODER_C_OFFSET 0x63000 3727 #define TRANSCODER_EDP_OFFSET 0x6f000 3728 3729 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ 3730 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 3731 dev_priv->info.display_mmio_offset) 3732 3733 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 3734 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 3735 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 3736 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 3737 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 3738 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 3739 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 3740 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 3741 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 3742 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 3743 3744 /* VLV eDP PSR registers */ 3745 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) 3746 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) 3747 #define VLV_EDP_PSR_ENABLE (1<<0) 3748 #define VLV_EDP_PSR_RESET (1<<1) 3749 #define VLV_EDP_PSR_MODE_MASK (7<<2) 3750 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) 3751 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) 3752 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) 3753 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) 3754 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) 3755 #define VLV_EDP_PSR_DBL_FRAME (1<<10) 3756 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) 3757 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 3758 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB) 3759 3760 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) 3761 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) 3762 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) 3763 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) 3764 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) 3765 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB) 3766 3767 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) 3768 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) 3769 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) 3770 #define VLV_EDP_PSR_CURR_STATE_MASK 7 3771 #define VLV_EDP_PSR_DISABLED (0<<0) 3772 #define VLV_EDP_PSR_INACTIVE (1<<0) 3773 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) 3774 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) 3775 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) 3776 #define VLV_EDP_PSR_EXIT (5<<0) 3777 #define VLV_EDP_PSR_IN_TRANS (1<<7) 3778 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) 3779 3780 /* HSW+ eDP PSR registers */ 3781 #define HSW_EDP_PSR_BASE 0x64800 3782 #define BDW_EDP_PSR_BASE 0x6f800 3783 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) 3784 #define EDP_PSR_ENABLE (1<<31) 3785 #define BDW_PSR_SINGLE_FRAME (1<<30) 3786 #define EDP_PSR_LINK_STANDBY (1<<27) 3787 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 3788 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 3789 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 3790 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 3791 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 3792 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 3793 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 3794 #define EDP_PSR_TP1_TP2_SEL (0<<11) 3795 #define EDP_PSR_TP1_TP3_SEL (1<<11) 3796 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 3797 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 3798 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 3799 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 3800 #define EDP_PSR_TP1_TIME_500us (0<<4) 3801 #define EDP_PSR_TP1_TIME_100us (1<<4) 3802 #define EDP_PSR_TP1_TIME_2500us (2<<4) 3803 #define EDP_PSR_TP1_TIME_0us (3<<4) 3804 #define EDP_PSR_IDLE_FRAME_SHIFT 0 3805 3806 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 3807 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ 3808 3809 #define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40) 3810 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 3811 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 3812 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 3813 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 3814 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 3815 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 3816 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 3817 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 3818 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 3819 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 3820 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 3821 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 3822 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 3823 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 3824 #define EDP_PSR_STATUS_COUNT_SHIFT 16 3825 #define EDP_PSR_STATUS_COUNT_MASK 0xf 3826 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 3827 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 3828 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 3829 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 3830 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 3831 #define EDP_PSR_STATUS_IDLE_MASK 0xf 3832 3833 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) 3834 #define EDP_PSR_PERF_CNT_MASK 0xffffff 3835 3836 #define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60) 3837 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28) 3838 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 3839 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 3840 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 3841 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16) 3842 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15) 3843 3844 #define EDP_PSR2_CTL _MMIO(0x6f900) 3845 #define EDP_PSR2_ENABLE (1<<31) 3846 #define EDP_SU_TRACK_ENABLE (1<<30) 3847 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) 3848 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) 3849 #define EDP_PSR2_TP2_TIME_500 (0<<8) 3850 #define EDP_PSR2_TP2_TIME_100 (1<<8) 3851 #define EDP_PSR2_TP2_TIME_2500 (2<<8) 3852 #define EDP_PSR2_TP2_TIME_50 (3<<8) 3853 #define EDP_PSR2_TP2_TIME_MASK (3<<8) 3854 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 3855 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) 3856 #define EDP_PSR2_IDLE_MASK 0xf 3857 #define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4) 3858 3859 #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) 3860 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) 3861 #define EDP_PSR2_STATUS_STATE_SHIFT 28 3862 3863 /* VGA port control */ 3864 #define ADPA _MMIO(0x61100) 3865 #define PCH_ADPA _MMIO(0xe1100) 3866 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 3867 3868 #define ADPA_DAC_ENABLE (1<<31) 3869 #define ADPA_DAC_DISABLE 0 3870 #define ADPA_PIPE_SELECT_MASK (1<<30) 3871 #define ADPA_PIPE_A_SELECT 0 3872 #define ADPA_PIPE_B_SELECT (1<<30) 3873 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 3874 /* CPT uses bits 29:30 for pch transcoder select */ 3875 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3876 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3877 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3878 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3879 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3880 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3881 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3882 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3883 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3884 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3885 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3886 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3887 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3888 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3889 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3890 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3891 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3892 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3893 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3894 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 3895 #define ADPA_SETS_HVPOLARITY 0 3896 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 3897 #define ADPA_VSYNC_CNTL_ENABLE 0 3898 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 3899 #define ADPA_HSYNC_CNTL_ENABLE 0 3900 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 3901 #define ADPA_VSYNC_ACTIVE_LOW 0 3902 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 3903 #define ADPA_HSYNC_ACTIVE_LOW 0 3904 #define ADPA_DPMS_MASK (~(3<<10)) 3905 #define ADPA_DPMS_ON (0<<10) 3906 #define ADPA_DPMS_SUSPEND (1<<10) 3907 #define ADPA_DPMS_STANDBY (2<<10) 3908 #define ADPA_DPMS_OFF (3<<10) 3909 3910 3911 /* Hotplug control (945+ only) */ 3912 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) 3913 #define PORTB_HOTPLUG_INT_EN (1 << 29) 3914 #define PORTC_HOTPLUG_INT_EN (1 << 28) 3915 #define PORTD_HOTPLUG_INT_EN (1 << 27) 3916 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 3917 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 3918 #define TV_HOTPLUG_INT_EN (1 << 18) 3919 #define CRT_HOTPLUG_INT_EN (1 << 9) 3920 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 3921 PORTC_HOTPLUG_INT_EN | \ 3922 PORTD_HOTPLUG_INT_EN | \ 3923 SDVOC_HOTPLUG_INT_EN | \ 3924 SDVOB_HOTPLUG_INT_EN | \ 3925 CRT_HOTPLUG_INT_EN) 3926 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 3927 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 3928 /* must use period 64 on GM45 according to docs */ 3929 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 3930 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 3931 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 3932 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 3933 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 3934 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 3935 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 3936 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 3937 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 3938 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 3939 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 3940 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 3941 3942 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) 3943 /* 3944 * HDMI/DP bits are g4x+ 3945 * 3946 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 3947 * Please check the detailed lore in the commit message for for experimental 3948 * evidence. 3949 */ 3950 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 3951 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 3952 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 3953 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 3954 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 3955 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 3956 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 3957 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 3958 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 3959 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 3960 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 3961 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 3962 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 3963 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 3964 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 3965 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 3966 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 3967 /* CRT/TV common between gen3+ */ 3968 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 3969 #define TV_HOTPLUG_INT_STATUS (1 << 10) 3970 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 3971 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 3972 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 3973 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 3974 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 3975 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 3976 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 3977 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 3978 3979 /* SDVO is different across gen3/4 */ 3980 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 3981 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 3982 /* 3983 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 3984 * since reality corrobates that they're the same as on gen3. But keep these 3985 * bits here (and the comment!) to help any other lost wanderers back onto the 3986 * right tracks. 3987 */ 3988 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 3989 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 3990 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 3991 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 3992 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 3993 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 3994 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 3995 PORTB_HOTPLUG_INT_STATUS | \ 3996 PORTC_HOTPLUG_INT_STATUS | \ 3997 PORTD_HOTPLUG_INT_STATUS) 3998 3999 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 4000 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 4001 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 4002 PORTB_HOTPLUG_INT_STATUS | \ 4003 PORTC_HOTPLUG_INT_STATUS | \ 4004 PORTD_HOTPLUG_INT_STATUS) 4005 4006 /* SDVO and HDMI port control. 4007 * The same register may be used for SDVO or HDMI */ 4008 #define _GEN3_SDVOB 0x61140 4009 #define _GEN3_SDVOC 0x61160 4010 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 4011 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 4012 #define GEN4_HDMIB GEN3_SDVOB 4013 #define GEN4_HDMIC GEN3_SDVOC 4014 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 4015 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 4016 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 4017 #define PCH_SDVOB _MMIO(0xe1140) 4018 #define PCH_HDMIB PCH_SDVOB 4019 #define PCH_HDMIC _MMIO(0xe1150) 4020 #define PCH_HDMID _MMIO(0xe1160) 4021 4022 #define PORT_DFT_I9XX _MMIO(0x61150) 4023 #define DC_BALANCE_RESET (1 << 25) 4024 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) 4025 #define DC_BALANCE_RESET_VLV (1 << 31) 4026 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 4027 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 4028 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 4029 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 4030 4031 /* Gen 3 SDVO bits: */ 4032 #define SDVO_ENABLE (1 << 31) 4033 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 4034 #define SDVO_PIPE_SEL_MASK (1 << 30) 4035 #define SDVO_PIPE_B_SELECT (1 << 30) 4036 #define SDVO_STALL_SELECT (1 << 29) 4037 #define SDVO_INTERRUPT_ENABLE (1 << 26) 4038 /* 4039 * 915G/GM SDVO pixel multiplier. 4040 * Programmed value is multiplier - 1, up to 5x. 4041 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 4042 */ 4043 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 4044 #define SDVO_PORT_MULTIPLY_SHIFT 23 4045 #define SDVO_PHASE_SELECT_MASK (15 << 19) 4046 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 4047 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 4048 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 4049 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 4050 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 4051 #define SDVO_DETECTED (1 << 2) 4052 /* Bits to be preserved when writing */ 4053 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 4054 SDVO_INTERRUPT_ENABLE) 4055 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 4056 4057 /* Gen 4 SDVO/HDMI bits: */ 4058 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 4059 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 4060 #define SDVO_ENCODING_SDVO (0 << 10) 4061 #define SDVO_ENCODING_HDMI (2 << 10) 4062 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 4063 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 4064 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 4065 #define SDVO_AUDIO_ENABLE (1 << 6) 4066 /* VSYNC/HSYNC bits new with 965, default is to be set */ 4067 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 4068 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 4069 4070 /* Gen 5 (IBX) SDVO/HDMI bits: */ 4071 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 4072 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 4073 4074 /* Gen 6 (CPT) SDVO/HDMI bits: */ 4075 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4076 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 4077 4078 /* CHV SDVO/HDMI bits: */ 4079 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 4080 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 4081 4082 4083 /* DVO port control */ 4084 #define _DVOA 0x61120 4085 #define DVOA _MMIO(_DVOA) 4086 #define _DVOB 0x61140 4087 #define DVOB _MMIO(_DVOB) 4088 #define _DVOC 0x61160 4089 #define DVOC _MMIO(_DVOC) 4090 #define DVO_ENABLE (1 << 31) 4091 #define DVO_PIPE_B_SELECT (1 << 30) 4092 #define DVO_PIPE_STALL_UNUSED (0 << 28) 4093 #define DVO_PIPE_STALL (1 << 28) 4094 #define DVO_PIPE_STALL_TV (2 << 28) 4095 #define DVO_PIPE_STALL_MASK (3 << 28) 4096 #define DVO_USE_VGA_SYNC (1 << 15) 4097 #define DVO_DATA_ORDER_I740 (0 << 14) 4098 #define DVO_DATA_ORDER_FP (1 << 14) 4099 #define DVO_VSYNC_DISABLE (1 << 11) 4100 #define DVO_HSYNC_DISABLE (1 << 10) 4101 #define DVO_VSYNC_TRISTATE (1 << 9) 4102 #define DVO_HSYNC_TRISTATE (1 << 8) 4103 #define DVO_BORDER_ENABLE (1 << 7) 4104 #define DVO_DATA_ORDER_GBRG (1 << 6) 4105 #define DVO_DATA_ORDER_RGGB (0 << 6) 4106 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 4107 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 4108 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 4109 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 4110 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 4111 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 4112 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 4113 #define DVO_PRESERVE_MASK (0x7<<24) 4114 #define DVOA_SRCDIM _MMIO(0x61124) 4115 #define DVOB_SRCDIM _MMIO(0x61144) 4116 #define DVOC_SRCDIM _MMIO(0x61164) 4117 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 4118 #define DVO_SRCDIM_VERTICAL_SHIFT 0 4119 4120 /* LVDS port control */ 4121 #define LVDS _MMIO(0x61180) 4122 /* 4123 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 4124 * the DPLL semantics change when the LVDS is assigned to that pipe. 4125 */ 4126 #define LVDS_PORT_EN (1 << 31) 4127 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 4128 #define LVDS_PIPEB_SELECT (1 << 30) 4129 #define LVDS_PIPE_MASK (1 << 30) 4130 #define LVDS_PIPE(pipe) ((pipe) << 30) 4131 /* LVDS dithering flag on 965/g4x platform */ 4132 #define LVDS_ENABLE_DITHER (1 << 25) 4133 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 4134 #define LVDS_VSYNC_POLARITY (1 << 21) 4135 #define LVDS_HSYNC_POLARITY (1 << 20) 4136 4137 /* Enable border for unscaled (or aspect-scaled) display */ 4138 #define LVDS_BORDER_ENABLE (1 << 15) 4139 /* 4140 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 4141 * pixel. 4142 */ 4143 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 4144 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 4145 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 4146 /* 4147 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 4148 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 4149 * on. 4150 */ 4151 #define LVDS_A3_POWER_MASK (3 << 6) 4152 #define LVDS_A3_POWER_DOWN (0 << 6) 4153 #define LVDS_A3_POWER_UP (3 << 6) 4154 /* 4155 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 4156 * is set. 4157 */ 4158 #define LVDS_CLKB_POWER_MASK (3 << 4) 4159 #define LVDS_CLKB_POWER_DOWN (0 << 4) 4160 #define LVDS_CLKB_POWER_UP (3 << 4) 4161 /* 4162 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 4163 * setting for whether we are in dual-channel mode. The B3 pair will 4164 * additionally only be powered up when LVDS_A3_POWER_UP is set. 4165 */ 4166 #define LVDS_B0B3_POWER_MASK (3 << 2) 4167 #define LVDS_B0B3_POWER_DOWN (0 << 2) 4168 #define LVDS_B0B3_POWER_UP (3 << 2) 4169 4170 /* Video Data Island Packet control */ 4171 #define VIDEO_DIP_DATA _MMIO(0x61178) 4172 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 4173 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 4174 * of the infoframe structure specified by CEA-861. */ 4175 #define VIDEO_DIP_DATA_SIZE 32 4176 #define VIDEO_DIP_VSC_DATA_SIZE 36 4177 #define VIDEO_DIP_CTL _MMIO(0x61170) 4178 /* Pre HSW: */ 4179 #define VIDEO_DIP_ENABLE (1 << 31) 4180 #define VIDEO_DIP_PORT(port) ((port) << 29) 4181 #define VIDEO_DIP_PORT_MASK (3 << 29) 4182 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 4183 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 4184 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 4185 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 4186 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 4187 #define VIDEO_DIP_SELECT_AVI (0 << 19) 4188 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 4189 #define VIDEO_DIP_SELECT_SPD (3 << 19) 4190 #define VIDEO_DIP_SELECT_MASK (3 << 19) 4191 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 4192 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 4193 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4194 #define VIDEO_DIP_FREQ_MASK (3 << 16) 4195 /* HSW and later: */ 4196 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4197 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4198 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4199 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 4200 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4201 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4202 4203 /* Panel power sequencing */ 4204 #define PPS_BASE 0x61200 4205 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4206 #define PCH_PPS_BASE 0xC7200 4207 4208 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 4209 PPS_BASE + (reg) + \ 4210 (pps_idx) * 0x100) 4211 4212 #define _PP_STATUS 0x61200 4213 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 4214 #define PP_ON (1 << 31) 4215 /* 4216 * Indicates that all dependencies of the panel are on: 4217 * 4218 * - PLL enabled 4219 * - pipe enabled 4220 * - LVDS/DVOB/DVOC on 4221 */ 4222 #define PP_READY (1 << 30) 4223 #define PP_SEQUENCE_NONE (0 << 28) 4224 #define PP_SEQUENCE_POWER_UP (1 << 28) 4225 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 4226 #define PP_SEQUENCE_MASK (3 << 28) 4227 #define PP_SEQUENCE_SHIFT 28 4228 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 4229 #define PP_SEQUENCE_STATE_MASK 0x0000000f 4230 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 4231 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 4232 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 4233 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 4234 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 4235 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 4236 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 4237 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 4238 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 4239 4240 #define _PP_CONTROL 0x61204 4241 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 4242 #define PANEL_UNLOCK_REGS (0xabcd << 16) 4243 #define PANEL_UNLOCK_MASK (0xffff << 16) 4244 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0 4245 #define BXT_POWER_CYCLE_DELAY_SHIFT 4 4246 #define EDP_FORCE_VDD (1 << 3) 4247 #define EDP_BLC_ENABLE (1 << 2) 4248 #define PANEL_POWER_RESET (1 << 1) 4249 #define PANEL_POWER_OFF (0 << 0) 4250 #define PANEL_POWER_ON (1 << 0) 4251 4252 #define _PP_ON_DELAYS 0x61208 4253 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 4254 #define PANEL_PORT_SELECT_SHIFT 30 4255 #define PANEL_PORT_SELECT_MASK (3 << 30) 4256 #define PANEL_PORT_SELECT_LVDS (0 << 30) 4257 #define PANEL_PORT_SELECT_DPA (1 << 30) 4258 #define PANEL_PORT_SELECT_DPC (2 << 30) 4259 #define PANEL_PORT_SELECT_DPD (3 << 30) 4260 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 4261 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000 4262 #define PANEL_POWER_UP_DELAY_SHIFT 16 4263 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff 4264 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 4265 4266 #define _PP_OFF_DELAYS 0x6120C 4267 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 4268 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000 4269 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 4270 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff 4271 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 4272 4273 #define _PP_DIVISOR 0x61210 4274 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 4275 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00 4276 #define PP_REFERENCE_DIVIDER_SHIFT 8 4277 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f 4278 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 4279 4280 /* Panel fitting */ 4281 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) 4282 #define PFIT_ENABLE (1 << 31) 4283 #define PFIT_PIPE_MASK (3 << 29) 4284 #define PFIT_PIPE_SHIFT 29 4285 #define VERT_INTERP_DISABLE (0 << 10) 4286 #define VERT_INTERP_BILINEAR (1 << 10) 4287 #define VERT_INTERP_MASK (3 << 10) 4288 #define VERT_AUTO_SCALE (1 << 9) 4289 #define HORIZ_INTERP_DISABLE (0 << 6) 4290 #define HORIZ_INTERP_BILINEAR (1 << 6) 4291 #define HORIZ_INTERP_MASK (3 << 6) 4292 #define HORIZ_AUTO_SCALE (1 << 5) 4293 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 4294 #define PFIT_FILTER_FUZZY (0 << 24) 4295 #define PFIT_SCALING_AUTO (0 << 26) 4296 #define PFIT_SCALING_PROGRAMMED (1 << 26) 4297 #define PFIT_SCALING_PILLAR (2 << 26) 4298 #define PFIT_SCALING_LETTER (3 << 26) 4299 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) 4300 /* Pre-965 */ 4301 #define PFIT_VERT_SCALE_SHIFT 20 4302 #define PFIT_VERT_SCALE_MASK 0xfff00000 4303 #define PFIT_HORIZ_SCALE_SHIFT 4 4304 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 4305 /* 965+ */ 4306 #define PFIT_VERT_SCALE_SHIFT_965 16 4307 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 4308 #define PFIT_HORIZ_SCALE_SHIFT_965 0 4309 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 4310 4311 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) 4312 4313 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 4314 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 4315 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 4316 _VLV_BLC_PWM_CTL2_B) 4317 4318 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 4319 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 4320 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 4321 _VLV_BLC_PWM_CTL_B) 4322 4323 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 4324 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 4325 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 4326 _VLV_BLC_HIST_CTL_B) 4327 4328 /* Backlight control */ 4329 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 4330 #define BLM_PWM_ENABLE (1 << 31) 4331 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 4332 #define BLM_PIPE_SELECT (1 << 29) 4333 #define BLM_PIPE_SELECT_IVB (3 << 29) 4334 #define BLM_PIPE_A (0 << 29) 4335 #define BLM_PIPE_B (1 << 29) 4336 #define BLM_PIPE_C (2 << 29) /* ivb + */ 4337 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 4338 #define BLM_TRANSCODER_B BLM_PIPE_B 4339 #define BLM_TRANSCODER_C BLM_PIPE_C 4340 #define BLM_TRANSCODER_EDP (3 << 29) 4341 #define BLM_PIPE(pipe) ((pipe) << 29) 4342 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 4343 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 4344 #define BLM_PHASE_IN_ENABLE (1 << 25) 4345 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 4346 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 4347 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 4348 #define BLM_PHASE_IN_COUNT_SHIFT (8) 4349 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 4350 #define BLM_PHASE_IN_INCR_SHIFT (0) 4351 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 4352 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) 4353 /* 4354 * This is the most significant 15 bits of the number of backlight cycles in a 4355 * complete cycle of the modulated backlight control. 4356 * 4357 * The actual value is this field multiplied by two. 4358 */ 4359 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 4360 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 4361 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 4362 /* 4363 * This is the number of cycles out of the backlight modulation cycle for which 4364 * the backlight is on. 4365 * 4366 * This field must be no greater than the number of cycles in the complete 4367 * backlight modulation cycle. 4368 */ 4369 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 4370 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 4371 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 4372 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 4373 4374 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) 4375 #define BLM_HISTOGRAM_ENABLE (1 << 31) 4376 4377 /* New registers for PCH-split platforms. Safe where new bits show up, the 4378 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 4379 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 4380 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 4381 4382 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 4383 4384 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 4385 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 4386 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 4387 #define BLM_PCH_PWM_ENABLE (1 << 31) 4388 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 4389 #define BLM_PCH_POLARITY (1 << 29) 4390 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 4391 4392 #define UTIL_PIN_CTL _MMIO(0x48400) 4393 #define UTIL_PIN_ENABLE (1 << 31) 4394 4395 #define UTIL_PIN_PIPE(x) ((x) << 29) 4396 #define UTIL_PIN_PIPE_MASK (3 << 29) 4397 #define UTIL_PIN_MODE_PWM (1 << 24) 4398 #define UTIL_PIN_MODE_MASK (0xf << 24) 4399 #define UTIL_PIN_POLARITY (1 << 22) 4400 4401 /* BXT backlight register definition. */ 4402 #define _BXT_BLC_PWM_CTL1 0xC8250 4403 #define BXT_BLC_PWM_ENABLE (1 << 31) 4404 #define BXT_BLC_PWM_POLARITY (1 << 29) 4405 #define _BXT_BLC_PWM_FREQ1 0xC8254 4406 #define _BXT_BLC_PWM_DUTY1 0xC8258 4407 4408 #define _BXT_BLC_PWM_CTL2 0xC8350 4409 #define _BXT_BLC_PWM_FREQ2 0xC8354 4410 #define _BXT_BLC_PWM_DUTY2 0xC8358 4411 4412 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 4413 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 4414 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 4415 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 4416 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 4417 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 4418 4419 #define PCH_GTC_CTL _MMIO(0xe7000) 4420 #define PCH_GTC_ENABLE (1 << 31) 4421 4422 /* TV port control */ 4423 #define TV_CTL _MMIO(0x68000) 4424 /* Enables the TV encoder */ 4425 # define TV_ENC_ENABLE (1 << 31) 4426 /* Sources the TV encoder input from pipe B instead of A. */ 4427 # define TV_ENC_PIPEB_SELECT (1 << 30) 4428 /* Outputs composite video (DAC A only) */ 4429 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 4430 /* Outputs SVideo video (DAC B/C) */ 4431 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 4432 /* Outputs Component video (DAC A/B/C) */ 4433 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 4434 /* Outputs Composite and SVideo (DAC A/B/C) */ 4435 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 4436 # define TV_TRILEVEL_SYNC (1 << 21) 4437 /* Enables slow sync generation (945GM only) */ 4438 # define TV_SLOW_SYNC (1 << 20) 4439 /* Selects 4x oversampling for 480i and 576p */ 4440 # define TV_OVERSAMPLE_4X (0 << 18) 4441 /* Selects 2x oversampling for 720p and 1080i */ 4442 # define TV_OVERSAMPLE_2X (1 << 18) 4443 /* Selects no oversampling for 1080p */ 4444 # define TV_OVERSAMPLE_NONE (2 << 18) 4445 /* Selects 8x oversampling */ 4446 # define TV_OVERSAMPLE_8X (3 << 18) 4447 /* Selects progressive mode rather than interlaced */ 4448 # define TV_PROGRESSIVE (1 << 17) 4449 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 4450 # define TV_PAL_BURST (1 << 16) 4451 /* Field for setting delay of Y compared to C */ 4452 # define TV_YC_SKEW_MASK (7 << 12) 4453 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 4454 # define TV_ENC_SDP_FIX (1 << 11) 4455 /* 4456 * Enables a fix for the 915GM only. 4457 * 4458 * Not sure what it does. 4459 */ 4460 # define TV_ENC_C0_FIX (1 << 10) 4461 /* Bits that must be preserved by software */ 4462 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 4463 # define TV_FUSE_STATE_MASK (3 << 4) 4464 /* Read-only state that reports all features enabled */ 4465 # define TV_FUSE_STATE_ENABLED (0 << 4) 4466 /* Read-only state that reports that Macrovision is disabled in hardware*/ 4467 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 4468 /* Read-only state that reports that TV-out is disabled in hardware. */ 4469 # define TV_FUSE_STATE_DISABLED (2 << 4) 4470 /* Normal operation */ 4471 # define TV_TEST_MODE_NORMAL (0 << 0) 4472 /* Encoder test pattern 1 - combo pattern */ 4473 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 4474 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 4475 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 4476 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 4477 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 4478 /* Encoder test pattern 4 - random noise */ 4479 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 4480 /* Encoder test pattern 5 - linear color ramps */ 4481 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 4482 /* 4483 * This test mode forces the DACs to 50% of full output. 4484 * 4485 * This is used for load detection in combination with TVDAC_SENSE_MASK 4486 */ 4487 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 4488 # define TV_TEST_MODE_MASK (7 << 0) 4489 4490 #define TV_DAC _MMIO(0x68004) 4491 # define TV_DAC_SAVE 0x00ffff00 4492 /* 4493 * Reports that DAC state change logic has reported change (RO). 4494 * 4495 * This gets cleared when TV_DAC_STATE_EN is cleared 4496 */ 4497 # define TVDAC_STATE_CHG (1 << 31) 4498 # define TVDAC_SENSE_MASK (7 << 28) 4499 /* Reports that DAC A voltage is above the detect threshold */ 4500 # define TVDAC_A_SENSE (1 << 30) 4501 /* Reports that DAC B voltage is above the detect threshold */ 4502 # define TVDAC_B_SENSE (1 << 29) 4503 /* Reports that DAC C voltage is above the detect threshold */ 4504 # define TVDAC_C_SENSE (1 << 28) 4505 /* 4506 * Enables DAC state detection logic, for load-based TV detection. 4507 * 4508 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 4509 * to off, for load detection to work. 4510 */ 4511 # define TVDAC_STATE_CHG_EN (1 << 27) 4512 /* Sets the DAC A sense value to high */ 4513 # define TVDAC_A_SENSE_CTL (1 << 26) 4514 /* Sets the DAC B sense value to high */ 4515 # define TVDAC_B_SENSE_CTL (1 << 25) 4516 /* Sets the DAC C sense value to high */ 4517 # define TVDAC_C_SENSE_CTL (1 << 24) 4518 /* Overrides the ENC_ENABLE and DAC voltage levels */ 4519 # define DAC_CTL_OVERRIDE (1 << 7) 4520 /* Sets the slew rate. Must be preserved in software */ 4521 # define ENC_TVDAC_SLEW_FAST (1 << 6) 4522 # define DAC_A_1_3_V (0 << 4) 4523 # define DAC_A_1_1_V (1 << 4) 4524 # define DAC_A_0_7_V (2 << 4) 4525 # define DAC_A_MASK (3 << 4) 4526 # define DAC_B_1_3_V (0 << 2) 4527 # define DAC_B_1_1_V (1 << 2) 4528 # define DAC_B_0_7_V (2 << 2) 4529 # define DAC_B_MASK (3 << 2) 4530 # define DAC_C_1_3_V (0 << 0) 4531 # define DAC_C_1_1_V (1 << 0) 4532 # define DAC_C_0_7_V (2 << 0) 4533 # define DAC_C_MASK (3 << 0) 4534 4535 /* 4536 * CSC coefficients are stored in a floating point format with 9 bits of 4537 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 4538 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 4539 * -1 (0x3) being the only legal negative value. 4540 */ 4541 #define TV_CSC_Y _MMIO(0x68010) 4542 # define TV_RY_MASK 0x07ff0000 4543 # define TV_RY_SHIFT 16 4544 # define TV_GY_MASK 0x00000fff 4545 # define TV_GY_SHIFT 0 4546 4547 #define TV_CSC_Y2 _MMIO(0x68014) 4548 # define TV_BY_MASK 0x07ff0000 4549 # define TV_BY_SHIFT 16 4550 /* 4551 * Y attenuation for component video. 4552 * 4553 * Stored in 1.9 fixed point. 4554 */ 4555 # define TV_AY_MASK 0x000003ff 4556 # define TV_AY_SHIFT 0 4557 4558 #define TV_CSC_U _MMIO(0x68018) 4559 # define TV_RU_MASK 0x07ff0000 4560 # define TV_RU_SHIFT 16 4561 # define TV_GU_MASK 0x000007ff 4562 # define TV_GU_SHIFT 0 4563 4564 #define TV_CSC_U2 _MMIO(0x6801c) 4565 # define TV_BU_MASK 0x07ff0000 4566 # define TV_BU_SHIFT 16 4567 /* 4568 * U attenuation for component video. 4569 * 4570 * Stored in 1.9 fixed point. 4571 */ 4572 # define TV_AU_MASK 0x000003ff 4573 # define TV_AU_SHIFT 0 4574 4575 #define TV_CSC_V _MMIO(0x68020) 4576 # define TV_RV_MASK 0x0fff0000 4577 # define TV_RV_SHIFT 16 4578 # define TV_GV_MASK 0x000007ff 4579 # define TV_GV_SHIFT 0 4580 4581 #define TV_CSC_V2 _MMIO(0x68024) 4582 # define TV_BV_MASK 0x07ff0000 4583 # define TV_BV_SHIFT 16 4584 /* 4585 * V attenuation for component video. 4586 * 4587 * Stored in 1.9 fixed point. 4588 */ 4589 # define TV_AV_MASK 0x000007ff 4590 # define TV_AV_SHIFT 0 4591 4592 #define TV_CLR_KNOBS _MMIO(0x68028) 4593 /* 2s-complement brightness adjustment */ 4594 # define TV_BRIGHTNESS_MASK 0xff000000 4595 # define TV_BRIGHTNESS_SHIFT 24 4596 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 4597 # define TV_CONTRAST_MASK 0x00ff0000 4598 # define TV_CONTRAST_SHIFT 16 4599 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 4600 # define TV_SATURATION_MASK 0x0000ff00 4601 # define TV_SATURATION_SHIFT 8 4602 /* Hue adjustment, as an integer phase angle in degrees */ 4603 # define TV_HUE_MASK 0x000000ff 4604 # define TV_HUE_SHIFT 0 4605 4606 #define TV_CLR_LEVEL _MMIO(0x6802c) 4607 /* Controls the DAC level for black */ 4608 # define TV_BLACK_LEVEL_MASK 0x01ff0000 4609 # define TV_BLACK_LEVEL_SHIFT 16 4610 /* Controls the DAC level for blanking */ 4611 # define TV_BLANK_LEVEL_MASK 0x000001ff 4612 # define TV_BLANK_LEVEL_SHIFT 0 4613 4614 #define TV_H_CTL_1 _MMIO(0x68030) 4615 /* Number of pixels in the hsync. */ 4616 # define TV_HSYNC_END_MASK 0x1fff0000 4617 # define TV_HSYNC_END_SHIFT 16 4618 /* Total number of pixels minus one in the line (display and blanking). */ 4619 # define TV_HTOTAL_MASK 0x00001fff 4620 # define TV_HTOTAL_SHIFT 0 4621 4622 #define TV_H_CTL_2 _MMIO(0x68034) 4623 /* Enables the colorburst (needed for non-component color) */ 4624 # define TV_BURST_ENA (1 << 31) 4625 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 4626 # define TV_HBURST_START_SHIFT 16 4627 # define TV_HBURST_START_MASK 0x1fff0000 4628 /* Length of the colorburst */ 4629 # define TV_HBURST_LEN_SHIFT 0 4630 # define TV_HBURST_LEN_MASK 0x0001fff 4631 4632 #define TV_H_CTL_3 _MMIO(0x68038) 4633 /* End of hblank, measured in pixels minus one from start of hsync */ 4634 # define TV_HBLANK_END_SHIFT 16 4635 # define TV_HBLANK_END_MASK 0x1fff0000 4636 /* Start of hblank, measured in pixels minus one from start of hsync */ 4637 # define TV_HBLANK_START_SHIFT 0 4638 # define TV_HBLANK_START_MASK 0x0001fff 4639 4640 #define TV_V_CTL_1 _MMIO(0x6803c) 4641 /* XXX */ 4642 # define TV_NBR_END_SHIFT 16 4643 # define TV_NBR_END_MASK 0x07ff0000 4644 /* XXX */ 4645 # define TV_VI_END_F1_SHIFT 8 4646 # define TV_VI_END_F1_MASK 0x00003f00 4647 /* XXX */ 4648 # define TV_VI_END_F2_SHIFT 0 4649 # define TV_VI_END_F2_MASK 0x0000003f 4650 4651 #define TV_V_CTL_2 _MMIO(0x68040) 4652 /* Length of vsync, in half lines */ 4653 # define TV_VSYNC_LEN_MASK 0x07ff0000 4654 # define TV_VSYNC_LEN_SHIFT 16 4655 /* Offset of the start of vsync in field 1, measured in one less than the 4656 * number of half lines. 4657 */ 4658 # define TV_VSYNC_START_F1_MASK 0x00007f00 4659 # define TV_VSYNC_START_F1_SHIFT 8 4660 /* 4661 * Offset of the start of vsync in field 2, measured in one less than the 4662 * number of half lines. 4663 */ 4664 # define TV_VSYNC_START_F2_MASK 0x0000007f 4665 # define TV_VSYNC_START_F2_SHIFT 0 4666 4667 #define TV_V_CTL_3 _MMIO(0x68044) 4668 /* Enables generation of the equalization signal */ 4669 # define TV_EQUAL_ENA (1 << 31) 4670 /* Length of vsync, in half lines */ 4671 # define TV_VEQ_LEN_MASK 0x007f0000 4672 # define TV_VEQ_LEN_SHIFT 16 4673 /* Offset of the start of equalization in field 1, measured in one less than 4674 * the number of half lines. 4675 */ 4676 # define TV_VEQ_START_F1_MASK 0x0007f00 4677 # define TV_VEQ_START_F1_SHIFT 8 4678 /* 4679 * Offset of the start of equalization in field 2, measured in one less than 4680 * the number of half lines. 4681 */ 4682 # define TV_VEQ_START_F2_MASK 0x000007f 4683 # define TV_VEQ_START_F2_SHIFT 0 4684 4685 #define TV_V_CTL_4 _MMIO(0x68048) 4686 /* 4687 * Offset to start of vertical colorburst, measured in one less than the 4688 * number of lines from vertical start. 4689 */ 4690 # define TV_VBURST_START_F1_MASK 0x003f0000 4691 # define TV_VBURST_START_F1_SHIFT 16 4692 /* 4693 * Offset to the end of vertical colorburst, measured in one less than the 4694 * number of lines from the start of NBR. 4695 */ 4696 # define TV_VBURST_END_F1_MASK 0x000000ff 4697 # define TV_VBURST_END_F1_SHIFT 0 4698 4699 #define TV_V_CTL_5 _MMIO(0x6804c) 4700 /* 4701 * Offset to start of vertical colorburst, measured in one less than the 4702 * number of lines from vertical start. 4703 */ 4704 # define TV_VBURST_START_F2_MASK 0x003f0000 4705 # define TV_VBURST_START_F2_SHIFT 16 4706 /* 4707 * Offset to the end of vertical colorburst, measured in one less than the 4708 * number of lines from the start of NBR. 4709 */ 4710 # define TV_VBURST_END_F2_MASK 0x000000ff 4711 # define TV_VBURST_END_F2_SHIFT 0 4712 4713 #define TV_V_CTL_6 _MMIO(0x68050) 4714 /* 4715 * Offset to start of vertical colorburst, measured in one less than the 4716 * number of lines from vertical start. 4717 */ 4718 # define TV_VBURST_START_F3_MASK 0x003f0000 4719 # define TV_VBURST_START_F3_SHIFT 16 4720 /* 4721 * Offset to the end of vertical colorburst, measured in one less than the 4722 * number of lines from the start of NBR. 4723 */ 4724 # define TV_VBURST_END_F3_MASK 0x000000ff 4725 # define TV_VBURST_END_F3_SHIFT 0 4726 4727 #define TV_V_CTL_7 _MMIO(0x68054) 4728 /* 4729 * Offset to start of vertical colorburst, measured in one less than the 4730 * number of lines from vertical start. 4731 */ 4732 # define TV_VBURST_START_F4_MASK 0x003f0000 4733 # define TV_VBURST_START_F4_SHIFT 16 4734 /* 4735 * Offset to the end of vertical colorburst, measured in one less than the 4736 * number of lines from the start of NBR. 4737 */ 4738 # define TV_VBURST_END_F4_MASK 0x000000ff 4739 # define TV_VBURST_END_F4_SHIFT 0 4740 4741 #define TV_SC_CTL_1 _MMIO(0x68060) 4742 /* Turns on the first subcarrier phase generation DDA */ 4743 # define TV_SC_DDA1_EN (1 << 31) 4744 /* Turns on the first subcarrier phase generation DDA */ 4745 # define TV_SC_DDA2_EN (1 << 30) 4746 /* Turns on the first subcarrier phase generation DDA */ 4747 # define TV_SC_DDA3_EN (1 << 29) 4748 /* Sets the subcarrier DDA to reset frequency every other field */ 4749 # define TV_SC_RESET_EVERY_2 (0 << 24) 4750 /* Sets the subcarrier DDA to reset frequency every fourth field */ 4751 # define TV_SC_RESET_EVERY_4 (1 << 24) 4752 /* Sets the subcarrier DDA to reset frequency every eighth field */ 4753 # define TV_SC_RESET_EVERY_8 (2 << 24) 4754 /* Sets the subcarrier DDA to never reset the frequency */ 4755 # define TV_SC_RESET_NEVER (3 << 24) 4756 /* Sets the peak amplitude of the colorburst.*/ 4757 # define TV_BURST_LEVEL_MASK 0x00ff0000 4758 # define TV_BURST_LEVEL_SHIFT 16 4759 /* Sets the increment of the first subcarrier phase generation DDA */ 4760 # define TV_SCDDA1_INC_MASK 0x00000fff 4761 # define TV_SCDDA1_INC_SHIFT 0 4762 4763 #define TV_SC_CTL_2 _MMIO(0x68064) 4764 /* Sets the rollover for the second subcarrier phase generation DDA */ 4765 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 4766 # define TV_SCDDA2_SIZE_SHIFT 16 4767 /* Sets the increent of the second subcarrier phase generation DDA */ 4768 # define TV_SCDDA2_INC_MASK 0x00007fff 4769 # define TV_SCDDA2_INC_SHIFT 0 4770 4771 #define TV_SC_CTL_3 _MMIO(0x68068) 4772 /* Sets the rollover for the third subcarrier phase generation DDA */ 4773 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 4774 # define TV_SCDDA3_SIZE_SHIFT 16 4775 /* Sets the increent of the third subcarrier phase generation DDA */ 4776 # define TV_SCDDA3_INC_MASK 0x00007fff 4777 # define TV_SCDDA3_INC_SHIFT 0 4778 4779 #define TV_WIN_POS _MMIO(0x68070) 4780 /* X coordinate of the display from the start of horizontal active */ 4781 # define TV_XPOS_MASK 0x1fff0000 4782 # define TV_XPOS_SHIFT 16 4783 /* Y coordinate of the display from the start of vertical active (NBR) */ 4784 # define TV_YPOS_MASK 0x00000fff 4785 # define TV_YPOS_SHIFT 0 4786 4787 #define TV_WIN_SIZE _MMIO(0x68074) 4788 /* Horizontal size of the display window, measured in pixels*/ 4789 # define TV_XSIZE_MASK 0x1fff0000 4790 # define TV_XSIZE_SHIFT 16 4791 /* 4792 * Vertical size of the display window, measured in pixels. 4793 * 4794 * Must be even for interlaced modes. 4795 */ 4796 # define TV_YSIZE_MASK 0x00000fff 4797 # define TV_YSIZE_SHIFT 0 4798 4799 #define TV_FILTER_CTL_1 _MMIO(0x68080) 4800 /* 4801 * Enables automatic scaling calculation. 4802 * 4803 * If set, the rest of the registers are ignored, and the calculated values can 4804 * be read back from the register. 4805 */ 4806 # define TV_AUTO_SCALE (1 << 31) 4807 /* 4808 * Disables the vertical filter. 4809 * 4810 * This is required on modes more than 1024 pixels wide */ 4811 # define TV_V_FILTER_BYPASS (1 << 29) 4812 /* Enables adaptive vertical filtering */ 4813 # define TV_VADAPT (1 << 28) 4814 # define TV_VADAPT_MODE_MASK (3 << 26) 4815 /* Selects the least adaptive vertical filtering mode */ 4816 # define TV_VADAPT_MODE_LEAST (0 << 26) 4817 /* Selects the moderately adaptive vertical filtering mode */ 4818 # define TV_VADAPT_MODE_MODERATE (1 << 26) 4819 /* Selects the most adaptive vertical filtering mode */ 4820 # define TV_VADAPT_MODE_MOST (3 << 26) 4821 /* 4822 * Sets the horizontal scaling factor. 4823 * 4824 * This should be the fractional part of the horizontal scaling factor divided 4825 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 4826 * 4827 * (src width - 1) / ((oversample * dest width) - 1) 4828 */ 4829 # define TV_HSCALE_FRAC_MASK 0x00003fff 4830 # define TV_HSCALE_FRAC_SHIFT 0 4831 4832 #define TV_FILTER_CTL_2 _MMIO(0x68084) 4833 /* 4834 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 4835 * 4836 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 4837 */ 4838 # define TV_VSCALE_INT_MASK 0x00038000 4839 # define TV_VSCALE_INT_SHIFT 15 4840 /* 4841 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 4842 * 4843 * \sa TV_VSCALE_INT_MASK 4844 */ 4845 # define TV_VSCALE_FRAC_MASK 0x00007fff 4846 # define TV_VSCALE_FRAC_SHIFT 0 4847 4848 #define TV_FILTER_CTL_3 _MMIO(0x68088) 4849 /* 4850 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 4851 * 4852 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 4853 * 4854 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 4855 */ 4856 # define TV_VSCALE_IP_INT_MASK 0x00038000 4857 # define TV_VSCALE_IP_INT_SHIFT 15 4858 /* 4859 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 4860 * 4861 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 4862 * 4863 * \sa TV_VSCALE_IP_INT_MASK 4864 */ 4865 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 4866 # define TV_VSCALE_IP_FRAC_SHIFT 0 4867 4868 #define TV_CC_CONTROL _MMIO(0x68090) 4869 # define TV_CC_ENABLE (1 << 31) 4870 /* 4871 * Specifies which field to send the CC data in. 4872 * 4873 * CC data is usually sent in field 0. 4874 */ 4875 # define TV_CC_FID_MASK (1 << 27) 4876 # define TV_CC_FID_SHIFT 27 4877 /* Sets the horizontal position of the CC data. Usually 135. */ 4878 # define TV_CC_HOFF_MASK 0x03ff0000 4879 # define TV_CC_HOFF_SHIFT 16 4880 /* Sets the vertical position of the CC data. Usually 21 */ 4881 # define TV_CC_LINE_MASK 0x0000003f 4882 # define TV_CC_LINE_SHIFT 0 4883 4884 #define TV_CC_DATA _MMIO(0x68094) 4885 # define TV_CC_RDY (1 << 31) 4886 /* Second word of CC data to be transmitted. */ 4887 # define TV_CC_DATA_2_MASK 0x007f0000 4888 # define TV_CC_DATA_2_SHIFT 16 4889 /* First word of CC data to be transmitted. */ 4890 # define TV_CC_DATA_1_MASK 0x0000007f 4891 # define TV_CC_DATA_1_SHIFT 0 4892 4893 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 4894 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 4895 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 4896 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 4897 4898 /* Display Port */ 4899 #define DP_A _MMIO(0x64000) /* eDP */ 4900 #define DP_B _MMIO(0x64100) 4901 #define DP_C _MMIO(0x64200) 4902 #define DP_D _MMIO(0x64300) 4903 4904 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 4905 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 4906 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 4907 4908 #define DP_PORT_EN (1 << 31) 4909 #define DP_PIPEB_SELECT (1 << 30) 4910 #define DP_PIPE_MASK (1 << 30) 4911 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 4912 #define DP_PIPE_MASK_CHV (3 << 16) 4913 4914 /* Link training mode - select a suitable mode for each stage */ 4915 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 4916 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 4917 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 4918 #define DP_LINK_TRAIN_OFF (3 << 28) 4919 #define DP_LINK_TRAIN_MASK (3 << 28) 4920 #define DP_LINK_TRAIN_SHIFT 28 4921 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 4922 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 4923 4924 /* CPT Link training mode */ 4925 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 4926 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 4927 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 4928 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 4929 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 4930 #define DP_LINK_TRAIN_SHIFT_CPT 8 4931 4932 /* Signal voltages. These are mostly controlled by the other end */ 4933 #define DP_VOLTAGE_0_4 (0 << 25) 4934 #define DP_VOLTAGE_0_6 (1 << 25) 4935 #define DP_VOLTAGE_0_8 (2 << 25) 4936 #define DP_VOLTAGE_1_2 (3 << 25) 4937 #define DP_VOLTAGE_MASK (7 << 25) 4938 #define DP_VOLTAGE_SHIFT 25 4939 4940 /* Signal pre-emphasis levels, like voltages, the other end tells us what 4941 * they want 4942 */ 4943 #define DP_PRE_EMPHASIS_0 (0 << 22) 4944 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 4945 #define DP_PRE_EMPHASIS_6 (2 << 22) 4946 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 4947 #define DP_PRE_EMPHASIS_MASK (7 << 22) 4948 #define DP_PRE_EMPHASIS_SHIFT 22 4949 4950 /* How many wires to use. I guess 3 was too hard */ 4951 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 4952 #define DP_PORT_WIDTH_MASK (7 << 19) 4953 #define DP_PORT_WIDTH_SHIFT 19 4954 4955 /* Mystic DPCD version 1.1 special mode */ 4956 #define DP_ENHANCED_FRAMING (1 << 18) 4957 4958 /* eDP */ 4959 #define DP_PLL_FREQ_270MHZ (0 << 16) 4960 #define DP_PLL_FREQ_162MHZ (1 << 16) 4961 #define DP_PLL_FREQ_MASK (3 << 16) 4962 4963 /* locked once port is enabled */ 4964 #define DP_PORT_REVERSAL (1 << 15) 4965 4966 /* eDP */ 4967 #define DP_PLL_ENABLE (1 << 14) 4968 4969 /* sends the clock on lane 15 of the PEG for debug */ 4970 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 4971 4972 #define DP_SCRAMBLING_DISABLE (1 << 12) 4973 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 4974 4975 /* limit RGB values to avoid confusing TVs */ 4976 #define DP_COLOR_RANGE_16_235 (1 << 8) 4977 4978 /* Turn on the audio link */ 4979 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 4980 4981 /* vs and hs sync polarity */ 4982 #define DP_SYNC_VS_HIGH (1 << 4) 4983 #define DP_SYNC_HS_HIGH (1 << 3) 4984 4985 /* A fantasy */ 4986 #define DP_DETECTED (1 << 2) 4987 4988 /* The aux channel provides a way to talk to the 4989 * signal sink for DDC etc. Max packet size supported 4990 * is 20 bytes in each direction, hence the 5 fixed 4991 * data registers 4992 */ 4993 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) 4994 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) 4995 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) 4996 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) 4997 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) 4998 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) 4999 5000 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) 5001 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) 5002 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) 5003 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) 5004 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) 5005 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) 5006 5007 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) 5008 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) 5009 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) 5010 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) 5011 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) 5012 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) 5013 5014 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) 5015 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) 5016 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) 5017 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) 5018 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) 5019 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) 5020 5021 #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 5022 #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5023 5024 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 5025 #define DP_AUX_CH_CTL_DONE (1 << 30) 5026 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 5027 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 5028 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 5029 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 5030 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 5031 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 5032 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 5033 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 5034 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 5035 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 5036 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 5037 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 5038 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 5039 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 5040 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 5041 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 5042 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 5043 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 5044 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 5045 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 5046 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 5047 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 5048 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 5049 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 5050 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 5051 5052 /* 5053 * Computing GMCH M and N values for the Display Port link 5054 * 5055 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 5056 * 5057 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 5058 * 5059 * The GMCH value is used internally 5060 * 5061 * bytes_per_pixel is the number of bytes coming out of the plane, 5062 * which is after the LUTs, so we want the bytes for our color format. 5063 * For our current usage, this is always 3, one byte for R, G and B. 5064 */ 5065 #define _PIPEA_DATA_M_G4X 0x70050 5066 #define _PIPEB_DATA_M_G4X 0x71050 5067 5068 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 5069 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 5070 #define TU_SIZE_SHIFT 25 5071 #define TU_SIZE_MASK (0x3f << 25) 5072 5073 #define DATA_LINK_M_N_MASK (0xffffff) 5074 #define DATA_LINK_N_MAX (0x800000) 5075 5076 #define _PIPEA_DATA_N_G4X 0x70054 5077 #define _PIPEB_DATA_N_G4X 0x71054 5078 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 5079 5080 /* 5081 * Computing Link M and N values for the Display Port link 5082 * 5083 * Link M / N = pixel_clock / ls_clk 5084 * 5085 * (the DP spec calls pixel_clock the 'strm_clk') 5086 * 5087 * The Link value is transmitted in the Main Stream 5088 * Attributes and VB-ID. 5089 */ 5090 5091 #define _PIPEA_LINK_M_G4X 0x70060 5092 #define _PIPEB_LINK_M_G4X 0x71060 5093 #define PIPEA_DP_LINK_M_MASK (0xffffff) 5094 5095 #define _PIPEA_LINK_N_G4X 0x70064 5096 #define _PIPEB_LINK_N_G4X 0x71064 5097 #define PIPEA_DP_LINK_N_MASK (0xffffff) 5098 5099 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 5100 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 5101 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 5102 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 5103 5104 /* Display & cursor control */ 5105 5106 /* Pipe A */ 5107 #define _PIPEADSL 0x70000 5108 #define DSL_LINEMASK_GEN2 0x00000fff 5109 #define DSL_LINEMASK_GEN3 0x00001fff 5110 #define _PIPEACONF 0x70008 5111 #define PIPECONF_ENABLE (1<<31) 5112 #define PIPECONF_DISABLE 0 5113 #define PIPECONF_DOUBLE_WIDE (1<<30) 5114 #define I965_PIPECONF_ACTIVE (1<<30) 5115 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 5116 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 5117 #define PIPECONF_SINGLE_WIDE 0 5118 #define PIPECONF_PIPE_UNLOCKED 0 5119 #define PIPECONF_PIPE_LOCKED (1<<25) 5120 #define PIPECONF_PALETTE 0 5121 #define PIPECONF_GAMMA (1<<24) 5122 #define PIPECONF_FORCE_BORDER (1<<25) 5123 #define PIPECONF_INTERLACE_MASK (7 << 21) 5124 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 5125 /* Note that pre-gen3 does not support interlaced display directly. Panel 5126 * fitting must be disabled on pre-ilk for interlaced. */ 5127 #define PIPECONF_PROGRESSIVE (0 << 21) 5128 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 5129 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 5130 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 5131 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 5132 /* Ironlake and later have a complete new set of values for interlaced. PFIT 5133 * means panel fitter required, PF means progressive fetch, DBL means power 5134 * saving pixel doubling. */ 5135 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 5136 #define PIPECONF_INTERLACED_ILK (3 << 21) 5137 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 5138 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 5139 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 5140 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 5141 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 5142 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 5143 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 5144 #define PIPECONF_BPC_MASK (0x7 << 5) 5145 #define PIPECONF_8BPC (0<<5) 5146 #define PIPECONF_10BPC (1<<5) 5147 #define PIPECONF_6BPC (2<<5) 5148 #define PIPECONF_12BPC (3<<5) 5149 #define PIPECONF_DITHER_EN (1<<4) 5150 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 5151 #define PIPECONF_DITHER_TYPE_SP (0<<2) 5152 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 5153 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 5154 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 5155 #define _PIPEASTAT 0x70024 5156 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 5157 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 5158 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 5159 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 5160 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 5161 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 5162 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 5163 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 5164 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 5165 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 5166 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 5167 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 5168 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 5169 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 5170 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 5171 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 5172 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 5173 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 5174 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 5175 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 5176 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 5177 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 5178 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 5179 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 5180 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 5181 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 5182 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 5183 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 5184 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 5185 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 5186 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 5187 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 5188 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 5189 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 5190 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 5191 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 5192 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 5193 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 5194 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 5195 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 5196 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 5197 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 5198 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 5199 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 5200 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 5201 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 5202 5203 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 5204 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 5205 5206 #define PIPE_A_OFFSET 0x70000 5207 #define PIPE_B_OFFSET 0x71000 5208 #define PIPE_C_OFFSET 0x72000 5209 #define CHV_PIPE_C_OFFSET 0x74000 5210 /* 5211 * There's actually no pipe EDP. Some pipe registers have 5212 * simply shifted from the pipe to the transcoder, while 5213 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 5214 * to access such registers in transcoder EDP. 5215 */ 5216 #define PIPE_EDP_OFFSET 0x7f000 5217 5218 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ 5219 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 5220 dev_priv->info.display_mmio_offset) 5221 5222 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 5223 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 5224 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 5225 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 5226 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 5227 5228 #define _PIPE_MISC_A 0x70030 5229 #define _PIPE_MISC_B 0x71030 5230 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 5231 #define PIPEMISC_DITHER_8_BPC (0<<5) 5232 #define PIPEMISC_DITHER_10_BPC (1<<5) 5233 #define PIPEMISC_DITHER_6_BPC (2<<5) 5234 #define PIPEMISC_DITHER_12_BPC (3<<5) 5235 #define PIPEMISC_DITHER_ENABLE (1<<4) 5236 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 5237 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 5238 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 5239 5240 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 5241 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 5242 #define PIPEB_HLINE_INT_EN (1<<28) 5243 #define PIPEB_VBLANK_INT_EN (1<<27) 5244 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 5245 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 5246 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 5247 #define PIPE_PSR_INT_EN (1<<22) 5248 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 5249 #define PIPEA_HLINE_INT_EN (1<<20) 5250 #define PIPEA_VBLANK_INT_EN (1<<19) 5251 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 5252 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 5253 #define PLANEA_FLIPDONE_INT_EN (1<<16) 5254 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 5255 #define PIPEC_HLINE_INT_EN (1<<12) 5256 #define PIPEC_VBLANK_INT_EN (1<<11) 5257 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 5258 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 5259 #define PLANEC_FLIPDONE_INT_EN (1<<8) 5260 5261 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 5262 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 5263 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 5264 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 5265 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 5266 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 5267 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 5268 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 5269 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 5270 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 5271 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 5272 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 5273 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 5274 #define DPINVGTT_EN_MASK 0xff0000 5275 #define DPINVGTT_EN_MASK_CHV 0xfff0000 5276 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 5277 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 5278 #define PLANEC_INVALID_GTT_STATUS (1<<9) 5279 #define CURSORC_INVALID_GTT_STATUS (1<<8) 5280 #define CURSORB_INVALID_GTT_STATUS (1<<7) 5281 #define CURSORA_INVALID_GTT_STATUS (1<<6) 5282 #define SPRITED_INVALID_GTT_STATUS (1<<5) 5283 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 5284 #define PLANEB_INVALID_GTT_STATUS (1<<3) 5285 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 5286 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 5287 #define PLANEA_INVALID_GTT_STATUS (1<<0) 5288 #define DPINVGTT_STATUS_MASK 0xff 5289 #define DPINVGTT_STATUS_MASK_CHV 0xfff 5290 5291 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) 5292 #define DSPARB_CSTART_MASK (0x7f << 7) 5293 #define DSPARB_CSTART_SHIFT 7 5294 #define DSPARB_BSTART_MASK (0x7f) 5295 #define DSPARB_BSTART_SHIFT 0 5296 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 5297 #define DSPARB_AEND_SHIFT 0 5298 #define DSPARB_SPRITEA_SHIFT_VLV 0 5299 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 5300 #define DSPARB_SPRITEB_SHIFT_VLV 8 5301 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 5302 #define DSPARB_SPRITEC_SHIFT_VLV 16 5303 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 5304 #define DSPARB_SPRITED_SHIFT_VLV 24 5305 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 5306 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 5307 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 5308 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 5309 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 5310 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 5311 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 5312 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 5313 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 5314 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 5315 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 5316 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 5317 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 5318 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 5319 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 5320 #define DSPARB_SPRITEE_SHIFT_VLV 0 5321 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 5322 #define DSPARB_SPRITEF_SHIFT_VLV 8 5323 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 5324 5325 /* pnv/gen4/g4x/vlv/chv */ 5326 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) 5327 #define DSPFW_SR_SHIFT 23 5328 #define DSPFW_SR_MASK (0x1ff<<23) 5329 #define DSPFW_CURSORB_SHIFT 16 5330 #define DSPFW_CURSORB_MASK (0x3f<<16) 5331 #define DSPFW_PLANEB_SHIFT 8 5332 #define DSPFW_PLANEB_MASK (0x7f<<8) 5333 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 5334 #define DSPFW_PLANEA_SHIFT 0 5335 #define DSPFW_PLANEA_MASK (0x7f<<0) 5336 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 5337 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) 5338 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 5339 #define DSPFW_FBC_SR_SHIFT 28 5340 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 5341 #define DSPFW_FBC_HPLL_SR_SHIFT 24 5342 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 5343 #define DSPFW_SPRITEB_SHIFT (16) 5344 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 5345 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 5346 #define DSPFW_CURSORA_SHIFT 8 5347 #define DSPFW_CURSORA_MASK (0x3f<<8) 5348 #define DSPFW_PLANEC_OLD_SHIFT 0 5349 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ 5350 #define DSPFW_SPRITEA_SHIFT 0 5351 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 5352 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 5353 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) 5354 #define DSPFW_HPLL_SR_EN (1<<31) 5355 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 5356 #define DSPFW_CURSOR_SR_SHIFT 24 5357 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 5358 #define DSPFW_HPLL_CURSOR_SHIFT 16 5359 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 5360 #define DSPFW_HPLL_SR_SHIFT 0 5361 #define DSPFW_HPLL_SR_MASK (0x1ff<<0) 5362 5363 /* vlv/chv */ 5364 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 5365 #define DSPFW_SPRITEB_WM1_SHIFT 16 5366 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 5367 #define DSPFW_CURSORA_WM1_SHIFT 8 5368 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 5369 #define DSPFW_SPRITEA_WM1_SHIFT 0 5370 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 5371 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 5372 #define DSPFW_PLANEB_WM1_SHIFT 24 5373 #define DSPFW_PLANEB_WM1_MASK (0xff<<24) 5374 #define DSPFW_PLANEA_WM1_SHIFT 16 5375 #define DSPFW_PLANEA_WM1_MASK (0xff<<16) 5376 #define DSPFW_CURSORB_WM1_SHIFT 8 5377 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 5378 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 5379 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 5380 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 5381 #define DSPFW_SR_WM1_SHIFT 0 5382 #define DSPFW_SR_WM1_MASK (0x1ff<<0) 5383 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 5384 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 5385 #define DSPFW_SPRITED_WM1_SHIFT 24 5386 #define DSPFW_SPRITED_WM1_MASK (0xff<<24) 5387 #define DSPFW_SPRITED_SHIFT 16 5388 #define DSPFW_SPRITED_MASK_VLV (0xff<<16) 5389 #define DSPFW_SPRITEC_WM1_SHIFT 8 5390 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 5391 #define DSPFW_SPRITEC_SHIFT 0 5392 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) 5393 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 5394 #define DSPFW_SPRITEF_WM1_SHIFT 24 5395 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 5396 #define DSPFW_SPRITEF_SHIFT 16 5397 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) 5398 #define DSPFW_SPRITEE_WM1_SHIFT 8 5399 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 5400 #define DSPFW_SPRITEE_SHIFT 0 5401 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) 5402 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 5403 #define DSPFW_PLANEC_WM1_SHIFT 24 5404 #define DSPFW_PLANEC_WM1_MASK (0xff<<24) 5405 #define DSPFW_PLANEC_SHIFT 16 5406 #define DSPFW_PLANEC_MASK_VLV (0xff<<16) 5407 #define DSPFW_CURSORC_WM1_SHIFT 8 5408 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 5409 #define DSPFW_CURSORC_SHIFT 0 5410 #define DSPFW_CURSORC_MASK (0x3f<<0) 5411 5412 /* vlv/chv high order bits */ 5413 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 5414 #define DSPFW_SR_HI_SHIFT 24 5415 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 5416 #define DSPFW_SPRITEF_HI_SHIFT 23 5417 #define DSPFW_SPRITEF_HI_MASK (1<<23) 5418 #define DSPFW_SPRITEE_HI_SHIFT 22 5419 #define DSPFW_SPRITEE_HI_MASK (1<<22) 5420 #define DSPFW_PLANEC_HI_SHIFT 21 5421 #define DSPFW_PLANEC_HI_MASK (1<<21) 5422 #define DSPFW_SPRITED_HI_SHIFT 20 5423 #define DSPFW_SPRITED_HI_MASK (1<<20) 5424 #define DSPFW_SPRITEC_HI_SHIFT 16 5425 #define DSPFW_SPRITEC_HI_MASK (1<<16) 5426 #define DSPFW_PLANEB_HI_SHIFT 12 5427 #define DSPFW_PLANEB_HI_MASK (1<<12) 5428 #define DSPFW_SPRITEB_HI_SHIFT 8 5429 #define DSPFW_SPRITEB_HI_MASK (1<<8) 5430 #define DSPFW_SPRITEA_HI_SHIFT 4 5431 #define DSPFW_SPRITEA_HI_MASK (1<<4) 5432 #define DSPFW_PLANEA_HI_SHIFT 0 5433 #define DSPFW_PLANEA_HI_MASK (1<<0) 5434 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 5435 #define DSPFW_SR_WM1_HI_SHIFT 24 5436 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 5437 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 5438 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 5439 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 5440 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 5441 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 5442 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 5443 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 5444 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 5445 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 5446 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 5447 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 5448 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 5449 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 5450 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 5451 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 5452 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 5453 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 5454 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 5455 5456 /* drain latency register values*/ 5457 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 5458 #define DDL_CURSOR_SHIFT 24 5459 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 5460 #define DDL_PLANE_SHIFT 0 5461 #define DDL_PRECISION_HIGH (1<<7) 5462 #define DDL_PRECISION_LOW (0<<7) 5463 #define DRAIN_LATENCY_MASK 0x7f 5464 5465 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 5466 #define CBR_PND_DEADLINE_DISABLE (1<<31) 5467 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30) 5468 5469 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 5470 #define CBR_DPLLBMD_PIPE_C (1<<29) 5471 #define CBR_DPLLBMD_PIPE_B (1<<18) 5472 5473 /* FIFO watermark sizes etc */ 5474 #define G4X_FIFO_LINE_SIZE 64 5475 #define I915_FIFO_LINE_SIZE 64 5476 #define I830_FIFO_LINE_SIZE 32 5477 5478 #define VALLEYVIEW_FIFO_SIZE 255 5479 #define G4X_FIFO_SIZE 127 5480 #define I965_FIFO_SIZE 512 5481 #define I945_FIFO_SIZE 127 5482 #define I915_FIFO_SIZE 95 5483 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 5484 #define I830_FIFO_SIZE 95 5485 5486 #define VALLEYVIEW_MAX_WM 0xff 5487 #define G4X_MAX_WM 0x3f 5488 #define I915_MAX_WM 0x3f 5489 5490 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 5491 #define PINEVIEW_FIFO_LINE_SIZE 64 5492 #define PINEVIEW_MAX_WM 0x1ff 5493 #define PINEVIEW_DFT_WM 0x3f 5494 #define PINEVIEW_DFT_HPLLOFF_WM 0 5495 #define PINEVIEW_GUARD_WM 10 5496 #define PINEVIEW_CURSOR_FIFO 64 5497 #define PINEVIEW_CURSOR_MAX_WM 0x3f 5498 #define PINEVIEW_CURSOR_DFT_WM 0 5499 #define PINEVIEW_CURSOR_GUARD_WM 5 5500 5501 #define VALLEYVIEW_CURSOR_MAX_WM 64 5502 #define I965_CURSOR_FIFO 64 5503 #define I965_CURSOR_MAX_WM 32 5504 #define I965_CURSOR_DFT_WM 8 5505 5506 /* Watermark register definitions for SKL */ 5507 #define _CUR_WM_A_0 0x70140 5508 #define _CUR_WM_B_0 0x71140 5509 #define _PLANE_WM_1_A_0 0x70240 5510 #define _PLANE_WM_1_B_0 0x71240 5511 #define _PLANE_WM_2_A_0 0x70340 5512 #define _PLANE_WM_2_B_0 0x71340 5513 #define _PLANE_WM_TRANS_1_A_0 0x70268 5514 #define _PLANE_WM_TRANS_1_B_0 0x71268 5515 #define _PLANE_WM_TRANS_2_A_0 0x70368 5516 #define _PLANE_WM_TRANS_2_B_0 0x71368 5517 #define _CUR_WM_TRANS_A_0 0x70168 5518 #define _CUR_WM_TRANS_B_0 0x71168 5519 #define PLANE_WM_EN (1 << 31) 5520 #define PLANE_WM_LINES_SHIFT 14 5521 #define PLANE_WM_LINES_MASK 0x1f 5522 #define PLANE_WM_BLOCKS_MASK 0x3ff 5523 5524 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 5525 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 5526 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 5527 5528 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 5529 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 5530 #define _PLANE_WM_BASE(pipe, plane) \ 5531 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 5532 #define PLANE_WM(pipe, plane, level) \ 5533 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 5534 #define _PLANE_WM_TRANS_1(pipe) \ 5535 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 5536 #define _PLANE_WM_TRANS_2(pipe) \ 5537 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 5538 #define PLANE_WM_TRANS(pipe, plane) \ 5539 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 5540 5541 /* define the Watermark register on Ironlake */ 5542 #define WM0_PIPEA_ILK _MMIO(0x45100) 5543 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 5544 #define WM0_PIPE_PLANE_SHIFT 16 5545 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 5546 #define WM0_PIPE_SPRITE_SHIFT 8 5547 #define WM0_PIPE_CURSOR_MASK (0xff) 5548 5549 #define WM0_PIPEB_ILK _MMIO(0x45104) 5550 #define WM0_PIPEC_IVB _MMIO(0x45200) 5551 #define WM1_LP_ILK _MMIO(0x45108) 5552 #define WM1_LP_SR_EN (1<<31) 5553 #define WM1_LP_LATENCY_SHIFT 24 5554 #define WM1_LP_LATENCY_MASK (0x7f<<24) 5555 #define WM1_LP_FBC_MASK (0xf<<20) 5556 #define WM1_LP_FBC_SHIFT 20 5557 #define WM1_LP_FBC_SHIFT_BDW 19 5558 #define WM1_LP_SR_MASK (0x7ff<<8) 5559 #define WM1_LP_SR_SHIFT 8 5560 #define WM1_LP_CURSOR_MASK (0xff) 5561 #define WM2_LP_ILK _MMIO(0x4510c) 5562 #define WM2_LP_EN (1<<31) 5563 #define WM3_LP_ILK _MMIO(0x45110) 5564 #define WM3_LP_EN (1<<31) 5565 #define WM1S_LP_ILK _MMIO(0x45120) 5566 #define WM2S_LP_IVB _MMIO(0x45124) 5567 #define WM3S_LP_IVB _MMIO(0x45128) 5568 #define WM1S_LP_EN (1<<31) 5569 5570 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 5571 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 5572 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 5573 5574 /* Memory latency timer register */ 5575 #define MLTR_ILK _MMIO(0x11222) 5576 #define MLTR_WM1_SHIFT 0 5577 #define MLTR_WM2_SHIFT 8 5578 /* the unit of memory self-refresh latency time is 0.5us */ 5579 #define ILK_SRLT_MASK 0x3f 5580 5581 5582 /* the address where we get all kinds of latency value */ 5583 #define SSKPD _MMIO(0x5d10) 5584 #define SSKPD_WM_MASK 0x3f 5585 #define SSKPD_WM0_SHIFT 0 5586 #define SSKPD_WM1_SHIFT 8 5587 #define SSKPD_WM2_SHIFT 16 5588 #define SSKPD_WM3_SHIFT 24 5589 5590 /* 5591 * The two pipe frame counter registers are not synchronized, so 5592 * reading a stable value is somewhat tricky. The following code 5593 * should work: 5594 * 5595 * do { 5596 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 5597 * PIPE_FRAME_HIGH_SHIFT; 5598 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 5599 * PIPE_FRAME_LOW_SHIFT); 5600 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 5601 * PIPE_FRAME_HIGH_SHIFT); 5602 * } while (high1 != high2); 5603 * frame = (high1 << 8) | low1; 5604 */ 5605 #define _PIPEAFRAMEHIGH 0x70040 5606 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 5607 #define PIPE_FRAME_HIGH_SHIFT 0 5608 #define _PIPEAFRAMEPIXEL 0x70044 5609 #define PIPE_FRAME_LOW_MASK 0xff000000 5610 #define PIPE_FRAME_LOW_SHIFT 24 5611 #define PIPE_PIXEL_MASK 0x00ffffff 5612 #define PIPE_PIXEL_SHIFT 0 5613 /* GM45+ just has to be different */ 5614 #define _PIPEA_FRMCOUNT_G4X 0x70040 5615 #define _PIPEA_FLIPCOUNT_G4X 0x70044 5616 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 5617 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 5618 5619 /* Cursor A & B regs */ 5620 #define _CURACNTR 0x70080 5621 /* Old style CUR*CNTR flags (desktop 8xx) */ 5622 #define CURSOR_ENABLE 0x80000000 5623 #define CURSOR_GAMMA_ENABLE 0x40000000 5624 #define CURSOR_STRIDE_SHIFT 28 5625 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 5626 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 5627 #define CURSOR_FORMAT_SHIFT 24 5628 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 5629 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 5630 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 5631 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 5632 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 5633 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 5634 /* New style CUR*CNTR flags */ 5635 #define CURSOR_MODE 0x27 5636 #define CURSOR_MODE_DISABLE 0x00 5637 #define CURSOR_MODE_128_32B_AX 0x02 5638 #define CURSOR_MODE_256_32B_AX 0x03 5639 #define CURSOR_MODE_64_32B_AX 0x07 5640 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 5641 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 5642 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 5643 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) 5644 #define MCURSOR_GAMMA_ENABLE (1 << 26) 5645 #define CURSOR_ROTATE_180 (1<<15) 5646 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 5647 #define _CURABASE 0x70084 5648 #define _CURAPOS 0x70088 5649 #define CURSOR_POS_MASK 0x007FF 5650 #define CURSOR_POS_SIGN 0x8000 5651 #define CURSOR_X_SHIFT 0 5652 #define CURSOR_Y_SHIFT 16 5653 #define CURSIZE _MMIO(0x700a0) /* 845/865 */ 5654 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 5655 #define CUR_FBC_CTL_EN (1 << 31) 5656 #define _CURBCNTR 0x700c0 5657 #define _CURBBASE 0x700c4 5658 #define _CURBPOS 0x700c8 5659 5660 #define _CURBCNTR_IVB 0x71080 5661 #define _CURBBASE_IVB 0x71084 5662 #define _CURBPOS_IVB 0x71088 5663 5664 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ 5665 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 5666 dev_priv->info.display_mmio_offset) 5667 5668 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 5669 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 5670 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 5671 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 5672 5673 #define CURSOR_A_OFFSET 0x70080 5674 #define CURSOR_B_OFFSET 0x700c0 5675 #define CHV_CURSOR_C_OFFSET 0x700e0 5676 #define IVB_CURSOR_B_OFFSET 0x71080 5677 #define IVB_CURSOR_C_OFFSET 0x72080 5678 5679 /* Display A control */ 5680 #define _DSPACNTR 0x70180 5681 #define DISPLAY_PLANE_ENABLE (1<<31) 5682 #define DISPLAY_PLANE_DISABLE 0 5683 #define DISPPLANE_GAMMA_ENABLE (1<<30) 5684 #define DISPPLANE_GAMMA_DISABLE 0 5685 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 5686 #define DISPPLANE_YUV422 (0x0<<26) 5687 #define DISPPLANE_8BPP (0x2<<26) 5688 #define DISPPLANE_BGRA555 (0x3<<26) 5689 #define DISPPLANE_BGRX555 (0x4<<26) 5690 #define DISPPLANE_BGRX565 (0x5<<26) 5691 #define DISPPLANE_BGRX888 (0x6<<26) 5692 #define DISPPLANE_BGRA888 (0x7<<26) 5693 #define DISPPLANE_RGBX101010 (0x8<<26) 5694 #define DISPPLANE_RGBA101010 (0x9<<26) 5695 #define DISPPLANE_BGRX101010 (0xa<<26) 5696 #define DISPPLANE_RGBX161616 (0xc<<26) 5697 #define DISPPLANE_RGBX888 (0xe<<26) 5698 #define DISPPLANE_RGBA888 (0xf<<26) 5699 #define DISPPLANE_STEREO_ENABLE (1<<25) 5700 #define DISPPLANE_STEREO_DISABLE 0 5701 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 5702 #define DISPPLANE_SEL_PIPE_SHIFT 24 5703 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 5704 #define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT) 5705 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 5706 #define DISPPLANE_SRC_KEY_DISABLE 0 5707 #define DISPPLANE_LINE_DOUBLE (1<<20) 5708 #define DISPPLANE_NO_LINE_DOUBLE 0 5709 #define DISPPLANE_STEREO_POLARITY_FIRST 0 5710 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 5711 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ 5712 #define DISPPLANE_ROTATE_180 (1<<15) 5713 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 5714 #define DISPPLANE_TILED (1<<10) 5715 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ 5716 #define _DSPAADDR 0x70184 5717 #define _DSPASTRIDE 0x70188 5718 #define _DSPAPOS 0x7018C /* reserved */ 5719 #define _DSPASIZE 0x70190 5720 #define _DSPASURF 0x7019C /* 965+ only */ 5721 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 5722 #define _DSPAOFFSET 0x701A4 /* HSW */ 5723 #define _DSPASURFLIVE 0x701AC 5724 5725 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 5726 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 5727 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 5728 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 5729 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 5730 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 5731 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 5732 #define DSPLINOFF(plane) DSPADDR(plane) 5733 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 5734 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 5735 5736 /* CHV pipe B blender and primary plane */ 5737 #define _CHV_BLEND_A 0x60a00 5738 #define CHV_BLEND_LEGACY (0<<30) 5739 #define CHV_BLEND_ANDROID (1<<30) 5740 #define CHV_BLEND_MPO (2<<30) 5741 #define CHV_BLEND_MASK (3<<30) 5742 #define _CHV_CANVAS_A 0x60a04 5743 #define _PRIMPOS_A 0x60a08 5744 #define _PRIMSIZE_A 0x60a0c 5745 #define _PRIMCNSTALPHA_A 0x60a10 5746 #define PRIM_CONST_ALPHA_ENABLE (1<<31) 5747 5748 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 5749 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 5750 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 5751 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 5752 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 5753 5754 /* Display/Sprite base address macros */ 5755 #define DISP_BASEADDR_MASK (0xfffff000) 5756 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 5757 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 5758 5759 /* 5760 * VBIOS flags 5761 * gen2: 5762 * [00:06] alm,mgm 5763 * [10:16] all 5764 * [30:32] alm,mgm 5765 * gen3+: 5766 * [00:0f] all 5767 * [10:1f] all 5768 * [30:32] all 5769 */ 5770 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) 5771 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) 5772 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) 5773 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 5774 5775 /* Pipe B */ 5776 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 5777 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 5778 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 5779 #define _PIPEBFRAMEHIGH 0x71040 5780 #define _PIPEBFRAMEPIXEL 0x71044 5781 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) 5782 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) 5783 5784 5785 /* Display B control */ 5786 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 5787 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 5788 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 5789 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 5790 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 5791 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 5792 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 5793 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 5794 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 5795 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 5796 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 5797 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 5798 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 5799 5800 /* Sprite A control */ 5801 #define _DVSACNTR 0x72180 5802 #define DVS_ENABLE (1<<31) 5803 #define DVS_GAMMA_ENABLE (1<<30) 5804 #define DVS_PIXFORMAT_MASK (3<<25) 5805 #define DVS_FORMAT_YUV422 (0<<25) 5806 #define DVS_FORMAT_RGBX101010 (1<<25) 5807 #define DVS_FORMAT_RGBX888 (2<<25) 5808 #define DVS_FORMAT_RGBX161616 (3<<25) 5809 #define DVS_PIPE_CSC_ENABLE (1<<24) 5810 #define DVS_SOURCE_KEY (1<<22) 5811 #define DVS_RGB_ORDER_XBGR (1<<20) 5812 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 5813 #define DVS_YUV_ORDER_YUYV (0<<16) 5814 #define DVS_YUV_ORDER_UYVY (1<<16) 5815 #define DVS_YUV_ORDER_YVYU (2<<16) 5816 #define DVS_YUV_ORDER_VYUY (3<<16) 5817 #define DVS_ROTATE_180 (1<<15) 5818 #define DVS_DEST_KEY (1<<2) 5819 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 5820 #define DVS_TILED (1<<10) 5821 #define _DVSALINOFF 0x72184 5822 #define _DVSASTRIDE 0x72188 5823 #define _DVSAPOS 0x7218c 5824 #define _DVSASIZE 0x72190 5825 #define _DVSAKEYVAL 0x72194 5826 #define _DVSAKEYMSK 0x72198 5827 #define _DVSASURF 0x7219c 5828 #define _DVSAKEYMAXVAL 0x721a0 5829 #define _DVSATILEOFF 0x721a4 5830 #define _DVSASURFLIVE 0x721ac 5831 #define _DVSASCALE 0x72204 5832 #define DVS_SCALE_ENABLE (1<<31) 5833 #define DVS_FILTER_MASK (3<<29) 5834 #define DVS_FILTER_MEDIUM (0<<29) 5835 #define DVS_FILTER_ENHANCING (1<<29) 5836 #define DVS_FILTER_SOFTENING (2<<29) 5837 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 5838 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 5839 #define _DVSAGAMC 0x72300 5840 5841 #define _DVSBCNTR 0x73180 5842 #define _DVSBLINOFF 0x73184 5843 #define _DVSBSTRIDE 0x73188 5844 #define _DVSBPOS 0x7318c 5845 #define _DVSBSIZE 0x73190 5846 #define _DVSBKEYVAL 0x73194 5847 #define _DVSBKEYMSK 0x73198 5848 #define _DVSBSURF 0x7319c 5849 #define _DVSBKEYMAXVAL 0x731a0 5850 #define _DVSBTILEOFF 0x731a4 5851 #define _DVSBSURFLIVE 0x731ac 5852 #define _DVSBSCALE 0x73204 5853 #define _DVSBGAMC 0x73300 5854 5855 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 5856 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 5857 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 5858 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 5859 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 5860 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 5861 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 5862 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 5863 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 5864 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 5865 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 5866 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 5867 5868 #define _SPRA_CTL 0x70280 5869 #define SPRITE_ENABLE (1<<31) 5870 #define SPRITE_GAMMA_ENABLE (1<<30) 5871 #define SPRITE_PIXFORMAT_MASK (7<<25) 5872 #define SPRITE_FORMAT_YUV422 (0<<25) 5873 #define SPRITE_FORMAT_RGBX101010 (1<<25) 5874 #define SPRITE_FORMAT_RGBX888 (2<<25) 5875 #define SPRITE_FORMAT_RGBX161616 (3<<25) 5876 #define SPRITE_FORMAT_YUV444 (4<<25) 5877 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 5878 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 5879 #define SPRITE_SOURCE_KEY (1<<22) 5880 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 5881 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 5882 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 5883 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 5884 #define SPRITE_YUV_ORDER_YUYV (0<<16) 5885 #define SPRITE_YUV_ORDER_UYVY (1<<16) 5886 #define SPRITE_YUV_ORDER_YVYU (2<<16) 5887 #define SPRITE_YUV_ORDER_VYUY (3<<16) 5888 #define SPRITE_ROTATE_180 (1<<15) 5889 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 5890 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 5891 #define SPRITE_TILED (1<<10) 5892 #define SPRITE_DEST_KEY (1<<2) 5893 #define _SPRA_LINOFF 0x70284 5894 #define _SPRA_STRIDE 0x70288 5895 #define _SPRA_POS 0x7028c 5896 #define _SPRA_SIZE 0x70290 5897 #define _SPRA_KEYVAL 0x70294 5898 #define _SPRA_KEYMSK 0x70298 5899 #define _SPRA_SURF 0x7029c 5900 #define _SPRA_KEYMAX 0x702a0 5901 #define _SPRA_TILEOFF 0x702a4 5902 #define _SPRA_OFFSET 0x702a4 5903 #define _SPRA_SURFLIVE 0x702ac 5904 #define _SPRA_SCALE 0x70304 5905 #define SPRITE_SCALE_ENABLE (1<<31) 5906 #define SPRITE_FILTER_MASK (3<<29) 5907 #define SPRITE_FILTER_MEDIUM (0<<29) 5908 #define SPRITE_FILTER_ENHANCING (1<<29) 5909 #define SPRITE_FILTER_SOFTENING (2<<29) 5910 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 5911 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 5912 #define _SPRA_GAMC 0x70400 5913 5914 #define _SPRB_CTL 0x71280 5915 #define _SPRB_LINOFF 0x71284 5916 #define _SPRB_STRIDE 0x71288 5917 #define _SPRB_POS 0x7128c 5918 #define _SPRB_SIZE 0x71290 5919 #define _SPRB_KEYVAL 0x71294 5920 #define _SPRB_KEYMSK 0x71298 5921 #define _SPRB_SURF 0x7129c 5922 #define _SPRB_KEYMAX 0x712a0 5923 #define _SPRB_TILEOFF 0x712a4 5924 #define _SPRB_OFFSET 0x712a4 5925 #define _SPRB_SURFLIVE 0x712ac 5926 #define _SPRB_SCALE 0x71304 5927 #define _SPRB_GAMC 0x71400 5928 5929 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 5930 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 5931 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 5932 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 5933 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 5934 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 5935 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 5936 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 5937 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 5938 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 5939 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 5940 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 5941 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 5942 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 5943 5944 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 5945 #define SP_ENABLE (1<<31) 5946 #define SP_GAMMA_ENABLE (1<<30) 5947 #define SP_PIXFORMAT_MASK (0xf<<26) 5948 #define SP_FORMAT_YUV422 (0<<26) 5949 #define SP_FORMAT_BGR565 (5<<26) 5950 #define SP_FORMAT_BGRX8888 (6<<26) 5951 #define SP_FORMAT_BGRA8888 (7<<26) 5952 #define SP_FORMAT_RGBX1010102 (8<<26) 5953 #define SP_FORMAT_RGBA1010102 (9<<26) 5954 #define SP_FORMAT_RGBX8888 (0xe<<26) 5955 #define SP_FORMAT_RGBA8888 (0xf<<26) 5956 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ 5957 #define SP_SOURCE_KEY (1<<22) 5958 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 5959 #define SP_YUV_ORDER_YUYV (0<<16) 5960 #define SP_YUV_ORDER_UYVY (1<<16) 5961 #define SP_YUV_ORDER_YVYU (2<<16) 5962 #define SP_YUV_ORDER_VYUY (3<<16) 5963 #define SP_ROTATE_180 (1<<15) 5964 #define SP_TILED (1<<10) 5965 #define SP_MIRROR (1<<8) /* CHV pipe B */ 5966 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 5967 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 5968 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 5969 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 5970 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 5971 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 5972 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 5973 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 5974 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 5975 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 5976 #define SP_CONST_ALPHA_ENABLE (1<<31) 5977 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 5978 5979 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 5980 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 5981 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 5982 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 5983 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 5984 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 5985 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 5986 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 5987 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 5988 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 5989 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 5990 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 5991 5992 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 5993 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 5994 5995 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 5996 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 5997 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 5998 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 5999 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 6000 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 6001 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 6002 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 6003 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 6004 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 6005 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 6006 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) 6007 6008 /* 6009 * CHV pipe B sprite CSC 6010 * 6011 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 6012 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 6013 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 6014 */ 6015 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 6016 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 6017 6018 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 6019 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 6020 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 6021 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 6022 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 6023 6024 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 6025 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 6026 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 6027 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 6028 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 6029 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 6030 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 6031 6032 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 6033 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 6034 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 6035 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 6036 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 6037 6038 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 6039 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 6040 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 6041 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 6042 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 6043 6044 /* Skylake plane registers */ 6045 6046 #define _PLANE_CTL_1_A 0x70180 6047 #define _PLANE_CTL_2_A 0x70280 6048 #define _PLANE_CTL_3_A 0x70380 6049 #define PLANE_CTL_ENABLE (1 << 31) 6050 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) 6051 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 6052 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) 6053 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) 6054 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) 6055 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) 6056 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) 6057 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) 6058 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) 6059 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) 6060 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) 6061 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 6062 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) 6063 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) 6064 #define PLANE_CTL_ORDER_BGRX (0 << 20) 6065 #define PLANE_CTL_ORDER_RGBX (1 << 20) 6066 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6067 #define PLANE_CTL_YUV422_YUYV ( 0 << 16) 6068 #define PLANE_CTL_YUV422_UYVY ( 1 << 16) 6069 #define PLANE_CTL_YUV422_YVYU ( 2 << 16) 6070 #define PLANE_CTL_YUV422_VYUY ( 3 << 16) 6071 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) 6072 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 6073 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) 6074 #define PLANE_CTL_TILED_MASK (0x7 << 10) 6075 #define PLANE_CTL_TILED_LINEAR ( 0 << 10) 6076 #define PLANE_CTL_TILED_X ( 1 << 10) 6077 #define PLANE_CTL_TILED_Y ( 4 << 10) 6078 #define PLANE_CTL_TILED_YF ( 5 << 10) 6079 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) 6080 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) 6081 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) 6082 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) 6083 #define PLANE_CTL_ROTATE_MASK 0x3 6084 #define PLANE_CTL_ROTATE_0 0x0 6085 #define PLANE_CTL_ROTATE_90 0x1 6086 #define PLANE_CTL_ROTATE_180 0x2 6087 #define PLANE_CTL_ROTATE_270 0x3 6088 #define _PLANE_STRIDE_1_A 0x70188 6089 #define _PLANE_STRIDE_2_A 0x70288 6090 #define _PLANE_STRIDE_3_A 0x70388 6091 #define _PLANE_POS_1_A 0x7018c 6092 #define _PLANE_POS_2_A 0x7028c 6093 #define _PLANE_POS_3_A 0x7038c 6094 #define _PLANE_SIZE_1_A 0x70190 6095 #define _PLANE_SIZE_2_A 0x70290 6096 #define _PLANE_SIZE_3_A 0x70390 6097 #define _PLANE_SURF_1_A 0x7019c 6098 #define _PLANE_SURF_2_A 0x7029c 6099 #define _PLANE_SURF_3_A 0x7039c 6100 #define _PLANE_OFFSET_1_A 0x701a4 6101 #define _PLANE_OFFSET_2_A 0x702a4 6102 #define _PLANE_OFFSET_3_A 0x703a4 6103 #define _PLANE_KEYVAL_1_A 0x70194 6104 #define _PLANE_KEYVAL_2_A 0x70294 6105 #define _PLANE_KEYMSK_1_A 0x70198 6106 #define _PLANE_KEYMSK_2_A 0x70298 6107 #define _PLANE_KEYMAX_1_A 0x701a0 6108 #define _PLANE_KEYMAX_2_A 0x702a0 6109 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6110 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6111 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6112 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) 6113 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) 6114 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) 6115 #define _PLANE_BUF_CFG_1_A 0x7027c 6116 #define _PLANE_BUF_CFG_2_A 0x7037c 6117 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 6118 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 6119 6120 6121 #define _PLANE_CTL_1_B 0x71180 6122 #define _PLANE_CTL_2_B 0x71280 6123 #define _PLANE_CTL_3_B 0x71380 6124 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 6125 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 6126 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 6127 #define PLANE_CTL(pipe, plane) \ 6128 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 6129 6130 #define _PLANE_STRIDE_1_B 0x71188 6131 #define _PLANE_STRIDE_2_B 0x71288 6132 #define _PLANE_STRIDE_3_B 0x71388 6133 #define _PLANE_STRIDE_1(pipe) \ 6134 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 6135 #define _PLANE_STRIDE_2(pipe) \ 6136 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 6137 #define _PLANE_STRIDE_3(pipe) \ 6138 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 6139 #define PLANE_STRIDE(pipe, plane) \ 6140 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 6141 6142 #define _PLANE_POS_1_B 0x7118c 6143 #define _PLANE_POS_2_B 0x7128c 6144 #define _PLANE_POS_3_B 0x7138c 6145 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 6146 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 6147 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 6148 #define PLANE_POS(pipe, plane) \ 6149 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 6150 6151 #define _PLANE_SIZE_1_B 0x71190 6152 #define _PLANE_SIZE_2_B 0x71290 6153 #define _PLANE_SIZE_3_B 0x71390 6154 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 6155 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 6156 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 6157 #define PLANE_SIZE(pipe, plane) \ 6158 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 6159 6160 #define _PLANE_SURF_1_B 0x7119c 6161 #define _PLANE_SURF_2_B 0x7129c 6162 #define _PLANE_SURF_3_B 0x7139c 6163 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 6164 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 6165 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 6166 #define PLANE_SURF(pipe, plane) \ 6167 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 6168 6169 #define _PLANE_OFFSET_1_B 0x711a4 6170 #define _PLANE_OFFSET_2_B 0x712a4 6171 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 6172 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 6173 #define PLANE_OFFSET(pipe, plane) \ 6174 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 6175 6176 #define _PLANE_KEYVAL_1_B 0x71194 6177 #define _PLANE_KEYVAL_2_B 0x71294 6178 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 6179 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 6180 #define PLANE_KEYVAL(pipe, plane) \ 6181 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 6182 6183 #define _PLANE_KEYMSK_1_B 0x71198 6184 #define _PLANE_KEYMSK_2_B 0x71298 6185 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 6186 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 6187 #define PLANE_KEYMSK(pipe, plane) \ 6188 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 6189 6190 #define _PLANE_KEYMAX_1_B 0x711a0 6191 #define _PLANE_KEYMAX_2_B 0x712a0 6192 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 6193 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 6194 #define PLANE_KEYMAX(pipe, plane) \ 6195 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 6196 6197 #define _PLANE_BUF_CFG_1_B 0x7127c 6198 #define _PLANE_BUF_CFG_2_B 0x7137c 6199 #define _PLANE_BUF_CFG_1(pipe) \ 6200 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 6201 #define _PLANE_BUF_CFG_2(pipe) \ 6202 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 6203 #define PLANE_BUF_CFG(pipe, plane) \ 6204 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 6205 6206 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 6207 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 6208 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 6209 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 6210 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 6211 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 6212 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 6213 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 6214 6215 #define _PLANE_COLOR_CTL_1_B 0x711CC 6216 #define _PLANE_COLOR_CTL_2_B 0x712CC 6217 #define _PLANE_COLOR_CTL_3_B 0x713CC 6218 #define _PLANE_COLOR_CTL_1(pipe) \ 6219 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 6220 #define _PLANE_COLOR_CTL_2(pipe) \ 6221 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 6222 #define PLANE_COLOR_CTL(pipe, plane) \ 6223 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 6224 6225 #/* SKL new cursor registers */ 6226 #define _CUR_BUF_CFG_A 0x7017c 6227 #define _CUR_BUF_CFG_B 0x7117c 6228 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 6229 6230 /* VBIOS regs */ 6231 #define VGACNTRL _MMIO(0x71400) 6232 # define VGA_DISP_DISABLE (1 << 31) 6233 # define VGA_2X_MODE (1 << 30) 6234 # define VGA_PIPE_B_SELECT (1 << 29) 6235 6236 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 6237 6238 /* Ironlake */ 6239 6240 #define CPU_VGACNTRL _MMIO(0x41000) 6241 6242 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 6243 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 6244 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 6245 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 6246 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 6247 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 6248 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 6249 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 6250 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 6251 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 6252 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 6253 6254 /* refresh rate hardware control */ 6255 #define RR_HW_CTL _MMIO(0x45300) 6256 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 6257 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 6258 6259 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 6260 #define FDI_PLL_FB_CLOCK_MASK 0xff 6261 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 6262 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 6263 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 6264 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 6265 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 6266 6267 #define PCH_3DCGDIS0 _MMIO(0x46020) 6268 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 6269 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 6270 6271 #define PCH_3DCGDIS1 _MMIO(0x46024) 6272 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 6273 6274 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 6275 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 6276 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 6277 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 6278 6279 6280 #define _PIPEA_DATA_M1 0x60030 6281 #define PIPE_DATA_M1_OFFSET 0 6282 #define _PIPEA_DATA_N1 0x60034 6283 #define PIPE_DATA_N1_OFFSET 0 6284 6285 #define _PIPEA_DATA_M2 0x60038 6286 #define PIPE_DATA_M2_OFFSET 0 6287 #define _PIPEA_DATA_N2 0x6003c 6288 #define PIPE_DATA_N2_OFFSET 0 6289 6290 #define _PIPEA_LINK_M1 0x60040 6291 #define PIPE_LINK_M1_OFFSET 0 6292 #define _PIPEA_LINK_N1 0x60044 6293 #define PIPE_LINK_N1_OFFSET 0 6294 6295 #define _PIPEA_LINK_M2 0x60048 6296 #define PIPE_LINK_M2_OFFSET 0 6297 #define _PIPEA_LINK_N2 0x6004c 6298 #define PIPE_LINK_N2_OFFSET 0 6299 6300 /* PIPEB timing regs are same start from 0x61000 */ 6301 6302 #define _PIPEB_DATA_M1 0x61030 6303 #define _PIPEB_DATA_N1 0x61034 6304 #define _PIPEB_DATA_M2 0x61038 6305 #define _PIPEB_DATA_N2 0x6103c 6306 #define _PIPEB_LINK_M1 0x61040 6307 #define _PIPEB_LINK_N1 0x61044 6308 #define _PIPEB_LINK_M2 0x61048 6309 #define _PIPEB_LINK_N2 0x6104c 6310 6311 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 6312 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 6313 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 6314 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 6315 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 6316 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 6317 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 6318 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 6319 6320 /* CPU panel fitter */ 6321 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 6322 #define _PFA_CTL_1 0x68080 6323 #define _PFB_CTL_1 0x68880 6324 #define PF_ENABLE (1<<31) 6325 #define PF_PIPE_SEL_MASK_IVB (3<<29) 6326 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 6327 #define PF_FILTER_MASK (3<<23) 6328 #define PF_FILTER_PROGRAMMED (0<<23) 6329 #define PF_FILTER_MED_3x3 (1<<23) 6330 #define PF_FILTER_EDGE_ENHANCE (2<<23) 6331 #define PF_FILTER_EDGE_SOFTEN (3<<23) 6332 #define _PFA_WIN_SZ 0x68074 6333 #define _PFB_WIN_SZ 0x68874 6334 #define _PFA_WIN_POS 0x68070 6335 #define _PFB_WIN_POS 0x68870 6336 #define _PFA_VSCALE 0x68084 6337 #define _PFB_VSCALE 0x68884 6338 #define _PFA_HSCALE 0x68090 6339 #define _PFB_HSCALE 0x68890 6340 6341 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 6342 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 6343 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 6344 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 6345 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 6346 6347 #define _PSA_CTL 0x68180 6348 #define _PSB_CTL 0x68980 6349 #define PS_ENABLE (1<<31) 6350 #define _PSA_WIN_SZ 0x68174 6351 #define _PSB_WIN_SZ 0x68974 6352 #define _PSA_WIN_POS 0x68170 6353 #define _PSB_WIN_POS 0x68970 6354 6355 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 6356 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 6357 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 6358 6359 /* 6360 * Skylake scalers 6361 */ 6362 #define _PS_1A_CTRL 0x68180 6363 #define _PS_2A_CTRL 0x68280 6364 #define _PS_1B_CTRL 0x68980 6365 #define _PS_2B_CTRL 0x68A80 6366 #define _PS_1C_CTRL 0x69180 6367 #define PS_SCALER_EN (1 << 31) 6368 #define PS_SCALER_MODE_MASK (3 << 28) 6369 #define PS_SCALER_MODE_DYN (0 << 28) 6370 #define PS_SCALER_MODE_HQ (1 << 28) 6371 #define PS_PLANE_SEL_MASK (7 << 25) 6372 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 6373 #define PS_FILTER_MASK (3 << 23) 6374 #define PS_FILTER_MEDIUM (0 << 23) 6375 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 6376 #define PS_FILTER_BILINEAR (3 << 23) 6377 #define PS_VERT3TAP (1 << 21) 6378 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 6379 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 6380 #define PS_PWRUP_PROGRESS (1 << 17) 6381 #define PS_V_FILTER_BYPASS (1 << 8) 6382 #define PS_VADAPT_EN (1 << 7) 6383 #define PS_VADAPT_MODE_MASK (3 << 5) 6384 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 6385 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 6386 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 6387 6388 #define _PS_PWR_GATE_1A 0x68160 6389 #define _PS_PWR_GATE_2A 0x68260 6390 #define _PS_PWR_GATE_1B 0x68960 6391 #define _PS_PWR_GATE_2B 0x68A60 6392 #define _PS_PWR_GATE_1C 0x69160 6393 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 6394 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 6395 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 6396 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 6397 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 6398 #define PS_PWR_GATE_SLPEN_8 0 6399 #define PS_PWR_GATE_SLPEN_16 1 6400 #define PS_PWR_GATE_SLPEN_24 2 6401 #define PS_PWR_GATE_SLPEN_32 3 6402 6403 #define _PS_WIN_POS_1A 0x68170 6404 #define _PS_WIN_POS_2A 0x68270 6405 #define _PS_WIN_POS_1B 0x68970 6406 #define _PS_WIN_POS_2B 0x68A70 6407 #define _PS_WIN_POS_1C 0x69170 6408 6409 #define _PS_WIN_SZ_1A 0x68174 6410 #define _PS_WIN_SZ_2A 0x68274 6411 #define _PS_WIN_SZ_1B 0x68974 6412 #define _PS_WIN_SZ_2B 0x68A74 6413 #define _PS_WIN_SZ_1C 0x69174 6414 6415 #define _PS_VSCALE_1A 0x68184 6416 #define _PS_VSCALE_2A 0x68284 6417 #define _PS_VSCALE_1B 0x68984 6418 #define _PS_VSCALE_2B 0x68A84 6419 #define _PS_VSCALE_1C 0x69184 6420 6421 #define _PS_HSCALE_1A 0x68190 6422 #define _PS_HSCALE_2A 0x68290 6423 #define _PS_HSCALE_1B 0x68990 6424 #define _PS_HSCALE_2B 0x68A90 6425 #define _PS_HSCALE_1C 0x69190 6426 6427 #define _PS_VPHASE_1A 0x68188 6428 #define _PS_VPHASE_2A 0x68288 6429 #define _PS_VPHASE_1B 0x68988 6430 #define _PS_VPHASE_2B 0x68A88 6431 #define _PS_VPHASE_1C 0x69188 6432 6433 #define _PS_HPHASE_1A 0x68194 6434 #define _PS_HPHASE_2A 0x68294 6435 #define _PS_HPHASE_1B 0x68994 6436 #define _PS_HPHASE_2B 0x68A94 6437 #define _PS_HPHASE_1C 0x69194 6438 6439 #define _PS_ECC_STAT_1A 0x681D0 6440 #define _PS_ECC_STAT_2A 0x682D0 6441 #define _PS_ECC_STAT_1B 0x689D0 6442 #define _PS_ECC_STAT_2B 0x68AD0 6443 #define _PS_ECC_STAT_1C 0x691D0 6444 6445 #define _ID(id, a, b) ((a) + (id)*((b)-(a))) 6446 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 6447 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 6448 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 6449 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 6450 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 6451 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 6452 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 6453 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 6454 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 6455 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 6456 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 6457 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 6458 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 6459 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 6460 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 6461 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 6462 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 6463 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 6464 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 6465 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 6466 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 6467 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 6468 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 6469 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 6470 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 6471 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 6472 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 6473 6474 /* legacy palette */ 6475 #define _LGC_PALETTE_A 0x4a000 6476 #define _LGC_PALETTE_B 0x4a800 6477 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 6478 6479 #define _GAMMA_MODE_A 0x4a480 6480 #define _GAMMA_MODE_B 0x4ac80 6481 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 6482 #define GAMMA_MODE_MODE_MASK (3 << 0) 6483 #define GAMMA_MODE_MODE_8BIT (0 << 0) 6484 #define GAMMA_MODE_MODE_10BIT (1 << 0) 6485 #define GAMMA_MODE_MODE_12BIT (2 << 0) 6486 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 6487 6488 /* DMC/CSR */ 6489 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 6490 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 6491 #define CSR_HTP_ADDR_SKL 0x00500034 6492 #define CSR_SSP_BASE _MMIO(0x8F074) 6493 #define CSR_HTP_SKL _MMIO(0x8F004) 6494 #define CSR_LAST_WRITE _MMIO(0x8F034) 6495 #define CSR_LAST_WRITE_VALUE 0xc003b400 6496 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 6497 #define CSR_MMIO_START_RANGE 0x80000 6498 #define CSR_MMIO_END_RANGE 0x8FFFF 6499 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 6500 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 6501 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 6502 6503 /* interrupts */ 6504 #define DE_MASTER_IRQ_CONTROL (1 << 31) 6505 #define DE_SPRITEB_FLIP_DONE (1 << 29) 6506 #define DE_SPRITEA_FLIP_DONE (1 << 28) 6507 #define DE_PLANEB_FLIP_DONE (1 << 27) 6508 #define DE_PLANEA_FLIP_DONE (1 << 26) 6509 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 6510 #define DE_PCU_EVENT (1 << 25) 6511 #define DE_GTT_FAULT (1 << 24) 6512 #define DE_POISON (1 << 23) 6513 #define DE_PERFORM_COUNTER (1 << 22) 6514 #define DE_PCH_EVENT (1 << 21) 6515 #define DE_AUX_CHANNEL_A (1 << 20) 6516 #define DE_DP_A_HOTPLUG (1 << 19) 6517 #define DE_GSE (1 << 18) 6518 #define DE_PIPEB_VBLANK (1 << 15) 6519 #define DE_PIPEB_EVEN_FIELD (1 << 14) 6520 #define DE_PIPEB_ODD_FIELD (1 << 13) 6521 #define DE_PIPEB_LINE_COMPARE (1 << 12) 6522 #define DE_PIPEB_VSYNC (1 << 11) 6523 #define DE_PIPEB_CRC_DONE (1 << 10) 6524 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 6525 #define DE_PIPEA_VBLANK (1 << 7) 6526 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 6527 #define DE_PIPEA_EVEN_FIELD (1 << 6) 6528 #define DE_PIPEA_ODD_FIELD (1 << 5) 6529 #define DE_PIPEA_LINE_COMPARE (1 << 4) 6530 #define DE_PIPEA_VSYNC (1 << 3) 6531 #define DE_PIPEA_CRC_DONE (1 << 2) 6532 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 6533 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 6534 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 6535 6536 /* More Ivybridge lolz */ 6537 #define DE_ERR_INT_IVB (1<<30) 6538 #define DE_GSE_IVB (1<<29) 6539 #define DE_PCH_EVENT_IVB (1<<28) 6540 #define DE_DP_A_HOTPLUG_IVB (1<<27) 6541 #define DE_AUX_CHANNEL_A_IVB (1<<26) 6542 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 6543 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 6544 #define DE_PIPEC_VBLANK_IVB (1<<10) 6545 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 6546 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 6547 #define DE_PIPEB_VBLANK_IVB (1<<5) 6548 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 6549 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 6550 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 6551 #define DE_PIPEA_VBLANK_IVB (1<<0) 6552 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 6553 6554 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 6555 #define MASTER_INTERRUPT_ENABLE (1<<31) 6556 6557 #define DEISR _MMIO(0x44000) 6558 #define DEIMR _MMIO(0x44004) 6559 #define DEIIR _MMIO(0x44008) 6560 #define DEIER _MMIO(0x4400c) 6561 6562 #define GTISR _MMIO(0x44010) 6563 #define GTIMR _MMIO(0x44014) 6564 #define GTIIR _MMIO(0x44018) 6565 #define GTIER _MMIO(0x4401c) 6566 6567 #define GEN8_MASTER_IRQ _MMIO(0x44200) 6568 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 6569 #define GEN8_PCU_IRQ (1<<30) 6570 #define GEN8_DE_PCH_IRQ (1<<23) 6571 #define GEN8_DE_MISC_IRQ (1<<22) 6572 #define GEN8_DE_PORT_IRQ (1<<20) 6573 #define GEN8_DE_PIPE_C_IRQ (1<<18) 6574 #define GEN8_DE_PIPE_B_IRQ (1<<17) 6575 #define GEN8_DE_PIPE_A_IRQ (1<<16) 6576 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe))) 6577 #define GEN8_GT_VECS_IRQ (1<<6) 6578 #define GEN8_GT_GUC_IRQ (1<<5) 6579 #define GEN8_GT_PM_IRQ (1<<4) 6580 #define GEN8_GT_VCS2_IRQ (1<<3) 6581 #define GEN8_GT_VCS1_IRQ (1<<2) 6582 #define GEN8_GT_BCS_IRQ (1<<1) 6583 #define GEN8_GT_RCS_IRQ (1<<0) 6584 6585 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 6586 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 6587 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 6588 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 6589 6590 #define GEN9_GUC_TO_HOST_INT_EVENT (1<<31) 6591 #define GEN9_GUC_EXEC_ERROR_EVENT (1<<30) 6592 #define GEN9_GUC_DISPLAY_EVENT (1<<29) 6593 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28) 6594 #define GEN9_GUC_IOMMU_MSG_EVENT (1<<27) 6595 #define GEN9_GUC_DB_RING_EVENT (1<<26) 6596 #define GEN9_GUC_DMA_DONE_EVENT (1<<25) 6597 #define GEN9_GUC_FATAL_ERROR_EVENT (1<<24) 6598 #define GEN9_GUC_NOTIFICATION_EVENT (1<<23) 6599 6600 #define GEN8_RCS_IRQ_SHIFT 0 6601 #define GEN8_BCS_IRQ_SHIFT 16 6602 #define GEN8_VCS1_IRQ_SHIFT 0 6603 #define GEN8_VCS2_IRQ_SHIFT 16 6604 #define GEN8_VECS_IRQ_SHIFT 0 6605 #define GEN8_WD_IRQ_SHIFT 16 6606 6607 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 6608 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 6609 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 6610 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 6611 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 6612 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 6613 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 6614 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 6615 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 6616 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 6617 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 6618 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 6619 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 6620 #define GEN8_PIPE_VSYNC (1 << 1) 6621 #define GEN8_PIPE_VBLANK (1 << 0) 6622 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 6623 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 6624 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 6625 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 6626 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 6627 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 6628 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 6629 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 6630 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 6631 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 6632 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 6633 (GEN8_PIPE_CURSOR_FAULT | \ 6634 GEN8_PIPE_SPRITE_FAULT | \ 6635 GEN8_PIPE_PRIMARY_FAULT) 6636 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 6637 (GEN9_PIPE_CURSOR_FAULT | \ 6638 GEN9_PIPE_PLANE4_FAULT | \ 6639 GEN9_PIPE_PLANE3_FAULT | \ 6640 GEN9_PIPE_PLANE2_FAULT | \ 6641 GEN9_PIPE_PLANE1_FAULT) 6642 6643 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 6644 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 6645 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 6646 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 6647 #define GEN9_AUX_CHANNEL_D (1 << 27) 6648 #define GEN9_AUX_CHANNEL_C (1 << 26) 6649 #define GEN9_AUX_CHANNEL_B (1 << 25) 6650 #define BXT_DE_PORT_HP_DDIC (1 << 5) 6651 #define BXT_DE_PORT_HP_DDIB (1 << 4) 6652 #define BXT_DE_PORT_HP_DDIA (1 << 3) 6653 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 6654 BXT_DE_PORT_HP_DDIB | \ 6655 BXT_DE_PORT_HP_DDIC) 6656 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 6657 #define BXT_DE_PORT_GMBUS (1 << 1) 6658 #define GEN8_AUX_CHANNEL_A (1 << 0) 6659 6660 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 6661 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 6662 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 6663 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 6664 #define GEN8_DE_MISC_GSE (1 << 27) 6665 6666 #define GEN8_PCU_ISR _MMIO(0x444e0) 6667 #define GEN8_PCU_IMR _MMIO(0x444e4) 6668 #define GEN8_PCU_IIR _MMIO(0x444e8) 6669 #define GEN8_PCU_IER _MMIO(0x444ec) 6670 6671 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 6672 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 6673 #define ILK_ELPIN_409_SELECT (1 << 25) 6674 #define ILK_DPARB_GATE (1<<22) 6675 #define ILK_VSDPFD_FULL (1<<21) 6676 #define FUSE_STRAP _MMIO(0x42014) 6677 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 6678 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 6679 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 6680 #define IVB_PIPE_C_DISABLE (1 << 28) 6681 #define ILK_HDCP_DISABLE (1 << 25) 6682 #define ILK_eDP_A_DISABLE (1 << 24) 6683 #define HSW_CDCLK_LIMIT (1 << 24) 6684 #define ILK_DESKTOP (1 << 23) 6685 6686 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 6687 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 6688 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 6689 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 6690 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 6691 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 6692 6693 #define IVB_CHICKEN3 _MMIO(0x4200c) 6694 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 6695 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 6696 6697 #define CHICKEN_PAR1_1 _MMIO(0x42080) 6698 #define DPA_MASK_VBLANK_SRD (1 << 15) 6699 #define FORCE_ARB_IDLE_PLANES (1 << 14) 6700 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 6701 6702 #define CHICKEN_PAR2_1 _MMIO(0x42090) 6703 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 6704 6705 #define CHICKEN_MISC_2 _MMIO(0x42084) 6706 #define GLK_CL0_PWR_DOWN (1 << 10) 6707 #define GLK_CL1_PWR_DOWN (1 << 11) 6708 #define GLK_CL2_PWR_DOWN (1 << 12) 6709 6710 #define CHICKEN_MISC_2 _MMIO(0x42084) 6711 #define COMP_PWR_DOWN (1 << 23) 6712 6713 #define _CHICKEN_PIPESL_1_A 0x420b0 6714 #define _CHICKEN_PIPESL_1_B 0x420b4 6715 #define HSW_FBCQ_DIS (1 << 22) 6716 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 6717 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 6718 6719 #define CHICKEN_TRANS_A 0x420c0 6720 #define CHICKEN_TRANS_B 0x420c4 6721 #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B) 6722 #define PSR2_VSC_ENABLE_PROG_HEADER (1<<12) 6723 #define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15) 6724 6725 #define DISP_ARB_CTL _MMIO(0x45000) 6726 #define DISP_FBC_MEMORY_WAKE (1<<31) 6727 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 6728 #define DISP_FBC_WM_DIS (1<<15) 6729 #define DISP_ARB_CTL2 _MMIO(0x45004) 6730 #define DISP_DATA_PARTITION_5_6 (1<<6) 6731 #define DBUF_CTL _MMIO(0x45008) 6732 #define DBUF_POWER_REQUEST (1<<31) 6733 #define DBUF_POWER_STATE (1<<30) 6734 #define GEN7_MSG_CTL _MMIO(0x45010) 6735 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 6736 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 6737 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 6738 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 6739 6740 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 6741 #define MASK_WAKEMEM (1<<13) 6742 6743 #define SKL_DFSM _MMIO(0x51000) 6744 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 6745 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 6746 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 6747 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 6748 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 6749 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 6750 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 6751 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 6752 6753 #define SKL_DSSM _MMIO(0x51004) 6754 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) 6755 6756 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 6757 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) 6758 6759 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 6760 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) 6761 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10) 6762 6763 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 6764 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 6765 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 6766 6767 /* GEN7 chicken */ 6768 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 6769 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 6770 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) 6771 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 6772 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12) 6773 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8) 6774 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 6775 6776 #define HIZ_CHICKEN _MMIO(0x7018) 6777 # define CHV_HZ_8X8_MODE_IN_1X (1<<15) 6778 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) 6779 6780 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 6781 #define DISABLE_PIXEL_MASK_CAMMING (1<<14) 6782 6783 #define GEN7_L3SQCREG1 _MMIO(0xB010) 6784 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 6785 6786 #define GEN8_L3SQCREG1 _MMIO(0xB100) 6787 /* 6788 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 6789 * Using the formula in BSpec leads to a hang, while the formula here works 6790 * fine and matches the formulas for all other platforms. A BSpec change 6791 * request has been filed to clarify this. 6792 */ 6793 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 6794 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 6795 6796 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 6797 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 6798 #define GEN7_L3AGDIS (1<<19) 6799 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 6800 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 6801 6802 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 6803 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 6804 6805 #define GEN7_L3SQCREG4 _MMIO(0xb034) 6806 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 6807 6808 #define GEN8_L3SQCREG4 _MMIO(0xb118) 6809 #define GEN8_LQSC_RO_PERF_DIS (1<<27) 6810 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) 6811 6812 /* GEN8 chicken */ 6813 #define HDC_CHICKEN0 _MMIO(0x7300) 6814 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) 6815 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 6816 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 6817 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) 6818 #define HDC_FORCE_NON_COHERENT (1<<4) 6819 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) 6820 6821 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 6822 6823 /* GEN9 chicken */ 6824 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 6825 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 6826 6827 /* WaCatErrorRejectionIssue */ 6828 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 6829 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 6830 6831 #define HSW_SCRATCH1 _MMIO(0xb038) 6832 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 6833 6834 #define BDW_SCRATCH1 _MMIO(0xb11c) 6835 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) 6836 6837 /* PCH */ 6838 6839 /* south display engine interrupt: IBX */ 6840 #define SDE_AUDIO_POWER_D (1 << 27) 6841 #define SDE_AUDIO_POWER_C (1 << 26) 6842 #define SDE_AUDIO_POWER_B (1 << 25) 6843 #define SDE_AUDIO_POWER_SHIFT (25) 6844 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 6845 #define SDE_GMBUS (1 << 24) 6846 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 6847 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 6848 #define SDE_AUDIO_HDCP_MASK (3 << 22) 6849 #define SDE_AUDIO_TRANSB (1 << 21) 6850 #define SDE_AUDIO_TRANSA (1 << 20) 6851 #define SDE_AUDIO_TRANS_MASK (3 << 20) 6852 #define SDE_POISON (1 << 19) 6853 /* 18 reserved */ 6854 #define SDE_FDI_RXB (1 << 17) 6855 #define SDE_FDI_RXA (1 << 16) 6856 #define SDE_FDI_MASK (3 << 16) 6857 #define SDE_AUXD (1 << 15) 6858 #define SDE_AUXC (1 << 14) 6859 #define SDE_AUXB (1 << 13) 6860 #define SDE_AUX_MASK (7 << 13) 6861 /* 12 reserved */ 6862 #define SDE_CRT_HOTPLUG (1 << 11) 6863 #define SDE_PORTD_HOTPLUG (1 << 10) 6864 #define SDE_PORTC_HOTPLUG (1 << 9) 6865 #define SDE_PORTB_HOTPLUG (1 << 8) 6866 #define SDE_SDVOB_HOTPLUG (1 << 6) 6867 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 6868 SDE_SDVOB_HOTPLUG | \ 6869 SDE_PORTB_HOTPLUG | \ 6870 SDE_PORTC_HOTPLUG | \ 6871 SDE_PORTD_HOTPLUG) 6872 #define SDE_TRANSB_CRC_DONE (1 << 5) 6873 #define SDE_TRANSB_CRC_ERR (1 << 4) 6874 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 6875 #define SDE_TRANSA_CRC_DONE (1 << 2) 6876 #define SDE_TRANSA_CRC_ERR (1 << 1) 6877 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 6878 #define SDE_TRANS_MASK (0x3f) 6879 6880 /* south display engine interrupt: CPT/PPT */ 6881 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 6882 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 6883 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 6884 #define SDE_AUDIO_POWER_SHIFT_CPT 29 6885 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 6886 #define SDE_AUXD_CPT (1 << 27) 6887 #define SDE_AUXC_CPT (1 << 26) 6888 #define SDE_AUXB_CPT (1 << 25) 6889 #define SDE_AUX_MASK_CPT (7 << 25) 6890 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 6891 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 6892 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 6893 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 6894 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 6895 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 6896 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 6897 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 6898 SDE_SDVOB_HOTPLUG_CPT | \ 6899 SDE_PORTD_HOTPLUG_CPT | \ 6900 SDE_PORTC_HOTPLUG_CPT | \ 6901 SDE_PORTB_HOTPLUG_CPT) 6902 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 6903 SDE_PORTD_HOTPLUG_CPT | \ 6904 SDE_PORTC_HOTPLUG_CPT | \ 6905 SDE_PORTB_HOTPLUG_CPT | \ 6906 SDE_PORTA_HOTPLUG_SPT) 6907 #define SDE_GMBUS_CPT (1 << 17) 6908 #define SDE_ERROR_CPT (1 << 16) 6909 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 6910 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 6911 #define SDE_FDI_RXC_CPT (1 << 8) 6912 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 6913 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 6914 #define SDE_FDI_RXB_CPT (1 << 4) 6915 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 6916 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 6917 #define SDE_FDI_RXA_CPT (1 << 0) 6918 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 6919 SDE_AUDIO_CP_REQ_B_CPT | \ 6920 SDE_AUDIO_CP_REQ_A_CPT) 6921 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 6922 SDE_AUDIO_CP_CHG_B_CPT | \ 6923 SDE_AUDIO_CP_CHG_A_CPT) 6924 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 6925 SDE_FDI_RXB_CPT | \ 6926 SDE_FDI_RXA_CPT) 6927 6928 #define SDEISR _MMIO(0xc4000) 6929 #define SDEIMR _MMIO(0xc4004) 6930 #define SDEIIR _MMIO(0xc4008) 6931 #define SDEIER _MMIO(0xc400c) 6932 6933 #define SERR_INT _MMIO(0xc4040) 6934 #define SERR_INT_POISON (1<<31) 6935 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 6936 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 6937 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 6938 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 6939 6940 /* digital port hotplug */ 6941 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6942 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6943 #define BXT_DDIA_HPD_INVERT (1 << 27) 6944 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6945 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6946 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6947 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6948 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6949 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6950 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6951 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6952 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6953 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6954 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6955 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6956 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6957 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6958 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6959 #define BXT_DDIC_HPD_INVERT (1 << 11) 6960 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6961 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6962 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6963 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6964 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6965 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6966 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6967 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6968 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6969 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6970 #define BXT_DDIB_HPD_INVERT (1 << 3) 6971 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6972 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6973 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6974 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6975 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6976 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6977 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6978 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6979 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6980 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6981 BXT_DDIB_HPD_INVERT | \ 6982 BXT_DDIC_HPD_INVERT) 6983 6984 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6985 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6986 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6987 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6988 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6989 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6990 6991 #define PCH_GPIOA _MMIO(0xc5010) 6992 #define PCH_GPIOB _MMIO(0xc5014) 6993 #define PCH_GPIOC _MMIO(0xc5018) 6994 #define PCH_GPIOD _MMIO(0xc501c) 6995 #define PCH_GPIOE _MMIO(0xc5020) 6996 #define PCH_GPIOF _MMIO(0xc5024) 6997 6998 #define PCH_GMBUS0 _MMIO(0xc5100) 6999 #define PCH_GMBUS1 _MMIO(0xc5104) 7000 #define PCH_GMBUS2 _MMIO(0xc5108) 7001 #define PCH_GMBUS3 _MMIO(0xc510c) 7002 #define PCH_GMBUS4 _MMIO(0xc5110) 7003 #define PCH_GMBUS5 _MMIO(0xc5120) 7004 7005 #define _PCH_DPLL_A 0xc6014 7006 #define _PCH_DPLL_B 0xc6018 7007 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 7008 7009 #define _PCH_FPA0 0xc6040 7010 #define FP_CB_TUNE (0x3<<22) 7011 #define _PCH_FPA1 0xc6044 7012 #define _PCH_FPB0 0xc6048 7013 #define _PCH_FPB1 0xc604c 7014 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 7015 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 7016 7017 #define PCH_DPLL_TEST _MMIO(0xc606c) 7018 7019 #define PCH_DREF_CONTROL _MMIO(0xC6200) 7020 #define DREF_CONTROL_MASK 0x7fc3 7021 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 7022 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 7023 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 7024 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 7025 #define DREF_SSC_SOURCE_DISABLE (0<<11) 7026 #define DREF_SSC_SOURCE_ENABLE (2<<11) 7027 #define DREF_SSC_SOURCE_MASK (3<<11) 7028 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 7029 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 7030 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 7031 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 7032 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 7033 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 7034 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 7035 #define DREF_SSC4_DOWNSPREAD (0<<6) 7036 #define DREF_SSC4_CENTERSPREAD (1<<6) 7037 #define DREF_SSC1_DISABLE (0<<1) 7038 #define DREF_SSC1_ENABLE (1<<1) 7039 #define DREF_SSC4_DISABLE (0) 7040 #define DREF_SSC4_ENABLE (1) 7041 7042 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 7043 #define FDL_TP1_TIMER_SHIFT 12 7044 #define FDL_TP1_TIMER_MASK (3<<12) 7045 #define FDL_TP2_TIMER_SHIFT 10 7046 #define FDL_TP2_TIMER_MASK (3<<10) 7047 #define RAWCLK_FREQ_MASK 0x3ff 7048 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 7049 #define CNP_RAWCLK_DIV(div) ((div) << 16) 7050 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 7051 #define CNP_RAWCLK_FRAC(frac) ((frac) << 26) 7052 7053 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 7054 7055 #define PCH_SSC4_PARMS _MMIO(0xc6210) 7056 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 7057 7058 #define PCH_DPLL_SEL _MMIO(0xc7000) 7059 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 7060 #define TRANS_DPLLA_SEL(pipe) 0 7061 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 7062 7063 /* transcoder */ 7064 7065 #define _PCH_TRANS_HTOTAL_A 0xe0000 7066 #define TRANS_HTOTAL_SHIFT 16 7067 #define TRANS_HACTIVE_SHIFT 0 7068 #define _PCH_TRANS_HBLANK_A 0xe0004 7069 #define TRANS_HBLANK_END_SHIFT 16 7070 #define TRANS_HBLANK_START_SHIFT 0 7071 #define _PCH_TRANS_HSYNC_A 0xe0008 7072 #define TRANS_HSYNC_END_SHIFT 16 7073 #define TRANS_HSYNC_START_SHIFT 0 7074 #define _PCH_TRANS_VTOTAL_A 0xe000c 7075 #define TRANS_VTOTAL_SHIFT 16 7076 #define TRANS_VACTIVE_SHIFT 0 7077 #define _PCH_TRANS_VBLANK_A 0xe0010 7078 #define TRANS_VBLANK_END_SHIFT 16 7079 #define TRANS_VBLANK_START_SHIFT 0 7080 #define _PCH_TRANS_VSYNC_A 0xe0014 7081 #define TRANS_VSYNC_END_SHIFT 16 7082 #define TRANS_VSYNC_START_SHIFT 0 7083 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 7084 7085 #define _PCH_TRANSA_DATA_M1 0xe0030 7086 #define _PCH_TRANSA_DATA_N1 0xe0034 7087 #define _PCH_TRANSA_DATA_M2 0xe0038 7088 #define _PCH_TRANSA_DATA_N2 0xe003c 7089 #define _PCH_TRANSA_LINK_M1 0xe0040 7090 #define _PCH_TRANSA_LINK_N1 0xe0044 7091 #define _PCH_TRANSA_LINK_M2 0xe0048 7092 #define _PCH_TRANSA_LINK_N2 0xe004c 7093 7094 /* Per-transcoder DIP controls (PCH) */ 7095 #define _VIDEO_DIP_CTL_A 0xe0200 7096 #define _VIDEO_DIP_DATA_A 0xe0208 7097 #define _VIDEO_DIP_GCP_A 0xe0210 7098 #define GCP_COLOR_INDICATION (1 << 2) 7099 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 7100 #define GCP_AV_MUTE (1 << 0) 7101 7102 #define _VIDEO_DIP_CTL_B 0xe1200 7103 #define _VIDEO_DIP_DATA_B 0xe1208 7104 #define _VIDEO_DIP_GCP_B 0xe1210 7105 7106 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 7107 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 7108 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 7109 7110 /* Per-transcoder DIP controls (VLV) */ 7111 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 7112 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 7113 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 7114 7115 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 7116 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 7117 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 7118 7119 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 7120 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 7121 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 7122 7123 #define VLV_TVIDEO_DIP_CTL(pipe) \ 7124 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 7125 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 7126 #define VLV_TVIDEO_DIP_DATA(pipe) \ 7127 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 7128 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 7129 #define VLV_TVIDEO_DIP_GCP(pipe) \ 7130 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 7131 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 7132 7133 /* Haswell DIP controls */ 7134 7135 #define _HSW_VIDEO_DIP_CTL_A 0x60200 7136 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 7137 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 7138 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 7139 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 7140 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 7141 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 7142 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 7143 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 7144 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 7145 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 7146 #define _HSW_VIDEO_DIP_GCP_A 0x60210 7147 7148 #define _HSW_VIDEO_DIP_CTL_B 0x61200 7149 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 7150 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 7151 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 7152 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 7153 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 7154 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 7155 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 7156 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 7157 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 7158 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 7159 #define _HSW_VIDEO_DIP_GCP_B 0x61210 7160 7161 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 7162 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 7163 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 7164 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 7165 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 7166 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 7167 7168 #define _HSW_STEREO_3D_CTL_A 0x70020 7169 #define S3D_ENABLE (1<<31) 7170 #define _HSW_STEREO_3D_CTL_B 0x71020 7171 7172 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 7173 7174 #define _PCH_TRANS_HTOTAL_B 0xe1000 7175 #define _PCH_TRANS_HBLANK_B 0xe1004 7176 #define _PCH_TRANS_HSYNC_B 0xe1008 7177 #define _PCH_TRANS_VTOTAL_B 0xe100c 7178 #define _PCH_TRANS_VBLANK_B 0xe1010 7179 #define _PCH_TRANS_VSYNC_B 0xe1014 7180 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 7181 7182 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 7183 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 7184 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 7185 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 7186 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 7187 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 7188 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 7189 7190 #define _PCH_TRANSB_DATA_M1 0xe1030 7191 #define _PCH_TRANSB_DATA_N1 0xe1034 7192 #define _PCH_TRANSB_DATA_M2 0xe1038 7193 #define _PCH_TRANSB_DATA_N2 0xe103c 7194 #define _PCH_TRANSB_LINK_M1 0xe1040 7195 #define _PCH_TRANSB_LINK_N1 0xe1044 7196 #define _PCH_TRANSB_LINK_M2 0xe1048 7197 #define _PCH_TRANSB_LINK_N2 0xe104c 7198 7199 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 7200 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 7201 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 7202 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 7203 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 7204 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 7205 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 7206 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 7207 7208 #define _PCH_TRANSACONF 0xf0008 7209 #define _PCH_TRANSBCONF 0xf1008 7210 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 7211 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 7212 #define TRANS_DISABLE (0<<31) 7213 #define TRANS_ENABLE (1<<31) 7214 #define TRANS_STATE_MASK (1<<30) 7215 #define TRANS_STATE_DISABLE (0<<30) 7216 #define TRANS_STATE_ENABLE (1<<30) 7217 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 7218 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 7219 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 7220 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 7221 #define TRANS_INTERLACE_MASK (7<<21) 7222 #define TRANS_PROGRESSIVE (0<<21) 7223 #define TRANS_INTERLACED (3<<21) 7224 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 7225 #define TRANS_8BPC (0<<5) 7226 #define TRANS_10BPC (1<<5) 7227 #define TRANS_6BPC (2<<5) 7228 #define TRANS_12BPC (3<<5) 7229 7230 #define _TRANSA_CHICKEN1 0xf0060 7231 #define _TRANSB_CHICKEN1 0xf1060 7232 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 7233 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10) 7234 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 7235 #define _TRANSA_CHICKEN2 0xf0064 7236 #define _TRANSB_CHICKEN2 0xf1064 7237 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 7238 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 7239 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 7240 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 7241 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 7242 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 7243 7244 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 7245 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 7246 #define FDIA_PHASE_SYNC_SHIFT_EN 18 7247 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 7248 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 7249 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 7250 #define SPT_PWM_GRANULARITY (1<<0) 7251 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 7252 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 7253 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 7254 #define LPT_PWM_GRANULARITY (1<<5) 7255 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 7256 7257 #define _FDI_RXA_CHICKEN 0xc200c 7258 #define _FDI_RXB_CHICKEN 0xc2010 7259 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 7260 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 7261 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 7262 7263 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 7264 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 7265 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 7266 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 7267 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 7268 7269 /* CPU: FDI_TX */ 7270 #define _FDI_TXA_CTL 0x60100 7271 #define _FDI_TXB_CTL 0x61100 7272 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 7273 #define FDI_TX_DISABLE (0<<31) 7274 #define FDI_TX_ENABLE (1<<31) 7275 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 7276 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 7277 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 7278 #define FDI_LINK_TRAIN_NONE (3<<28) 7279 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 7280 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 7281 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 7282 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 7283 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 7284 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 7285 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 7286 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 7287 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 7288 SNB has different settings. */ 7289 /* SNB A-stepping */ 7290 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 7291 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 7292 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 7293 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 7294 /* SNB B-stepping */ 7295 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 7296 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 7297 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 7298 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 7299 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 7300 #define FDI_DP_PORT_WIDTH_SHIFT 19 7301 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 7302 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 7303 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 7304 /* Ironlake: hardwired to 1 */ 7305 #define FDI_TX_PLL_ENABLE (1<<14) 7306 7307 /* Ivybridge has different bits for lolz */ 7308 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 7309 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 7310 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 7311 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 7312 7313 /* both Tx and Rx */ 7314 #define FDI_COMPOSITE_SYNC (1<<11) 7315 #define FDI_LINK_TRAIN_AUTO (1<<10) 7316 #define FDI_SCRAMBLING_ENABLE (0<<7) 7317 #define FDI_SCRAMBLING_DISABLE (1<<7) 7318 7319 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 7320 #define _FDI_RXA_CTL 0xf000c 7321 #define _FDI_RXB_CTL 0xf100c 7322 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 7323 #define FDI_RX_ENABLE (1<<31) 7324 /* train, dp width same as FDI_TX */ 7325 #define FDI_FS_ERRC_ENABLE (1<<27) 7326 #define FDI_FE_ERRC_ENABLE (1<<26) 7327 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 7328 #define FDI_8BPC (0<<16) 7329 #define FDI_10BPC (1<<16) 7330 #define FDI_6BPC (2<<16) 7331 #define FDI_12BPC (3<<16) 7332 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 7333 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 7334 #define FDI_RX_PLL_ENABLE (1<<13) 7335 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 7336 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 7337 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 7338 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 7339 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 7340 #define FDI_PCDCLK (1<<4) 7341 /* CPT */ 7342 #define FDI_AUTO_TRAINING (1<<10) 7343 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 7344 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 7345 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 7346 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 7347 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 7348 7349 #define _FDI_RXA_MISC 0xf0010 7350 #define _FDI_RXB_MISC 0xf1010 7351 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 7352 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 7353 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 7354 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 7355 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 7356 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 7357 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 7358 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 7359 7360 #define _FDI_RXA_TUSIZE1 0xf0030 7361 #define _FDI_RXA_TUSIZE2 0xf0038 7362 #define _FDI_RXB_TUSIZE1 0xf1030 7363 #define _FDI_RXB_TUSIZE2 0xf1038 7364 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 7365 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 7366 7367 /* FDI_RX interrupt register format */ 7368 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 7369 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 7370 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 7371 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 7372 #define FDI_RX_FS_CODE_ERR (1<<6) 7373 #define FDI_RX_FE_CODE_ERR (1<<5) 7374 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 7375 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 7376 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 7377 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 7378 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 7379 7380 #define _FDI_RXA_IIR 0xf0014 7381 #define _FDI_RXA_IMR 0xf0018 7382 #define _FDI_RXB_IIR 0xf1014 7383 #define _FDI_RXB_IMR 0xf1018 7384 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 7385 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 7386 7387 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 7388 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 7389 7390 #define PCH_LVDS _MMIO(0xe1180) 7391 #define LVDS_DETECTED (1 << 1) 7392 7393 #define _PCH_DP_B 0xe4100 7394 #define PCH_DP_B _MMIO(_PCH_DP_B) 7395 #define _PCH_DPB_AUX_CH_CTL 0xe4110 7396 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 7397 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 7398 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 7399 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 7400 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 7401 7402 #define _PCH_DP_C 0xe4200 7403 #define PCH_DP_C _MMIO(_PCH_DP_C) 7404 #define _PCH_DPC_AUX_CH_CTL 0xe4210 7405 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 7406 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 7407 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 7408 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 7409 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 7410 7411 #define _PCH_DP_D 0xe4300 7412 #define PCH_DP_D _MMIO(_PCH_DP_D) 7413 #define _PCH_DPD_AUX_CH_CTL 0xe4310 7414 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 7415 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 7416 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 7417 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 7418 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 7419 7420 #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 7421 #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 7422 7423 /* CPT */ 7424 #define PORT_TRANS_A_SEL_CPT 0 7425 #define PORT_TRANS_B_SEL_CPT (1<<29) 7426 #define PORT_TRANS_C_SEL_CPT (2<<29) 7427 #define PORT_TRANS_SEL_MASK (3<<29) 7428 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 7429 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 7430 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 7431 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 7432 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 7433 7434 #define _TRANS_DP_CTL_A 0xe0300 7435 #define _TRANS_DP_CTL_B 0xe1300 7436 #define _TRANS_DP_CTL_C 0xe2300 7437 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 7438 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 7439 #define TRANS_DP_PORT_SEL_B (0<<29) 7440 #define TRANS_DP_PORT_SEL_C (1<<29) 7441 #define TRANS_DP_PORT_SEL_D (2<<29) 7442 #define TRANS_DP_PORT_SEL_NONE (3<<29) 7443 #define TRANS_DP_PORT_SEL_MASK (3<<29) 7444 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) 7445 #define TRANS_DP_AUDIO_ONLY (1<<26) 7446 #define TRANS_DP_ENH_FRAMING (1<<18) 7447 #define TRANS_DP_8BPC (0<<9) 7448 #define TRANS_DP_10BPC (1<<9) 7449 #define TRANS_DP_6BPC (2<<9) 7450 #define TRANS_DP_12BPC (3<<9) 7451 #define TRANS_DP_BPC_MASK (3<<9) 7452 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 7453 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 7454 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 7455 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 7456 #define TRANS_DP_SYNC_MASK (3<<3) 7457 7458 /* SNB eDP training params */ 7459 /* SNB A-stepping */ 7460 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 7461 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 7462 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 7463 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 7464 /* SNB B-stepping */ 7465 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 7466 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 7467 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 7468 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 7469 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 7470 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 7471 7472 /* IVB */ 7473 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 7474 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 7475 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 7476 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 7477 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 7478 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 7479 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 7480 7481 /* legacy values */ 7482 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 7483 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 7484 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 7485 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 7486 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 7487 7488 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 7489 7490 #define VLV_PMWGICZ _MMIO(0x1300a4) 7491 7492 #define RC6_LOCATION _MMIO(0xD40) 7493 #define RC6_CTX_IN_DRAM (1 << 0) 7494 #define RC6_CTX_BASE _MMIO(0xD48) 7495 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 7496 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 7497 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 7498 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 7499 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 7500 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 7501 #define IDLE_TIME_MASK 0xFFFFF 7502 #define FORCEWAKE _MMIO(0xA18C) 7503 #define FORCEWAKE_VLV _MMIO(0x1300b0) 7504 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 7505 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 7506 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 7507 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 7508 #define FORCEWAKE_ACK _MMIO(0x130090) 7509 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 7510 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 7511 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 7512 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 7513 7514 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 7515 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 7516 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 7517 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 7518 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 7519 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 7520 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 7521 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 7522 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 7523 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 7524 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 7525 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 7526 #define FORCEWAKE_KERNEL 0x1 7527 #define FORCEWAKE_USER 0x2 7528 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 7529 #define ECOBUS _MMIO(0xa180) 7530 #define FORCEWAKE_MT_ENABLE (1<<5) 7531 #define VLV_SPAREG2H _MMIO(0xA194) 7532 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) 7533 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 7534 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 7535 7536 #define GTFIFODBG _MMIO(0x120000) 7537 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 7538 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 7539 #define GT_FIFO_SBDROPERR (1<<6) 7540 #define GT_FIFO_BLOBDROPERR (1<<5) 7541 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 7542 #define GT_FIFO_DROPERR (1<<3) 7543 #define GT_FIFO_OVFERR (1<<2) 7544 #define GT_FIFO_IAWRERR (1<<1) 7545 #define GT_FIFO_IARDERR (1<<0) 7546 7547 #define GTFIFOCTL _MMIO(0x120008) 7548 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 7549 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 7550 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 7551 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 7552 7553 #define HSW_IDICR _MMIO(0x9008) 7554 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 7555 #define HSW_EDRAM_CAP _MMIO(0x120010) 7556 #define EDRAM_ENABLED 0x1 7557 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 7558 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 7559 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 7560 7561 #define GEN6_UCGCTL1 _MMIO(0x9400) 7562 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 7563 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 7564 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 7565 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 7566 7567 #define GEN6_UCGCTL2 _MMIO(0x9404) 7568 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 7569 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 7570 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 7571 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 7572 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 7573 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 7574 7575 #define GEN6_UCGCTL3 _MMIO(0x9408) 7576 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 7577 7578 #define GEN7_UCGCTL4 _MMIO(0x940c) 7579 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 7580 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14) 7581 7582 #define GEN6_RCGCTL1 _MMIO(0x9410) 7583 #define GEN6_RCGCTL2 _MMIO(0x9414) 7584 #define GEN6_RSTCTL _MMIO(0x9420) 7585 7586 #define GEN8_UCGCTL6 _MMIO(0x9430) 7587 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) 7588 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 7589 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) 7590 7591 #define GEN6_GFXPAUSE _MMIO(0xA000) 7592 #define GEN6_RPNSWREQ _MMIO(0xA008) 7593 #define GEN6_TURBO_DISABLE (1<<31) 7594 #define GEN6_FREQUENCY(x) ((x)<<25) 7595 #define HSW_FREQUENCY(x) ((x)<<24) 7596 #define GEN9_FREQUENCY(x) ((x)<<23) 7597 #define GEN6_OFFSET(x) ((x)<<19) 7598 #define GEN6_AGGRESSIVE_TURBO (0<<15) 7599 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 7600 #define GEN6_RC_CONTROL _MMIO(0xA090) 7601 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 7602 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 7603 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 7604 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 7605 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 7606 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 7607 #define GEN7_RC_CTL_TO_MODE (1<<28) 7608 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 7609 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 7610 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 7611 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 7612 #define GEN6_RPSTAT1 _MMIO(0xA01C) 7613 #define GEN6_CAGF_SHIFT 8 7614 #define HSW_CAGF_SHIFT 7 7615 #define GEN9_CAGF_SHIFT 23 7616 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 7617 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 7618 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 7619 #define GEN6_RP_CONTROL _MMIO(0xA024) 7620 #define GEN6_RP_MEDIA_TURBO (1<<11) 7621 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 7622 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 7623 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 7624 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 7625 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 7626 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 7627 #define GEN6_RP_ENABLE (1<<7) 7628 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 7629 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 7630 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 7631 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 7632 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 7633 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 7634 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 7635 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 7636 #define GEN6_RP_EI_MASK 0xffffff 7637 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 7638 #define GEN6_RP_CUR_UP _MMIO(0xA054) 7639 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 7640 #define GEN6_RP_PREV_UP _MMIO(0xA058) 7641 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 7642 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 7643 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 7644 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 7645 #define GEN6_RP_UP_EI _MMIO(0xA068) 7646 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 7647 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 7648 #define GEN6_RPDEUHWTC _MMIO(0xA080) 7649 #define GEN6_RPDEUC _MMIO(0xA084) 7650 #define GEN6_RPDEUCSW _MMIO(0xA088) 7651 #define GEN6_RC_STATE _MMIO(0xA094) 7652 #define RC_SW_TARGET_STATE_SHIFT 16 7653 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 7654 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 7655 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 7656 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 7657 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 7658 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 7659 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 7660 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 7661 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 7662 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 7663 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 7664 #define VLV_RCEDATA _MMIO(0xA0BC) 7665 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 7666 #define GEN6_PMINTRMSK _MMIO(0xA168) 7667 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1<<31) 7668 #define ARAT_EXPIRED_INTRMSK (1<<9) 7669 #define GEN8_MISC_CTRL0 _MMIO(0xA180) 7670 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 7671 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 7672 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 7673 #define GEN9_PG_ENABLE _MMIO(0xA210) 7674 #define GEN9_RENDER_PG_ENABLE (1<<0) 7675 #define GEN9_MEDIA_PG_ENABLE (1<<1) 7676 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 7677 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 7678 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 7679 7680 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 7681 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 7682 #define PIXEL_OVERLAP_CNT_SHIFT 30 7683 7684 #define GEN6_PMISR _MMIO(0x44020) 7685 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 7686 #define GEN6_PMIIR _MMIO(0x44028) 7687 #define GEN6_PMIER _MMIO(0x4402C) 7688 #define GEN6_PM_MBOX_EVENT (1<<25) 7689 #define GEN6_PM_THERMAL_EVENT (1<<24) 7690 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 7691 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 7692 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 7693 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 7694 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 7695 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 7696 GEN6_PM_RP_DOWN_THRESHOLD | \ 7697 GEN6_PM_RP_DOWN_TIMEOUT) 7698 7699 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 7700 #define GEN7_GT_SCRATCH_REG_NUM 8 7701 7702 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 7703 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 7704 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 7705 7706 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 7707 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 7708 #define VLV_COUNT_RANGE_HIGH (1<<15) 7709 #define VLV_MEDIA_RC0_COUNT_EN (1<<5) 7710 #define VLV_RENDER_RC0_COUNT_EN (1<<4) 7711 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 7712 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 7713 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 7714 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 7715 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 7716 7717 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 7718 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 7719 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 7720 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 7721 7722 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 7723 #define GEN6_PCODE_READY (1<<31) 7724 #define GEN6_PCODE_ERROR_MASK 0xFF 7725 #define GEN6_PCODE_SUCCESS 0x0 7726 #define GEN6_PCODE_ILLEGAL_CMD 0x1 7727 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 7728 #define GEN6_PCODE_TIMEOUT 0x3 7729 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 7730 #define GEN7_PCODE_TIMEOUT 0x2 7731 #define GEN7_PCODE_ILLEGAL_DATA 0x3 7732 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 7733 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 7734 #define GEN6_PCODE_READ_RC6VIDS 0x5 7735 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 7736 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 7737 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 7738 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 7739 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 7740 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 7741 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 7742 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 7743 #define SKL_PCODE_CDCLK_CONTROL 0x7 7744 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 7745 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 7746 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 7747 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 7748 #define GEN6_READ_OC_PARAMS 0xc 7749 #define GEN6_PCODE_READ_D_COMP 0x10 7750 #define GEN6_PCODE_WRITE_D_COMP 0x11 7751 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 7752 #define DISPLAY_IPS_CONTROL 0x19 7753 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 7754 #define GEN9_PCODE_SAGV_CONTROL 0x21 7755 #define GEN9_SAGV_DISABLE 0x0 7756 #define GEN9_SAGV_IS_DISABLED 0x1 7757 #define GEN9_SAGV_ENABLE 0x3 7758 #define GEN6_PCODE_DATA _MMIO(0x138128) 7759 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 7760 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 7761 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 7762 7763 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 7764 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 7765 #define GEN6_RCn_MASK 7 7766 #define GEN6_RC0 0 7767 #define GEN6_RC3 2 7768 #define GEN6_RC6 3 7769 #define GEN6_RC7 4 7770 7771 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 7772 #define GEN8_LSLICESTAT_MASK 0x7 7773 7774 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 7775 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 7776 #define CHV_SS_PG_ENABLE (1<<1) 7777 #define CHV_EU08_PG_ENABLE (1<<9) 7778 #define CHV_EU19_PG_ENABLE (1<<17) 7779 #define CHV_EU210_PG_ENABLE (1<<25) 7780 7781 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 7782 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 7783 #define CHV_EU311_PG_ENABLE (1<<1) 7784 7785 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4) 7786 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 7787 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) 7788 7789 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8) 7790 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8) 7791 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 7792 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 7793 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 7794 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 7795 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 7796 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 7797 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 7798 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 7799 7800 #define GEN7_MISCCPCTL _MMIO(0x9424) 7801 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 7802 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2) 7803 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) 7804 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) 7805 7806 #define GEN8_GARBCNTL _MMIO(0xB004) 7807 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) 7808 7809 /* IVYBRIDGE DPF */ 7810 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 7811 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 7812 #define GEN7_PARITY_ERROR_VALID (1<<13) 7813 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 7814 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 7815 #define GEN7_PARITY_ERROR_ROW(reg) \ 7816 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 7817 #define GEN7_PARITY_ERROR_BANK(reg) \ 7818 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 7819 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 7820 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 7821 #define GEN7_L3CDERRST1_ENABLE (1<<7) 7822 7823 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 7824 #define GEN7_L3LOG_SIZE 0x80 7825 7826 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 7827 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 7828 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 7829 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 7830 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) 7831 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 7832 7833 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 7834 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) 7835 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) 7836 7837 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 7838 #define FLOW_CONTROL_ENABLE (1<<15) 7839 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 7840 #define STALL_DOP_GATING_DISABLE (1<<5) 7841 7842 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 7843 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 7844 #define DOP_CLOCK_GATING_DISABLE (1<<0) 7845 7846 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 7847 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 7848 7849 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 7850 #define GEN8_ST_PO_DISABLE (1<<13) 7851 7852 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 7853 #define HSW_SAMPLE_C_PERFORMANCE (1<<9) 7854 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 7855 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 7856 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 7857 7858 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 7859 #define GEN9_ENABLE_YV12_BUGFIX (1<<4) 7860 #define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2) 7861 7862 /* Audio */ 7863 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) 7864 #define INTEL_AUDIO_DEVCL 0x808629FB 7865 #define INTEL_AUDIO_DEVBLC 0x80862801 7866 #define INTEL_AUDIO_DEVCTG 0x80862802 7867 7868 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 7869 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 7870 #define G4X_ELDV_DEVCTG (1 << 14) 7871 #define G4X_ELD_ADDR_MASK (0xf << 5) 7872 #define G4X_ELD_ACK (1 << 4) 7873 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 7874 7875 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 7876 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 7877 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 7878 _IBX_HDMIW_HDMIEDID_B) 7879 #define _IBX_AUD_CNTL_ST_A 0xE20B4 7880 #define _IBX_AUD_CNTL_ST_B 0xE21B4 7881 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 7882 _IBX_AUD_CNTL_ST_B) 7883 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 7884 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 7885 #define IBX_ELD_ACK (1 << 4) 7886 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 7887 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 7888 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 7889 7890 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 7891 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 7892 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 7893 #define _CPT_AUD_CNTL_ST_A 0xE50B4 7894 #define _CPT_AUD_CNTL_ST_B 0xE51B4 7895 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 7896 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 7897 7898 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 7899 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 7900 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 7901 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 7902 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 7903 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 7904 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 7905 7906 /* These are the 4 32-bit write offset registers for each stream 7907 * output buffer. It determines the offset from the 7908 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 7909 */ 7910 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 7911 7912 #define _IBX_AUD_CONFIG_A 0xe2000 7913 #define _IBX_AUD_CONFIG_B 0xe2100 7914 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 7915 #define _CPT_AUD_CONFIG_A 0xe5000 7916 #define _CPT_AUD_CONFIG_B 0xe5100 7917 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 7918 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 7919 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 7920 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 7921 7922 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 7923 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 7924 #define AUD_CONFIG_UPPER_N_SHIFT 20 7925 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 7926 #define AUD_CONFIG_LOWER_N_SHIFT 4 7927 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 7928 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 7929 #define AUD_CONFIG_N(n) \ 7930 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 7931 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 7932 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 7933 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 7934 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 7935 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 7936 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 7937 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 7938 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 7939 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 7940 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 7941 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 7942 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 7943 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 7944 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 7945 7946 /* HSW Audio */ 7947 #define _HSW_AUD_CONFIG_A 0x65000 7948 #define _HSW_AUD_CONFIG_B 0x65100 7949 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 7950 7951 #define _HSW_AUD_MISC_CTRL_A 0x65010 7952 #define _HSW_AUD_MISC_CTRL_B 0x65110 7953 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 7954 7955 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 7956 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 7957 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 7958 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 7959 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 7960 #define AUD_CONFIG_M_MASK 0xfffff 7961 7962 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 7963 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 7964 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 7965 7966 /* Audio Digital Converter */ 7967 #define _HSW_AUD_DIG_CNVT_1 0x65080 7968 #define _HSW_AUD_DIG_CNVT_2 0x65180 7969 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 7970 #define DIP_PORT_SEL_MASK 0x3 7971 7972 #define _HSW_AUD_EDID_DATA_A 0x65050 7973 #define _HSW_AUD_EDID_DATA_B 0x65150 7974 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 7975 7976 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 7977 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 7978 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 7979 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 7980 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 7981 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 7982 7983 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 7984 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 7985 7986 /* HSW Power Wells */ 7987 #define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ 7988 #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ 7989 #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ 7990 #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ 7991 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 7992 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 7993 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 7994 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 7995 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 7996 #define HSW_PWR_WELL_FORCE_ON (1<<19) 7997 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 7998 7999 /* SKL Fuse Status */ 8000 #define SKL_FUSE_STATUS _MMIO(0x42000) 8001 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) 8002 #define SKL_FUSE_PG0_DIST_STATUS (1<<27) 8003 #define SKL_FUSE_PG1_DIST_STATUS (1<<26) 8004 #define SKL_FUSE_PG2_DIST_STATUS (1<<25) 8005 8006 /* Per-pipe DDI Function Control */ 8007 #define _TRANS_DDI_FUNC_CTL_A 0x60400 8008 #define _TRANS_DDI_FUNC_CTL_B 0x61400 8009 #define _TRANS_DDI_FUNC_CTL_C 0x62400 8010 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 8011 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 8012 8013 #define TRANS_DDI_FUNC_ENABLE (1<<31) 8014 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 8015 #define TRANS_DDI_PORT_MASK (7<<28) 8016 #define TRANS_DDI_PORT_SHIFT 28 8017 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 8018 #define TRANS_DDI_PORT_NONE (0<<28) 8019 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 8020 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 8021 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 8022 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 8023 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 8024 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 8025 #define TRANS_DDI_BPC_MASK (7<<20) 8026 #define TRANS_DDI_BPC_8 (0<<20) 8027 #define TRANS_DDI_BPC_10 (1<<20) 8028 #define TRANS_DDI_BPC_6 (2<<20) 8029 #define TRANS_DDI_BPC_12 (3<<20) 8030 #define TRANS_DDI_PVSYNC (1<<17) 8031 #define TRANS_DDI_PHSYNC (1<<16) 8032 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 8033 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 8034 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 8035 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 8036 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 8037 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 8038 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7) 8039 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6) 8040 #define TRANS_DDI_BFI_ENABLE (1<<4) 8041 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4) 8042 #define TRANS_DDI_HDMI_SCRAMBLING (1<<0) 8043 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 8044 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 8045 | TRANS_DDI_HDMI_SCRAMBLING) 8046 8047 /* DisplayPort Transport Control */ 8048 #define _DP_TP_CTL_A 0x64040 8049 #define _DP_TP_CTL_B 0x64140 8050 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 8051 #define DP_TP_CTL_ENABLE (1<<31) 8052 #define DP_TP_CTL_MODE_SST (0<<27) 8053 #define DP_TP_CTL_MODE_MST (1<<27) 8054 #define DP_TP_CTL_FORCE_ACT (1<<25) 8055 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 8056 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 8057 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 8058 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 8059 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 8060 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 8061 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 8062 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 8063 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 8064 8065 /* DisplayPort Transport Status */ 8066 #define _DP_TP_STATUS_A 0x64044 8067 #define _DP_TP_STATUS_B 0x64144 8068 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 8069 #define DP_TP_STATUS_IDLE_DONE (1<<25) 8070 #define DP_TP_STATUS_ACT_SENT (1<<24) 8071 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 8072 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 8073 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 8074 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 8075 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 8076 8077 /* DDI Buffer Control */ 8078 #define _DDI_BUF_CTL_A 0x64000 8079 #define _DDI_BUF_CTL_B 0x64100 8080 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 8081 #define DDI_BUF_CTL_ENABLE (1<<31) 8082 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 8083 #define DDI_BUF_EMP_MASK (0xf<<24) 8084 #define DDI_BUF_PORT_REVERSAL (1<<16) 8085 #define DDI_BUF_IS_IDLE (1<<7) 8086 #define DDI_A_4_LANES (1<<4) 8087 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 8088 #define DDI_PORT_WIDTH_MASK (7 << 1) 8089 #define DDI_PORT_WIDTH_SHIFT 1 8090 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 8091 8092 /* DDI Buffer Translations */ 8093 #define _DDI_BUF_TRANS_A 0x64E00 8094 #define _DDI_BUF_TRANS_B 0x64E60 8095 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 8096 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 8097 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 8098 8099 /* Sideband Interface (SBI) is programmed indirectly, via 8100 * SBI_ADDR, which contains the register offset; and SBI_DATA, 8101 * which contains the payload */ 8102 #define SBI_ADDR _MMIO(0xC6000) 8103 #define SBI_DATA _MMIO(0xC6004) 8104 #define SBI_CTL_STAT _MMIO(0xC6008) 8105 #define SBI_CTL_DEST_ICLK (0x0<<16) 8106 #define SBI_CTL_DEST_MPHY (0x1<<16) 8107 #define SBI_CTL_OP_IORD (0x2<<8) 8108 #define SBI_CTL_OP_IOWR (0x3<<8) 8109 #define SBI_CTL_OP_CRRD (0x6<<8) 8110 #define SBI_CTL_OP_CRWR (0x7<<8) 8111 #define SBI_RESPONSE_FAIL (0x1<<1) 8112 #define SBI_RESPONSE_SUCCESS (0x0<<1) 8113 #define SBI_BUSY (0x1<<0) 8114 #define SBI_READY (0x0<<0) 8115 8116 /* SBI offsets */ 8117 #define SBI_SSCDIVINTPHASE 0x0200 8118 #define SBI_SSCDIVINTPHASE6 0x0600 8119 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 8120 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1) 8121 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 8122 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 8123 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8) 8124 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 8125 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 8126 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 8127 #define SBI_SSCDITHPHASE 0x0204 8128 #define SBI_SSCCTL 0x020c 8129 #define SBI_SSCCTL6 0x060C 8130 #define SBI_SSCCTL_PATHALT (1<<3) 8131 #define SBI_SSCCTL_DISABLE (1<<0) 8132 #define SBI_SSCAUXDIV6 0x0610 8133 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 8134 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4) 8135 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 8136 #define SBI_DBUFF0 0x2a00 8137 #define SBI_GEN0 0x1f00 8138 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 8139 8140 /* LPT PIXCLK_GATE */ 8141 #define PIXCLK_GATE _MMIO(0xC6020) 8142 #define PIXCLK_GATE_UNGATE (1<<0) 8143 #define PIXCLK_GATE_GATE (0<<0) 8144 8145 /* SPLL */ 8146 #define SPLL_CTL _MMIO(0x46020) 8147 #define SPLL_PLL_ENABLE (1<<31) 8148 #define SPLL_PLL_SSC (1<<28) 8149 #define SPLL_PLL_NON_SSC (2<<28) 8150 #define SPLL_PLL_LCPLL (3<<28) 8151 #define SPLL_PLL_REF_MASK (3<<28) 8152 #define SPLL_PLL_FREQ_810MHz (0<<26) 8153 #define SPLL_PLL_FREQ_1350MHz (1<<26) 8154 #define SPLL_PLL_FREQ_2700MHz (2<<26) 8155 #define SPLL_PLL_FREQ_MASK (3<<26) 8156 8157 /* WRPLL */ 8158 #define _WRPLL_CTL1 0x46040 8159 #define _WRPLL_CTL2 0x46060 8160 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 8161 #define WRPLL_PLL_ENABLE (1<<31) 8162 #define WRPLL_PLL_SSC (1<<28) 8163 #define WRPLL_PLL_NON_SSC (2<<28) 8164 #define WRPLL_PLL_LCPLL (3<<28) 8165 #define WRPLL_PLL_REF_MASK (3<<28) 8166 /* WRPLL divider programming */ 8167 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 8168 #define WRPLL_DIVIDER_REF_MASK (0xff) 8169 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 8170 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 8171 #define WRPLL_DIVIDER_POST_SHIFT 8 8172 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 8173 #define WRPLL_DIVIDER_FB_SHIFT 16 8174 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 8175 8176 /* Port clock selection */ 8177 #define _PORT_CLK_SEL_A 0x46100 8178 #define _PORT_CLK_SEL_B 0x46104 8179 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 8180 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 8181 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 8182 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 8183 #define PORT_CLK_SEL_SPLL (3<<29) 8184 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 8185 #define PORT_CLK_SEL_WRPLL1 (4<<29) 8186 #define PORT_CLK_SEL_WRPLL2 (5<<29) 8187 #define PORT_CLK_SEL_NONE (7<<29) 8188 #define PORT_CLK_SEL_MASK (7<<29) 8189 8190 /* Transcoder clock selection */ 8191 #define _TRANS_CLK_SEL_A 0x46140 8192 #define _TRANS_CLK_SEL_B 0x46144 8193 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 8194 /* For each transcoder, we need to select the corresponding port clock */ 8195 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 8196 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) 8197 8198 #define CDCLK_FREQ _MMIO(0x46200) 8199 8200 #define _TRANSA_MSA_MISC 0x60410 8201 #define _TRANSB_MSA_MISC 0x61410 8202 #define _TRANSC_MSA_MISC 0x62410 8203 #define _TRANS_EDP_MSA_MISC 0x6f410 8204 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 8205 8206 #define TRANS_MSA_SYNC_CLK (1<<0) 8207 #define TRANS_MSA_6_BPC (0<<5) 8208 #define TRANS_MSA_8_BPC (1<<5) 8209 #define TRANS_MSA_10_BPC (2<<5) 8210 #define TRANS_MSA_12_BPC (3<<5) 8211 #define TRANS_MSA_16_BPC (4<<5) 8212 8213 /* LCPLL Control */ 8214 #define LCPLL_CTL _MMIO(0x130040) 8215 #define LCPLL_PLL_DISABLE (1<<31) 8216 #define LCPLL_PLL_LOCK (1<<30) 8217 #define LCPLL_CLK_FREQ_MASK (3<<26) 8218 #define LCPLL_CLK_FREQ_450 (0<<26) 8219 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 8220 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 8221 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 8222 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 8223 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24) 8224 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 8225 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 8226 #define LCPLL_CD_SOURCE_FCLK (1<<21) 8227 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 8228 8229 /* 8230 * SKL Clocks 8231 */ 8232 8233 /* CDCLK_CTL */ 8234 #define CDCLK_CTL _MMIO(0x46000) 8235 #define CDCLK_FREQ_SEL_MASK (3<<26) 8236 #define CDCLK_FREQ_450_432 (0<<26) 8237 #define CDCLK_FREQ_540 (1<<26) 8238 #define CDCLK_FREQ_337_308 (2<<26) 8239 #define CDCLK_FREQ_675_617 (3<<26) 8240 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) 8241 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) 8242 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) 8243 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) 8244 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) 8245 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) 8246 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 8247 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) 8248 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 8249 8250 /* LCPLL_CTL */ 8251 #define LCPLL1_CTL _MMIO(0x46010) 8252 #define LCPLL2_CTL _MMIO(0x46014) 8253 #define LCPLL_PLL_ENABLE (1<<31) 8254 8255 /* DPLL control1 */ 8256 #define DPLL_CTRL1 _MMIO(0x6C058) 8257 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) 8258 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) 8259 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) 8260 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) 8261 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) 8262 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) 8263 #define DPLL_CTRL1_LINK_RATE_2700 0 8264 #define DPLL_CTRL1_LINK_RATE_1350 1 8265 #define DPLL_CTRL1_LINK_RATE_810 2 8266 #define DPLL_CTRL1_LINK_RATE_1620 3 8267 #define DPLL_CTRL1_LINK_RATE_1080 4 8268 #define DPLL_CTRL1_LINK_RATE_2160 5 8269 8270 /* DPLL control2 */ 8271 #define DPLL_CTRL2 _MMIO(0x6C05C) 8272 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15)) 8273 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) 8274 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) 8275 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1)) 8276 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) 8277 8278 /* DPLL Status */ 8279 #define DPLL_STATUS _MMIO(0x6C060) 8280 #define DPLL_LOCK(id) (1<<((id)*8)) 8281 8282 /* DPLL cfg */ 8283 #define _DPLL1_CFGCR1 0x6C040 8284 #define _DPLL2_CFGCR1 0x6C048 8285 #define _DPLL3_CFGCR1 0x6C050 8286 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) 8287 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) 8288 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9) 8289 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 8290 8291 #define _DPLL1_CFGCR2 0x6C044 8292 #define _DPLL2_CFGCR2 0x6C04C 8293 #define _DPLL3_CFGCR2 0x6C054 8294 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) 8295 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8) 8296 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7) 8297 #define DPLL_CFGCR2_KDIV_MASK (3<<5) 8298 #define DPLL_CFGCR2_KDIV(x) ((x)<<5) 8299 #define DPLL_CFGCR2_KDIV_5 (0<<5) 8300 #define DPLL_CFGCR2_KDIV_2 (1<<5) 8301 #define DPLL_CFGCR2_KDIV_3 (2<<5) 8302 #define DPLL_CFGCR2_KDIV_1 (3<<5) 8303 #define DPLL_CFGCR2_PDIV_MASK (7<<2) 8304 #define DPLL_CFGCR2_PDIV(x) ((x)<<2) 8305 #define DPLL_CFGCR2_PDIV_1 (0<<2) 8306 #define DPLL_CFGCR2_PDIV_2 (1<<2) 8307 #define DPLL_CFGCR2_PDIV_3 (2<<2) 8308 #define DPLL_CFGCR2_PDIV_7 (4<<2) 8309 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 8310 8311 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 8312 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 8313 8314 /* 8315 * CNL Clocks 8316 */ 8317 #define DPCLKA_CFGCR0 _MMIO(0x6C200) 8318 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)+10)) 8319 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << ((port)*2)) 8320 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port)*2) 8321 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2)) 8322 8323 /* CNL PLL */ 8324 #define DPLL0_ENABLE 0x46010 8325 #define DPLL1_ENABLE 0x46014 8326 #define PLL_ENABLE (1 << 31) 8327 #define PLL_LOCK (1 << 30) 8328 #define PLL_POWER_ENABLE (1 << 27) 8329 #define PLL_POWER_STATE (1 << 26) 8330 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) 8331 8332 #define _CNL_DPLL0_CFGCR0 0x6C000 8333 #define _CNL_DPLL1_CFGCR0 0x6C080 8334 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 8335 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 8336 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 8337 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 8338 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 8339 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 8340 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 8341 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 8342 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 8343 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 8344 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 8345 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 8346 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 8347 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 8348 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) 8349 8350 #define _CNL_DPLL0_CFGCR1 0x6C004 8351 #define _CNL_DPLL1_CFGCR1 0x6C084 8352 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 8353 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 8354 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 8355 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 8356 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 8357 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 8358 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 8359 #define DPLL_CFGCR1_KDIV_4 (4 << 6) 8360 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 8361 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 8362 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 8363 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 8364 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 8365 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 8366 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 8367 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) 8368 8369 /* BXT display engine PLL */ 8370 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 8371 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 8372 #define BXT_DE_PLL_RATIO_MASK 0xff 8373 8374 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 8375 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 8376 #define BXT_DE_PLL_LOCK (1 << 30) 8377 #define CNL_CDCLK_PLL_RATIO(x) (x) 8378 #define CNL_CDCLK_PLL_RATIO_MASK 0xff 8379 8380 /* GEN9 DC */ 8381 #define DC_STATE_EN _MMIO(0x45504) 8382 #define DC_STATE_DISABLE 0 8383 #define DC_STATE_EN_UPTO_DC5 (1<<0) 8384 #define DC_STATE_EN_DC9 (1<<3) 8385 #define DC_STATE_EN_UPTO_DC6 (2<<0) 8386 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 8387 8388 #define DC_STATE_DEBUG _MMIO(0x45520) 8389 #define DC_STATE_DEBUG_MASK_CORES (1<<0) 8390 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) 8391 8392 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 8393 * since on HSW we can't write to it using I915_WRITE. */ 8394 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 8395 #define D_COMP_BDW _MMIO(0x138144) 8396 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 8397 #define D_COMP_COMP_FORCE (1<<8) 8398 #define D_COMP_COMP_DISABLE (1<<0) 8399 8400 /* Pipe WM_LINETIME - watermark line time */ 8401 #define _PIPE_WM_LINETIME_A 0x45270 8402 #define _PIPE_WM_LINETIME_B 0x45274 8403 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) 8404 #define PIPE_WM_LINETIME_MASK (0x1ff) 8405 #define PIPE_WM_LINETIME_TIME(x) ((x)) 8406 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 8407 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 8408 8409 /* SFUSE_STRAP */ 8410 #define SFUSE_STRAP _MMIO(0xc2014) 8411 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 8412 #define SFUSE_STRAP_RAW_FREQUENCY (1<<8) 8413 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 8414 #define SFUSE_STRAP_CRT_DISABLED (1<<6) 8415 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 8416 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 8417 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 8418 8419 #define WM_MISC _MMIO(0x45260) 8420 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 8421 8422 #define WM_DBG _MMIO(0x45280) 8423 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 8424 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 8425 #define WM_DBG_DISALLOW_SPRITE (1<<2) 8426 8427 /* pipe CSC */ 8428 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 8429 #define _PIPE_A_CSC_COEFF_BY 0x49014 8430 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 8431 #define _PIPE_A_CSC_COEFF_BU 0x4901c 8432 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 8433 #define _PIPE_A_CSC_COEFF_BV 0x49024 8434 #define _PIPE_A_CSC_MODE 0x49028 8435 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 8436 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 8437 #define CSC_MODE_YUV_TO_RGB (1 << 0) 8438 #define _PIPE_A_CSC_PREOFF_HI 0x49030 8439 #define _PIPE_A_CSC_PREOFF_ME 0x49034 8440 #define _PIPE_A_CSC_PREOFF_LO 0x49038 8441 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 8442 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 8443 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 8444 8445 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 8446 #define _PIPE_B_CSC_COEFF_BY 0x49114 8447 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 8448 #define _PIPE_B_CSC_COEFF_BU 0x4911c 8449 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 8450 #define _PIPE_B_CSC_COEFF_BV 0x49124 8451 #define _PIPE_B_CSC_MODE 0x49128 8452 #define _PIPE_B_CSC_PREOFF_HI 0x49130 8453 #define _PIPE_B_CSC_PREOFF_ME 0x49134 8454 #define _PIPE_B_CSC_PREOFF_LO 0x49138 8455 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 8456 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 8457 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 8458 8459 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 8460 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 8461 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 8462 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 8463 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 8464 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 8465 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 8466 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 8467 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 8468 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 8469 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 8470 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 8471 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 8472 8473 /* pipe degamma/gamma LUTs on IVB+ */ 8474 #define _PAL_PREC_INDEX_A 0x4A400 8475 #define _PAL_PREC_INDEX_B 0x4AC00 8476 #define _PAL_PREC_INDEX_C 0x4B400 8477 #define PAL_PREC_10_12_BIT (0 << 31) 8478 #define PAL_PREC_SPLIT_MODE (1 << 31) 8479 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 8480 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 8481 #define _PAL_PREC_DATA_A 0x4A404 8482 #define _PAL_PREC_DATA_B 0x4AC04 8483 #define _PAL_PREC_DATA_C 0x4B404 8484 #define _PAL_PREC_GC_MAX_A 0x4A410 8485 #define _PAL_PREC_GC_MAX_B 0x4AC10 8486 #define _PAL_PREC_GC_MAX_C 0x4B410 8487 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 8488 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 8489 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 8490 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 8491 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 8492 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 8493 8494 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 8495 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 8496 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 8497 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 8498 8499 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 8500 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 8501 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 8502 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 8503 #define _PRE_CSC_GAMC_DATA_A 0x4A488 8504 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 8505 #define _PRE_CSC_GAMC_DATA_C 0x4B488 8506 8507 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 8508 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 8509 8510 /* pipe CSC & degamma/gamma LUTs on CHV */ 8511 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 8512 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 8513 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 8514 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 8515 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 8516 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 8517 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 8518 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 8519 #define CGM_PIPE_MODE_GAMMA (1 << 2) 8520 #define CGM_PIPE_MODE_CSC (1 << 1) 8521 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 8522 8523 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 8524 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 8525 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 8526 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 8527 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 8528 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 8529 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 8530 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 8531 8532 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 8533 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 8534 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 8535 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 8536 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 8537 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 8538 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 8539 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 8540 8541 /* MIPI DSI registers */ 8542 8543 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 8544 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 8545 8546 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 8547 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 8548 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 8549 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 8550 8551 /* BXT MIPI clock controls */ 8552 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 8553 8554 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 8555 #define BXT_MIPI1_DIV_SHIFT 26 8556 #define BXT_MIPI2_DIV_SHIFT 10 8557 #define BXT_MIPI_DIV_SHIFT(port) \ 8558 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 8559 BXT_MIPI2_DIV_SHIFT) 8560 8561 /* TX control divider to select actual TX clock output from (8x/var) */ 8562 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 8563 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 8564 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 8565 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 8566 BXT_MIPI2_TX_ESCLK_SHIFT) 8567 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 8568 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 8569 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 8570 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 8571 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 8572 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 8573 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 8574 /* RX upper control divider to select actual RX clock output from 8x */ 8575 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 8576 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 8577 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 8578 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 8579 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 8580 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 8581 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 8582 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 8583 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 8584 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 8585 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 8586 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 8587 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 8588 #define BXT_MIPI1_8X_BY3_SHIFT 19 8589 #define BXT_MIPI2_8X_BY3_SHIFT 3 8590 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 8591 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 8592 BXT_MIPI2_8X_BY3_SHIFT) 8593 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 8594 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 8595 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 8596 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 8597 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 8598 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 8599 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 8600 /* RX lower control divider to select actual RX clock output from 8x */ 8601 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 8602 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 8603 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 8604 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 8605 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 8606 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 8607 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 8608 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 8609 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 8610 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 8611 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 8612 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 8613 8614 #define RX_DIVIDER_BIT_1_2 0x3 8615 #define RX_DIVIDER_BIT_3_4 0xC 8616 8617 /* BXT MIPI mode configure */ 8618 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 8619 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 8620 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 8621 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 8622 8623 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 8624 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 8625 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 8626 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 8627 8628 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 8629 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 8630 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 8631 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 8632 8633 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 8634 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 8635 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 8636 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 8637 #define BXT_DSIC_16X_BY1 (0 << 10) 8638 #define BXT_DSIC_16X_BY2 (1 << 10) 8639 #define BXT_DSIC_16X_BY3 (2 << 10) 8640 #define BXT_DSIC_16X_BY4 (3 << 10) 8641 #define BXT_DSIC_16X_MASK (3 << 10) 8642 #define BXT_DSIA_16X_BY1 (0 << 8) 8643 #define BXT_DSIA_16X_BY2 (1 << 8) 8644 #define BXT_DSIA_16X_BY3 (2 << 8) 8645 #define BXT_DSIA_16X_BY4 (3 << 8) 8646 #define BXT_DSIA_16X_MASK (3 << 8) 8647 #define BXT_DSI_FREQ_SEL_SHIFT 8 8648 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 8649 8650 #define BXT_DSI_PLL_RATIO_MAX 0x7D 8651 #define BXT_DSI_PLL_RATIO_MIN 0x22 8652 #define GLK_DSI_PLL_RATIO_MAX 0x6F 8653 #define GLK_DSI_PLL_RATIO_MIN 0x22 8654 #define BXT_DSI_PLL_RATIO_MASK 0xFF 8655 #define BXT_REF_CLOCK_KHZ 19200 8656 8657 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 8658 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 8659 #define BXT_DSI_PLL_LOCKED (1 << 30) 8660 8661 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 8662 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 8663 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 8664 8665 /* BXT port control */ 8666 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 8667 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 8668 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 8669 8670 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 8671 #define STAP_SELECT (1 << 0) 8672 8673 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 8674 #define HS_IO_CTRL_SELECT (1 << 0) 8675 8676 #define DPI_ENABLE (1 << 31) /* A + C */ 8677 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 8678 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 8679 #define DUAL_LINK_MODE_SHIFT 26 8680 #define DUAL_LINK_MODE_MASK (1 << 26) 8681 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 8682 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 8683 #define DITHERING_ENABLE (1 << 25) /* A + C */ 8684 #define FLOPPED_HSTX (1 << 23) 8685 #define DE_INVERT (1 << 19) /* XXX */ 8686 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 8687 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 8688 #define AFE_LATCHOUT (1 << 17) 8689 #define LP_OUTPUT_HOLD (1 << 16) 8690 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 8691 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 8692 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 8693 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 8694 #define CSB_SHIFT 9 8695 #define CSB_MASK (3 << 9) 8696 #define CSB_20MHZ (0 << 9) 8697 #define CSB_10MHZ (1 << 9) 8698 #define CSB_40MHZ (2 << 9) 8699 #define BANDGAP_MASK (1 << 8) 8700 #define BANDGAP_PNW_CIRCUIT (0 << 8) 8701 #define BANDGAP_LNC_CIRCUIT (1 << 8) 8702 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 8703 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 8704 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 8705 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 8706 #define TEARING_EFFECT_MASK (3 << 2) 8707 #define TEARING_EFFECT_OFF (0 << 2) 8708 #define TEARING_EFFECT_DSI (1 << 2) 8709 #define TEARING_EFFECT_GPIO (2 << 2) 8710 #define LANE_CONFIGURATION_SHIFT 0 8711 #define LANE_CONFIGURATION_MASK (3 << 0) 8712 #define LANE_CONFIGURATION_4LANE (0 << 0) 8713 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 8714 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 8715 8716 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 8717 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 8718 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 8719 #define TEARING_EFFECT_DELAY_SHIFT 0 8720 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 8721 8722 /* XXX: all bits reserved */ 8723 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 8724 8725 /* MIPI DSI Controller and D-PHY registers */ 8726 8727 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 8728 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 8729 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 8730 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 8731 #define ULPS_STATE_MASK (3 << 1) 8732 #define ULPS_STATE_ENTER (2 << 1) 8733 #define ULPS_STATE_EXIT (1 << 1) 8734 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 8735 #define DEVICE_READY (1 << 0) 8736 8737 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 8738 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 8739 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 8740 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 8741 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 8742 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 8743 #define TEARING_EFFECT (1 << 31) 8744 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 8745 #define GEN_READ_DATA_AVAIL (1 << 29) 8746 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 8747 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 8748 #define RX_PROT_VIOLATION (1 << 26) 8749 #define RX_INVALID_TX_LENGTH (1 << 25) 8750 #define ACK_WITH_NO_ERROR (1 << 24) 8751 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 8752 #define LP_RX_TIMEOUT (1 << 22) 8753 #define HS_TX_TIMEOUT (1 << 21) 8754 #define DPI_FIFO_UNDERRUN (1 << 20) 8755 #define LOW_CONTENTION (1 << 19) 8756 #define HIGH_CONTENTION (1 << 18) 8757 #define TXDSI_VC_ID_INVALID (1 << 17) 8758 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 8759 #define TXCHECKSUM_ERROR (1 << 15) 8760 #define TXECC_MULTIBIT_ERROR (1 << 14) 8761 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 8762 #define TXFALSE_CONTROL_ERROR (1 << 12) 8763 #define RXDSI_VC_ID_INVALID (1 << 11) 8764 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 8765 #define RXCHECKSUM_ERROR (1 << 9) 8766 #define RXECC_MULTIBIT_ERROR (1 << 8) 8767 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 8768 #define RXFALSE_CONTROL_ERROR (1 << 6) 8769 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 8770 #define RX_LP_TX_SYNC_ERROR (1 << 4) 8771 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 8772 #define RXEOT_SYNC_ERROR (1 << 2) 8773 #define RXSOT_SYNC_ERROR (1 << 1) 8774 #define RXSOT_ERROR (1 << 0) 8775 8776 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 8777 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 8778 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 8779 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 8780 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 8781 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 8782 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 8783 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 8784 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 8785 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 8786 #define VID_MODE_FORMAT_MASK (0xf << 7) 8787 #define VID_MODE_NOT_SUPPORTED (0 << 7) 8788 #define VID_MODE_FORMAT_RGB565 (1 << 7) 8789 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 8790 #define VID_MODE_FORMAT_RGB666 (3 << 7) 8791 #define VID_MODE_FORMAT_RGB888 (4 << 7) 8792 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 8793 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 8794 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 8795 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 8796 #define DATA_LANES_PRG_REG_SHIFT 0 8797 #define DATA_LANES_PRG_REG_MASK (7 << 0) 8798 8799 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 8800 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 8801 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 8802 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 8803 8804 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 8805 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 8806 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 8807 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 8808 8809 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 8810 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 8811 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 8812 #define TURN_AROUND_TIMEOUT_MASK 0x3f 8813 8814 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 8815 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 8816 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 8817 #define DEVICE_RESET_TIMER_MASK 0xffff 8818 8819 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 8820 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 8821 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 8822 #define VERTICAL_ADDRESS_SHIFT 16 8823 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 8824 #define HORIZONTAL_ADDRESS_SHIFT 0 8825 #define HORIZONTAL_ADDRESS_MASK 0xffff 8826 8827 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 8828 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 8829 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 8830 #define DBI_FIFO_EMPTY_HALF (0 << 0) 8831 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 8832 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 8833 8834 /* regs below are bits 15:0 */ 8835 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 8836 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 8837 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 8838 8839 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 8840 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 8841 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 8842 8843 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 8844 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 8845 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 8846 8847 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 8848 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 8849 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 8850 8851 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 8852 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 8853 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 8854 8855 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 8856 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 8857 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 8858 8859 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 8860 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 8861 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 8862 8863 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 8864 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 8865 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 8866 8867 /* regs above are bits 15:0 */ 8868 8869 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 8870 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 8871 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 8872 #define DPI_LP_MODE (1 << 6) 8873 #define BACKLIGHT_OFF (1 << 5) 8874 #define BACKLIGHT_ON (1 << 4) 8875 #define COLOR_MODE_OFF (1 << 3) 8876 #define COLOR_MODE_ON (1 << 2) 8877 #define TURN_ON (1 << 1) 8878 #define SHUTDOWN (1 << 0) 8879 8880 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 8881 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 8882 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 8883 #define COMMAND_BYTE_SHIFT 0 8884 #define COMMAND_BYTE_MASK (0x3f << 0) 8885 8886 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 8887 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 8888 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 8889 #define MASTER_INIT_TIMER_SHIFT 0 8890 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 8891 8892 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 8893 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 8894 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 8895 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 8896 #define MAX_RETURN_PKT_SIZE_SHIFT 0 8897 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 8898 8899 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 8900 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 8901 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 8902 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 8903 #define DISABLE_VIDEO_BTA (1 << 3) 8904 #define IP_TG_CONFIG (1 << 2) 8905 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 8906 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 8907 #define VIDEO_MODE_BURST (3 << 0) 8908 8909 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 8910 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 8911 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 8912 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 8913 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 8914 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 8915 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 8916 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 8917 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 8918 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 8919 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 8920 #define CLOCKSTOP (1 << 1) 8921 #define EOT_DISABLE (1 << 0) 8922 8923 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 8924 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 8925 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 8926 #define LP_BYTECLK_SHIFT 0 8927 #define LP_BYTECLK_MASK (0xffff << 0) 8928 8929 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 8930 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 8931 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 8932 8933 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 8934 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 8935 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 8936 8937 /* bits 31:0 */ 8938 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 8939 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 8940 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 8941 8942 /* bits 31:0 */ 8943 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 8944 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 8945 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 8946 8947 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 8948 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 8949 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 8950 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 8951 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 8952 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 8953 #define LONG_PACKET_WORD_COUNT_SHIFT 8 8954 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 8955 #define SHORT_PACKET_PARAM_SHIFT 8 8956 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 8957 #define VIRTUAL_CHANNEL_SHIFT 6 8958 #define VIRTUAL_CHANNEL_MASK (3 << 6) 8959 #define DATA_TYPE_SHIFT 0 8960 #define DATA_TYPE_MASK (0x3f << 0) 8961 /* data type values, see include/video/mipi_display.h */ 8962 8963 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 8964 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 8965 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 8966 #define DPI_FIFO_EMPTY (1 << 28) 8967 #define DBI_FIFO_EMPTY (1 << 27) 8968 #define LP_CTRL_FIFO_EMPTY (1 << 26) 8969 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 8970 #define LP_CTRL_FIFO_FULL (1 << 24) 8971 #define HS_CTRL_FIFO_EMPTY (1 << 18) 8972 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 8973 #define HS_CTRL_FIFO_FULL (1 << 16) 8974 #define LP_DATA_FIFO_EMPTY (1 << 10) 8975 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 8976 #define LP_DATA_FIFO_FULL (1 << 8) 8977 #define HS_DATA_FIFO_EMPTY (1 << 2) 8978 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 8979 #define HS_DATA_FIFO_FULL (1 << 0) 8980 8981 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 8982 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 8983 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 8984 #define DBI_HS_LP_MODE_MASK (1 << 0) 8985 #define DBI_LP_MODE (1 << 0) 8986 #define DBI_HS_MODE (0 << 0) 8987 8988 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 8989 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 8990 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 8991 #define EXIT_ZERO_COUNT_SHIFT 24 8992 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 8993 #define TRAIL_COUNT_SHIFT 16 8994 #define TRAIL_COUNT_MASK (0x1f << 16) 8995 #define CLK_ZERO_COUNT_SHIFT 8 8996 #define CLK_ZERO_COUNT_MASK (0xff << 8) 8997 #define PREPARE_COUNT_SHIFT 0 8998 #define PREPARE_COUNT_MASK (0x3f << 0) 8999 9000 /* bits 31:0 */ 9001 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 9002 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 9003 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 9004 9005 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 9006 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 9007 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 9008 #define LP_HS_SSW_CNT_SHIFT 16 9009 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 9010 #define HS_LP_PWR_SW_CNT_SHIFT 0 9011 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 9012 9013 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 9014 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 9015 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 9016 #define STOP_STATE_STALL_COUNTER_SHIFT 0 9017 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 9018 9019 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 9020 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 9021 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 9022 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 9023 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 9024 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 9025 #define RX_CONTENTION_DETECTED (1 << 0) 9026 9027 /* XXX: only pipe A ?!? */ 9028 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 9029 #define DBI_TYPEC_ENABLE (1 << 31) 9030 #define DBI_TYPEC_WIP (1 << 30) 9031 #define DBI_TYPEC_OPTION_SHIFT 28 9032 #define DBI_TYPEC_OPTION_MASK (3 << 28) 9033 #define DBI_TYPEC_FREQ_SHIFT 24 9034 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 9035 #define DBI_TYPEC_OVERRIDE (1 << 8) 9036 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 9037 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 9038 9039 9040 /* MIPI adapter registers */ 9041 9042 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 9043 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 9044 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 9045 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 9046 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 9047 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 9048 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 9049 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 9050 #define READ_REQUEST_PRIORITY_SHIFT 3 9051 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 9052 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 9053 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 9054 #define RGB_FLIP_TO_BGR (1 << 2) 9055 9056 #define BXT_PIPE_SELECT_SHIFT 7 9057 #define BXT_PIPE_SELECT_MASK (7 << 7) 9058 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 9059 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 9060 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 9061 #define GLK_MIPIIO_RESET_RELEASED (1 << 28) 9062 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 9063 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 9064 #define GLK_LP_WAKE (1 << 22) 9065 #define GLK_LP11_LOW_PWR_MODE (1 << 21) 9066 #define GLK_LP00_LOW_PWR_MODE (1 << 20) 9067 #define GLK_FIREWALL_ENABLE (1 << 16) 9068 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 9069 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 9070 #define BXT_DSC_ENABLE (1 << 3) 9071 #define BXT_RGB_FLIP (1 << 2) 9072 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 9073 #define GLK_MIPIIO_ENABLE (1 << 0) 9074 9075 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 9076 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 9077 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 9078 #define DATA_MEM_ADDRESS_SHIFT 5 9079 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 9080 #define DATA_VALID (1 << 0) 9081 9082 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 9083 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 9084 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 9085 #define DATA_LENGTH_SHIFT 0 9086 #define DATA_LENGTH_MASK (0xfffff << 0) 9087 9088 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 9089 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 9090 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 9091 #define COMMAND_MEM_ADDRESS_SHIFT 5 9092 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 9093 #define AUTO_PWG_ENABLE (1 << 2) 9094 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 9095 #define COMMAND_VALID (1 << 0) 9096 9097 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 9098 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 9099 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 9100 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 9101 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 9102 9103 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 9104 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 9105 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 9106 9107 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 9108 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 9109 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 9110 #define READ_DATA_VALID(n) (1 << (n)) 9111 9112 /* For UMS only (deprecated): */ 9113 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 9114 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 9115 9116 /* MOCS (Memory Object Control State) registers */ 9117 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 9118 9119 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ 9120 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ 9121 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ 9122 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ 9123 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ 9124 9125 /* gamt regs */ 9126 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 9127 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 9128 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 9129 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 9130 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 9131 9132 #endif /* _I915_REG_H_ */ 9133