1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 #include "display/intel_display_reg_defs.h" 30 31 /** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119 #define GU_CNTL_PROTECTED _MMIO(0x10100C) 120 #define DEPRESENT REG_BIT(9) 121 122 #define GU_CNTL _MMIO(0x101010) 123 #define LMEM_INIT REG_BIT(7) 124 #define DRIVERFLR REG_BIT(31) 125 #define GU_DEBUG _MMIO(0x101018) 126 #define DRIVERFLR_STATUS REG_BIT(31) 127 128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 131 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 132 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 133 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 134 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 135 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 136 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 137 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 138 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 139 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 140 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 141 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 142 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 143 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 146 147 #define _VGA_MSR_WRITE _MMIO(0x3c2) 148 149 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 150 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 151 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 152 153 /* 154 * Reset registers 155 */ 156 #define DEBUG_RESET_I830 _MMIO(0x6070) 157 #define DEBUG_RESET_FULL (1 << 7) 158 #define DEBUG_RESET_RENDER (1 << 8) 159 #define DEBUG_RESET_DISPLAY (1 << 9) 160 161 /* 162 * IOSF sideband 163 */ 164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 165 #define IOSF_DEVFN_SHIFT 24 166 #define IOSF_OPCODE_SHIFT 16 167 #define IOSF_PORT_SHIFT 8 168 #define IOSF_BYTE_ENABLES_SHIFT 4 169 #define IOSF_BAR_SHIFT 1 170 #define IOSF_SB_BUSY (1 << 0) 171 #define IOSF_PORT_BUNIT 0x03 172 #define IOSF_PORT_PUNIT 0x04 173 #define IOSF_PORT_NC 0x11 174 #define IOSF_PORT_DPIO 0x12 175 #define IOSF_PORT_GPIO_NC 0x13 176 #define IOSF_PORT_CCK 0x14 177 #define IOSF_PORT_DPIO_2 0x1a 178 #define IOSF_PORT_FLISDSI 0x1b 179 #define IOSF_PORT_GPIO_SC 0x48 180 #define IOSF_PORT_GPIO_SUS 0xa8 181 #define IOSF_PORT_CCU 0xa9 182 #define CHV_IOSF_PORT_GPIO_N 0x13 183 #define CHV_IOSF_PORT_GPIO_SE 0x48 184 #define CHV_IOSF_PORT_GPIO_E 0xa8 185 #define CHV_IOSF_PORT_GPIO_SW 0xb2 186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 188 189 /* DPIO registers */ 190 #define DPIO_DEVFN 0 191 192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 193 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 194 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 195 #define DPIO_SFR_BYPASS (1 << 1) 196 #define DPIO_CMNRST (1 << 0) 197 198 #define DPIO_PHY(pipe) ((pipe) >> 1) 199 200 /* 201 * Per pipe/PLL DPIO regs 202 */ 203 #define _VLV_PLL_DW3_CH0 0x800c 204 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 205 #define DPIO_POST_DIV_DAC 0 206 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 207 #define DPIO_POST_DIV_LVDS1 2 208 #define DPIO_POST_DIV_LVDS2 3 209 #define DPIO_K_SHIFT (24) /* 4 bits */ 210 #define DPIO_P1_SHIFT (21) /* 3 bits */ 211 #define DPIO_P2_SHIFT (16) /* 5 bits */ 212 #define DPIO_N_SHIFT (12) /* 4 bits */ 213 #define DPIO_ENABLE_CALIBRATION (1 << 11) 214 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 215 #define DPIO_M2DIV_MASK 0xff 216 #define _VLV_PLL_DW3_CH1 0x802c 217 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 218 219 #define _VLV_PLL_DW5_CH0 0x8014 220 #define DPIO_REFSEL_OVERRIDE 27 221 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 222 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 223 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 224 #define DPIO_PLL_REFCLK_SEL_MASK 3 225 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 226 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 227 #define _VLV_PLL_DW5_CH1 0x8034 228 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 229 230 #define _VLV_PLL_DW7_CH0 0x801c 231 #define _VLV_PLL_DW7_CH1 0x803c 232 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 233 234 #define _VLV_PLL_DW8_CH0 0x8040 235 #define _VLV_PLL_DW8_CH1 0x8060 236 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 237 238 #define VLV_PLL_DW9_BCAST 0xc044 239 #define _VLV_PLL_DW9_CH0 0x8044 240 #define _VLV_PLL_DW9_CH1 0x8064 241 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 242 243 #define _VLV_PLL_DW10_CH0 0x8048 244 #define _VLV_PLL_DW10_CH1 0x8068 245 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 246 247 #define _VLV_PLL_DW11_CH0 0x804c 248 #define _VLV_PLL_DW11_CH1 0x806c 249 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 250 251 /* Spec for ref block start counts at DW10 */ 252 #define VLV_REF_DW13 0x80ac 253 254 #define VLV_CMN_DW0 0x8100 255 256 /* 257 * Per DDI channel DPIO regs 258 */ 259 260 #define _VLV_PCS_DW0_CH0 0x8200 261 #define _VLV_PCS_DW0_CH1 0x8400 262 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 263 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 264 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 265 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 266 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 267 268 #define _VLV_PCS01_DW0_CH0 0x200 269 #define _VLV_PCS23_DW0_CH0 0x400 270 #define _VLV_PCS01_DW0_CH1 0x2600 271 #define _VLV_PCS23_DW0_CH1 0x2800 272 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 273 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 274 275 #define _VLV_PCS_DW1_CH0 0x8204 276 #define _VLV_PCS_DW1_CH1 0x8404 277 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 278 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 279 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 280 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 281 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 282 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 283 284 #define _VLV_PCS01_DW1_CH0 0x204 285 #define _VLV_PCS23_DW1_CH0 0x404 286 #define _VLV_PCS01_DW1_CH1 0x2604 287 #define _VLV_PCS23_DW1_CH1 0x2804 288 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 289 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 290 291 #define _VLV_PCS_DW8_CH0 0x8220 292 #define _VLV_PCS_DW8_CH1 0x8420 293 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 294 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 295 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 296 297 #define _VLV_PCS01_DW8_CH0 0x0220 298 #define _VLV_PCS23_DW8_CH0 0x0420 299 #define _VLV_PCS01_DW8_CH1 0x2620 300 #define _VLV_PCS23_DW8_CH1 0x2820 301 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 302 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 303 304 #define _VLV_PCS_DW9_CH0 0x8224 305 #define _VLV_PCS_DW9_CH1 0x8424 306 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 307 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 308 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 309 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 310 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 311 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 312 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 313 314 #define _VLV_PCS01_DW9_CH0 0x224 315 #define _VLV_PCS23_DW9_CH0 0x424 316 #define _VLV_PCS01_DW9_CH1 0x2624 317 #define _VLV_PCS23_DW9_CH1 0x2824 318 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 319 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 320 321 #define _CHV_PCS_DW10_CH0 0x8228 322 #define _CHV_PCS_DW10_CH1 0x8428 323 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 324 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 325 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 326 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 327 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 328 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 329 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 330 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 331 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 332 333 #define _VLV_PCS01_DW10_CH0 0x0228 334 #define _VLV_PCS23_DW10_CH0 0x0428 335 #define _VLV_PCS01_DW10_CH1 0x2628 336 #define _VLV_PCS23_DW10_CH1 0x2828 337 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 338 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 339 340 #define _VLV_PCS_DW11_CH0 0x822c 341 #define _VLV_PCS_DW11_CH1 0x842c 342 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 343 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 344 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 345 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 346 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 347 348 #define _VLV_PCS01_DW11_CH0 0x022c 349 #define _VLV_PCS23_DW11_CH0 0x042c 350 #define _VLV_PCS01_DW11_CH1 0x262c 351 #define _VLV_PCS23_DW11_CH1 0x282c 352 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 353 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 354 355 #define _VLV_PCS01_DW12_CH0 0x0230 356 #define _VLV_PCS23_DW12_CH0 0x0430 357 #define _VLV_PCS01_DW12_CH1 0x2630 358 #define _VLV_PCS23_DW12_CH1 0x2830 359 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 360 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 361 362 #define _VLV_PCS_DW12_CH0 0x8230 363 #define _VLV_PCS_DW12_CH1 0x8430 364 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 365 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 366 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 367 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 368 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 369 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 370 371 #define _VLV_PCS_DW14_CH0 0x8238 372 #define _VLV_PCS_DW14_CH1 0x8438 373 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 374 375 #define _VLV_PCS_DW23_CH0 0x825c 376 #define _VLV_PCS_DW23_CH1 0x845c 377 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 378 379 #define _VLV_TX_DW2_CH0 0x8288 380 #define _VLV_TX_DW2_CH1 0x8488 381 #define DPIO_SWING_MARGIN000_SHIFT 16 382 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 383 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 384 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 385 386 #define _VLV_TX_DW3_CH0 0x828c 387 #define _VLV_TX_DW3_CH1 0x848c 388 /* The following bit for CHV phy */ 389 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 390 #define DPIO_SWING_MARGIN101_SHIFT 16 391 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 392 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 393 394 #define _VLV_TX_DW4_CH0 0x8290 395 #define _VLV_TX_DW4_CH1 0x8490 396 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 397 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 398 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 399 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 400 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 401 402 #define _VLV_TX3_DW4_CH0 0x690 403 #define _VLV_TX3_DW4_CH1 0x2a90 404 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 405 406 #define _VLV_TX_DW5_CH0 0x8294 407 #define _VLV_TX_DW5_CH1 0x8494 408 #define DPIO_TX_OCALINIT_EN (1 << 31) 409 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 410 411 #define _VLV_TX_DW11_CH0 0x82ac 412 #define _VLV_TX_DW11_CH1 0x84ac 413 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 414 415 #define _VLV_TX_DW14_CH0 0x82b8 416 #define _VLV_TX_DW14_CH1 0x84b8 417 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 418 419 /* CHV dpPhy registers */ 420 #define _CHV_PLL_DW0_CH0 0x8000 421 #define _CHV_PLL_DW0_CH1 0x8180 422 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 423 424 #define _CHV_PLL_DW1_CH0 0x8004 425 #define _CHV_PLL_DW1_CH1 0x8184 426 #define DPIO_CHV_N_DIV_SHIFT 8 427 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 428 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 429 430 #define _CHV_PLL_DW2_CH0 0x8008 431 #define _CHV_PLL_DW2_CH1 0x8188 432 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 433 434 #define _CHV_PLL_DW3_CH0 0x800c 435 #define _CHV_PLL_DW3_CH1 0x818c 436 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 437 #define DPIO_CHV_FIRST_MOD (0 << 8) 438 #define DPIO_CHV_SECOND_MOD (1 << 8) 439 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 440 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 441 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 442 443 #define _CHV_PLL_DW6_CH0 0x8018 444 #define _CHV_PLL_DW6_CH1 0x8198 445 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 446 #define DPIO_CHV_INT_COEFF_SHIFT 8 447 #define DPIO_CHV_PROP_COEFF_SHIFT 0 448 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 449 450 #define _CHV_PLL_DW8_CH0 0x8020 451 #define _CHV_PLL_DW8_CH1 0x81A0 452 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 453 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 454 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 455 456 #define _CHV_PLL_DW9_CH0 0x8024 457 #define _CHV_PLL_DW9_CH1 0x81A4 458 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 459 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 460 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 461 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 462 463 #define _CHV_CMN_DW0_CH0 0x8100 464 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 465 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 466 #define DPIO_ALLDL_POWERDOWN (1 << 1) 467 #define DPIO_ANYDL_POWERDOWN (1 << 0) 468 469 #define _CHV_CMN_DW5_CH0 0x8114 470 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 471 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 472 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 473 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 474 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 475 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 476 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 477 #define CHV_BUFLEFTENA1_MASK (3 << 22) 478 479 #define _CHV_CMN_DW13_CH0 0x8134 480 #define _CHV_CMN_DW0_CH1 0x8080 481 #define DPIO_CHV_S1_DIV_SHIFT 21 482 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 483 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 484 #define DPIO_CHV_K_DIV_SHIFT 4 485 #define DPIO_PLL_FREQLOCK (1 << 1) 486 #define DPIO_PLL_LOCK (1 << 0) 487 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 488 489 #define _CHV_CMN_DW14_CH0 0x8138 490 #define _CHV_CMN_DW1_CH1 0x8084 491 #define DPIO_AFC_RECAL (1 << 14) 492 #define DPIO_DCLKP_EN (1 << 13) 493 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 494 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 495 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 496 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 497 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 498 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 499 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 500 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 501 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 502 503 #define _CHV_CMN_DW19_CH0 0x814c 504 #define _CHV_CMN_DW6_CH1 0x8098 505 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 506 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 507 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 508 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 509 510 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 511 512 #define CHV_CMN_DW28 0x8170 513 #define DPIO_CL1POWERDOWNEN (1 << 23) 514 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 515 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 516 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 517 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 518 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 519 520 #define CHV_CMN_DW30 0x8178 521 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 522 #define DPIO_LRC_BYPASS (1 << 3) 523 524 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 525 (lane) * 0x200 + (offset)) 526 527 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 528 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 529 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 530 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 531 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 532 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 533 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 534 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 535 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 536 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 537 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 538 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 539 #define DPIO_FRC_LATENCY_SHFIT 8 540 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 541 #define DPIO_UPAR_SHIFT 30 542 543 /* BXT PHY registers */ 544 #define _BXT_PHY0_BASE 0x6C000 545 #define _BXT_PHY1_BASE 0x162000 546 #define _BXT_PHY2_BASE 0x163000 547 #define BXT_PHY_BASE(phy) \ 548 _PICK_EVEN_2RANGES(phy, 1, \ 549 _BXT_PHY0_BASE, _BXT_PHY0_BASE, \ 550 _BXT_PHY1_BASE, _BXT_PHY2_BASE) 551 552 #define _BXT_PHY(phy, reg) \ 553 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 554 555 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 556 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 557 (reg_ch1) - _BXT_PHY0_BASE)) 558 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 559 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 560 561 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 562 #define MIPIO_RST_CTRL (1 << 2) 563 564 #define _BXT_PHY_CTL_DDI_A 0x64C00 565 #define _BXT_PHY_CTL_DDI_B 0x64C10 566 #define _BXT_PHY_CTL_DDI_C 0x64C20 567 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 568 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 569 #define BXT_PHY_LANE_ENABLED (1 << 8) 570 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 571 _BXT_PHY_CTL_DDI_B) 572 573 #define _PHY_CTL_FAMILY_DDI 0x64C90 574 #define _PHY_CTL_FAMILY_EDP 0x64C80 575 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 576 #define COMMON_RESET_DIS (1 << 31) 577 #define BXT_PHY_CTL_FAMILY(phy) \ 578 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ 579 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ 580 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) 581 582 /* BXT PHY PLL registers */ 583 #define _PORT_PLL_A 0x46074 584 #define _PORT_PLL_B 0x46078 585 #define _PORT_PLL_C 0x4607c 586 #define PORT_PLL_ENABLE REG_BIT(31) 587 #define PORT_PLL_LOCK REG_BIT(30) 588 #define PORT_PLL_REF_SEL REG_BIT(27) 589 #define PORT_PLL_POWER_ENABLE REG_BIT(26) 590 #define PORT_PLL_POWER_STATE REG_BIT(25) 591 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 592 593 #define _PORT_PLL_EBB_0_A 0x162034 594 #define _PORT_PLL_EBB_0_B 0x6C034 595 #define _PORT_PLL_EBB_0_C 0x6C340 596 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) 597 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) 598 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) 599 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) 600 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 601 _PORT_PLL_EBB_0_B, \ 602 _PORT_PLL_EBB_0_C) 603 604 #define _PORT_PLL_EBB_4_A 0x162038 605 #define _PORT_PLL_EBB_4_B 0x6C038 606 #define _PORT_PLL_EBB_4_C 0x6C344 607 #define PORT_PLL_RECALIBRATE REG_BIT(14) 608 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) 609 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 610 _PORT_PLL_EBB_4_B, \ 611 _PORT_PLL_EBB_4_C) 612 613 #define _PORT_PLL_0_A 0x162100 614 #define _PORT_PLL_0_B 0x6C100 615 #define _PORT_PLL_0_C 0x6C380 616 /* PORT_PLL_0_A */ 617 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) 618 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) 619 /* PORT_PLL_1_A */ 620 #define PORT_PLL_N_MASK REG_GENMASK(11, 8) 621 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) 622 /* PORT_PLL_2_A */ 623 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) 624 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) 625 /* PORT_PLL_3_A */ 626 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) 627 /* PORT_PLL_6_A */ 628 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) 629 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) 630 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) 631 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) 632 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) 633 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) 634 /* PORT_PLL_8_A */ 635 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) 636 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) 637 /* PORT_PLL_9_A */ 638 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) 639 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) 640 /* PORT_PLL_10_A */ 641 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) 642 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) 643 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) 644 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 645 _PORT_PLL_0_B, \ 646 _PORT_PLL_0_C) 647 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 648 (idx) * 4) 649 650 /* BXT PHY common lane registers */ 651 #define _PORT_CL1CM_DW0_A 0x162000 652 #define _PORT_CL1CM_DW0_BC 0x6C000 653 #define PHY_POWER_GOOD (1 << 16) 654 #define PHY_RESERVED (1 << 7) 655 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 656 657 #define _PORT_CL1CM_DW9_A 0x162024 658 #define _PORT_CL1CM_DW9_BC 0x6C024 659 #define IREF0RC_OFFSET_SHIFT 8 660 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 661 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 662 663 #define _PORT_CL1CM_DW10_A 0x162028 664 #define _PORT_CL1CM_DW10_BC 0x6C028 665 #define IREF1RC_OFFSET_SHIFT 8 666 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 667 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 668 669 #define _PORT_CL1CM_DW28_A 0x162070 670 #define _PORT_CL1CM_DW28_BC 0x6C070 671 #define OCL1_POWER_DOWN_EN (1 << 23) 672 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 673 #define SUS_CLK_CONFIG 0x3 674 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 675 676 #define _PORT_CL1CM_DW30_A 0x162078 677 #define _PORT_CL1CM_DW30_BC 0x6C078 678 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 679 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 680 681 /* The spec defines this only for BXT PHY0, but lets assume that this 682 * would exist for PHY1 too if it had a second channel. 683 */ 684 #define _PORT_CL2CM_DW6_A 0x162358 685 #define _PORT_CL2CM_DW6_BC 0x6C358 686 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 687 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 688 689 /* BXT PHY Ref registers */ 690 #define _PORT_REF_DW3_A 0x16218C 691 #define _PORT_REF_DW3_BC 0x6C18C 692 #define GRC_DONE (1 << 22) 693 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 694 695 #define _PORT_REF_DW6_A 0x162198 696 #define _PORT_REF_DW6_BC 0x6C198 697 #define GRC_CODE_SHIFT 24 698 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 699 #define GRC_CODE_FAST_SHIFT 16 700 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 701 #define GRC_CODE_SLOW_SHIFT 8 702 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 703 #define GRC_CODE_NOM_MASK 0xFF 704 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 705 706 #define _PORT_REF_DW8_A 0x1621A0 707 #define _PORT_REF_DW8_BC 0x6C1A0 708 #define GRC_DIS (1 << 15) 709 #define GRC_RDY_OVRD (1 << 1) 710 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 711 712 /* BXT PHY PCS registers */ 713 #define _PORT_PCS_DW10_LN01_A 0x162428 714 #define _PORT_PCS_DW10_LN01_B 0x6C428 715 #define _PORT_PCS_DW10_LN01_C 0x6C828 716 #define _PORT_PCS_DW10_GRP_A 0x162C28 717 #define _PORT_PCS_DW10_GRP_B 0x6CC28 718 #define _PORT_PCS_DW10_GRP_C 0x6CE28 719 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 720 _PORT_PCS_DW10_LN01_B, \ 721 _PORT_PCS_DW10_LN01_C) 722 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 723 _PORT_PCS_DW10_GRP_B, \ 724 _PORT_PCS_DW10_GRP_C) 725 726 #define TX2_SWING_CALC_INIT (1 << 31) 727 #define TX1_SWING_CALC_INIT (1 << 30) 728 729 #define _PORT_PCS_DW12_LN01_A 0x162430 730 #define _PORT_PCS_DW12_LN01_B 0x6C430 731 #define _PORT_PCS_DW12_LN01_C 0x6C830 732 #define _PORT_PCS_DW12_LN23_A 0x162630 733 #define _PORT_PCS_DW12_LN23_B 0x6C630 734 #define _PORT_PCS_DW12_LN23_C 0x6CA30 735 #define _PORT_PCS_DW12_GRP_A 0x162c30 736 #define _PORT_PCS_DW12_GRP_B 0x6CC30 737 #define _PORT_PCS_DW12_GRP_C 0x6CE30 738 #define LANESTAGGER_STRAP_OVRD (1 << 6) 739 #define LANE_STAGGER_MASK 0x1F 740 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 741 _PORT_PCS_DW12_LN01_B, \ 742 _PORT_PCS_DW12_LN01_C) 743 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 744 _PORT_PCS_DW12_LN23_B, \ 745 _PORT_PCS_DW12_LN23_C) 746 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 747 _PORT_PCS_DW12_GRP_B, \ 748 _PORT_PCS_DW12_GRP_C) 749 750 /* BXT PHY TX registers */ 751 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 752 ((lane) & 1) * 0x80) 753 754 #define _PORT_TX_DW2_LN0_A 0x162508 755 #define _PORT_TX_DW2_LN0_B 0x6C508 756 #define _PORT_TX_DW2_LN0_C 0x6C908 757 #define _PORT_TX_DW2_GRP_A 0x162D08 758 #define _PORT_TX_DW2_GRP_B 0x6CD08 759 #define _PORT_TX_DW2_GRP_C 0x6CF08 760 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 761 _PORT_TX_DW2_LN0_B, \ 762 _PORT_TX_DW2_LN0_C) 763 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 764 _PORT_TX_DW2_GRP_B, \ 765 _PORT_TX_DW2_GRP_C) 766 #define MARGIN_000_SHIFT 16 767 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 768 #define UNIQ_TRANS_SCALE_SHIFT 8 769 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 770 771 #define _PORT_TX_DW3_LN0_A 0x16250C 772 #define _PORT_TX_DW3_LN0_B 0x6C50C 773 #define _PORT_TX_DW3_LN0_C 0x6C90C 774 #define _PORT_TX_DW3_GRP_A 0x162D0C 775 #define _PORT_TX_DW3_GRP_B 0x6CD0C 776 #define _PORT_TX_DW3_GRP_C 0x6CF0C 777 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 778 _PORT_TX_DW3_LN0_B, \ 779 _PORT_TX_DW3_LN0_C) 780 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 781 _PORT_TX_DW3_GRP_B, \ 782 _PORT_TX_DW3_GRP_C) 783 #define SCALE_DCOMP_METHOD (1 << 26) 784 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 785 786 #define _PORT_TX_DW4_LN0_A 0x162510 787 #define _PORT_TX_DW4_LN0_B 0x6C510 788 #define _PORT_TX_DW4_LN0_C 0x6C910 789 #define _PORT_TX_DW4_GRP_A 0x162D10 790 #define _PORT_TX_DW4_GRP_B 0x6CD10 791 #define _PORT_TX_DW4_GRP_C 0x6CF10 792 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 793 _PORT_TX_DW4_LN0_B, \ 794 _PORT_TX_DW4_LN0_C) 795 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 796 _PORT_TX_DW4_GRP_B, \ 797 _PORT_TX_DW4_GRP_C) 798 #define DEEMPH_SHIFT 24 799 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 800 801 #define _PORT_TX_DW5_LN0_A 0x162514 802 #define _PORT_TX_DW5_LN0_B 0x6C514 803 #define _PORT_TX_DW5_LN0_C 0x6C914 804 #define _PORT_TX_DW5_GRP_A 0x162D14 805 #define _PORT_TX_DW5_GRP_B 0x6CD14 806 #define _PORT_TX_DW5_GRP_C 0x6CF14 807 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 808 _PORT_TX_DW5_LN0_B, \ 809 _PORT_TX_DW5_LN0_C) 810 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 811 _PORT_TX_DW5_GRP_B, \ 812 _PORT_TX_DW5_GRP_C) 813 #define DCC_DELAY_RANGE_1 (1 << 9) 814 #define DCC_DELAY_RANGE_2 (1 << 8) 815 816 #define _PORT_TX_DW14_LN0_A 0x162538 817 #define _PORT_TX_DW14_LN0_B 0x6C538 818 #define _PORT_TX_DW14_LN0_C 0x6C938 819 #define LATENCY_OPTIM_SHIFT 30 820 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 821 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 822 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 823 _PORT_TX_DW14_LN0_C) + \ 824 _BXT_LANE_OFFSET(lane)) 825 826 /* UAIMI scratch pad register 1 */ 827 #define UAIMI_SPR1 _MMIO(0x4F074) 828 /* SKL VccIO mask */ 829 #define SKL_VCCIO_MASK 0x1 830 /* SKL balance leg register */ 831 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 832 /* I_boost values */ 833 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 834 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 835 /* Balance leg disable bits */ 836 #define BALANCE_LEG_DISABLE_SHIFT 23 837 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 838 839 /* 840 * Fence registers 841 * [0-7] @ 0x2000 gen2,gen3 842 * [8-15] @ 0x3000 945,g33,pnv 843 * 844 * [0-15] @ 0x3000 gen4,gen5 845 * 846 * [0-15] @ 0x100000 gen6,vlv,chv 847 * [0-31] @ 0x100000 gen7+ 848 */ 849 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 850 #define I830_FENCE_START_MASK 0x07f80000 851 #define I830_FENCE_TILING_Y_SHIFT 12 852 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 853 #define I830_FENCE_PITCH_SHIFT 4 854 #define I830_FENCE_REG_VALID (1 << 0) 855 #define I915_FENCE_MAX_PITCH_VAL 4 856 #define I830_FENCE_MAX_PITCH_VAL 6 857 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 858 859 #define I915_FENCE_START_MASK 0x0ff00000 860 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 861 862 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 863 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 864 #define I965_FENCE_PITCH_SHIFT 2 865 #define I965_FENCE_TILING_Y_SHIFT 1 866 #define I965_FENCE_REG_VALID (1 << 0) 867 #define I965_FENCE_MAX_PITCH_VAL 0x0400 868 869 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 870 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 871 #define GEN6_FENCE_PITCH_SHIFT 32 872 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 873 874 875 /* control register for cpu gtt access */ 876 #define TILECTL _MMIO(0x101000) 877 #define TILECTL_SWZCTL (1 << 0) 878 #define TILECTL_TLBPF (1 << 1) 879 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 880 #define TILECTL_BACKSNOOP_DIS (1 << 3) 881 882 /* 883 * Instruction and interrupt control regs 884 */ 885 #define PGTBL_CTL _MMIO(0x02020) 886 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 887 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 888 #define PGTBL_ER _MMIO(0x02024) 889 #define PRB0_BASE (0x2030 - 0x30) 890 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 891 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 892 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 893 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 894 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 895 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 896 #define RENDER_RING_BASE 0x02000 897 #define BSD_RING_BASE 0x04000 898 #define GEN6_BSD_RING_BASE 0x12000 899 #define GEN8_BSD2_RING_BASE 0x1c000 900 #define GEN11_BSD_RING_BASE 0x1c0000 901 #define GEN11_BSD2_RING_BASE 0x1c4000 902 #define GEN11_BSD3_RING_BASE 0x1d0000 903 #define GEN11_BSD4_RING_BASE 0x1d4000 904 #define XEHP_BSD5_RING_BASE 0x1e0000 905 #define XEHP_BSD6_RING_BASE 0x1e4000 906 #define XEHP_BSD7_RING_BASE 0x1f0000 907 #define XEHP_BSD8_RING_BASE 0x1f4000 908 #define VEBOX_RING_BASE 0x1a000 909 #define GEN11_VEBOX_RING_BASE 0x1c8000 910 #define GEN11_VEBOX2_RING_BASE 0x1d8000 911 #define XEHP_VEBOX3_RING_BASE 0x1e8000 912 #define XEHP_VEBOX4_RING_BASE 0x1f8000 913 #define MTL_GSC_RING_BASE 0x11a000 914 #define GEN12_COMPUTE0_RING_BASE 0x1a000 915 #define GEN12_COMPUTE1_RING_BASE 0x1c000 916 #define GEN12_COMPUTE2_RING_BASE 0x1e000 917 #define GEN12_COMPUTE3_RING_BASE 0x26000 918 #define BLT_RING_BASE 0x22000 919 #define XEHPC_BCS1_RING_BASE 0x3e0000 920 #define XEHPC_BCS2_RING_BASE 0x3e2000 921 #define XEHPC_BCS3_RING_BASE 0x3e4000 922 #define XEHPC_BCS4_RING_BASE 0x3e6000 923 #define XEHPC_BCS5_RING_BASE 0x3e8000 924 #define XEHPC_BCS6_RING_BASE 0x3ea000 925 #define XEHPC_BCS7_RING_BASE 0x3ec000 926 #define XEHPC_BCS8_RING_BASE 0x3ee000 927 #define DG1_GSC_HECI1_BASE 0x00258000 928 #define DG1_GSC_HECI2_BASE 0x00259000 929 #define DG2_GSC_HECI1_BASE 0x00373000 930 #define DG2_GSC_HECI2_BASE 0x00374000 931 #define MTL_GSC_HECI1_BASE 0x00116000 932 #define MTL_GSC_HECI2_BASE 0x00117000 933 934 #define HECI_H_CSR(base) _MMIO((base) + 0x4) 935 #define HECI_H_CSR_IE REG_BIT(0) 936 #define HECI_H_CSR_IS REG_BIT(1) 937 #define HECI_H_CSR_IG REG_BIT(2) 938 #define HECI_H_CSR_RDY REG_BIT(3) 939 #define HECI_H_CSR_RST REG_BIT(4) 940 941 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c) 942 #define HECI_H_GS1_ER_PREP REG_BIT(0) 943 944 /* 945 * The FWSTS register values are FW defined and can be different between 946 * HECI1 and HECI2 947 */ 948 #define HECI_FWSTS1 0xc40 949 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0) 950 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0 951 #define HECI1_FWSTS1_PROXY_STATE_NORMAL 5 952 #define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9) 953 #define HECI_FWSTS2 0xc48 954 #define HECI_FWSTS3 0xc60 955 #define HECI_FWSTS4 0xc64 956 #define HECI_FWSTS5 0xc68 957 #define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19) 958 #define HECI_FWSTS6 0xc6c 959 960 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ 961 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \ 962 HECI_FWSTS1, \ 963 HECI_FWSTS2, \ 964 HECI_FWSTS3, \ 965 HECI_FWSTS4, \ 966 HECI_FWSTS5, \ 967 HECI_FWSTS6)) 968 969 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 970 #define GTT_CACHE_EN_ALL 0xF0007FFF 971 #define GEN7_WR_WATERMARK _MMIO(0x4028) 972 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 973 #define ARB_MODE _MMIO(0x4030) 974 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 975 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 976 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 977 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 978 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 979 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 980 #define GEN7_LRA_LIMITS_REG_NUM 13 981 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 982 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 983 984 #define GEN7_ERR_INT _MMIO(0x44040) 985 #define ERR_INT_POISON (1 << 31) 986 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 987 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 988 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 989 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 990 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 991 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 992 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 993 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 994 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 995 996 #define FPGA_DBG _MMIO(0x42300) 997 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 998 999 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1000 #define CLAIM_ER_CLR REG_BIT(31) 1001 #define CLAIM_ER_OVERFLOW REG_BIT(16) 1002 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 1003 1004 #define DERRMR _MMIO(0x44050) 1005 /* Note that HBLANK events are reserved on bdw+ */ 1006 #define DERRMR_PIPEA_SCANLINE (1 << 0) 1007 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 1008 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 1009 #define DERRMR_PIPEA_VBLANK (1 << 3) 1010 #define DERRMR_PIPEA_HBLANK (1 << 5) 1011 #define DERRMR_PIPEB_SCANLINE (1 << 8) 1012 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 1013 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 1014 #define DERRMR_PIPEB_VBLANK (1 << 11) 1015 #define DERRMR_PIPEB_HBLANK (1 << 13) 1016 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1017 #define DERRMR_PIPEC_SCANLINE (1 << 14) 1018 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 1019 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 1020 #define DERRMR_PIPEC_VBLANK (1 << 21) 1021 #define DERRMR_PIPEC_HBLANK (1 << 22) 1022 1023 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1024 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1025 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1026 #define SCPD_FBC_IGNORE_3D (1 << 6) 1027 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 1028 #define GEN2_IER _MMIO(0x20a0) 1029 #define GEN2_IIR _MMIO(0x20a4) 1030 #define GEN2_IMR _MMIO(0x20a8) 1031 #define GEN2_ISR _MMIO(0x20ac) 1032 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1033 #define GINT_DIS (1 << 22) 1034 #define GCFG_DIS (1 << 8) 1035 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1036 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1037 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1038 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1039 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1040 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1041 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1042 #define VLV_PCBR_ADDR_SHIFT 12 1043 1044 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1045 #define EIR _MMIO(0x20b0) 1046 #define EMR _MMIO(0x20b4) 1047 #define ESR _MMIO(0x20b8) 1048 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1049 #define GM45_ERROR_MEM_PRIV (1 << 4) 1050 #define I915_ERROR_PAGE_TABLE (1 << 4) 1051 #define GM45_ERROR_CP_PRIV (1 << 3) 1052 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1053 #define I915_ERROR_INSTRUCTION (1 << 0) 1054 #define INSTPM _MMIO(0x20c0) 1055 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1056 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1057 will not assert AGPBUSY# and will only 1058 be delivered when out of C3. */ 1059 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1060 #define INSTPM_TLB_INVALIDATE (1 << 9) 1061 #define INSTPM_SYNC_FLUSH (1 << 5) 1062 #define MEM_MODE _MMIO(0x20cc) 1063 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1064 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1065 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1066 #define FW_BLC _MMIO(0x20d8) 1067 #define FW_BLC2 _MMIO(0x20dc) 1068 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1069 #define FW_BLC_SELF_EN_MASK (1 << 31) 1070 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1071 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1072 #define MM_BURST_LENGTH 0x00700000 1073 #define MM_FIFO_WATERMARK 0x0001F000 1074 #define LM_BURST_LENGTH 0x00000700 1075 #define LM_FIFO_WATERMARK 0x0000001F 1076 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1077 1078 #define _MBUS_ABOX0_CTL 0x45038 1079 #define _MBUS_ABOX1_CTL 0x45048 1080 #define _MBUS_ABOX2_CTL 0x4504C 1081 #define MBUS_ABOX_CTL(x) \ 1082 _MMIO(_PICK_EVEN_2RANGES(x, 2, \ 1083 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ 1084 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) 1085 1086 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1087 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1088 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1089 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1090 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1091 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1092 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1093 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1094 1095 /* Make render/texture TLB fetches lower priorty than associated data 1096 * fetches. This is not turned on by default 1097 */ 1098 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1099 1100 /* Isoch request wait on GTT enable (Display A/B/C streams). 1101 * Make isoch requests stall on the TLB update. May cause 1102 * display underruns (test mode only) 1103 */ 1104 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1105 1106 /* Block grant count for isoch requests when block count is 1107 * set to a finite value. 1108 */ 1109 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1110 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1111 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1112 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1113 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1114 1115 /* Enable render writes to complete in C2/C3/C4 power states. 1116 * If this isn't enabled, render writes are prevented in low 1117 * power states. That seems bad to me. 1118 */ 1119 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1120 1121 /* This acknowledges an async flip immediately instead 1122 * of waiting for 2TLB fetches. 1123 */ 1124 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1125 1126 /* Enables non-sequential data reads through arbiter 1127 */ 1128 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1129 1130 /* Disable FSB snooping of cacheable write cycles from binner/render 1131 * command stream 1132 */ 1133 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1134 1135 /* Arbiter time slice for non-isoch streams */ 1136 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1137 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1138 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1139 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1140 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1141 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1142 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1143 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1144 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1145 1146 /* Low priority grace period page size */ 1147 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1148 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1149 1150 /* Disable display A/B trickle feed */ 1151 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1152 1153 /* Set display plane priority */ 1154 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1155 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1156 1157 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1158 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1159 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1160 1161 /* On modern GEN architectures interrupt control consists of two sets 1162 * of registers. The first set pertains to the ring generating the 1163 * interrupt. The second control is for the functional block generating the 1164 * interrupt. These are PM, GT, DE, etc. 1165 * 1166 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1167 * GT interrupt bits, so we don't need to duplicate the defines. 1168 * 1169 * These defines should cover us well from SNB->HSW with minor exceptions 1170 * it can also work on ILK. 1171 */ 1172 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1173 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1174 #define GT_BLT_USER_INTERRUPT (1 << 22) 1175 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1176 #define GT_BSD_USER_INTERRUPT (1 << 12) 1177 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1178 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1179 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1180 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1181 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1182 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1183 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1184 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1185 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1186 1187 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1188 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1189 1190 #define GT_PARITY_ERROR(dev_priv) \ 1191 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1192 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1193 1194 /* These are all the "old" interrupts */ 1195 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1196 1197 #define I915_PM_INTERRUPT (1 << 31) 1198 #define I915_ISP_INTERRUPT (1 << 22) 1199 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1200 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1201 #define I915_MIPIC_INTERRUPT (1 << 19) 1202 #define I915_MIPIA_INTERRUPT (1 << 18) 1203 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1204 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1205 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1206 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1207 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1208 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1209 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1210 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1211 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1212 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1213 #define I915_MISC_INTERRUPT (1 << 11) 1214 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1215 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1216 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1217 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1218 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1219 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1220 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1221 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1222 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1223 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1224 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1225 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1226 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1227 #define I915_DEBUG_INTERRUPT (1 << 2) 1228 #define I915_WINVALID_INTERRUPT (1 << 1) 1229 #define I915_USER_INTERRUPT (1 << 1) 1230 #define I915_ASLE_INTERRUPT (1 << 0) 1231 #define I915_BSD_USER_INTERRUPT (1 << 25) 1232 1233 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1234 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1235 1236 /* DisplayPort Audio w/ LPE */ 1237 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1238 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1239 1240 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1241 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1242 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1243 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1244 _VLV_AUD_PORT_EN_B_DBG, \ 1245 _VLV_AUD_PORT_EN_C_DBG, \ 1246 _VLV_AUD_PORT_EN_D_DBG) 1247 #define VLV_AMP_MUTE (1 << 1) 1248 1249 #define GEN6_BSD_RNCID _MMIO(0x12198) 1250 1251 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1252 #define GEN7_FF_SCHED_MASK 0x0077070 1253 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1254 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1255 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1256 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1257 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1258 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1259 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1260 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1261 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1262 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1263 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1264 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1265 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1266 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1267 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1268 1269 /* 1270 * Framebuffer compression (915+ only) 1271 */ 1272 1273 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1274 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1275 #define FBC_CONTROL _MMIO(0x3208) 1276 #define FBC_CTL_EN REG_BIT(31) 1277 #define FBC_CTL_PERIODIC REG_BIT(30) 1278 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1279 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1280 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1281 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1282 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1283 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1284 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1285 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1286 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1287 #define FBC_COMMAND _MMIO(0x320c) 1288 #define FBC_CMD_COMPRESS REG_BIT(0) 1289 #define FBC_STATUS _MMIO(0x3210) 1290 #define FBC_STAT_COMPRESSING REG_BIT(31) 1291 #define FBC_STAT_COMPRESSED REG_BIT(30) 1292 #define FBC_STAT_MODIFIED REG_BIT(29) 1293 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1294 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1295 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1296 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1297 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1298 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1299 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1300 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1301 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1302 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1303 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1304 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1305 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1306 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1307 #define FBC_MOD_NUM_VALID REG_BIT(0) 1308 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1309 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1310 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1311 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1312 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1313 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1314 1315 #define FBC_LL_SIZE (1536) 1316 1317 /* Framebuffer compression for GM45+ */ 1318 #define DPFC_CB_BASE _MMIO(0x3200) 1319 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1320 #define DPFC_CONTROL _MMIO(0x3208) 1321 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1322 #define DPFC_CTL_EN REG_BIT(31) 1323 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1324 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1325 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1326 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1327 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1328 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1329 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1330 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1331 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1332 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1333 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1334 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1335 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1336 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1337 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1338 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1339 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1340 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1341 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1342 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1343 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1344 #define DPFC_STATUS _MMIO(0x3210) 1345 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1346 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1347 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1348 #define DPFC_STATUS2 _MMIO(0x3214) 1349 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1350 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1351 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1352 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1353 #define DPFC_CHICKEN _MMIO(0x3224) 1354 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1355 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1356 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1357 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1358 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1359 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1360 1361 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1362 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1363 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1364 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1365 1366 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1367 #define ILK_FBC_RT_VALID REG_BIT(0) 1368 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1369 1370 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1371 #define ILK_FBCQ_DIS (1 << 22) 1372 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1373 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1374 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1375 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1376 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1377 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1378 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1379 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1380 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1381 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1382 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1383 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1384 1385 1386 /* 1387 * Framebuffer compression for Sandybridge 1388 * 1389 * The following two registers are of type GTTMMADR 1390 */ 1391 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1392 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1393 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1394 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1395 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1396 1397 /* Framebuffer compression for Ivybridge */ 1398 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1399 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1400 1401 #define IPS_CTL _MMIO(0x43408) 1402 #define IPS_ENABLE REG_BIT(31) 1403 #define IPS_FALSE_COLOR REG_BIT(4) 1404 1405 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1406 #define FBC_REND_NUKE REG_BIT(2) 1407 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1408 1409 /* 1410 * Clock control & power management 1411 */ 1412 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1413 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1414 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1415 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1416 1417 #define VGA0 _MMIO(0x6000) 1418 #define VGA1 _MMIO(0x6004) 1419 #define VGA_PD _MMIO(0x6010) 1420 #define VGA0_PD_P2_DIV_4 (1 << 7) 1421 #define VGA0_PD_P1_DIV_2 (1 << 5) 1422 #define VGA0_PD_P1_SHIFT 0 1423 #define VGA0_PD_P1_MASK (0x1f << 0) 1424 #define VGA1_PD_P2_DIV_4 (1 << 15) 1425 #define VGA1_PD_P1_DIV_2 (1 << 13) 1426 #define VGA1_PD_P1_SHIFT 8 1427 #define VGA1_PD_P1_MASK (0x1f << 8) 1428 #define DPLL_VCO_ENABLE (1 << 31) 1429 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1430 #define DPLL_DVO_2X_MODE (1 << 30) 1431 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1432 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1433 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1434 #define DPLL_VGA_MODE_DIS (1 << 28) 1435 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1436 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1437 #define DPLL_MODE_MASK (3 << 26) 1438 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1439 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1440 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1441 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1442 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1443 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1444 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1445 #define DPLL_LOCK_VLV (1 << 15) 1446 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1447 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1448 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1449 #define DPLL_PORTC_READY_MASK (0xf << 4) 1450 #define DPLL_PORTB_READY_MASK (0xf) 1451 1452 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1453 1454 /* Additional CHV pll/phy registers */ 1455 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1456 #define DPLL_PORTD_READY_MASK (0xf) 1457 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1458 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1459 #define PHY_LDO_DELAY_0NS 0x0 1460 #define PHY_LDO_DELAY_200NS 0x1 1461 #define PHY_LDO_DELAY_600NS 0x2 1462 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1463 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1464 #define PHY_CH_SU_PSR 0x1 1465 #define PHY_CH_DEEP_PSR 0x7 1466 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1467 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1468 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1469 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1470 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1471 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1472 1473 /* 1474 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1475 * this field (only one bit may be set). 1476 */ 1477 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1478 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1479 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1480 /* i830, required in DVO non-gang */ 1481 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1482 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1483 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1484 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1485 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1486 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1487 #define PLL_REF_INPUT_MASK (3 << 13) 1488 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1489 /* Ironlake */ 1490 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1491 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1492 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1493 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1494 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1495 1496 /* 1497 * Parallel to Serial Load Pulse phase selection. 1498 * Selects the phase for the 10X DPLL clock for the PCIe 1499 * digital display port. The range is 4 to 13; 10 or more 1500 * is just a flip delay. The default is 6 1501 */ 1502 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1503 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1504 /* 1505 * SDVO multiplier for 945G/GM. Not used on 965. 1506 */ 1507 #define SDVO_MULTIPLIER_MASK 0x000000ff 1508 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1509 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1510 1511 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1512 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1513 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1514 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1515 1516 /* 1517 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1518 * 1519 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1520 */ 1521 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1522 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1523 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1524 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1525 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1526 /* 1527 * SDVO/UDI pixel multiplier. 1528 * 1529 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1530 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1531 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1532 * dummy bytes in the datastream at an increased clock rate, with both sides of 1533 * the link knowing how many bytes are fill. 1534 * 1535 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1536 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1537 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1538 * through an SDVO command. 1539 * 1540 * This register field has values of multiplication factor minus 1, with 1541 * a maximum multiplier of 5 for SDVO. 1542 */ 1543 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1544 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1545 /* 1546 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1547 * This best be set to the default value (3) or the CRT won't work. No, 1548 * I don't entirely understand what this does... 1549 */ 1550 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1551 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1552 1553 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1554 1555 #define _FPA0 0x6040 1556 #define _FPA1 0x6044 1557 #define _FPB0 0x6048 1558 #define _FPB1 0x604c 1559 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1560 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1561 #define FP_N_DIV_MASK 0x003f0000 1562 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1563 #define FP_N_DIV_SHIFT 16 1564 #define FP_M1_DIV_MASK 0x00003f00 1565 #define FP_M1_DIV_SHIFT 8 1566 #define FP_M2_DIV_MASK 0x0000003f 1567 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1568 #define FP_M2_DIV_SHIFT 0 1569 #define DPLL_TEST _MMIO(0x606c) 1570 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1571 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1572 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1573 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1574 #define DPLLB_TEST_N_BYPASS (1 << 19) 1575 #define DPLLB_TEST_M_BYPASS (1 << 18) 1576 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1577 #define DPLLA_TEST_N_BYPASS (1 << 3) 1578 #define DPLLA_TEST_M_BYPASS (1 << 2) 1579 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1580 #define D_STATE _MMIO(0x6104) 1581 #define DSTATE_GFX_RESET_I830 (1 << 6) 1582 #define DSTATE_PLL_D3_OFF (1 << 3) 1583 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1584 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1585 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 1586 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1587 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1588 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1589 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1590 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1591 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1592 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1593 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1594 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1595 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1596 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1597 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1598 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1599 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1600 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1601 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1602 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1603 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1604 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1605 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1606 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1607 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1608 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1609 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1610 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1611 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1612 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1613 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1614 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1615 /* 1616 * This bit must be set on the 830 to prevent hangs when turning off the 1617 * overlay scaler. 1618 */ 1619 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1620 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1621 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1622 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1623 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1624 1625 #define RENCLK_GATE_D1 _MMIO(0x6204) 1626 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1627 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1628 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1629 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1630 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1631 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1632 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1633 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1634 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1635 /* This bit must be unset on 855,865 */ 1636 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1637 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1638 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1639 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1640 /* This bit must be set on 855,865. */ 1641 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1642 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1643 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1644 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1645 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1646 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1647 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1648 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1649 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1650 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1651 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1652 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1653 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1654 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1655 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1656 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1657 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1658 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1659 1660 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1661 /* This bit must always be set on 965G/965GM */ 1662 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1663 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1664 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1665 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1666 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1667 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1668 /* This bit must always be set on 965G */ 1669 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1670 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1671 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1672 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1673 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1674 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1675 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1676 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1677 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1678 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1679 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1680 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1681 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1682 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1683 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1684 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1685 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1686 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1687 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1688 1689 #define RENCLK_GATE_D2 _MMIO(0x6208) 1690 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1691 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1692 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1693 1694 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1695 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1696 1697 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1698 #define DEUC _MMIO(0x6214) /* CRL only */ 1699 1700 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1701 #define FW_CSPWRDWNEN (1 << 15) 1702 1703 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1704 1705 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1706 #define CDCLK_FREQ_SHIFT 4 1707 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1708 #define CZCLK_FREQ_MASK 0xf 1709 1710 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1711 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1712 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1713 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1714 #define PFI_CREDIT_RESEND (1 << 27) 1715 #define VGA_FAST_MODE_DISABLE (1 << 14) 1716 1717 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1718 1719 /* 1720 * Palette regs 1721 */ 1722 #define _PALETTE_A 0xa000 1723 #define _PALETTE_B 0xa800 1724 #define _CHV_PALETTE_C 0xc000 1725 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ 1726 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1727 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1728 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1729 /* pre-i965 10bit interpolated mode ldw */ 1730 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) 1731 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) 1732 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) 1733 /* pre-i965 10bit interpolated mode udw */ 1734 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) 1735 #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) 1736 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) 1737 #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) 1738 #define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) 1739 #define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) 1740 #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) 1741 #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) 1742 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) 1743 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1744 _PICK_EVEN_2RANGES(pipe, 2, \ 1745 _PALETTE_A, _PALETTE_B, \ 1746 _CHV_PALETTE_C, _CHV_PALETTE_C) + \ 1747 (i) * 4) 1748 1749 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1750 1751 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1752 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1753 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1754 #define PVC_RP_STATE_CAP _MMIO(0x281014) 1755 1756 #define MTL_RP_STATE_CAP _MMIO(0x138000) 1757 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) 1758 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 1759 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 1760 1761 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) 1762 #define MTL_MPE_FREQUENCY _MMIO(0x13802c) 1763 #define MTL_RPE_MASK REG_GENMASK(8, 0) 1764 1765 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1766 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1767 #define PROCHOT_MASK REG_BIT(0) 1768 #define THERMAL_LIMIT_MASK REG_BIT(1) 1769 #define RATL_MASK REG_BIT(5) 1770 #define VR_THERMALERT_MASK REG_BIT(6) 1771 #define VR_TDC_MASK REG_BIT(7) 1772 #define POWER_LIMIT_4_MASK REG_BIT(8) 1773 #define POWER_LIMIT_1_MASK REG_BIT(10) 1774 #define POWER_LIMIT_2_MASK REG_BIT(11) 1775 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) 1776 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) 1777 1778 #define CHV_CLK_CTL1 _MMIO(0x101100) 1779 #define VLV_CLK_CTL2 _MMIO(0x101104) 1780 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1781 1782 /* 1783 * Overlay regs 1784 */ 1785 1786 #define OVADD _MMIO(0x30000) 1787 #define DOVSTA _MMIO(0x30008) 1788 #define OC_BUF (0x3 << 20) 1789 #define OGAMC5 _MMIO(0x30010) 1790 #define OGAMC4 _MMIO(0x30014) 1791 #define OGAMC3 _MMIO(0x30018) 1792 #define OGAMC2 _MMIO(0x3001c) 1793 #define OGAMC1 _MMIO(0x30020) 1794 #define OGAMC0 _MMIO(0x30024) 1795 1796 /* 1797 * GEN9 clock gating regs 1798 */ 1799 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1800 #define DARBF_GATING_DIS REG_BIT(27) 1801 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) 1802 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) 1803 #define PWM2_GATING_DIS REG_BIT(14) 1804 #define PWM1_GATING_DIS REG_BIT(13) 1805 1806 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1807 #define TGL_VRH_GATING_DIS REG_BIT(31) 1808 #define DPT_GATING_DIS REG_BIT(22) 1809 1810 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1811 #define BXT_GMBUS_GATING_DIS (1 << 14) 1812 1813 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1814 #define DPCE_GATING_DIS REG_BIT(17) 1815 1816 #define _CLKGATE_DIS_PSL_A 0x46520 1817 #define _CLKGATE_DIS_PSL_B 0x46524 1818 #define _CLKGATE_DIS_PSL_C 0x46528 1819 #define DUPS1_GATING_DIS (1 << 15) 1820 #define DUPS2_GATING_DIS (1 << 19) 1821 #define DUPS3_GATING_DIS (1 << 23) 1822 #define CURSOR_GATING_DIS REG_BIT(28) 1823 #define DPF_GATING_DIS (1 << 10) 1824 #define DPF_RAM_GATING_DIS (1 << 9) 1825 #define DPFR_GATING_DIS (1 << 8) 1826 1827 #define CLKGATE_DIS_PSL(pipe) \ 1828 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1829 1830 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1831 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1832 #define PIPEDMC_GATING_DIS REG_BIT(12) 1833 1834 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1835 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1836 1837 /* 1838 * Display engine regs 1839 */ 1840 1841 /* Pipe A CRC regs */ 1842 #define _PIPE_CRC_CTL_A 0x60050 1843 #define PIPE_CRC_ENABLE REG_BIT(31) 1844 /* skl+ source selection */ 1845 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1846 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1847 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1848 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1849 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1850 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1851 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1852 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1853 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1854 /* ivb+ source selection */ 1855 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1856 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1857 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1858 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1859 /* ilk+ source selection */ 1860 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1861 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1862 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1863 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1864 /* embedded DP port on the north display block */ 1865 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1866 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1867 /* vlv source selection */ 1868 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1869 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1870 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1871 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1872 /* with DP port the pipe source is invalid */ 1873 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1874 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1875 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1876 /* gen3+ source selection */ 1877 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1878 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1879 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1880 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1881 /* with DP/TV port the pipe source is invalid */ 1882 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1883 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1884 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1885 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1886 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1887 /* gen2 doesn't have source selection bits */ 1888 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1889 1890 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1891 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1892 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1893 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1894 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1895 1896 #define _PIPE_CRC_RES_RED_A 0x60060 1897 #define _PIPE_CRC_RES_GREEN_A 0x60064 1898 #define _PIPE_CRC_RES_BLUE_A 0x60068 1899 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1900 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1901 1902 /* Pipe B CRC regs */ 1903 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1904 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1905 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1906 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1907 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1908 1909 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1910 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1911 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1912 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1913 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1914 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1915 1916 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1917 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 1918 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 1919 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 1920 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 1921 1922 /* Pipe/transcoder A timing regs */ 1923 #define _TRANS_HTOTAL_A 0x60000 1924 #define HTOTAL_MASK REG_GENMASK(31, 16) 1925 #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) 1926 #define HACTIVE_MASK REG_GENMASK(15, 0) 1927 #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) 1928 #define _TRANS_HBLANK_A 0x60004 1929 #define HBLANK_END_MASK REG_GENMASK(31, 16) 1930 #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) 1931 #define HBLANK_START_MASK REG_GENMASK(15, 0) 1932 #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) 1933 #define _TRANS_HSYNC_A 0x60008 1934 #define HSYNC_END_MASK REG_GENMASK(31, 16) 1935 #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) 1936 #define HSYNC_START_MASK REG_GENMASK(15, 0) 1937 #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) 1938 #define _TRANS_VTOTAL_A 0x6000c 1939 #define VTOTAL_MASK REG_GENMASK(31, 16) 1940 #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) 1941 #define VACTIVE_MASK REG_GENMASK(15, 0) 1942 #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) 1943 #define _TRANS_VBLANK_A 0x60010 1944 #define VBLANK_END_MASK REG_GENMASK(31, 16) 1945 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) 1946 #define VBLANK_START_MASK REG_GENMASK(15, 0) 1947 #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) 1948 #define _TRANS_VSYNC_A 0x60014 1949 #define VSYNC_END_MASK REG_GENMASK(31, 16) 1950 #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) 1951 #define VSYNC_START_MASK REG_GENMASK(15, 0) 1952 #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) 1953 #define _TRANS_EXITLINE_A 0x60018 1954 #define _PIPEASRC 0x6001c 1955 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1956 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1957 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1958 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1959 #define _BCLRPAT_A 0x60020 1960 #define _TRANS_VSYNCSHIFT_A 0x60028 1961 #define _TRANS_MULT_A 0x6002c 1962 1963 /* Pipe/transcoder B timing regs */ 1964 #define _TRANS_HTOTAL_B 0x61000 1965 #define _TRANS_HBLANK_B 0x61004 1966 #define _TRANS_HSYNC_B 0x61008 1967 #define _TRANS_VTOTAL_B 0x6100c 1968 #define _TRANS_VBLANK_B 0x61010 1969 #define _TRANS_VSYNC_B 0x61014 1970 #define _PIPEBSRC 0x6101c 1971 #define _BCLRPAT_B 0x61020 1972 #define _TRANS_VSYNCSHIFT_B 0x61028 1973 #define _TRANS_MULT_B 0x6102c 1974 1975 /* DSI 0 timing regs */ 1976 #define _TRANS_HTOTAL_DSI0 0x6b000 1977 #define _TRANS_HSYNC_DSI0 0x6b008 1978 #define _TRANS_VTOTAL_DSI0 0x6b00c 1979 #define _TRANS_VSYNC_DSI0 0x6b014 1980 #define _TRANS_VSYNCSHIFT_DSI0 0x6b028 1981 1982 /* DSI 1 timing regs */ 1983 #define _TRANS_HTOTAL_DSI1 0x6b800 1984 #define _TRANS_HSYNC_DSI1 0x6b808 1985 #define _TRANS_VTOTAL_DSI1 0x6b80c 1986 #define _TRANS_VSYNC_DSI1 0x6b814 1987 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 1988 1989 #define TRANSCODER_A_OFFSET 0x60000 1990 #define TRANSCODER_B_OFFSET 0x61000 1991 #define TRANSCODER_C_OFFSET 0x62000 1992 #define CHV_TRANSCODER_C_OFFSET 0x63000 1993 #define TRANSCODER_D_OFFSET 0x63000 1994 #define TRANSCODER_EDP_OFFSET 0x6f000 1995 #define TRANSCODER_DSI0_OFFSET 0x6b000 1996 #define TRANSCODER_DSI1_OFFSET 0x6b800 1997 1998 #define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A) 1999 #define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A) 2000 #define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A) 2001 #define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A) 2002 #define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A) 2003 #define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A) 2004 #define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A) 2005 #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A) 2006 #define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC) 2007 #define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A) 2008 2009 /* VRR registers */ 2010 #define _TRANS_VRR_CTL_A 0x60420 2011 #define _TRANS_VRR_CTL_B 0x61420 2012 #define _TRANS_VRR_CTL_C 0x62420 2013 #define _TRANS_VRR_CTL_D 0x63420 2014 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 2015 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 2016 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 2017 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 2018 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 2019 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 2020 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 2021 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 2022 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 2023 2024 #define _TRANS_VRR_VMAX_A 0x60424 2025 #define _TRANS_VRR_VMAX_B 0x61424 2026 #define _TRANS_VRR_VMAX_C 0x62424 2027 #define _TRANS_VRR_VMAX_D 0x63424 2028 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 2029 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 2030 2031 #define _TRANS_VRR_VMIN_A 0x60434 2032 #define _TRANS_VRR_VMIN_B 0x61434 2033 #define _TRANS_VRR_VMIN_C 0x62434 2034 #define _TRANS_VRR_VMIN_D 0x63434 2035 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2036 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2037 2038 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2039 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2040 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2041 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2042 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2043 _TRANS_VRR_VMAXSHIFT_A) 2044 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2045 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2046 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2047 2048 #define _TRANS_VRR_STATUS_A 0x6042C 2049 #define _TRANS_VRR_STATUS_B 0x6142C 2050 #define _TRANS_VRR_STATUS_C 0x6242C 2051 #define _TRANS_VRR_STATUS_D 0x6342C 2052 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2053 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2054 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2055 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2056 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2057 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2058 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2059 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2060 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2061 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2062 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2063 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2064 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2065 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2066 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2067 2068 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2069 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2070 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2071 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2072 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2073 _TRANS_VRR_VTOTAL_PREV_A) 2074 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2075 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2076 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2077 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2078 2079 #define _TRANS_VRR_FLIPLINE_A 0x60438 2080 #define _TRANS_VRR_FLIPLINE_B 0x61438 2081 #define _TRANS_VRR_FLIPLINE_C 0x62438 2082 #define _TRANS_VRR_FLIPLINE_D 0x63438 2083 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2084 _TRANS_VRR_FLIPLINE_A) 2085 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2086 2087 #define _TRANS_VRR_STATUS2_A 0x6043C 2088 #define _TRANS_VRR_STATUS2_B 0x6143C 2089 #define _TRANS_VRR_STATUS2_C 0x6243C 2090 #define _TRANS_VRR_STATUS2_D 0x6343C 2091 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2092 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2093 2094 #define _TRANS_PUSH_A 0x60A70 2095 #define _TRANS_PUSH_B 0x61A70 2096 #define _TRANS_PUSH_C 0x62A70 2097 #define _TRANS_PUSH_D 0x63A70 2098 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2099 #define TRANS_PUSH_EN REG_BIT(31) 2100 #define TRANS_PUSH_SEND REG_BIT(30) 2101 2102 /* VGA port control */ 2103 #define ADPA _MMIO(0x61100) 2104 #define PCH_ADPA _MMIO(0xe1100) 2105 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2106 2107 #define ADPA_DAC_ENABLE (1 << 31) 2108 #define ADPA_DAC_DISABLE 0 2109 #define ADPA_PIPE_SEL_SHIFT 30 2110 #define ADPA_PIPE_SEL_MASK (1 << 30) 2111 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2112 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2113 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2114 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2115 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2116 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2117 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2118 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2119 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2120 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2121 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2122 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2123 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2124 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2125 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2126 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2127 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2128 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2129 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2130 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2131 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2132 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2133 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2134 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2135 #define ADPA_SETS_HVPOLARITY 0 2136 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2137 #define ADPA_VSYNC_CNTL_ENABLE 0 2138 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2139 #define ADPA_HSYNC_CNTL_ENABLE 0 2140 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2141 #define ADPA_VSYNC_ACTIVE_LOW 0 2142 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2143 #define ADPA_HSYNC_ACTIVE_LOW 0 2144 #define ADPA_DPMS_MASK (~(3 << 10)) 2145 #define ADPA_DPMS_ON (0 << 10) 2146 #define ADPA_DPMS_SUSPEND (1 << 10) 2147 #define ADPA_DPMS_STANDBY (2 << 10) 2148 #define ADPA_DPMS_OFF (3 << 10) 2149 2150 2151 /* Hotplug control (945+ only) */ 2152 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2153 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2154 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2155 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2156 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2157 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2158 #define TV_HOTPLUG_INT_EN (1 << 18) 2159 #define CRT_HOTPLUG_INT_EN (1 << 9) 2160 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2161 PORTC_HOTPLUG_INT_EN | \ 2162 PORTD_HOTPLUG_INT_EN | \ 2163 SDVOC_HOTPLUG_INT_EN | \ 2164 SDVOB_HOTPLUG_INT_EN | \ 2165 CRT_HOTPLUG_INT_EN) 2166 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2167 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2168 /* must use period 64 on GM45 according to docs */ 2169 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2170 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2171 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2172 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2173 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2174 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2175 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2176 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2177 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2178 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2179 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2180 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2181 2182 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2183 /* HDMI/DP bits are g4x+ */ 2184 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2185 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2186 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2187 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2188 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2189 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2190 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2191 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2192 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2193 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2194 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2195 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2196 /* CRT/TV common between gen3+ */ 2197 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2198 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2199 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2200 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2201 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2202 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2203 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2204 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2205 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2206 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2207 2208 /* SDVO is different across gen3/4 */ 2209 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2210 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2211 /* 2212 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2213 * since reality corrobates that they're the same as on gen3. But keep these 2214 * bits here (and the comment!) to help any other lost wanderers back onto the 2215 * right tracks. 2216 */ 2217 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2218 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2219 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2220 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2221 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2222 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2223 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2224 PORTB_HOTPLUG_INT_STATUS | \ 2225 PORTC_HOTPLUG_INT_STATUS | \ 2226 PORTD_HOTPLUG_INT_STATUS) 2227 2228 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2229 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2230 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2231 PORTB_HOTPLUG_INT_STATUS | \ 2232 PORTC_HOTPLUG_INT_STATUS | \ 2233 PORTD_HOTPLUG_INT_STATUS) 2234 2235 /* SDVO and HDMI port control. 2236 * The same register may be used for SDVO or HDMI */ 2237 #define _GEN3_SDVOB 0x61140 2238 #define _GEN3_SDVOC 0x61160 2239 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2240 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2241 #define GEN4_HDMIB GEN3_SDVOB 2242 #define GEN4_HDMIC GEN3_SDVOC 2243 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2244 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2245 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2246 #define PCH_SDVOB _MMIO(0xe1140) 2247 #define PCH_HDMIB PCH_SDVOB 2248 #define PCH_HDMIC _MMIO(0xe1150) 2249 #define PCH_HDMID _MMIO(0xe1160) 2250 2251 #define PORT_DFT_I9XX _MMIO(0x61150) 2252 #define DC_BALANCE_RESET (1 << 25) 2253 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2254 #define DC_BALANCE_RESET_VLV (1 << 31) 2255 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2256 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2257 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2258 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2259 2260 /* Gen 3 SDVO bits: */ 2261 #define SDVO_ENABLE (1 << 31) 2262 #define SDVO_PIPE_SEL_SHIFT 30 2263 #define SDVO_PIPE_SEL_MASK (1 << 30) 2264 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2265 #define SDVO_STALL_SELECT (1 << 29) 2266 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2267 /* 2268 * 915G/GM SDVO pixel multiplier. 2269 * Programmed value is multiplier - 1, up to 5x. 2270 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2271 */ 2272 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2273 #define SDVO_PORT_MULTIPLY_SHIFT 23 2274 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2275 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2276 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2277 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2278 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2279 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2280 #define SDVO_DETECTED (1 << 2) 2281 /* Bits to be preserved when writing */ 2282 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2283 SDVO_INTERRUPT_ENABLE) 2284 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2285 2286 /* Gen 4 SDVO/HDMI bits: */ 2287 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2288 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2289 #define SDVO_ENCODING_SDVO (0 << 10) 2290 #define SDVO_ENCODING_HDMI (2 << 10) 2291 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2292 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2293 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2294 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2295 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2296 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2297 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2298 2299 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2300 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2301 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2302 2303 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2304 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2305 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2306 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2307 2308 /* CHV SDVO/HDMI bits: */ 2309 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2310 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2311 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2312 2313 /* Video Data Island Packet control */ 2314 #define VIDEO_DIP_DATA _MMIO(0x61178) 2315 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2316 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2317 * of the infoframe structure specified by CEA-861. */ 2318 #define VIDEO_DIP_DATA_SIZE 32 2319 #define VIDEO_DIP_GMP_DATA_SIZE 36 2320 #define VIDEO_DIP_VSC_DATA_SIZE 36 2321 #define VIDEO_DIP_PPS_DATA_SIZE 132 2322 #define VIDEO_DIP_CTL _MMIO(0x61170) 2323 /* Pre HSW: */ 2324 #define VIDEO_DIP_ENABLE (1 << 31) 2325 #define VIDEO_DIP_PORT(port) ((port) << 29) 2326 #define VIDEO_DIP_PORT_MASK (3 << 29) 2327 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2328 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2329 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2330 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2331 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2332 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2333 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2334 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2335 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2336 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2337 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2338 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2339 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2340 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2341 /* HSW and later: */ 2342 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2343 #define PSR_VSC_BIT_7_SET (1 << 27) 2344 #define VSC_SELECT_MASK (0x3 << 25) 2345 #define VSC_SELECT_SHIFT 25 2346 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2347 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2348 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2349 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2350 #define VDIP_ENABLE_PPS (1 << 24) 2351 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2352 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2353 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2354 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2355 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2356 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2357 2358 /* Panel fitting */ 2359 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2360 #define PFIT_ENABLE (1 << 31) 2361 #define PFIT_PIPE_MASK (3 << 29) 2362 #define PFIT_PIPE_SHIFT 29 2363 #define PFIT_PIPE(pipe) ((pipe) << 29) 2364 #define VERT_INTERP_DISABLE (0 << 10) 2365 #define VERT_INTERP_BILINEAR (1 << 10) 2366 #define VERT_INTERP_MASK (3 << 10) 2367 #define VERT_AUTO_SCALE (1 << 9) 2368 #define HORIZ_INTERP_DISABLE (0 << 6) 2369 #define HORIZ_INTERP_BILINEAR (1 << 6) 2370 #define HORIZ_INTERP_MASK (3 << 6) 2371 #define HORIZ_AUTO_SCALE (1 << 5) 2372 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2373 #define PFIT_FILTER_FUZZY (0 << 24) 2374 #define PFIT_SCALING_AUTO (0 << 26) 2375 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2376 #define PFIT_SCALING_PILLAR (2 << 26) 2377 #define PFIT_SCALING_LETTER (3 << 26) 2378 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2379 /* Pre-965 */ 2380 #define PFIT_VERT_SCALE_SHIFT 20 2381 #define PFIT_VERT_SCALE_MASK 0xfff00000 2382 #define PFIT_HORIZ_SCALE_SHIFT 4 2383 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2384 /* 965+ */ 2385 #define PFIT_VERT_SCALE_SHIFT_965 16 2386 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2387 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2388 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2389 2390 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2391 2392 #define PCH_GTC_CTL _MMIO(0xe7000) 2393 #define PCH_GTC_ENABLE (1 << 31) 2394 2395 /* Display Port */ 2396 #define DP_A _MMIO(0x64000) /* eDP */ 2397 #define DP_B _MMIO(0x64100) 2398 #define DP_C _MMIO(0x64200) 2399 #define DP_D _MMIO(0x64300) 2400 2401 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 2402 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 2403 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 2404 2405 #define DP_PORT_EN (1 << 31) 2406 #define DP_PIPE_SEL_SHIFT 30 2407 #define DP_PIPE_SEL_MASK (1 << 30) 2408 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 2409 #define DP_PIPE_SEL_SHIFT_IVB 29 2410 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 2411 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 2412 #define DP_PIPE_SEL_SHIFT_CHV 16 2413 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 2414 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 2415 2416 /* Link training mode - select a suitable mode for each stage */ 2417 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2418 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2419 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2420 #define DP_LINK_TRAIN_OFF (3 << 28) 2421 #define DP_LINK_TRAIN_MASK (3 << 28) 2422 #define DP_LINK_TRAIN_SHIFT 28 2423 2424 /* CPT Link training mode */ 2425 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2426 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2427 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2428 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2429 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2430 #define DP_LINK_TRAIN_SHIFT_CPT 8 2431 2432 /* Signal voltages. These are mostly controlled by the other end */ 2433 #define DP_VOLTAGE_0_4 (0 << 25) 2434 #define DP_VOLTAGE_0_6 (1 << 25) 2435 #define DP_VOLTAGE_0_8 (2 << 25) 2436 #define DP_VOLTAGE_1_2 (3 << 25) 2437 #define DP_VOLTAGE_MASK (7 << 25) 2438 #define DP_VOLTAGE_SHIFT 25 2439 2440 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2441 * they want 2442 */ 2443 #define DP_PRE_EMPHASIS_0 (0 << 22) 2444 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2445 #define DP_PRE_EMPHASIS_6 (2 << 22) 2446 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2447 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2448 #define DP_PRE_EMPHASIS_SHIFT 22 2449 2450 /* How many wires to use. I guess 3 was too hard */ 2451 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 2452 #define DP_PORT_WIDTH_MASK (7 << 19) 2453 #define DP_PORT_WIDTH_SHIFT 19 2454 2455 /* Mystic DPCD version 1.1 special mode */ 2456 #define DP_ENHANCED_FRAMING (1 << 18) 2457 2458 /* eDP */ 2459 #define DP_PLL_FREQ_270MHZ (0 << 16) 2460 #define DP_PLL_FREQ_162MHZ (1 << 16) 2461 #define DP_PLL_FREQ_MASK (3 << 16) 2462 2463 /* locked once port is enabled */ 2464 #define DP_PORT_REVERSAL (1 << 15) 2465 2466 /* eDP */ 2467 #define DP_PLL_ENABLE (1 << 14) 2468 2469 /* sends the clock on lane 15 of the PEG for debug */ 2470 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2471 2472 #define DP_SCRAMBLING_DISABLE (1 << 12) 2473 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2474 2475 /* limit RGB values to avoid confusing TVs */ 2476 #define DP_COLOR_RANGE_16_235 (1 << 8) 2477 2478 /* Turn on the audio link */ 2479 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2480 2481 /* vs and hs sync polarity */ 2482 #define DP_SYNC_VS_HIGH (1 << 4) 2483 #define DP_SYNC_HS_HIGH (1 << 3) 2484 2485 /* A fantasy */ 2486 #define DP_DETECTED (1 << 2) 2487 2488 /* 2489 * Computing GMCH M and N values for the Display Port link 2490 * 2491 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2492 * 2493 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2494 * 2495 * The GMCH value is used internally 2496 * 2497 * bytes_per_pixel is the number of bytes coming out of the plane, 2498 * which is after the LUTs, so we want the bytes for our color format. 2499 * For our current usage, this is always 3, one byte for R, G and B. 2500 */ 2501 #define _PIPEA_DATA_M_G4X 0x70050 2502 #define _PIPEB_DATA_M_G4X 0x71050 2503 2504 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2505 #define TU_SIZE_MASK REG_GENMASK(30, 25) 2506 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 2507 2508 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 2509 #define DATA_LINK_N_MAX (0x800000) 2510 2511 #define _PIPEA_DATA_N_G4X 0x70054 2512 #define _PIPEB_DATA_N_G4X 0x71054 2513 2514 /* 2515 * Computing Link M and N values for the Display Port link 2516 * 2517 * Link M / N = pixel_clock / ls_clk 2518 * 2519 * (the DP spec calls pixel_clock the 'strm_clk') 2520 * 2521 * The Link value is transmitted in the Main Stream 2522 * Attributes and VB-ID. 2523 */ 2524 2525 #define _PIPEA_LINK_M_G4X 0x70060 2526 #define _PIPEB_LINK_M_G4X 0x71060 2527 #define _PIPEA_LINK_N_G4X 0x70064 2528 #define _PIPEB_LINK_N_G4X 0x71064 2529 2530 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 2531 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 2532 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 2533 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 2534 2535 /* Display & cursor control */ 2536 2537 /* Pipe A */ 2538 #define _PIPEADSL 0x70000 2539 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 2540 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 2541 #define _TRANSACONF 0x70008 2542 #define TRANSCONF_ENABLE REG_BIT(31) 2543 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 2544 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 2545 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 2546 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 2547 #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 2548 #define TRANSCONF_PIPE_LOCKED REG_BIT(25) 2549 #define TRANSCONF_FORCE_BORDER REG_BIT(25) 2550 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 2551 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 2552 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) 2553 #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) 2554 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 2555 #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 2556 #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 2557 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 2558 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) 2559 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ 2560 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ 2561 #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) 2562 #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ 2563 /* 2564 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 2565 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 2566 */ 2567 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 2568 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 2569 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) 2570 #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) 2571 #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) 2572 #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 2573 #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 2574 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 2575 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 2576 #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) 2577 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) 2578 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 2579 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) 2580 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 2581 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 2582 #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 2583 #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 2584 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 2585 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 2586 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) 2587 #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) 2588 #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) 2589 #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) 2590 #define TRANSCONF_DITHER_EN REG_BIT(4) 2591 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 2592 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) 2593 #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) 2594 #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) 2595 #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) 2596 #define _PIPEASTAT 0x70024 2597 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 2598 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 2599 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 2600 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 2601 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 2602 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 2603 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 2604 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 2605 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 2606 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 2607 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 2608 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 2609 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 2610 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 2611 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 2612 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 2613 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 2614 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 2615 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 2616 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 2617 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 2618 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 2619 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 2620 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 2621 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 2622 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 2623 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 2624 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 2625 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 2626 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 2627 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 2628 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 2629 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 2630 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 2631 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 2632 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 2633 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 2634 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 2635 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 2636 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 2637 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 2638 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 2639 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 2640 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 2641 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 2642 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 2643 2644 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 2645 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 2646 2647 #define PIPE_A_OFFSET 0x70000 2648 #define PIPE_B_OFFSET 0x71000 2649 #define PIPE_C_OFFSET 0x72000 2650 #define PIPE_D_OFFSET 0x73000 2651 #define CHV_PIPE_C_OFFSET 0x74000 2652 /* 2653 * There's actually no pipe EDP. Some pipe registers have 2654 * simply shifted from the pipe to the transcoder, while 2655 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 2656 * to access such registers in transcoder EDP. 2657 */ 2658 #define PIPE_EDP_OFFSET 0x7f000 2659 2660 /* ICL DSI 0 and 1 */ 2661 #define PIPE_DSI0_OFFSET 0x7b000 2662 #define PIPE_DSI1_OFFSET 0x7b800 2663 2664 #define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF) 2665 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 2666 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 2667 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 2668 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 2669 2670 #define _PIPEAGCMAX 0x70010 2671 #define _PIPEBGCMAX 0x71010 2672 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ 2673 2674 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 2675 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 2676 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 2677 2678 #define _PIPE_MISC_A 0x70030 2679 #define _PIPE_MISC_B 0x71030 2680 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 2681 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 2682 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 2683 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 2684 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 2685 /* 2686 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 2687 * valid values of: 6, 8, 10 BPC. 2688 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 2689 * 6, 8, 10, 12 BPC. 2690 */ 2691 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) 2692 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) 2693 #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) 2694 #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) 2695 #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ 2696 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4) 2697 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 2698 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) 2699 #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) 2700 #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) 2701 #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) 2702 #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) 2703 2704 #define _PIPE_MISC2_A 0x7002C 2705 #define _PIPE_MISC2_B 0x7102C 2706 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 2707 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 2708 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 2709 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ 2710 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) 2711 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) 2712 2713 /* Skylake+ pipe bottom (background) color */ 2714 #define _SKL_BOTTOM_COLOR_A 0x70034 2715 #define _SKL_BOTTOM_COLOR_B 0x71034 2716 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 2717 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 2718 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B) 2719 2720 #define _ICL_PIPE_A_STATUS 0x70058 2721 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 2722 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 2723 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 2724 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 2725 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 2726 2727 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 2728 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 2729 #define PIPEB_HLINE_INT_EN REG_BIT(28) 2730 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 2731 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 2732 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 2733 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 2734 #define PIPE_PSR_INT_EN REG_BIT(22) 2735 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 2736 #define PIPEA_HLINE_INT_EN REG_BIT(20) 2737 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 2738 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 2739 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 2740 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 2741 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 2742 #define PIPEC_HLINE_INT_EN REG_BIT(12) 2743 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 2744 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 2745 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 2746 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 2747 2748 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 2749 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 2750 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 2751 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 2752 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 2753 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 2754 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 2755 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 2756 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 2757 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 2758 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 2759 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 2760 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 2761 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 2762 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 2763 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 2764 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 2765 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 2766 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 2767 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 2768 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 2769 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 2770 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 2771 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 2772 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 2773 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 2774 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 2775 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 2776 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 2777 2778 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 2779 #define DSPARB_CSTART_MASK (0x7f << 7) 2780 #define DSPARB_CSTART_SHIFT 7 2781 #define DSPARB_BSTART_MASK (0x7f) 2782 #define DSPARB_BSTART_SHIFT 0 2783 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2784 #define DSPARB_AEND_SHIFT 0 2785 #define DSPARB_SPRITEA_SHIFT_VLV 0 2786 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 2787 #define DSPARB_SPRITEB_SHIFT_VLV 8 2788 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 2789 #define DSPARB_SPRITEC_SHIFT_VLV 16 2790 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 2791 #define DSPARB_SPRITED_SHIFT_VLV 24 2792 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 2793 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 2794 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 2795 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 2796 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 2797 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 2798 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 2799 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 2800 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 2801 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 2802 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 2803 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 2804 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 2805 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 2806 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 2807 #define DSPARB_SPRITEE_SHIFT_VLV 0 2808 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 2809 #define DSPARB_SPRITEF_SHIFT_VLV 8 2810 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 2811 2812 /* pnv/gen4/g4x/vlv/chv */ 2813 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 2814 #define DSPFW_SR_SHIFT 23 2815 #define DSPFW_SR_MASK (0x1ff << 23) 2816 #define DSPFW_CURSORB_SHIFT 16 2817 #define DSPFW_CURSORB_MASK (0x3f << 16) 2818 #define DSPFW_PLANEB_SHIFT 8 2819 #define DSPFW_PLANEB_MASK (0x7f << 8) 2820 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 2821 #define DSPFW_PLANEA_SHIFT 0 2822 #define DSPFW_PLANEA_MASK (0x7f << 0) 2823 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 2824 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 2825 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 2826 #define DSPFW_FBC_SR_SHIFT 28 2827 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 2828 #define DSPFW_FBC_HPLL_SR_SHIFT 24 2829 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 2830 #define DSPFW_SPRITEB_SHIFT (16) 2831 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 2832 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 2833 #define DSPFW_CURSORA_SHIFT 8 2834 #define DSPFW_CURSORA_MASK (0x3f << 8) 2835 #define DSPFW_PLANEC_OLD_SHIFT 0 2836 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 2837 #define DSPFW_SPRITEA_SHIFT 0 2838 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 2839 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 2840 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 2841 #define DSPFW_HPLL_SR_EN (1 << 31) 2842 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 2843 #define DSPFW_CURSOR_SR_SHIFT 24 2844 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 2845 #define DSPFW_HPLL_CURSOR_SHIFT 16 2846 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 2847 #define DSPFW_HPLL_SR_SHIFT 0 2848 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 2849 2850 /* vlv/chv */ 2851 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 2852 #define DSPFW_SPRITEB_WM1_SHIFT 16 2853 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 2854 #define DSPFW_CURSORA_WM1_SHIFT 8 2855 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 2856 #define DSPFW_SPRITEA_WM1_SHIFT 0 2857 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 2858 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 2859 #define DSPFW_PLANEB_WM1_SHIFT 24 2860 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 2861 #define DSPFW_PLANEA_WM1_SHIFT 16 2862 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 2863 #define DSPFW_CURSORB_WM1_SHIFT 8 2864 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 2865 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 2866 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 2867 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 2868 #define DSPFW_SR_WM1_SHIFT 0 2869 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 2870 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 2871 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 2872 #define DSPFW_SPRITED_WM1_SHIFT 24 2873 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 2874 #define DSPFW_SPRITED_SHIFT 16 2875 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 2876 #define DSPFW_SPRITEC_WM1_SHIFT 8 2877 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 2878 #define DSPFW_SPRITEC_SHIFT 0 2879 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 2880 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 2881 #define DSPFW_SPRITEF_WM1_SHIFT 24 2882 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 2883 #define DSPFW_SPRITEF_SHIFT 16 2884 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 2885 #define DSPFW_SPRITEE_WM1_SHIFT 8 2886 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 2887 #define DSPFW_SPRITEE_SHIFT 0 2888 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 2889 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 2890 #define DSPFW_PLANEC_WM1_SHIFT 24 2891 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 2892 #define DSPFW_PLANEC_SHIFT 16 2893 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 2894 #define DSPFW_CURSORC_WM1_SHIFT 8 2895 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 2896 #define DSPFW_CURSORC_SHIFT 0 2897 #define DSPFW_CURSORC_MASK (0x3f << 0) 2898 2899 /* vlv/chv high order bits */ 2900 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 2901 #define DSPFW_SR_HI_SHIFT 24 2902 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 2903 #define DSPFW_SPRITEF_HI_SHIFT 23 2904 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 2905 #define DSPFW_SPRITEE_HI_SHIFT 22 2906 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 2907 #define DSPFW_PLANEC_HI_SHIFT 21 2908 #define DSPFW_PLANEC_HI_MASK (1 << 21) 2909 #define DSPFW_SPRITED_HI_SHIFT 20 2910 #define DSPFW_SPRITED_HI_MASK (1 << 20) 2911 #define DSPFW_SPRITEC_HI_SHIFT 16 2912 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 2913 #define DSPFW_PLANEB_HI_SHIFT 12 2914 #define DSPFW_PLANEB_HI_MASK (1 << 12) 2915 #define DSPFW_SPRITEB_HI_SHIFT 8 2916 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 2917 #define DSPFW_SPRITEA_HI_SHIFT 4 2918 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 2919 #define DSPFW_PLANEA_HI_SHIFT 0 2920 #define DSPFW_PLANEA_HI_MASK (1 << 0) 2921 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 2922 #define DSPFW_SR_WM1_HI_SHIFT 24 2923 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 2924 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 2925 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 2926 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 2927 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 2928 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 2929 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 2930 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 2931 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 2932 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 2933 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 2934 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 2935 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 2936 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 2937 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 2938 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 2939 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 2940 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 2941 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 2942 2943 /* drain latency register values*/ 2944 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 2945 #define DDL_CURSOR_SHIFT 24 2946 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 2947 #define DDL_PLANE_SHIFT 0 2948 #define DDL_PRECISION_HIGH (1 << 7) 2949 #define DDL_PRECISION_LOW (0 << 7) 2950 #define DRAIN_LATENCY_MASK 0x7f 2951 2952 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 2953 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 2954 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 2955 2956 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 2957 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 2958 2959 /* FIFO watermark sizes etc */ 2960 #define G4X_FIFO_LINE_SIZE 64 2961 #define I915_FIFO_LINE_SIZE 64 2962 #define I830_FIFO_LINE_SIZE 32 2963 2964 #define VALLEYVIEW_FIFO_SIZE 255 2965 #define G4X_FIFO_SIZE 127 2966 #define I965_FIFO_SIZE 512 2967 #define I945_FIFO_SIZE 127 2968 #define I915_FIFO_SIZE 95 2969 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2970 #define I830_FIFO_SIZE 95 2971 2972 #define VALLEYVIEW_MAX_WM 0xff 2973 #define G4X_MAX_WM 0x3f 2974 #define I915_MAX_WM 0x3f 2975 2976 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2977 #define PINEVIEW_FIFO_LINE_SIZE 64 2978 #define PINEVIEW_MAX_WM 0x1ff 2979 #define PINEVIEW_DFT_WM 0x3f 2980 #define PINEVIEW_DFT_HPLLOFF_WM 0 2981 #define PINEVIEW_GUARD_WM 10 2982 #define PINEVIEW_CURSOR_FIFO 64 2983 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2984 #define PINEVIEW_CURSOR_DFT_WM 0 2985 #define PINEVIEW_CURSOR_GUARD_WM 5 2986 2987 #define VALLEYVIEW_CURSOR_MAX_WM 64 2988 #define I965_CURSOR_FIFO 64 2989 #define I965_CURSOR_MAX_WM 32 2990 #define I965_CURSOR_DFT_WM 8 2991 2992 /* define the Watermark register on Ironlake */ 2993 #define _WM0_PIPEA_ILK 0x45100 2994 #define _WM0_PIPEB_ILK 0x45104 2995 #define _WM0_PIPEC_IVB 0x45200 2996 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 2997 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 2998 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 2999 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 3000 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 3001 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 3002 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 3003 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 3004 #define WM1_LP_ILK _MMIO(0x45108) 3005 #define WM2_LP_ILK _MMIO(0x4510c) 3006 #define WM3_LP_ILK _MMIO(0x45110) 3007 #define WM_LP_ENABLE REG_BIT(31) 3008 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 3009 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 3010 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 3011 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 3012 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 3013 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 3014 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 3015 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 3016 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 3017 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 3018 #define WM1S_LP_ILK _MMIO(0x45120) 3019 #define WM2S_LP_IVB _MMIO(0x45124) 3020 #define WM3S_LP_IVB _MMIO(0x45128) 3021 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 3022 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 3023 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 3024 3025 /* 3026 * The two pipe frame counter registers are not synchronized, so 3027 * reading a stable value is somewhat tricky. The following code 3028 * should work: 3029 * 3030 * do { 3031 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 3032 * PIPE_FRAME_HIGH_SHIFT; 3033 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 3034 * PIPE_FRAME_LOW_SHIFT); 3035 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 3036 * PIPE_FRAME_HIGH_SHIFT); 3037 * } while (high1 != high2); 3038 * frame = (high1 << 8) | low1; 3039 */ 3040 #define _PIPEAFRAMEHIGH 0x70040 3041 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 3042 #define PIPE_FRAME_HIGH_SHIFT 0 3043 #define _PIPEAFRAMEPIXEL 0x70044 3044 #define PIPE_FRAME_LOW_MASK 0xff000000 3045 #define PIPE_FRAME_LOW_SHIFT 24 3046 #define PIPE_PIXEL_MASK 0x00ffffff 3047 #define PIPE_PIXEL_SHIFT 0 3048 /* GM45+ just has to be different */ 3049 #define _PIPEA_FRMCOUNT_G4X 0x70040 3050 #define _PIPEA_FLIPCOUNT_G4X 0x70044 3051 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 3052 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 3053 3054 /* Cursor A & B regs */ 3055 #define _CURACNTR 0x70080 3056 /* Old style CUR*CNTR flags (desktop 8xx) */ 3057 #define CURSOR_ENABLE REG_BIT(31) 3058 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 3059 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 3060 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 3061 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 3062 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 3063 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 3064 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 3065 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 3066 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 3067 /* New style CUR*CNTR flags */ 3068 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 3069 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 3070 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 3071 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 3072 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 3073 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 3074 #define MCURSOR_ROTATE_180 REG_BIT(15) 3075 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 3076 #define MCURSOR_MODE_MASK 0x27 3077 #define MCURSOR_MODE_DISABLE 0x00 3078 #define MCURSOR_MODE_128_32B_AX 0x02 3079 #define MCURSOR_MODE_256_32B_AX 0x03 3080 #define MCURSOR_MODE_64_32B_AX 0x07 3081 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 3082 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 3083 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 3084 #define _CURABASE 0x70084 3085 #define _CURAPOS 0x70088 3086 #define CURSOR_POS_Y_SIGN REG_BIT(31) 3087 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 3088 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 3089 #define CURSOR_POS_X_SIGN REG_BIT(15) 3090 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 3091 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 3092 #define _CURASIZE 0x700a0 /* 845/865 */ 3093 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 3094 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 3095 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 3096 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 3097 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 3098 #define CUR_FBC_EN REG_BIT(31) 3099 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 3100 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 3101 #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ 3102 #define _CURASURFLIVE 0x700ac /* g4x+ */ 3103 #define _CURBCNTR 0x700c0 3104 #define _CURBBASE 0x700c4 3105 #define _CURBPOS 0x700c8 3106 3107 #define _CURBCNTR_IVB 0x71080 3108 #define _CURBBASE_IVB 0x71084 3109 #define _CURBPOS_IVB 0x71088 3110 3111 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) 3112 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) 3113 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) 3114 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) 3115 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) 3116 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A) 3117 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) 3118 3119 #define CURSOR_A_OFFSET 0x70080 3120 #define CURSOR_B_OFFSET 0x700c0 3121 #define CHV_CURSOR_C_OFFSET 0x700e0 3122 #define IVB_CURSOR_B_OFFSET 0x71080 3123 #define IVB_CURSOR_C_OFFSET 0x72080 3124 #define TGL_CURSOR_D_OFFSET 0x73080 3125 3126 /* Display A control */ 3127 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 3128 #define _DSPACNTR 0x70180 3129 #define DISP_ENABLE REG_BIT(31) 3130 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 3131 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 3132 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 3133 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 3134 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 3135 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 3136 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 3137 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 3138 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 3139 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 3140 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 3141 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 3142 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 3143 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 3144 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 3145 #define DISP_STEREO_ENABLE REG_BIT(25) 3146 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 3147 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 3148 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 3149 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 3150 #define DISP_LINE_DOUBLE REG_BIT(20) 3151 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 3152 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 3153 #define DISP_ROTATE_180 REG_BIT(15) 3154 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 3155 #define DISP_TILED REG_BIT(10) 3156 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 3157 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 3158 #define _DSPAADDR 0x70184 3159 #define _DSPASTRIDE 0x70188 3160 #define _DSPAPOS 0x7018C /* reserved */ 3161 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 3162 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 3163 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 3164 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 3165 #define _DSPASIZE 0x70190 3166 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 3167 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 3168 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 3169 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 3170 #define _DSPASURF 0x7019C /* 965+ only */ 3171 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 3172 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 3173 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 3174 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 3175 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 3176 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 3177 #define _DSPAOFFSET 0x701A4 /* HSW */ 3178 #define _DSPASURFLIVE 0x701AC 3179 #define _DSPAGAMC 0x701E0 3180 3181 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 3182 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 3183 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 3184 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 3185 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 3186 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 3187 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 3188 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 3189 #define DSPLINOFF(plane) DSPADDR(plane) 3190 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 3191 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 3192 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 3193 3194 /* CHV pipe B blender and primary plane */ 3195 #define _CHV_BLEND_A 0x60a00 3196 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 3197 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 3198 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 3199 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 3200 #define _CHV_CANVAS_A 0x60a04 3201 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 3202 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 3203 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 3204 #define _PRIMPOS_A 0x60a08 3205 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 3206 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 3207 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 3208 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 3209 #define _PRIMSIZE_A 0x60a0c 3210 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 3211 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 3212 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 3213 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 3214 #define _PRIMCNSTALPHA_A 0x60a10 3215 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 3216 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 3217 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 3218 3219 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 3220 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 3221 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 3222 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 3223 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 3224 3225 /* Display/Sprite base address macros */ 3226 #define DISP_BASEADDR_MASK (0xfffff000) 3227 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 3228 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 3229 3230 /* 3231 * VBIOS flags 3232 * gen2: 3233 * [00:06] alm,mgm 3234 * [10:16] all 3235 * [30:32] alm,mgm 3236 * gen3+: 3237 * [00:0f] all 3238 * [10:1f] all 3239 * [30:32] all 3240 */ 3241 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 3242 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 3243 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 3244 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 3245 3246 /* Pipe B */ 3247 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 3248 #define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 3249 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 3250 #define _PIPEBFRAMEHIGH 0x71040 3251 #define _PIPEBFRAMEPIXEL 0x71044 3252 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 3253 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 3254 3255 3256 /* Display B control */ 3257 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 3258 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 3259 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 3260 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 3261 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 3262 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 3263 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 3264 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 3265 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 3266 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 3267 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 3268 3269 /* ICL DSI 0 and 1 */ 3270 #define _PIPEDSI0CONF 0x7b008 3271 #define _PIPEDSI1CONF 0x7b808 3272 3273 /* Sprite A control */ 3274 #define _DVSACNTR 0x72180 3275 #define DVS_ENABLE REG_BIT(31) 3276 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 3277 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 3278 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 3279 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 3280 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 3281 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 3282 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 3283 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 3284 #define DVS_SOURCE_KEY REG_BIT(22) 3285 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 3286 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 3287 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 3288 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 3289 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 3290 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 3291 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 3292 #define DVS_ROTATE_180 REG_BIT(15) 3293 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 3294 #define DVS_TILED REG_BIT(10) 3295 #define DVS_DEST_KEY REG_BIT(2) 3296 #define _DVSALINOFF 0x72184 3297 #define _DVSASTRIDE 0x72188 3298 #define _DVSAPOS 0x7218c 3299 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 3300 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 3301 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 3302 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 3303 #define _DVSASIZE 0x72190 3304 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 3305 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 3306 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 3307 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 3308 #define _DVSAKEYVAL 0x72194 3309 #define _DVSAKEYMSK 0x72198 3310 #define _DVSASURF 0x7219c 3311 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 3312 #define _DVSAKEYMAXVAL 0x721a0 3313 #define _DVSATILEOFF 0x721a4 3314 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 3315 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 3316 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 3317 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 3318 #define _DVSASURFLIVE 0x721ac 3319 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 3320 #define _DVSASCALE 0x72204 3321 #define DVS_SCALE_ENABLE REG_BIT(31) 3322 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 3323 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 3324 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 3325 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 3326 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 3327 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 3328 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 3329 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 3330 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 3331 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 3332 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 3333 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 3334 3335 #define _DVSBCNTR 0x73180 3336 #define _DVSBLINOFF 0x73184 3337 #define _DVSBSTRIDE 0x73188 3338 #define _DVSBPOS 0x7318c 3339 #define _DVSBSIZE 0x73190 3340 #define _DVSBKEYVAL 0x73194 3341 #define _DVSBKEYMSK 0x73198 3342 #define _DVSBSURF 0x7319c 3343 #define _DVSBKEYMAXVAL 0x731a0 3344 #define _DVSBTILEOFF 0x731a4 3345 #define _DVSBSURFLIVE 0x731ac 3346 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 3347 #define _DVSBSCALE 0x73204 3348 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 3349 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 3350 3351 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 3352 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 3353 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 3354 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 3355 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 3356 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 3357 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 3358 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 3359 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 3360 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 3361 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 3362 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 3363 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 3364 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 3365 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 3366 3367 #define _SPRA_CTL 0x70280 3368 #define SPRITE_ENABLE REG_BIT(31) 3369 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 3370 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 3371 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 3372 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 3373 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 3374 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 3375 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 3376 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 3377 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 3378 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 3379 #define SPRITE_SOURCE_KEY REG_BIT(22) 3380 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 3381 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 3382 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 3383 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 3384 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 3385 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 3386 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 3387 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 3388 #define SPRITE_ROTATE_180 REG_BIT(15) 3389 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 3390 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 3391 #define SPRITE_TILED REG_BIT(10) 3392 #define SPRITE_DEST_KEY REG_BIT(2) 3393 #define _SPRA_LINOFF 0x70284 3394 #define _SPRA_STRIDE 0x70288 3395 #define _SPRA_POS 0x7028c 3396 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 3397 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 3398 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 3399 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 3400 #define _SPRA_SIZE 0x70290 3401 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 3402 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 3403 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 3404 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 3405 #define _SPRA_KEYVAL 0x70294 3406 #define _SPRA_KEYMSK 0x70298 3407 #define _SPRA_SURF 0x7029c 3408 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 3409 #define _SPRA_KEYMAX 0x702a0 3410 #define _SPRA_TILEOFF 0x702a4 3411 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 3412 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 3413 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 3414 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 3415 #define _SPRA_OFFSET 0x702a4 3416 #define _SPRA_SURFLIVE 0x702ac 3417 #define _SPRA_SCALE 0x70304 3418 #define SPRITE_SCALE_ENABLE REG_BIT(31) 3419 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 3420 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 3421 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 3422 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 3423 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 3424 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 3425 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 3426 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 3427 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 3428 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 3429 #define _SPRA_GAMC 0x70400 3430 #define _SPRA_GAMC16 0x70440 3431 #define _SPRA_GAMC17 0x7044c 3432 3433 #define _SPRB_CTL 0x71280 3434 #define _SPRB_LINOFF 0x71284 3435 #define _SPRB_STRIDE 0x71288 3436 #define _SPRB_POS 0x7128c 3437 #define _SPRB_SIZE 0x71290 3438 #define _SPRB_KEYVAL 0x71294 3439 #define _SPRB_KEYMSK 0x71298 3440 #define _SPRB_SURF 0x7129c 3441 #define _SPRB_KEYMAX 0x712a0 3442 #define _SPRB_TILEOFF 0x712a4 3443 #define _SPRB_OFFSET 0x712a4 3444 #define _SPRB_SURFLIVE 0x712ac 3445 #define _SPRB_SCALE 0x71304 3446 #define _SPRB_GAMC 0x71400 3447 #define _SPRB_GAMC16 0x71440 3448 #define _SPRB_GAMC17 0x7144c 3449 3450 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 3451 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 3452 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 3453 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 3454 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 3455 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 3456 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 3457 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 3458 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 3459 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 3460 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 3461 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 3462 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 3463 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 3464 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 3465 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 3466 3467 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 3468 #define SP_ENABLE REG_BIT(31) 3469 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 3470 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 3471 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 3472 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 3473 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 3474 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 3475 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 3476 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 3477 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 3478 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 3479 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 3480 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 3481 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 3482 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 3483 #define SP_SOURCE_KEY REG_BIT(22) 3484 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 3485 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 3486 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 3487 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 3488 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 3489 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 3490 #define SP_ROTATE_180 REG_BIT(15) 3491 #define SP_TILED REG_BIT(10) 3492 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 3493 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 3494 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 3495 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 3496 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 3497 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 3498 #define SP_POS_X_MASK REG_GENMASK(15, 0) 3499 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 3500 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 3501 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 3502 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 3503 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 3504 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 3505 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 3506 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 3507 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 3508 #define SP_ADDR_MASK REG_GENMASK(31, 12) 3509 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 3510 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 3511 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 3512 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 3513 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 3514 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 3515 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 3516 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 3517 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 3518 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 3519 #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) 3520 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 3521 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 3522 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 3523 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 3524 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 3525 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 3526 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 3527 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 3528 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 3529 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 3530 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 3531 3532 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 3533 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 3534 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 3535 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 3536 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 3537 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 3538 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 3539 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 3540 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 3541 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 3542 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 3543 #define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) 3544 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 3545 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 3546 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 3547 3548 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 3549 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 3550 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 3551 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 3552 3553 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 3554 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 3555 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 3556 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 3557 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 3558 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 3559 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 3560 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 3561 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 3562 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 3563 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 3564 #define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) 3565 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 3566 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 3567 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 3568 3569 /* 3570 * CHV pipe B sprite CSC 3571 * 3572 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 3573 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 3574 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 3575 */ 3576 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 3577 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 3578 3579 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 3580 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 3581 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 3582 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 3583 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 3584 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 3585 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 3586 3587 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 3588 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 3589 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 3590 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 3591 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 3592 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 3593 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 3594 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 3595 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 3596 3597 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 3598 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 3599 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 3600 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 3601 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 3602 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 3603 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 3604 3605 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 3606 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 3607 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 3608 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 3609 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 3610 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 3611 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 3612 3613 /* Skylake plane registers */ 3614 3615 #define _PLANE_CTL_1_A 0x70180 3616 #define _PLANE_CTL_2_A 0x70280 3617 #define _PLANE_CTL_3_A 0x70380 3618 #define PLANE_CTL_ENABLE REG_BIT(31) 3619 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 3620 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 3621 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 3622 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 3623 /* 3624 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 3625 * expanded to include bit 23 as well. However, the shift-24 based values 3626 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 3627 */ 3628 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 3629 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 3630 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 3631 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 3632 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 3633 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 3634 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 3635 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 3636 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 3637 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 3638 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 3639 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 3640 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 3641 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 3642 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 3643 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 3644 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 3645 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 3646 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 3647 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 3648 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 3649 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 3650 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 3651 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 3652 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 3653 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 3654 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 3655 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 3656 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 3657 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 3658 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 3659 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 3660 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 3661 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 3662 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 3663 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 3664 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 3665 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 3666 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 3667 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 3668 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 3669 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 3670 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 3671 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 3672 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 3673 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 3674 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 3675 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 3676 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 3677 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 3678 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 3679 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 3680 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 3681 #define _PLANE_STRIDE_1_A 0x70188 3682 #define _PLANE_STRIDE_2_A 0x70288 3683 #define _PLANE_STRIDE_3_A 0x70388 3684 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 3685 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 3686 #define _PLANE_POS_1_A 0x7018c 3687 #define _PLANE_POS_2_A 0x7028c 3688 #define _PLANE_POS_3_A 0x7038c 3689 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 3690 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 3691 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 3692 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 3693 #define _PLANE_SIZE_1_A 0x70190 3694 #define _PLANE_SIZE_2_A 0x70290 3695 #define _PLANE_SIZE_3_A 0x70390 3696 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 3697 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 3698 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 3699 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 3700 #define _PLANE_SURF_1_A 0x7019c 3701 #define _PLANE_SURF_2_A 0x7029c 3702 #define _PLANE_SURF_3_A 0x7039c 3703 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 3704 #define PLANE_SURF_DECRYPT REG_BIT(2) 3705 #define _PLANE_OFFSET_1_A 0x701a4 3706 #define _PLANE_OFFSET_2_A 0x702a4 3707 #define _PLANE_OFFSET_3_A 0x703a4 3708 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 3709 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 3710 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 3711 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 3712 #define _PLANE_KEYVAL_1_A 0x70194 3713 #define _PLANE_KEYVAL_2_A 0x70294 3714 #define _PLANE_KEYMSK_1_A 0x70198 3715 #define _PLANE_KEYMSK_2_A 0x70298 3716 #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) 3717 #define _PLANE_KEYMAX_1_A 0x701a0 3718 #define _PLANE_KEYMAX_2_A 0x702a0 3719 #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) 3720 #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) 3721 #define _PLANE_SURFLIVE_1_A 0x701ac 3722 #define _PLANE_SURFLIVE_2_A 0x702ac 3723 #define _PLANE_CC_VAL_1_A 0x701b4 3724 #define _PLANE_CC_VAL_2_A 0x702b4 3725 #define _PLANE_AUX_DIST_1_A 0x701c0 3726 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 3727 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 3728 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 3729 #define _PLANE_AUX_DIST_2_A 0x702c0 3730 #define _PLANE_AUX_OFFSET_1_A 0x701c4 3731 #define _PLANE_AUX_OFFSET_2_A 0x702c4 3732 #define _PLANE_CUS_CTL_1_A 0x701c8 3733 #define _PLANE_CUS_CTL_2_A 0x702c8 3734 #define PLANE_CUS_ENABLE REG_BIT(31) 3735 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 3736 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 3737 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 3738 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 3739 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 3740 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 3741 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 3742 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 3743 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 3744 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 3745 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 3746 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 3747 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 3748 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 3749 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 3750 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 3751 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 3752 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 3753 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 3754 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 3755 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 3756 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 3757 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 3758 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 3759 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 3760 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 3761 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 3762 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 3763 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 3764 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 3765 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 3766 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 3767 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 3768 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 3769 #define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ 3770 #define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ 3771 #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ 3772 #define _PLANE_BUF_CFG_1_A 0x7027c 3773 #define _PLANE_BUF_CFG_2_A 0x7037c 3774 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 3775 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 3776 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 3777 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 3778 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 3779 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 3780 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 3781 3782 #define _PLANE_CC_VAL_1_B 0x711b4 3783 #define _PLANE_CC_VAL_2_B 0x712b4 3784 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 3785 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 3786 #define PLANE_CC_VAL(pipe, plane, dw) \ 3787 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 3788 3789 /* Input CSC Register Definitions */ 3790 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 3791 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 3792 3793 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 3794 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 3795 3796 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 3797 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 3798 _PLANE_INPUT_CSC_RY_GY_1_B) 3799 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 3800 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 3801 _PLANE_INPUT_CSC_RY_GY_2_B) 3802 3803 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 3804 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 3805 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 3806 3807 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 3808 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 3809 3810 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 3811 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 3812 3813 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 3814 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 3815 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 3816 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 3817 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 3818 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 3819 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 3820 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 3821 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 3822 3823 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 3824 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 3825 3826 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 3827 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 3828 3829 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 3830 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 3831 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 3832 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 3833 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 3834 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 3835 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 3836 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 3837 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 3838 3839 #define _PLANE_CTL_1_B 0x71180 3840 #define _PLANE_CTL_2_B 0x71280 3841 #define _PLANE_CTL_3_B 0x71380 3842 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 3843 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 3844 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 3845 #define PLANE_CTL(pipe, plane) \ 3846 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 3847 3848 #define _PLANE_STRIDE_1_B 0x71188 3849 #define _PLANE_STRIDE_2_B 0x71288 3850 #define _PLANE_STRIDE_3_B 0x71388 3851 #define _PLANE_STRIDE_1(pipe) \ 3852 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 3853 #define _PLANE_STRIDE_2(pipe) \ 3854 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 3855 #define _PLANE_STRIDE_3(pipe) \ 3856 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 3857 #define PLANE_STRIDE(pipe, plane) \ 3858 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 3859 3860 #define _PLANE_POS_1_B 0x7118c 3861 #define _PLANE_POS_2_B 0x7128c 3862 #define _PLANE_POS_3_B 0x7138c 3863 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 3864 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 3865 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 3866 #define PLANE_POS(pipe, plane) \ 3867 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 3868 3869 #define _PLANE_SIZE_1_B 0x71190 3870 #define _PLANE_SIZE_2_B 0x71290 3871 #define _PLANE_SIZE_3_B 0x71390 3872 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 3873 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 3874 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 3875 #define PLANE_SIZE(pipe, plane) \ 3876 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 3877 3878 #define _PLANE_SURF_1_B 0x7119c 3879 #define _PLANE_SURF_2_B 0x7129c 3880 #define _PLANE_SURF_3_B 0x7139c 3881 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 3882 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 3883 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 3884 #define PLANE_SURF(pipe, plane) \ 3885 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 3886 3887 #define _PLANE_OFFSET_1_B 0x711a4 3888 #define _PLANE_OFFSET_2_B 0x712a4 3889 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 3890 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 3891 #define PLANE_OFFSET(pipe, plane) \ 3892 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 3893 3894 #define _PLANE_KEYVAL_1_B 0x71194 3895 #define _PLANE_KEYVAL_2_B 0x71294 3896 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 3897 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 3898 #define PLANE_KEYVAL(pipe, plane) \ 3899 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 3900 3901 #define _PLANE_KEYMSK_1_B 0x71198 3902 #define _PLANE_KEYMSK_2_B 0x71298 3903 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 3904 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 3905 #define PLANE_KEYMSK(pipe, plane) \ 3906 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 3907 3908 #define _PLANE_KEYMAX_1_B 0x711a0 3909 #define _PLANE_KEYMAX_2_B 0x712a0 3910 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 3911 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 3912 #define PLANE_KEYMAX(pipe, plane) \ 3913 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 3914 3915 #define _PLANE_SURFLIVE_1_B 0x711ac 3916 #define _PLANE_SURFLIVE_2_B 0x712ac 3917 #define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) 3918 #define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) 3919 #define PLANE_SURFLIVE(pipe, plane) \ 3920 _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) 3921 3922 #define _PLANE_CHICKEN_1_B 0x7126c 3923 #define _PLANE_CHICKEN_2_B 0x7136c 3924 #define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) 3925 #define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) 3926 #define PLANE_CHICKEN(pipe, plane) \ 3927 _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) 3928 3929 #define _PLANE_AUX_DIST_1_B 0x711c0 3930 #define _PLANE_AUX_DIST_2_B 0x712c0 3931 #define _PLANE_AUX_DIST_1(pipe) \ 3932 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 3933 #define _PLANE_AUX_DIST_2(pipe) \ 3934 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 3935 #define PLANE_AUX_DIST(pipe, plane) \ 3936 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 3937 3938 #define _PLANE_AUX_OFFSET_1_B 0x711c4 3939 #define _PLANE_AUX_OFFSET_2_B 0x712c4 3940 #define _PLANE_AUX_OFFSET_1(pipe) \ 3941 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 3942 #define _PLANE_AUX_OFFSET_2(pipe) \ 3943 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 3944 #define PLANE_AUX_OFFSET(pipe, plane) \ 3945 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 3946 3947 #define _PLANE_CUS_CTL_1_B 0x711c8 3948 #define _PLANE_CUS_CTL_2_B 0x712c8 3949 #define _PLANE_CUS_CTL_1(pipe) \ 3950 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 3951 #define _PLANE_CUS_CTL_2(pipe) \ 3952 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 3953 #define PLANE_CUS_CTL(pipe, plane) \ 3954 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 3955 3956 #define _PLANE_COLOR_CTL_1_B 0x711CC 3957 #define _PLANE_COLOR_CTL_2_B 0x712CC 3958 #define _PLANE_COLOR_CTL_3_B 0x713CC 3959 #define _PLANE_COLOR_CTL_1(pipe) \ 3960 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 3961 #define _PLANE_COLOR_CTL_2(pipe) \ 3962 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 3963 #define PLANE_COLOR_CTL(pipe, plane) \ 3964 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 3965 3966 /* VBIOS regs */ 3967 #define VGACNTRL _MMIO(0x71400) 3968 # define VGA_DISP_DISABLE (1 << 31) 3969 # define VGA_2X_MODE (1 << 30) 3970 # define VGA_PIPE_B_SELECT (1 << 29) 3971 3972 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 3973 3974 /* Ironlake */ 3975 3976 #define CPU_VGACNTRL _MMIO(0x41000) 3977 3978 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 3979 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 3980 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 3981 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 3982 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 3983 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 3984 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 3985 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 3986 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 3987 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 3988 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 3989 3990 /* refresh rate hardware control */ 3991 #define RR_HW_CTL _MMIO(0x45300) 3992 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 3993 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 3994 3995 #define PCH_3DCGDIS0 _MMIO(0x46020) 3996 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 3997 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 3998 3999 #define PCH_3DCGDIS1 _MMIO(0x46024) 4000 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 4001 4002 #define _PIPEA_DATA_M1 0x60030 4003 #define _PIPEA_DATA_N1 0x60034 4004 #define _PIPEA_DATA_M2 0x60038 4005 #define _PIPEA_DATA_N2 0x6003c 4006 #define _PIPEA_LINK_M1 0x60040 4007 #define _PIPEA_LINK_N1 0x60044 4008 #define _PIPEA_LINK_M2 0x60048 4009 #define _PIPEA_LINK_N2 0x6004c 4010 4011 /* PIPEB timing regs are same start from 0x61000 */ 4012 4013 #define _PIPEB_DATA_M1 0x61030 4014 #define _PIPEB_DATA_N1 0x61034 4015 #define _PIPEB_DATA_M2 0x61038 4016 #define _PIPEB_DATA_N2 0x6103c 4017 #define _PIPEB_LINK_M1 0x61040 4018 #define _PIPEB_LINK_N1 0x61044 4019 #define _PIPEB_LINK_M2 0x61048 4020 #define _PIPEB_LINK_N2 0x6104c 4021 4022 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 4023 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 4024 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 4025 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 4026 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 4027 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 4028 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 4029 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 4030 4031 /* CPU panel fitter */ 4032 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 4033 #define _PFA_CTL_1 0x68080 4034 #define _PFB_CTL_1 0x68880 4035 #define PF_ENABLE (1 << 31) 4036 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 4037 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 4038 #define PF_FILTER_MASK (3 << 23) 4039 #define PF_FILTER_PROGRAMMED (0 << 23) 4040 #define PF_FILTER_MED_3x3 (1 << 23) 4041 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 4042 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 4043 #define _PFA_WIN_SZ 0x68074 4044 #define _PFB_WIN_SZ 0x68874 4045 #define _PFA_WIN_POS 0x68070 4046 #define _PFB_WIN_POS 0x68870 4047 #define _PFA_VSCALE 0x68084 4048 #define _PFB_VSCALE 0x68884 4049 #define _PFA_HSCALE 0x68090 4050 #define _PFB_HSCALE 0x68890 4051 4052 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 4053 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 4054 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 4055 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 4056 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 4057 4058 #define _PSA_CTL 0x68180 4059 #define _PSB_CTL 0x68980 4060 #define PS_ENABLE (1 << 31) 4061 #define _PSA_WIN_SZ 0x68174 4062 #define _PSB_WIN_SZ 0x68974 4063 #define _PSA_WIN_POS 0x68170 4064 #define _PSB_WIN_POS 0x68970 4065 4066 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 4067 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 4068 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 4069 4070 /* 4071 * Skylake scalers 4072 */ 4073 #define _PS_1A_CTRL 0x68180 4074 #define _PS_2A_CTRL 0x68280 4075 #define _PS_1B_CTRL 0x68980 4076 #define _PS_2B_CTRL 0x68A80 4077 #define _PS_1C_CTRL 0x69180 4078 #define PS_SCALER_EN (1 << 31) 4079 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 4080 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 4081 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 4082 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 4083 #define PS_SCALER_MODE_PLANAR (1 << 29) 4084 #define PS_SCALER_MODE_NORMAL (0 << 29) 4085 #define PS_PLANE_SEL_MASK (7 << 25) 4086 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 4087 #define PS_FILTER_MASK (3 << 23) 4088 #define PS_FILTER_MEDIUM (0 << 23) 4089 #define PS_FILTER_PROGRAMMED (1 << 23) 4090 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 4091 #define PS_FILTER_BILINEAR (3 << 23) 4092 #define PS_VERT3TAP (1 << 21) 4093 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 4094 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 4095 #define PS_PWRUP_PROGRESS (1 << 17) 4096 #define PS_V_FILTER_BYPASS (1 << 8) 4097 #define PS_VADAPT_EN (1 << 7) 4098 #define PS_VADAPT_MODE_MASK (3 << 5) 4099 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 4100 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 4101 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 4102 #define PS_PLANE_Y_SEL_MASK (7 << 5) 4103 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 4104 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 4105 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 4106 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 4107 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 4108 4109 #define _PS_PWR_GATE_1A 0x68160 4110 #define _PS_PWR_GATE_2A 0x68260 4111 #define _PS_PWR_GATE_1B 0x68960 4112 #define _PS_PWR_GATE_2B 0x68A60 4113 #define _PS_PWR_GATE_1C 0x69160 4114 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 4115 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 4116 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 4117 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 4118 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 4119 #define PS_PWR_GATE_SLPEN_8 0 4120 #define PS_PWR_GATE_SLPEN_16 1 4121 #define PS_PWR_GATE_SLPEN_24 2 4122 #define PS_PWR_GATE_SLPEN_32 3 4123 4124 #define _PS_WIN_POS_1A 0x68170 4125 #define _PS_WIN_POS_2A 0x68270 4126 #define _PS_WIN_POS_1B 0x68970 4127 #define _PS_WIN_POS_2B 0x68A70 4128 #define _PS_WIN_POS_1C 0x69170 4129 4130 #define _PS_WIN_SZ_1A 0x68174 4131 #define _PS_WIN_SZ_2A 0x68274 4132 #define _PS_WIN_SZ_1B 0x68974 4133 #define _PS_WIN_SZ_2B 0x68A74 4134 #define _PS_WIN_SZ_1C 0x69174 4135 4136 #define _PS_VSCALE_1A 0x68184 4137 #define _PS_VSCALE_2A 0x68284 4138 #define _PS_VSCALE_1B 0x68984 4139 #define _PS_VSCALE_2B 0x68A84 4140 #define _PS_VSCALE_1C 0x69184 4141 4142 #define _PS_HSCALE_1A 0x68190 4143 #define _PS_HSCALE_2A 0x68290 4144 #define _PS_HSCALE_1B 0x68990 4145 #define _PS_HSCALE_2B 0x68A90 4146 #define _PS_HSCALE_1C 0x69190 4147 4148 #define _PS_VPHASE_1A 0x68188 4149 #define _PS_VPHASE_2A 0x68288 4150 #define _PS_VPHASE_1B 0x68988 4151 #define _PS_VPHASE_2B 0x68A88 4152 #define _PS_VPHASE_1C 0x69188 4153 #define PS_Y_PHASE(x) ((x) << 16) 4154 #define PS_UV_RGB_PHASE(x) ((x) << 0) 4155 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 4156 #define PS_PHASE_TRIP (1 << 0) 4157 4158 #define _PS_HPHASE_1A 0x68194 4159 #define _PS_HPHASE_2A 0x68294 4160 #define _PS_HPHASE_1B 0x68994 4161 #define _PS_HPHASE_2B 0x68A94 4162 #define _PS_HPHASE_1C 0x69194 4163 4164 #define _PS_ECC_STAT_1A 0x681D0 4165 #define _PS_ECC_STAT_2A 0x682D0 4166 #define _PS_ECC_STAT_1B 0x689D0 4167 #define _PS_ECC_STAT_2B 0x68AD0 4168 #define _PS_ECC_STAT_1C 0x691D0 4169 4170 #define _PS_COEF_SET0_INDEX_1A 0x68198 4171 #define _PS_COEF_SET0_INDEX_2A 0x68298 4172 #define _PS_COEF_SET0_INDEX_1B 0x68998 4173 #define _PS_COEF_SET0_INDEX_2B 0x68A98 4174 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 4175 4176 #define _PS_COEF_SET0_DATA_1A 0x6819C 4177 #define _PS_COEF_SET0_DATA_2A 0x6829C 4178 #define _PS_COEF_SET0_DATA_1B 0x6899C 4179 #define _PS_COEF_SET0_DATA_2B 0x68A9C 4180 4181 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 4182 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 4183 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 4184 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 4185 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 4186 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 4187 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 4188 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 4189 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 4190 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 4191 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 4192 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 4193 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 4194 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 4195 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 4196 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 4197 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 4198 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 4199 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 4200 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 4201 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 4202 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 4203 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 4204 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 4205 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 4206 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 4207 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 4208 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 4209 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 4210 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 4211 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 4212 4213 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 4214 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 4215 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 4216 /* legacy palette */ 4217 #define _LGC_PALETTE_A 0x4a000 4218 #define _LGC_PALETTE_B 0x4a800 4219 /* see PALETTE_* for the bits */ 4220 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 4221 4222 /* ilk/snb precision palette */ 4223 #define _PREC_PALETTE_A 0x4b000 4224 #define _PREC_PALETTE_B 0x4c000 4225 /* 10bit mode */ 4226 #define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20) 4227 #define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10) 4228 #define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0) 4229 /* 12.4 interpolated mode ldw */ 4230 #define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24) 4231 #define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14) 4232 #define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4) 4233 /* 12.4 interpolated mode udw */ 4234 #define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20) 4235 #define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10) 4236 #define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0) 4237 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 4238 4239 #define _PREC_PIPEAGCMAX 0x4d000 4240 #define _PREC_PIPEBGCMAX 0x4d010 4241 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ 4242 4243 #define _GAMMA_MODE_A 0x4a480 4244 #define _GAMMA_MODE_B 0x4ac80 4245 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 4246 #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ 4247 #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ 4248 #define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */ 4249 #define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) 4250 #define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) 4251 #define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) 4252 #define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2) 4253 #define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ 4254 #define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ 4255 4256 /* Display Internal Timeout Register */ 4257 #define RM_TIMEOUT _MMIO(0x42060) 4258 #define MMIO_TIMEOUT_US(us) ((us) << 0) 4259 4260 /* interrupts */ 4261 #define DE_MASTER_IRQ_CONTROL (1 << 31) 4262 #define DE_SPRITEB_FLIP_DONE (1 << 29) 4263 #define DE_SPRITEA_FLIP_DONE (1 << 28) 4264 #define DE_PLANEB_FLIP_DONE (1 << 27) 4265 #define DE_PLANEA_FLIP_DONE (1 << 26) 4266 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 4267 #define DE_PCU_EVENT (1 << 25) 4268 #define DE_GTT_FAULT (1 << 24) 4269 #define DE_POISON (1 << 23) 4270 #define DE_PERFORM_COUNTER (1 << 22) 4271 #define DE_PCH_EVENT (1 << 21) 4272 #define DE_AUX_CHANNEL_A (1 << 20) 4273 #define DE_DP_A_HOTPLUG (1 << 19) 4274 #define DE_GSE (1 << 18) 4275 #define DE_PIPEB_VBLANK (1 << 15) 4276 #define DE_PIPEB_EVEN_FIELD (1 << 14) 4277 #define DE_PIPEB_ODD_FIELD (1 << 13) 4278 #define DE_PIPEB_LINE_COMPARE (1 << 12) 4279 #define DE_PIPEB_VSYNC (1 << 11) 4280 #define DE_PIPEB_CRC_DONE (1 << 10) 4281 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 4282 #define DE_PIPEA_VBLANK (1 << 7) 4283 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 4284 #define DE_PIPEA_EVEN_FIELD (1 << 6) 4285 #define DE_PIPEA_ODD_FIELD (1 << 5) 4286 #define DE_PIPEA_LINE_COMPARE (1 << 4) 4287 #define DE_PIPEA_VSYNC (1 << 3) 4288 #define DE_PIPEA_CRC_DONE (1 << 2) 4289 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 4290 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 4291 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 4292 4293 /* More Ivybridge lolz */ 4294 #define DE_ERR_INT_IVB (1 << 30) 4295 #define DE_GSE_IVB (1 << 29) 4296 #define DE_PCH_EVENT_IVB (1 << 28) 4297 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 4298 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 4299 #define DE_EDP_PSR_INT_HSW (1 << 19) 4300 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 4301 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 4302 #define DE_PIPEC_VBLANK_IVB (1 << 10) 4303 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 4304 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 4305 #define DE_PIPEB_VBLANK_IVB (1 << 5) 4306 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 4307 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 4308 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 4309 #define DE_PIPEA_VBLANK_IVB (1 << 0) 4310 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 4311 4312 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 4313 #define MASTER_INTERRUPT_ENABLE (1 << 31) 4314 4315 #define DEISR _MMIO(0x44000) 4316 #define DEIMR _MMIO(0x44004) 4317 #define DEIIR _MMIO(0x44008) 4318 #define DEIER _MMIO(0x4400c) 4319 4320 #define GTISR _MMIO(0x44010) 4321 #define GTIMR _MMIO(0x44014) 4322 #define GTIIR _MMIO(0x44018) 4323 #define GTIER _MMIO(0x4401c) 4324 4325 #define GEN8_MASTER_IRQ _MMIO(0x44200) 4326 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 4327 #define GEN8_PCU_IRQ (1 << 30) 4328 #define GEN8_DE_PCH_IRQ (1 << 23) 4329 #define GEN8_DE_MISC_IRQ (1 << 22) 4330 #define GEN8_DE_PORT_IRQ (1 << 20) 4331 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 4332 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 4333 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 4334 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 4335 #define GEN8_GT_VECS_IRQ (1 << 6) 4336 #define GEN8_GT_GUC_IRQ (1 << 5) 4337 #define GEN8_GT_PM_IRQ (1 << 4) 4338 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 4339 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 4340 #define GEN8_GT_BCS_IRQ (1 << 1) 4341 #define GEN8_GT_RCS_IRQ (1 << 0) 4342 4343 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 4344 4345 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 4346 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 4347 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 4348 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 4349 4350 #define GEN8_RCS_IRQ_SHIFT 0 4351 #define GEN8_BCS_IRQ_SHIFT 16 4352 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 4353 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 4354 #define GEN8_VECS_IRQ_SHIFT 0 4355 #define GEN8_WD_IRQ_SHIFT 16 4356 4357 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 4358 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 4359 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 4360 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 4361 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 4362 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 4363 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 4364 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 4365 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 4366 #define GEN12_PIPE_VBLANK_UNMOD (1 << 19) 4367 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 4368 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 4369 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 4370 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 4371 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 4372 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 4373 #define GEN8_PIPE_VSYNC (1 << 1) 4374 #define GEN8_PIPE_VBLANK (1 << 0) 4375 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 4376 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 4377 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 4378 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 4379 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 4380 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 4381 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 4382 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 4383 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 4384 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 4385 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 4386 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 4387 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 4388 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 4389 (GEN8_PIPE_CURSOR_FAULT | \ 4390 GEN8_PIPE_SPRITE_FAULT | \ 4391 GEN8_PIPE_PRIMARY_FAULT) 4392 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 4393 (GEN9_PIPE_CURSOR_FAULT | \ 4394 GEN9_PIPE_PLANE4_FAULT | \ 4395 GEN9_PIPE_PLANE3_FAULT | \ 4396 GEN9_PIPE_PLANE2_FAULT | \ 4397 GEN9_PIPE_PLANE1_FAULT) 4398 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 4399 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 4400 GEN11_PIPE_PLANE7_FAULT | \ 4401 GEN11_PIPE_PLANE6_FAULT | \ 4402 GEN11_PIPE_PLANE5_FAULT) 4403 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 4404 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 4405 GEN11_PIPE_PLANE5_FAULT) 4406 4407 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 4408 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 4409 4410 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 4411 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 4412 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 4413 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 4414 #define DSI1_NON_TE (1 << 31) 4415 #define DSI0_NON_TE (1 << 30) 4416 #define ICL_AUX_CHANNEL_E (1 << 29) 4417 #define ICL_AUX_CHANNEL_F (1 << 28) 4418 #define GEN9_AUX_CHANNEL_D (1 << 27) 4419 #define GEN9_AUX_CHANNEL_C (1 << 26) 4420 #define GEN9_AUX_CHANNEL_B (1 << 25) 4421 #define DSI1_TE (1 << 24) 4422 #define DSI0_TE (1 << 23) 4423 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 4424 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 4425 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 4426 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 4427 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 4428 #define BXT_DE_PORT_GMBUS (1 << 1) 4429 #define GEN8_AUX_CHANNEL_A (1 << 0) 4430 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 4431 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 4432 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 4433 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 4434 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 4435 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 4436 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 4437 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 4438 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 4439 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 4440 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 4441 4442 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 4443 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 4444 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 4445 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 4446 #define GEN8_DE_MISC_GSE (1 << 27) 4447 #define GEN8_DE_EDP_PSR (1 << 19) 4448 4449 #define GEN8_PCU_ISR _MMIO(0x444e0) 4450 #define GEN8_PCU_IMR _MMIO(0x444e4) 4451 #define GEN8_PCU_IIR _MMIO(0x444e8) 4452 #define GEN8_PCU_IER _MMIO(0x444ec) 4453 4454 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 4455 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 4456 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 4457 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 4458 #define GEN11_GU_MISC_GSE (1 << 27) 4459 4460 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 4461 #define GEN11_MASTER_IRQ (1 << 31) 4462 #define GEN11_PCU_IRQ (1 << 30) 4463 #define GEN11_GU_MISC_IRQ (1 << 29) 4464 #define GEN11_DISPLAY_IRQ (1 << 16) 4465 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 4466 #define GEN11_GT_DW1_IRQ (1 << 1) 4467 #define GEN11_GT_DW0_IRQ (1 << 0) 4468 4469 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 4470 #define DG1_MSTR_IRQ REG_BIT(31) 4471 #define DG1_MSTR_TILE(t) REG_BIT(t) 4472 4473 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 4474 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 4475 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 4476 #define GEN11_DE_PCH_IRQ (1 << 23) 4477 #define GEN11_DE_MISC_IRQ (1 << 22) 4478 #define GEN11_DE_HPD_IRQ (1 << 21) 4479 #define GEN11_DE_PORT_IRQ (1 << 20) 4480 #define GEN11_DE_PIPE_C (1 << 18) 4481 #define GEN11_DE_PIPE_B (1 << 17) 4482 #define GEN11_DE_PIPE_A (1 << 16) 4483 4484 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 4485 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 4486 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 4487 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 4488 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 4489 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 4490 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 4491 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 4492 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 4493 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 4494 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 4495 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 4496 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 4497 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 4498 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 4499 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 4500 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 4501 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 4502 4503 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 4504 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 4505 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 4506 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 4507 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 4508 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 4509 4510 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 4511 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 4512 #define ILK_ELPIN_409_SELECT (1 << 25) 4513 #define ILK_DPARB_GATE (1 << 22) 4514 #define ILK_VSDPFD_FULL (1 << 21) 4515 #define FUSE_STRAP _MMIO(0x42014) 4516 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 4517 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 4518 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 4519 #define IVB_PIPE_C_DISABLE (1 << 28) 4520 #define ILK_HDCP_DISABLE (1 << 25) 4521 #define ILK_eDP_A_DISABLE (1 << 24) 4522 #define HSW_CDCLK_LIMIT (1 << 24) 4523 #define ILK_DESKTOP (1 << 23) 4524 #define HSW_CPU_SSC_ENABLE (1 << 21) 4525 4526 #define FUSE_STRAP3 _MMIO(0x42020) 4527 #define HSW_REF_CLK_SELECT (1 << 1) 4528 4529 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 4530 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 4531 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 4532 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 4533 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 4534 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 4535 4536 #define IVB_CHICKEN3 _MMIO(0x4200c) 4537 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 4538 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 4539 4540 #define CHICKEN_PAR1_1 _MMIO(0x42080) 4541 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 4542 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 4543 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 4544 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 4545 #define DPA_MASK_VBLANK_SRD (1 << 15) 4546 #define FORCE_ARB_IDLE_PLANES (1 << 14) 4547 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 4548 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 4549 4550 #define CHICKEN_PAR2_1 _MMIO(0x42090) 4551 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 4552 4553 #define CHICKEN_MISC_2 _MMIO(0x42084) 4554 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ 4555 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 4556 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 4557 #define GLK_CL2_PWR_DOWN (1 << 12) 4558 #define GLK_CL1_PWR_DOWN (1 << 11) 4559 #define GLK_CL0_PWR_DOWN (1 << 10) 4560 4561 #define CHICKEN_MISC_4 _MMIO(0x4208c) 4562 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 4563 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 4564 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 4565 4566 #define _CHICKEN_PIPESL_1_A 0x420b0 4567 #define _CHICKEN_PIPESL_1_B 0x420b4 4568 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 4569 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 4570 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 4571 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 4572 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 4573 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 4574 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 4575 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 4576 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 4577 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 4578 #define HSW_FBCQ_DIS (1 << 22) 4579 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 4580 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 4581 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 4582 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 4583 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 4584 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 4585 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 4586 4587 #define _CHICKEN_TRANS_A 0x420c0 4588 #define _CHICKEN_TRANS_B 0x420c4 4589 #define _CHICKEN_TRANS_C 0x420c8 4590 #define _CHICKEN_TRANS_EDP 0x420cc 4591 #define _CHICKEN_TRANS_D 0x420d8 4592 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 4593 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 4594 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 4595 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 4596 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 4597 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 4598 4599 #define _MTL_CHICKEN_TRANS_A 0x604e0 4600 #define _MTL_CHICKEN_TRANS_B 0x614e0 4601 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 4602 _MTL_CHICKEN_TRANS_A, \ 4603 _MTL_CHICKEN_TRANS_B) 4604 4605 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 4606 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 4607 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 4608 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 4609 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 4610 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 4611 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 4612 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 4613 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 4614 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 4615 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 4616 4617 #define DISP_ARB_CTL _MMIO(0x45000) 4618 #define DISP_FBC_MEMORY_WAKE (1 << 31) 4619 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 4620 #define DISP_FBC_WM_DIS (1 << 15) 4621 #define DISP_ARB_CTL2 _MMIO(0x45004) 4622 #define DISP_DATA_PARTITION_5_6 (1 << 6) 4623 #define DISP_IPC_ENABLE (1 << 3) 4624 4625 #define GEN7_MSG_CTL _MMIO(0x45010) 4626 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 4627 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 4628 4629 #define _BW_BUDDY0_CTL 0x45130 4630 #define _BW_BUDDY1_CTL 0x45140 4631 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 4632 _BW_BUDDY0_CTL, \ 4633 _BW_BUDDY1_CTL)) 4634 #define BW_BUDDY_DISABLE REG_BIT(31) 4635 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 4636 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 4637 4638 #define _BW_BUDDY0_PAGE_MASK 0x45134 4639 #define _BW_BUDDY1_PAGE_MASK 0x45144 4640 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 4641 _BW_BUDDY0_PAGE_MASK, \ 4642 _BW_BUDDY1_PAGE_MASK)) 4643 4644 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 4645 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 4646 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 4647 4648 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 4649 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 4650 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 4651 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 4652 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 4653 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 4654 #define ICL_DELAY_PMRSP REG_BIT(22) 4655 #define DISABLE_FLR_SRC REG_BIT(15) 4656 #define MASK_WAKEMEM REG_BIT(13) 4657 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 4658 4659 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 4660 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 4661 #define DCPR_MASK_LPMODE REG_BIT(26) 4662 #define DCPR_SEND_RESP_IMM REG_BIT(25) 4663 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 4664 4665 #define SKL_DFSM _MMIO(0x51000) 4666 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 4667 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 4668 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 4669 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 4670 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 4671 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 4672 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 4673 #define ICL_DFSM_DMC_DISABLE (1 << 23) 4674 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 4675 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 4676 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 4677 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 4678 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 4679 4680 #define SKL_DSSM _MMIO(0x51004) 4681 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 4682 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 4683 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 4684 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 4685 4686 #define GMD_ID_DISPLAY _MMIO(0x510a0) 4687 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 4688 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 4689 #define GMD_ID_STEP REG_GENMASK(5, 0) 4690 4691 /*GEN11 chicken */ 4692 #define _PIPEA_CHICKEN 0x70038 4693 #define _PIPEB_CHICKEN 0x71038 4694 #define _PIPEC_CHICKEN 0x72038 4695 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 4696 _PIPEB_CHICKEN) 4697 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 4698 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 4699 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 4700 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 4701 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 4702 4703 /* PCH */ 4704 4705 #define PCH_DISPLAY_BASE 0xc0000u 4706 4707 /* south display engine interrupt: IBX */ 4708 #define SDE_AUDIO_POWER_D (1 << 27) 4709 #define SDE_AUDIO_POWER_C (1 << 26) 4710 #define SDE_AUDIO_POWER_B (1 << 25) 4711 #define SDE_AUDIO_POWER_SHIFT (25) 4712 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 4713 #define SDE_GMBUS (1 << 24) 4714 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 4715 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 4716 #define SDE_AUDIO_HDCP_MASK (3 << 22) 4717 #define SDE_AUDIO_TRANSB (1 << 21) 4718 #define SDE_AUDIO_TRANSA (1 << 20) 4719 #define SDE_AUDIO_TRANS_MASK (3 << 20) 4720 #define SDE_POISON (1 << 19) 4721 /* 18 reserved */ 4722 #define SDE_FDI_RXB (1 << 17) 4723 #define SDE_FDI_RXA (1 << 16) 4724 #define SDE_FDI_MASK (3 << 16) 4725 #define SDE_AUXD (1 << 15) 4726 #define SDE_AUXC (1 << 14) 4727 #define SDE_AUXB (1 << 13) 4728 #define SDE_AUX_MASK (7 << 13) 4729 /* 12 reserved */ 4730 #define SDE_CRT_HOTPLUG (1 << 11) 4731 #define SDE_PORTD_HOTPLUG (1 << 10) 4732 #define SDE_PORTC_HOTPLUG (1 << 9) 4733 #define SDE_PORTB_HOTPLUG (1 << 8) 4734 #define SDE_SDVOB_HOTPLUG (1 << 6) 4735 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 4736 SDE_SDVOB_HOTPLUG | \ 4737 SDE_PORTB_HOTPLUG | \ 4738 SDE_PORTC_HOTPLUG | \ 4739 SDE_PORTD_HOTPLUG) 4740 #define SDE_TRANSB_CRC_DONE (1 << 5) 4741 #define SDE_TRANSB_CRC_ERR (1 << 4) 4742 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 4743 #define SDE_TRANSA_CRC_DONE (1 << 2) 4744 #define SDE_TRANSA_CRC_ERR (1 << 1) 4745 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 4746 #define SDE_TRANS_MASK (0x3f) 4747 4748 /* south display engine interrupt: CPT - CNP */ 4749 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 4750 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 4751 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 4752 #define SDE_AUDIO_POWER_SHIFT_CPT 29 4753 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 4754 #define SDE_AUXD_CPT (1 << 27) 4755 #define SDE_AUXC_CPT (1 << 26) 4756 #define SDE_AUXB_CPT (1 << 25) 4757 #define SDE_AUX_MASK_CPT (7 << 25) 4758 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 4759 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 4760 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 4761 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 4762 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 4763 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 4764 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 4765 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 4766 SDE_SDVOB_HOTPLUG_CPT | \ 4767 SDE_PORTD_HOTPLUG_CPT | \ 4768 SDE_PORTC_HOTPLUG_CPT | \ 4769 SDE_PORTB_HOTPLUG_CPT) 4770 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 4771 SDE_PORTD_HOTPLUG_CPT | \ 4772 SDE_PORTC_HOTPLUG_CPT | \ 4773 SDE_PORTB_HOTPLUG_CPT | \ 4774 SDE_PORTA_HOTPLUG_SPT) 4775 #define SDE_GMBUS_CPT (1 << 17) 4776 #define SDE_ERROR_CPT (1 << 16) 4777 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 4778 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 4779 #define SDE_FDI_RXC_CPT (1 << 8) 4780 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 4781 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 4782 #define SDE_FDI_RXB_CPT (1 << 4) 4783 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 4784 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 4785 #define SDE_FDI_RXA_CPT (1 << 0) 4786 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 4787 SDE_AUDIO_CP_REQ_B_CPT | \ 4788 SDE_AUDIO_CP_REQ_A_CPT) 4789 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 4790 SDE_AUDIO_CP_CHG_B_CPT | \ 4791 SDE_AUDIO_CP_CHG_A_CPT) 4792 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 4793 SDE_FDI_RXB_CPT | \ 4794 SDE_FDI_RXA_CPT) 4795 4796 /* south display engine interrupt: ICP/TGP */ 4797 #define SDE_GMBUS_ICP (1 << 23) 4798 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 4799 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 4800 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 4801 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 4802 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 4803 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 4804 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 4805 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 4806 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 4807 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 4808 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 4809 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 4810 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 4811 4812 #define SDEISR _MMIO(0xc4000) 4813 #define SDEIMR _MMIO(0xc4004) 4814 #define SDEIIR _MMIO(0xc4008) 4815 #define SDEIER _MMIO(0xc400c) 4816 4817 #define SERR_INT _MMIO(0xc4040) 4818 #define SERR_INT_POISON (1 << 31) 4819 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 4820 4821 /* digital port hotplug */ 4822 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 4823 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 4824 #define BXT_DDIA_HPD_INVERT (1 << 27) 4825 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 4826 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 4827 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 4828 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 4829 #define PORTD_HOTPLUG_ENABLE (1 << 20) 4830 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 4831 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 4832 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 4833 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 4834 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 4835 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 4836 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 4837 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 4838 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 4839 #define PORTC_HOTPLUG_ENABLE (1 << 12) 4840 #define BXT_DDIC_HPD_INVERT (1 << 11) 4841 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 4842 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 4843 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 4844 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 4845 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 4846 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 4847 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 4848 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 4849 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 4850 #define PORTB_HOTPLUG_ENABLE (1 << 4) 4851 #define BXT_DDIB_HPD_INVERT (1 << 3) 4852 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 4853 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 4854 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 4855 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 4856 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 4857 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 4858 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 4859 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 4860 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 4861 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 4862 BXT_DDIB_HPD_INVERT | \ 4863 BXT_DDIC_HPD_INVERT) 4864 4865 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 4866 #define PORTE_HOTPLUG_ENABLE (1 << 4) 4867 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 4868 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 4869 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 4870 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 4871 4872 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 4873 * functionality covered in PCH_PORT_HOTPLUG is split into 4874 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 4875 */ 4876 4877 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 4878 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4879 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4880 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4881 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4882 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4883 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4884 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 4885 4886 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 4887 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 4888 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 4889 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 4890 4891 #define SHPD_FILTER_CNT _MMIO(0xc4038) 4892 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 4893 4894 #define _PCH_DPLL_A 0xc6014 4895 #define _PCH_DPLL_B 0xc6018 4896 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 4897 4898 #define _PCH_FPA0 0xc6040 4899 #define FP_CB_TUNE (0x3 << 22) 4900 #define _PCH_FPA1 0xc6044 4901 #define _PCH_FPB0 0xc6048 4902 #define _PCH_FPB1 0xc604c 4903 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 4904 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 4905 4906 #define PCH_DPLL_TEST _MMIO(0xc606c) 4907 4908 #define PCH_DREF_CONTROL _MMIO(0xC6200) 4909 #define DREF_CONTROL_MASK 0x7fc3 4910 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 4911 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 4912 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 4913 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 4914 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 4915 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 4916 #define DREF_SSC_SOURCE_MASK (3 << 11) 4917 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 4918 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 4919 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 4920 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 4921 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 4922 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 4923 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 4924 #define DREF_SSC4_DOWNSPREAD (0 << 6) 4925 #define DREF_SSC4_CENTERSPREAD (1 << 6) 4926 #define DREF_SSC1_DISABLE (0 << 1) 4927 #define DREF_SSC1_ENABLE (1 << 1) 4928 #define DREF_SSC4_DISABLE (0) 4929 #define DREF_SSC4_ENABLE (1) 4930 4931 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 4932 #define FDL_TP1_TIMER_SHIFT 12 4933 #define FDL_TP1_TIMER_MASK (3 << 12) 4934 #define FDL_TP2_TIMER_SHIFT 10 4935 #define FDL_TP2_TIMER_MASK (3 << 10) 4936 #define RAWCLK_FREQ_MASK 0x3ff 4937 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 4938 #define CNP_RAWCLK_DIV(div) ((div) << 16) 4939 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 4940 #define CNP_RAWCLK_DEN(den) ((den) << 26) 4941 #define ICP_RAWCLK_NUM(num) ((num) << 11) 4942 4943 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 4944 4945 #define PCH_SSC4_PARMS _MMIO(0xc6210) 4946 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 4947 4948 #define PCH_DPLL_SEL _MMIO(0xc7000) 4949 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 4950 #define TRANS_DPLLA_SEL(pipe) 0 4951 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 4952 4953 /* transcoder */ 4954 4955 #define _PCH_TRANS_HTOTAL_A 0xe0000 4956 #define TRANS_HTOTAL_SHIFT 16 4957 #define TRANS_HACTIVE_SHIFT 0 4958 #define _PCH_TRANS_HBLANK_A 0xe0004 4959 #define TRANS_HBLANK_END_SHIFT 16 4960 #define TRANS_HBLANK_START_SHIFT 0 4961 #define _PCH_TRANS_HSYNC_A 0xe0008 4962 #define TRANS_HSYNC_END_SHIFT 16 4963 #define TRANS_HSYNC_START_SHIFT 0 4964 #define _PCH_TRANS_VTOTAL_A 0xe000c 4965 #define TRANS_VTOTAL_SHIFT 16 4966 #define TRANS_VACTIVE_SHIFT 0 4967 #define _PCH_TRANS_VBLANK_A 0xe0010 4968 #define TRANS_VBLANK_END_SHIFT 16 4969 #define TRANS_VBLANK_START_SHIFT 0 4970 #define _PCH_TRANS_VSYNC_A 0xe0014 4971 #define TRANS_VSYNC_END_SHIFT 16 4972 #define TRANS_VSYNC_START_SHIFT 0 4973 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 4974 4975 #define _PCH_TRANSA_DATA_M1 0xe0030 4976 #define _PCH_TRANSA_DATA_N1 0xe0034 4977 #define _PCH_TRANSA_DATA_M2 0xe0038 4978 #define _PCH_TRANSA_DATA_N2 0xe003c 4979 #define _PCH_TRANSA_LINK_M1 0xe0040 4980 #define _PCH_TRANSA_LINK_N1 0xe0044 4981 #define _PCH_TRANSA_LINK_M2 0xe0048 4982 #define _PCH_TRANSA_LINK_N2 0xe004c 4983 4984 /* Per-transcoder DIP controls (PCH) */ 4985 #define _VIDEO_DIP_CTL_A 0xe0200 4986 #define _VIDEO_DIP_DATA_A 0xe0208 4987 #define _VIDEO_DIP_GCP_A 0xe0210 4988 #define GCP_COLOR_INDICATION (1 << 2) 4989 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 4990 #define GCP_AV_MUTE (1 << 0) 4991 4992 #define _VIDEO_DIP_CTL_B 0xe1200 4993 #define _VIDEO_DIP_DATA_B 0xe1208 4994 #define _VIDEO_DIP_GCP_B 0xe1210 4995 4996 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 4997 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 4998 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 4999 5000 /* Per-transcoder DIP controls (VLV) */ 5001 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 5002 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 5003 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 5004 5005 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 5006 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 5007 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 5008 5009 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 5010 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 5011 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 5012 5013 #define VLV_TVIDEO_DIP_CTL(pipe) \ 5014 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 5015 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 5016 #define VLV_TVIDEO_DIP_DATA(pipe) \ 5017 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 5018 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 5019 #define VLV_TVIDEO_DIP_GCP(pipe) \ 5020 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 5021 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 5022 5023 /* Haswell DIP controls */ 5024 5025 #define _HSW_VIDEO_DIP_CTL_A 0x60200 5026 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 5027 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 5028 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 5029 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 5030 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 5031 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 5032 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 5033 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 5034 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 5035 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 5036 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 5037 #define _HSW_VIDEO_DIP_GCP_A 0x60210 5038 5039 #define _HSW_VIDEO_DIP_CTL_B 0x61200 5040 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 5041 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 5042 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 5043 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 5044 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 5045 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 5046 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 5047 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 5048 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 5049 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 5050 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 5051 #define _HSW_VIDEO_DIP_GCP_B 0x61210 5052 5053 /* Icelake PPS_DATA and _ECC DIP Registers. 5054 * These are available for transcoders B,C and eDP. 5055 * Adding the _A so as to reuse the _MMIO_TRANS2 5056 * definition, with which it offsets to the right location. 5057 */ 5058 5059 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 5060 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 5061 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 5062 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 5063 5064 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 5065 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 5066 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 5067 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 5068 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 5069 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 5070 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 5071 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 5072 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 5073 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 5074 5075 #define _HSW_STEREO_3D_CTL_A 0x70020 5076 #define S3D_ENABLE (1 << 31) 5077 #define _HSW_STEREO_3D_CTL_B 0x71020 5078 5079 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 5080 5081 #define _PCH_TRANS_HTOTAL_B 0xe1000 5082 #define _PCH_TRANS_HBLANK_B 0xe1004 5083 #define _PCH_TRANS_HSYNC_B 0xe1008 5084 #define _PCH_TRANS_VTOTAL_B 0xe100c 5085 #define _PCH_TRANS_VBLANK_B 0xe1010 5086 #define _PCH_TRANS_VSYNC_B 0xe1014 5087 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 5088 5089 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 5090 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 5091 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 5092 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 5093 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 5094 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 5095 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 5096 5097 #define _PCH_TRANSB_DATA_M1 0xe1030 5098 #define _PCH_TRANSB_DATA_N1 0xe1034 5099 #define _PCH_TRANSB_DATA_M2 0xe1038 5100 #define _PCH_TRANSB_DATA_N2 0xe103c 5101 #define _PCH_TRANSB_LINK_M1 0xe1040 5102 #define _PCH_TRANSB_LINK_N1 0xe1044 5103 #define _PCH_TRANSB_LINK_M2 0xe1048 5104 #define _PCH_TRANSB_LINK_N2 0xe104c 5105 5106 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 5107 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 5108 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 5109 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 5110 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 5111 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 5112 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 5113 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 5114 5115 #define _PCH_TRANSACONF 0xf0008 5116 #define _PCH_TRANSBCONF 0xf1008 5117 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 5118 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 5119 #define TRANS_ENABLE REG_BIT(31) 5120 #define TRANS_STATE_ENABLE REG_BIT(30) 5121 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 5122 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 5123 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 5124 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 5125 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 5126 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 5127 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 5128 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 5129 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 5130 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 5131 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 5132 #define _TRANSA_CHICKEN1 0xf0060 5133 #define _TRANSB_CHICKEN1 0xf1060 5134 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 5135 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 5136 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 5137 #define _TRANSA_CHICKEN2 0xf0064 5138 #define _TRANSB_CHICKEN2 0xf1064 5139 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 5140 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 5141 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 5142 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 5143 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 5144 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 5145 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 5146 5147 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 5148 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 5149 #define FDIA_PHASE_SYNC_SHIFT_EN 18 5150 #define INVERT_DDID_HPD (1 << 18) 5151 #define INVERT_DDIC_HPD (1 << 17) 5152 #define INVERT_DDIB_HPD (1 << 16) 5153 #define INVERT_DDIA_HPD (1 << 15) 5154 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 5155 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 5156 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 5157 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 5158 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 5159 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 5160 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2) 5161 #define SPT_PWM_GRANULARITY (1 << 0) 5162 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 5163 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 5164 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 5165 #define LPT_PWM_GRANULARITY (1 << 5) 5166 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 5167 5168 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 5169 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 5170 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 5171 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 5172 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 5173 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 5174 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 5175 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 5176 5177 #define _PCH_DP_B 0xe4100 5178 #define PCH_DP_B _MMIO(_PCH_DP_B) 5179 #define _PCH_DPB_AUX_CH_CTL 0xe4110 5180 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 5181 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 5182 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 5183 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 5184 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 5185 5186 #define _PCH_DP_C 0xe4200 5187 #define PCH_DP_C _MMIO(_PCH_DP_C) 5188 #define _PCH_DPC_AUX_CH_CTL 0xe4210 5189 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 5190 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 5191 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 5192 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 5193 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 5194 5195 #define _PCH_DP_D 0xe4300 5196 #define PCH_DP_D _MMIO(_PCH_DP_D) 5197 #define _PCH_DPD_AUX_CH_CTL 0xe4310 5198 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 5199 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 5200 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 5201 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 5202 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 5203 5204 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 5205 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5206 5207 /* CPT */ 5208 #define _TRANS_DP_CTL_A 0xe0300 5209 #define _TRANS_DP_CTL_B 0xe1300 5210 #define _TRANS_DP_CTL_C 0xe2300 5211 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 5212 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 5213 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 5214 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 5215 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 5216 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 5217 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 5218 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 5219 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 5220 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 5221 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 5222 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 5223 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 5224 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 5225 5226 #define _TRANS_DP2_CTL_A 0x600a0 5227 #define _TRANS_DP2_CTL_B 0x610a0 5228 #define _TRANS_DP2_CTL_C 0x620a0 5229 #define _TRANS_DP2_CTL_D 0x630a0 5230 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 5231 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 5232 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 5233 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 5234 5235 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 5236 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 5237 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 5238 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 5239 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 5240 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 5241 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 5242 5243 #define _TRANS_DP2_VFREQLOW_A 0x600a8 5244 #define _TRANS_DP2_VFREQLOW_B 0x610a8 5245 #define _TRANS_DP2_VFREQLOW_C 0x620a8 5246 #define _TRANS_DP2_VFREQLOW_D 0x630a8 5247 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 5248 5249 /* SNB eDP training params */ 5250 /* SNB A-stepping */ 5251 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 5252 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 5253 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 5254 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 5255 /* SNB B-stepping */ 5256 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 5257 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 5258 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 5259 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 5260 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 5261 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 5262 5263 /* IVB */ 5264 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 5265 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 5266 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 5267 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 5268 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 5269 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 5270 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 5271 5272 /* legacy values */ 5273 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 5274 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 5275 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 5276 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 5277 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 5278 5279 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 5280 5281 #define VLV_PMWGICZ _MMIO(0x1300a4) 5282 5283 #define HSW_EDRAM_CAP _MMIO(0x120010) 5284 #define EDRAM_ENABLED 0x1 5285 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 5286 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 5287 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 5288 5289 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 5290 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 5291 #define PIXEL_OVERLAP_CNT_SHIFT 30 5292 5293 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 5294 #define GEN6_PCODE_READY (1 << 31) 5295 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 5296 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 5297 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 5298 #define GEN6_PCODE_ERROR_MASK 0xFF 5299 #define GEN6_PCODE_SUCCESS 0x0 5300 #define GEN6_PCODE_ILLEGAL_CMD 0x1 5301 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 5302 #define GEN6_PCODE_TIMEOUT 0x3 5303 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 5304 #define GEN7_PCODE_TIMEOUT 0x2 5305 #define GEN7_PCODE_ILLEGAL_DATA 0x3 5306 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 5307 #define GEN11_PCODE_LOCKED 0x6 5308 #define GEN11_PCODE_REJECTED 0x11 5309 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 5310 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 5311 #define GEN6_PCODE_READ_RC6VIDS 0x5 5312 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 5313 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 5314 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 5315 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 5316 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 5317 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 5318 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 5319 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 5320 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 5321 #define SKL_PCODE_CDCLK_CONTROL 0x7 5322 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 5323 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 5324 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 5325 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 5326 #define GEN6_READ_OC_PARAMS 0xc 5327 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 5328 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 5329 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 5330 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 5331 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 5332 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 5333 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 5334 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 5335 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 5336 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 5337 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 5338 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 5339 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 5340 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 5341 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 5342 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 5343 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 5344 #define GEN6_PCODE_READ_D_COMP 0x10 5345 #define GEN6_PCODE_WRITE_D_COMP 0x11 5346 #define ICL_PCODE_EXIT_TCCOLD 0x12 5347 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 5348 #define DISPLAY_IPS_CONTROL 0x19 5349 #define TGL_PCODE_TCCOLD 0x26 5350 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 5351 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 5352 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 5353 /* See also IPS_CTL */ 5354 #define IPS_PCODE_CONTROL (1 << 30) 5355 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 5356 #define GEN9_PCODE_SAGV_CONTROL 0x21 5357 #define GEN9_SAGV_DISABLE 0x0 5358 #define GEN9_SAGV_IS_DISABLED 0x1 5359 #define GEN9_SAGV_ENABLE 0x3 5360 #define DG1_PCODE_STATUS 0x7E 5361 #define DG1_UNCORE_GET_INIT_STATUS 0x0 5362 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 5363 #define PCODE_POWER_SETUP 0x7C 5364 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4 5365 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5 5366 #define POWER_SETUP_I1_WATTS REG_BIT(31) 5367 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ 5368 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) 5369 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 5370 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ 5371 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 5372 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 5373 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 5374 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 5375 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 5376 #define PCODE_MBOX_DOMAIN_NONE 0x0 5377 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 5378 #define GEN6_PCODE_DATA _MMIO(0x138128) 5379 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 5380 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 5381 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 5382 5383 /* IVYBRIDGE DPF */ 5384 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 5385 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 5386 #define GEN7_PARITY_ERROR_VALID (1 << 13) 5387 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 5388 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 5389 #define GEN7_PARITY_ERROR_ROW(reg) \ 5390 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 5391 #define GEN7_PARITY_ERROR_BANK(reg) \ 5392 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 5393 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 5394 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 5395 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 5396 5397 /* These are the 4 32-bit write offset registers for each stream 5398 * output buffer. It determines the offset from the 5399 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 5400 */ 5401 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 5402 5403 /* 5404 * HSW - ICL power wells 5405 * 5406 * Platforms have up to 3 power well control register sets, each set 5407 * controlling up to 16 power wells via a request/status HW flag tuple: 5408 * - main (HSW_PWR_WELL_CTL[1-4]) 5409 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 5410 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 5411 * Each control register set consists of up to 4 registers used by different 5412 * sources that can request a power well to be enabled: 5413 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 5414 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 5415 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 5416 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 5417 */ 5418 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 5419 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 5420 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 5421 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 5422 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 5423 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 5424 5425 /* HSW/BDW power well */ 5426 #define HSW_PW_CTL_IDX_GLOBAL 15 5427 5428 /* SKL/BXT/GLK power wells */ 5429 #define SKL_PW_CTL_IDX_PW_2 15 5430 #define SKL_PW_CTL_IDX_PW_1 14 5431 #define GLK_PW_CTL_IDX_AUX_C 10 5432 #define GLK_PW_CTL_IDX_AUX_B 9 5433 #define GLK_PW_CTL_IDX_AUX_A 8 5434 #define SKL_PW_CTL_IDX_DDI_D 4 5435 #define SKL_PW_CTL_IDX_DDI_C 3 5436 #define SKL_PW_CTL_IDX_DDI_B 2 5437 #define SKL_PW_CTL_IDX_DDI_A_E 1 5438 #define GLK_PW_CTL_IDX_DDI_A 1 5439 #define SKL_PW_CTL_IDX_MISC_IO 0 5440 5441 /* ICL/TGL - power wells */ 5442 #define TGL_PW_CTL_IDX_PW_5 4 5443 #define ICL_PW_CTL_IDX_PW_4 3 5444 #define ICL_PW_CTL_IDX_PW_3 2 5445 #define ICL_PW_CTL_IDX_PW_2 1 5446 #define ICL_PW_CTL_IDX_PW_1 0 5447 5448 /* XE_LPD - power wells */ 5449 #define XELPD_PW_CTL_IDX_PW_D 8 5450 #define XELPD_PW_CTL_IDX_PW_C 7 5451 #define XELPD_PW_CTL_IDX_PW_B 6 5452 #define XELPD_PW_CTL_IDX_PW_A 5 5453 5454 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 5455 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 5456 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 5457 #define TGL_PW_CTL_IDX_AUX_TBT6 14 5458 #define TGL_PW_CTL_IDX_AUX_TBT5 13 5459 #define TGL_PW_CTL_IDX_AUX_TBT4 12 5460 #define ICL_PW_CTL_IDX_AUX_TBT4 11 5461 #define TGL_PW_CTL_IDX_AUX_TBT3 11 5462 #define ICL_PW_CTL_IDX_AUX_TBT3 10 5463 #define TGL_PW_CTL_IDX_AUX_TBT2 10 5464 #define ICL_PW_CTL_IDX_AUX_TBT2 9 5465 #define TGL_PW_CTL_IDX_AUX_TBT1 9 5466 #define ICL_PW_CTL_IDX_AUX_TBT1 8 5467 #define TGL_PW_CTL_IDX_AUX_TC6 8 5468 #define XELPD_PW_CTL_IDX_AUX_E 8 5469 #define TGL_PW_CTL_IDX_AUX_TC5 7 5470 #define XELPD_PW_CTL_IDX_AUX_D 7 5471 #define TGL_PW_CTL_IDX_AUX_TC4 6 5472 #define ICL_PW_CTL_IDX_AUX_F 5 5473 #define TGL_PW_CTL_IDX_AUX_TC3 5 5474 #define ICL_PW_CTL_IDX_AUX_E 4 5475 #define TGL_PW_CTL_IDX_AUX_TC2 4 5476 #define ICL_PW_CTL_IDX_AUX_D 3 5477 #define TGL_PW_CTL_IDX_AUX_TC1 3 5478 #define ICL_PW_CTL_IDX_AUX_C 2 5479 #define ICL_PW_CTL_IDX_AUX_B 1 5480 #define ICL_PW_CTL_IDX_AUX_A 0 5481 5482 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 5483 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 5484 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 5485 #define XELPD_PW_CTL_IDX_DDI_E 8 5486 #define TGL_PW_CTL_IDX_DDI_TC6 8 5487 #define XELPD_PW_CTL_IDX_DDI_D 7 5488 #define TGL_PW_CTL_IDX_DDI_TC5 7 5489 #define TGL_PW_CTL_IDX_DDI_TC4 6 5490 #define ICL_PW_CTL_IDX_DDI_F 5 5491 #define TGL_PW_CTL_IDX_DDI_TC3 5 5492 #define ICL_PW_CTL_IDX_DDI_E 4 5493 #define TGL_PW_CTL_IDX_DDI_TC2 4 5494 #define ICL_PW_CTL_IDX_DDI_D 3 5495 #define TGL_PW_CTL_IDX_DDI_TC1 3 5496 #define ICL_PW_CTL_IDX_DDI_C 2 5497 #define ICL_PW_CTL_IDX_DDI_B 1 5498 #define ICL_PW_CTL_IDX_DDI_A 0 5499 5500 /* HSW - power well misc debug registers */ 5501 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 5502 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 5503 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 5504 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 5505 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 5506 5507 /* SKL Fuse Status */ 5508 enum skl_power_gate { 5509 SKL_PG0, 5510 SKL_PG1, 5511 SKL_PG2, 5512 ICL_PG3, 5513 ICL_PG4, 5514 }; 5515 5516 #define SKL_FUSE_STATUS _MMIO(0x42000) 5517 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 5518 /* 5519 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 5520 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 5521 */ 5522 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 5523 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 5524 /* 5525 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 5526 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 5527 */ 5528 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 5529 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 5530 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 5531 5532 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 5533 #define _ICL_AUX_ANAOVRD1_A 0x162398 5534 #define _ICL_AUX_ANAOVRD1_B 0x6C398 5535 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 5536 _ICL_AUX_ANAOVRD1_A, \ 5537 _ICL_AUX_ANAOVRD1_B)) 5538 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 5539 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 5540 5541 /* Per-pipe DDI Function Control */ 5542 #define _TRANS_DDI_FUNC_CTL_A 0x60400 5543 #define _TRANS_DDI_FUNC_CTL_B 0x61400 5544 #define _TRANS_DDI_FUNC_CTL_C 0x62400 5545 #define _TRANS_DDI_FUNC_CTL_D 0x63400 5546 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 5547 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 5548 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 5549 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 5550 5551 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 5552 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 5553 #define TRANS_DDI_PORT_SHIFT 28 5554 #define TGL_TRANS_DDI_PORT_SHIFT 27 5555 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 5556 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 5557 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 5558 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 5559 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 5560 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 5561 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 5562 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 5563 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 5564 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 5565 #define TRANS_DDI_BPC_MASK (7 << 20) 5566 #define TRANS_DDI_BPC_8 (0 << 20) 5567 #define TRANS_DDI_BPC_10 (1 << 20) 5568 #define TRANS_DDI_BPC_6 (2 << 20) 5569 #define TRANS_DDI_BPC_12 (3 << 20) 5570 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 5571 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 5572 #define TRANS_DDI_PVSYNC (1 << 17) 5573 #define TRANS_DDI_PHSYNC (1 << 16) 5574 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 5575 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 5576 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 5577 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 5578 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 5579 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 5580 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 5581 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 5582 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 5583 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 5584 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 5585 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 5586 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 5587 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 5588 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 5589 #define TRANS_DDI_BFI_ENABLE (1 << 4) 5590 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 5591 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 5592 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 5593 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 5594 | TRANS_DDI_HDMI_SCRAMBLING) 5595 5596 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 5597 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 5598 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 5599 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 5600 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 5601 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 5602 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 5603 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 5604 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 5605 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 5606 5607 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 5608 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 5609 5610 /* DisplayPort Transport Control */ 5611 #define _DP_TP_CTL_A 0x64040 5612 #define _DP_TP_CTL_B 0x64140 5613 #define _TGL_DP_TP_CTL_A 0x60540 5614 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 5615 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 5616 #define DP_TP_CTL_ENABLE (1 << 31) 5617 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 5618 #define DP_TP_CTL_MODE_SST (0 << 27) 5619 #define DP_TP_CTL_MODE_MST (1 << 27) 5620 #define DP_TP_CTL_FORCE_ACT (1 << 25) 5621 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 5622 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 5623 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 5624 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 5625 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 5626 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 5627 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 5628 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 5629 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 5630 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 5631 5632 /* DisplayPort Transport Status */ 5633 #define _DP_TP_STATUS_A 0x64044 5634 #define _DP_TP_STATUS_B 0x64144 5635 #define _TGL_DP_TP_STATUS_A 0x60544 5636 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 5637 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 5638 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 5639 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 5640 #define DP_TP_STATUS_ACT_SENT (1 << 24) 5641 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 5642 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 5643 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 5644 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 5645 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 5646 5647 /* DDI Buffer Control */ 5648 #define _DDI_BUF_CTL_A 0x64000 5649 #define _DDI_BUF_CTL_B 0x64100 5650 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 5651 #define DDI_BUF_CTL_ENABLE (1 << 31) 5652 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 5653 #define DDI_BUF_EMP_MASK (0xf << 24) 5654 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 5655 #define DDI_BUF_PORT_REVERSAL (1 << 16) 5656 #define DDI_BUF_IS_IDLE (1 << 7) 5657 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 5658 #define DDI_A_4_LANES (1 << 4) 5659 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 5660 #define DDI_PORT_WIDTH_MASK (7 << 1) 5661 #define DDI_PORT_WIDTH_SHIFT 1 5662 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 5663 5664 /* DDI Buffer Translations */ 5665 #define _DDI_BUF_TRANS_A 0x64E00 5666 #define _DDI_BUF_TRANS_B 0x64E60 5667 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 5668 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 5669 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 5670 5671 /* DDI DP Compliance Control */ 5672 #define _DDI_DP_COMP_CTL_A 0x605F0 5673 #define _DDI_DP_COMP_CTL_B 0x615F0 5674 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 5675 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 5676 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 5677 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 5678 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 5679 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 5680 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 5681 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 5682 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 5683 5684 /* DDI DP Compliance Pattern */ 5685 #define _DDI_DP_COMP_PAT_A 0x605F4 5686 #define _DDI_DP_COMP_PAT_B 0x615F4 5687 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 5688 5689 /* Sideband Interface (SBI) is programmed indirectly, via 5690 * SBI_ADDR, which contains the register offset; and SBI_DATA, 5691 * which contains the payload */ 5692 #define SBI_ADDR _MMIO(0xC6000) 5693 #define SBI_DATA _MMIO(0xC6004) 5694 #define SBI_CTL_STAT _MMIO(0xC6008) 5695 #define SBI_CTL_DEST_ICLK (0x0 << 16) 5696 #define SBI_CTL_DEST_MPHY (0x1 << 16) 5697 #define SBI_CTL_OP_IORD (0x2 << 8) 5698 #define SBI_CTL_OP_IOWR (0x3 << 8) 5699 #define SBI_CTL_OP_CRRD (0x6 << 8) 5700 #define SBI_CTL_OP_CRWR (0x7 << 8) 5701 #define SBI_RESPONSE_FAIL (0x1 << 1) 5702 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 5703 #define SBI_BUSY (0x1 << 0) 5704 #define SBI_READY (0x0 << 0) 5705 5706 /* SBI offsets */ 5707 #define SBI_SSCDIVINTPHASE 0x0200 5708 #define SBI_SSCDIVINTPHASE6 0x0600 5709 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 5710 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 5711 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 5712 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 5713 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 5714 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 5715 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 5716 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 5717 #define SBI_SSCDITHPHASE 0x0204 5718 #define SBI_SSCCTL 0x020c 5719 #define SBI_SSCCTL6 0x060C 5720 #define SBI_SSCCTL_PATHALT (1 << 3) 5721 #define SBI_SSCCTL_DISABLE (1 << 0) 5722 #define SBI_SSCAUXDIV6 0x0610 5723 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 5724 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 5725 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 5726 #define SBI_DBUFF0 0x2a00 5727 #define SBI_GEN0 0x1f00 5728 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 5729 5730 /* LPT PIXCLK_GATE */ 5731 #define PIXCLK_GATE _MMIO(0xC6020) 5732 #define PIXCLK_GATE_UNGATE (1 << 0) 5733 #define PIXCLK_GATE_GATE (0 << 0) 5734 5735 /* SPLL */ 5736 #define SPLL_CTL _MMIO(0x46020) 5737 #define SPLL_PLL_ENABLE (1 << 31) 5738 #define SPLL_REF_BCLK (0 << 28) 5739 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 5740 #define SPLL_REF_NON_SSC_HSW (2 << 28) 5741 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 5742 #define SPLL_REF_LCPLL (3 << 28) 5743 #define SPLL_REF_MASK (3 << 28) 5744 #define SPLL_FREQ_810MHz (0 << 26) 5745 #define SPLL_FREQ_1350MHz (1 << 26) 5746 #define SPLL_FREQ_2700MHz (2 << 26) 5747 #define SPLL_FREQ_MASK (3 << 26) 5748 5749 /* WRPLL */ 5750 #define _WRPLL_CTL1 0x46040 5751 #define _WRPLL_CTL2 0x46060 5752 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 5753 #define WRPLL_PLL_ENABLE (1 << 31) 5754 #define WRPLL_REF_BCLK (0 << 28) 5755 #define WRPLL_REF_PCH_SSC (1 << 28) 5756 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 5757 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 5758 #define WRPLL_REF_LCPLL (3 << 28) 5759 #define WRPLL_REF_MASK (3 << 28) 5760 /* WRPLL divider programming */ 5761 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 5762 #define WRPLL_DIVIDER_REF_MASK (0xff) 5763 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 5764 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 5765 #define WRPLL_DIVIDER_POST_SHIFT 8 5766 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 5767 #define WRPLL_DIVIDER_FB_SHIFT 16 5768 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 5769 5770 /* Port clock selection */ 5771 #define _PORT_CLK_SEL_A 0x46100 5772 #define _PORT_CLK_SEL_B 0x46104 5773 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 5774 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 5775 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 5776 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 5777 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 5778 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 5779 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 5780 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 5781 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 5782 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 5783 5784 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 5785 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 5786 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 5787 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 5788 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 5789 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 5790 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 5791 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 5792 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 5793 5794 /* Transcoder clock selection */ 5795 #define _TRANS_CLK_SEL_A 0x46140 5796 #define _TRANS_CLK_SEL_B 0x46144 5797 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 5798 /* For each transcoder, we need to select the corresponding port clock */ 5799 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 5800 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 5801 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 5802 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 5803 5804 5805 #define CDCLK_FREQ _MMIO(0x46200) 5806 5807 #define _TRANSA_MSA_MISC 0x60410 5808 #define _TRANSB_MSA_MISC 0x61410 5809 #define _TRANSC_MSA_MISC 0x62410 5810 #define _TRANS_EDP_MSA_MISC 0x6f410 5811 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 5812 /* See DP_MSA_MISC_* for the bit definitions */ 5813 5814 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 5815 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 5816 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 5817 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 5818 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 5819 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 5820 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 5821 5822 /* LCPLL Control */ 5823 #define LCPLL_CTL _MMIO(0x130040) 5824 #define LCPLL_PLL_DISABLE (1 << 31) 5825 #define LCPLL_PLL_LOCK (1 << 30) 5826 #define LCPLL_REF_NON_SSC (0 << 28) 5827 #define LCPLL_REF_BCLK (2 << 28) 5828 #define LCPLL_REF_PCH_SSC (3 << 28) 5829 #define LCPLL_REF_MASK (3 << 28) 5830 #define LCPLL_CLK_FREQ_MASK (3 << 26) 5831 #define LCPLL_CLK_FREQ_450 (0 << 26) 5832 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 5833 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 5834 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 5835 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 5836 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 5837 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 5838 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 5839 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 5840 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 5841 5842 /* 5843 * SKL Clocks 5844 */ 5845 5846 /* CDCLK_CTL */ 5847 #define CDCLK_CTL _MMIO(0x46000) 5848 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 5849 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 5850 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 5851 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 5852 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 5853 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 5854 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 5855 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 5856 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 5857 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 5858 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 5859 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 5860 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 5861 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 5862 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 5863 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 5864 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 5865 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 5866 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 5867 5868 /* CDCLK_SQUASH_CTL */ 5869 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 5870 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 5871 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 5872 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 5873 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 5874 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 5875 5876 /* LCPLL_CTL */ 5877 #define LCPLL1_CTL _MMIO(0x46010) 5878 #define LCPLL2_CTL _MMIO(0x46014) 5879 #define LCPLL_PLL_ENABLE (1 << 31) 5880 5881 /* DPLL control1 */ 5882 #define DPLL_CTRL1 _MMIO(0x6C058) 5883 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 5884 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 5885 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 5886 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 5887 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 5888 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 5889 #define DPLL_CTRL1_LINK_RATE_2700 0 5890 #define DPLL_CTRL1_LINK_RATE_1350 1 5891 #define DPLL_CTRL1_LINK_RATE_810 2 5892 #define DPLL_CTRL1_LINK_RATE_1620 3 5893 #define DPLL_CTRL1_LINK_RATE_1080 4 5894 #define DPLL_CTRL1_LINK_RATE_2160 5 5895 5896 /* DPLL control2 */ 5897 #define DPLL_CTRL2 _MMIO(0x6C05C) 5898 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 5899 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 5900 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 5901 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 5902 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 5903 5904 /* DPLL Status */ 5905 #define DPLL_STATUS _MMIO(0x6C060) 5906 #define DPLL_LOCK(id) (1 << ((id) * 8)) 5907 5908 /* DPLL cfg */ 5909 #define _DPLL1_CFGCR1 0x6C040 5910 #define _DPLL2_CFGCR1 0x6C048 5911 #define _DPLL3_CFGCR1 0x6C050 5912 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 5913 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 5914 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 5915 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 5916 5917 #define _DPLL1_CFGCR2 0x6C044 5918 #define _DPLL2_CFGCR2 0x6C04C 5919 #define _DPLL3_CFGCR2 0x6C054 5920 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 5921 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 5922 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 5923 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 5924 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 5925 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 5926 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 5927 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 5928 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 5929 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 5930 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 5931 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 5932 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 5933 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 5934 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 5935 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 5936 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 5937 5938 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 5939 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 5940 5941 /* ICL Clocks */ 5942 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 5943 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 5944 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 5945 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 5946 (tc_port) + 12 : \ 5947 (tc_port) - TC_PORT_4 + 21)) 5948 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 5949 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5950 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5951 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 5952 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 5953 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5954 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 5955 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5956 5957 /* 5958 * DG1 Clocks 5959 * First registers controls the first A and B, while the second register 5960 * controls the phy C and D. The bits on these registers are the 5961 * same, but refer to different phys 5962 */ 5963 #define _DG1_DPCLKA_CFGCR0 0x164280 5964 #define _DG1_DPCLKA1_CFGCR0 0x16C280 5965 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 5966 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 5967 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 5968 _DG1_DPCLKA_CFGCR0, \ 5969 _DG1_DPCLKA1_CFGCR0) 5970 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 5971 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 5972 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5973 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 5974 5975 /* ADLS Clocks */ 5976 #define _ADLS_DPCLKA_CFGCR0 0x164280 5977 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 5978 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 5979 _ADLS_DPCLKA_CFGCR0, \ 5980 _ADLS_DPCLKA_CFGCR1) 5981 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 5982 /* ADLS DPCLKA_CFGCR0 DDI mask */ 5983 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 5984 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 5985 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 5986 /* ADLS DPCLKA_CFGCR1 DDI mask */ 5987 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 5988 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 5989 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 5990 ADLS_DPCLKA_DDIA_SEL_MASK, \ 5991 ADLS_DPCLKA_DDIB_SEL_MASK, \ 5992 ADLS_DPCLKA_DDII_SEL_MASK, \ 5993 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 5994 ADLS_DPCLKA_DDIK_SEL_MASK) 5995 5996 /* ICL PLL */ 5997 #define _DPLL0_ENABLE 0x46010 5998 #define _DPLL1_ENABLE 0x46014 5999 #define _ADLS_DPLL2_ENABLE 0x46018 6000 #define _ADLS_DPLL3_ENABLE 0x46030 6001 #define PLL_ENABLE REG_BIT(31) 6002 #define PLL_LOCK REG_BIT(30) 6003 #define PLL_POWER_ENABLE REG_BIT(27) 6004 #define PLL_POWER_STATE REG_BIT(26) 6005 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 6006 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 6007 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) 6008 6009 #define _DG2_PLL3_ENABLE 0x4601C 6010 6011 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ 6012 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 6013 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) 6014 6015 #define TBT_PLL_ENABLE _MMIO(0x46020) 6016 6017 #define _MG_PLL1_ENABLE 0x46030 6018 #define _MG_PLL2_ENABLE 0x46034 6019 #define _MG_PLL3_ENABLE 0x46038 6020 #define _MG_PLL4_ENABLE 0x4603C 6021 /* Bits are the same as _DPLL0_ENABLE */ 6022 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 6023 _MG_PLL2_ENABLE) 6024 6025 /* DG1 PLL */ 6026 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6027 _DPLL0_ENABLE, _DPLL1_ENABLE, \ 6028 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) 6029 6030 /* ADL-P Type C PLL */ 6031 #define PORTTC1_PLL_ENABLE 0x46038 6032 #define PORTTC2_PLL_ENABLE 0x46040 6033 6034 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 6035 PORTTC1_PLL_ENABLE, \ 6036 PORTTC2_PLL_ENABLE) 6037 6038 #define _ICL_DPLL0_CFGCR0 0x164000 6039 #define _ICL_DPLL1_CFGCR0 0x164080 6040 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 6041 _ICL_DPLL1_CFGCR0) 6042 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 6043 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 6044 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 6045 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 6046 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 6047 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 6048 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 6049 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 6050 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 6051 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 6052 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 6053 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 6054 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 6055 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 6056 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 6057 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 6058 6059 #define _ICL_DPLL0_CFGCR1 0x164004 6060 #define _ICL_DPLL1_CFGCR1 0x164084 6061 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 6062 _ICL_DPLL1_CFGCR1) 6063 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 6064 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 6065 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 6066 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 6067 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 6068 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 6069 #define DPLL_CFGCR1_KDIV_SHIFT (6) 6070 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 6071 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 6072 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 6073 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 6074 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 6075 #define DPLL_CFGCR1_PDIV_SHIFT (2) 6076 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 6077 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 6078 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 6079 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 6080 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 6081 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 6082 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 6083 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 6084 6085 #define _TGL_DPLL0_CFGCR0 0x164284 6086 #define _TGL_DPLL1_CFGCR0 0x16428C 6087 #define _TGL_TBTPLL_CFGCR0 0x16429C 6088 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6089 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 6090 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) 6091 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 6092 _TGL_DPLL1_CFGCR0) 6093 6094 #define _TGL_DPLL0_DIV0 0x164B00 6095 #define _TGL_DPLL1_DIV0 0x164C00 6096 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 6097 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 6098 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 6099 6100 #define _TGL_DPLL0_CFGCR1 0x164288 6101 #define _TGL_DPLL1_CFGCR1 0x164290 6102 #define _TGL_TBTPLL_CFGCR1 0x1642A0 6103 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6104 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 6105 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) 6106 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 6107 _TGL_DPLL1_CFGCR1) 6108 6109 #define _DG1_DPLL2_CFGCR0 0x16C284 6110 #define _DG1_DPLL3_CFGCR0 0x16C28C 6111 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6112 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 6113 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) 6114 6115 #define _DG1_DPLL2_CFGCR1 0x16C288 6116 #define _DG1_DPLL3_CFGCR1 0x16C290 6117 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6118 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 6119 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) 6120 6121 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 6122 #define _ADLS_DPLL4_CFGCR0 0x164294 6123 #define _ADLS_DPLL3_CFGCR0 0x1642C0 6124 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6125 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ 6126 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) 6127 6128 #define _ADLS_DPLL4_CFGCR1 0x164298 6129 #define _ADLS_DPLL3_CFGCR1 0x1642C4 6130 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ 6131 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ 6132 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) 6133 6134 /* BXT display engine PLL */ 6135 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 6136 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 6137 #define BXT_DE_PLL_RATIO_MASK 0xff 6138 6139 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 6140 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 6141 #define BXT_DE_PLL_LOCK (1 << 30) 6142 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 6143 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 6144 #define ICL_CDCLK_PLL_RATIO(x) (x) 6145 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 6146 6147 /* GEN9 DC */ 6148 #define DC_STATE_EN _MMIO(0x45504) 6149 #define DC_STATE_DISABLE 0 6150 #define DC_STATE_EN_DC3CO REG_BIT(30) 6151 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 6152 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) 6153 #define HOLD_PHY_PG1_LATCH REG_BIT(20) 6154 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 6155 #define DC_STATE_EN_DC9 (1 << 3) 6156 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 6157 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 6158 6159 #define DC_STATE_DEBUG _MMIO(0x45520) 6160 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 6161 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 6162 6163 #define D_COMP_BDW _MMIO(0x138144) 6164 6165 /* Pipe WM_LINETIME - watermark line time */ 6166 #define _WM_LINETIME_A 0x45270 6167 #define _WM_LINETIME_B 0x45274 6168 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 6169 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 6170 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 6171 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 6172 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 6173 6174 /* SFUSE_STRAP */ 6175 #define SFUSE_STRAP _MMIO(0xc2014) 6176 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 6177 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 6178 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 6179 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 6180 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 6181 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 6182 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 6183 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 6184 6185 #define WM_MISC _MMIO(0x45260) 6186 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 6187 6188 #define WM_DBG _MMIO(0x45280) 6189 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 6190 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 6191 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 6192 6193 /* pipe CSC */ 6194 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 6195 #define _PIPE_A_CSC_COEFF_BY 0x49014 6196 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 6197 #define _PIPE_A_CSC_COEFF_BU 0x4901c 6198 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 6199 #define _PIPE_A_CSC_COEFF_BV 0x49024 6200 6201 #define _PIPE_A_CSC_MODE 0x49028 6202 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 6203 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 6204 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 6205 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 6206 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 6207 6208 #define _PIPE_A_CSC_PREOFF_HI 0x49030 6209 #define _PIPE_A_CSC_PREOFF_ME 0x49034 6210 #define _PIPE_A_CSC_PREOFF_LO 0x49038 6211 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 6212 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 6213 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 6214 6215 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 6216 #define _PIPE_B_CSC_COEFF_BY 0x49114 6217 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 6218 #define _PIPE_B_CSC_COEFF_BU 0x4911c 6219 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 6220 #define _PIPE_B_CSC_COEFF_BV 0x49124 6221 #define _PIPE_B_CSC_MODE 0x49128 6222 #define _PIPE_B_CSC_PREOFF_HI 0x49130 6223 #define _PIPE_B_CSC_PREOFF_ME 0x49134 6224 #define _PIPE_B_CSC_PREOFF_LO 0x49138 6225 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 6226 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 6227 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 6228 6229 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 6230 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 6231 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 6232 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 6233 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 6234 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 6235 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 6236 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 6237 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 6238 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 6239 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 6240 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 6241 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 6242 6243 /* Pipe Output CSC */ 6244 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 6245 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 6246 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 6247 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 6248 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 6249 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 6250 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 6251 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 6252 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 6253 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 6254 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 6255 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 6256 6257 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 6258 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 6259 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 6260 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 6261 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 6262 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 6263 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 6264 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 6265 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 6266 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 6267 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 6268 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 6269 6270 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 6271 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 6272 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 6273 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 6274 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 6275 _PIPE_B_OUTPUT_CSC_COEFF_BY) 6276 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 6277 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 6278 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 6279 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 6280 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 6281 _PIPE_B_OUTPUT_CSC_COEFF_BU) 6282 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 6283 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 6284 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 6285 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 6286 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 6287 _PIPE_B_OUTPUT_CSC_COEFF_BV) 6288 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 6289 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 6290 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 6291 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 6292 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 6293 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 6294 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 6295 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 6296 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 6297 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 6298 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 6299 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 6300 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 6301 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 6302 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 6303 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 6304 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 6305 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 6306 6307 /* pipe degamma/gamma LUTs on IVB+ */ 6308 #define _PAL_PREC_INDEX_A 0x4A400 6309 #define _PAL_PREC_INDEX_B 0x4AC00 6310 #define _PAL_PREC_INDEX_C 0x4B400 6311 #define PAL_PREC_SPLIT_MODE REG_BIT(31) 6312 #define PAL_PREC_AUTO_INCREMENT REG_BIT(15) 6313 #define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0) 6314 #define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x)) 6315 #define _PAL_PREC_DATA_A 0x4A404 6316 #define _PAL_PREC_DATA_B 0x4AC04 6317 #define _PAL_PREC_DATA_C 0x4B404 6318 /* see PREC_PALETTE_* for the bits */ 6319 #define _PAL_PREC_GC_MAX_A 0x4A410 6320 #define _PAL_PREC_GC_MAX_B 0x4AC10 6321 #define _PAL_PREC_GC_MAX_C 0x4B410 6322 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 6323 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 6324 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 6325 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 6326 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 6327 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 6328 6329 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 6330 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 6331 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */ 6332 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */ 6333 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */ 6334 6335 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 6336 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 6337 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 6338 #define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10) 6339 #define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0) 6340 #define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x)) 6341 #define _PRE_CSC_GAMC_DATA_A 0x4A488 6342 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 6343 #define _PRE_CSC_GAMC_DATA_C 0x4B488 6344 6345 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 6346 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 6347 6348 /* ICL Multi segmented gamma */ 6349 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 6350 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 6351 #define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15) 6352 #define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0) 6353 #define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x)) 6354 6355 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 6356 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 6357 /* see PREC_PALETTE_12P4_* for the bits */ 6358 6359 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 6360 _PAL_PREC_MULTI_SEG_INDEX_A, \ 6361 _PAL_PREC_MULTI_SEG_INDEX_B) 6362 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 6363 _PAL_PREC_MULTI_SEG_DATA_A, \ 6364 _PAL_PREC_MULTI_SEG_DATA_B) 6365 6366 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 6367 6368 /* Plane CSC Registers */ 6369 #define _PLANE_CSC_RY_GY_1_A 0x70210 6370 #define _PLANE_CSC_RY_GY_2_A 0x70310 6371 6372 #define _PLANE_CSC_RY_GY_1_B 0x71210 6373 #define _PLANE_CSC_RY_GY_2_B 0x71310 6374 6375 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 6376 _PLANE_CSC_RY_GY_1_B) 6377 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ 6378 _PLANE_CSC_RY_GY_2_B) 6379 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 6380 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 6381 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 6382 6383 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 6384 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 6385 6386 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 6387 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 6388 6389 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 6390 _PLANE_CSC_PREOFF_HI_1_B) 6391 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 6392 _PLANE_CSC_PREOFF_HI_2_B) 6393 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 6394 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 6395 (index) * 4) 6396 6397 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 6398 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 6399 6400 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 6401 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 6402 6403 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 6404 _PLANE_CSC_POSTOFF_HI_1_B) 6405 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 6406 _PLANE_CSC_POSTOFF_HI_2_B) 6407 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 6408 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 6409 (index) * 4) 6410 6411 /* pipe CSC & degamma/gamma LUTs on CHV */ 6412 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 6413 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 6414 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 6415 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 6416 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 6417 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 6418 /* cgm degamma ldw */ 6419 #define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16) 6420 #define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0) 6421 /* cgm degamma udw */ 6422 #define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0) 6423 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 6424 /* cgm gamma ldw */ 6425 #define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16) 6426 #define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0) 6427 /* cgm gamma udw */ 6428 #define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0) 6429 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 6430 #define CGM_PIPE_MODE_GAMMA (1 << 2) 6431 #define CGM_PIPE_MODE_CSC (1 << 1) 6432 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 6433 6434 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 6435 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 6436 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 6437 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 6438 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 6439 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 6440 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 6441 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 6442 6443 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 6444 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 6445 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 6446 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 6447 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 6448 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 6449 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 6450 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 6451 6452 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 6453 #define GEN4_TIMESTAMP _MMIO(0x2358) 6454 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 6455 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 6456 6457 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 6458 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 6459 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 6460 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 6461 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 6462 6463 /* g4x+, except vlv/chv! */ 6464 #define _PIPE_FRMTMSTMP_A 0x70048 6465 #define _PIPE_FRMTMSTMP_B 0x71048 6466 #define PIPE_FRMTMSTMP(pipe) \ 6467 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) 6468 6469 /* g4x+, except vlv/chv! */ 6470 #define _PIPE_FLIPTMSTMP_A 0x7004C 6471 #define _PIPE_FLIPTMSTMP_B 0x7104C 6472 #define PIPE_FLIPTMSTMP(pipe) \ 6473 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) 6474 6475 /* tgl+ */ 6476 #define _PIPE_FLIPDONETMSTMP_A 0x70054 6477 #define _PIPE_FLIPDONETMSTMP_B 0x71054 6478 #define PIPE_FLIPDONETIMSTMP(pipe) \ 6479 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) 6480 6481 #define _VLV_PIPE_MSA_MISC_A 0x70048 6482 #define VLV_PIPE_MSA_MISC(pipe) \ 6483 _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A) 6484 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) 6485 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ 6486 6487 #define GGC _MMIO(0x108040) 6488 #define GMS_MASK REG_GENMASK(15, 8) 6489 #define GGMS_MASK REG_GENMASK(7, 6) 6490 6491 #define GEN12_GSMBASE _MMIO(0x108100) 6492 #define GEN12_DSMBASE _MMIO(0x1080C0) 6493 #define GEN12_BDSM_MASK REG_GENMASK64(63, 20) 6494 6495 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 6496 #define SGSI_SIDECLK_DIS REG_BIT(17) 6497 #define SGGI_DIS REG_BIT(15) 6498 #define SGR_DIS REG_BIT(13) 6499 6500 #define _ICL_PHY_MISC_A 0x64C00 6501 #define _ICL_PHY_MISC_B 0x64C04 6502 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 6503 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 6504 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 6505 ICL_PHY_MISC(port)) 6506 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 6507 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 6508 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 6509 6510 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 6511 #define MODULAR_FIA_MASK (1 << 4) 6512 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 6513 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 6514 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 6515 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 6516 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 6517 6518 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 6519 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 6520 6521 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 6522 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 6523 6524 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 6525 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 6526 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 6527 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 6528 6529 #define _TCSS_DDI_STATUS_1 0x161500 6530 #define _TCSS_DDI_STATUS_2 0x161504 6531 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 6532 _TCSS_DDI_STATUS_1, \ 6533 _TCSS_DDI_STATUS_2)) 6534 #define TCSS_DDI_STATUS_READY REG_BIT(2) 6535 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 6536 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 6537 6538 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 6539 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 6540 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 6541 #define SPI_STATIC_REGIONS _MMIO(0x102090) 6542 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 6543 #define OROM_OFFSET _MMIO(0x1020c0) 6544 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 6545 6546 #define CLKREQ_POLICY _MMIO(0x101038) 6547 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 6548 6549 #define CLKGATE_DIS_MISC _MMIO(0x46534) 6550 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 6551 6552 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 6553 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 6554 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A) 6555 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 6556 6557 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 6558 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 6559 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 6560 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 6561 6562 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 6563 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) 6564 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 6565 #define MTL_TRP_MASK REG_GENMASK(23, 16) 6566 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 6567 6568 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) 6569 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 6570 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 6571 6572 #define MTL_MEDIA_GSI_BASE 0x380000 6573 6574 #endif /* _I915_REG_H_ */ 6575