1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 30 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 31 32 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) 33 #define _MASKED_BIT_DISABLE(a) ((a) << 16) 34 35 /* 36 * The Bridge device's PCI config space has information about the 37 * fb aperture size and the amount of pre-reserved memory. 38 * This is all handled in the intel-gtt.ko module. i915.ko only 39 * cares about the vga bit for the vga rbiter. 40 */ 41 #define INTEL_GMCH_CTRL 0x52 42 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 43 44 /* PCI config space */ 45 46 #define HPLLCC 0xc0 /* 855 only */ 47 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 48 #define GC_CLOCK_133_200 (0 << 0) 49 #define GC_CLOCK_100_200 (1 << 0) 50 #define GC_CLOCK_100_133 (2 << 0) 51 #define GC_CLOCK_166_250 (3 << 0) 52 #define GCFGC2 0xda 53 #define GCFGC 0xf0 /* 915+ only */ 54 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 55 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 56 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 57 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 58 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 59 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 60 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 61 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 62 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 63 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 64 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 65 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 66 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 67 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 68 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 69 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 70 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 71 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 72 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 73 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 74 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 75 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 76 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 77 #define LBB 0xf4 78 79 /* Graphics reset regs */ 80 #define I965_GDRST 0xc0 /* PCI config register */ 81 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 82 #define GRDOM_FULL (0<<2) 83 #define GRDOM_RENDER (1<<2) 84 #define GRDOM_MEDIA (3<<2) 85 #define GRDOM_RESET_ENABLE (1<<0) 86 87 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 88 #define GEN6_MBC_SNPCR_SHIFT 21 89 #define GEN6_MBC_SNPCR_MASK (3<<21) 90 #define GEN6_MBC_SNPCR_MAX (0<<21) 91 #define GEN6_MBC_SNPCR_MED (1<<21) 92 #define GEN6_MBC_SNPCR_LOW (2<<21) 93 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 94 95 #define GEN6_MBCTL 0x0907c 96 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 97 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 98 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 99 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 100 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 101 102 #define GEN6_GDRST 0x941c 103 #define GEN6_GRDOM_FULL (1 << 0) 104 #define GEN6_GRDOM_RENDER (1 << 1) 105 #define GEN6_GRDOM_MEDIA (1 << 2) 106 #define GEN6_GRDOM_BLT (1 << 3) 107 108 /* PPGTT stuff */ 109 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 110 111 #define GEN6_PDE_VALID (1 << 0) 112 #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */ 113 /* gen6+ has bit 11-4 for physical addr bit 39-32 */ 114 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 115 116 #define GEN6_PTE_VALID (1 << 0) 117 #define GEN6_PTE_UNCACHED (1 << 1) 118 #define GEN6_PTE_CACHE_LLC (2 << 1) 119 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) 120 #define GEN6_PTE_CACHE_BITS (3 << 1) 121 #define GEN6_PTE_GFDT (1 << 3) 122 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 123 124 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 125 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 126 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 127 #define PP_DIR_DCLV_2G 0xffffffff 128 129 #define GAM_ECOCHK 0x4090 130 #define ECOCHK_SNB_BIT (1<<10) 131 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 132 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 133 134 #define GAC_ECO_BITS 0x14090 135 #define ECOBITS_PPGTT_CACHE64B (3<<8) 136 #define ECOBITS_PPGTT_CACHE4B (0<<8) 137 138 #define GAB_CTL 0x24000 139 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 140 141 /* VGA stuff */ 142 143 #define VGA_ST01_MDA 0x3ba 144 #define VGA_ST01_CGA 0x3da 145 146 #define VGA_MSR_WRITE 0x3c2 147 #define VGA_MSR_READ 0x3cc 148 #define VGA_MSR_MEM_EN (1<<1) 149 #define VGA_MSR_CGA_MODE (1<<0) 150 151 #define VGA_SR_INDEX 0x3c4 152 #define VGA_SR_DATA 0x3c5 153 154 #define VGA_AR_INDEX 0x3c0 155 #define VGA_AR_VID_EN (1<<5) 156 #define VGA_AR_DATA_WRITE 0x3c0 157 #define VGA_AR_DATA_READ 0x3c1 158 159 #define VGA_GR_INDEX 0x3ce 160 #define VGA_GR_DATA 0x3cf 161 /* GR05 */ 162 #define VGA_GR_MEM_READ_MODE_SHIFT 3 163 #define VGA_GR_MEM_READ_MODE_PLANE 1 164 /* GR06 */ 165 #define VGA_GR_MEM_MODE_MASK 0xc 166 #define VGA_GR_MEM_MODE_SHIFT 2 167 #define VGA_GR_MEM_A0000_AFFFF 0 168 #define VGA_GR_MEM_A0000_BFFFF 1 169 #define VGA_GR_MEM_B0000_B7FFF 2 170 #define VGA_GR_MEM_B0000_BFFFF 3 171 172 #define VGA_DACMASK 0x3c6 173 #define VGA_DACRX 0x3c7 174 #define VGA_DACWX 0x3c8 175 #define VGA_DACDATA 0x3c9 176 177 #define VGA_CR_INDEX_MDA 0x3b4 178 #define VGA_CR_DATA_MDA 0x3b5 179 #define VGA_CR_INDEX_CGA 0x3d4 180 #define VGA_CR_DATA_CGA 0x3d5 181 182 /* 183 * Memory interface instructions used by the kernel 184 */ 185 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 186 187 #define MI_NOOP MI_INSTR(0, 0) 188 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 189 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 190 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 191 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 192 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 193 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 194 #define MI_FLUSH MI_INSTR(0x04, 0) 195 #define MI_READ_FLUSH (1 << 0) 196 #define MI_EXE_FLUSH (1 << 1) 197 #define MI_NO_WRITE_FLUSH (1 << 2) 198 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 199 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 200 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 201 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 202 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 203 #define MI_SUSPEND_FLUSH_EN (1<<0) 204 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 205 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 206 #define MI_OVERLAY_CONTINUE (0x0<<21) 207 #define MI_OVERLAY_ON (0x1<<21) 208 #define MI_OVERLAY_OFF (0x2<<21) 209 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 210 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 211 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 212 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 213 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 214 #define MI_MM_SPACE_GTT (1<<8) 215 #define MI_MM_SPACE_PHYSICAL (0<<8) 216 #define MI_SAVE_EXT_STATE_EN (1<<3) 217 #define MI_RESTORE_EXT_STATE_EN (1<<2) 218 #define MI_FORCE_RESTORE (1<<1) 219 #define MI_RESTORE_INHIBIT (1<<0) 220 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 221 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 222 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 223 #define MI_STORE_DWORD_INDEX_SHIFT 2 224 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 225 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 226 * simply ignores the register load under certain conditions. 227 * - One can actually load arbitrary many arbitrary registers: Simply issue x 228 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 229 */ 230 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 231 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 232 #define MI_INVALIDATE_TLB (1<<18) 233 #define MI_INVALIDATE_BSD (1<<7) 234 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 235 #define MI_BATCH_NON_SECURE (1) 236 #define MI_BATCH_NON_SECURE_I965 (1<<8) 237 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 238 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 239 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 240 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 241 #define MI_SEMAPHORE_UPDATE (1<<21) 242 #define MI_SEMAPHORE_COMPARE (1<<20) 243 #define MI_SEMAPHORE_REGISTER (1<<18) 244 #define MI_SEMAPHORE_SYNC_RV (2<<16) 245 #define MI_SEMAPHORE_SYNC_RB (0<<16) 246 #define MI_SEMAPHORE_SYNC_VR (0<<16) 247 #define MI_SEMAPHORE_SYNC_VB (2<<16) 248 #define MI_SEMAPHORE_SYNC_BR (2<<16) 249 #define MI_SEMAPHORE_SYNC_BV (0<<16) 250 #define MI_SEMAPHORE_SYNC_INVALID (1<<0) 251 /* 252 * 3D instructions used by the kernel 253 */ 254 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 255 256 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 257 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 258 #define SC_UPDATE_SCISSOR (0x1<<1) 259 #define SC_ENABLE_MASK (0x1<<0) 260 #define SC_ENABLE (0x1<<0) 261 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 262 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 263 #define SCI_YMIN_MASK (0xffff<<16) 264 #define SCI_XMIN_MASK (0xffff<<0) 265 #define SCI_YMAX_MASK (0xffff<<16) 266 #define SCI_XMAX_MASK (0xffff<<0) 267 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 268 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 269 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 270 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 271 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 272 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 273 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 274 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 275 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 276 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 277 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 278 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 279 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 280 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 281 #define BLT_DEPTH_8 (0<<24) 282 #define BLT_DEPTH_16_565 (1<<24) 283 #define BLT_DEPTH_16_1555 (2<<24) 284 #define BLT_DEPTH_32 (3<<24) 285 #define BLT_ROP_GXCOPY (0xcc<<16) 286 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 287 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 288 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 289 #define ASYNC_FLIP (1<<22) 290 #define DISPLAY_PLANE_A (0<<20) 291 #define DISPLAY_PLANE_B (1<<20) 292 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 293 #define PIPE_CONTROL_CS_STALL (1<<20) 294 #define PIPE_CONTROL_QW_WRITE (1<<14) 295 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 296 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 297 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 298 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 299 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 300 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 301 #define PIPE_CONTROL_NOTIFY (1<<8) 302 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 303 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 304 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 305 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 306 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 307 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 308 309 310 /* 311 * Reset registers 312 */ 313 #define DEBUG_RESET_I830 0x6070 314 #define DEBUG_RESET_FULL (1<<7) 315 #define DEBUG_RESET_RENDER (1<<8) 316 #define DEBUG_RESET_DISPLAY (1<<9) 317 318 /* 319 * DPIO - a special bus for various display related registers to hide behind: 320 * 0x800c: m1, m2, n, p1, p2, k dividers 321 * 0x8014: REF and SFR select 322 * 0x8014: N divider, VCO select 323 * 0x801c/3c: core clock bits 324 * 0x8048/68: low pass filter coefficients 325 * 0x8100: fast clock controls 326 */ 327 #define DPIO_PKT 0x2100 328 #define DPIO_RID (0<<24) 329 #define DPIO_OP_WRITE (1<<16) 330 #define DPIO_OP_READ (0<<16) 331 #define DPIO_PORTID (0x12<<8) 332 #define DPIO_BYTE (0xf<<4) 333 #define DPIO_BUSY (1<<0) /* status only */ 334 #define DPIO_DATA 0x2104 335 #define DPIO_REG 0x2108 336 #define DPIO_CTL 0x2110 337 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 338 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 339 #define DPIO_SFR_BYPASS (1<<1) 340 #define DPIO_RESET (1<<0) 341 342 #define _DPIO_DIV_A 0x800c 343 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 344 #define DPIO_K_SHIFT (24) /* 4 bits */ 345 #define DPIO_P1_SHIFT (21) /* 3 bits */ 346 #define DPIO_P2_SHIFT (16) /* 5 bits */ 347 #define DPIO_N_SHIFT (12) /* 4 bits */ 348 #define DPIO_ENABLE_CALIBRATION (1<<11) 349 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 350 #define DPIO_M2DIV_MASK 0xff 351 #define _DPIO_DIV_B 0x802c 352 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) 353 354 #define _DPIO_REFSFR_A 0x8014 355 #define DPIO_REFSEL_OVERRIDE 27 356 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 357 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 358 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 359 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 360 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 361 #define _DPIO_REFSFR_B 0x8034 362 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) 363 364 #define _DPIO_CORE_CLK_A 0x801c 365 #define _DPIO_CORE_CLK_B 0x803c 366 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) 367 368 #define _DPIO_LFP_COEFF_A 0x8048 369 #define _DPIO_LFP_COEFF_B 0x8068 370 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B) 371 372 #define DPIO_FASTCLK_DISABLE 0x8100 373 374 /* 375 * Fence registers 376 */ 377 #define FENCE_REG_830_0 0x2000 378 #define FENCE_REG_945_8 0x3000 379 #define I830_FENCE_START_MASK 0x07f80000 380 #define I830_FENCE_TILING_Y_SHIFT 12 381 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 382 #define I830_FENCE_PITCH_SHIFT 4 383 #define I830_FENCE_REG_VALID (1<<0) 384 #define I915_FENCE_MAX_PITCH_VAL 4 385 #define I830_FENCE_MAX_PITCH_VAL 6 386 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 387 388 #define I915_FENCE_START_MASK 0x0ff00000 389 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 390 391 #define FENCE_REG_965_0 0x03000 392 #define I965_FENCE_PITCH_SHIFT 2 393 #define I965_FENCE_TILING_Y_SHIFT 1 394 #define I965_FENCE_REG_VALID (1<<0) 395 #define I965_FENCE_MAX_PITCH_VAL 0x0400 396 397 #define FENCE_REG_SANDYBRIDGE_0 0x100000 398 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 399 400 /* control register for cpu gtt access */ 401 #define TILECTL 0x101000 402 #define TILECTL_SWZCTL (1 << 0) 403 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 404 #define TILECTL_BACKSNOOP_DIS (1 << 3) 405 406 /* 407 * Instruction and interrupt control regs 408 */ 409 #define PGTBL_ER 0x02024 410 #define RENDER_RING_BASE 0x02000 411 #define BSD_RING_BASE 0x04000 412 #define GEN6_BSD_RING_BASE 0x12000 413 #define BLT_RING_BASE 0x22000 414 #define RING_TAIL(base) ((base)+0x30) 415 #define RING_HEAD(base) ((base)+0x34) 416 #define RING_START(base) ((base)+0x38) 417 #define RING_CTL(base) ((base)+0x3c) 418 #define RING_SYNC_0(base) ((base)+0x40) 419 #define RING_SYNC_1(base) ((base)+0x44) 420 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 421 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 422 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 423 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 424 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 425 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 426 #define RING_MAX_IDLE(base) ((base)+0x54) 427 #define RING_HWS_PGA(base) ((base)+0x80) 428 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 429 #define ARB_MODE 0x04030 430 #define ARB_MODE_SWIZZLE_SNB (1<<4) 431 #define ARB_MODE_SWIZZLE_IVB (1<<5) 432 #define RENDER_HWS_PGA_GEN7 (0x04080) 433 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 434 #define DONE_REG 0x40b0 435 #define BSD_HWS_PGA_GEN7 (0x04180) 436 #define BLT_HWS_PGA_GEN7 (0x04280) 437 #define RING_ACTHD(base) ((base)+0x74) 438 #define RING_NOPID(base) ((base)+0x94) 439 #define RING_IMR(base) ((base)+0xa8) 440 #define TAIL_ADDR 0x001FFFF8 441 #define HEAD_WRAP_COUNT 0xFFE00000 442 #define HEAD_WRAP_ONE 0x00200000 443 #define HEAD_ADDR 0x001FFFFC 444 #define RING_NR_PAGES 0x001FF000 445 #define RING_REPORT_MASK 0x00000006 446 #define RING_REPORT_64K 0x00000002 447 #define RING_REPORT_128K 0x00000004 448 #define RING_NO_REPORT 0x00000000 449 #define RING_VALID_MASK 0x00000001 450 #define RING_VALID 0x00000001 451 #define RING_INVALID 0x00000000 452 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 453 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 454 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 455 #if 0 456 #define PRB0_TAIL 0x02030 457 #define PRB0_HEAD 0x02034 458 #define PRB0_START 0x02038 459 #define PRB0_CTL 0x0203c 460 #define PRB1_TAIL 0x02040 /* 915+ only */ 461 #define PRB1_HEAD 0x02044 /* 915+ only */ 462 #define PRB1_START 0x02048 /* 915+ only */ 463 #define PRB1_CTL 0x0204c /* 915+ only */ 464 #endif 465 #define IPEIR_I965 0x02064 466 #define IPEHR_I965 0x02068 467 #define INSTDONE_I965 0x0206c 468 #define RING_IPEIR(base) ((base)+0x64) 469 #define RING_IPEHR(base) ((base)+0x68) 470 #define RING_INSTDONE(base) ((base)+0x6c) 471 #define RING_INSTPS(base) ((base)+0x70) 472 #define RING_DMA_FADD(base) ((base)+0x78) 473 #define RING_INSTPM(base) ((base)+0xc0) 474 #define INSTPS 0x02070 /* 965+ only */ 475 #define INSTDONE1 0x0207c /* 965+ only */ 476 #define ACTHD_I965 0x02074 477 #define HWS_PGA 0x02080 478 #define HWS_ADDRESS_MASK 0xfffff000 479 #define HWS_START_ADDRESS_SHIFT 4 480 #define PWRCTXA 0x2088 /* 965GM+ only */ 481 #define PWRCTX_EN (1<<0) 482 #define IPEIR 0x02088 483 #define IPEHR 0x0208c 484 #define INSTDONE 0x02090 485 #define NOPID 0x02094 486 #define HWSTAM 0x02098 487 #define DMA_FADD_I8XX 0x020d0 488 489 #define ERROR_GEN6 0x040a0 490 491 /* GM45+ chicken bits -- debug workaround bits that may be required 492 * for various sorts of correct behavior. The top 16 bits of each are 493 * the enables for writing to the corresponding low bit. 494 */ 495 #define _3D_CHICKEN 0x02084 496 #define _3D_CHICKEN2 0x0208c 497 /* Disables pipelining of read flushes past the SF-WIZ interface. 498 * Required on all Ironlake steppings according to the B-Spec, but the 499 * particular danger of not doing so is not specified. 500 */ 501 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 502 #define _3D_CHICKEN3 0x02090 503 #define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5) 504 505 #define MI_MODE 0x0209c 506 # define VS_TIMER_DISPATCH (1 << 6) 507 # define MI_FLUSH_ENABLE (1 << 12) 508 509 #define GFX_MODE 0x02520 510 #define GFX_MODE_GEN7 0x0229c 511 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 512 #define GFX_RUN_LIST_ENABLE (1<<15) 513 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 514 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 515 #define GFX_REPLAY_MODE (1<<11) 516 #define GFX_PSMI_GRANULARITY (1<<10) 517 #define GFX_PPGTT_ENABLE (1<<9) 518 519 #define SCPD0 0x0209c /* 915+ only */ 520 #define IER 0x020a0 521 #define IIR 0x020a4 522 #define IMR 0x020a8 523 #define ISR 0x020ac 524 #define VLV_IIR_RW 0x182084 525 #define VLV_IER 0x1820a0 526 #define VLV_IIR 0x1820a4 527 #define VLV_IMR 0x1820a8 528 #define VLV_ISR 0x1820ac 529 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 530 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 531 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 532 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 533 #define I915_HWB_OOM_INTERRUPT (1<<13) 534 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 535 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 536 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 537 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 538 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 539 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 540 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 541 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 542 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 543 #define I915_DEBUG_INTERRUPT (1<<2) 544 #define I915_USER_INTERRUPT (1<<1) 545 #define I915_ASLE_INTERRUPT (1<<0) 546 #define I915_BSD_USER_INTERRUPT (1<<25) 547 #define EIR 0x020b0 548 #define EMR 0x020b4 549 #define ESR 0x020b8 550 #define GM45_ERROR_PAGE_TABLE (1<<5) 551 #define GM45_ERROR_MEM_PRIV (1<<4) 552 #define I915_ERROR_PAGE_TABLE (1<<4) 553 #define GM45_ERROR_CP_PRIV (1<<3) 554 #define I915_ERROR_MEMORY_REFRESH (1<<1) 555 #define I915_ERROR_INSTRUCTION (1<<0) 556 #define INSTPM 0x020c0 557 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 558 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 559 will not assert AGPBUSY# and will only 560 be delivered when out of C3. */ 561 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 562 #define ACTHD 0x020c8 563 #define FW_BLC 0x020d8 564 #define FW_BLC2 0x020dc 565 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 566 #define FW_BLC_SELF_EN_MASK (1<<31) 567 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 568 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 569 #define MM_BURST_LENGTH 0x00700000 570 #define MM_FIFO_WATERMARK 0x0001F000 571 #define LM_BURST_LENGTH 0x00000700 572 #define LM_FIFO_WATERMARK 0x0000001F 573 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 574 575 /* Make render/texture TLB fetches lower priorty than associated data 576 * fetches. This is not turned on by default 577 */ 578 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 579 580 /* Isoch request wait on GTT enable (Display A/B/C streams). 581 * Make isoch requests stall on the TLB update. May cause 582 * display underruns (test mode only) 583 */ 584 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 585 586 /* Block grant count for isoch requests when block count is 587 * set to a finite value. 588 */ 589 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 590 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 591 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 592 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 593 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 594 595 /* Enable render writes to complete in C2/C3/C4 power states. 596 * If this isn't enabled, render writes are prevented in low 597 * power states. That seems bad to me. 598 */ 599 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 600 601 /* This acknowledges an async flip immediately instead 602 * of waiting for 2TLB fetches. 603 */ 604 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 605 606 /* Enables non-sequential data reads through arbiter 607 */ 608 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 609 610 /* Disable FSB snooping of cacheable write cycles from binner/render 611 * command stream 612 */ 613 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 614 615 /* Arbiter time slice for non-isoch streams */ 616 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 617 #define MI_ARB_TIME_SLICE_1 (0 << 5) 618 #define MI_ARB_TIME_SLICE_2 (1 << 5) 619 #define MI_ARB_TIME_SLICE_4 (2 << 5) 620 #define MI_ARB_TIME_SLICE_6 (3 << 5) 621 #define MI_ARB_TIME_SLICE_8 (4 << 5) 622 #define MI_ARB_TIME_SLICE_10 (5 << 5) 623 #define MI_ARB_TIME_SLICE_14 (6 << 5) 624 #define MI_ARB_TIME_SLICE_16 (7 << 5) 625 626 /* Low priority grace period page size */ 627 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 628 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 629 630 /* Disable display A/B trickle feed */ 631 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 632 633 /* Set display plane priority */ 634 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 635 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 636 637 #define CACHE_MODE_0 0x02120 /* 915+ only */ 638 #define CM0_IZ_OPT_DISABLE (1<<6) 639 #define CM0_ZR_OPT_DISABLE (1<<5) 640 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 641 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 642 #define CM0_COLOR_EVICT_DISABLE (1<<3) 643 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 644 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 645 #define BB_ADDR 0x02140 /* 8 bytes */ 646 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 647 #define ECOSKPD 0x021d0 648 #define ECO_GATING_CX_ONLY (1<<3) 649 #define ECO_FLIP_DONE (1<<0) 650 651 #define CACHE_MODE_1 0x7004 /* IVB+ */ 652 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 653 654 /* GEN6 interrupt control 655 * Note that the per-ring interrupt bits do alias with the global interrupt bits 656 * in GTIMR. */ 657 #define GEN6_RENDER_HWSTAM 0x2098 658 #define GEN6_RENDER_IMR 0x20a8 659 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 660 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 661 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 662 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 663 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 664 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 665 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 666 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 667 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 668 669 #define GEN6_BLITTER_HWSTAM 0x22098 670 #define GEN6_BLITTER_IMR 0x220a8 671 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 672 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 673 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 674 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 675 676 #define GEN6_BLITTER_ECOSKPD 0x221d0 677 #define GEN6_BLITTER_LOCK_SHIFT 16 678 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 679 680 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 681 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 682 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) 683 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 684 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 685 686 #define GEN6_BSD_HWSTAM 0x12098 687 #define GEN6_BSD_IMR 0x120a8 688 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 689 690 #define GEN6_BSD_RNCID 0x12198 691 692 #define GEN7_FF_THREAD_MODE 0x20a0 693 #define GEN7_FF_SCHED_MASK 0x0077070 694 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 695 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 696 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 697 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 698 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 699 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 700 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 701 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 702 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 703 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 704 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 705 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 706 707 /* 708 * Framebuffer compression (915+ only) 709 */ 710 711 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 712 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 713 #define FBC_CONTROL 0x03208 714 #define FBC_CTL_EN (1<<31) 715 #define FBC_CTL_PERIODIC (1<<30) 716 #define FBC_CTL_INTERVAL_SHIFT (16) 717 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 718 #define FBC_CTL_C3_IDLE (1<<13) 719 #define FBC_CTL_STRIDE_SHIFT (5) 720 #define FBC_CTL_FENCENO (1<<0) 721 #define FBC_COMMAND 0x0320c 722 #define FBC_CMD_COMPRESS (1<<0) 723 #define FBC_STATUS 0x03210 724 #define FBC_STAT_COMPRESSING (1<<31) 725 #define FBC_STAT_COMPRESSED (1<<30) 726 #define FBC_STAT_MODIFIED (1<<29) 727 #define FBC_STAT_CURRENT_LINE (1<<0) 728 #define FBC_CONTROL2 0x03214 729 #define FBC_CTL_FENCE_DBL (0<<4) 730 #define FBC_CTL_IDLE_IMM (0<<2) 731 #define FBC_CTL_IDLE_FULL (1<<2) 732 #define FBC_CTL_IDLE_LINE (2<<2) 733 #define FBC_CTL_IDLE_DEBUG (3<<2) 734 #define FBC_CTL_CPU_FENCE (1<<1) 735 #define FBC_CTL_PLANEA (0<<0) 736 #define FBC_CTL_PLANEB (1<<0) 737 #define FBC_FENCE_OFF 0x0321b 738 #define FBC_TAG 0x03300 739 740 #define FBC_LL_SIZE (1536) 741 742 /* Framebuffer compression for GM45+ */ 743 #define DPFC_CB_BASE 0x3200 744 #define DPFC_CONTROL 0x3208 745 #define DPFC_CTL_EN (1<<31) 746 #define DPFC_CTL_PLANEA (0<<30) 747 #define DPFC_CTL_PLANEB (1<<30) 748 #define DPFC_CTL_FENCE_EN (1<<29) 749 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 750 #define DPFC_SR_EN (1<<10) 751 #define DPFC_CTL_LIMIT_1X (0<<6) 752 #define DPFC_CTL_LIMIT_2X (1<<6) 753 #define DPFC_CTL_LIMIT_4X (2<<6) 754 #define DPFC_RECOMP_CTL 0x320c 755 #define DPFC_RECOMP_STALL_EN (1<<27) 756 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 757 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 758 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 759 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 760 #define DPFC_STATUS 0x3210 761 #define DPFC_INVAL_SEG_SHIFT (16) 762 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 763 #define DPFC_COMP_SEG_SHIFT (0) 764 #define DPFC_COMP_SEG_MASK (0x000003ff) 765 #define DPFC_STATUS2 0x3214 766 #define DPFC_FENCE_YOFF 0x3218 767 #define DPFC_CHICKEN 0x3224 768 #define DPFC_HT_MODIFY (1<<31) 769 770 /* Framebuffer compression for Ironlake */ 771 #define ILK_DPFC_CB_BASE 0x43200 772 #define ILK_DPFC_CONTROL 0x43208 773 /* The bit 28-8 is reserved */ 774 #define DPFC_RESERVED (0x1FFFFF00) 775 #define ILK_DPFC_RECOMP_CTL 0x4320c 776 #define ILK_DPFC_STATUS 0x43210 777 #define ILK_DPFC_FENCE_YOFF 0x43218 778 #define ILK_DPFC_CHICKEN 0x43224 779 #define ILK_FBC_RT_BASE 0x2128 780 #define ILK_FBC_RT_VALID (1<<0) 781 782 #define ILK_DISPLAY_CHICKEN1 0x42000 783 #define ILK_FBCQ_DIS (1<<22) 784 #define ILK_PABSTRETCH_DIS (1<<21) 785 786 787 /* 788 * Framebuffer compression for Sandybridge 789 * 790 * The following two registers are of type GTTMMADR 791 */ 792 #define SNB_DPFC_CTL_SA 0x100100 793 #define SNB_CPU_FENCE_ENABLE (1<<29) 794 #define DPFC_CPU_FENCE_OFFSET 0x100104 795 796 797 /* 798 * GPIO regs 799 */ 800 #define GPIOA 0x5010 801 #define GPIOB 0x5014 802 #define GPIOC 0x5018 803 #define GPIOD 0x501c 804 #define GPIOE 0x5020 805 #define GPIOF 0x5024 806 #define GPIOG 0x5028 807 #define GPIOH 0x502c 808 # define GPIO_CLOCK_DIR_MASK (1 << 0) 809 # define GPIO_CLOCK_DIR_IN (0 << 1) 810 # define GPIO_CLOCK_DIR_OUT (1 << 1) 811 # define GPIO_CLOCK_VAL_MASK (1 << 2) 812 # define GPIO_CLOCK_VAL_OUT (1 << 3) 813 # define GPIO_CLOCK_VAL_IN (1 << 4) 814 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 815 # define GPIO_DATA_DIR_MASK (1 << 8) 816 # define GPIO_DATA_DIR_IN (0 << 9) 817 # define GPIO_DATA_DIR_OUT (1 << 9) 818 # define GPIO_DATA_VAL_MASK (1 << 10) 819 # define GPIO_DATA_VAL_OUT (1 << 11) 820 # define GPIO_DATA_VAL_IN (1 << 12) 821 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 822 823 #define GMBUS0 0x5100 /* clock/port select */ 824 #define GMBUS_RATE_100KHZ (0<<8) 825 #define GMBUS_RATE_50KHZ (1<<8) 826 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 827 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 828 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 829 #define GMBUS_PORT_DISABLED 0 830 #define GMBUS_PORT_SSC 1 831 #define GMBUS_PORT_VGADDC 2 832 #define GMBUS_PORT_PANEL 3 833 #define GMBUS_PORT_DPC 4 /* HDMIC */ 834 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 835 #define GMBUS_PORT_DPD 6 /* HDMID */ 836 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 837 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 838 #define GMBUS1 0x5104 /* command/status */ 839 #define GMBUS_SW_CLR_INT (1<<31) 840 #define GMBUS_SW_RDY (1<<30) 841 #define GMBUS_ENT (1<<29) /* enable timeout */ 842 #define GMBUS_CYCLE_NONE (0<<25) 843 #define GMBUS_CYCLE_WAIT (1<<25) 844 #define GMBUS_CYCLE_INDEX (2<<25) 845 #define GMBUS_CYCLE_STOP (4<<25) 846 #define GMBUS_BYTE_COUNT_SHIFT 16 847 #define GMBUS_SLAVE_INDEX_SHIFT 8 848 #define GMBUS_SLAVE_ADDR_SHIFT 1 849 #define GMBUS_SLAVE_READ (1<<0) 850 #define GMBUS_SLAVE_WRITE (0<<0) 851 #define GMBUS2 0x5108 /* status */ 852 #define GMBUS_INUSE (1<<15) 853 #define GMBUS_HW_WAIT_PHASE (1<<14) 854 #define GMBUS_STALL_TIMEOUT (1<<13) 855 #define GMBUS_INT (1<<12) 856 #define GMBUS_HW_RDY (1<<11) 857 #define GMBUS_SATOER (1<<10) 858 #define GMBUS_ACTIVE (1<<9) 859 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 860 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 861 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 862 #define GMBUS_NAK_EN (1<<3) 863 #define GMBUS_IDLE_EN (1<<2) 864 #define GMBUS_HW_WAIT_EN (1<<1) 865 #define GMBUS_HW_RDY_EN (1<<0) 866 #define GMBUS5 0x5120 /* byte index */ 867 #define GMBUS_2BYTE_INDEX_EN (1<<31) 868 869 /* 870 * Clock control & power management 871 */ 872 873 #define VGA0 0x6000 874 #define VGA1 0x6004 875 #define VGA_PD 0x6010 876 #define VGA0_PD_P2_DIV_4 (1 << 7) 877 #define VGA0_PD_P1_DIV_2 (1 << 5) 878 #define VGA0_PD_P1_SHIFT 0 879 #define VGA0_PD_P1_MASK (0x1f << 0) 880 #define VGA1_PD_P2_DIV_4 (1 << 15) 881 #define VGA1_PD_P1_DIV_2 (1 << 13) 882 #define VGA1_PD_P1_SHIFT 8 883 #define VGA1_PD_P1_MASK (0x1f << 8) 884 #define _DPLL_A 0x06014 885 #define _DPLL_B 0x06018 886 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) 887 #define DPLL_VCO_ENABLE (1 << 31) 888 #define DPLL_DVO_HIGH_SPEED (1 << 30) 889 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 890 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 891 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 892 #define DPLL_VGA_MODE_DIS (1 << 28) 893 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 894 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 895 #define DPLL_MODE_MASK (3 << 26) 896 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 897 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 898 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 899 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 900 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 901 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 902 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 903 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 904 905 #define SRX_INDEX 0x3c4 906 #define SRX_DATA 0x3c5 907 #define SR01 1 908 #define SR01_SCREEN_OFF (1<<5) 909 910 #define PPCR 0x61204 911 #define PPCR_ON (1<<0) 912 913 #define DVOB 0x61140 914 #define DVOB_ON (1<<31) 915 #define DVOC 0x61160 916 #define DVOC_ON (1<<31) 917 #define LVDS 0x61180 918 #define LVDS_ON (1<<31) 919 920 /* Scratch pad debug 0 reg: 921 */ 922 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 923 /* 924 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 925 * this field (only one bit may be set). 926 */ 927 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 928 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 929 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 930 /* i830, required in DVO non-gang */ 931 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 932 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 933 #define PLL_REF_INPUT_DREFCLK (0 << 13) 934 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 935 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 936 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 937 #define PLL_REF_INPUT_MASK (3 << 13) 938 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 939 /* Ironlake */ 940 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 941 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 942 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 943 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 944 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 945 946 /* 947 * Parallel to Serial Load Pulse phase selection. 948 * Selects the phase for the 10X DPLL clock for the PCIe 949 * digital display port. The range is 4 to 13; 10 or more 950 * is just a flip delay. The default is 6 951 */ 952 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 953 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 954 /* 955 * SDVO multiplier for 945G/GM. Not used on 965. 956 */ 957 #define SDVO_MULTIPLIER_MASK 0x000000ff 958 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 959 #define SDVO_MULTIPLIER_SHIFT_VGA 0 960 #define _DPLL_A_MD 0x0601c /* 965+ only */ 961 /* 962 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 963 * 964 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 965 */ 966 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 967 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 968 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 969 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 970 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 971 /* 972 * SDVO/UDI pixel multiplier. 973 * 974 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 975 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 976 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 977 * dummy bytes in the datastream at an increased clock rate, with both sides of 978 * the link knowing how many bytes are fill. 979 * 980 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 981 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 982 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 983 * through an SDVO command. 984 * 985 * This register field has values of multiplication factor minus 1, with 986 * a maximum multiplier of 5 for SDVO. 987 */ 988 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 989 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 990 /* 991 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 992 * This best be set to the default value (3) or the CRT won't work. No, 993 * I don't entirely understand what this does... 994 */ 995 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 996 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 997 #define _DPLL_B_MD 0x06020 /* 965+ only */ 998 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) 999 1000 #define _FPA0 0x06040 1001 #define _FPA1 0x06044 1002 #define _FPB0 0x06048 1003 #define _FPB1 0x0604c 1004 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1005 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1006 #define FP_N_DIV_MASK 0x003f0000 1007 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1008 #define FP_N_DIV_SHIFT 16 1009 #define FP_M1_DIV_MASK 0x00003f00 1010 #define FP_M1_DIV_SHIFT 8 1011 #define FP_M2_DIV_MASK 0x0000003f 1012 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1013 #define FP_M2_DIV_SHIFT 0 1014 #define DPLL_TEST 0x606c 1015 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1016 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1017 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1018 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1019 #define DPLLB_TEST_N_BYPASS (1 << 19) 1020 #define DPLLB_TEST_M_BYPASS (1 << 18) 1021 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1022 #define DPLLA_TEST_N_BYPASS (1 << 3) 1023 #define DPLLA_TEST_M_BYPASS (1 << 2) 1024 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1025 #define D_STATE 0x6104 1026 #define DSTATE_GFX_RESET_I830 (1<<6) 1027 #define DSTATE_PLL_D3_OFF (1<<3) 1028 #define DSTATE_GFX_CLOCK_GATING (1<<1) 1029 #define DSTATE_DOT_CLOCK_GATING (1<<0) 1030 #define DSPCLK_GATE_D 0x6200 1031 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1032 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1033 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1034 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1035 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1036 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1037 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1038 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1039 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1040 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1041 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1042 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1043 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1044 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1045 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1046 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1047 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1048 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1049 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1050 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1051 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1052 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1053 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1054 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1055 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1056 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1057 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1058 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1059 /** 1060 * This bit must be set on the 830 to prevent hangs when turning off the 1061 * overlay scaler. 1062 */ 1063 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1064 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1065 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1066 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1067 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1068 1069 #define RENCLK_GATE_D1 0x6204 1070 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1071 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1072 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1073 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1074 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1075 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1076 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1077 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1078 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1079 /** This bit must be unset on 855,865 */ 1080 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1081 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1082 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1083 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1084 /** This bit must be set on 855,865. */ 1085 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1086 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1087 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1088 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1089 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1090 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1091 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1092 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1093 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1094 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1095 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1096 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1097 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1098 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1099 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1100 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1101 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1102 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1103 1104 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1105 /** This bit must always be set on 965G/965GM */ 1106 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1107 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1108 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1109 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1110 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1111 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1112 /** This bit must always be set on 965G */ 1113 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1114 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1115 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1116 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1117 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1118 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1119 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1120 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1121 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1122 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1123 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1124 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1125 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1126 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1127 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1128 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1129 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1130 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1131 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1132 1133 #define RENCLK_GATE_D2 0x6208 1134 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1135 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1136 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1137 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1138 #define DEUC 0x6214 /* CRL only */ 1139 1140 #define FW_BLC_SELF_VLV 0x6500 1141 #define FW_CSPWRDWNEN (1<<15) 1142 1143 /* 1144 * Palette regs 1145 */ 1146 1147 #define _PALETTE_A 0x0a000 1148 #define _PALETTE_B 0x0a800 1149 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1150 1151 /* MCH MMIO space */ 1152 1153 /* 1154 * MCHBAR mirror. 1155 * 1156 * This mirrors the MCHBAR MMIO space whose location is determined by 1157 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1158 * every way. It is not accessible from the CP register read instructions. 1159 * 1160 */ 1161 #define MCHBAR_MIRROR_BASE 0x10000 1162 1163 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1164 1165 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 1166 #define DCC 0x10200 1167 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1168 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1169 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1170 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1171 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1172 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1173 1174 /** Pineview MCH register contains DDR3 setting */ 1175 #define CSHRDDR3CTL 0x101a8 1176 #define CSHRDDR3CTL_DDR3 (1 << 2) 1177 1178 /** 965 MCH register controlling DRAM channel configuration */ 1179 #define C0DRB3 0x10206 1180 #define C1DRB3 0x10606 1181 1182 /** snb MCH registers for reading the DRAM channel configuration */ 1183 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 1184 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 1185 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 1186 #define MAD_DIMM_ECC_MASK (0x3 << 24) 1187 #define MAD_DIMM_ECC_OFF (0x0 << 24) 1188 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 1189 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 1190 #define MAD_DIMM_ECC_ON (0x3 << 24) 1191 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 1192 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 1193 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 1194 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 1195 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 1196 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 1197 #define MAD_DIMM_A_SELECT (0x1 << 16) 1198 /* DIMM sizes are in multiples of 256mb. */ 1199 #define MAD_DIMM_B_SIZE_SHIFT 8 1200 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 1201 #define MAD_DIMM_A_SIZE_SHIFT 0 1202 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 1203 1204 1205 /* Clocking configuration register */ 1206 #define CLKCFG 0x10c00 1207 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1208 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1209 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1210 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1211 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1212 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1213 /* Note, below two are guess */ 1214 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1215 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1216 #define CLKCFG_FSB_MASK (7 << 0) 1217 #define CLKCFG_MEM_533 (1 << 4) 1218 #define CLKCFG_MEM_667 (2 << 4) 1219 #define CLKCFG_MEM_800 (3 << 4) 1220 #define CLKCFG_MEM_MASK (7 << 4) 1221 1222 #define TSC1 0x11001 1223 #define TSE (1<<0) 1224 #define TR1 0x11006 1225 #define TSFS 0x11020 1226 #define TSFS_SLOPE_MASK 0x0000ff00 1227 #define TSFS_SLOPE_SHIFT 8 1228 #define TSFS_INTR_MASK 0x000000ff 1229 1230 #define CRSTANDVID 0x11100 1231 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1232 #define PXVFREQ_PX_MASK 0x7f000000 1233 #define PXVFREQ_PX_SHIFT 24 1234 #define VIDFREQ_BASE 0x11110 1235 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1236 #define VIDFREQ2 0x11114 1237 #define VIDFREQ3 0x11118 1238 #define VIDFREQ4 0x1111c 1239 #define VIDFREQ_P0_MASK 0x1f000000 1240 #define VIDFREQ_P0_SHIFT 24 1241 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1242 #define VIDFREQ_P0_CSCLK_SHIFT 20 1243 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1244 #define VIDFREQ_P0_CRCLK_SHIFT 16 1245 #define VIDFREQ_P1_MASK 0x00001f00 1246 #define VIDFREQ_P1_SHIFT 8 1247 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1248 #define VIDFREQ_P1_CSCLK_SHIFT 4 1249 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1250 #define INTTOEXT_BASE_ILK 0x11300 1251 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1252 #define INTTOEXT_MAP3_SHIFT 24 1253 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1254 #define INTTOEXT_MAP2_SHIFT 16 1255 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1256 #define INTTOEXT_MAP1_SHIFT 8 1257 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1258 #define INTTOEXT_MAP0_SHIFT 0 1259 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1260 #define MEMSWCTL 0x11170 /* Ironlake only */ 1261 #define MEMCTL_CMD_MASK 0xe000 1262 #define MEMCTL_CMD_SHIFT 13 1263 #define MEMCTL_CMD_RCLK_OFF 0 1264 #define MEMCTL_CMD_RCLK_ON 1 1265 #define MEMCTL_CMD_CHFREQ 2 1266 #define MEMCTL_CMD_CHVID 3 1267 #define MEMCTL_CMD_VMMOFF 4 1268 #define MEMCTL_CMD_VMMON 5 1269 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1270 when command complete */ 1271 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1272 #define MEMCTL_FREQ_SHIFT 8 1273 #define MEMCTL_SFCAVM (1<<7) 1274 #define MEMCTL_TGT_VID_MASK 0x007f 1275 #define MEMIHYST 0x1117c 1276 #define MEMINTREN 0x11180 /* 16 bits */ 1277 #define MEMINT_RSEXIT_EN (1<<8) 1278 #define MEMINT_CX_SUPR_EN (1<<7) 1279 #define MEMINT_CONT_BUSY_EN (1<<6) 1280 #define MEMINT_AVG_BUSY_EN (1<<5) 1281 #define MEMINT_EVAL_CHG_EN (1<<4) 1282 #define MEMINT_MON_IDLE_EN (1<<3) 1283 #define MEMINT_UP_EVAL_EN (1<<2) 1284 #define MEMINT_DOWN_EVAL_EN (1<<1) 1285 #define MEMINT_SW_CMD_EN (1<<0) 1286 #define MEMINTRSTR 0x11182 /* 16 bits */ 1287 #define MEM_RSEXIT_MASK 0xc000 1288 #define MEM_RSEXIT_SHIFT 14 1289 #define MEM_CONT_BUSY_MASK 0x3000 1290 #define MEM_CONT_BUSY_SHIFT 12 1291 #define MEM_AVG_BUSY_MASK 0x0c00 1292 #define MEM_AVG_BUSY_SHIFT 10 1293 #define MEM_EVAL_CHG_MASK 0x0300 1294 #define MEM_EVAL_BUSY_SHIFT 8 1295 #define MEM_MON_IDLE_MASK 0x00c0 1296 #define MEM_MON_IDLE_SHIFT 6 1297 #define MEM_UP_EVAL_MASK 0x0030 1298 #define MEM_UP_EVAL_SHIFT 4 1299 #define MEM_DOWN_EVAL_MASK 0x000c 1300 #define MEM_DOWN_EVAL_SHIFT 2 1301 #define MEM_SW_CMD_MASK 0x0003 1302 #define MEM_INT_STEER_GFX 0 1303 #define MEM_INT_STEER_CMR 1 1304 #define MEM_INT_STEER_SMI 2 1305 #define MEM_INT_STEER_SCI 3 1306 #define MEMINTRSTS 0x11184 1307 #define MEMINT_RSEXIT (1<<7) 1308 #define MEMINT_CONT_BUSY (1<<6) 1309 #define MEMINT_AVG_BUSY (1<<5) 1310 #define MEMINT_EVAL_CHG (1<<4) 1311 #define MEMINT_MON_IDLE (1<<3) 1312 #define MEMINT_UP_EVAL (1<<2) 1313 #define MEMINT_DOWN_EVAL (1<<1) 1314 #define MEMINT_SW_CMD (1<<0) 1315 #define MEMMODECTL 0x11190 1316 #define MEMMODE_BOOST_EN (1<<31) 1317 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1318 #define MEMMODE_BOOST_FREQ_SHIFT 24 1319 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1320 #define MEMMODE_IDLE_MODE_SHIFT 16 1321 #define MEMMODE_IDLE_MODE_EVAL 0 1322 #define MEMMODE_IDLE_MODE_CONT 1 1323 #define MEMMODE_HWIDLE_EN (1<<15) 1324 #define MEMMODE_SWMODE_EN (1<<14) 1325 #define MEMMODE_RCLK_GATE (1<<13) 1326 #define MEMMODE_HW_UPDATE (1<<12) 1327 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1328 #define MEMMODE_FSTART_SHIFT 8 1329 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1330 #define MEMMODE_FMAX_SHIFT 4 1331 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1332 #define RCBMAXAVG 0x1119c 1333 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1334 #define SWMEMCMD_RENDER_OFF (0 << 13) 1335 #define SWMEMCMD_RENDER_ON (1 << 13) 1336 #define SWMEMCMD_SWFREQ (2 << 13) 1337 #define SWMEMCMD_TARVID (3 << 13) 1338 #define SWMEMCMD_VRM_OFF (4 << 13) 1339 #define SWMEMCMD_VRM_ON (5 << 13) 1340 #define CMDSTS (1<<12) 1341 #define SFCAVM (1<<11) 1342 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1343 #define SWFREQ_SHIFT 7 1344 #define TARVID_MASK 0x001f 1345 #define MEMSTAT_CTG 0x111a0 1346 #define RCBMINAVG 0x111a0 1347 #define RCUPEI 0x111b0 1348 #define RCDNEI 0x111b4 1349 #define RSTDBYCTL 0x111b8 1350 #define RS1EN (1<<31) 1351 #define RS2EN (1<<30) 1352 #define RS3EN (1<<29) 1353 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1354 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1355 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1356 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1357 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1358 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1359 #define RSX_STATUS_MASK (7<<20) 1360 #define RSX_STATUS_ON (0<<20) 1361 #define RSX_STATUS_RC1 (1<<20) 1362 #define RSX_STATUS_RC1E (2<<20) 1363 #define RSX_STATUS_RS1 (3<<20) 1364 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1365 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1366 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1367 #define RSX_STATUS_RSVD2 (7<<20) 1368 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1369 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1370 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1371 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1372 #define RS1CONTSAV_MASK (3<<14) 1373 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1374 #define RS1CONTSAV_RSVD (1<<14) 1375 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1376 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1377 #define NORMSLEXLAT_MASK (3<<12) 1378 #define SLOW_RS123 (0<<12) 1379 #define SLOW_RS23 (1<<12) 1380 #define SLOW_RS3 (2<<12) 1381 #define NORMAL_RS123 (3<<12) 1382 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1383 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1384 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1385 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1386 #define RS_CSTATE_MASK (3<<4) 1387 #define RS_CSTATE_C367_RS1 (0<<4) 1388 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1389 #define RS_CSTATE_RSVD (2<<4) 1390 #define RS_CSTATE_C367_RS2 (3<<4) 1391 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1392 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1393 #define VIDCTL 0x111c0 1394 #define VIDSTS 0x111c8 1395 #define VIDSTART 0x111cc /* 8 bits */ 1396 #define MEMSTAT_ILK 0x111f8 1397 #define MEMSTAT_VID_MASK 0x7f00 1398 #define MEMSTAT_VID_SHIFT 8 1399 #define MEMSTAT_PSTATE_MASK 0x00f8 1400 #define MEMSTAT_PSTATE_SHIFT 3 1401 #define MEMSTAT_MON_ACTV (1<<2) 1402 #define MEMSTAT_SRC_CTL_MASK 0x0003 1403 #define MEMSTAT_SRC_CTL_CORE 0 1404 #define MEMSTAT_SRC_CTL_TRB 1 1405 #define MEMSTAT_SRC_CTL_THM 2 1406 #define MEMSTAT_SRC_CTL_STDBY 3 1407 #define RCPREVBSYTUPAVG 0x113b8 1408 #define RCPREVBSYTDNAVG 0x113bc 1409 #define PMMISC 0x11214 1410 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1411 #define SDEW 0x1124c 1412 #define CSIEW0 0x11250 1413 #define CSIEW1 0x11254 1414 #define CSIEW2 0x11258 1415 #define PEW 0x1125c 1416 #define DEW 0x11270 1417 #define MCHAFE 0x112c0 1418 #define CSIEC 0x112e0 1419 #define DMIEC 0x112e4 1420 #define DDREC 0x112e8 1421 #define PEG0EC 0x112ec 1422 #define PEG1EC 0x112f0 1423 #define GFXEC 0x112f4 1424 #define RPPREVBSYTUPAVG 0x113b8 1425 #define RPPREVBSYTDNAVG 0x113bc 1426 #define ECR 0x11600 1427 #define ECR_GPFE (1<<31) 1428 #define ECR_IMONE (1<<30) 1429 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1430 #define OGW0 0x11608 1431 #define OGW1 0x1160c 1432 #define EG0 0x11610 1433 #define EG1 0x11614 1434 #define EG2 0x11618 1435 #define EG3 0x1161c 1436 #define EG4 0x11620 1437 #define EG5 0x11624 1438 #define EG6 0x11628 1439 #define EG7 0x1162c 1440 #define PXW 0x11664 1441 #define PXWL 0x11680 1442 #define LCFUSE02 0x116c0 1443 #define LCFUSE_HIV_MASK 0x000000ff 1444 #define CSIPLL0 0x12c10 1445 #define DDRMPLL1 0X12c20 1446 #define PEG_BAND_GAP_DATA 0x14d68 1447 1448 #define GEN6_GT_PERF_STATUS 0x145948 1449 #define GEN6_RP_STATE_LIMITS 0x145994 1450 #define GEN6_RP_STATE_CAP 0x145998 1451 1452 /* 1453 * Logical Context regs 1454 */ 1455 #define CCID 0x2180 1456 #define CCID_EN (1<<0) 1457 /* 1458 * Overlay regs 1459 */ 1460 1461 #define OVADD 0x30000 1462 #define DOVSTA 0x30008 1463 #define OC_BUF (0x3<<20) 1464 #define OGAMC5 0x30010 1465 #define OGAMC4 0x30014 1466 #define OGAMC3 0x30018 1467 #define OGAMC2 0x3001c 1468 #define OGAMC1 0x30020 1469 #define OGAMC0 0x30024 1470 1471 /* 1472 * Display engine regs 1473 */ 1474 1475 /* Pipe A timing regs */ 1476 #define _HTOTAL_A 0x60000 1477 #define _HBLANK_A 0x60004 1478 #define _HSYNC_A 0x60008 1479 #define _VTOTAL_A 0x6000c 1480 #define _VBLANK_A 0x60010 1481 #define _VSYNC_A 0x60014 1482 #define _PIPEASRC 0x6001c 1483 #define _BCLRPAT_A 0x60020 1484 #define _VSYNCSHIFT_A 0x60028 1485 1486 /* Pipe B timing regs */ 1487 #define _HTOTAL_B 0x61000 1488 #define _HBLANK_B 0x61004 1489 #define _HSYNC_B 0x61008 1490 #define _VTOTAL_B 0x6100c 1491 #define _VBLANK_B 0x61010 1492 #define _VSYNC_B 0x61014 1493 #define _PIPEBSRC 0x6101c 1494 #define _BCLRPAT_B 0x61020 1495 #define _VSYNCSHIFT_B 0x61028 1496 1497 1498 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) 1499 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) 1500 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) 1501 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) 1502 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) 1503 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) 1504 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1505 #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B) 1506 1507 /* VGA port control */ 1508 #define ADPA 0x61100 1509 #define ADPA_DAC_ENABLE (1<<31) 1510 #define ADPA_DAC_DISABLE 0 1511 #define ADPA_PIPE_SELECT_MASK (1<<30) 1512 #define ADPA_PIPE_A_SELECT 0 1513 #define ADPA_PIPE_B_SELECT (1<<30) 1514 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 1515 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1516 #define ADPA_SETS_HVPOLARITY 0 1517 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1518 #define ADPA_VSYNC_CNTL_ENABLE 0 1519 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1520 #define ADPA_HSYNC_CNTL_ENABLE 0 1521 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1522 #define ADPA_VSYNC_ACTIVE_LOW 0 1523 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1524 #define ADPA_HSYNC_ACTIVE_LOW 0 1525 #define ADPA_DPMS_MASK (~(3<<10)) 1526 #define ADPA_DPMS_ON (0<<10) 1527 #define ADPA_DPMS_SUSPEND (1<<10) 1528 #define ADPA_DPMS_STANDBY (2<<10) 1529 #define ADPA_DPMS_OFF (3<<10) 1530 1531 1532 /* Hotplug control (945+ only) */ 1533 #define PORT_HOTPLUG_EN 0x61110 1534 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1535 #define DPB_HOTPLUG_INT_EN (1 << 29) 1536 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1537 #define DPC_HOTPLUG_INT_EN (1 << 28) 1538 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1539 #define DPD_HOTPLUG_INT_EN (1 << 27) 1540 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1541 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1542 #define TV_HOTPLUG_INT_EN (1 << 18) 1543 #define CRT_HOTPLUG_INT_EN (1 << 9) 1544 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1545 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1546 /* must use period 64 on GM45 according to docs */ 1547 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1548 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1549 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1550 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1551 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1552 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1553 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1554 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1555 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1556 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1557 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1558 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1559 1560 #define PORT_HOTPLUG_STAT 0x61114 1561 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1562 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 1563 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1564 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 1565 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1566 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 1567 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1568 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1569 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1570 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1571 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1572 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1573 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1574 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1575 1576 /* SDVO port control */ 1577 #define SDVOB 0x61140 1578 #define SDVOC 0x61160 1579 #define SDVO_ENABLE (1 << 31) 1580 #define SDVO_PIPE_B_SELECT (1 << 30) 1581 #define SDVO_STALL_SELECT (1 << 29) 1582 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1583 /** 1584 * 915G/GM SDVO pixel multiplier. 1585 * 1586 * Programmed value is multiplier - 1, up to 5x. 1587 * 1588 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1589 */ 1590 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1591 #define SDVO_PORT_MULTIPLY_SHIFT 23 1592 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1593 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1594 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1595 #define SDVOC_GANG_MODE (1 << 16) 1596 #define SDVO_ENCODING_SDVO (0x0 << 10) 1597 #define SDVO_ENCODING_HDMI (0x2 << 10) 1598 /** Requird for HDMI operation */ 1599 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1600 #define SDVO_COLOR_RANGE_16_235 (1 << 8) 1601 #define SDVO_BORDER_ENABLE (1 << 7) 1602 #define SDVO_AUDIO_ENABLE (1 << 6) 1603 /** New with 965, default is to be set */ 1604 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1605 /** New with 965, default is to be set */ 1606 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1607 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1608 #define SDVO_DETECTED (1 << 2) 1609 /* Bits to be preserved when writing */ 1610 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1611 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1612 1613 /* DVO port control */ 1614 #define DVOA 0x61120 1615 #define DVOB 0x61140 1616 #define DVOC 0x61160 1617 #define DVO_ENABLE (1 << 31) 1618 #define DVO_PIPE_B_SELECT (1 << 30) 1619 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1620 #define DVO_PIPE_STALL (1 << 28) 1621 #define DVO_PIPE_STALL_TV (2 << 28) 1622 #define DVO_PIPE_STALL_MASK (3 << 28) 1623 #define DVO_USE_VGA_SYNC (1 << 15) 1624 #define DVO_DATA_ORDER_I740 (0 << 14) 1625 #define DVO_DATA_ORDER_FP (1 << 14) 1626 #define DVO_VSYNC_DISABLE (1 << 11) 1627 #define DVO_HSYNC_DISABLE (1 << 10) 1628 #define DVO_VSYNC_TRISTATE (1 << 9) 1629 #define DVO_HSYNC_TRISTATE (1 << 8) 1630 #define DVO_BORDER_ENABLE (1 << 7) 1631 #define DVO_DATA_ORDER_GBRG (1 << 6) 1632 #define DVO_DATA_ORDER_RGGB (0 << 6) 1633 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1634 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1635 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1636 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1637 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1638 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1639 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1640 #define DVO_PRESERVE_MASK (0x7<<24) 1641 #define DVOA_SRCDIM 0x61124 1642 #define DVOB_SRCDIM 0x61144 1643 #define DVOC_SRCDIM 0x61164 1644 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1645 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1646 1647 /* LVDS port control */ 1648 #define LVDS 0x61180 1649 /* 1650 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1651 * the DPLL semantics change when the LVDS is assigned to that pipe. 1652 */ 1653 #define LVDS_PORT_EN (1 << 31) 1654 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1655 #define LVDS_PIPEB_SELECT (1 << 30) 1656 #define LVDS_PIPE_MASK (1 << 30) 1657 #define LVDS_PIPE(pipe) ((pipe) << 30) 1658 /* LVDS dithering flag on 965/g4x platform */ 1659 #define LVDS_ENABLE_DITHER (1 << 25) 1660 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 1661 #define LVDS_VSYNC_POLARITY (1 << 21) 1662 #define LVDS_HSYNC_POLARITY (1 << 20) 1663 1664 /* Enable border for unscaled (or aspect-scaled) display */ 1665 #define LVDS_BORDER_ENABLE (1 << 15) 1666 /* 1667 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1668 * pixel. 1669 */ 1670 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1671 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1672 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1673 /* 1674 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1675 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1676 * on. 1677 */ 1678 #define LVDS_A3_POWER_MASK (3 << 6) 1679 #define LVDS_A3_POWER_DOWN (0 << 6) 1680 #define LVDS_A3_POWER_UP (3 << 6) 1681 /* 1682 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1683 * is set. 1684 */ 1685 #define LVDS_CLKB_POWER_MASK (3 << 4) 1686 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1687 #define LVDS_CLKB_POWER_UP (3 << 4) 1688 /* 1689 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1690 * setting for whether we are in dual-channel mode. The B3 pair will 1691 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1692 */ 1693 #define LVDS_B0B3_POWER_MASK (3 << 2) 1694 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1695 #define LVDS_B0B3_POWER_UP (3 << 2) 1696 1697 /* Video Data Island Packet control */ 1698 #define VIDEO_DIP_DATA 0x61178 1699 #define VIDEO_DIP_CTL 0x61170 1700 /* Pre HSW: */ 1701 #define VIDEO_DIP_ENABLE (1 << 31) 1702 #define VIDEO_DIP_PORT_B (1 << 29) 1703 #define VIDEO_DIP_PORT_C (2 << 29) 1704 #define VIDEO_DIP_PORT_D (3 << 29) 1705 #define VIDEO_DIP_PORT_MASK (3 << 29) 1706 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1707 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1708 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1709 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1710 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1711 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1712 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1713 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1714 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1715 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1716 #define VIDEO_DIP_FREQ_MASK (3 << 16) 1717 /* HSW and later: */ 1718 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 1719 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 1720 1721 /* Panel power sequencing */ 1722 #define PP_STATUS 0x61200 1723 #define PP_ON (1 << 31) 1724 /* 1725 * Indicates that all dependencies of the panel are on: 1726 * 1727 * - PLL enabled 1728 * - pipe enabled 1729 * - LVDS/DVOB/DVOC on 1730 */ 1731 #define PP_READY (1 << 30) 1732 #define PP_SEQUENCE_NONE (0 << 28) 1733 #define PP_SEQUENCE_POWER_UP (1 << 28) 1734 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 1735 #define PP_SEQUENCE_MASK (3 << 28) 1736 #define PP_SEQUENCE_SHIFT 28 1737 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1738 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1739 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 1740 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 1741 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 1742 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 1743 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 1744 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 1745 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 1746 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 1747 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 1748 #define PP_CONTROL 0x61204 1749 #define POWER_TARGET_ON (1 << 0) 1750 #define PP_ON_DELAYS 0x61208 1751 #define PP_OFF_DELAYS 0x6120c 1752 #define PP_DIVISOR 0x61210 1753 1754 /* Panel fitting */ 1755 #define PFIT_CONTROL 0x61230 1756 #define PFIT_ENABLE (1 << 31) 1757 #define PFIT_PIPE_MASK (3 << 29) 1758 #define PFIT_PIPE_SHIFT 29 1759 #define VERT_INTERP_DISABLE (0 << 10) 1760 #define VERT_INTERP_BILINEAR (1 << 10) 1761 #define VERT_INTERP_MASK (3 << 10) 1762 #define VERT_AUTO_SCALE (1 << 9) 1763 #define HORIZ_INTERP_DISABLE (0 << 6) 1764 #define HORIZ_INTERP_BILINEAR (1 << 6) 1765 #define HORIZ_INTERP_MASK (3 << 6) 1766 #define HORIZ_AUTO_SCALE (1 << 5) 1767 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1768 #define PFIT_FILTER_FUZZY (0 << 24) 1769 #define PFIT_SCALING_AUTO (0 << 26) 1770 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1771 #define PFIT_SCALING_PILLAR (2 << 26) 1772 #define PFIT_SCALING_LETTER (3 << 26) 1773 #define PFIT_PGM_RATIOS 0x61234 1774 #define PFIT_VERT_SCALE_MASK 0xfff00000 1775 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1776 /* Pre-965 */ 1777 #define PFIT_VERT_SCALE_SHIFT 20 1778 #define PFIT_VERT_SCALE_MASK 0xfff00000 1779 #define PFIT_HORIZ_SCALE_SHIFT 4 1780 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1781 /* 965+ */ 1782 #define PFIT_VERT_SCALE_SHIFT_965 16 1783 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1784 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1785 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1786 1787 #define PFIT_AUTO_RATIOS 0x61238 1788 1789 /* Backlight control */ 1790 #define BLC_PWM_CTL 0x61254 1791 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1792 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1793 #define BLM_COMBINATION_MODE (1 << 30) 1794 /* 1795 * This is the most significant 15 bits of the number of backlight cycles in a 1796 * complete cycle of the modulated backlight control. 1797 * 1798 * The actual value is this field multiplied by two. 1799 */ 1800 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1801 #define BLM_LEGACY_MODE (1 << 16) 1802 /* 1803 * This is the number of cycles out of the backlight modulation cycle for which 1804 * the backlight is on. 1805 * 1806 * This field must be no greater than the number of cycles in the complete 1807 * backlight modulation cycle. 1808 */ 1809 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1810 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1811 1812 #define BLC_HIST_CTL 0x61260 1813 1814 /* TV port control */ 1815 #define TV_CTL 0x68000 1816 /** Enables the TV encoder */ 1817 # define TV_ENC_ENABLE (1 << 31) 1818 /** Sources the TV encoder input from pipe B instead of A. */ 1819 # define TV_ENC_PIPEB_SELECT (1 << 30) 1820 /** Outputs composite video (DAC A only) */ 1821 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1822 /** Outputs SVideo video (DAC B/C) */ 1823 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1824 /** Outputs Component video (DAC A/B/C) */ 1825 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1826 /** Outputs Composite and SVideo (DAC A/B/C) */ 1827 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1828 # define TV_TRILEVEL_SYNC (1 << 21) 1829 /** Enables slow sync generation (945GM only) */ 1830 # define TV_SLOW_SYNC (1 << 20) 1831 /** Selects 4x oversampling for 480i and 576p */ 1832 # define TV_OVERSAMPLE_4X (0 << 18) 1833 /** Selects 2x oversampling for 720p and 1080i */ 1834 # define TV_OVERSAMPLE_2X (1 << 18) 1835 /** Selects no oversampling for 1080p */ 1836 # define TV_OVERSAMPLE_NONE (2 << 18) 1837 /** Selects 8x oversampling */ 1838 # define TV_OVERSAMPLE_8X (3 << 18) 1839 /** Selects progressive mode rather than interlaced */ 1840 # define TV_PROGRESSIVE (1 << 17) 1841 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1842 # define TV_PAL_BURST (1 << 16) 1843 /** Field for setting delay of Y compared to C */ 1844 # define TV_YC_SKEW_MASK (7 << 12) 1845 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1846 # define TV_ENC_SDP_FIX (1 << 11) 1847 /** 1848 * Enables a fix for the 915GM only. 1849 * 1850 * Not sure what it does. 1851 */ 1852 # define TV_ENC_C0_FIX (1 << 10) 1853 /** Bits that must be preserved by software */ 1854 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1855 # define TV_FUSE_STATE_MASK (3 << 4) 1856 /** Read-only state that reports all features enabled */ 1857 # define TV_FUSE_STATE_ENABLED (0 << 4) 1858 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1859 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1860 /** Read-only state that reports that TV-out is disabled in hardware. */ 1861 # define TV_FUSE_STATE_DISABLED (2 << 4) 1862 /** Normal operation */ 1863 # define TV_TEST_MODE_NORMAL (0 << 0) 1864 /** Encoder test pattern 1 - combo pattern */ 1865 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1866 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1867 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1868 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1869 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1870 /** Encoder test pattern 4 - random noise */ 1871 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1872 /** Encoder test pattern 5 - linear color ramps */ 1873 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1874 /** 1875 * This test mode forces the DACs to 50% of full output. 1876 * 1877 * This is used for load detection in combination with TVDAC_SENSE_MASK 1878 */ 1879 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1880 # define TV_TEST_MODE_MASK (7 << 0) 1881 1882 #define TV_DAC 0x68004 1883 # define TV_DAC_SAVE 0x00ffff00 1884 /** 1885 * Reports that DAC state change logic has reported change (RO). 1886 * 1887 * This gets cleared when TV_DAC_STATE_EN is cleared 1888 */ 1889 # define TVDAC_STATE_CHG (1 << 31) 1890 # define TVDAC_SENSE_MASK (7 << 28) 1891 /** Reports that DAC A voltage is above the detect threshold */ 1892 # define TVDAC_A_SENSE (1 << 30) 1893 /** Reports that DAC B voltage is above the detect threshold */ 1894 # define TVDAC_B_SENSE (1 << 29) 1895 /** Reports that DAC C voltage is above the detect threshold */ 1896 # define TVDAC_C_SENSE (1 << 28) 1897 /** 1898 * Enables DAC state detection logic, for load-based TV detection. 1899 * 1900 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1901 * to off, for load detection to work. 1902 */ 1903 # define TVDAC_STATE_CHG_EN (1 << 27) 1904 /** Sets the DAC A sense value to high */ 1905 # define TVDAC_A_SENSE_CTL (1 << 26) 1906 /** Sets the DAC B sense value to high */ 1907 # define TVDAC_B_SENSE_CTL (1 << 25) 1908 /** Sets the DAC C sense value to high */ 1909 # define TVDAC_C_SENSE_CTL (1 << 24) 1910 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1911 # define DAC_CTL_OVERRIDE (1 << 7) 1912 /** Sets the slew rate. Must be preserved in software */ 1913 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1914 # define DAC_A_1_3_V (0 << 4) 1915 # define DAC_A_1_1_V (1 << 4) 1916 # define DAC_A_0_7_V (2 << 4) 1917 # define DAC_A_MASK (3 << 4) 1918 # define DAC_B_1_3_V (0 << 2) 1919 # define DAC_B_1_1_V (1 << 2) 1920 # define DAC_B_0_7_V (2 << 2) 1921 # define DAC_B_MASK (3 << 2) 1922 # define DAC_C_1_3_V (0 << 0) 1923 # define DAC_C_1_1_V (1 << 0) 1924 # define DAC_C_0_7_V (2 << 0) 1925 # define DAC_C_MASK (3 << 0) 1926 1927 /** 1928 * CSC coefficients are stored in a floating point format with 9 bits of 1929 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1930 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1931 * -1 (0x3) being the only legal negative value. 1932 */ 1933 #define TV_CSC_Y 0x68010 1934 # define TV_RY_MASK 0x07ff0000 1935 # define TV_RY_SHIFT 16 1936 # define TV_GY_MASK 0x00000fff 1937 # define TV_GY_SHIFT 0 1938 1939 #define TV_CSC_Y2 0x68014 1940 # define TV_BY_MASK 0x07ff0000 1941 # define TV_BY_SHIFT 16 1942 /** 1943 * Y attenuation for component video. 1944 * 1945 * Stored in 1.9 fixed point. 1946 */ 1947 # define TV_AY_MASK 0x000003ff 1948 # define TV_AY_SHIFT 0 1949 1950 #define TV_CSC_U 0x68018 1951 # define TV_RU_MASK 0x07ff0000 1952 # define TV_RU_SHIFT 16 1953 # define TV_GU_MASK 0x000007ff 1954 # define TV_GU_SHIFT 0 1955 1956 #define TV_CSC_U2 0x6801c 1957 # define TV_BU_MASK 0x07ff0000 1958 # define TV_BU_SHIFT 16 1959 /** 1960 * U attenuation for component video. 1961 * 1962 * Stored in 1.9 fixed point. 1963 */ 1964 # define TV_AU_MASK 0x000003ff 1965 # define TV_AU_SHIFT 0 1966 1967 #define TV_CSC_V 0x68020 1968 # define TV_RV_MASK 0x0fff0000 1969 # define TV_RV_SHIFT 16 1970 # define TV_GV_MASK 0x000007ff 1971 # define TV_GV_SHIFT 0 1972 1973 #define TV_CSC_V2 0x68024 1974 # define TV_BV_MASK 0x07ff0000 1975 # define TV_BV_SHIFT 16 1976 /** 1977 * V attenuation for component video. 1978 * 1979 * Stored in 1.9 fixed point. 1980 */ 1981 # define TV_AV_MASK 0x000007ff 1982 # define TV_AV_SHIFT 0 1983 1984 #define TV_CLR_KNOBS 0x68028 1985 /** 2s-complement brightness adjustment */ 1986 # define TV_BRIGHTNESS_MASK 0xff000000 1987 # define TV_BRIGHTNESS_SHIFT 24 1988 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1989 # define TV_CONTRAST_MASK 0x00ff0000 1990 # define TV_CONTRAST_SHIFT 16 1991 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1992 # define TV_SATURATION_MASK 0x0000ff00 1993 # define TV_SATURATION_SHIFT 8 1994 /** Hue adjustment, as an integer phase angle in degrees */ 1995 # define TV_HUE_MASK 0x000000ff 1996 # define TV_HUE_SHIFT 0 1997 1998 #define TV_CLR_LEVEL 0x6802c 1999 /** Controls the DAC level for black */ 2000 # define TV_BLACK_LEVEL_MASK 0x01ff0000 2001 # define TV_BLACK_LEVEL_SHIFT 16 2002 /** Controls the DAC level for blanking */ 2003 # define TV_BLANK_LEVEL_MASK 0x000001ff 2004 # define TV_BLANK_LEVEL_SHIFT 0 2005 2006 #define TV_H_CTL_1 0x68030 2007 /** Number of pixels in the hsync. */ 2008 # define TV_HSYNC_END_MASK 0x1fff0000 2009 # define TV_HSYNC_END_SHIFT 16 2010 /** Total number of pixels minus one in the line (display and blanking). */ 2011 # define TV_HTOTAL_MASK 0x00001fff 2012 # define TV_HTOTAL_SHIFT 0 2013 2014 #define TV_H_CTL_2 0x68034 2015 /** Enables the colorburst (needed for non-component color) */ 2016 # define TV_BURST_ENA (1 << 31) 2017 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 2018 # define TV_HBURST_START_SHIFT 16 2019 # define TV_HBURST_START_MASK 0x1fff0000 2020 /** Length of the colorburst */ 2021 # define TV_HBURST_LEN_SHIFT 0 2022 # define TV_HBURST_LEN_MASK 0x0001fff 2023 2024 #define TV_H_CTL_3 0x68038 2025 /** End of hblank, measured in pixels minus one from start of hsync */ 2026 # define TV_HBLANK_END_SHIFT 16 2027 # define TV_HBLANK_END_MASK 0x1fff0000 2028 /** Start of hblank, measured in pixels minus one from start of hsync */ 2029 # define TV_HBLANK_START_SHIFT 0 2030 # define TV_HBLANK_START_MASK 0x0001fff 2031 2032 #define TV_V_CTL_1 0x6803c 2033 /** XXX */ 2034 # define TV_NBR_END_SHIFT 16 2035 # define TV_NBR_END_MASK 0x07ff0000 2036 /** XXX */ 2037 # define TV_VI_END_F1_SHIFT 8 2038 # define TV_VI_END_F1_MASK 0x00003f00 2039 /** XXX */ 2040 # define TV_VI_END_F2_SHIFT 0 2041 # define TV_VI_END_F2_MASK 0x0000003f 2042 2043 #define TV_V_CTL_2 0x68040 2044 /** Length of vsync, in half lines */ 2045 # define TV_VSYNC_LEN_MASK 0x07ff0000 2046 # define TV_VSYNC_LEN_SHIFT 16 2047 /** Offset of the start of vsync in field 1, measured in one less than the 2048 * number of half lines. 2049 */ 2050 # define TV_VSYNC_START_F1_MASK 0x00007f00 2051 # define TV_VSYNC_START_F1_SHIFT 8 2052 /** 2053 * Offset of the start of vsync in field 2, measured in one less than the 2054 * number of half lines. 2055 */ 2056 # define TV_VSYNC_START_F2_MASK 0x0000007f 2057 # define TV_VSYNC_START_F2_SHIFT 0 2058 2059 #define TV_V_CTL_3 0x68044 2060 /** Enables generation of the equalization signal */ 2061 # define TV_EQUAL_ENA (1 << 31) 2062 /** Length of vsync, in half lines */ 2063 # define TV_VEQ_LEN_MASK 0x007f0000 2064 # define TV_VEQ_LEN_SHIFT 16 2065 /** Offset of the start of equalization in field 1, measured in one less than 2066 * the number of half lines. 2067 */ 2068 # define TV_VEQ_START_F1_MASK 0x0007f00 2069 # define TV_VEQ_START_F1_SHIFT 8 2070 /** 2071 * Offset of the start of equalization in field 2, measured in one less than 2072 * the number of half lines. 2073 */ 2074 # define TV_VEQ_START_F2_MASK 0x000007f 2075 # define TV_VEQ_START_F2_SHIFT 0 2076 2077 #define TV_V_CTL_4 0x68048 2078 /** 2079 * Offset to start of vertical colorburst, measured in one less than the 2080 * number of lines from vertical start. 2081 */ 2082 # define TV_VBURST_START_F1_MASK 0x003f0000 2083 # define TV_VBURST_START_F1_SHIFT 16 2084 /** 2085 * Offset to the end of vertical colorburst, measured in one less than the 2086 * number of lines from the start of NBR. 2087 */ 2088 # define TV_VBURST_END_F1_MASK 0x000000ff 2089 # define TV_VBURST_END_F1_SHIFT 0 2090 2091 #define TV_V_CTL_5 0x6804c 2092 /** 2093 * Offset to start of vertical colorburst, measured in one less than the 2094 * number of lines from vertical start. 2095 */ 2096 # define TV_VBURST_START_F2_MASK 0x003f0000 2097 # define TV_VBURST_START_F2_SHIFT 16 2098 /** 2099 * Offset to the end of vertical colorburst, measured in one less than the 2100 * number of lines from the start of NBR. 2101 */ 2102 # define TV_VBURST_END_F2_MASK 0x000000ff 2103 # define TV_VBURST_END_F2_SHIFT 0 2104 2105 #define TV_V_CTL_6 0x68050 2106 /** 2107 * Offset to start of vertical colorburst, measured in one less than the 2108 * number of lines from vertical start. 2109 */ 2110 # define TV_VBURST_START_F3_MASK 0x003f0000 2111 # define TV_VBURST_START_F3_SHIFT 16 2112 /** 2113 * Offset to the end of vertical colorburst, measured in one less than the 2114 * number of lines from the start of NBR. 2115 */ 2116 # define TV_VBURST_END_F3_MASK 0x000000ff 2117 # define TV_VBURST_END_F3_SHIFT 0 2118 2119 #define TV_V_CTL_7 0x68054 2120 /** 2121 * Offset to start of vertical colorburst, measured in one less than the 2122 * number of lines from vertical start. 2123 */ 2124 # define TV_VBURST_START_F4_MASK 0x003f0000 2125 # define TV_VBURST_START_F4_SHIFT 16 2126 /** 2127 * Offset to the end of vertical colorburst, measured in one less than the 2128 * number of lines from the start of NBR. 2129 */ 2130 # define TV_VBURST_END_F4_MASK 0x000000ff 2131 # define TV_VBURST_END_F4_SHIFT 0 2132 2133 #define TV_SC_CTL_1 0x68060 2134 /** Turns on the first subcarrier phase generation DDA */ 2135 # define TV_SC_DDA1_EN (1 << 31) 2136 /** Turns on the first subcarrier phase generation DDA */ 2137 # define TV_SC_DDA2_EN (1 << 30) 2138 /** Turns on the first subcarrier phase generation DDA */ 2139 # define TV_SC_DDA3_EN (1 << 29) 2140 /** Sets the subcarrier DDA to reset frequency every other field */ 2141 # define TV_SC_RESET_EVERY_2 (0 << 24) 2142 /** Sets the subcarrier DDA to reset frequency every fourth field */ 2143 # define TV_SC_RESET_EVERY_4 (1 << 24) 2144 /** Sets the subcarrier DDA to reset frequency every eighth field */ 2145 # define TV_SC_RESET_EVERY_8 (2 << 24) 2146 /** Sets the subcarrier DDA to never reset the frequency */ 2147 # define TV_SC_RESET_NEVER (3 << 24) 2148 /** Sets the peak amplitude of the colorburst.*/ 2149 # define TV_BURST_LEVEL_MASK 0x00ff0000 2150 # define TV_BURST_LEVEL_SHIFT 16 2151 /** Sets the increment of the first subcarrier phase generation DDA */ 2152 # define TV_SCDDA1_INC_MASK 0x00000fff 2153 # define TV_SCDDA1_INC_SHIFT 0 2154 2155 #define TV_SC_CTL_2 0x68064 2156 /** Sets the rollover for the second subcarrier phase generation DDA */ 2157 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 2158 # define TV_SCDDA2_SIZE_SHIFT 16 2159 /** Sets the increent of the second subcarrier phase generation DDA */ 2160 # define TV_SCDDA2_INC_MASK 0x00007fff 2161 # define TV_SCDDA2_INC_SHIFT 0 2162 2163 #define TV_SC_CTL_3 0x68068 2164 /** Sets the rollover for the third subcarrier phase generation DDA */ 2165 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 2166 # define TV_SCDDA3_SIZE_SHIFT 16 2167 /** Sets the increent of the third subcarrier phase generation DDA */ 2168 # define TV_SCDDA3_INC_MASK 0x00007fff 2169 # define TV_SCDDA3_INC_SHIFT 0 2170 2171 #define TV_WIN_POS 0x68070 2172 /** X coordinate of the display from the start of horizontal active */ 2173 # define TV_XPOS_MASK 0x1fff0000 2174 # define TV_XPOS_SHIFT 16 2175 /** Y coordinate of the display from the start of vertical active (NBR) */ 2176 # define TV_YPOS_MASK 0x00000fff 2177 # define TV_YPOS_SHIFT 0 2178 2179 #define TV_WIN_SIZE 0x68074 2180 /** Horizontal size of the display window, measured in pixels*/ 2181 # define TV_XSIZE_MASK 0x1fff0000 2182 # define TV_XSIZE_SHIFT 16 2183 /** 2184 * Vertical size of the display window, measured in pixels. 2185 * 2186 * Must be even for interlaced modes. 2187 */ 2188 # define TV_YSIZE_MASK 0x00000fff 2189 # define TV_YSIZE_SHIFT 0 2190 2191 #define TV_FILTER_CTL_1 0x68080 2192 /** 2193 * Enables automatic scaling calculation. 2194 * 2195 * If set, the rest of the registers are ignored, and the calculated values can 2196 * be read back from the register. 2197 */ 2198 # define TV_AUTO_SCALE (1 << 31) 2199 /** 2200 * Disables the vertical filter. 2201 * 2202 * This is required on modes more than 1024 pixels wide */ 2203 # define TV_V_FILTER_BYPASS (1 << 29) 2204 /** Enables adaptive vertical filtering */ 2205 # define TV_VADAPT (1 << 28) 2206 # define TV_VADAPT_MODE_MASK (3 << 26) 2207 /** Selects the least adaptive vertical filtering mode */ 2208 # define TV_VADAPT_MODE_LEAST (0 << 26) 2209 /** Selects the moderately adaptive vertical filtering mode */ 2210 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2211 /** Selects the most adaptive vertical filtering mode */ 2212 # define TV_VADAPT_MODE_MOST (3 << 26) 2213 /** 2214 * Sets the horizontal scaling factor. 2215 * 2216 * This should be the fractional part of the horizontal scaling factor divided 2217 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2218 * 2219 * (src width - 1) / ((oversample * dest width) - 1) 2220 */ 2221 # define TV_HSCALE_FRAC_MASK 0x00003fff 2222 # define TV_HSCALE_FRAC_SHIFT 0 2223 2224 #define TV_FILTER_CTL_2 0x68084 2225 /** 2226 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2227 * 2228 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2229 */ 2230 # define TV_VSCALE_INT_MASK 0x00038000 2231 # define TV_VSCALE_INT_SHIFT 15 2232 /** 2233 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2234 * 2235 * \sa TV_VSCALE_INT_MASK 2236 */ 2237 # define TV_VSCALE_FRAC_MASK 0x00007fff 2238 # define TV_VSCALE_FRAC_SHIFT 0 2239 2240 #define TV_FILTER_CTL_3 0x68088 2241 /** 2242 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2243 * 2244 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2245 * 2246 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2247 */ 2248 # define TV_VSCALE_IP_INT_MASK 0x00038000 2249 # define TV_VSCALE_IP_INT_SHIFT 15 2250 /** 2251 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2252 * 2253 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2254 * 2255 * \sa TV_VSCALE_IP_INT_MASK 2256 */ 2257 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2258 # define TV_VSCALE_IP_FRAC_SHIFT 0 2259 2260 #define TV_CC_CONTROL 0x68090 2261 # define TV_CC_ENABLE (1 << 31) 2262 /** 2263 * Specifies which field to send the CC data in. 2264 * 2265 * CC data is usually sent in field 0. 2266 */ 2267 # define TV_CC_FID_MASK (1 << 27) 2268 # define TV_CC_FID_SHIFT 27 2269 /** Sets the horizontal position of the CC data. Usually 135. */ 2270 # define TV_CC_HOFF_MASK 0x03ff0000 2271 # define TV_CC_HOFF_SHIFT 16 2272 /** Sets the vertical position of the CC data. Usually 21 */ 2273 # define TV_CC_LINE_MASK 0x0000003f 2274 # define TV_CC_LINE_SHIFT 0 2275 2276 #define TV_CC_DATA 0x68094 2277 # define TV_CC_RDY (1 << 31) 2278 /** Second word of CC data to be transmitted. */ 2279 # define TV_CC_DATA_2_MASK 0x007f0000 2280 # define TV_CC_DATA_2_SHIFT 16 2281 /** First word of CC data to be transmitted. */ 2282 # define TV_CC_DATA_1_MASK 0x0000007f 2283 # define TV_CC_DATA_1_SHIFT 0 2284 2285 #define TV_H_LUMA_0 0x68100 2286 #define TV_H_LUMA_59 0x681ec 2287 #define TV_H_CHROMA_0 0x68200 2288 #define TV_H_CHROMA_59 0x682ec 2289 #define TV_V_LUMA_0 0x68300 2290 #define TV_V_LUMA_42 0x683a8 2291 #define TV_V_CHROMA_0 0x68400 2292 #define TV_V_CHROMA_42 0x684a8 2293 2294 /* Display Port */ 2295 #define DP_A 0x64000 /* eDP */ 2296 #define DP_B 0x64100 2297 #define DP_C 0x64200 2298 #define DP_D 0x64300 2299 2300 #define DP_PORT_EN (1 << 31) 2301 #define DP_PIPEB_SELECT (1 << 30) 2302 #define DP_PIPE_MASK (1 << 30) 2303 2304 /* Link training mode - select a suitable mode for each stage */ 2305 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2306 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2307 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2308 #define DP_LINK_TRAIN_OFF (3 << 28) 2309 #define DP_LINK_TRAIN_MASK (3 << 28) 2310 #define DP_LINK_TRAIN_SHIFT 28 2311 2312 /* CPT Link training mode */ 2313 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2314 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2315 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2316 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2317 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2318 #define DP_LINK_TRAIN_SHIFT_CPT 8 2319 2320 /* Signal voltages. These are mostly controlled by the other end */ 2321 #define DP_VOLTAGE_0_4 (0 << 25) 2322 #define DP_VOLTAGE_0_6 (1 << 25) 2323 #define DP_VOLTAGE_0_8 (2 << 25) 2324 #define DP_VOLTAGE_1_2 (3 << 25) 2325 #define DP_VOLTAGE_MASK (7 << 25) 2326 #define DP_VOLTAGE_SHIFT 25 2327 2328 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2329 * they want 2330 */ 2331 #define DP_PRE_EMPHASIS_0 (0 << 22) 2332 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2333 #define DP_PRE_EMPHASIS_6 (2 << 22) 2334 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2335 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2336 #define DP_PRE_EMPHASIS_SHIFT 22 2337 2338 /* How many wires to use. I guess 3 was too hard */ 2339 #define DP_PORT_WIDTH_1 (0 << 19) 2340 #define DP_PORT_WIDTH_2 (1 << 19) 2341 #define DP_PORT_WIDTH_4 (3 << 19) 2342 #define DP_PORT_WIDTH_MASK (7 << 19) 2343 2344 /* Mystic DPCD version 1.1 special mode */ 2345 #define DP_ENHANCED_FRAMING (1 << 18) 2346 2347 /* eDP */ 2348 #define DP_PLL_FREQ_270MHZ (0 << 16) 2349 #define DP_PLL_FREQ_160MHZ (1 << 16) 2350 #define DP_PLL_FREQ_MASK (3 << 16) 2351 2352 /** locked once port is enabled */ 2353 #define DP_PORT_REVERSAL (1 << 15) 2354 2355 /* eDP */ 2356 #define DP_PLL_ENABLE (1 << 14) 2357 2358 /** sends the clock on lane 15 of the PEG for debug */ 2359 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2360 2361 #define DP_SCRAMBLING_DISABLE (1 << 12) 2362 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2363 2364 /** limit RGB values to avoid confusing TVs */ 2365 #define DP_COLOR_RANGE_16_235 (1 << 8) 2366 2367 /** Turn on the audio link */ 2368 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2369 2370 /** vs and hs sync polarity */ 2371 #define DP_SYNC_VS_HIGH (1 << 4) 2372 #define DP_SYNC_HS_HIGH (1 << 3) 2373 2374 /** A fantasy */ 2375 #define DP_DETECTED (1 << 2) 2376 2377 /** The aux channel provides a way to talk to the 2378 * signal sink for DDC etc. Max packet size supported 2379 * is 20 bytes in each direction, hence the 5 fixed 2380 * data registers 2381 */ 2382 #define DPA_AUX_CH_CTL 0x64010 2383 #define DPA_AUX_CH_DATA1 0x64014 2384 #define DPA_AUX_CH_DATA2 0x64018 2385 #define DPA_AUX_CH_DATA3 0x6401c 2386 #define DPA_AUX_CH_DATA4 0x64020 2387 #define DPA_AUX_CH_DATA5 0x64024 2388 2389 #define DPB_AUX_CH_CTL 0x64110 2390 #define DPB_AUX_CH_DATA1 0x64114 2391 #define DPB_AUX_CH_DATA2 0x64118 2392 #define DPB_AUX_CH_DATA3 0x6411c 2393 #define DPB_AUX_CH_DATA4 0x64120 2394 #define DPB_AUX_CH_DATA5 0x64124 2395 2396 #define DPC_AUX_CH_CTL 0x64210 2397 #define DPC_AUX_CH_DATA1 0x64214 2398 #define DPC_AUX_CH_DATA2 0x64218 2399 #define DPC_AUX_CH_DATA3 0x6421c 2400 #define DPC_AUX_CH_DATA4 0x64220 2401 #define DPC_AUX_CH_DATA5 0x64224 2402 2403 #define DPD_AUX_CH_CTL 0x64310 2404 #define DPD_AUX_CH_DATA1 0x64314 2405 #define DPD_AUX_CH_DATA2 0x64318 2406 #define DPD_AUX_CH_DATA3 0x6431c 2407 #define DPD_AUX_CH_DATA4 0x64320 2408 #define DPD_AUX_CH_DATA5 0x64324 2409 2410 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2411 #define DP_AUX_CH_CTL_DONE (1 << 30) 2412 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2413 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2414 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2415 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2416 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2417 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2418 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2419 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2420 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2421 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2422 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2423 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2424 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2425 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2426 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2427 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2428 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2429 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2430 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2431 2432 /* 2433 * Computing GMCH M and N values for the Display Port link 2434 * 2435 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2436 * 2437 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2438 * 2439 * The GMCH value is used internally 2440 * 2441 * bytes_per_pixel is the number of bytes coming out of the plane, 2442 * which is after the LUTs, so we want the bytes for our color format. 2443 * For our current usage, this is always 3, one byte for R, G and B. 2444 */ 2445 #define _PIPEA_GMCH_DATA_M 0x70050 2446 #define _PIPEB_GMCH_DATA_M 0x71050 2447 2448 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2449 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2450 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2451 2452 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2453 2454 #define _PIPEA_GMCH_DATA_N 0x70054 2455 #define _PIPEB_GMCH_DATA_N 0x71054 2456 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2457 2458 /* 2459 * Computing Link M and N values for the Display Port link 2460 * 2461 * Link M / N = pixel_clock / ls_clk 2462 * 2463 * (the DP spec calls pixel_clock the 'strm_clk') 2464 * 2465 * The Link value is transmitted in the Main Stream 2466 * Attributes and VB-ID. 2467 */ 2468 2469 #define _PIPEA_DP_LINK_M 0x70060 2470 #define _PIPEB_DP_LINK_M 0x71060 2471 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2472 2473 #define _PIPEA_DP_LINK_N 0x70064 2474 #define _PIPEB_DP_LINK_N 0x71064 2475 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2476 2477 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) 2478 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) 2479 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) 2480 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) 2481 2482 /* Display & cursor control */ 2483 2484 /* Pipe A */ 2485 #define _PIPEADSL 0x70000 2486 #define DSL_LINEMASK_GEN2 0x00000fff 2487 #define DSL_LINEMASK_GEN3 0x00001fff 2488 #define _PIPEACONF 0x70008 2489 #define PIPECONF_ENABLE (1<<31) 2490 #define PIPECONF_DISABLE 0 2491 #define PIPECONF_DOUBLE_WIDE (1<<30) 2492 #define I965_PIPECONF_ACTIVE (1<<30) 2493 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 2494 #define PIPECONF_SINGLE_WIDE 0 2495 #define PIPECONF_PIPE_UNLOCKED 0 2496 #define PIPECONF_PIPE_LOCKED (1<<25) 2497 #define PIPECONF_PALETTE 0 2498 #define PIPECONF_GAMMA (1<<24) 2499 #define PIPECONF_FORCE_BORDER (1<<25) 2500 #define PIPECONF_INTERLACE_MASK (7 << 21) 2501 /* Note that pre-gen3 does not support interlaced display directly. Panel 2502 * fitting must be disabled on pre-ilk for interlaced. */ 2503 #define PIPECONF_PROGRESSIVE (0 << 21) 2504 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 2505 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 2506 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2507 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 2508 /* Ironlake and later have a complete new set of values for interlaced. PFIT 2509 * means panel fitter required, PF means progressive fetch, DBL means power 2510 * saving pixel doubling. */ 2511 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 2512 #define PIPECONF_INTERLACED_ILK (3 << 21) 2513 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 2514 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 2515 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2516 #define PIPECONF_BPP_MASK (0x000000e0) 2517 #define PIPECONF_BPP_8 (0<<5) 2518 #define PIPECONF_BPP_10 (1<<5) 2519 #define PIPECONF_BPP_6 (2<<5) 2520 #define PIPECONF_BPP_12 (3<<5) 2521 #define PIPECONF_DITHER_EN (1<<4) 2522 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2523 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2524 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2525 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2526 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2527 #define _PIPEASTAT 0x70024 2528 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2529 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) 2530 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2531 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2532 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2533 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 2534 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2535 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2536 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2537 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2538 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) 2539 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2540 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2541 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2542 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2543 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2544 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2545 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 2546 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2547 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) 2548 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) 2549 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2550 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2551 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2552 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) 2553 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2554 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2555 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2556 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2557 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2558 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2559 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2560 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2561 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2562 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2563 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2564 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2565 #define PIPE_8BPC (0 << 5) 2566 #define PIPE_10BPC (1 << 5) 2567 #define PIPE_6BPC (2 << 5) 2568 #define PIPE_12BPC (3 << 5) 2569 2570 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 2571 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) 2572 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 2573 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 2574 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 2575 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 2576 2577 #define VLV_DPFLIPSTAT 0x70028 2578 #define PIPEB_LINE_COMPARE_STATUS (1<<29) 2579 #define PIPEB_HLINE_INT_EN (1<<28) 2580 #define PIPEB_VBLANK_INT_EN (1<<27) 2581 #define SPRITED_FLIPDONE_INT_EN (1<<26) 2582 #define SPRITEC_FLIPDONE_INT_EN (1<<25) 2583 #define PLANEB_FLIPDONE_INT_EN (1<<24) 2584 #define PIPEA_LINE_COMPARE_STATUS (1<<21) 2585 #define PIPEA_HLINE_INT_EN (1<<20) 2586 #define PIPEA_VBLANK_INT_EN (1<<19) 2587 #define SPRITEB_FLIPDONE_INT_EN (1<<18) 2588 #define SPRITEA_FLIPDONE_INT_EN (1<<17) 2589 #define PLANEA_FLIPDONE_INT_EN (1<<16) 2590 2591 #define DPINVGTT 0x7002c /* VLV only */ 2592 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 2593 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 2594 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 2595 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 2596 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 2597 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 2598 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 2599 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 2600 #define DPINVGTT_EN_MASK 0xff0000 2601 #define CURSORB_INVALID_GTT_STATUS (1<<7) 2602 #define CURSORA_INVALID_GTT_STATUS (1<<6) 2603 #define SPRITED_INVALID_GTT_STATUS (1<<5) 2604 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 2605 #define PLANEB_INVALID_GTT_STATUS (1<<3) 2606 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 2607 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 2608 #define PLANEA_INVALID_GTT_STATUS (1<<0) 2609 #define DPINVGTT_STATUS_MASK 0xff 2610 2611 #define DSPARB 0x70030 2612 #define DSPARB_CSTART_MASK (0x7f << 7) 2613 #define DSPARB_CSTART_SHIFT 7 2614 #define DSPARB_BSTART_MASK (0x7f) 2615 #define DSPARB_BSTART_SHIFT 0 2616 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2617 #define DSPARB_AEND_SHIFT 0 2618 2619 #define DSPFW1 0x70034 2620 #define DSPFW_SR_SHIFT 23 2621 #define DSPFW_SR_MASK (0x1ff<<23) 2622 #define DSPFW_CURSORB_SHIFT 16 2623 #define DSPFW_CURSORB_MASK (0x3f<<16) 2624 #define DSPFW_PLANEB_SHIFT 8 2625 #define DSPFW_PLANEB_MASK (0x7f<<8) 2626 #define DSPFW_PLANEA_MASK (0x7f) 2627 #define DSPFW2 0x70038 2628 #define DSPFW_CURSORA_MASK 0x00003f00 2629 #define DSPFW_CURSORA_SHIFT 8 2630 #define DSPFW_PLANEC_MASK (0x7f) 2631 #define DSPFW3 0x7003c 2632 #define DSPFW_HPLL_SR_EN (1<<31) 2633 #define DSPFW_CURSOR_SR_SHIFT 24 2634 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2635 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2636 #define DSPFW_HPLL_CURSOR_SHIFT 16 2637 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2638 #define DSPFW_HPLL_SR_MASK (0x1ff) 2639 2640 /* drain latency register values*/ 2641 #define DRAIN_LATENCY_PRECISION_32 32 2642 #define DRAIN_LATENCY_PRECISION_16 16 2643 #define VLV_DDL1 0x70050 2644 #define DDL_CURSORA_PRECISION_32 (1<<31) 2645 #define DDL_CURSORA_PRECISION_16 (0<<31) 2646 #define DDL_CURSORA_SHIFT 24 2647 #define DDL_PLANEA_PRECISION_32 (1<<7) 2648 #define DDL_PLANEA_PRECISION_16 (0<<7) 2649 #define VLV_DDL2 0x70054 2650 #define DDL_CURSORB_PRECISION_32 (1<<31) 2651 #define DDL_CURSORB_PRECISION_16 (0<<31) 2652 #define DDL_CURSORB_SHIFT 24 2653 #define DDL_PLANEB_PRECISION_32 (1<<7) 2654 #define DDL_PLANEB_PRECISION_16 (0<<7) 2655 2656 /* FIFO watermark sizes etc */ 2657 #define G4X_FIFO_LINE_SIZE 64 2658 #define I915_FIFO_LINE_SIZE 64 2659 #define I830_FIFO_LINE_SIZE 32 2660 2661 #define VALLEYVIEW_FIFO_SIZE 255 2662 #define G4X_FIFO_SIZE 127 2663 #define I965_FIFO_SIZE 512 2664 #define I945_FIFO_SIZE 127 2665 #define I915_FIFO_SIZE 95 2666 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2667 #define I830_FIFO_SIZE 95 2668 2669 #define VALLEYVIEW_MAX_WM 0xff 2670 #define G4X_MAX_WM 0x3f 2671 #define I915_MAX_WM 0x3f 2672 2673 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2674 #define PINEVIEW_FIFO_LINE_SIZE 64 2675 #define PINEVIEW_MAX_WM 0x1ff 2676 #define PINEVIEW_DFT_WM 0x3f 2677 #define PINEVIEW_DFT_HPLLOFF_WM 0 2678 #define PINEVIEW_GUARD_WM 10 2679 #define PINEVIEW_CURSOR_FIFO 64 2680 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2681 #define PINEVIEW_CURSOR_DFT_WM 0 2682 #define PINEVIEW_CURSOR_GUARD_WM 5 2683 2684 #define VALLEYVIEW_CURSOR_MAX_WM 64 2685 #define I965_CURSOR_FIFO 64 2686 #define I965_CURSOR_MAX_WM 32 2687 #define I965_CURSOR_DFT_WM 8 2688 2689 /* define the Watermark register on Ironlake */ 2690 #define WM0_PIPEA_ILK 0x45100 2691 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2692 #define WM0_PIPE_PLANE_SHIFT 16 2693 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2694 #define WM0_PIPE_SPRITE_SHIFT 8 2695 #define WM0_PIPE_CURSOR_MASK (0x1f) 2696 2697 #define WM0_PIPEB_ILK 0x45104 2698 #define WM0_PIPEC_IVB 0x45200 2699 #define WM1_LP_ILK 0x45108 2700 #define WM1_LP_SR_EN (1<<31) 2701 #define WM1_LP_LATENCY_SHIFT 24 2702 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2703 #define WM1_LP_FBC_MASK (0xf<<20) 2704 #define WM1_LP_FBC_SHIFT 20 2705 #define WM1_LP_SR_MASK (0x1ff<<8) 2706 #define WM1_LP_SR_SHIFT 8 2707 #define WM1_LP_CURSOR_MASK (0x3f) 2708 #define WM2_LP_ILK 0x4510c 2709 #define WM2_LP_EN (1<<31) 2710 #define WM3_LP_ILK 0x45110 2711 #define WM3_LP_EN (1<<31) 2712 #define WM1S_LP_ILK 0x45120 2713 #define WM2S_LP_IVB 0x45124 2714 #define WM3S_LP_IVB 0x45128 2715 #define WM1S_LP_EN (1<<31) 2716 2717 /* Memory latency timer register */ 2718 #define MLTR_ILK 0x11222 2719 #define MLTR_WM1_SHIFT 0 2720 #define MLTR_WM2_SHIFT 8 2721 /* the unit of memory self-refresh latency time is 0.5us */ 2722 #define ILK_SRLT_MASK 0x3f 2723 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2724 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2725 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2726 2727 /* define the fifo size on Ironlake */ 2728 #define ILK_DISPLAY_FIFO 128 2729 #define ILK_DISPLAY_MAXWM 64 2730 #define ILK_DISPLAY_DFTWM 8 2731 #define ILK_CURSOR_FIFO 32 2732 #define ILK_CURSOR_MAXWM 16 2733 #define ILK_CURSOR_DFTWM 8 2734 2735 #define ILK_DISPLAY_SR_FIFO 512 2736 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2737 #define ILK_DISPLAY_DFT_SRWM 0x3f 2738 #define ILK_CURSOR_SR_FIFO 64 2739 #define ILK_CURSOR_MAX_SRWM 0x3f 2740 #define ILK_CURSOR_DFT_SRWM 8 2741 2742 #define ILK_FIFO_LINE_SIZE 64 2743 2744 /* define the WM info on Sandybridge */ 2745 #define SNB_DISPLAY_FIFO 128 2746 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2747 #define SNB_DISPLAY_DFTWM 8 2748 #define SNB_CURSOR_FIFO 32 2749 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2750 #define SNB_CURSOR_DFTWM 8 2751 2752 #define SNB_DISPLAY_SR_FIFO 512 2753 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2754 #define SNB_DISPLAY_DFT_SRWM 0x3f 2755 #define SNB_CURSOR_SR_FIFO 64 2756 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2757 #define SNB_CURSOR_DFT_SRWM 8 2758 2759 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2760 2761 #define SNB_FIFO_LINE_SIZE 64 2762 2763 2764 /* the address where we get all kinds of latency value */ 2765 #define SSKPD 0x5d10 2766 #define SSKPD_WM_MASK 0x3f 2767 #define SSKPD_WM0_SHIFT 0 2768 #define SSKPD_WM1_SHIFT 8 2769 #define SSKPD_WM2_SHIFT 16 2770 #define SSKPD_WM3_SHIFT 24 2771 2772 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) 2773 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) 2774 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) 2775 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) 2776 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) 2777 2778 /* 2779 * The two pipe frame counter registers are not synchronized, so 2780 * reading a stable value is somewhat tricky. The following code 2781 * should work: 2782 * 2783 * do { 2784 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2785 * PIPE_FRAME_HIGH_SHIFT; 2786 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2787 * PIPE_FRAME_LOW_SHIFT); 2788 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2789 * PIPE_FRAME_HIGH_SHIFT); 2790 * } while (high1 != high2); 2791 * frame = (high1 << 8) | low1; 2792 */ 2793 #define _PIPEAFRAMEHIGH 0x70040 2794 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2795 #define PIPE_FRAME_HIGH_SHIFT 0 2796 #define _PIPEAFRAMEPIXEL 0x70044 2797 #define PIPE_FRAME_LOW_MASK 0xff000000 2798 #define PIPE_FRAME_LOW_SHIFT 24 2799 #define PIPE_PIXEL_MASK 0x00ffffff 2800 #define PIPE_PIXEL_SHIFT 0 2801 /* GM45+ just has to be different */ 2802 #define _PIPEA_FRMCOUNT_GM45 0x70040 2803 #define _PIPEA_FLIPCOUNT_GM45 0x70044 2804 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 2805 2806 /* Cursor A & B regs */ 2807 #define _CURACNTR 0x70080 2808 /* Old style CUR*CNTR flags (desktop 8xx) */ 2809 #define CURSOR_ENABLE 0x80000000 2810 #define CURSOR_GAMMA_ENABLE 0x40000000 2811 #define CURSOR_STRIDE_MASK 0x30000000 2812 #define CURSOR_FORMAT_SHIFT 24 2813 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2814 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2815 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2816 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2817 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2818 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2819 /* New style CUR*CNTR flags */ 2820 #define CURSOR_MODE 0x27 2821 #define CURSOR_MODE_DISABLE 0x00 2822 #define CURSOR_MODE_64_32B_AX 0x07 2823 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2824 #define MCURSOR_PIPE_SELECT (1 << 28) 2825 #define MCURSOR_PIPE_A 0x00 2826 #define MCURSOR_PIPE_B (1 << 28) 2827 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2828 #define _CURABASE 0x70084 2829 #define _CURAPOS 0x70088 2830 #define CURSOR_POS_MASK 0x007FF 2831 #define CURSOR_POS_SIGN 0x8000 2832 #define CURSOR_X_SHIFT 0 2833 #define CURSOR_Y_SHIFT 16 2834 #define CURSIZE 0x700a0 2835 #define _CURBCNTR 0x700c0 2836 #define _CURBBASE 0x700c4 2837 #define _CURBPOS 0x700c8 2838 2839 #define _CURBCNTR_IVB 0x71080 2840 #define _CURBBASE_IVB 0x71084 2841 #define _CURBPOS_IVB 0x71088 2842 2843 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) 2844 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) 2845 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) 2846 2847 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) 2848 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) 2849 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 2850 2851 /* Display A control */ 2852 #define _DSPACNTR 0x70180 2853 #define DISPLAY_PLANE_ENABLE (1<<31) 2854 #define DISPLAY_PLANE_DISABLE 0 2855 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2856 #define DISPPLANE_GAMMA_DISABLE 0 2857 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2858 #define DISPPLANE_8BPP (0x2<<26) 2859 #define DISPPLANE_15_16BPP (0x4<<26) 2860 #define DISPPLANE_16BPP (0x5<<26) 2861 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2862 #define DISPPLANE_32BPP (0x7<<26) 2863 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2864 #define DISPPLANE_STEREO_ENABLE (1<<25) 2865 #define DISPPLANE_STEREO_DISABLE 0 2866 #define DISPPLANE_SEL_PIPE_SHIFT 24 2867 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 2868 #define DISPPLANE_SEL_PIPE_A 0 2869 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 2870 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2871 #define DISPPLANE_SRC_KEY_DISABLE 0 2872 #define DISPPLANE_LINE_DOUBLE (1<<20) 2873 #define DISPPLANE_NO_LINE_DOUBLE 0 2874 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2875 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2876 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2877 #define DISPPLANE_TILED (1<<10) 2878 #define _DSPAADDR 0x70184 2879 #define _DSPASTRIDE 0x70188 2880 #define _DSPAPOS 0x7018C /* reserved */ 2881 #define _DSPASIZE 0x70190 2882 #define _DSPASURF 0x7019C /* 965+ only */ 2883 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2884 2885 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 2886 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 2887 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 2888 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 2889 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 2890 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 2891 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 2892 2893 /* Display/Sprite base address macros */ 2894 #define DISP_BASEADDR_MASK (0xfffff000) 2895 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 2896 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 2897 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ 2898 (I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg)))) 2899 2900 /* VBIOS flags */ 2901 #define SWF00 0x71410 2902 #define SWF01 0x71414 2903 #define SWF02 0x71418 2904 #define SWF03 0x7141c 2905 #define SWF04 0x71420 2906 #define SWF05 0x71424 2907 #define SWF06 0x71428 2908 #define SWF10 0x70410 2909 #define SWF11 0x70414 2910 #define SWF14 0x71420 2911 #define SWF30 0x72414 2912 #define SWF31 0x72418 2913 #define SWF32 0x7241c 2914 2915 /* Pipe B */ 2916 #define _PIPEBDSL 0x71000 2917 #define _PIPEBCONF 0x71008 2918 #define _PIPEBSTAT 0x71024 2919 #define _PIPEBFRAMEHIGH 0x71040 2920 #define _PIPEBFRAMEPIXEL 0x71044 2921 #define _PIPEB_FRMCOUNT_GM45 0x71040 2922 #define _PIPEB_FLIPCOUNT_GM45 0x71044 2923 2924 2925 /* Display B control */ 2926 #define _DSPBCNTR 0x71180 2927 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2928 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2929 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2930 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2931 #define _DSPBADDR 0x71184 2932 #define _DSPBSTRIDE 0x71188 2933 #define _DSPBPOS 0x7118C 2934 #define _DSPBSIZE 0x71190 2935 #define _DSPBSURF 0x7119C 2936 #define _DSPBTILEOFF 0x711A4 2937 2938 /* Sprite A control */ 2939 #define _DVSACNTR 0x72180 2940 #define DVS_ENABLE (1<<31) 2941 #define DVS_GAMMA_ENABLE (1<<30) 2942 #define DVS_PIXFORMAT_MASK (3<<25) 2943 #define DVS_FORMAT_YUV422 (0<<25) 2944 #define DVS_FORMAT_RGBX101010 (1<<25) 2945 #define DVS_FORMAT_RGBX888 (2<<25) 2946 #define DVS_FORMAT_RGBX161616 (3<<25) 2947 #define DVS_SOURCE_KEY (1<<22) 2948 #define DVS_RGB_ORDER_XBGR (1<<20) 2949 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 2950 #define DVS_YUV_ORDER_YUYV (0<<16) 2951 #define DVS_YUV_ORDER_UYVY (1<<16) 2952 #define DVS_YUV_ORDER_YVYU (2<<16) 2953 #define DVS_YUV_ORDER_VYUY (3<<16) 2954 #define DVS_DEST_KEY (1<<2) 2955 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 2956 #define DVS_TILED (1<<10) 2957 #define _DVSALINOFF 0x72184 2958 #define _DVSASTRIDE 0x72188 2959 #define _DVSAPOS 0x7218c 2960 #define _DVSASIZE 0x72190 2961 #define _DVSAKEYVAL 0x72194 2962 #define _DVSAKEYMSK 0x72198 2963 #define _DVSASURF 0x7219c 2964 #define _DVSAKEYMAXVAL 0x721a0 2965 #define _DVSATILEOFF 0x721a4 2966 #define _DVSASURFLIVE 0x721ac 2967 #define _DVSASCALE 0x72204 2968 #define DVS_SCALE_ENABLE (1<<31) 2969 #define DVS_FILTER_MASK (3<<29) 2970 #define DVS_FILTER_MEDIUM (0<<29) 2971 #define DVS_FILTER_ENHANCING (1<<29) 2972 #define DVS_FILTER_SOFTENING (2<<29) 2973 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2974 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 2975 #define _DVSAGAMC 0x72300 2976 2977 #define _DVSBCNTR 0x73180 2978 #define _DVSBLINOFF 0x73184 2979 #define _DVSBSTRIDE 0x73188 2980 #define _DVSBPOS 0x7318c 2981 #define _DVSBSIZE 0x73190 2982 #define _DVSBKEYVAL 0x73194 2983 #define _DVSBKEYMSK 0x73198 2984 #define _DVSBSURF 0x7319c 2985 #define _DVSBKEYMAXVAL 0x731a0 2986 #define _DVSBTILEOFF 0x731a4 2987 #define _DVSBSURFLIVE 0x731ac 2988 #define _DVSBSCALE 0x73204 2989 #define _DVSBGAMC 0x73300 2990 2991 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 2992 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 2993 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 2994 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 2995 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 2996 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 2997 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 2998 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 2999 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 3000 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 3001 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 3002 3003 #define _SPRA_CTL 0x70280 3004 #define SPRITE_ENABLE (1<<31) 3005 #define SPRITE_GAMMA_ENABLE (1<<30) 3006 #define SPRITE_PIXFORMAT_MASK (7<<25) 3007 #define SPRITE_FORMAT_YUV422 (0<<25) 3008 #define SPRITE_FORMAT_RGBX101010 (1<<25) 3009 #define SPRITE_FORMAT_RGBX888 (2<<25) 3010 #define SPRITE_FORMAT_RGBX161616 (3<<25) 3011 #define SPRITE_FORMAT_YUV444 (4<<25) 3012 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 3013 #define SPRITE_CSC_ENABLE (1<<24) 3014 #define SPRITE_SOURCE_KEY (1<<22) 3015 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 3016 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 3017 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 3018 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 3019 #define SPRITE_YUV_ORDER_YUYV (0<<16) 3020 #define SPRITE_YUV_ORDER_UYVY (1<<16) 3021 #define SPRITE_YUV_ORDER_YVYU (2<<16) 3022 #define SPRITE_YUV_ORDER_VYUY (3<<16) 3023 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 3024 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 3025 #define SPRITE_TILED (1<<10) 3026 #define SPRITE_DEST_KEY (1<<2) 3027 #define _SPRA_LINOFF 0x70284 3028 #define _SPRA_STRIDE 0x70288 3029 #define _SPRA_POS 0x7028c 3030 #define _SPRA_SIZE 0x70290 3031 #define _SPRA_KEYVAL 0x70294 3032 #define _SPRA_KEYMSK 0x70298 3033 #define _SPRA_SURF 0x7029c 3034 #define _SPRA_KEYMAX 0x702a0 3035 #define _SPRA_TILEOFF 0x702a4 3036 #define _SPRA_SCALE 0x70304 3037 #define SPRITE_SCALE_ENABLE (1<<31) 3038 #define SPRITE_FILTER_MASK (3<<29) 3039 #define SPRITE_FILTER_MEDIUM (0<<29) 3040 #define SPRITE_FILTER_ENHANCING (1<<29) 3041 #define SPRITE_FILTER_SOFTENING (2<<29) 3042 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 3043 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 3044 #define _SPRA_GAMC 0x70400 3045 3046 #define _SPRB_CTL 0x71280 3047 #define _SPRB_LINOFF 0x71284 3048 #define _SPRB_STRIDE 0x71288 3049 #define _SPRB_POS 0x7128c 3050 #define _SPRB_SIZE 0x71290 3051 #define _SPRB_KEYVAL 0x71294 3052 #define _SPRB_KEYMSK 0x71298 3053 #define _SPRB_SURF 0x7129c 3054 #define _SPRB_KEYMAX 0x712a0 3055 #define _SPRB_TILEOFF 0x712a4 3056 #define _SPRB_SCALE 0x71304 3057 #define _SPRB_GAMC 0x71400 3058 3059 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 3060 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 3061 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 3062 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 3063 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 3064 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 3065 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 3066 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 3067 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 3068 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 3069 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 3070 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 3071 3072 /* VBIOS regs */ 3073 #define VGACNTRL 0x71400 3074 # define VGA_DISP_DISABLE (1 << 31) 3075 # define VGA_2X_MODE (1 << 30) 3076 # define VGA_PIPE_B_SELECT (1 << 29) 3077 3078 /* Ironlake */ 3079 3080 #define CPU_VGACNTRL 0x41000 3081 3082 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 3083 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 3084 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 3085 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 3086 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 3087 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 3088 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 3089 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 3090 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 3091 3092 /* refresh rate hardware control */ 3093 #define RR_HW_CTL 0x45300 3094 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 3095 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 3096 3097 #define FDI_PLL_BIOS_0 0x46000 3098 #define FDI_PLL_FB_CLOCK_MASK 0xff 3099 #define FDI_PLL_BIOS_1 0x46004 3100 #define FDI_PLL_BIOS_2 0x46008 3101 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 3102 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 3103 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 3104 3105 #define PCH_DSPCLK_GATE_D 0x42020 3106 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3107 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 3108 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 3109 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 3110 3111 #define PCH_3DCGDIS0 0x46020 3112 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 3113 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 3114 3115 #define PCH_3DCGDIS1 0x46024 3116 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 3117 3118 #define FDI_PLL_FREQ_CTL 0x46030 3119 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 3120 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 3121 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 3122 3123 3124 #define _PIPEA_DATA_M1 0x60030 3125 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 3126 #define TU_SIZE_MASK 0x7e000000 3127 #define PIPE_DATA_M1_OFFSET 0 3128 #define _PIPEA_DATA_N1 0x60034 3129 #define PIPE_DATA_N1_OFFSET 0 3130 3131 #define _PIPEA_DATA_M2 0x60038 3132 #define PIPE_DATA_M2_OFFSET 0 3133 #define _PIPEA_DATA_N2 0x6003c 3134 #define PIPE_DATA_N2_OFFSET 0 3135 3136 #define _PIPEA_LINK_M1 0x60040 3137 #define PIPE_LINK_M1_OFFSET 0 3138 #define _PIPEA_LINK_N1 0x60044 3139 #define PIPE_LINK_N1_OFFSET 0 3140 3141 #define _PIPEA_LINK_M2 0x60048 3142 #define PIPE_LINK_M2_OFFSET 0 3143 #define _PIPEA_LINK_N2 0x6004c 3144 #define PIPE_LINK_N2_OFFSET 0 3145 3146 /* PIPEB timing regs are same start from 0x61000 */ 3147 3148 #define _PIPEB_DATA_M1 0x61030 3149 #define _PIPEB_DATA_N1 0x61034 3150 3151 #define _PIPEB_DATA_M2 0x61038 3152 #define _PIPEB_DATA_N2 0x6103c 3153 3154 #define _PIPEB_LINK_M1 0x61040 3155 #define _PIPEB_LINK_N1 0x61044 3156 3157 #define _PIPEB_LINK_M2 0x61048 3158 #define _PIPEB_LINK_N2 0x6104c 3159 3160 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 3161 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 3162 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 3163 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 3164 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 3165 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1) 3166 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2) 3167 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2) 3168 3169 /* CPU panel fitter */ 3170 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3171 #define _PFA_CTL_1 0x68080 3172 #define _PFB_CTL_1 0x68880 3173 #define PF_ENABLE (1<<31) 3174 #define PF_FILTER_MASK (3<<23) 3175 #define PF_FILTER_PROGRAMMED (0<<23) 3176 #define PF_FILTER_MED_3x3 (1<<23) 3177 #define PF_FILTER_EDGE_ENHANCE (2<<23) 3178 #define PF_FILTER_EDGE_SOFTEN (3<<23) 3179 #define _PFA_WIN_SZ 0x68074 3180 #define _PFB_WIN_SZ 0x68874 3181 #define _PFA_WIN_POS 0x68070 3182 #define _PFB_WIN_POS 0x68870 3183 #define _PFA_VSCALE 0x68084 3184 #define _PFB_VSCALE 0x68884 3185 #define _PFA_HSCALE 0x68090 3186 #define _PFB_HSCALE 0x68890 3187 3188 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 3189 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 3190 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 3191 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 3192 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 3193 3194 /* legacy palette */ 3195 #define _LGC_PALETTE_A 0x4a000 3196 #define _LGC_PALETTE_B 0x4a800 3197 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 3198 3199 /* interrupts */ 3200 #define DE_MASTER_IRQ_CONTROL (1 << 31) 3201 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3202 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3203 #define DE_PLANEB_FLIP_DONE (1 << 27) 3204 #define DE_PLANEA_FLIP_DONE (1 << 26) 3205 #define DE_PCU_EVENT (1 << 25) 3206 #define DE_GTT_FAULT (1 << 24) 3207 #define DE_POISON (1 << 23) 3208 #define DE_PERFORM_COUNTER (1 << 22) 3209 #define DE_PCH_EVENT (1 << 21) 3210 #define DE_AUX_CHANNEL_A (1 << 20) 3211 #define DE_DP_A_HOTPLUG (1 << 19) 3212 #define DE_GSE (1 << 18) 3213 #define DE_PIPEB_VBLANK (1 << 15) 3214 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3215 #define DE_PIPEB_ODD_FIELD (1 << 13) 3216 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3217 #define DE_PIPEB_VSYNC (1 << 11) 3218 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3219 #define DE_PIPEA_VBLANK (1 << 7) 3220 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3221 #define DE_PIPEA_ODD_FIELD (1 << 5) 3222 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3223 #define DE_PIPEA_VSYNC (1 << 3) 3224 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3225 3226 /* More Ivybridge lolz */ 3227 #define DE_ERR_DEBUG_IVB (1<<30) 3228 #define DE_GSE_IVB (1<<29) 3229 #define DE_PCH_EVENT_IVB (1<<28) 3230 #define DE_DP_A_HOTPLUG_IVB (1<<27) 3231 #define DE_AUX_CHANNEL_A_IVB (1<<26) 3232 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 3233 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 3234 #define DE_PIPEC_VBLANK_IVB (1<<10) 3235 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 3236 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 3237 #define DE_PIPEB_VBLANK_IVB (1<<5) 3238 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 3239 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 3240 #define DE_PIPEA_VBLANK_IVB (1<<0) 3241 3242 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 3243 #define MASTER_INTERRUPT_ENABLE (1<<31) 3244 3245 #define DEISR 0x44000 3246 #define DEIMR 0x44004 3247 #define DEIIR 0x44008 3248 #define DEIER 0x4400c 3249 3250 /* GT interrupt. 3251 * Note that for gen6+ the ring-specific interrupt bits do alias with the 3252 * corresponding bits in the per-ring interrupt control registers. */ 3253 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 3254 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) 3255 #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) 3256 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) 3257 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 3258 #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ 3259 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) 3260 #define GT_PIPE_NOTIFY (1 << 4) 3261 #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) 3262 #define GT_SYNC_STATUS (1 << 2) 3263 #define GT_USER_INTERRUPT (1 << 0) 3264 3265 #define GTISR 0x44010 3266 #define GTIMR 0x44014 3267 #define GTIIR 0x44018 3268 #define GTIER 0x4401c 3269 3270 #define ILK_DISPLAY_CHICKEN2 0x42004 3271 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3272 #define ILK_ELPIN_409_SELECT (1 << 25) 3273 #define ILK_DPARB_GATE (1<<22) 3274 #define ILK_VSDPFD_FULL (1<<21) 3275 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 3276 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 3277 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 3278 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 3279 #define ILK_HDCP_DISABLE (1<<25) 3280 #define ILK_eDP_A_DISABLE (1<<24) 3281 #define ILK_DESKTOP (1<<23) 3282 #define ILK_DSPCLK_GATE 0x42020 3283 #define IVB_VRHUNIT_CLK_GATE (1<<28) 3284 #define ILK_DPARB_CLK_GATE (1<<5) 3285 #define ILK_DPFD_CLK_GATE (1<<7) 3286 3287 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 3288 #define ILK_CLK_FBC (1<<7) 3289 #define ILK_DPFC_DIS1 (1<<8) 3290 #define ILK_DPFC_DIS2 (1<<9) 3291 3292 #define IVB_CHICKEN3 0x4200c 3293 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 3294 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 3295 3296 #define DISP_ARB_CTL 0x45000 3297 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 3298 #define DISP_FBC_WM_DIS (1<<15) 3299 3300 /* GEN7 chicken */ 3301 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 3302 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 3303 3304 #define GEN7_L3CNTLREG1 0xB01C 3305 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C 3306 3307 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 3308 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 3309 3310 /* WaCatErrorRejectionIssue */ 3311 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3312 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3313 3314 /* PCH */ 3315 3316 /* south display engine interrupt */ 3317 #define SDE_AUDIO_POWER_D (1 << 27) 3318 #define SDE_AUDIO_POWER_C (1 << 26) 3319 #define SDE_AUDIO_POWER_B (1 << 25) 3320 #define SDE_AUDIO_POWER_SHIFT (25) 3321 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3322 #define SDE_GMBUS (1 << 24) 3323 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3324 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3325 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3326 #define SDE_AUDIO_TRANSB (1 << 21) 3327 #define SDE_AUDIO_TRANSA (1 << 20) 3328 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3329 #define SDE_POISON (1 << 19) 3330 /* 18 reserved */ 3331 #define SDE_FDI_RXB (1 << 17) 3332 #define SDE_FDI_RXA (1 << 16) 3333 #define SDE_FDI_MASK (3 << 16) 3334 #define SDE_AUXD (1 << 15) 3335 #define SDE_AUXC (1 << 14) 3336 #define SDE_AUXB (1 << 13) 3337 #define SDE_AUX_MASK (7 << 13) 3338 /* 12 reserved */ 3339 #define SDE_CRT_HOTPLUG (1 << 11) 3340 #define SDE_PORTD_HOTPLUG (1 << 10) 3341 #define SDE_PORTC_HOTPLUG (1 << 9) 3342 #define SDE_PORTB_HOTPLUG (1 << 8) 3343 #define SDE_SDVOB_HOTPLUG (1 << 6) 3344 #define SDE_HOTPLUG_MASK (0xf << 8) 3345 #define SDE_TRANSB_CRC_DONE (1 << 5) 3346 #define SDE_TRANSB_CRC_ERR (1 << 4) 3347 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3348 #define SDE_TRANSA_CRC_DONE (1 << 2) 3349 #define SDE_TRANSA_CRC_ERR (1 << 1) 3350 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3351 #define SDE_TRANS_MASK (0x3f) 3352 /* CPT */ 3353 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3354 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3355 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3356 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3357 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3358 SDE_PORTD_HOTPLUG_CPT | \ 3359 SDE_PORTC_HOTPLUG_CPT | \ 3360 SDE_PORTB_HOTPLUG_CPT) 3361 3362 #define SDEISR 0xc4000 3363 #define SDEIMR 0xc4004 3364 #define SDEIIR 0xc4008 3365 #define SDEIER 0xc400c 3366 3367 /* digital port hotplug */ 3368 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 3369 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3370 #define PORTD_PULSE_DURATION_2ms (0) 3371 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 3372 #define PORTD_PULSE_DURATION_6ms (2 << 18) 3373 #define PORTD_PULSE_DURATION_100ms (3 << 18) 3374 #define PORTD_PULSE_DURATION_MASK (3 << 18) 3375 #define PORTD_HOTPLUG_NO_DETECT (0) 3376 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3377 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 3378 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3379 #define PORTC_PULSE_DURATION_2ms (0) 3380 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 3381 #define PORTC_PULSE_DURATION_6ms (2 << 10) 3382 #define PORTC_PULSE_DURATION_100ms (3 << 10) 3383 #define PORTC_PULSE_DURATION_MASK (3 << 10) 3384 #define PORTC_HOTPLUG_NO_DETECT (0) 3385 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3386 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 3387 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3388 #define PORTB_PULSE_DURATION_2ms (0) 3389 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 3390 #define PORTB_PULSE_DURATION_6ms (2 << 2) 3391 #define PORTB_PULSE_DURATION_100ms (3 << 2) 3392 #define PORTB_PULSE_DURATION_MASK (3 << 2) 3393 #define PORTB_HOTPLUG_NO_DETECT (0) 3394 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3395 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 3396 3397 #define PCH_GPIOA 0xc5010 3398 #define PCH_GPIOB 0xc5014 3399 #define PCH_GPIOC 0xc5018 3400 #define PCH_GPIOD 0xc501c 3401 #define PCH_GPIOE 0xc5020 3402 #define PCH_GPIOF 0xc5024 3403 3404 #define PCH_GMBUS0 0xc5100 3405 #define PCH_GMBUS1 0xc5104 3406 #define PCH_GMBUS2 0xc5108 3407 #define PCH_GMBUS3 0xc510c 3408 #define PCH_GMBUS4 0xc5110 3409 #define PCH_GMBUS5 0xc5120 3410 3411 #define _PCH_DPLL_A 0xc6014 3412 #define _PCH_DPLL_B 0xc6018 3413 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3414 3415 #define _PCH_FPA0 0xc6040 3416 #define FP_CB_TUNE (0x3<<22) 3417 #define _PCH_FPA1 0xc6044 3418 #define _PCH_FPB0 0xc6048 3419 #define _PCH_FPB1 0xc604c 3420 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 3421 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 3422 3423 #define PCH_DPLL_TEST 0xc606c 3424 3425 #define PCH_DREF_CONTROL 0xC6200 3426 #define DREF_CONTROL_MASK 0x7fc3 3427 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 3428 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 3429 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 3430 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 3431 #define DREF_SSC_SOURCE_DISABLE (0<<11) 3432 #define DREF_SSC_SOURCE_ENABLE (2<<11) 3433 #define DREF_SSC_SOURCE_MASK (3<<11) 3434 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 3435 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 3436 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 3437 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 3438 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 3439 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 3440 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 3441 #define DREF_SSC4_DOWNSPREAD (0<<6) 3442 #define DREF_SSC4_CENTERSPREAD (1<<6) 3443 #define DREF_SSC1_DISABLE (0<<1) 3444 #define DREF_SSC1_ENABLE (1<<1) 3445 #define DREF_SSC4_DISABLE (0) 3446 #define DREF_SSC4_ENABLE (1) 3447 3448 #define PCH_RAWCLK_FREQ 0xc6204 3449 #define FDL_TP1_TIMER_SHIFT 12 3450 #define FDL_TP1_TIMER_MASK (3<<12) 3451 #define FDL_TP2_TIMER_SHIFT 10 3452 #define FDL_TP2_TIMER_MASK (3<<10) 3453 #define RAWCLK_FREQ_MASK 0x3ff 3454 3455 #define PCH_DPLL_TMR_CFG 0xc6208 3456 3457 #define PCH_SSC4_PARMS 0xc6210 3458 #define PCH_SSC4_AUX_PARMS 0xc6214 3459 3460 #define PCH_DPLL_SEL 0xc7000 3461 #define TRANSA_DPLL_ENABLE (1<<3) 3462 #define TRANSA_DPLLB_SEL (1<<0) 3463 #define TRANSA_DPLLA_SEL 0 3464 #define TRANSB_DPLL_ENABLE (1<<7) 3465 #define TRANSB_DPLLB_SEL (1<<4) 3466 #define TRANSB_DPLLA_SEL (0) 3467 #define TRANSC_DPLL_ENABLE (1<<11) 3468 #define TRANSC_DPLLB_SEL (1<<8) 3469 #define TRANSC_DPLLA_SEL (0) 3470 3471 /* transcoder */ 3472 3473 #define _TRANS_HTOTAL_A 0xe0000 3474 #define TRANS_HTOTAL_SHIFT 16 3475 #define TRANS_HACTIVE_SHIFT 0 3476 #define _TRANS_HBLANK_A 0xe0004 3477 #define TRANS_HBLANK_END_SHIFT 16 3478 #define TRANS_HBLANK_START_SHIFT 0 3479 #define _TRANS_HSYNC_A 0xe0008 3480 #define TRANS_HSYNC_END_SHIFT 16 3481 #define TRANS_HSYNC_START_SHIFT 0 3482 #define _TRANS_VTOTAL_A 0xe000c 3483 #define TRANS_VTOTAL_SHIFT 16 3484 #define TRANS_VACTIVE_SHIFT 0 3485 #define _TRANS_VBLANK_A 0xe0010 3486 #define TRANS_VBLANK_END_SHIFT 16 3487 #define TRANS_VBLANK_START_SHIFT 0 3488 #define _TRANS_VSYNC_A 0xe0014 3489 #define TRANS_VSYNC_END_SHIFT 16 3490 #define TRANS_VSYNC_START_SHIFT 0 3491 #define _TRANS_VSYNCSHIFT_A 0xe0028 3492 3493 #define _TRANSA_DATA_M1 0xe0030 3494 #define _TRANSA_DATA_N1 0xe0034 3495 #define _TRANSA_DATA_M2 0xe0038 3496 #define _TRANSA_DATA_N2 0xe003c 3497 #define _TRANSA_DP_LINK_M1 0xe0040 3498 #define _TRANSA_DP_LINK_N1 0xe0044 3499 #define _TRANSA_DP_LINK_M2 0xe0048 3500 #define _TRANSA_DP_LINK_N2 0xe004c 3501 3502 /* Per-transcoder DIP controls */ 3503 3504 #define _VIDEO_DIP_CTL_A 0xe0200 3505 #define _VIDEO_DIP_DATA_A 0xe0208 3506 #define _VIDEO_DIP_GCP_A 0xe0210 3507 3508 #define _VIDEO_DIP_CTL_B 0xe1200 3509 #define _VIDEO_DIP_DATA_B 0xe1208 3510 #define _VIDEO_DIP_GCP_B 0xe1210 3511 3512 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3513 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3514 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3515 3516 #define VLV_VIDEO_DIP_CTL_A 0x60220 3517 #define VLV_VIDEO_DIP_DATA_A 0x60208 3518 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 3519 3520 #define VLV_VIDEO_DIP_CTL_B 0x61170 3521 #define VLV_VIDEO_DIP_DATA_B 0x61174 3522 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 3523 3524 #define VLV_TVIDEO_DIP_CTL(pipe) \ 3525 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) 3526 #define VLV_TVIDEO_DIP_DATA(pipe) \ 3527 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) 3528 #define VLV_TVIDEO_DIP_GCP(pipe) \ 3529 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) 3530 3531 /* Haswell DIP controls */ 3532 #define HSW_VIDEO_DIP_CTL_A 0x60200 3533 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 3534 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 3535 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 3536 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 3537 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 3538 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 3539 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 3540 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 3541 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 3542 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 3543 #define HSW_VIDEO_DIP_GCP_A 0x60210 3544 3545 #define HSW_VIDEO_DIP_CTL_B 0x61200 3546 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 3547 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 3548 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 3549 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 3550 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 3551 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 3552 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 3553 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 3554 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 3555 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 3556 #define HSW_VIDEO_DIP_GCP_B 0x61210 3557 3558 #define HSW_TVIDEO_DIP_CTL(pipe) \ 3559 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) 3560 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ 3561 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) 3562 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \ 3563 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) 3564 #define HSW_TVIDEO_DIP_GCP(pipe) \ 3565 _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) 3566 3567 #define _TRANS_HTOTAL_B 0xe1000 3568 #define _TRANS_HBLANK_B 0xe1004 3569 #define _TRANS_HSYNC_B 0xe1008 3570 #define _TRANS_VTOTAL_B 0xe100c 3571 #define _TRANS_VBLANK_B 0xe1010 3572 #define _TRANS_VSYNC_B 0xe1014 3573 #define _TRANS_VSYNCSHIFT_B 0xe1028 3574 3575 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) 3576 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) 3577 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) 3578 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) 3579 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) 3580 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) 3581 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ 3582 _TRANS_VSYNCSHIFT_B) 3583 3584 #define _TRANSB_DATA_M1 0xe1030 3585 #define _TRANSB_DATA_N1 0xe1034 3586 #define _TRANSB_DATA_M2 0xe1038 3587 #define _TRANSB_DATA_N2 0xe103c 3588 #define _TRANSB_DP_LINK_M1 0xe1040 3589 #define _TRANSB_DP_LINK_N1 0xe1044 3590 #define _TRANSB_DP_LINK_M2 0xe1048 3591 #define _TRANSB_DP_LINK_N2 0xe104c 3592 3593 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) 3594 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) 3595 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) 3596 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) 3597 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) 3598 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) 3599 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) 3600 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) 3601 3602 #define _TRANSACONF 0xf0008 3603 #define _TRANSBCONF 0xf1008 3604 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) 3605 #define TRANS_DISABLE (0<<31) 3606 #define TRANS_ENABLE (1<<31) 3607 #define TRANS_STATE_MASK (1<<30) 3608 #define TRANS_STATE_DISABLE (0<<30) 3609 #define TRANS_STATE_ENABLE (1<<30) 3610 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 3611 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 3612 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 3613 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 3614 #define TRANS_DP_AUDIO_ONLY (1<<26) 3615 #define TRANS_DP_VIDEO_AUDIO (0<<26) 3616 #define TRANS_INTERLACE_MASK (7<<21) 3617 #define TRANS_PROGRESSIVE (0<<21) 3618 #define TRANS_INTERLACED (3<<21) 3619 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 3620 #define TRANS_8BPC (0<<5) 3621 #define TRANS_10BPC (1<<5) 3622 #define TRANS_6BPC (2<<5) 3623 #define TRANS_12BPC (3<<5) 3624 3625 #define _TRANSA_CHICKEN2 0xf0064 3626 #define _TRANSB_CHICKEN2 0xf1064 3627 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3628 #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) 3629 3630 #define SOUTH_CHICKEN1 0xc2000 3631 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3632 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3633 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3634 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3635 #define SOUTH_CHICKEN2 0xc2004 3636 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 3637 3638 #define _FDI_RXA_CHICKEN 0xc200c 3639 #define _FDI_RXB_CHICKEN 0xc2010 3640 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3641 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 3642 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 3643 3644 #define SOUTH_DSPCLK_GATE_D 0xc2020 3645 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3646 3647 /* CPU: FDI_TX */ 3648 #define _FDI_TXA_CTL 0x60100 3649 #define _FDI_TXB_CTL 0x61100 3650 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 3651 #define FDI_TX_DISABLE (0<<31) 3652 #define FDI_TX_ENABLE (1<<31) 3653 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3654 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3655 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3656 #define FDI_LINK_TRAIN_NONE (3<<28) 3657 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3658 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3659 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3660 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3661 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3662 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3663 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3664 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3665 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3666 SNB has different settings. */ 3667 /* SNB A-stepping */ 3668 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3669 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3670 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3671 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3672 /* SNB B-stepping */ 3673 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3674 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3675 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3676 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3677 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3678 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3679 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3680 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3681 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3682 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3683 /* Ironlake: hardwired to 1 */ 3684 #define FDI_TX_PLL_ENABLE (1<<14) 3685 3686 /* Ivybridge has different bits for lolz */ 3687 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 3688 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 3689 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 3690 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 3691 3692 /* both Tx and Rx */ 3693 #define FDI_COMPOSITE_SYNC (1<<11) 3694 #define FDI_LINK_TRAIN_AUTO (1<<10) 3695 #define FDI_SCRAMBLING_ENABLE (0<<7) 3696 #define FDI_SCRAMBLING_DISABLE (1<<7) 3697 3698 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3699 #define _FDI_RXA_CTL 0xf000c 3700 #define _FDI_RXB_CTL 0xf100c 3701 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 3702 #define FDI_RX_ENABLE (1<<31) 3703 /* train, dp width same as FDI_TX */ 3704 #define FDI_FS_ERRC_ENABLE (1<<27) 3705 #define FDI_FE_ERRC_ENABLE (1<<26) 3706 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3707 #define FDI_8BPC (0<<16) 3708 #define FDI_10BPC (1<<16) 3709 #define FDI_6BPC (2<<16) 3710 #define FDI_12BPC (3<<16) 3711 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3712 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3713 #define FDI_RX_PLL_ENABLE (1<<13) 3714 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3715 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3716 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3717 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3718 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3719 #define FDI_PCDCLK (1<<4) 3720 /* CPT */ 3721 #define FDI_AUTO_TRAINING (1<<10) 3722 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3723 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3724 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3725 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3726 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3727 /* LPT */ 3728 #define FDI_PORT_WIDTH_2X_LPT (1<<19) 3729 #define FDI_PORT_WIDTH_1X_LPT (0<<19) 3730 3731 #define _FDI_RXA_MISC 0xf0010 3732 #define _FDI_RXB_MISC 0xf1010 3733 #define _FDI_RXA_TUSIZE1 0xf0030 3734 #define _FDI_RXA_TUSIZE2 0xf0038 3735 #define _FDI_RXB_TUSIZE1 0xf1030 3736 #define _FDI_RXB_TUSIZE2 0xf1038 3737 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 3738 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 3739 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 3740 3741 /* FDI_RX interrupt register format */ 3742 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3743 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3744 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3745 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3746 #define FDI_RX_FS_CODE_ERR (1<<6) 3747 #define FDI_RX_FE_CODE_ERR (1<<5) 3748 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3749 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3750 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3751 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3752 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3753 3754 #define _FDI_RXA_IIR 0xf0014 3755 #define _FDI_RXA_IMR 0xf0018 3756 #define _FDI_RXB_IIR 0xf1014 3757 #define _FDI_RXB_IMR 0xf1018 3758 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 3759 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 3760 3761 #define FDI_PLL_CTL_1 0xfe000 3762 #define FDI_PLL_CTL_2 0xfe004 3763 3764 /* CRT */ 3765 #define PCH_ADPA 0xe1100 3766 #define ADPA_TRANS_SELECT_MASK (1<<30) 3767 #define ADPA_TRANS_A_SELECT 0 3768 #define ADPA_TRANS_B_SELECT (1<<30) 3769 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3770 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3771 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3772 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3773 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3774 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3775 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3776 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3777 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3778 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3779 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3780 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3781 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3782 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3783 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3784 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3785 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3786 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3787 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3788 3789 /* or SDVOB */ 3790 #define VLV_HDMIB 0x61140 3791 #define HDMIB 0xe1140 3792 #define PORT_ENABLE (1 << 31) 3793 #define TRANSCODER(pipe) ((pipe) << 30) 3794 #define TRANSCODER_CPT(pipe) ((pipe) << 29) 3795 #define TRANSCODER_MASK (1 << 30) 3796 #define TRANSCODER_MASK_CPT (3 << 29) 3797 #define COLOR_FORMAT_8bpc (0) 3798 #define COLOR_FORMAT_12bpc (3 << 26) 3799 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3800 #define SDVO_ENCODING (0) 3801 #define TMDS_ENCODING (2 << 10) 3802 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3803 /* CPT */ 3804 #define HDMI_MODE_SELECT (1 << 9) 3805 #define DVI_MODE_SELECT (0) 3806 #define SDVOB_BORDER_ENABLE (1 << 7) 3807 #define AUDIO_ENABLE (1 << 6) 3808 #define VSYNC_ACTIVE_HIGH (1 << 4) 3809 #define HSYNC_ACTIVE_HIGH (1 << 3) 3810 #define PORT_DETECTED (1 << 2) 3811 3812 /* PCH SDVOB multiplex with HDMIB */ 3813 #define PCH_SDVOB HDMIB 3814 3815 #define HDMIC 0xe1150 3816 #define HDMID 0xe1160 3817 3818 #define PCH_LVDS 0xe1180 3819 #define LVDS_DETECTED (1 << 1) 3820 3821 #define BLC_PWM_CPU_CTL2 0x48250 3822 #define PWM_ENABLE (1 << 31) 3823 #define PWM_PIPE_A (0 << 29) 3824 #define PWM_PIPE_B (1 << 29) 3825 #define BLC_PWM_CPU_CTL 0x48254 3826 3827 #define BLC_PWM_PCH_CTL1 0xc8250 3828 #define PWM_PCH_ENABLE (1 << 31) 3829 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3830 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3831 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3832 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3833 3834 #define BLC_PWM_PCH_CTL2 0xc8254 3835 3836 #define PCH_PP_STATUS 0xc7200 3837 #define PCH_PP_CONTROL 0xc7204 3838 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3839 #define PANEL_UNLOCK_MASK (0xffff << 16) 3840 #define EDP_FORCE_VDD (1 << 3) 3841 #define EDP_BLC_ENABLE (1 << 2) 3842 #define PANEL_POWER_RESET (1 << 1) 3843 #define PANEL_POWER_OFF (0 << 0) 3844 #define PANEL_POWER_ON (1 << 0) 3845 #define PCH_PP_ON_DELAYS 0xc7208 3846 #define PANEL_PORT_SELECT_MASK (3 << 30) 3847 #define PANEL_PORT_SELECT_LVDS (0 << 30) 3848 #define PANEL_PORT_SELECT_DPA (1 << 30) 3849 #define EDP_PANEL (1 << 30) 3850 #define PANEL_PORT_SELECT_DPC (2 << 30) 3851 #define PANEL_PORT_SELECT_DPD (3 << 30) 3852 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 3853 #define PANEL_POWER_UP_DELAY_SHIFT 16 3854 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 3855 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 3856 3857 #define PCH_PP_OFF_DELAYS 0xc720c 3858 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 3859 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 3860 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 3861 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 3862 3863 #define PCH_PP_DIVISOR 0xc7210 3864 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 3865 #define PP_REFERENCE_DIVIDER_SHIFT 8 3866 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 3867 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 3868 3869 #define PCH_DP_B 0xe4100 3870 #define PCH_DPB_AUX_CH_CTL 0xe4110 3871 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3872 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3873 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3874 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3875 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3876 3877 #define PCH_DP_C 0xe4200 3878 #define PCH_DPC_AUX_CH_CTL 0xe4210 3879 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3880 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3881 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3882 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3883 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3884 3885 #define PCH_DP_D 0xe4300 3886 #define PCH_DPD_AUX_CH_CTL 0xe4310 3887 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3888 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3889 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3890 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3891 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3892 3893 /* CPT */ 3894 #define PORT_TRANS_A_SEL_CPT 0 3895 #define PORT_TRANS_B_SEL_CPT (1<<29) 3896 #define PORT_TRANS_C_SEL_CPT (2<<29) 3897 #define PORT_TRANS_SEL_MASK (3<<29) 3898 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 3899 3900 #define TRANS_DP_CTL_A 0xe0300 3901 #define TRANS_DP_CTL_B 0xe1300 3902 #define TRANS_DP_CTL_C 0xe2300 3903 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) 3904 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3905 #define TRANS_DP_PORT_SEL_B (0<<29) 3906 #define TRANS_DP_PORT_SEL_C (1<<29) 3907 #define TRANS_DP_PORT_SEL_D (2<<29) 3908 #define TRANS_DP_PORT_SEL_NONE (3<<29) 3909 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3910 #define TRANS_DP_AUDIO_ONLY (1<<26) 3911 #define TRANS_DP_ENH_FRAMING (1<<18) 3912 #define TRANS_DP_8BPC (0<<9) 3913 #define TRANS_DP_10BPC (1<<9) 3914 #define TRANS_DP_6BPC (2<<9) 3915 #define TRANS_DP_12BPC (3<<9) 3916 #define TRANS_DP_BPC_MASK (3<<9) 3917 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3918 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3919 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3920 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3921 #define TRANS_DP_SYNC_MASK (3<<3) 3922 3923 /* SNB eDP training params */ 3924 /* SNB A-stepping */ 3925 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3926 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3927 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3928 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3929 /* SNB B-stepping */ 3930 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3931 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3932 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3933 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3934 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3935 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3936 3937 /* IVB */ 3938 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 3939 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 3940 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 3941 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 3942 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 3943 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 3944 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) 3945 3946 /* legacy values */ 3947 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 3948 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 3949 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 3950 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 3951 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 3952 3953 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 3954 3955 #define FORCEWAKE 0xA18C 3956 #define FORCEWAKE_VLV 0x1300b0 3957 #define FORCEWAKE_ACK_VLV 0x1300b4 3958 #define FORCEWAKE_ACK 0x130090 3959 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 3960 #define FORCEWAKE_MT_ACK 0x130040 3961 #define ECOBUS 0xa180 3962 #define FORCEWAKE_MT_ENABLE (1<<5) 3963 3964 #define GTFIFODBG 0x120000 3965 #define GT_FIFO_CPU_ERROR_MASK 7 3966 #define GT_FIFO_OVFERR (1<<2) 3967 #define GT_FIFO_IAWRERR (1<<1) 3968 #define GT_FIFO_IARDERR (1<<0) 3969 3970 #define GT_FIFO_FREE_ENTRIES 0x120008 3971 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 3972 3973 #define GEN6_UCGCTL1 0x9400 3974 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 3975 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 3976 3977 #define GEN6_UCGCTL2 0x9404 3978 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 3979 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 3980 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 3981 3982 #define GEN6_RPNSWREQ 0xA008 3983 #define GEN6_TURBO_DISABLE (1<<31) 3984 #define GEN6_FREQUENCY(x) ((x)<<25) 3985 #define GEN6_OFFSET(x) ((x)<<19) 3986 #define GEN6_AGGRESSIVE_TURBO (0<<15) 3987 #define GEN6_RC_VIDEO_FREQ 0xA00C 3988 #define GEN6_RC_CONTROL 0xA090 3989 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 3990 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 3991 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 3992 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 3993 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 3994 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 3995 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 3996 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3997 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3998 #define GEN6_RPSTAT1 0xA01C 3999 #define GEN6_CAGF_SHIFT 8 4000 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 4001 #define GEN6_RP_CONTROL 0xA024 4002 #define GEN6_RP_MEDIA_TURBO (1<<11) 4003 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 4004 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 4005 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 4006 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 4007 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 4008 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 4009 #define GEN6_RP_ENABLE (1<<7) 4010 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 4011 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 4012 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 4013 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 4014 #define GEN6_RP_UP_THRESHOLD 0xA02C 4015 #define GEN6_RP_DOWN_THRESHOLD 0xA030 4016 #define GEN6_RP_CUR_UP_EI 0xA050 4017 #define GEN6_CURICONT_MASK 0xffffff 4018 #define GEN6_RP_CUR_UP 0xA054 4019 #define GEN6_CURBSYTAVG_MASK 0xffffff 4020 #define GEN6_RP_PREV_UP 0xA058 4021 #define GEN6_RP_CUR_DOWN_EI 0xA05C 4022 #define GEN6_CURIAVG_MASK 0xffffff 4023 #define GEN6_RP_CUR_DOWN 0xA060 4024 #define GEN6_RP_PREV_DOWN 0xA064 4025 #define GEN6_RP_UP_EI 0xA068 4026 #define GEN6_RP_DOWN_EI 0xA06C 4027 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 4028 #define GEN6_RC_STATE 0xA094 4029 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 4030 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 4031 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 4032 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 4033 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 4034 #define GEN6_RC_SLEEP 0xA0B0 4035 #define GEN6_RC1e_THRESHOLD 0xA0B4 4036 #define GEN6_RC6_THRESHOLD 0xA0B8 4037 #define GEN6_RC6p_THRESHOLD 0xA0BC 4038 #define GEN6_RC6pp_THRESHOLD 0xA0C0 4039 #define GEN6_PMINTRMSK 0xA168 4040 4041 #define GEN6_PMISR 0x44020 4042 #define GEN6_PMIMR 0x44024 /* rps_lock */ 4043 #define GEN6_PMIIR 0x44028 4044 #define GEN6_PMIER 0x4402C 4045 #define GEN6_PM_MBOX_EVENT (1<<25) 4046 #define GEN6_PM_THERMAL_EVENT (1<<24) 4047 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 4048 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 4049 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 4050 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 4051 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 4052 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 4053 GEN6_PM_RP_DOWN_THRESHOLD | \ 4054 GEN6_PM_RP_DOWN_TIMEOUT) 4055 4056 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 4057 #define GEN6_GT_GFX_RC6 0x138108 4058 #define GEN6_GT_GFX_RC6p 0x13810C 4059 #define GEN6_GT_GFX_RC6pp 0x138110 4060 4061 #define GEN6_PCODE_MAILBOX 0x138124 4062 #define GEN6_PCODE_READY (1<<31) 4063 #define GEN6_READ_OC_PARAMS 0xc 4064 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 4065 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 4066 #define GEN6_PCODE_DATA 0x138128 4067 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 4068 4069 #define GEN6_GT_CORE_STATUS 0x138060 4070 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 4071 #define GEN6_RCn_MASK 7 4072 #define GEN6_RC0 0 4073 #define GEN6_RC3 2 4074 #define GEN6_RC6 3 4075 #define GEN6_RC7 4 4076 4077 #define G4X_AUD_VID_DID 0x62020 4078 #define INTEL_AUDIO_DEVCL 0x808629FB 4079 #define INTEL_AUDIO_DEVBLC 0x80862801 4080 #define INTEL_AUDIO_DEVCTG 0x80862802 4081 4082 #define G4X_AUD_CNTL_ST 0x620B4 4083 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 4084 #define G4X_ELDV_DEVCTG (1 << 14) 4085 #define G4X_ELD_ADDR (0xf << 5) 4086 #define G4X_ELD_ACK (1 << 4) 4087 #define G4X_HDMIW_HDMIEDID 0x6210C 4088 4089 #define IBX_HDMIW_HDMIEDID_A 0xE2050 4090 #define IBX_AUD_CNTL_ST_A 0xE20B4 4091 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 4092 #define IBX_ELD_ADDRESS (0x1f << 5) 4093 #define IBX_ELD_ACK (1 << 4) 4094 #define IBX_AUD_CNTL_ST2 0xE20C0 4095 #define IBX_ELD_VALIDB (1 << 0) 4096 #define IBX_CP_READYB (1 << 1) 4097 4098 #define CPT_HDMIW_HDMIEDID_A 0xE5050 4099 #define CPT_AUD_CNTL_ST_A 0xE50B4 4100 #define CPT_AUD_CNTRL_ST2 0xE50C0 4101 4102 /* These are the 4 32-bit write offset registers for each stream 4103 * output buffer. It determines the offset from the 4104 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 4105 */ 4106 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 4107 4108 #define IBX_AUD_CONFIG_A 0xe2000 4109 #define CPT_AUD_CONFIG_A 0xe5000 4110 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 4111 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 4112 #define AUD_CONFIG_UPPER_N_SHIFT 20 4113 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 4114 #define AUD_CONFIG_LOWER_N_SHIFT 4 4115 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 4116 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 4117 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) 4118 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 4119 4120 /* HSW Power Wells */ 4121 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ 4122 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ 4123 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ 4124 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ 4125 #define HSW_PWR_WELL_ENABLE (1<<31) 4126 #define HSW_PWR_WELL_STATE (1<<30) 4127 #define HSW_PWR_WELL_CTL5 0x45410 4128 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 4129 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 4130 #define HSW_PWR_WELL_FORCE_ON (1<<19) 4131 #define HSW_PWR_WELL_CTL6 0x45414 4132 4133 /* Per-pipe DDI Function Control */ 4134 #define PIPE_DDI_FUNC_CTL_A 0x60400 4135 #define PIPE_DDI_FUNC_CTL_B 0x61400 4136 #define PIPE_DDI_FUNC_CTL_C 0x62400 4137 #define PIPE_DDI_FUNC_CTL_EDP 0x6F400 4138 #define DDI_FUNC_CTL(pipe) _PIPE(pipe, \ 4139 PIPE_DDI_FUNC_CTL_A, \ 4140 PIPE_DDI_FUNC_CTL_B) 4141 #define PIPE_DDI_FUNC_ENABLE (1<<31) 4142 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 4143 #define PIPE_DDI_PORT_MASK (0xf<<28) 4144 #define PIPE_DDI_SELECT_PORT(x) ((x)<<28) 4145 #define PIPE_DDI_MODE_SELECT_HDMI (0<<24) 4146 #define PIPE_DDI_MODE_SELECT_DVI (1<<24) 4147 #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) 4148 #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) 4149 #define PIPE_DDI_MODE_SELECT_FDI (4<<24) 4150 #define PIPE_DDI_BPC_8 (0<<20) 4151 #define PIPE_DDI_BPC_10 (1<<20) 4152 #define PIPE_DDI_BPC_6 (2<<20) 4153 #define PIPE_DDI_BPC_12 (3<<20) 4154 #define PIPE_DDI_BFI_ENABLE (1<<4) 4155 #define PIPE_DDI_PORT_WIDTH_X1 (0<<1) 4156 #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) 4157 #define PIPE_DDI_PORT_WIDTH_X4 (3<<1) 4158 4159 /* DisplayPort Transport Control */ 4160 #define DP_TP_CTL_A 0x64040 4161 #define DP_TP_CTL_B 0x64140 4162 #define DP_TP_CTL(port) _PORT(port, \ 4163 DP_TP_CTL_A, \ 4164 DP_TP_CTL_B) 4165 #define DP_TP_CTL_ENABLE (1<<31) 4166 #define DP_TP_CTL_MODE_SST (0<<27) 4167 #define DP_TP_CTL_MODE_MST (1<<27) 4168 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 4169 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 4170 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 4171 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 4172 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 4173 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 4174 4175 /* DisplayPort Transport Status */ 4176 #define DP_TP_STATUS_A 0x64044 4177 #define DP_TP_STATUS_B 0x64144 4178 #define DP_TP_STATUS(port) _PORT(port, \ 4179 DP_TP_STATUS_A, \ 4180 DP_TP_STATUS_B) 4181 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 4182 4183 /* DDI Buffer Control */ 4184 #define DDI_BUF_CTL_A 0x64000 4185 #define DDI_BUF_CTL_B 0x64100 4186 #define DDI_BUF_CTL(port) _PORT(port, \ 4187 DDI_BUF_CTL_A, \ 4188 DDI_BUF_CTL_B) 4189 #define DDI_BUF_CTL_ENABLE (1<<31) 4190 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 4191 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ 4192 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ 4193 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ 4194 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ 4195 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ 4196 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ 4197 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ 4198 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ 4199 #define DDI_BUF_EMP_MASK (0xf<<24) 4200 #define DDI_BUF_IS_IDLE (1<<7) 4201 #define DDI_PORT_WIDTH_X1 (0<<1) 4202 #define DDI_PORT_WIDTH_X2 (1<<1) 4203 #define DDI_PORT_WIDTH_X4 (3<<1) 4204 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 4205 4206 /* DDI Buffer Translations */ 4207 #define DDI_BUF_TRANS_A 0x64E00 4208 #define DDI_BUF_TRANS_B 0x64E60 4209 #define DDI_BUF_TRANS(port) _PORT(port, \ 4210 DDI_BUF_TRANS_A, \ 4211 DDI_BUF_TRANS_B) 4212 4213 /* Sideband Interface (SBI) is programmed indirectly, via 4214 * SBI_ADDR, which contains the register offset; and SBI_DATA, 4215 * which contains the payload */ 4216 #define SBI_ADDR 0xC6000 4217 #define SBI_DATA 0xC6004 4218 #define SBI_CTL_STAT 0xC6008 4219 #define SBI_CTL_OP_CRRD (0x6<<8) 4220 #define SBI_CTL_OP_CRWR (0x7<<8) 4221 #define SBI_RESPONSE_FAIL (0x1<<1) 4222 #define SBI_RESPONSE_SUCCESS (0x0<<1) 4223 #define SBI_BUSY (0x1<<0) 4224 #define SBI_READY (0x0<<0) 4225 4226 /* SBI offsets */ 4227 #define SBI_SSCDIVINTPHASE6 0x0600 4228 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 4229 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 4230 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 4231 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 4232 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 4233 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 4234 #define SBI_SSCCTL 0x020c 4235 #define SBI_SSCCTL6 0x060C 4236 #define SBI_SSCCTL_DISABLE (1<<0) 4237 #define SBI_SSCAUXDIV6 0x0610 4238 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 4239 #define SBI_DBUFF0 0x2a00 4240 4241 /* LPT PIXCLK_GATE */ 4242 #define PIXCLK_GATE 0xC6020 4243 #define PIXCLK_GATE_UNGATE 1<<0 4244 #define PIXCLK_GATE_GATE 0<<0 4245 4246 /* SPLL */ 4247 #define SPLL_CTL 0x46020 4248 #define SPLL_PLL_ENABLE (1<<31) 4249 #define SPLL_PLL_SCC (1<<28) 4250 #define SPLL_PLL_NON_SCC (2<<28) 4251 #define SPLL_PLL_FREQ_810MHz (0<<26) 4252 #define SPLL_PLL_FREQ_1350MHz (1<<26) 4253 4254 /* WRPLL */ 4255 #define WRPLL_CTL1 0x46040 4256 #define WRPLL_CTL2 0x46060 4257 #define WRPLL_PLL_ENABLE (1<<31) 4258 #define WRPLL_PLL_SELECT_SSC (0x01<<28) 4259 #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) 4260 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) 4261 /* WRPLL divider programming */ 4262 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 4263 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 4264 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 4265 4266 /* Port clock selection */ 4267 #define PORT_CLK_SEL_A 0x46100 4268 #define PORT_CLK_SEL_B 0x46104 4269 #define PORT_CLK_SEL(port) _PORT(port, \ 4270 PORT_CLK_SEL_A, \ 4271 PORT_CLK_SEL_B) 4272 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 4273 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 4274 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 4275 #define PORT_CLK_SEL_SPLL (3<<29) 4276 #define PORT_CLK_SEL_WRPLL1 (4<<29) 4277 #define PORT_CLK_SEL_WRPLL2 (5<<29) 4278 4279 /* Pipe clock selection */ 4280 #define PIPE_CLK_SEL_A 0x46140 4281 #define PIPE_CLK_SEL_B 0x46144 4282 #define PIPE_CLK_SEL(pipe) _PIPE(pipe, \ 4283 PIPE_CLK_SEL_A, \ 4284 PIPE_CLK_SEL_B) 4285 /* For each pipe, we need to select the corresponding port clock */ 4286 #define PIPE_CLK_SEL_DISABLED (0x0<<29) 4287 #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) 4288 4289 /* LCPLL Control */ 4290 #define LCPLL_CTL 0x130040 4291 #define LCPLL_PLL_DISABLE (1<<31) 4292 #define LCPLL_PLL_LOCK (1<<30) 4293 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 4294 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 4295 4296 /* Pipe WM_LINETIME - watermark line time */ 4297 #define PIPE_WM_LINETIME_A 0x45270 4298 #define PIPE_WM_LINETIME_B 0x45274 4299 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \ 4300 PIPE_WM_LINETIME_A, \ 4301 PIPE_WM_LINETIME_A) 4302 #define PIPE_WM_LINETIME_MASK (0x1ff) 4303 #define PIPE_WM_LINETIME_TIME(x) ((x)) 4304 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 4305 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 4306 4307 /* SFUSE_STRAP */ 4308 #define SFUSE_STRAP 0xc2014 4309 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 4310 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 4311 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 4312 4313 #endif /* _I915_REG_H_ */ 4314